2022-06-08 23:46:35 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2007 - 2011 Realtek Corporation. */
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2013-05-08 21:45:39 +00:00
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2022-06-08 23:46:35 +00:00
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#include "../include/drv_types.h"
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2013-05-08 21:45:39 +00:00
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2022-06-08 23:46:35 +00:00
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static void odm_ConfigRFReg_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr,
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u32 Data, u32 RegAddr)
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2013-05-08 21:45:39 +00:00
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{
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2022-06-08 23:46:35 +00:00
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if (Addr == 0xffe) {
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msleep(50);
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2013-08-07 21:24:48 +00:00
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} else if (Addr == 0xfd) {
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2022-06-08 23:46:35 +00:00
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mdelay(5);
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2013-08-07 21:24:48 +00:00
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} else if (Addr == 0xfc) {
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mdelay(1);
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2013-08-07 21:24:48 +00:00
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} else if (Addr == 0xfb) {
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2022-06-08 23:46:35 +00:00
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udelay(50);
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2013-08-07 21:24:48 +00:00
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} else if (Addr == 0xfa) {
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2022-06-08 23:46:35 +00:00
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udelay(5);
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2013-08-07 21:24:48 +00:00
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} else if (Addr == 0xf9) {
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2022-06-08 23:46:35 +00:00
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udelay(1);
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2013-08-07 21:24:48 +00:00
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} else {
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2022-06-08 23:46:35 +00:00
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rtl8188e_PHY_SetRFReg(pDM_Odm->Adapter, RegAddr, bRFRegOffsetMask, Data);
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2013-07-10 18:25:07 +00:00
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/* Add 1us delay between BB/RF register setting. */
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2022-06-08 23:46:35 +00:00
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udelay(1);
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2013-05-19 04:28:07 +00:00
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}
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2013-05-08 21:45:39 +00:00
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}
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2013-08-14 17:03:28 +00:00
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void odm_ConfigRF_RadioA_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Data)
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{
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u32 content = 0x1000; /* RF_Content: radioa_txt */
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u32 maskforPhySet = (u32)(content & 0xE000);
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2013-05-08 21:45:39 +00:00
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2022-06-08 23:46:35 +00:00
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odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, Addr | maskforPhySet);
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2013-05-08 21:45:39 +00:00
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}
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2013-08-14 17:03:28 +00:00
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void odm_ConfigMAC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u8 Data)
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{
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rtw_write8(pDM_Odm->Adapter, Addr, Data);
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2013-05-08 21:45:39 +00:00
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}
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2013-08-14 17:03:28 +00:00
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void odm_ConfigBB_AGC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data)
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{
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rtl8188e_PHY_SetBBReg(pDM_Odm->Adapter, Addr, Bitmask, Data);
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2013-07-10 18:25:07 +00:00
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/* Add 1us delay between BB/RF register setting. */
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udelay(1);
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2013-05-08 21:45:39 +00:00
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}
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2013-08-14 17:03:28 +00:00
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void odm_ConfigBB_PHY_REG_PG_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr,
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u32 Bitmask, u32 Data)
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2013-05-19 04:28:07 +00:00
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{
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2022-06-08 23:46:35 +00:00
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if (Addr == 0xfe)
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msleep(50);
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else if (Addr == 0xfd)
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mdelay(5);
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else if (Addr == 0xfc)
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mdelay(1);
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else if (Addr == 0xfb)
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udelay(50);
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else if (Addr == 0xfa)
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udelay(5);
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else if (Addr == 0xf9)
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udelay(1);
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else
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storePwrIndexDiffRateOffset(pDM_Odm->Adapter, Addr, Bitmask, Data);
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}
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2013-08-14 17:03:28 +00:00
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void odm_ConfigBB_PHY_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data)
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2013-05-19 04:28:07 +00:00
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{
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2013-08-07 21:24:48 +00:00
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if (Addr == 0xfe) {
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2022-06-08 23:46:35 +00:00
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msleep(50);
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2013-08-07 21:24:48 +00:00
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} else if (Addr == 0xfd) {
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2022-06-08 23:46:35 +00:00
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mdelay(5);
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2013-08-07 21:24:48 +00:00
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} else if (Addr == 0xfc) {
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2022-06-08 23:46:35 +00:00
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mdelay(1);
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2013-08-07 21:24:48 +00:00
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} else if (Addr == 0xfb) {
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2022-06-08 23:46:35 +00:00
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udelay(50);
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2013-08-07 21:24:48 +00:00
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} else if (Addr == 0xfa) {
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2022-06-08 23:46:35 +00:00
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udelay(5);
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2013-08-07 21:24:48 +00:00
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} else if (Addr == 0xf9) {
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2022-06-08 23:46:35 +00:00
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udelay(1);
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2013-08-07 21:24:48 +00:00
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} else {
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2013-05-08 21:45:39 +00:00
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if (Addr == 0xa24)
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2013-05-19 04:28:07 +00:00
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pDM_Odm->RFCalibrateInfo.RegA24 = Data;
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2022-06-08 23:46:35 +00:00
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rtl8188e_PHY_SetBBReg(pDM_Odm->Adapter, Addr, Bitmask, Data);
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2013-05-19 04:28:07 +00:00
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2013-07-10 18:25:07 +00:00
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/* Add 1us delay between BB/RF register setting. */
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2022-06-08 23:46:35 +00:00
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udelay(1);
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2013-05-08 21:45:39 +00:00
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}
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}
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