/*2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement.*/
/*We need to remove to other position???*/
structrtl8192cd_priv{
u8temp;
};
struct_dynamic_primary_cca{
u8pri_cca_flag;
u8intf_flag;
u8intf_type;
u8dup_rts_flag;
u8monitor_flag;
u8CH_offset;
u8MF_state;
};
#define dm_type_by_fw 0
#define dm_type_by_driver 1
/*Declare for common info*/
#define IQK_THRESHOLD 8
#define DPK_THRESHOLD 4
struct_odm_phy_status_info_{
/* */
/* Be care, if you want to add any element please insert between */
/* rx_pwdb_all & signal_strength. */
/* */
u8rx_pwdb_all;
u8signal_quality;/* in 0-100 index. */
s8rx_mimo_signal_quality[4];/* per-path's EVM translate to 0~100% */
u8rx_mimo_evm_dbm[4];/* per-path's original EVM (dbm) */
u8rx_mimo_signal_strength[4];/* in 0~100 index */
s16cfo_short[4];/* per-path's cfo_short */
s16cfo_tail[4];/* per-path's cfo_tail */
s8rx_power;/* in dBm Translate from PWdB */
s8recv_signal_power;/* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */
u8bt_rx_rssi_percentage;
u8signal_strength;/* in 0-100 index. */
s8rx_pwr[4];/* per-path's pwdb */
s8rx_snr[4];/* per-path's SNR */
/* s8 BB_Backup[13]; backup reg. */
#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
u8rx_count:2;/* RX path counter---*/
u8band_width:2;
u8rxsc:4;/* sub-channel---*/
#else
u8band_width;
#endif
u8bt_coex_pwr_adjust;
#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
u8channel;/* channel number---*/
boolis_mu_packet;/* is MU packet or not---*/
boolis_beamformed;/* BF packet---*/
#endif
};
struct_odm_per_pkt_info_{
u8data_rate;
u8station_id;
boolis_packet_match_bssid;
boolis_packet_to_self;
boolis_packet_beacon;
boolis_to_self;
u8ppdu_cnt;
};
struct_odm_phy_dbg_info_{
/*ODM Write,debug info*/
s8rx_snr_db[4];
u32num_qry_phy_status;
u32num_qry_phy_status_cck;
u32num_qry_phy_status_ofdm;
#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
u32num_qry_mu_pkt;
u32num_qry_bf_pkt;
u32num_qry_mu_vht_pkt[40];
u32num_qry_vht_pkt[40];
boolis_ldpc_pkt;
boolis_stbc_pkt;
u8num_of_ppdu[4];
u8gid_num[4];
#endif
u8num_qry_beacon_pkt;
/* Others */
s32rx_evm[4];
};
/*2011/20/20 MH For MP driver RT_WLAN_STA = struct sta_info*/
/*Please declare below ODM relative info in your STA info structure.*/
struct_ODM_STA_INFO{
/*Driver Write*/
boolis_used;/*record the sta status link or not?*/
u8iot_peer;/*Enum value. HT_IOT_PEER_E*/
/*ODM Write*/
/*PHY_STATUS_INFO*/
u8rssi_path[4];
u8rssi_ave;
u8RXEVM[4];
u8RXSNR[4];
};
enumodm_cmninfo_e{
/*Fixed value*/
/*-----------HOOK BEFORE REG INIT-----------*/
ODM_CMNINFO_PLATFORM=0,
ODM_CMNINFO_ABILITY,
ODM_CMNINFO_INTERFACE,
ODM_CMNINFO_MP_TEST_CHIP,
ODM_CMNINFO_IC_TYPE,
ODM_CMNINFO_CUT_VER,
ODM_CMNINFO_FAB_VER,
ODM_CMNINFO_RF_TYPE,
ODM_CMNINFO_RFE_TYPE,
ODM_CMNINFO_BOARD_TYPE,
ODM_CMNINFO_PACKAGE_TYPE,
ODM_CMNINFO_EXT_LNA,
ODM_CMNINFO_5G_EXT_LNA,
ODM_CMNINFO_EXT_PA,
ODM_CMNINFO_5G_EXT_PA,
ODM_CMNINFO_GPA,
ODM_CMNINFO_APA,
ODM_CMNINFO_GLNA,
ODM_CMNINFO_ALNA,
ODM_CMNINFO_EXT_TRSW,
ODM_CMNINFO_EXT_LNA_GAIN,
ODM_CMNINFO_PATCH_ID,
ODM_CMNINFO_BINHCT_TEST,
ODM_CMNINFO_BWIFI_TEST,
ODM_CMNINFO_SMART_CONCURRENT,
ODM_CMNINFO_CONFIG_BB_RF,
ODM_CMNINFO_DOMAIN_CODE_2G,
ODM_CMNINFO_DOMAIN_CODE_5G,
ODM_CMNINFO_IQKFWOFFLOAD,
ODM_CMNINFO_IQKPAOFF,
ODM_CMNINFO_HUBUSBMODE,
ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS,
ODM_CMNINFO_TX_TP,
ODM_CMNINFO_RX_TP,
ODM_CMNINFO_SOUNDING_SEQ,
ODM_CMNINFO_REGRFKFREEENABLE,
ODM_CMNINFO_RFKFREEENABLE,
ODM_CMNINFO_NORMAL_RX_PATH_CHANGE,
ODM_CMNINFO_EFUSE0X3D8,
ODM_CMNINFO_EFUSE0X3D7,
/*-----------HOOK BEFORE REG INIT-----------*/
/*Dynamic value:*/
/*--------- POINTER REFERENCE-----------*/
ODM_CMNINFO_MAC_PHY_MODE,
ODM_CMNINFO_TX_UNI,
ODM_CMNINFO_RX_UNI,
ODM_CMNINFO_WM_MODE,
ODM_CMNINFO_BAND,
ODM_CMNINFO_SEC_CHNL_OFFSET,
ODM_CMNINFO_SEC_MODE,
ODM_CMNINFO_BW,
ODM_CMNINFO_CHNL,
ODM_CMNINFO_FORCED_RATE,
ODM_CMNINFO_ANT_DIV,
ODM_CMNINFO_ADAPTIVITY,
ODM_CMNINFO_DMSP_GET_VALUE,
ODM_CMNINFO_BUDDY_ADAPTOR,
ODM_CMNINFO_DMSP_IS_MASTER,
ODM_CMNINFO_SCAN,
ODM_CMNINFO_POWER_SAVING,
ODM_CMNINFO_ONE_PATH_CCA,
ODM_CMNINFO_DRV_STOP,
ODM_CMNINFO_PNP_IN,
ODM_CMNINFO_INIT_ON,
ODM_CMNINFO_ANT_TEST,
ODM_CMNINFO_NET_CLOSED,
ODM_CMNINFO_FORCED_IGI_LB,
ODM_CMNINFO_P2P_LINK,
ODM_CMNINFO_FCS_MODE,
ODM_CMNINFO_IS1ANTENNA,
ODM_CMNINFO_RFDEFAULTPATH,
ODM_CMNINFO_DFS_MASTER_ENABLE,
ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC,
ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA,
/*--------- POINTER REFERENCE-----------*/
/*------------CALL BY VALUE-------------*/
ODM_CMNINFO_WIFI_DIRECT,
ODM_CMNINFO_WIFI_DISPLAY,
ODM_CMNINFO_LINK_IN_PROGRESS,
ODM_CMNINFO_LINK,
ODM_CMNINFO_STATION_STATE,
ODM_CMNINFO_RSSI_MIN,
ODM_CMNINFO_DBG_COMP,
ODM_CMNINFO_DBG_LEVEL,
ODM_CMNINFO_RA_THRESHOLD_HIGH,
ODM_CMNINFO_RA_THRESHOLD_LOW,
ODM_CMNINFO_RF_ANTENNA_TYPE,
ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH,
ODM_CMNINFO_BE_FIX_TX_ANT,
ODM_CMNINFO_BT_ENABLED,
ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
ODM_CMNINFO_BT_HS_RSSI,
ODM_CMNINFO_BT_OPERATION,
ODM_CMNINFO_BT_LIMITED_DIG,
ODM_CMNINFO_BT_DIG,
ODM_CMNINFO_BT_BUSY,
ODM_CMNINFO_BT_DISABLE_EDCA,
ODM_CMNINFO_AP_TOTAL_NUM,
ODM_CMNINFO_POWER_TRAINING,
ODM_CMNINFO_DFS_REGION_DOMAIN,
/*------------CALL BY VALUE-------------*/
/*Dynamic ptr array hook itms.*/
ODM_CMNINFO_STA_STATUS,
ODM_CMNINFO_MAX,
};
enumphydm_info_query_e{
PHYDM_INFO_FA_OFDM,
PHYDM_INFO_FA_CCK,
PHYDM_INFO_FA_TOTAL,
PHYDM_INFO_CCA_OFDM,
PHYDM_INFO_CCA_CCK,
PHYDM_INFO_CCA_ALL,
PHYDM_INFO_CRC32_OK_VHT,
PHYDM_INFO_CRC32_OK_HT,
PHYDM_INFO_CRC32_OK_LEGACY,
PHYDM_INFO_CRC32_OK_CCK,
PHYDM_INFO_CRC32_ERROR_VHT,
PHYDM_INFO_CRC32_ERROR_HT,
PHYDM_INFO_CRC32_ERROR_LEGACY,
PHYDM_INFO_CRC32_ERROR_CCK,
PHYDM_INFO_EDCCA_FLAG,
PHYDM_INFO_OFDM_ENABLE,
PHYDM_INFO_CCK_ENABLE,
PHYDM_INFO_DBG_PORT_0
};
enumphydm_api_e{
PHYDM_API_NBI=1,
PHYDM_API_CSI_MASK,
};
/*2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY*/
enumodm_ability_e{
/*BB ODM section BIT 0-19*/
ODM_BB_DIG=BIT(0),
ODM_BB_RA_MASK=BIT(1),
ODM_BB_DYNAMIC_TXPWR=BIT(2),
ODM_BB_FA_CNT=BIT(3),
ODM_BB_RSSI_MONITOR=BIT(4),
ODM_BB_CCK_PD=BIT(5),
ODM_BB_ANT_DIV=BIT(6),
ODM_BB_PWR_TRAIN=BIT(8),
ODM_BB_RATE_ADAPTIVE=BIT(9),
ODM_BB_PATH_DIV=BIT(10),
ODM_BB_ADAPTIVITY=BIT(13),
ODM_BB_CFO_TRACKING=BIT(14),
ODM_BB_NHM_CNT=BIT(15),
ODM_BB_PRIMARY_CCA=BIT(16),
ODM_BB_TXBF=BIT(17),
ODM_BB_DYNAMIC_ARFR=BIT(18),
ODM_MAC_EDCA_TURBO=BIT(20),
ODM_BB_DYNAMIC_RX_PATH=BIT(21),
/*RF ODM section BIT 24-31*/
ODM_RF_TX_PWR_TRACK=BIT(24),
ODM_RF_RX_GAIN_TRACK=BIT(25),
ODM_RF_CALIBRATION=BIT(26),
};
/*ODM_CMNINFO_ONE_PATH_CCA*/
enumodm_cca_path_e{
ODM_CCA_2R=0,
ODM_CCA_1R_A=1,
ODM_CCA_1R_B=2,
};
enumcca_pathdiv_en_e{
CCA_PATHDIV_DISABLE=0,
CCA_PATHDIV_ENABLE=1,
};
enumphy_reg_pg_type{
PHY_REG_PG_RELATIVE_VALUE=0,
PHY_REG_PG_EXACT_VALUE=1
};
/*2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration.*/
