2013-05-08 21:45:39 +00:00
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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2014-12-19 06:59:46 +00:00
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*
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2013-05-08 21:45:39 +00:00
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef _RTW_IO_H_
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#define _RTW_IO_H_
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2018-10-15 00:07:45 +00:00
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#define NUM_IOREQ 8
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2013-05-08 21:45:39 +00:00
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2018-10-19 20:16:35 +00:00
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#define MAX_PROT_SZ (64-16)
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2014-12-11 21:15:04 +00:00
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#define _IOREADY 0
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#define _IO_WAIT_COMPLETE 1
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#define _IO_WAIT_RSP 2
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2013-05-08 21:45:39 +00:00
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2018-10-15 00:07:45 +00:00
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/* IO COMMAND TYPE */
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2013-05-08 21:45:39 +00:00
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#define _IOSZ_MASK_ (0x7F)
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#define _IO_WRITE_ BIT(7)
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#define _IO_FIXED_ BIT(8)
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#define _IO_BURST_ BIT(9)
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#define _IO_BYTE_ BIT(10)
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#define _IO_HW_ BIT(11)
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#define _IO_WORD_ BIT(12)
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#define _IO_SYNC_ BIT(13)
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2014-12-11 21:15:04 +00:00
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#define _IO_CMDMASK_ (0x1F80)
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2013-05-08 21:45:39 +00:00
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2014-12-11 21:15:04 +00:00
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2014-12-19 06:59:46 +00:00
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/*
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2013-05-08 21:45:39 +00:00
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For prompt mode accessing, caller shall free io_req
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Otherwise, io_handler will free io_req
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*/
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2014-12-11 21:15:04 +00:00
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2018-10-15 00:07:45 +00:00
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/* IO STATUS TYPE */
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2013-05-08 21:45:39 +00:00
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#define _IO_ERR_ BIT(2)
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2014-12-11 21:15:04 +00:00
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#define _IO_SUCCESS_ BIT(1)
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2013-05-08 21:45:39 +00:00
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#define _IO_DONE_ BIT(0)
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2014-12-11 21:15:04 +00:00
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2013-05-08 21:45:39 +00:00
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#define IO_RD32 (_IO_SYNC_ | _IO_WORD_)
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#define IO_RD16 (_IO_SYNC_ | _IO_HW_)
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#define IO_RD8 (_IO_SYNC_ | _IO_BYTE_)
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2014-12-11 21:15:04 +00:00
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#define IO_RD32_ASYNC (_IO_WORD_)
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#define IO_RD16_ASYNC (_IO_HW_)
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#define IO_RD8_ASYNC (_IO_BYTE_)
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2013-05-08 21:45:39 +00:00
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#define IO_WR32 (_IO_WRITE_ | _IO_SYNC_ | _IO_WORD_)
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#define IO_WR16 (_IO_WRITE_ | _IO_SYNC_ | _IO_HW_)
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#define IO_WR8 (_IO_WRITE_ | _IO_SYNC_ | _IO_BYTE_)
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2014-12-11 21:15:04 +00:00
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#define IO_WR32_ASYNC (_IO_WRITE_ | _IO_WORD_)
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#define IO_WR16_ASYNC (_IO_WRITE_ | _IO_HW_)
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#define IO_WR8_ASYNC (_IO_WRITE_ | _IO_BYTE_)
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2013-05-08 21:45:39 +00:00
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/*
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2014-12-11 21:15:04 +00:00
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2013-05-08 21:45:39 +00:00
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Only Sync. burst accessing is provided.
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2014-12-11 21:15:04 +00:00
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2013-05-08 21:45:39 +00:00
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*/
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2018-10-15 00:07:45 +00:00
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#define IO_WR_BURST(x) (_IO_WRITE_ | _IO_SYNC_ | _IO_BURST_ | ((x) & _IOSZ_MASK_))
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#define IO_RD_BURST(x) (_IO_SYNC_ | _IO_BURST_ | ((x) & _IOSZ_MASK_))
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2014-12-11 21:15:04 +00:00
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2013-05-08 21:45:39 +00:00
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2015-03-16 14:43:53 +00:00
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/* below is for the intf_option bit defition... */
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2014-12-11 21:15:04 +00:00
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2015-03-16 14:43:53 +00:00
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#define _INTF_ASYNC_ BIT(0) /* support async io */
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2013-05-08 21:45:39 +00:00
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struct intf_priv;
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struct intf_hdl;
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struct io_queue;
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2018-10-15 00:07:45 +00:00
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struct _io_ops {
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u8(*_read8)(struct intf_hdl *pintfhdl, u32 addr);
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2018-11-02 01:34:15 +00:00
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u16(*_read16)(struct intf_hdl *pintfhdl, u32 addr);
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u32(*_read32)(struct intf_hdl *pintfhdl, u32 addr);
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2018-10-15 00:07:45 +00:00
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int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
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2018-10-25 19:23:42 +00:00
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int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, __le16 val);
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int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, __le32 val);
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2018-10-15 00:07:45 +00:00
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int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata);
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2014-12-11 21:15:04 +00:00
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2018-10-15 00:07:45 +00:00
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int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
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2018-10-25 19:23:42 +00:00
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int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, __le16 val);
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int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, __le32 val);
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2014-12-11 21:15:04 +00:00
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2018-10-15 00:07:45 +00:00
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void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
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void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
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2014-12-11 21:15:04 +00:00
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2018-10-15 00:07:45 +00:00
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void (*_sync_irp_protocol_rw)(struct io_queue *pio_q);
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2014-12-11 21:15:04 +00:00
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2018-10-15 00:07:45 +00:00
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u32(*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
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2014-12-11 21:15:04 +00:00
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2018-10-15 00:07:45 +00:00
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u32(*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
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u32(*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
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2014-12-11 21:15:04 +00:00
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2018-10-15 00:07:45 +00:00
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u32(*_write_scsi)(struct intf_hdl *pintfhdl, u32 cnt, u8 *pmem);
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2014-12-11 21:15:04 +00:00
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2018-10-15 00:07:45 +00:00
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void (*_read_port_cancel)(struct intf_hdl *pintfhdl);
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void (*_write_port_cancel)(struct intf_hdl *pintfhdl);
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2014-12-11 21:15:04 +00:00
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2018-10-15 00:07:45 +00:00
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#ifdef CONFIG_SDIO_HCI
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u8(*_sd_f0_read8)(struct intf_hdl *pintfhdl, u32 addr);
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#ifdef CONFIG_SDIO_INDIRECT_ACCESS
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u8(*_sd_iread8)(struct intf_hdl *pintfhdl, u32 addr);
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u16(*_sd_iread16)(struct intf_hdl *pintfhdl, u32 addr);
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u32(*_sd_iread32)(struct intf_hdl *pintfhdl, u32 addr);
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int (*_sd_iwrite8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
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int (*_sd_iwrite16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
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int (*_sd_iwrite32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
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#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
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#endif
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2014-12-19 06:59:46 +00:00
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2013-05-08 21:45:39 +00:00
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};
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2014-12-19 06:59:46 +00:00
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struct io_req {
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2018-10-15 00:07:45 +00:00
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_list list;
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2014-12-19 06:59:46 +00:00
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u32 addr;
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2014-12-11 21:15:04 +00:00
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volatile u32 val;
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2013-05-08 21:45:39 +00:00
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u32 command;
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u32 status;
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2014-12-19 06:59:46 +00:00
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u8 *pbuf;
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2018-10-15 00:07:45 +00:00
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_sema sema;
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2014-12-11 21:15:04 +00:00
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2018-10-15 00:07:45 +00:00
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void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt);
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2014-12-19 06:59:46 +00:00
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u8 *cnxt;
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2013-05-08 21:45:39 +00:00
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};
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struct intf_hdl {
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2018-10-15 00:07:45 +00:00
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_adapter *padapter;
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struct dvobj_priv *pintf_dev;/* pointer to &(padapter->dvobjpriv); */
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2014-12-11 21:15:04 +00:00
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2013-05-08 21:45:39 +00:00
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struct _io_ops io_ops;
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2014-12-11 21:15:04 +00:00
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2013-05-08 21:45:39 +00:00
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};
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struct reg_protocol_rd {
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2014-12-11 21:15:04 +00:00
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2018-10-24 22:25:46 +00:00
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#ifdef __LITTLE_ENDIAN
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2014-12-11 21:15:04 +00:00
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2015-03-16 14:43:53 +00:00
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/* DW1 */
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2013-05-08 21:45:39 +00:00
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u32 NumOfTrans:4;
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u32 Reserved1:4;
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u32 Reserved2:24;
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2015-03-16 14:43:53 +00:00
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/* DW2 */
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2013-05-08 21:45:39 +00:00
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u32 ByteCount:7;
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2015-03-16 14:43:53 +00:00
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u32 WriteEnable:1; /* 0:read, 1:write */
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u32 FixOrContinuous:1; /* 0:continuous, 1: Fix */
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2013-05-08 21:45:39 +00:00
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u32 BurstMode:1;
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u32 Byte1Access:1;
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u32 Byte2Access:1;
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u32 Byte4Access:1;
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u32 Reserved3:3;
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u32 Reserved4:16;
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2015-03-16 14:43:53 +00:00
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/* DW3 */
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2013-05-08 21:45:39 +00:00
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u32 BusAddress;
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2015-03-16 14:43:53 +00:00
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/* DW4 */
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/* u32 Value; */
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2013-05-08 21:45:39 +00:00
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#else
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2014-12-11 21:15:04 +00:00
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2018-10-15 00:07:45 +00:00
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/* DW1 */
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2018-10-24 22:25:46 +00:00
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u32 Reserved2:24;
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2018-10-15 00:07:45 +00:00
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u32 Reserved1:4;
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u32 NumOfTrans:4;
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2014-12-11 21:15:04 +00:00
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2015-03-16 14:43:53 +00:00
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/* DW2 */
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2018-10-24 22:25:46 +00:00
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u32 Reserved4:16;
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2018-10-15 00:07:45 +00:00
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u32 Reserved3:3;
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u32 Byte4Access:1;
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u32 Byte2Access:1;
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2018-10-24 22:25:46 +00:00
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u32 WriteEnable:1;
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2018-10-15 00:07:45 +00:00
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u32 Byte1Access:1;
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u32 BurstMode:1;
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u32 FixOrContinuous:1;
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2018-10-24 22:25:46 +00:00
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u32 ByteCount:7;
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2014-12-11 21:15:04 +00:00
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2015-03-16 14:43:53 +00:00
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/* DW3 */
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2014-12-11 21:15:04 +00:00
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u32 BusAddress;
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2015-03-16 14:43:53 +00:00
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/* DW4 */
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/* u32 Value; */
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2014-12-11 21:15:04 +00:00
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2013-05-08 21:45:39 +00:00
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#endif
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};
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struct reg_protocol_wt {
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2014-12-19 06:59:46 +00:00
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2014-12-11 21:15:04 +00:00
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2018-10-24 22:25:46 +00:00
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#ifdef __LITTLE_ENDIAN
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2014-12-11 21:15:04 +00:00
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2015-03-16 14:43:53 +00:00
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/* DW1 */
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2014-12-11 21:15:04 +00:00
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u32 NumOfTrans:4;
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u32 Reserved1:4;
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u32 Reserved2:24;
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2015-03-16 14:43:53 +00:00
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/* DW2 */
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2014-12-11 21:15:04 +00:00
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u32 ByteCount:7;
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2015-03-16 14:43:53 +00:00
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u32 WriteEnable:1; /* 0:read, 1:write */
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u32 FixOrContinuous:1; /* 0:continuous, 1: Fix */
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2014-12-11 21:15:04 +00:00
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u32 BurstMode:1;
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u32 Byte1Access:1;
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u32 Byte2Access:1;
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u32 Byte4Access:1;
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u32 Reserved3:3;
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u32 Reserved4:16;
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2015-03-16 14:43:53 +00:00
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/* DW3 */
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2014-12-11 21:15:04 +00:00
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u32 BusAddress;
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2015-03-16 14:43:53 +00:00
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/* DW4 */
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2014-12-11 21:15:04 +00:00
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u32 Value;
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2013-05-08 21:45:39 +00:00
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#else
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2015-03-16 14:43:53 +00:00
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/* DW1 */
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2018-10-24 22:25:46 +00:00
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u32 Reserved2:24;
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2018-10-15 00:07:45 +00:00
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u32 Reserved1:4;
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u32 NumOfTrans:4;
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2014-12-11 21:15:04 +00:00
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2015-03-16 14:43:53 +00:00
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/* DW2 */
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2018-10-24 22:25:46 +00:00
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u32 Reserved4:16;
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2018-10-15 00:07:45 +00:00
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u32 Reserved3:3;
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u32 Byte4Access:1;
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u32 Byte2Access:1;
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u32 Byte1Access:1;
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u32 BurstMode:1;
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u32 FixOrContinuous:1;
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2018-10-24 22:25:46 +00:00
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u32 WriteEnable:1;
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u32 ByteCount:7;
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2014-12-11 21:15:04 +00:00
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2015-03-16 14:43:53 +00:00
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/* DW3 */
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2014-12-11 21:15:04 +00:00
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u32 BusAddress;
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2015-03-16 14:43:53 +00:00
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/* DW4 */
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2014-12-11 21:15:04 +00:00
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u32 Value;
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2013-05-08 21:45:39 +00:00
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#endif
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2014-12-11 21:15:04 +00:00
|
|
|
|
2013-05-08 21:45:39 +00:00
|
|
|
};
|
2018-10-15 00:07:45 +00:00
|
|
|
#ifdef CONFIG_PCI_HCI
|
2014-12-11 21:15:04 +00:00
|
|
|
#define MAX_CONTINUAL_IO_ERR 4
|
2018-10-15 00:07:45 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_USB_HCI
|
|
|
|
|
#define MAX_CONTINUAL_IO_ERR 4
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_SDIO_HCI
|
|
|
|
|
#define SD_IO_TRY_CNT (8)
|
|
|
|
|
#define MAX_CONTINUAL_IO_ERR SD_IO_TRY_CNT
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_GSPI_HCI
|
|
|
|
|
#define SD_IO_TRY_CNT (8)
|
|
|
|
|
#define MAX_CONTINUAL_IO_ERR SD_IO_TRY_CNT
|
|
|
|
|
#endif
|
|
|
|
|
|
2014-12-11 21:15:04 +00:00
|
|
|
|
|
|
|
|
int rtw_inc_and_chk_continual_io_error(struct dvobj_priv *dvobj);
|
|
|
|
|
void rtw_reset_continual_io_error(struct dvobj_priv *dvobj);
|
2013-05-08 21:45:39 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
Below is the data structure used by _io_handler
|
2014-12-11 21:15:04 +00:00
|
|
|
|
2013-05-08 21:45:39 +00:00
|
|
|
*/
|
|
|
|
|
|
2014-12-19 06:59:46 +00:00
|
|
|
struct io_queue {
|
2018-10-15 00:07:45 +00:00
|
|
|
_lock lock;
|
|
|
|
|
_list free_ioreqs;
|
|
|
|
|
_list pending; /* The io_req list that will be served in the single protocol read/write. */
|
|
|
|
|
_list processing;
|
|
|
|
|
u8 *free_ioreqs_buf; /* 4-byte aligned */
|
2013-05-08 21:45:39 +00:00
|
|
|
u8 *pallocated_free_ioreqs_buf;
|
|
|
|
|
struct intf_hdl intf;
|
|
|
|
|
};
|
|
|
|
|
|
2018-10-15 00:07:45 +00:00
|
|
|
struct io_priv {
|
2014-12-19 06:59:46 +00:00
|
|
|
|
2018-10-15 00:07:45 +00:00
|
|
|
_adapter *padapter;
|
2014-12-19 06:59:46 +00:00
|
|
|
|
2013-05-08 21:45:39 +00:00
|
|
|
struct intf_hdl intf;
|
2014-12-11 21:15:04 +00:00
|
|
|
|
2013-05-08 21:45:39 +00:00
|
|
|
};
|
|
|
|
|
|
2018-10-15 00:07:45 +00:00
|
|
|
extern uint ioreq_flush(_adapter *adapter, struct io_queue *ioqueue);
|
|
|
|
|
extern void sync_ioreq_enqueue(struct io_req *preq, struct io_queue *ioqueue);
|
|
|
|
|
extern uint sync_ioreq_flush(_adapter *adapter, struct io_queue *ioqueue);
|
2014-12-11 21:15:04 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
extern uint free_ioreq(struct io_req *preq, struct io_queue *pio_queue);
|
|
|
|
|
extern struct io_req *alloc_ioreq(struct io_queue *pio_q);
|
2013-05-08 21:45:39 +00:00
|
|
|
|
2014-12-11 21:15:04 +00:00
|
|
|
extern uint register_intf_hdl(u8 *dev, struct intf_hdl *pintfhdl);
|
|
|
|
|
extern void unregister_intf_hdl(struct intf_hdl *pintfhdl);
|
2013-05-08 21:45:39 +00:00
|
|
|
|
2018-10-15 00:07:45 +00:00
|
|
|
extern void _rtw_attrib_read(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
|
|
|
|
|
extern void _rtw_attrib_write(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
|
|
|
|
|
|
|
|
|
|
extern u8 _rtw_read8(_adapter *adapter, u32 addr);
|
|
|
|
|
extern u16 _rtw_read16(_adapter *adapter, u32 addr);
|
|
|
|
|
extern u32 _rtw_read32(_adapter *adapter, u32 addr);
|
|
|
|
|
extern void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
|
|
|
|
|
extern void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
|
|
|
|
|
extern void _rtw_read_port_cancel(_adapter *adapter);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
extern int _rtw_write8(_adapter *adapter, u32 addr, u8 val);
|
|
|
|
|
extern int _rtw_write16(_adapter *adapter, u32 addr, u16 val);
|
|
|
|
|
extern int _rtw_write32(_adapter *adapter, u32 addr, u32 val);
|
|
|
|
|
extern int _rtw_writeN(_adapter *adapter, u32 addr, u32 length, u8 *pdata);
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_SDIO_HCI
|
|
|
|
|
u8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr);
|
|
|
|
|
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
|
|
|
|
|
u8 _rtw_sd_iread8(_adapter *adapter, u32 addr);
|
|
|
|
|
u16 _rtw_sd_iread16(_adapter *adapter, u32 addr);
|
|
|
|
|
u32 _rtw_sd_iread32(_adapter *adapter, u32 addr);
|
|
|
|
|
int _rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val);
|
|
|
|
|
int _rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val);
|
|
|
|
|
int _rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val);
|
|
|
|
|
#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
|
|
|
|
|
#endif /* CONFIG_SDIO_HCI */
|
|
|
|
|
|
|
|
|
|
extern int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val);
|
|
|
|
|
extern int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val);
|
|
|
|
|
extern int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val);
|
|
|
|
|
|
|
|
|
|
extern void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
|
|
|
|
|
extern u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
|
|
|
|
|
u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms);
|
|
|
|
|
extern void _rtw_write_port_cancel(_adapter *adapter);
|
2014-12-11 21:15:04 +00:00
|
|
|
|
|
|
|
|
#ifdef DBG_IO
|
2018-10-15 00:07:45 +00:00
|
|
|
bool match_read_sniff_ranges(u32 addr, u16 len);
|
|
|
|
|
bool match_write_sniff_ranges(u32 addr, u16 len);
|
|
|
|
|
bool match_rf_read_sniff_ranges(u8 path, u32 addr, u32 mask);
|
|
|
|
|
bool match_rf_write_sniff_ranges(u8 path, u32 addr, u32 mask);
|
|
|
|
|
|
|
|
|
|
extern u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line);
|
|
|
|
|
extern u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line);
|
|
|
|
|
extern u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line);
|
|
|
|
|
|
|
|
|
|
extern int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line);
|
|
|
|
|
extern int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line);
|
|
|
|
|
extern int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line);
|
|
|
|
|
extern int dbg_rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *data, const char *caller, const int line);
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_SDIO_HCI
|
|
|
|
|
u8 dbg_rtw_sd_f0_read8(_adapter *adapter, u32 addr, const char *caller, const int line);
|
|
|
|
|
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
|
|
|
|
|
u8 dbg_rtw_sd_iread8(_adapter *adapter, u32 addr, const char *caller, const int line);
|
|
|
|
|
u16 dbg_rtw_sd_iread16(_adapter *adapter, u32 addr, const char *caller, const int line);
|
|
|
|
|
u32 dbg_rtw_sd_iread32(_adapter *adapter, u32 addr, const char *caller, const int line);
|
|
|
|
|
int dbg_rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line);
|
|
|
|
|
int dbg_rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line);
|
|
|
|
|
int dbg_rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line);
|
|
|
|
|
#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
|
|
|
|
|
#endif /* CONFIG_SDIO_HCI */
|
2014-12-11 21:15:04 +00:00
|
|
|
|
|
|
|
|
#define rtw_read8(adapter, addr) dbg_rtw_read8((adapter), (addr), __FUNCTION__, __LINE__)
|
|
|
|
|
#define rtw_read16(adapter, addr) dbg_rtw_read16((adapter), (addr), __FUNCTION__, __LINE__)
|
|
|
|
|
#define rtw_read32(adapter, addr) dbg_rtw_read32((adapter), (addr), __FUNCTION__, __LINE__)
|
|
|
|
|
#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem))
|
|
|
|
|
#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem))
|
|
|
|
|
#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter))
|
|
|
|
|
|
|
|
|
|
#define rtw_write8(adapter, addr, val) dbg_rtw_write8((adapter), (addr), (val), __FUNCTION__, __LINE__)
|
|
|
|
|
#define rtw_write16(adapter, addr, val) dbg_rtw_write16((adapter), (addr), (val), __FUNCTION__, __LINE__)
|
|
|
|
|
#define rtw_write32(adapter, addr, val) dbg_rtw_write32((adapter), (addr), (val), __FUNCTION__, __LINE__)
|
|
|
|
|
#define rtw_writeN(adapter, addr, length, data) dbg_rtw_writeN((adapter), (addr), (length), (data), __FUNCTION__, __LINE__)
|
|
|
|
|
|
|
|
|
|
#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val))
|
|
|
|
|
#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val))
|
|
|
|
|
#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val))
|
|
|
|
|
|
|
|
|
|
#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), addr, cnt, mem)
|
|
|
|
|
#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port(adapter, addr, cnt, mem)
|
|
|
|
|
#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms))
|
|
|
|
|
#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel(adapter)
|
2018-10-15 00:07:45 +00:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_SDIO_HCI
|
|
|
|
|
#define rtw_sd_f0_read8(adapter, addr) dbg_rtw_sd_f0_read8((adapter), (addr), __func__, __LINE__)
|
|
|
|
|
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
|
|
|
|
|
#define rtw_sd_iread8(adapter, addr) dbg_rtw_sd_iread8((adapter), (addr), __func__, __LINE__)
|
|
|
|
|
#define rtw_sd_iread16(adapter, addr) dbg_rtw_sd_iread16((adapter), (addr), __func__, __LINE__)
|
|
|
|
|
#define rtw_sd_iread32(adapter, addr) dbg_rtw_sd_iread32((adapter), (addr), __func__, __LINE__)
|
|
|
|
|
#define rtw_sd_iwrite8(adapter, addr, val) dbg_rtw_sd_iwrite8((adapter), (addr), (val), __func__, __LINE__)
|
|
|
|
|
#define rtw_sd_iwrite16(adapter, addr, val) dbg_rtw_sd_iwrite16((adapter), (addr), (val), __func__, __LINE__)
|
|
|
|
|
#define rtw_sd_iwrite32(adapter, addr, val) dbg_rtw_sd_iwrite32((adapter), (addr), (val), __func__, __LINE__)
|
|
|
|
|
#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
|
|
|
|
|
#endif /* CONFIG_SDIO_HCI */
|
|
|
|
|
|
2015-03-16 14:43:53 +00:00
|
|
|
#else /* DBG_IO */
|
2018-10-15 00:07:45 +00:00
|
|
|
#define match_read_sniff_ranges(addr, len) _FALSE
|
|
|
|
|
#define match_write_sniff_ranges(addr, len) _FALSE
|
|
|
|
|
#define match_rf_read_sniff_ranges(path, addr, mask) _FALSE
|
|
|
|
|
#define match_rf_write_sniff_ranges(path, addr, mask) _FALSE
|
2013-05-08 21:45:39 +00:00
|
|
|
#define rtw_read8(adapter, addr) _rtw_read8((adapter), (addr))
|
|
|
|
|
#define rtw_read16(adapter, addr) _rtw_read16((adapter), (addr))
|
|
|
|
|
#define rtw_read32(adapter, addr) _rtw_read32((adapter), (addr))
|
2014-12-11 21:15:04 +00:00
|
|
|
#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem))
|
|
|
|
|
#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem))
|
2013-05-08 21:45:39 +00:00
|
|
|
#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter))
|
|
|
|
|
|
2014-12-11 21:15:04 +00:00
|
|
|
#define rtw_write8(adapter, addr, val) _rtw_write8((adapter), (addr), (val))
|
|
|
|
|
#define rtw_write16(adapter, addr, val) _rtw_write16((adapter), (addr), (val))
|
|
|
|
|
#define rtw_write32(adapter, addr, val) _rtw_write32((adapter), (addr), (val))
|
|
|
|
|
#define rtw_writeN(adapter, addr, length, data) _rtw_writeN((adapter), (addr), (length), (data))
|
|
|
|
|
|
|
|
|
|
#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val))
|
|
|
|
|
#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val))
|
|
|
|
|
#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val))
|
|
|
|
|
|
|
|
|
|
#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), (addr), (cnt), (mem))
|
|
|
|
|
#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port((adapter), (addr), (cnt), (mem))
|
|
|
|
|
#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms))
|
2013-05-08 21:45:39 +00:00
|
|
|
#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel((adapter))
|
2018-10-15 00:07:45 +00:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_SDIO_HCI
|
|
|
|
|
#define rtw_sd_f0_read8(adapter, addr) _rtw_sd_f0_read8((adapter), (addr))
|
|
|
|
|
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
|
|
|
|
|
#define rtw_sd_iread8(adapter, addr) _rtw_sd_iread8((adapter), (addr))
|
|
|
|
|
#define rtw_sd_iread16(adapter, addr) _rtw_sd_iread16((adapter), (addr))
|
|
|
|
|
#define rtw_sd_iread32(adapter, addr) _rtw_sd_iread32((adapter), (addr))
|
|
|
|
|
#define rtw_sd_iwrite8(adapter, addr, val) _rtw_sd_iwrite8((adapter), (addr), (val))
|
|
|
|
|
#define rtw_sd_iwrite16(adapter, addr, val) _rtw_sd_iwrite16((adapter), (addr), (val))
|
|
|
|
|
#define rtw_sd_iwrite32(adapter, addr, val) _rtw_sd_iwrite32((adapter), (addr), (val))
|
|
|
|
|
#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
|
|
|
|
|
#endif /* CONFIG_SDIO_HCI */
|
|
|
|
|
|
2015-03-16 14:43:53 +00:00
|
|
|
#endif /* DBG_IO */
|
2014-12-11 21:15:04 +00:00
|
|
|
|
2018-10-15 00:07:45 +00:00
|
|
|
extern void rtw_write_scsi(_adapter *adapter, u32 cnt, u8 *pmem);
|
2014-12-11 21:15:04 +00:00
|
|
|
|
2015-03-16 14:43:53 +00:00
|
|
|
/* ioreq */
|
2018-10-15 00:07:45 +00:00
|
|
|
extern void ioreq_read8(_adapter *adapter, u32 addr, u8 *pval);
|
|
|
|
|
extern void ioreq_read16(_adapter *adapter, u32 addr, u16 *pval);
|
|
|
|
|
extern void ioreq_read32(_adapter *adapter, u32 addr, u32 *pval);
|
|
|
|
|
extern void ioreq_write8(_adapter *adapter, u32 addr, u8 val);
|
|
|
|
|
extern void ioreq_write16(_adapter *adapter, u32 addr, u16 val);
|
|
|
|
|
extern void ioreq_write32(_adapter *adapter, u32 addr, u32 val);
|
2014-12-11 21:15:04 +00:00
|
|
|
|
|
|
|
|
|
2018-10-15 00:07:45 +00:00
|
|
|
extern uint async_read8(_adapter *adapter, u32 addr, u8 *pbuff,
|
|
|
|
|
void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
|
|
|
|
|
extern uint async_read16(_adapter *adapter, u32 addr, u8 *pbuff,
|
|
|
|
|
void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
|
|
|
|
|
extern uint async_read32(_adapter *adapter, u32 addr, u8 *pbuff,
|
|
|
|
|
void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
|
2013-05-08 21:45:39 +00:00
|
|
|
|
2018-10-15 00:07:45 +00:00
|
|
|
extern void async_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
|
|
|
|
|
extern void async_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
|
2014-12-11 21:15:04 +00:00
|
|
|
|
2018-10-15 00:07:45 +00:00
|
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extern void async_write8(_adapter *adapter, u32 addr, u8 val,
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void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
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extern void async_write16(_adapter *adapter, u32 addr, u16 val,
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void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
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extern void async_write32(_adapter *adapter, u32 addr, u32 val,
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void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
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2014-12-11 21:15:04 +00:00
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2018-10-15 00:07:45 +00:00
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extern void async_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
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extern void async_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
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2014-12-11 21:15:04 +00:00
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2018-10-15 00:07:45 +00:00
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int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(_adapter *padapter, struct _io_ops *pops));
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2014-12-11 21:15:04 +00:00
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2018-10-15 00:07:45 +00:00
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extern uint alloc_io_queue(_adapter *adapter);
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extern void free_io_queue(_adapter *adapter);
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2014-12-11 21:15:04 +00:00
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extern void async_bus_io(struct io_queue *pio_q);
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extern void bus_sync_io(struct io_queue *pio_q);
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extern u32 _ioreq2rwmem(struct io_queue *pio_q);
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2018-10-15 00:07:45 +00:00
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extern void dev_power_down(_adapter *Adapter, u8 bpwrup);
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2014-12-11 21:15:04 +00:00
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/*
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#define RTL_R8(reg) rtw_read8(padapter, reg)
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#define RTL_R16(reg) rtw_read16(padapter, reg)
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#define RTL_R32(reg) rtw_read32(padapter, reg)
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#define RTL_W8(reg, val8) rtw_write8(padapter, reg, val8)
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#define RTL_W16(reg, val16) rtw_write16(padapter, reg, val16)
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#define RTL_W32(reg, val32) rtw_write32(padapter, reg, val32)
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*/
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/*
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#define RTL_W8_ASYNC(reg, val8) rtw_write32_async(padapter, reg, val8)
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#define RTL_W16_ASYNC(reg, val16) rtw_write32_async(padapter, reg, val16)
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#define RTL_W32_ASYNC(reg, val32) rtw_write32_async(padapter, reg, val32)
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#define RTL_WRITE_BB(reg, val32) phy_SetUsbBBReg(padapter, reg, val32)
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#define RTL_READ_BB(reg) phy_QueryUsbBBReg(padapter, reg)
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*/
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2013-05-08 21:45:39 +00:00
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2018-10-15 00:07:45 +00:00
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#define PlatformEFIOWrite1Byte(_a, _b, _c) \
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rtw_write8(_a, _b, _c)
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#define PlatformEFIOWrite2Byte(_a, _b, _c) \
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rtw_write16(_a, _b, _c)
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#define PlatformEFIOWrite4Byte(_a, _b, _c) \
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rtw_write32(_a, _b, _c)
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#define PlatformEFIORead1Byte(_a, _b) \
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rtw_read8(_a, _b)
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#define PlatformEFIORead2Byte(_a, _b) \
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rtw_read16(_a, _b)
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#define PlatformEFIORead4Byte(_a, _b) \
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rtw_read32(_a, _b)
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#endif /* _RTL8711_IO_H_ */
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