mirror of
https://github.com/lwfinger/rtl8188eu.git
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rtl8188eu: Remove code for platforms other than Linux in hal/
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
parent
85ec7cf9ce
commit
038e7c215b
13 changed files with 4 additions and 2920 deletions
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@ -5,8 +5,6 @@
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/*
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* 2011/03/15 MH Add for different IC HW image file selection. code size consideration.
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* */
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#if RT_PLATFORM == PLATFORM_LINUX
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#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
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/* For 92C */
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#define RTL8192CE_HWIMG_SUPPORT 1
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@ -77,47 +75,4 @@
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#define RTL8188ES_HWIMG_SUPPORT 0
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#endif
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#else /* PLATFORM_WINDOWS & MacOSX */
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/* For 92C */
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#define RTL8192CE_HWIMG_SUPPORT 1
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#define RTL8192CE_TEST_HWIMG_SUPPORT 1
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#define RTL8192CU_HWIMG_SUPPORT 1
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#define RTL8192CU_TEST_HWIMG_SUPPORT 1
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/* For 92D */
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#define RTL8192DE_HWIMG_SUPPORT 1
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#define RTL8192DE_TEST_HWIMG_SUPPORT 1
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#define RTL8192DU_HWIMG_SUPPORT 1
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#define RTL8192DU_TEST_HWIMG_SUPPORT 1
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#if defined(UNDER_CE)
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/* For 8723 */
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#define RTL8723E_HWIMG_SUPPORT 0
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#define RTL8723U_HWIMG_SUPPORT 0
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#define RTL8723S_HWIMG_SUPPORT 1
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/* For 88E */
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#define RTL8188EE_HWIMG_SUPPORT 0
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#define RTL8188EU_HWIMG_SUPPORT 0
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#define RTL8188ES_HWIMG_SUPPORT 0
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#else
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/* For 8723 */
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#define RTL8723E_HWIMG_SUPPORT 1
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/* #define RTL_8723E_TEST_HWIMG_SUPPORT 1 */
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#define RTL8723U_HWIMG_SUPPORT 1
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/* #define RTL_8723U_TEST_HWIMG_SUPPORT 1 */
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#define RTL8723S_HWIMG_SUPPORT 1
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/* #define RTL_8723S_TEST_HWIMG_SUPPORT 1 */
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/* For 88E */
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#define RTL8188EE_HWIMG_SUPPORT 1
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#define RTL8188EU_HWIMG_SUPPORT 1
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#define RTL8188ES_HWIMG_SUPPORT 1
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#endif
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#endif
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#endif /* __INC_HW_IMG_H */
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@ -18,7 +18,6 @@
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*
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******************************************************************************/
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#ifndef __HALDMOUTSRC_H__
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#define __HALDMOUTSRC_H__
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@ -47,7 +46,6 @@
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#include "phydm_adc_sampling.h"
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#include "phydm_dynamic_rx_path.h"
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#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
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#include "phydm_beamforming.h"
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#endif
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@ -107,7 +105,6 @@
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#define FREQ_POSITIVE 1
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#define FREQ_NEGATIVE 2
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
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#define PHYDM_WATCH_DOG_PERIOD 1
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#else
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@ -128,7 +125,6 @@ struct rtl8192cd_priv {
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};
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#endif
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#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
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struct _ADAPTER {
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u8 temp;
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@ -157,7 +153,6 @@ struct _dynamic_primary_cca {
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u8 MF_state;
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};
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#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
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#ifdef ADSL_AP_BUILD_WORKAROUND
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#define MAX_TOLERANCE 5
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@ -173,7 +168,6 @@ struct _dynamic_primary_cca {
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#define IQK_THRESHOLD 8
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#define DPK_THRESHOLD 4
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#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
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__PACK struct _odm_phy_status_info_ {
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u8 rx_pwdb_all;
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@ -253,7 +247,6 @@ struct _odm_per_pkt_info_ {
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u8 ppdu_cnt;
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};
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struct _odm_phy_dbg_info_ {
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/*ODM Write,debug info*/
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s8 rx_snr_db[4];
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@ -276,7 +269,6 @@ struct _odm_phy_dbg_info_ {
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};
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/*2011/20/20 MH For MP driver RT_WLAN_STA = struct sta_info*/
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/*Please declare below ODM relative info in your STA info structure.*/
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@ -415,7 +407,6 @@ enum odm_cmninfo_e {
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};
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enum phydm_info_query_e {
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PHYDM_INFO_FA_OFDM,
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PHYDM_INFO_FA_CCK,
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@ -444,7 +435,6 @@ enum phydm_api_e {
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};
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/*2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY*/
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enum odm_ability_e {
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@ -476,7 +466,6 @@ enum odm_ability_e {
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};
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/*ODM_CMNINFO_ONE_PATH_CCA*/
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enum odm_cca_path_e {
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ODM_CCA_2R = 0,
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@ -490,7 +479,6 @@ enum cca_pathdiv_en_e {
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};
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enum phy_reg_pg_type {
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PHY_REG_PG_RELATIVE_VALUE = 0,
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PHY_REG_PG_EXACT_VALUE = 1
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@ -498,15 +486,7 @@ enum phy_reg_pg_type {
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/*2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration.*/
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#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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#if (RT_PLATFORM != PLATFORM_LINUX)
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typedef
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#endif
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struct PHY_DM_STRUCT
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#else/*for AP,ADSL,CE Team*/
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struct PHY_DM_STRUCT
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#endif
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{
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/*Add for different team use temporarily*/
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struct _ADAPTER *adapter; /*For CE/NIC team*/
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@ -514,14 +494,7 @@ enum phy_reg_pg_type {
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/*WHen you use adapter or priv pointer, you must make sure the pointer is ready.*/
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bool odm_ready;
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#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
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struct rtl8192cd_priv fake_priv;
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#endif
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#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
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/* ADSL_AP_BUILD_WORKAROUND */
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struct _ADAPTER fake_adapter;
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#endif
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enum phy_reg_pg_type phy_reg_pg_value_type;
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u8 phy_reg_pg_version;
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@ -542,7 +515,6 @@ enum phy_reg_pg_type {
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u8 control_channel;
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/*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
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/* 1 COMMON INFORMATION */
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/*Init value*/
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@ -940,19 +912,7 @@ enum phy_reg_pg_type {
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u32 radar_detect_reg_924;
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/*====== phydm_radar_detect_with_dbg_parm end ======*/
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#endif
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#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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#if (RT_PLATFORM != PLATFORM_LINUX)
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}; /*DM_Dynamic_Mechanism_Structure*/
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#else
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};
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#endif
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#else /*for AP,ADSL,CE Team*/
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};
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#endif
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enum phydm_structure_type {
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PHYDM_FALSEALMCNT,
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@ -962,8 +922,6 @@ enum phydm_structure_type {
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};
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enum odm_rf_content {
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odm_radioa_txt = 0x1000,
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odm_radiob_txt = 0x1001,
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@ -1081,7 +1039,6 @@ odm_dm_watchdog_lps(
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);
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#endif
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s32
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odm_pwdb_conversion(
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s32 X,
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@ -1105,7 +1062,6 @@ phydm_txcurrentcalibration(
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struct PHY_DM_STRUCT *p_dm_odm
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);
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void
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phydm_seq_sorting(
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void *p_dm_void,
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@ -1221,7 +1177,6 @@ odm_release_all_timers(
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struct PHY_DM_STRUCT *p_dm_odm
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);
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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void odm_init_all_work_items(struct PHY_DM_STRUCT *p_dm_odm);
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void odm_free_all_work_items(struct PHY_DM_STRUCT *p_dm_odm);
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@ -1259,7 +1214,6 @@ odm_asoc_entry_init(
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struct PHY_DM_STRUCT *p_dm_odm
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);
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void *
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phydm_get_structure(
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struct PHY_DM_STRUCT *p_dm_odm,
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@ -1277,7 +1231,6 @@ phydm_get_structure(
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#define IS_HARDWARE_TYPE_8192D(_adapter) false
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#define RF_T_METER_92D 0x42
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#define GET_RX_STATUS_DESC_RX_MCS(__prx_status_desc) LE_BITS_TO_1BYTE(__prx_status_desc+12, 0, 6)
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#define REG_CONFIG_RAM64X16 0xb2c
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@ -1295,10 +1248,8 @@ phydm_get_structure(
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void odm_dtc(struct PHY_DM_STRUCT *p_dm_odm);
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#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
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void phydm_noisy_detection(struct PHY_DM_STRUCT *p_dm_odm);
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#endif
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void
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@ -28,7 +28,6 @@
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#define READ_AND_CONFIG_MP(ic, txt) (odm_read_and_config_mp_##ic##txt(p_dm_odm))
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#define READ_AND_CONFIG_TC(ic, txt) (odm_read_and_config_tc_##ic##txt(p_dm_odm))
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#if (PHYDM_TESTCHIP_SUPPORT == 1)
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#define READ_AND_CONFIG(ic, txt) do {\
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if (p_dm_odm->is_mp_chip)\
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@ -40,7 +39,6 @@
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#define READ_AND_CONFIG READ_AND_CONFIG_MP
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#endif
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#define READ_FIRMWARE_MP(ic, txt) (odm_read_firmware_mp_##ic##txt(p_dm_odm, p_firmware, p_size))
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#define READ_FIRMWARE_TC(ic, txt) (odm_read_firmware_tc_##ic##txt(p_dm_odm, p_firmware, p_size))
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@ -77,7 +75,6 @@ odm_query_rx_pwr_percentage(
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return 100 + ant_power;
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}
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/*
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* 2012/01/12 MH MOve some signal strength smooth method to MP HAL layer.
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* IF other SW team do not support the feature, remove this section.??
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@ -158,7 +155,6 @@ odm_signal_scale_mapping_92c_series_patch_rt_cid_819x_netcore(
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return ret_sig;
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}
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s32
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odm_signal_scale_mapping_92c_series(
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struct PHY_DM_STRUCT *p_dm_odm,
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@ -242,8 +238,6 @@ odm_signal_scale_mapping(
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}
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static u8 odm_sq_process_patch_rt_cid_819x_lenovo(
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struct PHY_DM_STRUCT *p_dm_odm,
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u8 is_cck_rate,
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@ -382,8 +376,6 @@ static u8 odm_sq_process_patch_rt_cid_819x_acer(
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SQ = 20;
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#endif
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} else {
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/* OFDM rate */
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@ -659,7 +651,6 @@ odm_rx_phy_status92c_series_parsing(
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p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = -1;
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p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1;
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if (is_cck_rate) {
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p_dm_odm->phy_dbg_info.num_qry_phy_status_cck++;
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cck_agc_rpt = p_phy_sta_rpt->cck_agc_rpt_ofdm_cfosho_a ;
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@ -832,7 +823,6 @@ odm_rx_phy_status92c_series_parsing(
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}
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}
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/* */
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/* (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) */
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/* */
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@ -840,7 +830,6 @@ odm_rx_phy_status92c_series_parsing(
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PWDB_ALL_BT = PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all);
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p_phy_info->rx_pwdb_all = PWDB_ALL;
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/* ODM_RT_TRACE(p_dm_odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",p_phy_info->rx_pwdb_all)); */
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
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@ -1200,7 +1189,6 @@ odm_rx_phy_status_jaguar_series_parsing(
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p_phy_info->rx_mimo_signal_strength[i] = (u8) RSSI;
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/*Get Rx snr value in DB*/
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if (i < ODM_RF_PATH_C)
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p_phy_info->rx_snr[i] = p_dm_odm->phy_dbg_info.rx_snr_db[i] = p_phy_sta_rpt->rxsnr[i] / 2;
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@ -1356,7 +1344,6 @@ odm_rx_phy_status_jaguar_series_parsing(
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p_dm_odm->dm_fat_table.antsel_rx_keep_3 = p_phy_sta_rpt->antidx_antd;
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/*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antidx_anta = ((%d)), MatchBSSID = ((%d))\n", p_pktinfo->station_id, p_phy_sta_rpt->antidx_anta, p_pktinfo->is_packet_match_bssid));*/
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/* dbg_print("p_phy_sta_rpt->antidx_anta = %d, p_phy_sta_rpt->antidx_antb = %d\n",*/
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/* p_phy_sta_rpt->antidx_anta, p_phy_sta_rpt->antidx_antb);*/
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/* dbg_print("----------------------------\n");*/
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@ -1403,7 +1390,6 @@ phydm_reset_rssi_for_dm(
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}
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ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("Reset RSSI for macid = (( %d ))\n", station_id));
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p_entry->rssi_stat.undecorated_smoothed_cck = -1;
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p_entry->rssi_stat.undecorated_smoothed_ofdm = -1;
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p_entry->rssi_stat.undecorated_smoothed_pwdb = -1;
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@ -1690,7 +1676,6 @@ odm_process_rssi_for_dm(
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}
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}
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if ((p_entry->rssi_stat.ofdm_pkt >= 1 || p_entry->rssi_stat.cck_pkt >= 5) && (p_entry->rssi_stat.is_send_rssi == RA_RSSI_STATE_INIT)) {
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send_rssi_2_fw = 1;
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@ -1701,8 +1686,6 @@ odm_process_rssi_for_dm(
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p_entry->rssi_stat.undecorated_smoothed_ofdm = undecorated_smoothed_ofdm;
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p_entry->rssi_stat.undecorated_smoothed_pwdb = undecorated_smoothed_pwdb;
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if (send_rssi_2_fw) { /* Trigger init rate by RSSI */
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if (p_entry->rssi_stat.ofdm_pkt != 0)
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@ -1716,7 +1699,6 @@ odm_process_rssi_for_dm(
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#endif
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}
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/*in WIN Driver: sta_ID==0->p_entry==NULL -> default port HAL_Data*/
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
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@ -1735,7 +1717,6 @@ odm_process_rssi_for_dm(
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}
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}
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#if (ODM_IC_11N_SERIES_SUPPORT == 1)
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/*
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* Endianness before calling this API
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@ -1753,7 +1734,6 @@ odm_phy_status_query_92c_series(
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}
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#endif
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/*
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* Endianness before calling this API
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* */
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@ -1890,7 +1870,6 @@ phydm_normal_driver_rx_sniffer(
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));
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}
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#endif
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}
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#endif
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@ -1936,7 +1915,6 @@ odm_mac_status_query(
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}
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/*
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* If you want to add a new IC, Please follow below template and generate a new one.
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*
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@ -2153,7 +2131,6 @@ odm_config_rf_with_tx_pwr_track_header_file(
|
|||
("p_dm_odm->support_platform: 0x%X, p_dm_odm->support_interface: 0x%X, p_dm_odm->board_type: 0x%X\n",
|
||||
p_dm_odm->support_platform, p_dm_odm->support_interface, p_dm_odm->board_type));
|
||||
|
||||
|
||||
/* 1 AP doesn't use PHYDM power tracking table in these ICs */
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
|
||||
#if RTL8821A_SUPPORT
|
||||
|
|
@ -2324,7 +2301,6 @@ odm_config_bb_with_header_file(
|
|||
#endif
|
||||
|
||||
/* 1 AP doesn't use PHYDM initialization in these ICs */
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
|
||||
#if (RTL8812A_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8812) {
|
||||
if (config_type == CONFIG_BB_PHY_REG)
|
||||
|
|
@ -2334,20 +2310,6 @@ odm_config_bb_with_header_file(
|
|||
else if (config_type == CONFIG_BB_PHY_REG_PG) {
|
||||
if (p_dm_odm->rfe_type == 3 && p_dm_odm->is_mp_chip)
|
||||
READ_AND_CONFIG_MP(8812a, _phy_reg_pg_asus);
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
else if (p_mgnt_info->CustomerID == RT_CID_WNC_NEC && p_dm_odm->is_mp_chip)
|
||||
READ_AND_CONFIG_MP(8812a, _phy_reg_pg_nec);
|
||||
#if RT_PLATFORM == PLATFORM_MACOSX
|
||||
/*{1827}{1024} for BUFFALO power by rate table. Isaiah 2013-11-29*/
|
||||
else if (p_mgnt_info->CustomerID == RT_CID_DNI_BUFFALO)
|
||||
READ_AND_CONFIG_MP(8812a, _phy_reg_pg_dni);
|
||||
/* TP-Link T4UH, Isaiah 2015-03-16*/
|
||||
else if (p_mgnt_info->CustomerID == RT_CID_TPLINK_HPWR) {
|
||||
dbg_print("RT_CID_TPLINK_HPWR:: _PHY_REG_PG_TPLINK\n");
|
||||
READ_AND_CONFIG_MP(8812a, _phy_reg_pg_tplink);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
else
|
||||
READ_AND_CONFIG_MP(8812a, _phy_reg_pg);
|
||||
} else if (config_type == CONFIG_BB_PHY_REG_MP)
|
||||
|
|
@ -2361,7 +2323,6 @@ odm_config_bb_with_header_file(
|
|||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8812AGCTABArray\n"));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8812PHY_REGArray\n"));
|
||||
}
|
||||
#endif
|
||||
#if (RTL8821A_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8821) {
|
||||
if (config_type == CONFIG_BB_PHY_REG)
|
||||
|
|
@ -2369,25 +2330,6 @@ odm_config_bb_with_header_file(
|
|||
else if (config_type == CONFIG_BB_AGC_TAB)
|
||||
READ_AND_CONFIG_MP(8821a, _agc_tab);
|
||||
else if (config_type == CONFIG_BB_PHY_REG_PG) {
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
|
||||
if ((p_hal_data->EEPROMSVID == 0x1043 && p_hal_data->EEPROMSMID == 0x207F))
|
||||
READ_AND_CONFIG_MP(8821a, _phy_reg_pg_e202_sa);
|
||||
else
|
||||
#endif
|
||||
#if (RT_PLATFORM == PLATFORM_MACOSX)
|
||||
/*{1827}{1022} for BUFFALO power by rate table. Isaiah 2013-10-18*/
|
||||
if (p_mgnt_info->CustomerID == RT_CID_DNI_BUFFALO) {
|
||||
/*{1024} for BUFFALO power by rate table. (JP/US)*/
|
||||
if (p_mgnt_info->channel_plan == RT_CHANNEL_DOMAIN_US_2G_CANADA_5G)
|
||||
READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_us);
|
||||
else
|
||||
READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_jp);
|
||||
} else
|
||||
#endif
|
||||
#endif
|
||||
READ_AND_CONFIG_MP(8821a, _phy_reg_pg);
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8821AGCTABArray\n"));
|
||||
|
|
@ -2416,7 +2358,6 @@ odm_config_bb_with_header_file(
|
|||
#endif
|
||||
#endif/* (DM_ODM_SUPPORT_TYPE != ODM_AP) */
|
||||
|
||||
|
||||
/* 1 All platforms support */
|
||||
#if (RTL8188E_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8188E) {
|
||||
|
|
@ -3009,7 +2950,6 @@ phydm_set_per_path_phy_info(
|
|||
evm_percentage = (evm_dbm << 1) + (evm_dbm);
|
||||
}
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
p_phy_info->rx_pwr[rx_path] = rx_pwr;
|
||||
p_phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm;
|
||||
|
|
@ -3023,16 +2963,6 @@ phydm_set_per_path_phy_info(
|
|||
p_phy_info->rx_mimo_signal_strength[rx_path] = odm_query_rx_pwr_percentage(rx_pwr);
|
||||
p_phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage;
|
||||
p_phy_info->rx_snr[rx_path] = rx_snr >> 1;
|
||||
|
||||
#if 0
|
||||
/* if (p_pktinfo->is_packet_match_bssid) */
|
||||
{
|
||||
dbg_print("path (%d)--------\n", rx_path);
|
||||
dbg_print("rx_pwr = %d, Signal strength = %d\n", p_phy_info->rx_pwr[rx_path], p_phy_info->rx_mimo_signal_strength[rx_path]);
|
||||
dbg_print("evm_dbm = %d, Signal quality = %d\n", p_phy_info->rx_mimo_evm_dbm[rx_path], p_phy_info->rx_mimo_signal_quality[rx_path]);
|
||||
dbg_print("CFO = %d, SNR = %d\n", p_phy_info->cfo_tail[rx_path], p_phy_info->rx_snr[rx_path]);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -3058,16 +2988,6 @@ phydm_set_common_phy_info(
|
|||
p_phy_info->rx_pwdb_all = odm_query_rx_pwr_percentage(rx_power); /* RSSI in percentage */
|
||||
p_phy_info->signal_quality = signal_quality; /* signal quality */
|
||||
p_phy_info->band_width = bandwidth; /* bandwidth */
|
||||
|
||||
#if 0
|
||||
/* if (p_pktinfo->is_packet_match_bssid) */
|
||||
{
|
||||
dbg_print("rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\n", p_phy_info->rx_pwdb_all, p_phy_info->rx_power, p_phy_info->recv_signal_power);
|
||||
dbg_print("signal_quality = %d\n", p_phy_info->signal_quality);
|
||||
dbg_print("is_beamformed = %d, is_mu_packet = %d, rx_count = %d\n", p_phy_info->is_beamformed, p_phy_info->is_mu_packet, p_phy_info->rx_count + 1);
|
||||
dbg_print("channel = %d, rxsc = %d, band_width = %d\n", channel, rxsc, bandwidth);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -3084,7 +3004,6 @@ phydm_get_rx_phy_status_type0(
|
|||
u8 i, SQ = 0;
|
||||
s8 rx_power = p_phy_sta_rpt->pwdb - 110;
|
||||
|
||||
|
||||
#if (RTL8723D_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8723D)
|
||||
rx_power = p_phy_sta_rpt->pwdb - 97;
|
||||
|
|
@ -3152,19 +3071,6 @@ phydm_get_rx_phy_status_type0(
|
|||
p_dm_odm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->antidx_b;
|
||||
p_dm_odm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antidx_c;
|
||||
p_dm_odm->dm_fat_table.antsel_rx_keep_3 = p_phy_sta_rpt->antidx_d;
|
||||
#if 0
|
||||
/* if (p_pktinfo->is_packet_match_bssid) */
|
||||
{
|
||||
dbg_print("pwdb = 0x%x, MP gain index = 0x%x, TRSW = 0x%x\n", p_phy_sta_rpt->pwdb, p_phy_sta_rpt->gain, p_phy_sta_rpt->trsw);
|
||||
dbg_print("channel = %d, band = %d, rxsc = %d\n", p_phy_sta_rpt->channel, p_phy_sta_rpt->band, p_phy_sta_rpt->rxsc);
|
||||
dbg_print("agc_table = 0x%x, agc_rpt 0x%x, bb_power = 0x%x\n", p_phy_sta_rpt->agc_table, p_phy_sta_rpt->agc_rpt, p_phy_sta_rpt->bb_power);
|
||||
dbg_print("length = %d, SQ = %d\n", p_phy_sta_rpt->length, p_phy_sta_rpt->signal_quality);
|
||||
dbg_print("antidx a = 0x%x, b = 0x%x, c = 0x%x, d = 0x%x\n", p_phy_sta_rpt->antidx_a, p_phy_sta_rpt->antidx_b, p_phy_sta_rpt->antidx_c, p_phy_sta_rpt->antidx_d);
|
||||
dbg_print("rsvd_0 = 0x%x, rsvd_1 = 0x%x, rsvd_2 = 0x%x\n", p_phy_sta_rpt->rsvd_0, p_phy_sta_rpt->rsvd_1, p_phy_sta_rpt->rsvd_2);
|
||||
dbg_print("rsvd_3 = 0x%x, rsvd_4 = 0x%x, rsvd_5 = 0x%x\n", p_phy_sta_rpt->rsvd_3, p_phy_sta_rpt->rsvd_4, p_phy_sta_rpt->rsvd_5);
|
||||
dbg_print("rsvd_6 = 0x%x, rsvd_7 = 0x%x, rsvd_8 = 0x%x\n", p_phy_sta_rpt->rsvd_6, p_phy_sta_rpt->rsvd_7, p_phy_sta_rpt->rsvd_8);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -3368,24 +3274,6 @@ phydm_get_rx_phy_status_type2(
|
|||
phydm_set_common_phy_info(rx_pwr_db, p_phy_sta_rpt->channel, (bool)p_phy_sta_rpt->beamformed,
|
||||
false, bw, 0, rxsc, p_phy_info);
|
||||
|
||||
#if 0
|
||||
/* if (p_pktinfo->is_packet_match_bssid) */
|
||||
{
|
||||
dbg_print("channel = %d, band = %d, l_rxsc = %d, ht_rxsc = %d\n", p_phy_sta_rpt->channel, p_phy_sta_rpt->band, p_phy_sta_rpt->l_rxsc, p_phy_sta_rpt->ht_rxsc);
|
||||
dbg_print("pwdb A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->pwdb[0], p_phy_sta_rpt->pwdb[1], p_phy_sta_rpt->pwdb[2], p_phy_sta_rpt->pwdb[3]);
|
||||
dbg_print("Agc table A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->agc_table_a, p_phy_sta_rpt->agc_table_b, p_phy_sta_rpt->agc_table_c, p_phy_sta_rpt->agc_table_d);
|
||||
dbg_print("Gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->gain_a, p_phy_sta_rpt->gain_b, p_phy_sta_rpt->gain_c, p_phy_sta_rpt->gain_d);
|
||||
dbg_print("TRSW A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->trsw_a, p_phy_sta_rpt->trsw_b, p_phy_sta_rpt->trsw_c, p_phy_sta_rpt->trsw_d);
|
||||
dbg_print("AAGC step A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->aagc_step_a, p_phy_sta_rpt->aagc_step_b, p_phy_sta_rpt->aagc_step_c, p_phy_sta_rpt->aagc_step_d);
|
||||
dbg_print("HT AAGC gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->ht_aagc_gain[0], p_phy_sta_rpt->ht_aagc_gain[1], p_phy_sta_rpt->ht_aagc_gain[2], p_phy_sta_rpt->ht_aagc_gain[3]);
|
||||
dbg_print("DAGC gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->dagc_gain[0], p_phy_sta_rpt->dagc_gain[1], p_phy_sta_rpt->dagc_gain[2], p_phy_sta_rpt->dagc_gain[3]);
|
||||
dbg_print("ldpc: %d, stbc: %d, bf: %d, gnt_bt: %d, antsw: %d\n", p_phy_sta_rpt->ldpc, p_phy_sta_rpt->stbc, p_phy_sta_rpt->beamformed, p_phy_sta_rpt->gnt_bt, p_phy_sta_rpt->hw_antsw_occu);
|
||||
dbg_print("counter: %d, syn_count: %d\n", p_phy_sta_rpt->counter, p_phy_sta_rpt->syn_count);
|
||||
dbg_print("cnt_cca2agc_rdy: %d, cnt_pw2cca: %d, shift_l_map\n", p_phy_sta_rpt->cnt_cca2agc_rdy, p_phy_sta_rpt->cnt_pw2cca, p_phy_sta_rpt->shift_l_map);
|
||||
dbg_print("rsvd_0 = %d, rsvd_1 = %d, rsvd_2 = %d, rsvd_3 = %d, rsvd_4 = %d, rsvd_5 = %d\n", p_phy_sta_rpt->rsvd_0, p_phy_sta_rpt->rsvd_1, p_phy_sta_rpt->rsvd_2, p_phy_sta_rpt->rsvd_3, p_phy_sta_rpt->rsvd_4);
|
||||
dbg_print("rsvd_5 = %d, rsvd_6 = %d, rsvd_6 = %d\n", p_phy_sta_rpt->rsvd_5, p_phy_sta_rpt->rsvd_6, p_phy_sta_rpt->rsvd_7);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -3393,15 +3281,6 @@ phydm_get_rx_phy_status_type5(
|
|||
u8 *p_phy_status
|
||||
)
|
||||
{
|
||||
/*
|
||||
dbg_print("DW0: 0x%02x%02x%02x%02x\n", *(p_phy_status + 3), *(p_phy_status + 2), *(p_phy_status + 1), *(p_phy_status + 0));
|
||||
dbg_print("DW1: 0x%02x%02x%02x%02x\n", *(p_phy_status + 7), *(p_phy_status + 6), *(p_phy_status + 5), *(p_phy_status + 4));
|
||||
dbg_print("DW2: 0x%02x%02x%02x%02x\n", *(p_phy_status + 11), *(p_phy_status + 10), *(p_phy_status + 9), *(p_phy_status + 8));
|
||||
dbg_print("DW3: 0x%02x%02x%02x%02x\n", *(p_phy_status + 15), *(p_phy_status + 14), *(p_phy_status + 13), *(p_phy_status + 12));
|
||||
dbg_print("DW4: 0x%02x%02x%02x%02x\n", *(p_phy_status + 19), *(p_phy_status + 18), *(p_phy_status + 17), *(p_phy_status + 16));
|
||||
dbg_print("DW5: 0x%02x%02x%02x%02x\n", *(p_phy_status + 23), *(p_phy_status + 22), *(p_phy_status + 21), *(p_phy_status + 20));
|
||||
dbg_print("DW6: 0x%02x%02x%02x%02x\n", *(p_phy_status + 27), *(p_phy_status + 26), *(p_phy_status + 25), *(p_phy_status + 24));
|
||||
*/
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -3513,27 +3392,14 @@ phydm_rx_phy_status_new_type(
|
|||
/* Phy status parsing */
|
||||
switch (phy_status_type) {
|
||||
case 0:
|
||||
{
|
||||
phydm_get_rx_phy_status_type0(p_phydm, p_phy_status, p_pktinfo, p_phy_info);
|
||||
break;
|
||||
}
|
||||
case 1:
|
||||
{
|
||||
phydm_get_rx_phy_status_type1(p_phydm, p_phy_status, p_pktinfo, p_phy_info);
|
||||
break;
|
||||
}
|
||||
case 2:
|
||||
{
|
||||
phydm_get_rx_phy_status_type2(p_phydm, p_phy_status, p_pktinfo, p_phy_info);
|
||||
break;
|
||||
}
|
||||
#if 0
|
||||
case 5:
|
||||
{
|
||||
phydm_get_rx_phy_status_type5(p_phy_status);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -124,37 +124,8 @@ void do_iqk_8188e(
|
|||
|
||||
odm_reset_iqk_result(p_dm_odm);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
|
||||
#if USE_WORKITEM
|
||||
platform_acquire_mutex(&p_hal_data->mx_chnl_bw_control);
|
||||
#else
|
||||
platform_acquire_spin_lock(adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK);
|
||||
#endif
|
||||
#elif ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
|
||||
platform_acquire_mutex(&p_hal_data->mx_chnl_bw_control);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
p_dm_odm->rf_calibrate_info.thermal_value_iqk = thermal_value;
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
phy_iq_calibrate_8188e(p_dm_odm, false);
|
||||
#else
|
||||
phy_iq_calibrate_8188e(adapter, false);
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
|
||||
#if USE_WORKITEM
|
||||
platform_release_mutex(&p_hal_data->mx_chnl_bw_control);
|
||||
#else
|
||||
platform_release_spin_lock(adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK);
|
||||
#endif
|
||||
#elif ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
|
||||
platform_release_mutex(&p_hal_data->mx_chnl_bw_control);
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
|
|
@ -359,18 +330,7 @@ phy_path_a_iqk_8188e(
|
|||
RESTORE_INT(x);
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
if (!(reg_eac & BIT(27)) && /* if Tx is OK, check whether Rx is OK */
|
||||
(((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
|
||||
(((reg_eac & 0x03FF0000) >> 16) != 0x36))
|
||||
result |= 0x02;
|
||||
else
|
||||
RTPRINT(FINIT, INIT_IQK, ("path A Rx IQK fail!!\n"));
|
||||
#endif
|
||||
|
||||
return result;
|
||||
|
||||
|
||||
}
|
||||
|
||||
u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
|
||||
|
|
@ -519,15 +479,6 @@ phy_path_a_rx_iqk(
|
|||
reg_ea4 = odm_get_bb_reg(p_dm_odm, REG_RX_POWER_BEFORE_IQK_A_2, MASKDWORD);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", reg_ea4));
|
||||
|
||||
#if 0
|
||||
if (!(reg_eac & BIT(28)) &&
|
||||
(((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
|
||||
(((reg_e9c & 0x03FF0000) >> 16) != 0x42))
|
||||
result |= 0x01;
|
||||
else /* if Tx not OK, ignore Rx */
|
||||
return result;
|
||||
#endif
|
||||
|
||||
if (!(reg_eac & BIT(27)) && /* if Tx is OK, check whether Rx is OK */
|
||||
(((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
|
||||
(((reg_eac & 0x03FF0000) >> 16) != 0x36))
|
||||
|
|
@ -750,36 +701,6 @@ _phy_path_b_fill_iqk_matrix(
|
|||
* 2011/07/26 MH Add an API for testing IQK fail case.
|
||||
*
|
||||
* MP Already declare in odm.c */
|
||||
#if 0 /* !(DM_ODM_SUPPORT_TYPE & ODM_WIN) */ /* 0824 */
|
||||
bool
|
||||
odm_check_power_status(
|
||||
struct _ADAPTER *adapter)
|
||||
{
|
||||
#if 0
|
||||
/* HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); */
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
RT_RF_POWER_STATE rt_state;
|
||||
PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo);
|
||||
|
||||
/* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */
|
||||
if (p_mgnt_info->init_adpt_in_progress == true) {
|
||||
ODM_RT_TRACE(p_dm_odm, COMP_INIT, DBG_LOUD, ("odm_check_power_status Return true, due to initadapter"));
|
||||
return true;
|
||||
}
|
||||
|
||||
/* */
|
||||
/* 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. */
|
||||
/* */
|
||||
phydm_get_hw_reg_interface(p_dm_odm, HW_VAR_RF_STATE, (u8 *)(&rt_state));
|
||||
if (adapter->is_driver_stopped || adapter->is_driver_is_going_to_pnp_set_power_sleep || rt_state == eRfOff) {
|
||||
ODM_RT_TRACE(p_dm_odm, COMP_INIT, DBG_LOUD, ("odm_check_power_status Return false, due to %d/%d/%d\n",
|
||||
adapter->is_driver_stopped, adapter->is_driver_is_going_to_pnp_set_power_sleep, rt_state));
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
return true;
|
||||
}
|
||||
#endif
|
||||
|
||||
void
|
||||
_phy_save_adda_registers(
|
||||
|
|
@ -1270,22 +1191,10 @@ _phy_iq_calibrate_8188e(
|
|||
result[t][1] = (odm_get_bb_reg(p_dm_odm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
|
||||
break;
|
||||
}
|
||||
#if 0
|
||||
else if (i == (retry_count - 1) && path_aok == 0x01) { /* Tx IQK OK */
|
||||
RTPRINT(FINIT, INIT_IQK, ("path A IQK Only Tx Success!!\n"));
|
||||
|
||||
result[t][0] = (odm_get_bb_reg(p_dm_odm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
|
||||
result[t][1] = (odm_get_bb_reg(p_dm_odm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
for (i = 0 ; i < retry_count ; i++) {
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
path_aok = phy_path_a_rx_iqk(p_adapter, is2T);
|
||||
#else
|
||||
path_aok = phy_path_a_rx_iqk(p_dm_odm, is2T);
|
||||
#endif
|
||||
if (path_aok == 0x03) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A Rx IQK Success!!\n"));
|
||||
/* result[t][0] = (odm_get_bb_reg(p_dm_odm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD)&0x3FF0000)>>16;
|
||||
|
|
@ -1297,32 +1206,17 @@ _phy_iq_calibrate_8188e(
|
|||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A Rx IQK Fail!!\n"));
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
SAVE_INT_AND_CLI(x);
|
||||
#endif
|
||||
|
||||
if (0x00 == path_aok)
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A IQK failed!!\n"));
|
||||
|
||||
if (is2T) {
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
_phy_path_a_stand_by(p_adapter);
|
||||
|
||||
/* Turn path B ADDA on */
|
||||
_phy_path_adda_on(p_adapter, ADDA_REG, false, is2T);
|
||||
#else
|
||||
_phy_path_a_stand_by(p_dm_odm);
|
||||
|
||||
/* Turn path B ADDA on */
|
||||
_phy_path_adda_on(p_dm_odm, ADDA_REG, false, is2T);
|
||||
#endif
|
||||
|
||||
for (i = 0 ; i < retry_count ; i++) {
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
path_bok = phy_path_b_iqk_8188e(p_adapter);
|
||||
#else
|
||||
path_bok = phy_path_b_iqk_8188e(p_dm_odm);
|
||||
#endif
|
||||
if (path_bok == 0x03) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B IQK Success!!\n"));
|
||||
result[t][4] = (odm_get_bb_reg(p_dm_odm, REG_TX_POWER_BEFORE_IQK_B, MASKDWORD) & 0x3FF0000) >> 16;
|
||||
|
|
@ -2054,19 +1948,6 @@ phy_iq_calibrate_8188e(
|
|||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n"));
|
||||
priv->pshare->IQK_total_cnt++;
|
||||
#if 0/* Suggested by Edlu,120413 */
|
||||
|
||||
/* IQK on channel 7, should switch back when completed. */
|
||||
/* origin_channel = p_hal_data->current_channel; */
|
||||
origin_channel = *(p_dm_odm->p_channel);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
p_adapter->hal_func.sw_chnl_by_timer_handler(p_adapter, channel_to_iqk);
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
p_adapter->hal_func.set_channel_handler(p_adapter, channel_to_iqk);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
for (i = 0; i < 8; i++) {
|
||||
result[0][i] = 0;
|
||||
|
|
@ -2083,27 +1964,15 @@ phy_iq_calibrate_8188e(
|
|||
|
||||
|
||||
for (i = 0; i < 3; i++) {
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
|
||||
if (IS_92C_SERIAL(p_hal_data->version_id))
|
||||
_phy_iq_calibrate_8188e(p_adapter, result, i, true);
|
||||
else
|
||||
#endif
|
||||
{
|
||||
else {
|
||||
/* For 88C 1T1R */
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
_phy_iq_calibrate_8188e(p_adapter, result, i, false);
|
||||
#else
|
||||
_phy_iq_calibrate_8188e(p_dm_odm, result, i, false);
|
||||
#endif
|
||||
}
|
||||
|
||||
if (i == 1) {
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
is12simular = phy_simularity_compare_8188e(p_adapter, result, 0, 1);
|
||||
#else
|
||||
is12simular = phy_simularity_compare_8188e(p_dm_odm, result, 0, 1);
|
||||
#endif
|
||||
if (is12simular) {
|
||||
final_candidate = 0;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n", final_candidate));
|
||||
|
|
@ -2181,11 +2050,7 @@ phy_iq_calibrate_8188e(
|
|||
}
|
||||
|
||||
if ((rege94 != 0)/*&&(regea4 != 0)*/) {
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
_phy_path_a_fill_iqk_matrix(p_adapter, is_patha_ok, result, final_candidate, (regea4 == 0));
|
||||
#else
|
||||
_phy_path_a_fill_iqk_matrix(p_dm_odm, is_patha_ok, result, final_candidate, (regea4 == 0));
|
||||
#endif
|
||||
}
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
|
|
@ -2195,11 +2060,7 @@ phy_iq_calibrate_8188e(
|
|||
}
|
||||
#endif
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
indexforchannel = odm_get_right_chnl_place_for_iqk(*p_dm_odm->p_channel);
|
||||
#else
|
||||
indexforchannel = 0;
|
||||
#endif
|
||||
|
||||
/* To Fix BSOD when final_candidate is 0xff
|
||||
* by sherry 20120321 */
|
||||
|
|
@ -2210,57 +2071,25 @@ phy_iq_calibrate_8188e(
|
|||
}
|
||||
/* RTPRINT(FINIT, INIT_IQK, ("\nIQK OK indexforchannel %d.\n", indexforchannel)); */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK indexforchannel %d.\n", indexforchannel));
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
|
||||
_phy_save_adda_registers(p_adapter, IQK_BB_REG_92C, p_dm_odm->rf_calibrate_info.IQK_BB_backup_recover, 9);
|
||||
#else
|
||||
_phy_save_adda_registers(p_dm_odm, IQK_BB_REG_92C, p_dm_odm->rf_calibrate_info.IQK_BB_backup_recover, IQK_BB_REG_NUM);
|
||||
#endif
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n"));
|
||||
#if 0 /* Suggested by Edlu,120413 */
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
p_adapter->hal_func.sw_chnl_by_timer_handler(p_adapter, origin_channel);
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
p_adapter->hal_func.set_channel_handler(p_adapter, origin_channel);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
RESTORE_INT(x);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
phy_lc_calibrate_8188e(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
#else
|
||||
struct _ADAPTER *p_adapter
|
||||
#endif
|
||||
)
|
||||
{
|
||||
bool /*is_start_cont_tx = false,*/ is_single_tone = false, is_carrier_suppression = false;
|
||||
u32 timeout = 2000, timecount = 0;
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#else /* (DM_ODM_SUPPORT_TYPE == ODM_CE) */
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv;
|
||||
#endif
|
||||
|
||||
#if (MP_DRIVER == 1)
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PMPT_CONTEXT p_mpt_ctx = &(p_adapter->mpt_ctx);
|
||||
#else/* (DM_ODM_SUPPORT_TYPE == ODM_CE) */
|
||||
PMPT_CONTEXT p_mpt_ctx = &(p_adapter->mppriv.mpt_ctx);
|
||||
#endif
|
||||
#endif/* (MP_DRIVER == 1) */
|
||||
#endif
|
||||
|
||||
|
|
@ -2338,32 +2167,6 @@ phy_ap_calibrate_8188e(
|
|||
return;
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
|
||||
if (!(p_dm_odm->support_ability & ODM_RF_CALIBRATION))
|
||||
return;
|
||||
#endif
|
||||
|
||||
#if FOR_BRAZIL_PRETEST != 1
|
||||
if (p_dm_odm->rf_calibrate_info.is_ap_kdone)
|
||||
#endif
|
||||
return;
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
if (IS_92C_SERIAL(p_hal_data->version_id))
|
||||
_phy_ap_calibrate_8188e(p_adapter, delta, true);
|
||||
else
|
||||
#endif
|
||||
{
|
||||
/* For 88C 1T1R */
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
_phy_ap_calibrate_8188e(p_adapter, delta, false);
|
||||
#else
|
||||
_phy_ap_calibrate_8188e(p_dm_odm, delta, false);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
}
|
||||
void _phy_set_rf_path_switch_8188e(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
|
|
@ -2464,533 +2267,4 @@ void phy_set_rf_path_switch_8188e(
|
|||
}
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
/* digital predistortion */
|
||||
void
|
||||
phy_digital_predistortion(
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct _ADAPTER *p_adapter,
|
||||
#else
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#endif
|
||||
bool is2T
|
||||
)
|
||||
{
|
||||
#if (RT_PLATFORM == PLATFORM_WINDOWS)
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv;
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
u32 tmp_reg, tmp_reg2, index, i;
|
||||
u8 path, pathbound = PATH_NUM;
|
||||
u32 AFE_backup[IQK_ADDA_REG_NUM];
|
||||
u32 AFE_REG[IQK_ADDA_REG_NUM] = {
|
||||
REG_FPGA0_XCD_SWITCH_CONTROL, REG_BLUE_TOOTH,
|
||||
REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
|
||||
REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
|
||||
REG_TX_OFDM_BBON, REG_TX_TO_RX,
|
||||
REG_TX_TO_TX, REG_RX_CCK,
|
||||
REG_RX_OFDM, REG_RX_WAIT_RIFS,
|
||||
REG_RX_TO_RX, REG_STANDBY,
|
||||
REG_SLEEP, REG_PMPD_ANAEN
|
||||
};
|
||||
|
||||
u32 BB_backup[DP_BB_REG_NUM];
|
||||
u32 BB_REG[DP_BB_REG_NUM] = {
|
||||
REG_OFDM_0_TRX_PATH_ENABLE, REG_FPGA0_RFMOD,
|
||||
REG_OFDM_0_TR_MUX_PAR, REG_FPGA0_XCD_RF_INTERFACE_SW,
|
||||
REG_FPGA0_XAB_RF_INTERFACE_SW, REG_FPGA0_XA_RF_INTERFACE_OE,
|
||||
REG_FPGA0_XB_RF_INTERFACE_OE
|
||||
};
|
||||
u32 BB_settings[DP_BB_REG_NUM] = {
|
||||
0x00a05430, 0x02040000, 0x000800e4, 0x22208000,
|
||||
0x0, 0x0, 0x0
|
||||
};
|
||||
|
||||
u32 RF_backup[DP_PATH_NUM][DP_RF_REG_NUM];
|
||||
u32 RF_REG[DP_RF_REG_NUM] = {
|
||||
RF_TXBIAS_A
|
||||
};
|
||||
|
||||
u32 MAC_backup[IQK_MAC_REG_NUM];
|
||||
u32 MAC_REG[IQK_MAC_REG_NUM] = {
|
||||
REG_TXPAUSE, REG_BCN_CTRL,
|
||||
REG_BCN_CTRL_1, REG_GPIO_MUXCFG
|
||||
};
|
||||
|
||||
u32 tx_agc[DP_DPK_NUM][DP_DPK_VALUE_NUM] = {
|
||||
{0x1e1e1e1e, 0x03901e1e},
|
||||
{0x18181818, 0x03901818},
|
||||
{0x0e0e0e0e, 0x03900e0e}
|
||||
};
|
||||
|
||||
u32 AFE_on_off[PATH_NUM] = {
|
||||
0x04db25a4, 0x0b1b25a4
|
||||
}; /* path A on path B off / path A off path B on */
|
||||
|
||||
u8 retry_count = 0;
|
||||
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_digital_predistortion()\n"));
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_digital_predistortion for %s %s\n", (is2T ? "2T2R" : "1T1R")));
|
||||
|
||||
/* save BB default value */
|
||||
for (index = 0; index < DP_BB_REG_NUM; index++)
|
||||
BB_backup[index] = odm_get_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD);
|
||||
|
||||
/* save MAC default value */
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
_phy_save_mac_registers(p_adapter, BB_REG, MAC_backup);
|
||||
#else
|
||||
_phy_save_mac_registers(p_dm_odm, BB_REG, MAC_backup);
|
||||
#endif
|
||||
|
||||
/* save RF default value */
|
||||
for (path = 0; path < DP_PATH_NUM; path++) {
|
||||
for (index = 0; index < DP_RF_REG_NUM; index++)
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
RF_backup[path][index] = phy_query_rf_reg(p_adapter, path, RF_REG[index], MASKDWORD);
|
||||
#else
|
||||
RF_backup[path][index] = odm_get_rf_reg(p_adapter, path, RF_REG[index], MASKDWORD);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* save AFE default value */
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
_phy_save_adda_registers(p_adapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
|
||||
#else
|
||||
_phy_save_adda_registers(p_dm_odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
|
||||
#endif
|
||||
|
||||
/* path A/B AFE all on */
|
||||
for (index = 0; index < IQK_ADDA_REG_NUM ; index++)
|
||||
odm_set_bb_reg(p_dm_odm, AFE_REG[index], MASKDWORD, 0x6fdb25a4);
|
||||
|
||||
/* BB register setting */
|
||||
for (index = 0; index < DP_BB_REG_NUM; index++) {
|
||||
if (index < 4)
|
||||
odm_set_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD, BB_settings[index]);
|
||||
else if (index == 4)
|
||||
odm_set_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD, BB_backup[index] | BIT(10) | BIT(26));
|
||||
else
|
||||
odm_set_bb_reg(p_dm_odm, BB_REG[index], BIT(10), 0x00);
|
||||
}
|
||||
|
||||
/* MAC register setting */
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
_phy_mac_setting_calibration(p_adapter, MAC_REG, MAC_backup);
|
||||
#else
|
||||
_phy_mac_setting_calibration(p_dm_odm, MAC_REG, MAC_backup);
|
||||
#endif
|
||||
|
||||
/* PAGE-E IQC setting */
|
||||
odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_A, MASKDWORD, 0x01008c00);
|
||||
odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_A, MASKDWORD, 0x01008c00);
|
||||
odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_B, MASKDWORD, 0x01008c00);
|
||||
odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_B, MASKDWORD, 0x01008c00);
|
||||
|
||||
/* path_A DPK */
|
||||
/* path B to standby mode */
|
||||
odm_set_rf_reg(p_dm_odm, RF_PATH_B, RF_AC, MASKDWORD, 0x10000);
|
||||
|
||||
/* PA gain = 11 & PAD1 => tx_agc 1f ~11 */
|
||||
/* PA gain = 11 & PAD2 => tx_agc 10~0e */
|
||||
/* PA gain = 01 => tx_agc 0b~0d */
|
||||
/* PA gain = 00 => tx_agc 0a~00 */
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x400000);
|
||||
odm_set_bb_reg(p_dm_odm, 0xbc0, MASKDWORD, 0x0005361f);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0);
|
||||
|
||||
/* do inner loopback DPK 3 times */
|
||||
for (i = 0; i < 3; i++) {
|
||||
/* PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 */
|
||||
for (index = 0; index < 3; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0xe00 + index * 4, MASKDWORD, tx_agc[i][0]);
|
||||
odm_set_bb_reg(p_dm_odm, 0xe00 + index * 4, MASKDWORD, tx_agc[i][1]);
|
||||
for (index = 0; index < 4; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0xe10 + index * 4, MASKDWORD, tx_agc[i][0]);
|
||||
|
||||
/* PAGE_B for path-A inner loopback DPK setting */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x02097098);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0xf76d9f84);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x0004ab87);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00880000);
|
||||
|
||||
/* ----send one shot signal---- */
|
||||
/* path A */
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x80047788);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x00047788);
|
||||
ODM_delay_ms(50);
|
||||
}
|
||||
|
||||
/* PA gain = 11 => tx_agc = 1a */
|
||||
for (index = 0; index < 3; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0xe00 + index * 4, MASKDWORD, 0x34343434);
|
||||
odm_set_bb_reg(p_dm_odm, 0xe08 + index * 4, MASKDWORD, 0x03903434);
|
||||
for (index = 0; index < 4; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0xe10 + index * 4, MASKDWORD, 0x34343434);
|
||||
|
||||
/* ==================================== */
|
||||
/* PAGE_B for path-A DPK setting */
|
||||
/* ==================================== */
|
||||
/* open inner loopback @ b00[19]:10 od 0xb00 0x01097018 */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x02017098);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0xf76d9f84);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x0004ab87);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00880000);
|
||||
|
||||
/* rf_lpbk_setup */
|
||||
/* 1.rf 00:5205a, rf 0d:0e52c */
|
||||
odm_set_rf_reg(p_dm_odm, RF_PATH_A, 0x0c, MASKDWORD, 0x8992b);
|
||||
odm_set_rf_reg(p_dm_odm, RF_PATH_A, 0x0d, MASKDWORD, 0x0e52c);
|
||||
odm_set_rf_reg(p_dm_odm, RF_PATH_A, 0x00, MASKDWORD, 0x5205a);
|
||||
|
||||
/* ----send one shot signal---- */
|
||||
/* path A */
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x800477c0);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x000477c0);
|
||||
ODM_delay_ms(50);
|
||||
|
||||
while (retry_count < DP_RETRY_LIMIT && !p_dm_odm->rf_calibrate_info.is_dp_path_aok) {
|
||||
/* ----read back measurement results---- */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x0c297018);
|
||||
tmp_reg = odm_get_bb_reg(p_dm_odm, 0xbe0, MASKDWORD);
|
||||
ODM_delay_ms(10);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x0c29701f);
|
||||
tmp_reg2 = odm_get_bb_reg(p_dm_odm, 0xbe8, MASKDWORD);
|
||||
ODM_delay_ms(10);
|
||||
|
||||
tmp_reg = (tmp_reg & MASKHWORD) >> 16;
|
||||
tmp_reg2 = (tmp_reg2 & MASKHWORD) >> 16;
|
||||
if (tmp_reg < 0xf0 || tmp_reg > 0x105 || tmp_reg2 > 0xff) {
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x02017098);
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x800000);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x800477c0);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x000477c0);
|
||||
ODM_delay_ms(50);
|
||||
retry_count++;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK retry_count %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", retry_count, tmp_reg, tmp_reg2));
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n"));
|
||||
p_dm_odm->rf_calibrate_info.is_dp_path_aok = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
retry_count = 0;
|
||||
|
||||
/* DPP path A */
|
||||
if (p_dm_odm->rf_calibrate_info.is_dp_path_aok) {
|
||||
/* DP settings */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x01017098);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0x776d9f84);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x0004ab87);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00880000);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x400000);
|
||||
|
||||
for (i = REG_PDP_ANT_A; i <= 0xb3c; i += 4) {
|
||||
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x40004000);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i));
|
||||
}
|
||||
|
||||
/* pwsf */
|
||||
odm_set_bb_reg(p_dm_odm, 0xb40, MASKDWORD, 0x40404040);
|
||||
odm_set_bb_reg(p_dm_odm, 0xb44, MASKDWORD, 0x28324040);
|
||||
odm_set_bb_reg(p_dm_odm, 0xb48, MASKDWORD, 0x10141920);
|
||||
|
||||
for (i = 0xb4c; i <= 0xb5c; i += 4)
|
||||
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x0c0c0c0c);
|
||||
|
||||
/* TX_AGC boundary */
|
||||
odm_set_bb_reg(p_dm_odm, 0xbc0, MASKDWORD, 0x0005361f);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0);
|
||||
} else {
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x00000000);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0x00000000);
|
||||
}
|
||||
|
||||
/* DPK path B */
|
||||
if (is2T) {
|
||||
/* path A to standby mode */
|
||||
odm_set_rf_reg(p_dm_odm, RF_PATH_A, RF_AC, MASKDWORD, 0x10000);
|
||||
|
||||
/* LUTs => tx_agc */
|
||||
/* PA gain = 11 & PAD1, => tx_agc 1f ~11 */
|
||||
/* PA gain = 11 & PAD2, => tx_agc 10 ~0e */
|
||||
/* PA gain = 01 => tx_agc 0b ~0d */
|
||||
/* PA gain = 00 => tx_agc 0a ~00 */
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x400000);
|
||||
odm_set_bb_reg(p_dm_odm, 0xbc4, MASKDWORD, 0x0005361f);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0);
|
||||
|
||||
/* do inner loopback DPK 3 times */
|
||||
for (i = 0; i < 3; i++) {
|
||||
/* PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 */
|
||||
for (index = 0; index < 4; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0x830 + index * 4, MASKDWORD, tx_agc[i][0]);
|
||||
for (index = 0; index < 2; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0x848 + index * 4, MASKDWORD, tx_agc[i][0]);
|
||||
for (index = 0; index < 2; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0x868 + index * 4, MASKDWORD, tx_agc[i][0]);
|
||||
|
||||
/* PAGE_B for path-A inner loopback DPK setting */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x02097098);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0xf76d9f84);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x0004ab87);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_B, MASKDWORD, 0x00880000);
|
||||
|
||||
/* ----send one shot signal---- */
|
||||
/* path B */
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x80047788);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x00047788);
|
||||
ODM_delay_ms(50);
|
||||
}
|
||||
|
||||
/* PA gain = 11 => tx_agc = 1a */
|
||||
for (index = 0; index < 4; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0x830 + index * 4, MASKDWORD, 0x34343434);
|
||||
for (index = 0; index < 2; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0x848 + index * 4, MASKDWORD, 0x34343434);
|
||||
for (index = 0; index < 2; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0x868 + index * 4, MASKDWORD, 0x34343434);
|
||||
|
||||
/* PAGE_B for path-B DPK setting */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x02017098);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0xf76d9f84);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x0004ab87);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_B, MASKDWORD, 0x00880000);
|
||||
|
||||
/* RF lpbk switches on */
|
||||
odm_set_bb_reg(p_dm_odm, 0x840, MASKDWORD, 0x0101000f);
|
||||
odm_set_bb_reg(p_dm_odm, 0x840, MASKDWORD, 0x01120103);
|
||||
|
||||
/* path-B RF lpbk */
|
||||
odm_set_rf_reg(p_dm_odm, RF_PATH_B, 0x0c, MASKDWORD, 0x8992b);
|
||||
odm_set_rf_reg(p_dm_odm, RF_PATH_B, 0x0d, MASKDWORD, 0x0e52c);
|
||||
odm_set_rf_reg(p_dm_odm, RF_PATH_B, RF_AC, MASKDWORD, 0x5205a);
|
||||
|
||||
/* ----send one shot signal---- */
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x800477c0);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x000477c0);
|
||||
ODM_delay_ms(50);
|
||||
|
||||
while (retry_count < DP_RETRY_LIMIT && !p_dm_odm->rf_calibrate_info.is_dp_path_bok) {
|
||||
/* ----read back measurement results---- */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x0c297018);
|
||||
tmp_reg = odm_get_bb_reg(p_dm_odm, 0xbf0, MASKDWORD);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x0c29701f);
|
||||
tmp_reg2 = odm_get_bb_reg(p_dm_odm, 0xbf8, MASKDWORD);
|
||||
|
||||
tmp_reg = (tmp_reg & MASKHWORD) >> 16;
|
||||
tmp_reg2 = (tmp_reg2 & MASKHWORD) >> 16;
|
||||
|
||||
if (tmp_reg < 0xf0 || tmp_reg > 0x105 || tmp_reg2 > 0xff) {
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x02017098);
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x800000);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x800477c0);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x000477c0);
|
||||
ODM_delay_ms(50);
|
||||
retry_count++;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK retry_count %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", retry_count, tmp_reg, tmp_reg2));
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n"));
|
||||
p_dm_odm->rf_calibrate_info.is_dp_path_bok = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* DPP path B */
|
||||
if (p_dm_odm->rf_calibrate_info.is_dp_path_bok) {
|
||||
/* DP setting */
|
||||
/* LUT by SRAM */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x01017098);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0x776d9f84);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x0004ab87);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_B, MASKDWORD, 0x00880000);
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x400000);
|
||||
for (i = 0xb60; i <= 0xb9c; i += 4) {
|
||||
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x40004000);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i));
|
||||
}
|
||||
|
||||
/* PWSF */
|
||||
odm_set_bb_reg(p_dm_odm, 0xba0, MASKDWORD, 0x40404040);
|
||||
odm_set_bb_reg(p_dm_odm, 0xba4, MASKDWORD, 0x28324050);
|
||||
odm_set_bb_reg(p_dm_odm, 0xba8, MASKDWORD, 0x0c141920);
|
||||
|
||||
for (i = 0xbac; i <= 0xbbc; i += 4)
|
||||
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x0c0c0c0c);
|
||||
|
||||
/* tx_agc boundary */
|
||||
odm_set_bb_reg(p_dm_odm, 0xbc4, MASKDWORD, 0x0005361f);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0);
|
||||
|
||||
} else {
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x00000000);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0x00000000);
|
||||
}
|
||||
}
|
||||
|
||||
/* reload BB default value */
|
||||
for (index = 0; index < DP_BB_REG_NUM; index++)
|
||||
odm_set_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD, BB_backup[index]);
|
||||
|
||||
/* reload RF default value */
|
||||
for (path = 0; path < DP_PATH_NUM; path++) {
|
||||
for (i = 0 ; i < DP_RF_REG_NUM ; i++)
|
||||
odm_set_rf_reg(p_dm_odm, path, RF_REG[i], MASKDWORD, RF_backup[path][i]);
|
||||
}
|
||||
odm_set_rf_reg(p_dm_odm, RF_PATH_A, RF_MODE1, MASKDWORD, 0x1000f); /* standby mode */
|
||||
odm_set_rf_reg(p_dm_odm, RF_PATH_A, RF_MODE2, MASKDWORD, 0x20101); /* RF lpbk switches off */
|
||||
|
||||
/* reload AFE default value */
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
_phy_reload_adda_registers(p_adapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
|
||||
|
||||
/* reload MAC default value */
|
||||
_phy_reload_mac_registers(p_adapter, MAC_REG, MAC_backup);
|
||||
#else
|
||||
_phy_reload_adda_registers(p_dm_odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
|
||||
|
||||
/* reload MAC default value */
|
||||
_phy_reload_mac_registers(p_dm_odm, MAC_REG, MAC_backup);
|
||||
#endif
|
||||
|
||||
p_dm_odm->rf_calibrate_info.is_dp_done = true;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_digital_predistortion()\n"));
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
phy_digital_predistortion_8188e(
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct _ADAPTER *p_adapter
|
||||
#else
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv;
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#endif
|
||||
#endif
|
||||
#ifdef DISABLE_BB_RF
|
||||
return;
|
||||
#endif
|
||||
|
||||
return;
|
||||
|
||||
if (p_dm_odm->rf_calibrate_info.is_dp_done)
|
||||
return;
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
|
||||
if (IS_92C_SERIAL(p_hal_data->version_id))
|
||||
phy_digital_predistortion(p_adapter, true);
|
||||
else
|
||||
#endif
|
||||
{
|
||||
/* For 88C 1T1R */
|
||||
phy_digital_predistortion(p_adapter, false);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* return value true => Main; false => Aux */
|
||||
|
||||
bool _phy_query_rf_path_switch_8188e(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#else
|
||||
struct _ADAPTER *p_adapter,
|
||||
#endif
|
||||
bool is2T
|
||||
)
|
||||
{
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv;
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#endif
|
||||
#endif
|
||||
if (!p_adapter->is_hw_init_ready) {
|
||||
u8 u1b_tmp;
|
||||
u1b_tmp = odm_read_1byte(p_dm_odm, REG_LEDCFG2) | BIT(7);
|
||||
odm_write_1byte(p_dm_odm, REG_LEDCFG2, u1b_tmp);
|
||||
/* odm_set_bb_reg(p_dm_odm, REG_LEDCFG0, BIT23, 0x01); */
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_XAB_RF_PARAMETER, BIT(13), 0x01);
|
||||
}
|
||||
|
||||
if (is2T) {
|
||||
if (odm_get_bb_reg(p_dm_odm, REG_FPGA0_XB_RF_INTERFACE_OE, BIT(5) | BIT(6)) == 0x01)
|
||||
return true;
|
||||
else
|
||||
return false;
|
||||
} else {
|
||||
if ((odm_get_bb_reg(p_dm_odm, REG_FPGA0_XB_RF_INTERFACE_OE, BIT(5) | BIT(4) | BIT(3)) == 0x1))
|
||||
return true;
|
||||
else
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* return value true => Main; false => Aux */
|
||||
bool phy_query_rf_path_switch_8188e(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
#else
|
||||
struct _ADAPTER *p_adapter
|
||||
#endif
|
||||
)
|
||||
{
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
|
||||
|
||||
#ifdef DISABLE_BB_RF
|
||||
return true;
|
||||
#endif
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
|
||||
/* if(IS_92C_SERIAL( p_hal_data->version_id)) { */
|
||||
if (IS_2T2R(p_hal_data->version_id))
|
||||
return _phy_query_rf_path_switch_8188e(p_adapter, true);
|
||||
else
|
||||
#endif
|
||||
{
|
||||
/* For 88C 1T1R */
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
return _phy_query_rf_path_switch_8188e(p_adapter, false);
|
||||
#else
|
||||
return _phy_query_rf_path_switch_8188e(p_dm_odm, false);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -21,20 +21,16 @@
|
|||
#include "mp_precomp.h"
|
||||
#include "../phydm_precomp.h"
|
||||
|
||||
|
||||
|
||||
/*---------------------------Define Local Constant---------------------------*/
|
||||
/* 2010/04/25 MH Define the max tx power tracking tx agc power. */
|
||||
#define ODM_TXPWRTRACK_MAX_IDX_88E 6
|
||||
|
||||
/*---------------------------Define Local Constant---------------------------*/
|
||||
|
||||
|
||||
/* 3============================================================
|
||||
* 3 Tx Power Tracking
|
||||
* 3============================================================ */
|
||||
|
||||
|
||||
static void set_iqk_matrix_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 OFDM_index,
|
||||
|
|
@ -136,7 +132,6 @@ void do_iqk_8188e(
|
|||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
p_dm_odm->rf_calibrate_info.thermal_value_iqk = thermal_value;
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
phy_iq_calibrate_8188e(p_dm_odm, false);
|
||||
|
|
@ -289,7 +284,6 @@ odm_tx_pwr_track_set_pwr88_e(
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
/* phy_rf6052_set_cck_tx_power(p_dm_odm->priv, *(p_dm_odm->p_channel)); */
|
||||
|
|
@ -618,19 +612,7 @@ phy_path_a_iqk_8188e(
|
|||
result |= 0x01;
|
||||
else /* if Tx not OK, ignore Rx */
|
||||
return result;
|
||||
|
||||
#if 0
|
||||
if (!(reg_eac & BIT(27)) && /* if Tx is OK, check whether Rx is OK */
|
||||
(((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
|
||||
(((reg_eac & 0x03FF0000) >> 16) != 0x36))
|
||||
result |= 0x02;
|
||||
else
|
||||
RT_DISP(FINIT, INIT_IQK, ("path A Rx IQK fail!!\n"));
|
||||
#endif
|
||||
|
||||
return result;
|
||||
|
||||
|
||||
}
|
||||
|
||||
static u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
|
||||
|
|
@ -679,7 +661,6 @@ phy_path_a_rx_iqk(
|
|||
/* platform_stall_execution(IQK_DELAY_TIME_88E*1000); */
|
||||
ODM_delay_ms(IQK_DELAY_TIME_88E);
|
||||
|
||||
|
||||
/* Check failed */
|
||||
reg_eac = odm_get_bb_reg(p_dm_odm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", reg_eac));
|
||||
|
|
@ -699,7 +680,6 @@ phy_path_a_rx_iqk(
|
|||
odm_set_bb_reg(p_dm_odm, REG_TX_IQK, MASKDWORD, u4tmp);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", odm_get_bb_reg(p_dm_odm, REG_TX_IQK, MASKDWORD), u4tmp));
|
||||
|
||||
|
||||
/* 1 RX IQK */
|
||||
/* modify RXIQK mode table */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path-A Rx IQK modify RXIQK mode table 2!\n"));
|
||||
|
|
@ -743,15 +723,6 @@ phy_path_a_rx_iqk(
|
|||
reg_ea4 = odm_get_bb_reg(p_dm_odm, REG_RX_POWER_BEFORE_IQK_A_2, MASKDWORD);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", reg_ea4));
|
||||
|
||||
#if 0
|
||||
if (!(reg_eac & BIT(28)) &&
|
||||
(((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
|
||||
(((reg_e9c & 0x03FF0000) >> 16) != 0x42))
|
||||
result |= 0x01;
|
||||
else /* if Tx not OK, ignore Rx */
|
||||
return result;
|
||||
#endif
|
||||
|
||||
if (!(reg_eac & BIT(27)) && /* if Tx is OK, check whether Rx is OK */
|
||||
(((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
|
||||
(((reg_eac & 0x03FF0000) >> 16) != 0x36))
|
||||
|
|
@ -760,8 +731,6 @@ phy_path_a_rx_iqk(
|
|||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A Rx IQK fail!!\n"));
|
||||
|
||||
return result;
|
||||
|
||||
|
||||
}
|
||||
|
||||
static u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
|
||||
|
|
@ -811,7 +780,6 @@ phy_path_b_iqk_8188e(
|
|||
else
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B Rx IQK fail!!\n"));
|
||||
|
||||
|
||||
return result;
|
||||
|
||||
}
|
||||
|
|
@ -849,7 +817,6 @@ static void _phy_path_a_fill_iqk_matrix(
|
|||
if ((Y & 0x00000200) != 0)
|
||||
Y = Y | 0xFFFFFC00;
|
||||
|
||||
|
||||
TX0_C = (Y * oldval_0) >> 8;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C));
|
||||
odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XC_TX_AFE, 0xF0000000, ((TX0_C & 0x3C0) >> 6));
|
||||
|
|
@ -957,7 +924,6 @@ _phy_save_adda_registers(
|
|||
adda_backup[i] = odm_get_bb_reg(p_dm_odm, adda_reg[i], MASKDWORD);
|
||||
}
|
||||
|
||||
|
||||
static void _phy_save_mac_registers(
|
||||
struct _ADAPTER *p_adapter,
|
||||
u32 *mac_reg,
|
||||
|
|
@ -974,7 +940,6 @@ static void _phy_save_mac_registers(
|
|||
|
||||
}
|
||||
|
||||
|
||||
static void _phy_reload_adda_registers(
|
||||
struct _ADAPTER *p_adapter,
|
||||
u32 *adda_reg,
|
||||
|
|
@ -1006,7 +971,6 @@ static void _phy_reload_mac_registers(
|
|||
odm_write_4byte(p_dm_odm, mac_reg[i], mac_backup[i]);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
_phy_path_adda_on(
|
||||
struct _ADAPTER *p_adapter,
|
||||
|
|
@ -1103,7 +1067,6 @@ static bool phy_simularity_compare_8188e(
|
|||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_simularity_compare_8188e c1 %d c2 %d!!!\n", c1, c2));
|
||||
|
||||
|
||||
simularity_bit_map = 0;
|
||||
|
||||
for (i = 0; i < bound; i++) {
|
||||
|
|
@ -1147,8 +1110,6 @@ static bool phy_simularity_compare_8188e(
|
|||
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void _phy_iq_calibrate_8188e(
|
||||
struct _ADAPTER *p_adapter,
|
||||
s32 result[][8],
|
||||
|
|
@ -1216,7 +1177,6 @@ static void _phy_iq_calibrate_8188e(
|
|||
_phy_pi_mode_switch(p_adapter, true);
|
||||
}
|
||||
|
||||
|
||||
/* MAC settings */
|
||||
_phy_mac_setting_calibration(p_adapter, IQK_MAC_REG, p_dm_odm->rf_calibrate_info.IQK_MAC_backup);
|
||||
|
||||
|
|
@ -1232,7 +1192,6 @@ static void _phy_iq_calibrate_8188e(
|
|||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_XA_RF_INTERFACE_OE, BIT(10), 0x00);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_XB_RF_INTERFACE_OE, BIT(10), 0x00);
|
||||
|
||||
|
||||
if (is2T) {
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_XA_LSSI_PARAMETER, MASKDWORD, 0x00010000);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_XB_LSSI_PARAMETER, MASKDWORD, 0x00010000);
|
||||
|
|
@ -1336,7 +1295,6 @@ static void _phy_iq_calibrate_8188e(
|
|||
|
||||
}
|
||||
|
||||
|
||||
static void _phy_lc_calibrate_8188e(struct PHY_DM_STRUCT *p_dm_odm, bool is2T)
|
||||
{
|
||||
u8 tmp_reg;
|
||||
|
|
@ -1376,7 +1334,6 @@ static void _phy_lc_calibrate_8188e(struct PHY_DM_STRUCT *p_dm_odm, bool is2T)
|
|||
|
||||
ODM_delay_ms(100);
|
||||
|
||||
|
||||
/* Restore original situation */
|
||||
if ((tmp_reg & 0x70) != 0) { /* Deal with contisuous TX case */
|
||||
/* path-A */
|
||||
|
|
@ -1737,7 +1694,6 @@ static void _phy_ap_calibrate_8188e(
|
|||
tmp_reg = odm_get_bb_reg(p_dm_odm, REG_APK, 0xF8000000);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_phy_ap_calibrate_8188e() offset 0xbd8[25:21] %x\n", tmp_reg));
|
||||
|
||||
|
||||
i++;
|
||||
} while (tmp_reg > apkbound && i < 4);
|
||||
|
||||
|
|
@ -1775,7 +1731,6 @@ static void _phy_ap_calibrate_8188e(
|
|||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n"));
|
||||
|
||||
|
||||
for (path = 0; path < pathbound; path++) {
|
||||
odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3, MASKDWORD,
|
||||
((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1]));
|
||||
|
|
@ -1794,8 +1749,6 @@ static void _phy_ap_calibrate_8188e(
|
|||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==_phy_ap_calibrate_8188e()\n"));
|
||||
}
|
||||
|
||||
|
||||
|
||||
#define DP_BB_REG_NUM 7
|
||||
#define DP_RF_REG_NUM 1
|
||||
#define DP_RETRY_LIMIT 10
|
||||
|
|
@ -1803,10 +1756,6 @@ static void _phy_ap_calibrate_8188e(
|
|||
#define DP_DPK_NUM 3
|
||||
#define DP_DPK_VALUE_NUM 2
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
void
|
||||
phy_iq_calibrate_8188e(
|
||||
struct _ADAPTER *p_adapter,
|
||||
|
|
@ -1869,18 +1818,13 @@ phy_iq_calibrate_8188e(
|
|||
return;
|
||||
}
|
||||
|
||||
|
||||
odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK);
|
||||
p_dm_odm->rf_calibrate_info.is_iqk_in_progress = true;
|
||||
odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK);
|
||||
|
||||
|
||||
|
||||
start_time = odm_get_current_time(p_dm_odm);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n"));
|
||||
|
||||
|
||||
|
||||
for (i = 0; i < 8; i++) {
|
||||
result[0][i] = 0;
|
||||
result[1][i] = 0;
|
||||
|
|
@ -1894,7 +1838,6 @@ phy_iq_calibrate_8188e(
|
|||
is23simular = false;
|
||||
is13simular = false;
|
||||
|
||||
|
||||
for (i = 0; i < 3; i++) {
|
||||
/* For 88C 1T1R */
|
||||
_phy_iq_calibrate_8188e(p_adapter, result, i, false);
|
||||
|
|
@ -1992,7 +1935,6 @@ phy_iq_calibrate_8188e(
|
|||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
phy_lc_calibrate_8188e(
|
||||
void *p_dm_void
|
||||
|
|
@ -2004,7 +1946,6 @@ phy_lc_calibrate_8188e(
|
|||
s32 progressing_time;
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
|
||||
|
||||
struct _ADAPTER *p_adapter = p_dm_odm->adapter;
|
||||
/* HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); */
|
||||
|
||||
|
|
@ -2018,7 +1959,6 @@ phy_lc_calibrate_8188e(
|
|||
}
|
||||
#endif
|
||||
|
||||
|
||||
#if DISABLE_BB_RF
|
||||
return;
|
||||
#endif
|
||||
|
|
@ -2100,17 +2040,11 @@ static void _phy_set_rf_path_switch_8188e(
|
|||
}
|
||||
}
|
||||
void phy_set_rf_path_switch_8188e(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#else
|
||||
struct _ADAPTER *p_adapter,
|
||||
#endif
|
||||
bool is_main
|
||||
)
|
||||
{
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
|
||||
#endif
|
||||
|
||||
#if DISABLE_BB_RF
|
||||
return;
|
||||
|
|
@ -2118,458 +2052,8 @@ void phy_set_rf_path_switch_8188e(
|
|||
|
||||
{
|
||||
/* For 88C 1T1R */
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
_phy_set_rf_path_switch_8188e(p_adapter, is_main, false);
|
||||
#else
|
||||
_phy_set_rf_path_switch_8188e(p_dm_odm, is_main, false);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
/* digital predistortion */
|
||||
void
|
||||
phy_digital_predistortion(
|
||||
struct _ADAPTER *p_adapter,
|
||||
bool is2T
|
||||
)
|
||||
{
|
||||
#if (RT_PLATFORM == PLATFORM_WINDOWS)
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv;
|
||||
|
||||
u32 tmp_reg, tmp_reg2, index, i;
|
||||
u8 path, pathbound = PATH_NUM;
|
||||
u32 AFE_backup[IQK_ADDA_REG_NUM];
|
||||
u32 AFE_REG[IQK_ADDA_REG_NUM] = {
|
||||
REG_FPGA0_XCD_SWITCH_CONTROL, REG_BLUE_TOOTH,
|
||||
REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
|
||||
REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
|
||||
REG_TX_OFDM_BBON, REG_TX_TO_RX,
|
||||
REG_TX_TO_TX, REG_RX_CCK,
|
||||
REG_RX_OFDM, REG_RX_WAIT_RIFS,
|
||||
REG_RX_TO_RX, REG_STANDBY,
|
||||
REG_SLEEP, REG_PMPD_ANAEN
|
||||
};
|
||||
|
||||
u32 BB_backup[DP_BB_REG_NUM];
|
||||
u32 BB_REG[DP_BB_REG_NUM] = {
|
||||
REG_OFDM_0_TRX_PATH_ENABLE, REG_FPGA0_RFMOD,
|
||||
REG_OFDM_0_TR_MUX_PAR, REG_FPGA0_XCD_RF_INTERFACE_SW,
|
||||
REG_FPGA0_XAB_RF_INTERFACE_SW, REG_FPGA0_XA_RF_INTERFACE_OE,
|
||||
REG_FPGA0_XB_RF_INTERFACE_OE
|
||||
};
|
||||
u32 BB_settings[DP_BB_REG_NUM] = {
|
||||
0x00a05430, 0x02040000, 0x000800e4, 0x22208000,
|
||||
0x0, 0x0, 0x0
|
||||
};
|
||||
|
||||
u32 RF_backup[DP_PATH_NUM][DP_RF_REG_NUM];
|
||||
u32 RF_REG[DP_RF_REG_NUM] = {
|
||||
RF_TXBIAS_A
|
||||
};
|
||||
|
||||
u32 MAC_backup[IQK_MAC_REG_NUM];
|
||||
u32 MAC_REG[IQK_MAC_REG_NUM] = {
|
||||
REG_TXPAUSE, REG_BCN_CTRL,
|
||||
REG_BCN_CTRL_1, REG_GPIO_MUXCFG
|
||||
};
|
||||
|
||||
u32 tx_agc[DP_DPK_NUM][DP_DPK_VALUE_NUM] = {
|
||||
{0x1e1e1e1e, 0x03901e1e},
|
||||
{0x18181818, 0x03901818},
|
||||
{0x0e0e0e0e, 0x03900e0e}
|
||||
};
|
||||
|
||||
u32 AFE_on_off[PATH_NUM] = {
|
||||
0x04db25a4, 0x0b1b25a4
|
||||
}; /* path A on path B off / path A off path B on */
|
||||
|
||||
u8 retry_count = 0;
|
||||
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_digital_predistortion()\n"));
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_digital_predistortion for %s\n", (is2T ? "2T2R" : "1T1R")));
|
||||
|
||||
/* save BB default value */
|
||||
for (index = 0; index < DP_BB_REG_NUM; index++)
|
||||
BB_backup[index] = odm_get_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD);
|
||||
|
||||
/* save MAC default value */
|
||||
_phy_save_mac_registers(p_adapter, BB_REG, MAC_backup);
|
||||
|
||||
/* save RF default value */
|
||||
for (path = 0; path < DP_PATH_NUM; path++) {
|
||||
for (index = 0; index < DP_RF_REG_NUM; index++)
|
||||
RF_backup[path][index] = phy_query_rf_reg(p_adapter, path, RF_REG[index], MASKDWORD);
|
||||
}
|
||||
|
||||
/* save AFE default value */
|
||||
_phy_save_adda_registers(p_adapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
|
||||
|
||||
/* path A/B AFE all on */
|
||||
for (index = 0; index < IQK_ADDA_REG_NUM ; index++)
|
||||
odm_set_bb_reg(p_dm_odm, AFE_REG[index], MASKDWORD, 0x6fdb25a4);
|
||||
|
||||
/* BB register setting */
|
||||
for (index = 0; index < DP_BB_REG_NUM; index++) {
|
||||
if (index < 4)
|
||||
odm_set_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD, BB_settings[index]);
|
||||
else if (index == 4)
|
||||
odm_set_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD, BB_backup[index] | BIT(10) | BIT(26));
|
||||
else
|
||||
odm_set_bb_reg(p_dm_odm, BB_REG[index], BIT(10), 0x00);
|
||||
}
|
||||
|
||||
/* MAC register setting */
|
||||
_phy_mac_setting_calibration(p_adapter, MAC_REG, MAC_backup);
|
||||
|
||||
/* PAGE-E IQC setting */
|
||||
odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_A, MASKDWORD, 0x01008c00);
|
||||
odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_A, MASKDWORD, 0x01008c00);
|
||||
odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_B, MASKDWORD, 0x01008c00);
|
||||
odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_B, MASKDWORD, 0x01008c00);
|
||||
|
||||
/* path_A DPK */
|
||||
/* path B to standby mode */
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, RF_AC, MASKDWORD, 0x10000);
|
||||
|
||||
/* PA gain = 11 & PAD1 => tx_agc 1f ~11 */
|
||||
/* PA gain = 11 & PAD2 => tx_agc 10~0e */
|
||||
/* PA gain = 01 => tx_agc 0b~0d */
|
||||
/* PA gain = 00 => tx_agc 0a~00 */
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x400000);
|
||||
odm_set_bb_reg(p_dm_odm, 0xbc0, MASKDWORD, 0x0005361f);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
|
||||
|
||||
/* do inner loopback DPK 3 times */
|
||||
for (i = 0; i < 3; i++) {
|
||||
/* PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 */
|
||||
for (index = 0; index < 3; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0xe00 + index * 4, MASKDWORD, tx_agc[i][0]);
|
||||
odm_set_bb_reg(p_dm_odm, 0xe00 + index * 4, MASKDWORD, tx_agc[i][1]);
|
||||
for (index = 0; index < 4; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0xe10 + index * 4, MASKDWORD, tx_agc[i][0]);
|
||||
|
||||
/* PAGE_B for path-A inner loopback DPK setting */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x02097098);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0xf76d9f84);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x0004ab87);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00880000);
|
||||
|
||||
/* ----send one shot signal---- */
|
||||
/* path A */
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x80047788);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x00047788);
|
||||
ODM_delay_ms(50);
|
||||
}
|
||||
|
||||
/* PA gain = 11 => tx_agc = 1a */
|
||||
for (index = 0; index < 3; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0xe00 + index * 4, MASKDWORD, 0x34343434);
|
||||
odm_set_bb_reg(p_dm_odm, 0xe08 + index * 4, MASKDWORD, 0x03903434);
|
||||
for (index = 0; index < 4; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0xe10 + index * 4, MASKDWORD, 0x34343434);
|
||||
|
||||
/* ==================================== */
|
||||
/* PAGE_B for path-A DPK setting */
|
||||
/* ==================================== */
|
||||
/* open inner loopback @ b00[19]:10 od 0xb00 0x01097018 */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x02017098);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0xf76d9f84);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x0004ab87);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00880000);
|
||||
|
||||
/* rf_lpbk_setup */
|
||||
/* 1.rf 00:5205a, rf 0d:0e52c */
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0c, MASKDWORD, 0x8992b);
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0d, MASKDWORD, 0x0e52c);
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x00, MASKDWORD, 0x5205a);
|
||||
|
||||
/* ----send one shot signal---- */
|
||||
/* path A */
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x800477c0);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x000477c0);
|
||||
ODM_delay_ms(50);
|
||||
|
||||
while (retry_count < DP_RETRY_LIMIT && !p_dm_odm->rf_calibrate_info.is_dp_path_aok) {
|
||||
/* ----read back measurement results---- */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x0c297018);
|
||||
tmp_reg = odm_get_bb_reg(p_dm_odm, 0xbe0, MASKDWORD);
|
||||
ODM_delay_ms(10);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x0c29701f);
|
||||
tmp_reg2 = odm_get_bb_reg(p_dm_odm, 0xbe8, MASKDWORD);
|
||||
ODM_delay_ms(10);
|
||||
|
||||
tmp_reg = (tmp_reg & MASKHWORD) >> 16;
|
||||
tmp_reg2 = (tmp_reg2 & MASKHWORD) >> 16;
|
||||
if (tmp_reg < 0xf0 || tmp_reg > 0x105 || tmp_reg2 > 0xff) {
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x02017098);
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x800000);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x800477c0);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x000477c0);
|
||||
ODM_delay_ms(50);
|
||||
retry_count++;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK retry_count %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", retry_count, tmp_reg, tmp_reg2));
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n"));
|
||||
p_dm_odm->rf_calibrate_info.is_dp_path_aok = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
retry_count = 0;
|
||||
|
||||
/* DPP path A */
|
||||
if (p_dm_odm->rf_calibrate_info.is_dp_path_aok) {
|
||||
/* DP settings */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x01017098);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0x776d9f84);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x0004ab87);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00880000);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x400000);
|
||||
|
||||
for (i = REG_PDP_ANT_A; i <= 0xb3c; i += 4) {
|
||||
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x40004000);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i));
|
||||
}
|
||||
|
||||
/* pwsf */
|
||||
odm_set_bb_reg(p_dm_odm, 0xb40, MASKDWORD, 0x40404040);
|
||||
odm_set_bb_reg(p_dm_odm, 0xb44, MASKDWORD, 0x28324040);
|
||||
odm_set_bb_reg(p_dm_odm, 0xb48, MASKDWORD, 0x10141920);
|
||||
|
||||
for (i = 0xb4c; i <= 0xb5c; i += 4)
|
||||
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x0c0c0c0c);
|
||||
|
||||
/* TX_AGC boundary */
|
||||
odm_set_bb_reg(p_dm_odm, 0xbc0, MASKDWORD, 0x0005361f);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
|
||||
} else {
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x00000000);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0x00000000);
|
||||
}
|
||||
|
||||
/* DPK path B */
|
||||
if (is2T) {
|
||||
/* path A to standby mode */
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_AC, MASKDWORD, 0x10000);
|
||||
|
||||
/* LUTs => tx_agc */
|
||||
/* PA gain = 11 & PAD1, => tx_agc 1f ~11 */
|
||||
/* PA gain = 11 & PAD2, => tx_agc 10 ~0e */
|
||||
/* PA gain = 01 => tx_agc 0b ~0d */
|
||||
/* PA gain = 00 => tx_agc 0a ~00 */
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x400000);
|
||||
odm_set_bb_reg(p_dm_odm, 0xbc4, MASKDWORD, 0x0005361f);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
|
||||
|
||||
/* do inner loopback DPK 3 times */
|
||||
for (i = 0; i < 3; i++) {
|
||||
/* PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 */
|
||||
for (index = 0; index < 4; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0x830 + index * 4, MASKDWORD, tx_agc[i][0]);
|
||||
for (index = 0; index < 2; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0x848 + index * 4, MASKDWORD, tx_agc[i][0]);
|
||||
for (index = 0; index < 2; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0x868 + index * 4, MASKDWORD, tx_agc[i][0]);
|
||||
|
||||
/* PAGE_B for path-A inner loopback DPK setting */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x02097098);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0xf76d9f84);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x0004ab87);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_B, MASKDWORD, 0x00880000);
|
||||
|
||||
/* ----send one shot signal---- */
|
||||
/* path B */
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x80047788);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x00047788);
|
||||
ODM_delay_ms(50);
|
||||
}
|
||||
|
||||
/* PA gain = 11 => tx_agc = 1a */
|
||||
for (index = 0; index < 4; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0x830 + index * 4, MASKDWORD, 0x34343434);
|
||||
for (index = 0; index < 2; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0x848 + index * 4, MASKDWORD, 0x34343434);
|
||||
for (index = 0; index < 2; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0x868 + index * 4, MASKDWORD, 0x34343434);
|
||||
|
||||
/* PAGE_B for path-B DPK setting */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x02017098);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0xf76d9f84);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x0004ab87);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_B, MASKDWORD, 0x00880000);
|
||||
|
||||
/* RF lpbk switches on */
|
||||
odm_set_bb_reg(p_dm_odm, 0x840, MASKDWORD, 0x0101000f);
|
||||
odm_set_bb_reg(p_dm_odm, 0x840, MASKDWORD, 0x01120103);
|
||||
|
||||
/* path-B RF lpbk */
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x0c, MASKDWORD, 0x8992b);
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x0d, MASKDWORD, 0x0e52c);
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, RF_AC, MASKDWORD, 0x5205a);
|
||||
|
||||
/* ----send one shot signal---- */
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x800477c0);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x000477c0);
|
||||
ODM_delay_ms(50);
|
||||
|
||||
while (retry_count < DP_RETRY_LIMIT && !p_dm_odm->rf_calibrate_info.is_dp_path_bok) {
|
||||
/* ----read back measurement results---- */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x0c297018);
|
||||
tmp_reg = odm_get_bb_reg(p_dm_odm, 0xbf0, MASKDWORD);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x0c29701f);
|
||||
tmp_reg2 = odm_get_bb_reg(p_dm_odm, 0xbf8, MASKDWORD);
|
||||
|
||||
tmp_reg = (tmp_reg & MASKHWORD) >> 16;
|
||||
tmp_reg2 = (tmp_reg2 & MASKHWORD) >> 16;
|
||||
|
||||
if (tmp_reg < 0xf0 || tmp_reg > 0x105 || tmp_reg2 > 0xff) {
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x02017098);
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x800000);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x800477c0);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x000477c0);
|
||||
ODM_delay_ms(50);
|
||||
retry_count++;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK retry_count %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", retry_count, tmp_reg, tmp_reg2));
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n"));
|
||||
p_dm_odm->rf_calibrate_info.is_dp_path_bok = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* DPP path B */
|
||||
if (p_dm_odm->rf_calibrate_info.is_dp_path_bok) {
|
||||
/* DP setting */
|
||||
/* LUT by SRAM */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x01017098);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0x776d9f84);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x0004ab87);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_B, MASKDWORD, 0x00880000);
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x400000);
|
||||
for (i = 0xb60; i <= 0xb9c; i += 4) {
|
||||
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x40004000);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i));
|
||||
}
|
||||
|
||||
/* PWSF */
|
||||
odm_set_bb_reg(p_dm_odm, 0xba0, MASKDWORD, 0x40404040);
|
||||
odm_set_bb_reg(p_dm_odm, 0xba4, MASKDWORD, 0x28324050);
|
||||
odm_set_bb_reg(p_dm_odm, 0xba8, MASKDWORD, 0x0c141920);
|
||||
|
||||
for (i = 0xbac; i <= 0xbbc; i += 4)
|
||||
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x0c0c0c0c);
|
||||
|
||||
/* tx_agc boundary */
|
||||
odm_set_bb_reg(p_dm_odm, 0xbc4, MASKDWORD, 0x0005361f);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
|
||||
|
||||
} else {
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x00000000);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0x00000000);
|
||||
}
|
||||
}
|
||||
|
||||
/* reload BB default value */
|
||||
for (index = 0; index < DP_BB_REG_NUM; index++)
|
||||
odm_set_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD, BB_backup[index]);
|
||||
|
||||
/* reload RF default value */
|
||||
for (path = 0; path < DP_PATH_NUM; path++) {
|
||||
for (i = 0 ; i < DP_RF_REG_NUM ; i++)
|
||||
odm_set_rf_reg(p_dm_odm, path, RF_REG[i], MASKDWORD, RF_backup[path][i]);
|
||||
}
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_MODE1, MASKDWORD, 0x1000f); /* standby mode */
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_MODE2, MASKDWORD, 0x20101); /* RF lpbk switches off */
|
||||
|
||||
/* reload AFE default value */
|
||||
_phy_reload_adda_registers(p_adapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
|
||||
|
||||
/* reload MAC default value */
|
||||
_phy_reload_mac_registers(p_adapter, MAC_REG, MAC_backup);
|
||||
|
||||
p_dm_odm->rf_calibrate_info.is_dp_done = true;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_digital_predistortion()\n"));
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
phy_digital_predistortion_8188e(
|
||||
struct _ADAPTER *p_adapter
|
||||
)
|
||||
{
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* return value true => Main; false => Aux */
|
||||
|
||||
bool _phy_query_rf_path_switch_8188e(
|
||||
struct _ADAPTER *p_adapter,
|
||||
bool is2T
|
||||
)
|
||||
{
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv;
|
||||
|
||||
if (!p_adapter->is_hw_init_ready) {
|
||||
u8 u1b_tmp;
|
||||
u1b_tmp = odm_read_1byte(p_dm_odm, REG_LEDCFG2) | BIT(7);
|
||||
odm_write_1byte(p_dm_odm, REG_LEDCFG2, u1b_tmp);
|
||||
/* odm_set_bb_reg(p_dm_odm, REG_LEDCFG0, BIT23, 0x01); */
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_XAB_RF_PARAMETER, BIT(13), 0x01);
|
||||
}
|
||||
|
||||
if (is2T) {
|
||||
if (odm_get_bb_reg(p_dm_odm, REG_FPGA0_XB_RF_INTERFACE_OE, BIT(5) | BIT(6)) == 0x01)
|
||||
return true;
|
||||
else
|
||||
return false;
|
||||
} else {
|
||||
if ((odm_get_bb_reg(p_dm_odm, REG_FPGA0_XB_RF_INTERFACE_OE, BIT(5) | BIT(4) | BIT(3)) == 0x1))
|
||||
return true;
|
||||
else
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* return value true => Main; false => Aux */
|
||||
bool phy_query_rf_path_switch_8188e(
|
||||
struct _ADAPTER *p_adapter
|
||||
)
|
||||
{
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
|
||||
|
||||
#if DISABLE_BB_RF
|
||||
return true;
|
||||
#endif
|
||||
if (IS_2T2R(p_hal_data->version_id))
|
||||
return _phy_query_rf_path_switch_8188e(p_adapter, true);
|
||||
else
|
||||
{
|
||||
/* For 88C 1T1R */
|
||||
return _phy_query_rf_path_switch_8188e(p_adapter, false);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -2668,428 +2668,15 @@ phy_digital_predistortion(
|
|||
bool is2T
|
||||
)
|
||||
{
|
||||
#if (RT_PLATFORM == PLATFORM_WINDOWS)
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv;
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#endif
|
||||
#endif
|
||||
struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
|
||||
u32 tmp_reg, tmp_reg2, index, i;
|
||||
u8 path, pathbound = PATH_NUM;
|
||||
u32 AFE_backup[IQK_ADDA_REG_NUM];
|
||||
u32 AFE_REG[IQK_ADDA_REG_NUM] = {
|
||||
REG_FPGA0_XCD_SWITCH_CONTROL, REG_BLUE_TOOTH,
|
||||
REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
|
||||
REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
|
||||
REG_TX_OFDM_BBON, REG_TX_TO_RX,
|
||||
REG_TX_TO_TX, REG_RX_CCK,
|
||||
REG_RX_OFDM, REG_RX_WAIT_RIFS,
|
||||
REG_RX_TO_RX, REG_STANDBY,
|
||||
REG_SLEEP, REG_PMPD_ANAEN
|
||||
};
|
||||
|
||||
u32 BB_backup[DP_BB_REG_NUM];
|
||||
u32 BB_REG[DP_BB_REG_NUM] = {
|
||||
REG_OFDM_0_TRX_PATH_ENABLE, REG_FPGA0_RFMOD,
|
||||
REG_OFDM_0_TR_MUX_PAR, REG_FPGA0_XCD_RF_INTERFACE_SW,
|
||||
REG_FPGA0_XAB_RF_INTERFACE_SW, REG_FPGA0_XA_RF_INTERFACE_OE,
|
||||
REG_FPGA0_XB_RF_INTERFACE_OE
|
||||
};
|
||||
u32 BB_settings[DP_BB_REG_NUM] = {
|
||||
0x00a05430, 0x02040000, 0x000800e4, 0x22208000,
|
||||
0x0, 0x0, 0x0
|
||||
};
|
||||
|
||||
u32 RF_backup[DP_PATH_NUM][DP_RF_REG_NUM];
|
||||
u32 RF_REG[DP_RF_REG_NUM] = {
|
||||
RF_TXBIAS_A
|
||||
};
|
||||
|
||||
u32 MAC_backup[IQK_MAC_REG_NUM];
|
||||
u32 MAC_REG[IQK_MAC_REG_NUM] = {
|
||||
REG_TXPAUSE, REG_BCN_CTRL,
|
||||
REG_BCN_CTRL_1, REG_GPIO_MUXCFG
|
||||
};
|
||||
|
||||
u32 tx_agc[DP_DPK_NUM][DP_DPK_VALUE_NUM] = {
|
||||
{0x1e1e1e1e, 0x03901e1e},
|
||||
{0x18181818, 0x03901818},
|
||||
{0x0e0e0e0e, 0x03900e0e}
|
||||
};
|
||||
|
||||
u32 AFE_on_off[PATH_NUM] = {
|
||||
0x04db25a4, 0x0b1b25a4
|
||||
}; /* path A on path B off / path A off path B on */
|
||||
|
||||
u8 retry_count = 0;
|
||||
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_digital_predistortion()\n"));
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_digital_predistortion for %s\n", (is2T ? "2T2R" : "1T1R")));
|
||||
|
||||
/* save BB default value */
|
||||
for (index = 0; index < DP_BB_REG_NUM; index++)
|
||||
BB_backup[index] = odm_get_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD);
|
||||
|
||||
/* save MAC default value */
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
_phy_save_mac_registers(p_adapter, BB_REG, MAC_backup);
|
||||
#else
|
||||
_phy_save_mac_registers(p_dm_odm, BB_REG, MAC_backup);
|
||||
#endif
|
||||
|
||||
/* save RF default value */
|
||||
for (path = 0; path < DP_PATH_NUM; path++) {
|
||||
for (index = 0; index < DP_RF_REG_NUM; index++)
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
RF_backup[path][index] = odm_get_rf_reg(p_dm_odm, path, RF_REG[index], MASKDWORD);
|
||||
#else
|
||||
RF_backup[path][index] = odm_get_rf_reg(p_dm_odm, path, RF_REG[index], MASKDWORD);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* save AFE default value */
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
_phy_save_adda_registers(p_adapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
|
||||
#else
|
||||
_phy_save_adda_registers(p_dm_odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
|
||||
#endif
|
||||
|
||||
/* path A/B AFE all on */
|
||||
for (index = 0; index < IQK_ADDA_REG_NUM ; index++)
|
||||
odm_set_bb_reg(p_dm_odm, AFE_REG[index], MASKDWORD, 0x6fdb25a4);
|
||||
|
||||
/* BB register setting */
|
||||
for (index = 0; index < DP_BB_REG_NUM; index++) {
|
||||
if (index < 4)
|
||||
odm_set_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD, BB_settings[index]);
|
||||
else if (index == 4)
|
||||
odm_set_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD, BB_backup[index] | BIT(10) | BIT(26));
|
||||
else
|
||||
odm_set_bb_reg(p_dm_odm, BB_REG[index], BIT(10), 0x00);
|
||||
}
|
||||
|
||||
/* MAC register setting */
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
_phy_mac_setting_calibration(p_adapter, MAC_REG, MAC_backup);
|
||||
#else
|
||||
_phy_mac_setting_calibration(p_dm_odm, MAC_REG, MAC_backup);
|
||||
#endif
|
||||
|
||||
/* PAGE-E IQC setting */
|
||||
odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_A, MASKDWORD, 0x01008c00);
|
||||
odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_A, MASKDWORD, 0x01008c00);
|
||||
odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_B, MASKDWORD, 0x01008c00);
|
||||
odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_B, MASKDWORD, 0x01008c00);
|
||||
|
||||
/* path_A DPK */
|
||||
/* path B to standby mode */
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, RF_AC, MASKDWORD, 0x10000);
|
||||
|
||||
/* PA gain = 11 & PAD1 => tx_agc 1f ~11 */
|
||||
/* PA gain = 11 & PAD2 => tx_agc 10~0e */
|
||||
/* PA gain = 01 => tx_agc 0b~0d */
|
||||
/* PA gain = 00 => tx_agc 0a~00 */
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x400000);
|
||||
odm_set_bb_reg(p_dm_odm, 0xbc0, MASKDWORD, 0x0005361f);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
|
||||
|
||||
/* do inner loopback DPK 3 times */
|
||||
for (i = 0; i < 3; i++) {
|
||||
/* PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 */
|
||||
for (index = 0; index < 3; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0xe00 + index * 4, MASKDWORD, tx_agc[i][0]);
|
||||
odm_set_bb_reg(p_dm_odm, 0xe00 + index * 4, MASKDWORD, tx_agc[i][1]);
|
||||
for (index = 0; index < 4; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0xe10 + index * 4, MASKDWORD, tx_agc[i][0]);
|
||||
|
||||
/* PAGE_B for path-A inner loopback DPK setting */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x02097098);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0xf76d9f84);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x0004ab87);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00880000);
|
||||
|
||||
/* ----send one shot signal---- */
|
||||
/* path A */
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x80047788);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x00047788);
|
||||
ODM_delay_ms(50);
|
||||
}
|
||||
|
||||
/* PA gain = 11 => tx_agc = 1a */
|
||||
for (index = 0; index < 3; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0xe00 + index * 4, MASKDWORD, 0x34343434);
|
||||
odm_set_bb_reg(p_dm_odm, 0xe08 + index * 4, MASKDWORD, 0x03903434);
|
||||
for (index = 0; index < 4; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0xe10 + index * 4, MASKDWORD, 0x34343434);
|
||||
|
||||
/* ==================================== */
|
||||
/* PAGE_B for path-A DPK setting */
|
||||
/* ==================================== */
|
||||
/* open inner loopback @ b00[19]:10 od 0xb00 0x01097018 */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x02017098);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0xf76d9f84);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x0004ab87);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00880000);
|
||||
|
||||
/* rf_lpbk_setup */
|
||||
/* 1.rf 00:5205a, rf 0d:0e52c */
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0c, MASKDWORD, 0x8992b);
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0d, MASKDWORD, 0x0e52c);
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x00, MASKDWORD, 0x5205a);
|
||||
|
||||
/* ----send one shot signal---- */
|
||||
/* path A */
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x800477c0);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x000477c0);
|
||||
ODM_delay_ms(50);
|
||||
|
||||
while (retry_count < DP_RETRY_LIMIT && !p_rf_calibrate_info->is_dp_path_aok) {
|
||||
/* ----read back measurement results---- */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x0c297018);
|
||||
tmp_reg = odm_get_bb_reg(p_dm_odm, 0xbe0, MASKDWORD);
|
||||
ODM_delay_ms(10);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x0c29701f);
|
||||
tmp_reg2 = odm_get_bb_reg(p_dm_odm, 0xbe8, MASKDWORD);
|
||||
ODM_delay_ms(10);
|
||||
|
||||
tmp_reg = (tmp_reg & MASKHWORD) >> 16;
|
||||
tmp_reg2 = (tmp_reg2 & MASKHWORD) >> 16;
|
||||
if (tmp_reg < 0xf0 || tmp_reg > 0x105 || tmp_reg2 > 0xff) {
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x02017098);
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x800000);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x800477c0);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x000477c0);
|
||||
ODM_delay_ms(50);
|
||||
retry_count++;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK retry_count %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", retry_count, tmp_reg, tmp_reg2));
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n"));
|
||||
p_rf_calibrate_info->is_dp_path_aok = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
retry_count = 0;
|
||||
|
||||
/* DPP path A */
|
||||
if (p_rf_calibrate_info->is_dp_path_aok) {
|
||||
/* DP settings */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x01017098);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0x776d9f84);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x0004ab87);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00880000);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x400000);
|
||||
|
||||
for (i = REG_PDP_ANT_A; i <= 0xb3c; i += 4) {
|
||||
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x40004000);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i));
|
||||
}
|
||||
|
||||
/* pwsf */
|
||||
odm_set_bb_reg(p_dm_odm, 0xb40, MASKDWORD, 0x40404040);
|
||||
odm_set_bb_reg(p_dm_odm, 0xb44, MASKDWORD, 0x28324040);
|
||||
odm_set_bb_reg(p_dm_odm, 0xb48, MASKDWORD, 0x10141920);
|
||||
|
||||
for (i = 0xb4c; i <= 0xb5c; i += 4)
|
||||
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x0c0c0c0c);
|
||||
|
||||
/* TX_AGC boundary */
|
||||
odm_set_bb_reg(p_dm_odm, 0xbc0, MASKDWORD, 0x0005361f);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
|
||||
} else {
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x00000000);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0x00000000);
|
||||
}
|
||||
|
||||
/* DPK path B */
|
||||
if (is2T) {
|
||||
/* path A to standby mode */
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_AC, MASKDWORD, 0x10000);
|
||||
|
||||
/* LUTs => tx_agc */
|
||||
/* PA gain = 11 & PAD1, => tx_agc 1f ~11 */
|
||||
/* PA gain = 11 & PAD2, => tx_agc 10 ~0e */
|
||||
/* PA gain = 01 => tx_agc 0b ~0d */
|
||||
/* PA gain = 00 => tx_agc 0a ~00 */
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x400000);
|
||||
odm_set_bb_reg(p_dm_odm, 0xbc4, MASKDWORD, 0x0005361f);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
|
||||
|
||||
/* do inner loopback DPK 3 times */
|
||||
for (i = 0; i < 3; i++) {
|
||||
/* PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 */
|
||||
for (index = 0; index < 4; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0x830 + index * 4, MASKDWORD, tx_agc[i][0]);
|
||||
for (index = 0; index < 2; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0x848 + index * 4, MASKDWORD, tx_agc[i][0]);
|
||||
for (index = 0; index < 2; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0x868 + index * 4, MASKDWORD, tx_agc[i][0]);
|
||||
|
||||
/* PAGE_B for path-A inner loopback DPK setting */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x02097098);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0xf76d9f84);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x0004ab87);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_B, MASKDWORD, 0x00880000);
|
||||
|
||||
/* ----send one shot signal---- */
|
||||
/* path B */
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x80047788);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x00047788);
|
||||
ODM_delay_ms(50);
|
||||
}
|
||||
|
||||
/* PA gain = 11 => tx_agc = 1a */
|
||||
for (index = 0; index < 4; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0x830 + index * 4, MASKDWORD, 0x34343434);
|
||||
for (index = 0; index < 2; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0x848 + index * 4, MASKDWORD, 0x34343434);
|
||||
for (index = 0; index < 2; index++)
|
||||
odm_set_bb_reg(p_dm_odm, 0x868 + index * 4, MASKDWORD, 0x34343434);
|
||||
|
||||
/* PAGE_B for path-B DPK setting */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x02017098);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0xf76d9f84);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x0004ab87);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_B, MASKDWORD, 0x00880000);
|
||||
|
||||
/* RF lpbk switches on */
|
||||
odm_set_bb_reg(p_dm_odm, 0x840, MASKDWORD, 0x0101000f);
|
||||
odm_set_bb_reg(p_dm_odm, 0x840, MASKDWORD, 0x01120103);
|
||||
|
||||
/* path-B RF lpbk */
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x0c, MASKDWORD, 0x8992b);
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x0d, MASKDWORD, 0x0e52c);
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, RF_AC, MASKDWORD, 0x5205a);
|
||||
|
||||
/* ----send one shot signal---- */
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x800477c0);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x000477c0);
|
||||
ODM_delay_ms(50);
|
||||
|
||||
while (retry_count < DP_RETRY_LIMIT && !p_rf_calibrate_info->is_dp_path_bok) {
|
||||
/* ----read back measurement results---- */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x0c297018);
|
||||
tmp_reg = odm_get_bb_reg(p_dm_odm, 0xbf0, MASKDWORD);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x0c29701f);
|
||||
tmp_reg2 = odm_get_bb_reg(p_dm_odm, 0xbf8, MASKDWORD);
|
||||
|
||||
tmp_reg = (tmp_reg & MASKHWORD) >> 16;
|
||||
tmp_reg2 = (tmp_reg2 & MASKHWORD) >> 16;
|
||||
|
||||
if (tmp_reg < 0xf0 || tmp_reg > 0x105 || tmp_reg2 > 0xff) {
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x02017098);
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x800000);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x800477c0);
|
||||
ODM_delay_ms(1);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x000477c0);
|
||||
ODM_delay_ms(50);
|
||||
retry_count++;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK retry_count %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", retry_count, tmp_reg, tmp_reg2));
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n"));
|
||||
p_rf_calibrate_info->is_dp_path_bok = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* DPP path B */
|
||||
if (p_rf_calibrate_info->is_dp_path_bok) {
|
||||
/* DP setting */
|
||||
/* LUT by SRAM */
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x01017098);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0x776d9f84);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x0004ab87);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_B, MASKDWORD, 0x00880000);
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x400000);
|
||||
for (i = 0xb60; i <= 0xb9c; i += 4) {
|
||||
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x40004000);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i));
|
||||
}
|
||||
|
||||
/* PWSF */
|
||||
odm_set_bb_reg(p_dm_odm, 0xba0, MASKDWORD, 0x40404040);
|
||||
odm_set_bb_reg(p_dm_odm, 0xba4, MASKDWORD, 0x28324050);
|
||||
odm_set_bb_reg(p_dm_odm, 0xba8, MASKDWORD, 0x0c141920);
|
||||
|
||||
for (i = 0xbac; i <= 0xbbc; i += 4)
|
||||
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x0c0c0c0c);
|
||||
|
||||
/* tx_agc boundary */
|
||||
odm_set_bb_reg(p_dm_odm, 0xbc4, MASKDWORD, 0x0005361f);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
|
||||
|
||||
} else {
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x00000000);
|
||||
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0x00000000);
|
||||
}
|
||||
}
|
||||
|
||||
/* reload BB default value */
|
||||
for (index = 0; index < DP_BB_REG_NUM; index++)
|
||||
odm_set_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD, BB_backup[index]);
|
||||
|
||||
/* reload RF default value */
|
||||
for (path = 0; path < DP_PATH_NUM; path++) {
|
||||
for (i = 0 ; i < DP_RF_REG_NUM ; i++)
|
||||
odm_set_rf_reg(p_dm_odm, path, RF_REG[i], MASKDWORD, RF_backup[path][i]);
|
||||
}
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_MODE1, MASKDWORD, 0x1000f); /* standby mode */
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_MODE2, MASKDWORD, 0x20101); /* RF lpbk switches off */
|
||||
|
||||
/* reload AFE default value */
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
_phy_reload_adda_registers(p_adapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
|
||||
|
||||
/* reload MAC default value */
|
||||
_phy_reload_mac_registers(p_adapter, MAC_REG, MAC_backup);
|
||||
#else
|
||||
_phy_reload_adda_registers(p_dm_odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
|
||||
|
||||
/* reload MAC default value */
|
||||
_phy_reload_mac_registers(p_dm_odm, MAC_REG, MAC_backup);
|
||||
#endif
|
||||
|
||||
p_rf_calibrate_info->is_dp_done = true;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_digital_predistortion()\n"));
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
phy_digital_predistortion_8188e(
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct _ADAPTER *p_adapter
|
||||
#else
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv;
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#endif
|
||||
#endif
|
||||
struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
|
||||
#if DISABLE_BB_RF
|
||||
return;
|
||||
|
|
@ -3099,13 +2686,10 @@ phy_digital_predistortion_8188e(
|
|||
|
||||
if (p_rf_calibrate_info->is_dp_done)
|
||||
return;
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
|
||||
if (IS_92C_SERIAL(p_hal_data->VersionID))
|
||||
phy_digital_predistortion(p_adapter, true);
|
||||
else
|
||||
#endif
|
||||
{
|
||||
else {
|
||||
/* For 88C 1T1R */
|
||||
phy_digital_predistortion(p_adapter, false);
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue