skyfall/rtl8188eu
1
0
Fork 0
mirror of https://github.com/lwfinger/rtl8188eu.git synced 2024-11-15 01:19:36 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

rtl8188eu: Remove code for platforms other than Linux in hal/

Browse source 
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2018-10-20 14:52:30 -05:00
parent 85ec7cf9ce
commit 038e7c215b
13 changed files with 4 additions and 2920 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

143
hal/btc/halbtc8723b1ant.c
View file

@ -27,7 +27,6 @@ static struct coex_sta_8723b_1ant *coex_sta = &glcoex_sta_8723b_1ant;
static struct psdscan_sta_8723b_1ant gl_psd_scan_8723b_1ant;
static struct psdscan_sta_8723b_1ant *psd_scan = &gl_psd_scan_8723b_1ant;
const char *const glbt_info_src_8723b_1ant[] = {
"BT Info[wifi fw]",
"BT Info[bt rsp]",
@ -192,7 +191,6 @@ void halbtc8723b1ant_limited_rx(IN struct btc_coexist *btcoexist,
/* real update aggregation setting */
btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
}
void halbtc8723b1ant_query_bt_info(IN struct btc_coexist *btcoexist)
@ -273,7 +271,6 @@ void halbtc8723b1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
}
void halbtc8723b1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
{
s32 wifi_rssi = 0;
@ -364,7 +361,6 @@ void halbtc8723b1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
coex_sta->pre_ccklock = coex_sta->cck_lock;
}
boolean halbtc8723b1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist)
@ -395,7 +391,6 @@ boolean halbtc8723b1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist)
return true;
}
}
return false;
@ -586,8 +581,6 @@ void halbtc8723b1ant_set_coex_table(IN struct btc_coexist *btcoexist,
btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
}
void halbtc8723b1ant_coex_table(IN struct btc_coexist *btcoexist,
IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
IN u32 val0x6c8, IN u8 val0x6cc)
@ -967,7 +960,6 @@ void halbtc8723b1ant_set_ant_path(IN struct btc_coexist *btcoexist,
u32tmp |= BIT(24);
btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist,
0x948);
if ((u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240))
@ -977,7 +969,6 @@ void halbtc8723b1ant_set_ant_path(IN struct btc_coexist *btcoexist,
btcoexist->btc_write_4byte(btcoexist, 0x948,
0x0);
if (board_info->btdm_ant_pos ==
BTC_ANTENNA_AT_MAIN_PORT) {
/* tell firmware "no antenna inverse" */
@ -1175,7 +1166,6 @@ void halbtc8723b1ant_ps_tdma_check_for_power_save_state(
}
}
void halbtc8723b1ant_power_save_state(IN struct btc_coexist *btcoexist,
IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
{
@ -1219,7 +1209,6 @@ void halbtc8723b1ant_power_save_state(IN struct btc_coexist *btcoexist,
}
}
void halbtc8723b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
{
@ -1265,7 +1254,6 @@ void halbtc8723b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
}
void halbtc8723b1ant_ps_tdma(IN struct btc_coexist *btcoexist,
IN boolean force_exec, IN boolean turn_on, IN u8 type)
{
@ -1355,11 +1343,6 @@ void halbtc8723b1ant_ps_tdma(IN struct btc_coexist *btcoexist,
ps_tdma_byte3_val = 0x10; /* tx-pause at BT-slot */
ps_tdma_byte4_val =
0x10; /* 0x778 = d/1 toggle, no dynamic slot */
#if 0
if (!wifi_busy)
ps_tdma_byte4_val = ps_tdma_byte4_val |
0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
#endif
} else { /* native power save case */
ps_tdma_byte0_val = 0x61; /* no null-pkt */
ps_tdma_byte3_val = 0x11; /* no tx-pause at BT-slot */
@ -1380,7 +1363,6 @@ void halbtc8723b1ant_ps_tdma(IN struct btc_coexist *btcoexist,
0x60; /* set antenna no toggle, control by antenna diversity */
}
if (turn_on) {
switch (type) {
default:
@ -1839,7 +1821,6 @@ void halbtc8723b1ant_tdma_duration_adjust_for_acl(IN struct btc_coexist
}
}
/* *********************************************
*
* Non-Software Coex Mechanism start
@ -1853,7 +1834,6 @@ void halbtc8723b1ant_action_bt_whck_test(IN struct btc_coexist *btcoexist)
halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
}
void halbtc8723b1ant_action_hs(IN struct btc_coexist *btcoexist)
{
halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
@ -2189,7 +2169,6 @@ void halbtc8723b1ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
&ap_enable);
btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
/* tdma and coex table */
if (!wifi_busy) {
if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
@ -2396,7 +2375,6 @@ void halbtc8723b1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
return;
}
if (!wifi_connected) {
boolean scan = false, link = false, roam = false;
@ -2446,7 +2424,6 @@ void halbtc8723b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
psd_scan->ant_det_is_ant_det_available = false;
/* Give bt_coex_supported_version the default value */
coex_sta->bt_coex_supported_version = 0;
@ -2465,7 +2442,6 @@ void halbtc8723b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
/* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, 0x1); */ /*BT select s0/s1 is controlled by WiFi */
halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
@ -2493,9 +2469,6 @@ void halbtc8723b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
}
/* Donot remove optimize off flag, otherwise antenna detection would trigger BT collapsed */
#ifdef PLATFORM_WINDOWS
#pragma optimize("", off)
#endif
void halbtc8723b1ant_mechanism_switch(IN struct btc_coexist *btcoexist,
IN boolean bSwitchTo2Antenna)
{
@ -2520,52 +2493,6 @@ void halbtc8723b1ant_mechanism_switch(IN struct btc_coexist *btcoexist,
BTC_TRACE(trace_buf);
}
#if 0
if (bSwitchTo2Antenna) { /* 1-Ant -> 2-Ant */
/* un-lock TRx Mask setup for 8723b f-cut */
btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd, 0x80, 0x1);
btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf, 0x1, 0x1);
/* WiFi TRx Mask on */
btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
0x0);
/* BT TRx Mask un-lock 0x2c[0], 0x30[0] = 1 */
btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x2c,
0x7c45);
btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x30,
0x7c45);
/* BT TRx Mask on */
btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x1);
halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
FORCE_EXEC, false, false);
} else {
/* WiFi TRx Mask on */
btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
0x780);
/* lock TRx Mask setup for 8723b f-cut */
btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd, 0x80, 0x0);
btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf, 0x1, 0x0);
/* BT TRx Mask on */
btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x15);
/* BT TRx Mask ock 0x2c[0], 0x30[0] = 0 */
btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x2c,
0x7c44);
btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x30,
0x7c44);
halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
FORCE_EXEC, false, false);
}
#endif
}
u32 halbtc8723b1ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val)
@ -2590,7 +2517,6 @@ u32 halbtc8723b1ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val)
shiftcount++;
}
val_integerd_b = shiftcount + 1;
tmp2 = 1;
@ -2609,7 +2535,6 @@ u32 halbtc8723b1ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val)
return result;
}
void halbtc8723b1ant_psd_show_antenna_detect_result(IN struct btc_coexist
@ -2698,7 +2623,6 @@ void halbtc8723b1ant_psd_show_antenna_detect_result(IN struct btc_coexist
}
CL_PRINTF(cli_buf);
CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
"Ant Detect Total Count", psd_scan->ant_det_try_count);
CL_PRINTF(cli_buf);
@ -2752,7 +2676,6 @@ void halbtc8723b1ant_psd_show_antenna_detect_result(IN struct btc_coexist
"PSD Scan Peak Freq", psd_scan->ant_det_peak_freq);
CL_PRINTF(cli_buf);
CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "TFBGA Package",
(board_info->tfbga_package) ? "Yes" : "No");
CL_PRINTF(cli_buf);
@ -2886,7 +2809,6 @@ void halbtc8723b1ant_psd_showdata(IN struct btc_coexist *btcoexist)
} while ((i <= 8) && (m <= psd_scan->psd_stop_point));
do {
psd_rep1 = psd_scan->psd_report_max_hold[n] /
100;
@ -2947,7 +2869,6 @@ void halbtc8723b1ant_psd_showdata(IN struct btc_coexist *btcoexist)
}
}
}
void halbtc8723b1ant_psd_max_holddata(IN struct btc_coexist *btcoexist,
@ -2990,7 +2911,6 @@ void halbtc8723b1ant_psd_max_holddata(IN struct btc_coexist *btcoexist,
}
}
u32 halbtc8723b1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point)
@ -3024,7 +2944,6 @@ u32 halbtc8723b1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point)
return psd_report;
}
boolean halbtc8723b1ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points,
IN u32 avgnum, IN u32 loopcnt)
@ -3056,7 +2975,6 @@ boolean halbtc8723b1ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
psd_scan->real_offset = offset;
psd_scan->real_span = span;
points1 = psd_scan->psd_point;
delta_freq_per_point = psd_scan->psd_band_width /
psd_scan->psd_point;
@ -3141,7 +3059,6 @@ boolean halbtc8723b1ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
0x18, 0x3ff, (cent_freq - 2412) / 5 +
1); /* WiFi TRx Mask on */
/* Set RF Rx filter corner */
btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
0xfffff, 0x3e4);
@ -3214,7 +3131,6 @@ boolean halbtc8723b1ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
n = i - psd_scan->psd_start_base;
psd_scan->psd_report[n] = tmp;
halbtc8723b1ant_psd_max_holddata(
btcoexist, j);
@ -3273,8 +3189,6 @@ boolean halbtc8723b1ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
} while (!outloop);
psd_scan->is_psd_running = false;
BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
@ -3640,8 +3554,6 @@ void halbtc8723b1ant_psd_antenna_detection(IN struct btc_coexist *btcoexist,
} while (!outloop);
}
void halbtc8723b1ant_psd_antenna_detection_check(IN struct btc_coexist
@ -3655,7 +3567,6 @@ void halbtc8723b1ant_psd_antenna_detection_check(IN struct btc_coexist
btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
/* psd_scan->ant_det_bt_tx_time = 20; */
psd_scan->ant_det_bt_tx_time =
BT_8723B_1ANT_ANTDET_BTTXTIME; /* 0.42ms*50 = 20ms (0.42ms = 1 PSD sweep) */
@ -3717,7 +3628,6 @@ void halbtc8723b1ant_psd_antenna_detection_check(IN struct btc_coexist
}
/* ************************************************************
* work around function start with wa_halbtc8723b1ant_
* ************************************************************
@ -3731,7 +3641,6 @@ void ex_halbtc8723b1ant_power_on_setting(IN struct btc_coexist *btcoexist)
u16 u16tmp = 0x0;
u32 value;
BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
"xxxxxxxxxxxxxxxx Execute 8723b 1-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n");
BTC_TRACE(trace_buf);
@ -3742,7 +3651,6 @@ void ex_halbtc8723b1ant_power_on_setting(IN struct btc_coexist *btcoexist)
board_info->btdm_ant_num_by_ant_det);
BTC_TRACE(trace_buf);
btcoexist->stop_coex_dm = true;
btcoexist->btc_write_1byte(btcoexist, 0x67, 0x20);
@ -3997,7 +3905,6 @@ void ex_halbtc8723b1ant_display_coex_info(IN struct btc_coexist *btcoexist)
}
}
if (btcoexist->manual_control)
CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
"============[mechanisms] (before Manual)============");
@ -4169,7 +4076,6 @@ void ex_halbtc8723b1ant_display_coex_info(IN struct btc_coexist *btcoexist)
btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
}
void ex_halbtc8723b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
{
if (btcoexist->manual_control || btcoexist->stop_coex_dm)
@ -4246,7 +4152,6 @@ void ex_halbtc8723b1ant_scan_notify(IN struct btc_coexist *btcoexist,
u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765);
u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67);
BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
"[BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n",
u32tmp, u8tmpa, u8tmpb);
@ -4538,9 +4443,6 @@ void ex_halbtc8723b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
}
/* Donot remove optimize off flag, otherwise antenna detection would trigger BT collapsed */
#ifdef PLATFORM_WINDOWS
#pragma optimize("", off)
#endif
void ex_halbtc8723b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
IN u8 *tmp_buf, IN u8 length)
{
@ -4620,7 +4522,6 @@ void ex_halbtc8723b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
return;
}
#if BT_8723B_1ANT_ANTDET_ENABLE
#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE
if ((board_info->btdm_ant_det_finish) &&
@ -4633,21 +4534,6 @@ void ex_halbtc8723b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
"############# [BTCoex], BT TRx Mask off for BT Info Notify\n");
BTC_TRACE(trace_buf);
#if 0
/* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */
BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
"[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x1\n");
BTC_TRACE(trace_buf);
/* BT TRx Mask un-lock 0x2c[0], 0x30[0] = 1 */
btcoexist->btc_set_bt_reg(btcoexist,
BTC_BT_REG_RF, 0x2c, 0x7c45);
btcoexist->btc_set_bt_reg(btcoexist,
BTC_BT_REG_RF, 0x30, 0x7c45);
btcoexist->btc_set_bt_reg(btcoexist,
BTC_BT_REG_RF, 0x3c, 0x1);
#endif
}
} else
#endif
@ -4662,23 +4548,6 @@ void ex_halbtc8723b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
"############# [BTCoex], BT TRx Mask on for BT Info Notify\n");
BTC_TRACE(trace_buf);
#if 0
/* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */
BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
"[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n");
BTC_TRACE(trace_buf);
btcoexist->btc_set_bt_reg(btcoexist,
BTC_BT_REG_RF,
0x3c, 0x15);
/* BT TRx Mask lock 0x2c[0], 0x30[0] = 0 */
btcoexist->btc_set_bt_reg(btcoexist,
BTC_BT_REG_RF,
0x2c, 0x7c44);
btcoexist->btc_set_bt_reg(btcoexist,
BTC_BT_REG_RF,
0x30, 0x7c44);
#endif
}
}
@ -4852,7 +4721,6 @@ void ex_halbtc8723b1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67);
u8tmpc = btcoexist->btc_read_1byte(btcoexist, 0x76e);
BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
"############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x, 0x76e=0x%x\n",
u32tmp, u8tmpa, u8tmpb, u8tmpc);
@ -4932,7 +4800,6 @@ void ex_halbtc8723b1ant_periodical(IN struct btc_coexist *btcoexist)
halbtc8723b1ant_monitor_bt_enable_disable(btcoexist);
if (halbtc8723b1ant_is_wifi_status_changed(btcoexist) ||
coex_dm->auto_tdma_adjust ||
btcoexist->bt_info.bt_enable_disable_change)
@ -4962,9 +4829,6 @@ void ex_halbtc8723b1ant_periodical(IN struct btc_coexist *btcoexist)
}
/* Donot remove optimize off flag, otherwise antenna detection would trigger BT collapsed */
#ifdef PLATFORM_WINDOWS
#pragma optimize("", off)
#endif
void ex_halbtc8723b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
{
@ -4999,7 +4863,6 @@ void ex_halbtc8723b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
"xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Success!!\n");
BTC_TRACE(trace_buf);
#if 1
if (board_info->btdm_ant_num_by_ant_det == 2)
halbtc8723b1ant_mechanism_switch(
@ -5029,12 +4892,10 @@ void ex_halbtc8723b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
}
#endif
/*
btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
psd_scan->ant_det_bt_tx_time = seconds;
psd_scan->ant_det_bt_le_channel = cent_freq;
@ -5087,7 +4948,6 @@ void ex_halbtc8723b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
*/
}
void ex_halbtc8723b1ant_display_ant_detection(IN struct btc_coexist *btcoexist)
{
#if BT_8723B_1ANT_ANTDET_ENABLE
@ -5108,6 +4968,3 @@ void ex_halbtc8723b1ant_display_ant_detection(IN struct btc_coexist *btcoexist)
#endif
#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */

147
hal/btc/halbtc8723d1ant.c
View file

@ -27,7 +27,6 @@ static struct coex_sta_8723d_1ant *coex_sta = &glcoex_sta_8723d_1ant;
static struct psdscan_sta_8723d_1ant gl_psd_scan_8723d_1ant;
static struct psdscan_sta_8723d_1ant *psd_scan = &gl_psd_scan_8723d_1ant;
const char *const glbt_info_src_8723d_1ant[] = {
"BT Info[wifi fw]",
"BT Info[bt rsp]",
@ -48,7 +47,6 @@ u32 glcoex_ver_date_8723d_1ant = 20161027;
u32 glcoex_ver_8723d_1ant = 0x0f;
u32 glcoex_ver_btdesired_8723d_1ant = 0x0d;
/* ************************************************************
* local function proto type if needed
* ************************************************************
@ -329,7 +327,6 @@ void halbtc8723d1ant_limited_rx(IN struct btc_coexist *btcoexist,
/* real update aggregation setting */
btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
}
void halbtc8723d1ant_query_bt_info(IN struct btc_coexist *btcoexist)
@ -571,8 +568,6 @@ void halbtc8723d1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
#endif
}
boolean halbtc8723d1ant_is_wifibt_status_changed(IN struct btc_coexist
*btcoexist)
{
@ -653,7 +648,6 @@ void halbtc8723d1ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
boolean bt_hs_on = false;
boolean bt_busy = false;
coex_sta->num_of_profile = 0;
/* set link exist status */
@ -788,7 +782,6 @@ void halbtc8723d1ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
}
void halbtc8723d1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist,
IN u8 type)
{
@ -1087,16 +1080,7 @@ void halbtc8723d1ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
halbtc8723d1ant_set_fw_low_penalty_ra(btcoexist,
coex_dm->cur_low_penalty_ra);
#if 0
if (low_penalty_ra)
btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 15);
else
btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0);
#endif
coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
#endif
}
void halbtc8723d1ant_write_score_board(
@ -1113,7 +1097,6 @@ void halbtc8723d1ant_write_score_board(
else
originalval = originalval & (~bitpos);
btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval);
}
@ -1144,29 +1127,11 @@ void halbtc8723d1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
u16 u16tmp;
/* This function check if bt is disabled */
#if 0
if (coex_sta->high_priority_tx == 0 &&
coex_sta->high_priority_rx == 0 &&
coex_sta->low_priority_tx == 0 &&
coex_sta->low_priority_rx == 0)
bt_active = false;
if (coex_sta->high_priority_tx == 0xffff &&
coex_sta->high_priority_rx == 0xffff &&
coex_sta->low_priority_tx == 0xffff &&
coex_sta->low_priority_rx == 0xffff)
bt_active = false;
#else
/* Read BT on/off status from scoreboard[1], enable this only if BT patch support this feature */
halbtc8723d1ant_read_score_board(btcoexist, &u16tmp);
bt_active = u16tmp & BIT(1);
#endif
if (bt_active) {
bt_disable_cnt = 0;
bt_disabled = false;
@ -1200,8 +1165,6 @@ void halbtc8723d1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
}
void halbtc8723d1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist,
boolean isenable)
{
@ -1246,7 +1209,6 @@ u32 halbtc8723d1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist,
{
u32 j = 0;
/* wait for ready bit before access 0x7c0 */
btcoexist->btc_write_4byte(btcoexist, 0x7c0, 0x800F0000 | reg_addr);
@ -1256,7 +1218,6 @@ u32 halbtc8723d1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist,
0x7c3)&BIT(5)) == 0) &&
(j < BT_8723D_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
return btcoexist->btc_read_4byte(btcoexist,
0x7c8); /* get read data */
@ -1268,7 +1229,6 @@ void halbtc8723d1ant_ltecoex_indirect_write_reg(IN struct btc_coexist
{
u32 val, i = 0, j = 0, bitpos = 0;
if (bit_mask == 0x0)
return;
if (bit_mask == 0xffffffff) {
@ -1282,7 +1242,6 @@ void halbtc8723d1ant_ltecoex_indirect_write_reg(IN struct btc_coexist
0x7c3)&BIT(5)) == 0) &&
(j < BT_8723D_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
btcoexist->btc_write_4byte(btcoexist, 0x7c0,
0xc00F0000 | reg_addr);
} else {
@ -1308,7 +1267,6 @@ void halbtc8723d1ant_ltecoex_indirect_write_reg(IN struct btc_coexist
0x7c3)&BIT(5)) == 0) &&
(j < BT_8723D_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
btcoexist->btc_write_4byte(btcoexist, 0x7c0,
0xc00F0000 | reg_addr);
@ -1370,7 +1328,6 @@ void halbtc8723d1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist,
0x38, 0xffffffff, val);
}
void halbtc8723d1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist,
IN u8 control_block, IN boolean sw_control, IN u8 state)
{
@ -1403,7 +1360,6 @@ void halbtc8723d1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist,
0xffffffff, val);
}
void halbtc8723d1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist,
IN u8 table_type, IN u16 table_content)
{
@ -1422,10 +1378,8 @@ void halbtc8723d1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist,
halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */
}
void halbtc8723d1ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist,
IN u8 table_type, IN u8 table_content)
{
@ -1487,7 +1441,6 @@ void halbtc8723d1ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist,
btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter);
}
void halbtc8723d1ant_set_coex_table(IN struct btc_coexist *btcoexist,
IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
{
@ -1730,7 +1683,6 @@ void halbtc8723d1ant_power_save_state(IN struct btc_coexist *btcoexist,
}
}
void halbtc8723d1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
{
@ -1779,7 +1731,6 @@ void halbtc8723d1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
0x0);
}
h2c_parameter[0] = real_byte1;
h2c_parameter[1] = byte2;
h2c_parameter[2] = byte3;
@ -1795,7 +1746,6 @@ void halbtc8723d1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
}
void halbtc8723d1ant_ps_tdma(IN struct btc_coexist *btcoexist,
IN boolean force_exec, IN boolean turn_on, IN u8 type)
{
@ -1805,15 +1755,9 @@ void halbtc8723d1ant_ps_tdma(IN struct btc_coexist *btcoexist,
static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0;
static boolean pre_wifi_busy = false;
#if BT_8723D_1ANT_ANTDET_ENABLE
if (board_info->btdm_ant_num_by_ant_det == 2) {
#if 0
if (turn_on)
type = type +
100;
#endif
}
#endif
@ -1861,7 +1805,6 @@ void halbtc8723d1ant_ps_tdma(IN struct btc_coexist *btcoexist,
BTC_TRACE(trace_buf);
}
if (turn_on) {
switch (type) {
default:
@ -2082,7 +2025,6 @@ void halbtc8723d1ant_ps_tdma(IN struct btc_coexist *btcoexist,
coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
}
void halbtc8723d1ant_set_ant_path(IN struct btc_coexist *btcoexist,
IN u8 ant_pos_type, IN boolean force_exec,
IN u8 phase)
@ -2149,7 +2091,6 @@ void halbtc8723d1ant_set_ant_path(IN struct btc_coexist *btcoexist,
coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type;
switch (phase) {
case BT_8723D_1ANT_PHASE_COEX_POWERON:
/* Set Path control to WL */
@ -2316,7 +2257,6 @@ void halbtc8723d1ant_set_ant_path(IN struct btc_coexist *btcoexist,
}
}
/* Set Path control to WL */
/* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1); */
@ -2390,7 +2330,6 @@ void halbtc8723d1ant_set_ant_path(IN struct btc_coexist *btcoexist,
break;
}
is_hw_ant_div_on = board_info->ant_div_cfg;
if ((is_hw_ant_div_on) && (phase != BT_8723D_1ANT_PHASE_ANTENNA_DET))
@ -2442,7 +2381,6 @@ void halbtc8723d1ant_set_ant_path(IN struct btc_coexist *btcoexist,
}
}
#if BT_8723D_1ANT_COEX_DBG
u32tmp1 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
@ -2464,7 +2402,6 @@ void halbtc8723d1ant_set_ant_path(IN struct btc_coexist *btcoexist,
}
boolean halbtc8723d1ant_is_common_action(IN struct btc_coexist *btcoexist)
{
boolean common = false, wifi_connected = false, wifi_busy = false;
@ -2525,7 +2462,6 @@ boolean halbtc8723d1ant_is_common_action(IN struct btc_coexist *btcoexist)
return common;
}
/* *********************************************
*
* Non-Software Coex Mechanism start
@ -2592,7 +2528,6 @@ void halbtc8723d1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link);
btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam);
if ((coex_sta->bt_create_connection) && ((wifi_link) || (wifi_roam)
|| (wifi_scan) || (wifi_busy) || (coex_sta->wifi_is_high_pri_task))) {
@ -2634,7 +2569,6 @@ void halbtc8723d1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
}
}
void halbtc8723d1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist
*btcoexist)
{
@ -2650,7 +2584,6 @@ void halbtc8723d1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist
btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
if (bt_link_info->sco_exist) {
halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC,
true, 5);
@ -2700,7 +2633,6 @@ void halbtc8723d1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist
}
}
void halbtc8723d1ant_action_wifi_only(IN struct btc_coexist *btcoexist)
{
halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
@ -2930,7 +2862,6 @@ void halbtc8723d1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist)
halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
}
void halbtc8723d1ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
{
struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
@ -2960,7 +2891,6 @@ void halbtc8723d1ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
halbtc8723d1ant_action_bt_idle(btcoexist);
}
void halbtc8723d1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist)
{
u8 algorithm = 0;
@ -3032,7 +2962,6 @@ void halbtc8723d1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist)
}
}
void halbtc8723d1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
{
struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
@ -3245,7 +3174,6 @@ void halbtc8723d1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
}
}
void halbtc8723d1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
{
/* force to reset coex mechanism */
@ -3275,7 +3203,6 @@ void halbtc8723d1ant_init_hw_config(IN struct btc_coexist *btcoexist,
struct btc_board_info *board_info = &btcoexist->board_info;
u8 i = 0;
BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
"[BTCoex], 1Ant Init HW Config!!\n");
BTC_TRACE(trace_buf);
@ -3300,7 +3227,6 @@ void halbtc8723d1ant_init_hw_config(IN struct btc_coexist *btcoexist,
BTC_TRACE(trace_buf);
#endif
coex_sta->bt_coex_supported_feature = 0;
coex_sta->bt_coex_supported_version = 0;
coex_sta->bt_ble_scan_type = 0;
@ -3408,7 +3334,6 @@ u32 halbtc8723d1ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val)
}
}
val_integerd_b = shiftcount + 1;
tmp2 = 1;
@ -3427,7 +3352,6 @@ u32 halbtc8723d1ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val)
return result;
}
void halbtc8723d1ant_psd_show_antenna_detect_result(IN struct btc_coexist
@ -3604,7 +3528,6 @@ void halbtc8723d1ant_psd_show_antenna_detect_result(IN struct btc_coexist
"PSD Scan Peak Freq", psd_scan->ant_det_peak_freq);
CL_PRINTF(cli_buf);
CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "TFBGA Package",
(board_info->tfbga_package) ? "Yes" : "No");
CL_PRINTF(cli_buf);
@ -3615,8 +3538,6 @@ void halbtc8723d1ant_psd_show_antenna_detect_result(IN struct btc_coexist
}
void halbtc8723d1ant_psd_showdata(IN struct btc_coexist *btcoexist)
{
u8 *cli_buf = btcoexist->cli_buf;
@ -3743,7 +3664,6 @@ void halbtc8723d1ant_psd_showdata(IN struct btc_coexist *btcoexist)
} while ((i <= 8) && (m <= psd_scan->psd_stop_point));
do {
psd_rep1 = psd_scan->psd_report_max_hold[n] /
100;
@ -3806,13 +3726,8 @@ void halbtc8723d1ant_psd_showdata(IN struct btc_coexist *btcoexist)
}
}
}
#ifdef PLATFORM_WINDOWS
#pragma optimize("", off)
#endif
void halbtc8723d1ant_psd_maxholddata(IN struct btc_coexist *btcoexist,
IN u32 gen_count)
{
@ -3844,10 +3759,7 @@ void halbtc8723d1ant_psd_maxholddata(IN struct btc_coexist *btcoexist,
psd_scan->psd_loop_max_value[gen_count - 1] = loop_val_max;
}
#ifdef PLATFORM_WINDOWS
#pragma optimize("", off)
#endif
u32 halbtc8723d1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point)
32 halbtc8723d1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point)
{
/* reg 0x808[9:0]: FFT data x */
/* reg 0x808[22]: 0-->1 to get 1 FFT data y */
@ -3878,9 +3790,6 @@ u32 halbtc8723d1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point)
return psd_report;
}
#ifdef PLATFORM_WINDOWS
#pragma optimize("", off)
#endif
boolean halbtc8723d1ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points,
IN u32 avgnum, IN u32 loopcnt)
@ -3913,7 +3822,6 @@ boolean halbtc8723d1ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
psd_scan->real_offset = offset;
psd_scan->real_span = span;
points1 = psd_scan->psd_point;
delta_freq_per_point = psd_scan->psd_band_width /
psd_scan->psd_point;
@ -4013,7 +3921,6 @@ boolean halbtc8723d1ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1d,
0xfffff, 0x2e);
/* Set RF mode = Rx, RF Gain = 0x320a0 */
btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x0,
0xfffff, 0x320a0);
@ -4210,9 +4117,6 @@ boolean halbtc8723d1ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
}
#ifdef PLATFORM_WINDOWS
#pragma optimize("", off)
#endif
boolean halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist
*btcoexist)
{
@ -4271,15 +4175,6 @@ boolean halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist
break;
}
}
#if 0
wlpsd_sweep_count = bt_tx_time * 238 /
100; /* bt_tx_time/0.42 */
wlpsd_sweep_count = wlpsd_sweep_count / 5;
if (wlpsd_sweep_count % 5 != 0)
wlpsd_sweep_count = (wlpsd_sweep_count /
5 + 1) * 5;
#endif
BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
"xxxxxxxxxxxxxxxx AntennaDetect(), BT_LETxTime=%d, BT_LECh = %d\n",
bt_tx_time, bt_le_channel);
@ -4424,16 +4319,6 @@ boolean halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist
#if 1
psd_scan->ant_det_psd_scan_peak_val =
psd_scan->psd_max_value;
#endif
#if 0
psd_scan->ant_det_psd_scan_peak_val =
((psd_scan->psd_max_value - psd_scan->psd_avg_value) <
800) ?
psd_scan->psd_max_value : ((
psd_scan->psd_max_value -
psd_scan->psd_max_value2 <= 300) ?
psd_scan->psd_avg_value :
psd_scan->psd_max_value2);
#endif
psd_scan->ant_det_psd_scan_peak_freq =
psd_scan->psd_max_value_point;
@ -4594,9 +4479,6 @@ boolean halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist
}
#ifdef PLATFORM_WINDOWS
#pragma optimize("", off)
#endif
boolean halbtc8723d1ant_psd_antenna_detection_check(IN struct btc_coexist
*btcoexist)
{
@ -4654,8 +4536,6 @@ boolean halbtc8723d1ant_psd_antenna_detection_check(IN struct btc_coexist
}
/* ************************************************************
* work around function start with wa_halbtc8723d1ant_
* ************************************************************
@ -5020,7 +4900,6 @@ void ex_halbtc8723d1ant_display_coex_info(IN struct btc_coexist *btcoexist)
}
}
if (btcoexist->manual_control)
CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
"============[mechanisms] (before Manual)============");
@ -5244,7 +5123,6 @@ void ex_halbtc8723d1ant_display_coex_info(IN struct btc_coexist *btcoexist)
btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
}
void ex_halbtc8723d1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
{
if (btcoexist->manual_control || btcoexist->stop_coex_dm)
@ -5509,7 +5387,6 @@ void ex_halbtc8723d1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
btcoexist->stop_coex_dm)
return;
btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
&under_4way);
@ -5703,7 +5580,6 @@ void ex_halbtc8723d1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
BTC_MEDIA_DISCONNECT);
}
/* If Ignore_WLanAct && not SetUp_Link or Role_Switch */
if ((coex_sta->bt_info_ext & BIT(3)) &&
(!(coex_sta->bt_info_ext & BIT(2))) &&
@ -5748,8 +5624,6 @@ void ex_halbtc8723d1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
halbtc8723d1ant_run_coexist_mechanism(btcoexist);
}
void ex_halbtc8723d1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
IN u8 type)
{
@ -5857,7 +5731,6 @@ void ex_halbtc8723d1ant_pnp_notify(IN struct btc_coexist *btcoexist,
}
}
void ex_halbtc8723d1ant_coex_dm_reset(IN struct btc_coexist *btcoexist)
{
BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
@ -5986,15 +5859,6 @@ void ex_halbtc8723d1ant_periodical(IN struct btc_coexist *btcoexist)
board_info->antdetval = psd_scan->ant_det_psd_scan_peak_val/100;
value = board_info->antdetval;
#ifdef PLATFORM_WINDOWS
{
PWCHAR registryName;
registryName = L"antdetval";
PlatformWriteCommonDwordRegistry(registryName, &value);
}
#endif
}
}
@ -6004,7 +5868,6 @@ void ex_halbtc8723d1ant_periodical(IN struct btc_coexist *btcoexist)
if (halbtc8723d1ant_is_wifibt_status_changed(btcoexist))
halbtc8723d1ant_run_coexist_mechanism(btcoexist);
}
void ex_halbtc8723d1ant_set_antenna_notify(IN struct btc_coexist *btcoexist,
@ -6027,9 +5890,6 @@ void ex_halbtc8723d1ant_set_antenna_notify(IN struct btc_coexist *btcoexist,
}
}
#ifdef PLATFORM_WINDOWS
#pragma optimize("", off)
#endif
void ex_halbtc8723d1ant_antenna_detection(IN struct btc_coexist *btcoexist,
IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
{
@ -6185,10 +6045,8 @@ void ex_halbtc8723d1ant_antenna_detection(IN struct btc_coexist *btcoexist,
}
#endif
}
void ex_halbtc8723d1ant_display_ant_detection(IN struct btc_coexist *btcoexist)
{
#if BT_8723D_1ANT_ANTDET_ENABLE
@ -6208,17 +6066,14 @@ void ex_halbtc8723d1ant_antenna_isolation(IN struct btc_coexist *btcoexist,
IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
{
}
void ex_halbtc8723d1ant_psd_scan(IN struct btc_coexist *btcoexist,
IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
{
}
#endif
#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */

218
hal/btc/halbtc8723d2ant.c
View file

@ -47,7 +47,6 @@ u32 glcoex_ver_date_8723d_2ant = 20161027;
u32 glcoex_ver_8723d_2ant = 0x0f;
u32 glcoex_ver_btdesired_8723d_2ant = 0x0d;
/* ************************************************************
* local function proto type if needed
* ************************************************************
@ -178,52 +177,18 @@ void halbtc8723d2ant_coex_switch_threshold(IN struct btc_coexist *btcoexist,
{
s8 interference_wl_tx = 0, interference_bt_tx = 0;
interference_wl_tx = BT_8723D_2ANT_WIFI_MAX_TX_POWER -
isolation_measuared;
interference_bt_tx = BT_8723D_2ANT_BT_MAX_TX_POWER -
isolation_measuared;
coex_sta->wifi_coex_thres = BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES1;
coex_sta->wifi_coex_thres2 = BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES2;
coex_sta->bt_coex_thres = BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES1;
coex_sta->bt_coex_thres2 = BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES2;
/*
coex_sta->wifi_coex_thres = interference_wl_tx + BT_8723D_2ANT_WIFI_SIR_THRES1;
coex_sta->wifi_coex_thres2 = interference_wl_tx + BT_8723D_2ANT_WIFI_SIR_THRES2;
coex_sta->bt_coex_thres = interference_bt_tx + BT_8723D_2ANT_BT_SIR_THRES1;
coex_sta->bt_coex_thres2 = interference_bt_tx + BT_8723D_2ANT_BT_SIR_THRES2;
*/
/*
if ( BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 < (isolation_measuared -
BT_8723D_2ANT_DEFAULT_ISOLATION) )
coex_sta->wifi_coex_thres = BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES1;
else
coex_sta->wifi_coex_thres = BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 - (isolation_measuared -
BT_8723D_2ANT_DEFAULT_ISOLATION);
if ( BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES1 < (isolation_measuared -
BT_8723D_2ANT_DEFAULT_ISOLATION) )
coex_sta->bt_coex_thres = BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES1;
else
coex_sta->bt_coex_thres = BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES1 - (isolation_measuared -
BT_8723D_2ANT_DEFAULT_ISOLATION);
*/
}
void halbtc8723d2ant_limited_rx(IN struct btc_coexist *btcoexist,
IN boolean force_exec, IN boolean rej_ap_agg_pkt,
IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
@ -250,7 +215,6 @@ void halbtc8723d2ant_query_bt_info(IN struct btc_coexist *btcoexist)
{
u8 h2c_parameter[1] = {0};
h2c_parameter[0] |= BIT(0); /* trigger */
btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
@ -472,8 +436,6 @@ void halbtc8723d2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
#endif
}
boolean halbtc8723d2ant_is_wifibt_status_changed(IN struct btc_coexist
*btcoexist)
{
@ -555,7 +517,6 @@ void halbtc8723d2ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
boolean bt_hs_on = false;
boolean bt_busy = false;
coex_sta->num_of_profile = 0;
/* set link exist status */
@ -799,7 +760,6 @@ void halbtc8723d2ant_set_fw_low_penalty_ra(IN struct btc_coexist
void halbtc8723d2ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
IN boolean force_exec, IN boolean low_penalty_ra)
{
#if 1
coex_dm->cur_low_penalty_ra = low_penalty_ra;
if (!force_exec) {
@ -810,15 +770,7 @@ void halbtc8723d2ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
halbtc8723d2ant_set_fw_low_penalty_ra(btcoexist,
coex_dm->cur_low_penalty_ra);
#if 0
if (low_penalty_ra)
btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 15);
else
btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0);
#endif
coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
#endif
}
void halbtc8723d2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
@ -863,7 +815,6 @@ void halbtc8723d2ant_write_score_board(
else
originalval = originalval & (~bitpos);
btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval);
}
@ -878,7 +829,6 @@ void halbtc8723d2ant_read_score_board(
0xaa)) & 0x7fff;
}
void halbtc8723d2ant_post_state_to_bt(
IN struct btc_coexist *btcoexist,
IN u16 type,
@ -897,29 +847,12 @@ void halbtc8723d2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
u16 u16tmp;
/* This function check if bt is disabled */
#if 0
if (coex_sta->high_priority_tx == 0 &&
coex_sta->high_priority_rx == 0 &&
coex_sta->low_priority_tx == 0 &&
coex_sta->low_priority_rx == 0)
bt_active = false;
if (coex_sta->high_priority_tx == 0xffff &&
coex_sta->high_priority_rx == 0xffff &&
coex_sta->low_priority_tx == 0xffff &&
coex_sta->low_priority_rx == 0xffff)
bt_active = false;
#else
/* Read BT on/off status from scoreboard[1], enable this only if BT patch support this feature */
halbtc8723d2ant_read_score_board(btcoexist, &u16tmp);
bt_active = u16tmp & BIT(1);
#endif
if (bt_active) {
bt_disable_cnt = 0;
bt_disabled = false;
@ -953,8 +886,6 @@ void halbtc8723d2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
}
void halbtc8723d2ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist,
boolean isenable)
{
@ -999,7 +930,6 @@ u32 halbtc8723d2ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist,
{
u32 j = 0;
/* wait for ready bit before access 0x7c0 */
btcoexist->btc_write_4byte(btcoexist, 0x7c0, 0x800F0000 | reg_addr);
@ -1009,7 +939,6 @@ u32 halbtc8723d2ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist,
0x7c3)&BIT(5)) == 0) &&
(j < BT_8723D_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
return btcoexist->btc_read_4byte(btcoexist,
0x7c8); /* get read data */
@ -1021,7 +950,6 @@ void halbtc8723d2ant_ltecoex_indirect_write_reg(IN struct btc_coexist
{
u32 val, i = 0, j = 0, bitpos = 0;
if (bit_mask == 0x0)
return;
if (bit_mask == 0xffffffff) {
@ -1035,7 +963,6 @@ void halbtc8723d2ant_ltecoex_indirect_write_reg(IN struct btc_coexist
0x7c3)&BIT(5)) == 0) &&
(j < BT_8723D_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
btcoexist->btc_write_4byte(btcoexist, 0x7c0,
0xc00F0000 | reg_addr);
} else {
@ -1061,7 +988,6 @@ void halbtc8723d2ant_ltecoex_indirect_write_reg(IN struct btc_coexist
0x7c3)&BIT(5)) == 0) &&
(j < BT_8723D_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
btcoexist->btc_write_4byte(btcoexist, 0x7c0,
0xc00F0000 | reg_addr);
@ -1123,7 +1049,6 @@ void halbtc8723d2ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist,
0x38, 0xffffffff, val);
}
void halbtc8723d2ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist,
IN u8 control_block, IN boolean sw_control, IN u8 state)
{
@ -1174,10 +1099,8 @@ void halbtc8723d2ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist,
halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */
}
void halbtc8723d2ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist,
IN u8 table_type, IN u8 table_content)
{
@ -1202,7 +1125,6 @@ void halbtc8723d2ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist,
halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */
}
void halbtc8723d2ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist,
@ -1468,8 +1390,6 @@ void halbtc8723d2ant_power_save_state(IN struct btc_coexist *btcoexist,
}
}
void halbtc8723d2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
{
@ -1518,7 +1438,6 @@ void halbtc8723d2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
0x0);
}
h2c_parameter[0] = real_byte1;
h2c_parameter[1] = byte2;
h2c_parameter[2] = byte3;
@ -1541,7 +1460,6 @@ void halbtc8723d2ant_ps_tdma(IN struct btc_coexist *btcoexist,
static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0;
struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
coex_dm->cur_ps_tdma_on = turn_on;
coex_dm->cur_ps_tdma = type;
@ -1578,7 +1496,6 @@ void halbtc8723d2ant_ps_tdma(IN struct btc_coexist *btcoexist,
BTC_TRACE(trace_buf);
}
if (turn_on) {
switch (type) {
case 1:
@ -1774,7 +1691,6 @@ void halbtc8723d2ant_set_ant_path(IN struct btc_coexist *btcoexist,
u32 u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0;
u16 u16tmp0 = 0, u16tmp1 = 0;
u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
0x38);
@ -1784,7 +1700,6 @@ void halbtc8723d2ant_set_ant_path(IN struct btc_coexist *btcoexist,
coex_sta->gnt_error_cnt++;
}
#if BT_8723D_2ANT_COEX_DBG
u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0xaa);
@ -1887,7 +1802,6 @@ void halbtc8723d2ant_set_ant_path(IN struct btc_coexist *btcoexist,
}
}
/* Set Path control to WL */
btcoexist->btc_write_1byte_bitmask(btcoexist,
0x67, 0x80, 0x1);
@ -2024,7 +1938,6 @@ void halbtc8723d2ant_set_ant_path(IN struct btc_coexist *btcoexist,
btcoexist,
BT_8723D_2ANT_PCO_WLSIDE);
halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist,
BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
BT_8723D_2ANT_GNT_TYPE_CTRL_BY_PTA,
@ -2139,7 +2052,6 @@ void halbtc8723d2ant_set_ant_path(IN struct btc_coexist *btcoexist,
}
}
#if BT_8723D_2ANT_COEX_DBG
u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
@ -2377,8 +2289,6 @@ u8 halbtc8723d2ant_action_algorithm(IN struct btc_coexist *btcoexist)
return algorithm;
}
void halbtc8723d2ant_action_coex_all_off(IN struct btc_coexist *btcoexist)
{
@ -2412,7 +2322,6 @@ void halbtc8723d2ant_action_bt_hs(IN struct btc_coexist *btcoexist)
u8 wifi_rssi_state2, bt_rssi_state2;
boolean wifi_busy = false, wifi_turbo = false;
btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
&coex_sta->scan_ap_num);
@ -2426,7 +2335,6 @@ void halbtc8723d2ant_action_bt_hs(IN struct btc_coexist *btcoexist)
wifi_turbo = true;
#endif
wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
&prewifi_rssi_state, 2,
coex_sta->wifi_coex_thres , 0);
@ -2464,7 +2372,6 @@ void halbtc8723d2ant_action_bt_hs(IN struct btc_coexist *btcoexist)
halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
} else {
halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
@ -2479,7 +2386,6 @@ void halbtc8723d2ant_action_bt_hs(IN struct btc_coexist *btcoexist)
}
void halbtc8723d2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
{
@ -2488,7 +2394,6 @@ void halbtc8723d2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
boolean wifi_busy = false;
struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
@ -2549,7 +2454,6 @@ void halbtc8723d2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
}
void halbtc8723d2ant_action_bt_relink(IN struct btc_coexist *btcoexist)
{
halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 8);
@ -2595,8 +2499,6 @@ void halbtc8723d2ant_action_bt_idle(IN struct btc_coexist *btcoexist)
}
/* SCO only or SCO+PAN(HS) */
void halbtc8723d2ant_action_sco(IN struct btc_coexist *btcoexist)
{
@ -2629,7 +2531,6 @@ void halbtc8723d2ant_action_sco(IN struct btc_coexist *btcoexist)
bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
coex_sta->bt_coex_thres2 , 0);
if (BTC_RSSI_HIGH(wifi_rssi_state) &&
BTC_RSSI_HIGH(bt_rssi_state)) {
@ -2655,7 +2556,6 @@ void halbtc8723d2ant_action_sco(IN struct btc_coexist *btcoexist)
}
void halbtc8723d2ant_action_hid(IN struct btc_coexist *btcoexist)
{
static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
@ -2668,7 +2568,6 @@ void halbtc8723d2ant_action_hid(IN struct btc_coexist *btcoexist)
boolean wifi_busy = false;
u32 wifi_bw = 1;
btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
@ -2686,7 +2585,6 @@ void halbtc8723d2ant_action_hid(IN struct btc_coexist *btcoexist)
bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
coex_sta->bt_coex_thres2 , 0);
if (BTC_RSSI_HIGH(wifi_rssi_state) &&
BTC_RSSI_HIGH(bt_rssi_state)) {
@ -2747,7 +2645,6 @@ void halbtc8723d2ant_action_hid(IN struct btc_coexist *btcoexist)
}
/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
void halbtc8723d2ant_action_a2dp(IN struct btc_coexist *btcoexist)
{
@ -2760,7 +2657,6 @@ void halbtc8723d2ant_action_a2dp(IN struct btc_coexist *btcoexist)
u8 wifi_rssi_state2, bt_rssi_state2;
boolean wifi_busy = false, wifi_turbo = false;
btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
&coex_sta->scan_ap_num);
@ -2788,7 +2684,6 @@ void halbtc8723d2ant_action_a2dp(IN struct btc_coexist *btcoexist)
bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
coex_sta->bt_coex_thres2 , 0);
if (BTC_RSSI_HIGH(wifi_rssi_state) &&
BTC_RSSI_HIGH(bt_rssi_state)) {
@ -2854,7 +2749,6 @@ void halbtc8723d2ant_action_a2dp(IN struct btc_coexist *btcoexist)
}
void halbtc8723d2ant_action_pan_edr(IN struct btc_coexist *btcoexist)
{
static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
@ -2866,7 +2760,6 @@ void halbtc8723d2ant_action_pan_edr(IN struct btc_coexist *btcoexist)
u8 wifi_rssi_state2, bt_rssi_state2;
boolean wifi_busy = false, wifi_turbo = false;
btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
&coex_sta->scan_ap_num);
@ -2894,19 +2787,6 @@ void halbtc8723d2ant_action_pan_edr(IN struct btc_coexist *btcoexist)
bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
coex_sta->bt_coex_thres2 , 0);
#if 0
halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
coex_dm->is_switch_to_1dot5_ant = false;
halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
#endif
#if 1
if (BTC_RSSI_HIGH(wifi_rssi_state) &&
BTC_RSSI_HIGH(bt_rssi_state)) {
@ -2956,9 +2836,6 @@ void halbtc8723d2ant_action_pan_edr(IN struct btc_coexist *btcoexist)
104);
}
#endif
}
void halbtc8723d2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist)
@ -2991,7 +2868,6 @@ void halbtc8723d2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist)
bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
coex_sta->bt_coex_thres2 , 0);
if (BTC_RSSI_HIGH(wifi_rssi_state) &&
BTC_RSSI_HIGH(bt_rssi_state)) {
@ -3068,7 +2944,6 @@ void halbtc8723d2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist)
}
void halbtc8723d2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
{
static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
@ -3080,7 +2955,6 @@ void halbtc8723d2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
u8 wifi_rssi_state2, bt_rssi_state2;
boolean wifi_busy = false, wifi_turbo = false;
btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
&coex_sta->scan_ap_num);
@ -3094,7 +2968,6 @@ void halbtc8723d2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
wifi_turbo = true;
#endif
wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
&prewifi_rssi_state, 2,
coex_sta->wifi_coex_thres , 0);
@ -3109,7 +2982,6 @@ void halbtc8723d2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
coex_sta->bt_coex_thres2 , 0);
if (BTC_RSSI_HIGH(wifi_rssi_state) &&
BTC_RSSI_HIGH(bt_rssi_state)) {
@ -3175,7 +3047,6 @@ void halbtc8723d2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
}
/* PAN(EDR)+A2DP */
void halbtc8723d2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist)
{
@ -3188,7 +3059,6 @@ void halbtc8723d2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist)
u8 wifi_rssi_state2, bt_rssi_state2;
boolean wifi_busy = false, wifi_turbo = false;
btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
&coex_sta->scan_ap_num);
@ -3202,7 +3072,6 @@ void halbtc8723d2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist)
wifi_turbo = true;
#endif
wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
&prewifi_rssi_state, 2,
coex_sta->wifi_coex_thres , 0);
@ -3284,7 +3153,6 @@ void halbtc8723d2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist)
}
void halbtc8723d2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist)
{
static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
@ -3316,7 +3184,6 @@ void halbtc8723d2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist)
bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
coex_sta->bt_coex_thres2 , 0);
if (BTC_RSSI_HIGH(wifi_rssi_state) &&
BTC_RSSI_HIGH(bt_rssi_state)) {
@ -3384,7 +3251,6 @@ void halbtc8723d2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist)
}
/* HID+A2DP+PAN(EDR) */
void halbtc8723d2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist)
{
@ -3417,7 +3283,6 @@ void halbtc8723d2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist)
bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
coex_sta->bt_coex_thres2 , 0);
if (BTC_RSSI_HIGH(wifi_rssi_state) &&
BTC_RSSI_HIGH(bt_rssi_state)) {
@ -3495,7 +3360,6 @@ void halbtc8723d2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist)
}
void halbtc8723d2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
{
halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
@ -3624,7 +3488,6 @@ void halbtc8723d2ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
}
void halbtc8723d2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
{
u8 algorithm = 0;
@ -3807,7 +3670,6 @@ void halbtc8723d2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
}
}
void halbtc8723d2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
{
BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
@ -3830,7 +3692,6 @@ void halbtc8723d2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
halbtc8723d2ant_query_bt_info(btcoexist);
}
void halbtc8723d2ant_init_hw_config(IN struct btc_coexist *btcoexist,
IN boolean wifi_only)
{
@ -3840,7 +3701,6 @@ void halbtc8723d2ant_init_hw_config(IN struct btc_coexist *btcoexist,
u16 u16tmp1 = 0;
u8 i = 0;
BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
"[BTCoex], 2Ant Init HW Config!!\n");
BTC_TRACE(trace_buf);
@ -3865,7 +3725,6 @@ void halbtc8723d2ant_init_hw_config(IN struct btc_coexist *btcoexist,
BTC_TRACE(trace_buf);
#endif
coex_sta->bt_coex_supported_feature = 0;
coex_sta->bt_coex_supported_version = 0;
coex_sta->bt_ble_scan_type = 0;
@ -3880,13 +3739,6 @@ void halbtc8723d2ant_init_hw_config(IN struct btc_coexist *btcoexist,
for (i = 0; i <= 9; i++)
coex_sta->bt_afh_map[i] = 0;
#if 0
btcoexist->btc_get(btcoexist, BTC_GET_U4_VENDOR, &vendor);
if (vendor == BTC_VENDOR_LENOVO)
coex_dm->switch_thres_offset = 0;
else
coex_dm->switch_thres_offset = 20;
#endif
/* 0xf0[15:12] --> Chip Cut information */
coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist,
0xf1) & 0xf0) >> 4;
@ -3963,7 +3815,6 @@ void halbtc8723d2ant_init_hw_config(IN struct btc_coexist *btcoexist,
btcoexist->stop_coex_dm = false;
}
}
u32 halbtc8723d2ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val)
@ -3989,7 +3840,6 @@ u32 halbtc8723d2ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val)
}
}
val_integerd_b = shiftcount + 1;
tmp2 = 1;
@ -4008,7 +3858,6 @@ u32 halbtc8723d2ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val)
return result;
}
void halbtc8723d2ant_psd_show_antenna_detect_result(IN struct btc_coexist
@ -4187,7 +4036,6 @@ void halbtc8723d2ant_psd_show_antenna_detect_result(IN struct btc_coexist
"PSD Scan Peak Freq", psd_scan->ant_det_peak_freq);
CL_PRINTF(cli_buf);
CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "TFBGA Package",
(board_info->tfbga_package) ? "Yes" : "No");
CL_PRINTF(cli_buf);
@ -4324,7 +4172,6 @@ void halbtc8723d2ant_psd_showdata(IN struct btc_coexist *btcoexist)
} while ((i <= 8) && (m <= psd_scan->psd_stop_point));
do {
psd_rep1 = psd_scan->psd_report_max_hold[n] /
100;
@ -4387,12 +4234,8 @@ void halbtc8723d2ant_psd_showdata(IN struct btc_coexist *btcoexist)
}
}
}
#ifdef PLATFORM_WINDOWS
#pragma optimize("", off)
#endif
void halbtc8723d2ant_psd_maxholddata(IN struct btc_coexist *btcoexist,
IN u32 gen_count)
{
@ -4425,10 +4268,6 @@ void halbtc8723d2ant_psd_maxholddata(IN struct btc_coexist *btcoexist,
}
#ifdef PLATFORM_WINDOWS
#pragma optimize("", off)
#endif
u32 halbtc8723d2ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point)
{
/* reg 0x808[9:0]: FFT data x */
@ -4460,9 +4299,6 @@ u32 halbtc8723d2ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point)
return psd_report;
}
#ifdef PLATFORM_WINDOWS
#pragma optimize("", off)
#endif
boolean halbtc8723d2ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points,
IN u32 avgnum, IN u32 loopcnt)
@ -4495,7 +4331,6 @@ boolean halbtc8723d2ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
psd_scan->real_offset = offset;
psd_scan->real_span = span;
points1 = psd_scan->psd_point;
delta_freq_per_point = psd_scan->psd_band_width /
psd_scan->psd_point;
@ -4595,7 +4430,6 @@ boolean halbtc8723d2ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1d,
0xfffff, 0x2e);
/* Set RF mode = Rx, RF Gain = 0x320a0 */
btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x0,
0xfffff, 0x320a0);
@ -4792,9 +4626,6 @@ boolean halbtc8723d2ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
}
#ifdef PLATFORM_WINDOWS
#pragma optimize("", off)
#endif
boolean halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist
*btcoexist)
{
@ -4853,15 +4684,6 @@ boolean halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist
break;
}
}
#if 0
wlpsd_sweep_count = bt_tx_time * 238 /
100; /* bt_tx_time/0.42 */
wlpsd_sweep_count = wlpsd_sweep_count / 5;
if (wlpsd_sweep_count % 5 != 0)
wlpsd_sweep_count = (wlpsd_sweep_count /
5 + 1) * 5;
#endif
BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
"xxxxxxxxxxxxxxxx AntennaDetect(), BT_LETxTime=%d, BT_LECh = %d\n",
bt_tx_time, bt_le_channel);
@ -5001,21 +4823,8 @@ boolean halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist
state = 99;
break;
}
#if 1
psd_scan->ant_det_psd_scan_peak_val =
psd_scan->psd_max_value;
#endif
#if 0
psd_scan->ant_det_psd_scan_peak_val =
((psd_scan->psd_max_value - psd_scan->psd_avg_value) <
800) ?
psd_scan->psd_max_value : ((
psd_scan->psd_max_value -
psd_scan->psd_max_value2 <= 300) ?
psd_scan->psd_avg_value :
psd_scan->psd_max_value2);
#endif
psd_scan->ant_det_psd_scan_peak_freq =
psd_scan->psd_max_value_point;
state = 4;
@ -5175,9 +4984,6 @@ boolean halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist
}
#ifdef PLATFORM_WINDOWS
#pragma optimize("", off)
#endif
boolean halbtc8723d2ant_psd_antenna_detection_check(IN struct btc_coexist
*btcoexist)
{
@ -5217,7 +5023,6 @@ boolean halbtc8723d2ant_psd_antenna_detection_check(IN struct btc_coexist
delay_ms(psd_scan->ant_det_bt_tx_time);
}
if (!ant_det_finish)
ant_det_fail_count++;
@ -5234,7 +5039,6 @@ boolean halbtc8723d2ant_psd_antenna_detection_check(IN struct btc_coexist
}
/* ************************************************************
* work around function start with wa_halbtc8723d2ant_
* ************************************************************
@ -5258,7 +5062,6 @@ void ex_halbtc8723d2ant_power_on_setting(IN struct btc_coexist *btcoexist)
board_info->btdm_ant_num_by_ant_det);
BTC_TRACE(trace_buf);
btcoexist->stop_coex_dm = true;
psd_scan->ant_det_is_ant_det_available = false;
@ -5266,7 +5069,6 @@ void ex_halbtc8723d2ant_power_on_setting(IN struct btc_coexist *btcoexist)
u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
/* Local setting bit define */
/* BIT0: "0" for no antenna inverse; "1" for antenna inverse */
/* BIT1: "0" for internal switch; "1" for external switch */
@ -5362,7 +5164,6 @@ void ex_halbtc8723d2ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
}
}
void ex_halbtc8723d2ant_init_hw_config(IN struct btc_coexist *btcoexist,
IN boolean wifi_only)
{
@ -5446,7 +5247,6 @@ void ex_halbtc8723d2ant_display_coex_info(IN struct btc_coexist *btcoexist)
CL_PRINTF(cli_buf);
}
bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;
btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
phyver = btcoexist->btc_get_bt_phydm_version(btcoexist);
@ -5514,7 +5314,6 @@ void ex_halbtc8723d2ant_display_coex_info(IN struct btc_coexist *btcoexist)
pop_report_in_10s = 0;
}
if (coex_sta->num_of_profile != 0)
CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
"\r\n %-35s = %s%s%s%s%s",
@ -5533,7 +5332,6 @@ void ex_halbtc8723d2ant_display_coex_info(IN struct btc_coexist *btcoexist)
CL_PRINTF(cli_buf);
if (bt_link_info->a2dp_exist) {
CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s",
"A2DP Rate/Bitpool/Auto_Slot",
@ -5645,7 +5443,6 @@ void ex_halbtc8723d2ant_display_coex_info(IN struct btc_coexist *btcoexist)
CL_PRINTF(cli_buf);
ps_tdma_case = coex_dm->cur_ps_tdma;
CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
@ -5797,7 +5594,6 @@ void ex_halbtc8723d2ant_display_coex_info(IN struct btc_coexist *btcoexist)
(int)((u8tmp[3] & BIT(7)) >> 7));
CL_PRINTF(cli_buf);
u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6);
u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x45e);
@ -5866,7 +5662,6 @@ void ex_halbtc8723d2ant_display_coex_info(IN struct btc_coexist *btcoexist)
btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
}
void ex_halbtc8723d2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
{
if (btcoexist->manual_control || btcoexist->stop_coex_dm)
@ -5932,7 +5727,6 @@ void ex_halbtc8723d2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
BT_8723D_2ANT_SCOREBOARD_ACTIVE, false);
}
} else if (BTC_LPS_DISABLE == type) {
BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
"[BTCoex], LPS DISABLE notify\n");
@ -5951,7 +5745,6 @@ void ex_halbtc8723d2ant_scan_notify(IN struct btc_coexist *btcoexist,
u8 u8tmpa, u8tmpb;
boolean wifi_connected = false;
if (btcoexist->manual_control ||
btcoexist->stop_coex_dm)
return;
@ -6104,7 +5897,6 @@ void ex_halbtc8723d2ant_media_status_notify(IN struct btc_coexist *btcoexist,
BT_8723D_2ANT_SCOREBOARD_ACTIVE, false);
}
halbtc8723d2ant_update_wifi_channel_info(btcoexist, type);
}
@ -6309,7 +6101,6 @@ void ex_halbtc8723d2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
BTC_MEDIA_DISCONNECT);
}
/* If Ignore_WLanAct && not SetUp_Link or Role_Switch */
if ((coex_sta->bt_info_ext & BIT(3)) &&
(!(coex_sta->bt_info_ext & BIT(2))) &&
@ -6428,7 +6219,6 @@ void ex_halbtc8723d2ant_pnp_notify(IN struct btc_coexist *btcoexist,
coex_sta->under_ips = false;
coex_sta->under_lps = false;
halbtc8723d2ant_post_state_to_bt(btcoexist,
BT_8723D_2ANT_SCOREBOARD_ACTIVE, false);
halbtc8723d2ant_post_state_to_bt(btcoexist,
@ -6446,7 +6236,6 @@ void ex_halbtc8723d2ant_pnp_notify(IN struct btc_coexist *btcoexist,
BT_8723D_2ANT_PHASE_WLAN_OFF);
}
} else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
"[BTCoex], Pnp notify to WAKE UP\n");
@ -6575,7 +6364,6 @@ void ex_halbtc8723d2ant_periodical(IN struct btc_coexist *btcoexist)
#endif
}
if (halbtc8723d2ant_is_wifibt_status_changed(btcoexist))
halbtc8723d2ant_run_coexist_mechanism(btcoexist);
}
@ -6604,9 +6392,6 @@ void ex_halbtc8723d2ant_set_antenna_notify(IN struct btc_coexist *btcoexist,
}
}
#ifdef PLATFORM_WINDOWS
#pragma optimize("", off)
#endif
void ex_halbtc8723d2ant_antenna_detection(IN struct btc_coexist *btcoexist,
IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
{
@ -6747,10 +6532,8 @@ void ex_halbtc8723d2ant_antenna_detection(IN struct btc_coexist *btcoexist,
}
#endif
}
void ex_halbtc8723d2ant_display_ant_detection(IN struct btc_coexist *btcoexist)
{
@ -6767,7 +6550,6 @@ void ex_halbtc8723d2ant_display_ant_detection(IN struct btc_coexist *btcoexist)
}
#endif
#endif /* #if (RTL8723D_SUPPORT == 1) */

4
hal/btc/mp_precomp.h
View file

@ -25,11 +25,7 @@
#define BT_TMP_BUF_SIZE 100
#ifdef PLATFORM_LINUX
#define rsprintf snprintf
#elif defined(PLATFORM_WINDOWS)
#define rsprintf sprintf_s
#endif
#define DCMD_Printf DBG_BT_INFO

60
hal/hal_hci/hal_usb.c
View file

@ -28,27 +28,17 @@ int usb_init_recv_priv(_adapter *padapter, u16 ini_in_buf_sz)
int i, res = _SUCCESS;
struct recv_buf *precvbuf;
#ifdef PLATFORM_LINUX
tasklet_init(&precvpriv->recv_tasklet,
(void(*)(unsigned long))usb_recv_tasklet,
(unsigned long)padapter);
#endif /* PLATFORM_LINUX */
#ifdef PLATFORM_FREEBSD
#ifdef CONFIG_RX_INDICATE_QUEUE
TASK_INIT(&precvpriv->rx_indicate_tasklet, 0, rtw_rx_indicate_tasklet, padapter);
#endif /* CONFIG_RX_INDICATE_QUEUE */
#endif /* PLATFORM_FREEBSD */
#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
#ifdef PLATFORM_LINUX
precvpriv->int_in_urb = usb_alloc_urb(0, GFP_KERNEL);
if (precvpriv->int_in_urb == NULL) {
res = _FAIL;
RTW_INFO("alloc_urb for interrupt in endpoint fail !!!!\n");
goto exit;
}
#endif /* PLATFORM_LINUX */
precvpriv->int_in_buf = rtw_zmalloc(ini_in_buf_sz);
if (precvpriv->int_in_buf == NULL) {
res = _FAIL;
@ -98,8 +88,6 @@ int usb_init_recv_priv(_adapter *padapter, u16 ini_in_buf_sz)
precvpriv->free_recv_buf_queue_cnt = NR_RECVBUFF;
#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)
skb_queue_head_init(&precvpriv->rx_skb_queue);
#ifdef CONFIG_RX_INDICATE_QUEUE
@ -127,11 +115,7 @@ int usb_init_recv_priv(_adapter *padapter, u16 ini_in_buf_sz)
#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */
if (pskb) {
#ifdef PLATFORM_FREEBSD
pskb->dev = padapter->pifp;
#else
pskb->dev = padapter->pnetdev;
#endif /* PLATFORM_FREEBSD */
#ifndef CONFIG_PREALLOC_RX_SKB_BUFFER
tmpaddr = (SIZE_PTR)pskb->data;
@ -144,8 +128,6 @@ int usb_init_recv_priv(_adapter *padapter, u16 ini_in_buf_sz)
}
#endif /* CONFIG_PREALLOC_RECV_SKB */
#endif /* defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD) */
exit:
return res;
@ -168,16 +150,12 @@ void usb_free_recv_priv(_adapter *padapter, u16 ini_in_buf_sz)
rtw_mfree(precvpriv->pallocated_recv_buf, NR_RECVBUFF * sizeof(struct recv_buf) + 4);
#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
#ifdef PLATFORM_LINUX
if (precvpriv->int_in_urb)
usb_free_urb(precvpriv->int_in_urb);
#endif
if (precvpriv->int_in_buf)
rtw_mfree(precvpriv->int_in_buf, ini_in_buf_sz);
#endif /* CONFIG_USB_INTERRUPT_IN_PIPE */
#ifdef PLATFORM_LINUX
if (skb_queue_len(&precvpriv->rx_skb_queue))
RTW_WARN("rx_skb_queue not empty\n");
@ -200,30 +178,6 @@ void usb_free_recv_priv(_adapter *padapter, u16 ini_in_buf_sz)
rtw_skb_queue_purge(&precvpriv->free_recv_skb_queue);
#endif /* defined(CONFIG_PREALLOC_RX_SKB_BUFFER) && defined(CONFIG_PREALLOC_RECV_SKB) */
#endif /* !defined(CONFIG_USE_USB_BUFFER_ALLOC_RX) */
#endif /* PLATFORM_LINUX */
#ifdef PLATFORM_FREEBSD
struct sk_buff *pskb;
while (NULL != (pskb = skb_dequeue(&precvpriv->rx_skb_queue)))
rtw_skb_free(pskb);
#if !defined(CONFIG_USE_USB_BUFFER_ALLOC_RX)
rtw_skb_queue_purge(&precvpriv->free_recv_skb_queue);
#endif
#ifdef CONFIG_RX_INDICATE_QUEUE
struct mbuf *m;
for (;;) {
IF_DEQUEUE(&precvpriv->rx_indicate_queue, m);
if (m == NULL)
break;
m_freem(m);
}
mtx_destroy(&precvpriv->rx_indicate_queue.ifq_mtx);
#endif /* CONFIG_RX_INDICATE_QUEUE */
#endif /* PLATFORM_FREEBSD */
}
#ifdef CONFIG_FW_C2H_REG
@ -331,7 +285,6 @@ u8 usb_read8(struct intf_hdl *pintfhdl, u32 addr)
u16 len;
u8 data = 0;
request = 0x05;
requesttype = 0x01;/* read_in */
index = 0;/* n/a */
@ -341,7 +294,6 @@ u8 usb_read8(struct intf_hdl *pintfhdl, u32 addr)
usbctrl_vendorreq(pintfhdl, request, wvalue, index,
&data, len, requesttype);
return data;
}
@ -354,7 +306,6 @@ u16 usb_read16(struct intf_hdl *pintfhdl, u32 addr)
u16 len;
u16 data = 0;
request = 0x05;
requesttype = 0x01;/* read_in */
index = 0;/* n/a */
@ -364,7 +315,6 @@ u16 usb_read16(struct intf_hdl *pintfhdl, u32 addr)
usbctrl_vendorreq(pintfhdl, request, wvalue, index,
&data, len, requesttype);
return data;
}
@ -378,7 +328,6 @@ u32 usb_read32(struct intf_hdl *pintfhdl, u32 addr)
u16 len;
u32 data = 0;
request = 0x05;
requesttype = 0x01;/* read_in */
index = 0;/* n/a */
@ -388,7 +337,6 @@ u32 usb_read32(struct intf_hdl *pintfhdl, u32 addr)
usbctrl_vendorreq(pintfhdl, request, wvalue, index,
&data, len, requesttype);
return data;
}
@ -402,7 +350,6 @@ int usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val)
u8 data;
int ret;
request = 0x05;
requesttype = 0x00;/* write_out */
index = 0;/* n/a */
@ -414,7 +361,6 @@ int usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val)
ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index,
&data, len, requesttype);
return ret;
}
@ -428,7 +374,6 @@ int usb_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val)
u16 data;
int ret;
request = 0x05;
requesttype = 0x00;/* write_out */
index = 0;/* n/a */
@ -440,7 +385,6 @@ int usb_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val)
ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index,
&data, len, requesttype);
return ret;
}
@ -455,7 +399,6 @@ int usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val)
u32 data;
int ret;
request = 0x05;
requesttype = 0x00;/* write_out */
index = 0;/* n/a */
@ -466,7 +409,6 @@ int usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val)
ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index,
&data, len, requesttype);
return ret;
}
@ -481,7 +423,6 @@ int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata)
u8 buf[VENDOR_CMD_MAX_DATA_LEN] = {0};
int ret;
request = 0x05;
requesttype = 0x00;/* write_out */
index = 0;/* n/a */
@ -492,7 +433,6 @@ int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata)
ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index,
buf, len, requesttype);
return ret;
}

45
hal/phydm/halhwimg.h
View file

@ -5,8 +5,6 @@
/*
* 2011/03/15 MH Add for different IC HW image file selection. code size consideration.
* */
#if RT_PLATFORM == PLATFORM_LINUX
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
/* For 92C */
#define RTL8192CE_HWIMG_SUPPORT 1
@ -77,47 +75,4 @@
#define RTL8188ES_HWIMG_SUPPORT 0
#endif
#else /* PLATFORM_WINDOWS & MacOSX */
/* For 92C */
#define RTL8192CE_HWIMG_SUPPORT 1
#define RTL8192CE_TEST_HWIMG_SUPPORT 1
#define RTL8192CU_HWIMG_SUPPORT 1
#define RTL8192CU_TEST_HWIMG_SUPPORT 1
/* For 92D */
#define RTL8192DE_HWIMG_SUPPORT 1
#define RTL8192DE_TEST_HWIMG_SUPPORT 1
#define RTL8192DU_HWIMG_SUPPORT 1
#define RTL8192DU_TEST_HWIMG_SUPPORT 1
#if defined(UNDER_CE)
/* For 8723 */
#define RTL8723E_HWIMG_SUPPORT 0
#define RTL8723U_HWIMG_SUPPORT 0
#define RTL8723S_HWIMG_SUPPORT 1
/* For 88E */
#define RTL8188EE_HWIMG_SUPPORT 0
#define RTL8188EU_HWIMG_SUPPORT 0
#define RTL8188ES_HWIMG_SUPPORT 0
#else
/* For 8723 */
#define RTL8723E_HWIMG_SUPPORT 1
/* #define RTL_8723E_TEST_HWIMG_SUPPORT 1 */
#define RTL8723U_HWIMG_SUPPORT 1
/* #define RTL_8723U_TEST_HWIMG_SUPPORT 1 */
#define RTL8723S_HWIMG_SUPPORT 1
/* #define RTL_8723S_TEST_HWIMG_SUPPORT 1 */
/* For 88E */
#define RTL8188EE_HWIMG_SUPPORT 1
#define RTL8188EU_HWIMG_SUPPORT 1
#define RTL8188ES_HWIMG_SUPPORT 1
#endif
#endif
#endif /* __INC_HW_IMG_H */

49
hal/phydm/phydm.h
View file

@ -18,7 +18,6 @@
*
******************************************************************************/
#ifndef __HALDMOUTSRC_H__
#define __HALDMOUTSRC_H__
@ -47,7 +46,6 @@
#include "phydm_adc_sampling.h"
#include "phydm_dynamic_rx_path.h"
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
#include "phydm_beamforming.h"
#endif
@ -107,7 +105,6 @@
#define FREQ_POSITIVE 1
#define FREQ_NEGATIVE 2
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#define PHYDM_WATCH_DOG_PERIOD 1
#else
@ -128,7 +125,6 @@ struct rtl8192cd_priv {
};
#endif
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct _ADAPTER {
u8 temp;
@ -157,7 +153,6 @@ struct _dynamic_primary_cca {
u8 MF_state;
};
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
#ifdef ADSL_AP_BUILD_WORKAROUND
#define MAX_TOLERANCE 5
@ -173,7 +168,6 @@ struct _dynamic_primary_cca {
#define IQK_THRESHOLD 8
#define DPK_THRESHOLD 4
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
__PACK struct _odm_phy_status_info_ {
u8 rx_pwdb_all;
@ -253,7 +247,6 @@ struct _odm_per_pkt_info_ {
u8 ppdu_cnt;
};
struct _odm_phy_dbg_info_ {
/*ODM Write,debug info*/
s8 rx_snr_db[4];
@ -276,7 +269,6 @@ struct _odm_phy_dbg_info_ {
};
/*2011/20/20 MH For MP driver RT_WLAN_STA = struct sta_info*/
/*Please declare below ODM relative info in your STA info structure.*/
@ -415,7 +407,6 @@ enum odm_cmninfo_e {
};
enum phydm_info_query_e {
PHYDM_INFO_FA_OFDM,
PHYDM_INFO_FA_CCK,
@ -444,7 +435,6 @@ enum phydm_api_e {
};
/*2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY*/
enum odm_ability_e {
@ -476,7 +466,6 @@ enum odm_ability_e {
};
/*ODM_CMNINFO_ONE_PATH_CCA*/
enum odm_cca_path_e {
ODM_CCA_2R = 0,
@ -490,7 +479,6 @@ enum cca_pathdiv_en_e {
};
enum phy_reg_pg_type {
PHY_REG_PG_RELATIVE_VALUE = 0,
PHY_REG_PG_EXACT_VALUE = 1
@ -498,15 +486,7 @@ enum phy_reg_pg_type {
/*2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration.*/
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (RT_PLATFORM != PLATFORM_LINUX)
typedef
#endif
struct PHY_DM_STRUCT
#else/*for AP,ADSL,CE Team*/
struct PHY_DM_STRUCT
#endif
{
/*Add for different team use temporarily*/
struct _ADAPTER *adapter; /*For CE/NIC team*/
@ -514,14 +494,7 @@ enum phy_reg_pg_type {
/*WHen you use adapter or priv pointer, you must make sure the pointer is ready.*/
bool odm_ready;
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
struct rtl8192cd_priv fake_priv;
#endif
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
/* ADSL_AP_BUILD_WORKAROUND */
struct _ADAPTER fake_adapter;
#endif
enum phy_reg_pg_type phy_reg_pg_value_type;
u8 phy_reg_pg_version;
@ -542,7 +515,6 @@ enum phy_reg_pg_type {
u8 control_channel;
/*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
/* 1 COMMON INFORMATION */
/*Init value*/
@ -940,19 +912,7 @@ enum phy_reg_pg_type {
u32 radar_detect_reg_924;
/*====== phydm_radar_detect_with_dbg_parm end ======*/
#endif
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (RT_PLATFORM != PLATFORM_LINUX)
}; /*DM_Dynamic_Mechanism_Structure*/
#else
};
#endif
#else /*for AP,ADSL,CE Team*/
};
#endif
enum phydm_structure_type {
PHYDM_FALSEALMCNT,
@ -962,8 +922,6 @@ enum phydm_structure_type {
};
enum odm_rf_content {
odm_radioa_txt = 0x1000,
odm_radiob_txt = 0x1001,
@ -1081,7 +1039,6 @@ odm_dm_watchdog_lps(
);
#endif
s32
odm_pwdb_conversion(
s32 X,
@ -1105,7 +1062,6 @@ phydm_txcurrentcalibration(
struct PHY_DM_STRUCT *p_dm_odm
);
void
phydm_seq_sorting(
void *p_dm_void,
@ -1221,7 +1177,6 @@ odm_release_all_timers(
struct PHY_DM_STRUCT *p_dm_odm
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void odm_init_all_work_items(struct PHY_DM_STRUCT *p_dm_odm);
void odm_free_all_work_items(struct PHY_DM_STRUCT *p_dm_odm);
@ -1259,7 +1214,6 @@ odm_asoc_entry_init(
struct PHY_DM_STRUCT *p_dm_odm
);
void *
phydm_get_structure(
struct PHY_DM_STRUCT *p_dm_odm,
@ -1277,7 +1231,6 @@ phydm_get_structure(
#define IS_HARDWARE_TYPE_8192D(_adapter) false
#define RF_T_METER_92D 0x42
#define GET_RX_STATUS_DESC_RX_MCS(__prx_status_desc) LE_BITS_TO_1BYTE(__prx_status_desc+12, 0, 6)
#define REG_CONFIG_RAM64X16 0xb2c
@ -1295,10 +1248,8 @@ phydm_get_structure(
void odm_dtc(struct PHY_DM_STRUCT *p_dm_odm);
#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
void phydm_noisy_detection(struct PHY_DM_STRUCT *p_dm_odm);
#endif
void

134
hal/phydm/phydm_hwconfig.c
View file

@ -28,7 +28,6 @@
#define READ_AND_CONFIG_MP(ic, txt) (odm_read_and_config_mp_##ic##txt(p_dm_odm))
#define READ_AND_CONFIG_TC(ic, txt) (odm_read_and_config_tc_##ic##txt(p_dm_odm))
#if (PHYDM_TESTCHIP_SUPPORT == 1)
#define READ_AND_CONFIG(ic, txt) do {\
if (p_dm_odm->is_mp_chip)\
@ -40,7 +39,6 @@
#define READ_AND_CONFIG READ_AND_CONFIG_MP
#endif
#define READ_FIRMWARE_MP(ic, txt) (odm_read_firmware_mp_##ic##txt(p_dm_odm, p_firmware, p_size))
#define READ_FIRMWARE_TC(ic, txt) (odm_read_firmware_tc_##ic##txt(p_dm_odm, p_firmware, p_size))
@ -77,7 +75,6 @@ odm_query_rx_pwr_percentage(
return 100 + ant_power;
}
/*
* 2012/01/12 MH MOve some signal strength smooth method to MP HAL layer.
* IF other SW team do not support the feature, remove this section.??
@ -158,7 +155,6 @@ odm_signal_scale_mapping_92c_series_patch_rt_cid_819x_netcore(
return ret_sig;
}
s32
odm_signal_scale_mapping_92c_series(
struct PHY_DM_STRUCT *p_dm_odm,
@ -242,8 +238,6 @@ odm_signal_scale_mapping(
}
static u8 odm_sq_process_patch_rt_cid_819x_lenovo(
struct PHY_DM_STRUCT *p_dm_odm,
u8 is_cck_rate,
@ -382,8 +376,6 @@ static u8 odm_sq_process_patch_rt_cid_819x_acer(
SQ = 20;
#endif
} else {
/* OFDM rate */
@ -659,7 +651,6 @@ odm_rx_phy_status92c_series_parsing(
p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = -1;
p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1;
if (is_cck_rate) {
p_dm_odm->phy_dbg_info.num_qry_phy_status_cck++;
cck_agc_rpt = p_phy_sta_rpt->cck_agc_rpt_ofdm_cfosho_a ;
@ -832,7 +823,6 @@ odm_rx_phy_status92c_series_parsing(
}
}
/* */
/* (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) */
/* */
@ -840,7 +830,6 @@ odm_rx_phy_status92c_series_parsing(
PWDB_ALL_BT = PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all);
p_phy_info->rx_pwdb_all = PWDB_ALL;
/* ODM_RT_TRACE(p_dm_odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",p_phy_info->rx_pwdb_all)); */
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
@ -1200,7 +1189,6 @@ odm_rx_phy_status_jaguar_series_parsing(
p_phy_info->rx_mimo_signal_strength[i] = (u8) RSSI;
/*Get Rx snr value in DB*/
if (i < ODM_RF_PATH_C)
p_phy_info->rx_snr[i] = p_dm_odm->phy_dbg_info.rx_snr_db[i] = p_phy_sta_rpt->rxsnr[i] / 2;
@ -1356,7 +1344,6 @@ odm_rx_phy_status_jaguar_series_parsing(
p_dm_odm->dm_fat_table.antsel_rx_keep_3 = p_phy_sta_rpt->antidx_antd;
/*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antidx_anta = ((%d)), MatchBSSID = ((%d))\n", p_pktinfo->station_id, p_phy_sta_rpt->antidx_anta, p_pktinfo->is_packet_match_bssid));*/
/* dbg_print("p_phy_sta_rpt->antidx_anta = %d, p_phy_sta_rpt->antidx_antb = %d\n",*/
/* p_phy_sta_rpt->antidx_anta, p_phy_sta_rpt->antidx_antb);*/
/* dbg_print("----------------------------\n");*/
@ -1403,7 +1390,6 @@ phydm_reset_rssi_for_dm(
}
ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("Reset RSSI for macid = (( %d ))\n", station_id));
p_entry->rssi_stat.undecorated_smoothed_cck = -1;
p_entry->rssi_stat.undecorated_smoothed_ofdm = -1;
p_entry->rssi_stat.undecorated_smoothed_pwdb = -1;
@ -1690,7 +1676,6 @@ odm_process_rssi_for_dm(
}
}
if ((p_entry->rssi_stat.ofdm_pkt >= 1 || p_entry->rssi_stat.cck_pkt >= 5) && (p_entry->rssi_stat.is_send_rssi == RA_RSSI_STATE_INIT)) {
send_rssi_2_fw = 1;
@ -1701,8 +1686,6 @@ odm_process_rssi_for_dm(
p_entry->rssi_stat.undecorated_smoothed_ofdm = undecorated_smoothed_ofdm;
p_entry->rssi_stat.undecorated_smoothed_pwdb = undecorated_smoothed_pwdb;
if (send_rssi_2_fw) { /* Trigger init rate by RSSI */
if (p_entry->rssi_stat.ofdm_pkt != 0)
@ -1716,7 +1699,6 @@ odm_process_rssi_for_dm(
#endif
}
/*in WIN Driver: sta_ID==0->p_entry==NULL -> default port HAL_Data*/
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
@ -1735,7 +1717,6 @@ odm_process_rssi_for_dm(
}
}
#if (ODM_IC_11N_SERIES_SUPPORT == 1)
/*
* Endianness before calling this API
@ -1753,7 +1734,6 @@ odm_phy_status_query_92c_series(
}
#endif
/*
* Endianness before calling this API
* */
@ -1890,7 +1870,6 @@ phydm_normal_driver_rx_sniffer(
));
}
#endif
}
#endif
@ -1936,7 +1915,6 @@ odm_mac_status_query(
}
/*
* If you want to add a new IC, Please follow below template and generate a new one.
*
@ -2153,7 +2131,6 @@ odm_config_rf_with_tx_pwr_track_header_file(
("p_dm_odm->support_platform: 0x%X, p_dm_odm->support_interface: 0x%X, p_dm_odm->board_type: 0x%X\n",
p_dm_odm->support_platform, p_dm_odm->support_interface, p_dm_odm->board_type));
/* 1 AP doesn't use PHYDM power tracking table in these ICs */
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
#if RTL8821A_SUPPORT
@ -2324,7 +2301,6 @@ odm_config_bb_with_header_file(
#endif
/* 1 AP doesn't use PHYDM initialization in these ICs */
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
#if (RTL8812A_SUPPORT == 1)
if (p_dm_odm->support_ic_type == ODM_RTL8812) {
if (config_type == CONFIG_BB_PHY_REG)
@ -2334,20 +2310,6 @@ odm_config_bb_with_header_file(
else if (config_type == CONFIG_BB_PHY_REG_PG) {
if (p_dm_odm->rfe_type == 3 && p_dm_odm->is_mp_chip)
READ_AND_CONFIG_MP(8812a, _phy_reg_pg_asus);
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
else if (p_mgnt_info->CustomerID == RT_CID_WNC_NEC && p_dm_odm->is_mp_chip)
READ_AND_CONFIG_MP(8812a, _phy_reg_pg_nec);
#if RT_PLATFORM == PLATFORM_MACOSX
/*{1827}{1024} for BUFFALO power by rate table. Isaiah 2013-11-29*/
else if (p_mgnt_info->CustomerID == RT_CID_DNI_BUFFALO)
READ_AND_CONFIG_MP(8812a, _phy_reg_pg_dni);
/* TP-Link T4UH, Isaiah 2015-03-16*/
else if (p_mgnt_info->CustomerID == RT_CID_TPLINK_HPWR) {
dbg_print("RT_CID_TPLINK_HPWR:: _PHY_REG_PG_TPLINK\n");
READ_AND_CONFIG_MP(8812a, _phy_reg_pg_tplink);
}
#endif
#endif
else
READ_AND_CONFIG_MP(8812a, _phy_reg_pg);
} else if (config_type == CONFIG_BB_PHY_REG_MP)
@ -2361,7 +2323,6 @@ odm_config_bb_with_header_file(
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8812AGCTABArray\n"));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8812PHY_REGArray\n"));
}
#endif
#if (RTL8821A_SUPPORT == 1)
if (p_dm_odm->support_ic_type == ODM_RTL8821) {
if (config_type == CONFIG_BB_PHY_REG)
@ -2369,25 +2330,6 @@ odm_config_bb_with_header_file(
else if (config_type == CONFIG_BB_AGC_TAB)
READ_AND_CONFIG_MP(8821a, _agc_tab);
else if (config_type == CONFIG_BB_PHY_REG_PG) {
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
if ((p_hal_data->EEPROMSVID == 0x1043 && p_hal_data->EEPROMSMID == 0x207F))
READ_AND_CONFIG_MP(8821a, _phy_reg_pg_e202_sa);
else
#endif
#if (RT_PLATFORM == PLATFORM_MACOSX)
/*{1827}{1022} for BUFFALO power by rate table. Isaiah 2013-10-18*/
if (p_mgnt_info->CustomerID == RT_CID_DNI_BUFFALO) {
/*{1024} for BUFFALO power by rate table. (JP/US)*/
if (p_mgnt_info->channel_plan == RT_CHANNEL_DOMAIN_US_2G_CANADA_5G)
READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_us);
else
READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_jp);
} else
#endif
#endif
READ_AND_CONFIG_MP(8821a, _phy_reg_pg);
}
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8821AGCTABArray\n"));
@ -2416,7 +2358,6 @@ odm_config_bb_with_header_file(
#endif
#endif/* (DM_ODM_SUPPORT_TYPE != ODM_AP) */
/* 1 All platforms support */
#if (RTL8188E_SUPPORT == 1)
if (p_dm_odm->support_ic_type == ODM_RTL8188E) {
@ -3009,7 +2950,6 @@ phydm_set_per_path_phy_info(
evm_percentage = (evm_dbm << 1) + (evm_dbm);
}
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
p_phy_info->rx_pwr[rx_path] = rx_pwr;
p_phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm;
@ -3023,16 +2963,6 @@ phydm_set_per_path_phy_info(
p_phy_info->rx_mimo_signal_strength[rx_path] = odm_query_rx_pwr_percentage(rx_pwr);
p_phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage;
p_phy_info->rx_snr[rx_path] = rx_snr >> 1;
#if 0
/* if (p_pktinfo->is_packet_match_bssid) */
{
dbg_print("path (%d)--------\n", rx_path);
dbg_print("rx_pwr = %d, Signal strength = %d\n", p_phy_info->rx_pwr[rx_path], p_phy_info->rx_mimo_signal_strength[rx_path]);
dbg_print("evm_dbm = %d, Signal quality = %d\n", p_phy_info->rx_mimo_evm_dbm[rx_path], p_phy_info->rx_mimo_signal_quality[rx_path]);
dbg_print("CFO = %d, SNR = %d\n", p_phy_info->cfo_tail[rx_path], p_phy_info->rx_snr[rx_path]);
}
#endif
}
void
@ -3058,16 +2988,6 @@ phydm_set_common_phy_info(
p_phy_info->rx_pwdb_all = odm_query_rx_pwr_percentage(rx_power); /* RSSI in percentage */
p_phy_info->signal_quality = signal_quality; /* signal quality */
p_phy_info->band_width = bandwidth; /* bandwidth */
#if 0
/* if (p_pktinfo->is_packet_match_bssid) */
{
dbg_print("rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\n", p_phy_info->rx_pwdb_all, p_phy_info->rx_power, p_phy_info->recv_signal_power);
dbg_print("signal_quality = %d\n", p_phy_info->signal_quality);
dbg_print("is_beamformed = %d, is_mu_packet = %d, rx_count = %d\n", p_phy_info->is_beamformed, p_phy_info->is_mu_packet, p_phy_info->rx_count + 1);
dbg_print("channel = %d, rxsc = %d, band_width = %d\n", channel, rxsc, bandwidth);
}
#endif
}
void
@ -3084,7 +3004,6 @@ phydm_get_rx_phy_status_type0(
u8 i, SQ = 0;
s8 rx_power = p_phy_sta_rpt->pwdb - 110;
#if (RTL8723D_SUPPORT == 1)
if (p_dm_odm->support_ic_type & ODM_RTL8723D)
rx_power = p_phy_sta_rpt->pwdb - 97;
@ -3152,19 +3071,6 @@ phydm_get_rx_phy_status_type0(
p_dm_odm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->antidx_b;
p_dm_odm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antidx_c;
p_dm_odm->dm_fat_table.antsel_rx_keep_3 = p_phy_sta_rpt->antidx_d;
#if 0
/* if (p_pktinfo->is_packet_match_bssid) */
{
dbg_print("pwdb = 0x%x, MP gain index = 0x%x, TRSW = 0x%x\n", p_phy_sta_rpt->pwdb, p_phy_sta_rpt->gain, p_phy_sta_rpt->trsw);
dbg_print("channel = %d, band = %d, rxsc = %d\n", p_phy_sta_rpt->channel, p_phy_sta_rpt->band, p_phy_sta_rpt->rxsc);
dbg_print("agc_table = 0x%x, agc_rpt 0x%x, bb_power = 0x%x\n", p_phy_sta_rpt->agc_table, p_phy_sta_rpt->agc_rpt, p_phy_sta_rpt->bb_power);
dbg_print("length = %d, SQ = %d\n", p_phy_sta_rpt->length, p_phy_sta_rpt->signal_quality);
dbg_print("antidx a = 0x%x, b = 0x%x, c = 0x%x, d = 0x%x\n", p_phy_sta_rpt->antidx_a, p_phy_sta_rpt->antidx_b, p_phy_sta_rpt->antidx_c, p_phy_sta_rpt->antidx_d);
dbg_print("rsvd_0 = 0x%x, rsvd_1 = 0x%x, rsvd_2 = 0x%x\n", p_phy_sta_rpt->rsvd_0, p_phy_sta_rpt->rsvd_1, p_phy_sta_rpt->rsvd_2);
dbg_print("rsvd_3 = 0x%x, rsvd_4 = 0x%x, rsvd_5 = 0x%x\n", p_phy_sta_rpt->rsvd_3, p_phy_sta_rpt->rsvd_4, p_phy_sta_rpt->rsvd_5);
dbg_print("rsvd_6 = 0x%x, rsvd_7 = 0x%x, rsvd_8 = 0x%x\n", p_phy_sta_rpt->rsvd_6, p_phy_sta_rpt->rsvd_7, p_phy_sta_rpt->rsvd_8);
}
#endif
}
void
@ -3368,24 +3274,6 @@ phydm_get_rx_phy_status_type2(
phydm_set_common_phy_info(rx_pwr_db, p_phy_sta_rpt->channel, (bool)p_phy_sta_rpt->beamformed,
false, bw, 0, rxsc, p_phy_info);
#if 0
/* if (p_pktinfo->is_packet_match_bssid) */
{
dbg_print("channel = %d, band = %d, l_rxsc = %d, ht_rxsc = %d\n", p_phy_sta_rpt->channel, p_phy_sta_rpt->band, p_phy_sta_rpt->l_rxsc, p_phy_sta_rpt->ht_rxsc);
dbg_print("pwdb A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->pwdb[0], p_phy_sta_rpt->pwdb[1], p_phy_sta_rpt->pwdb[2], p_phy_sta_rpt->pwdb[3]);
dbg_print("Agc table A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->agc_table_a, p_phy_sta_rpt->agc_table_b, p_phy_sta_rpt->agc_table_c, p_phy_sta_rpt->agc_table_d);
dbg_print("Gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->gain_a, p_phy_sta_rpt->gain_b, p_phy_sta_rpt->gain_c, p_phy_sta_rpt->gain_d);
dbg_print("TRSW A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->trsw_a, p_phy_sta_rpt->trsw_b, p_phy_sta_rpt->trsw_c, p_phy_sta_rpt->trsw_d);
dbg_print("AAGC step A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->aagc_step_a, p_phy_sta_rpt->aagc_step_b, p_phy_sta_rpt->aagc_step_c, p_phy_sta_rpt->aagc_step_d);
dbg_print("HT AAGC gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->ht_aagc_gain[0], p_phy_sta_rpt->ht_aagc_gain[1], p_phy_sta_rpt->ht_aagc_gain[2], p_phy_sta_rpt->ht_aagc_gain[3]);
dbg_print("DAGC gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->dagc_gain[0], p_phy_sta_rpt->dagc_gain[1], p_phy_sta_rpt->dagc_gain[2], p_phy_sta_rpt->dagc_gain[3]);
dbg_print("ldpc: %d, stbc: %d, bf: %d, gnt_bt: %d, antsw: %d\n", p_phy_sta_rpt->ldpc, p_phy_sta_rpt->stbc, p_phy_sta_rpt->beamformed, p_phy_sta_rpt->gnt_bt, p_phy_sta_rpt->hw_antsw_occu);
dbg_print("counter: %d, syn_count: %d\n", p_phy_sta_rpt->counter, p_phy_sta_rpt->syn_count);
dbg_print("cnt_cca2agc_rdy: %d, cnt_pw2cca: %d, shift_l_map\n", p_phy_sta_rpt->cnt_cca2agc_rdy, p_phy_sta_rpt->cnt_pw2cca, p_phy_sta_rpt->shift_l_map);
dbg_print("rsvd_0 = %d, rsvd_1 = %d, rsvd_2 = %d, rsvd_3 = %d, rsvd_4 = %d, rsvd_5 = %d\n", p_phy_sta_rpt->rsvd_0, p_phy_sta_rpt->rsvd_1, p_phy_sta_rpt->rsvd_2, p_phy_sta_rpt->rsvd_3, p_phy_sta_rpt->rsvd_4);
dbg_print("rsvd_5 = %d, rsvd_6 = %d, rsvd_6 = %d\n", p_phy_sta_rpt->rsvd_5, p_phy_sta_rpt->rsvd_6, p_phy_sta_rpt->rsvd_7);
}
#endif
}
void
@ -3393,15 +3281,6 @@ phydm_get_rx_phy_status_type5(
u8 *p_phy_status
)
{
/*
dbg_print("DW0: 0x%02x%02x%02x%02x\n", *(p_phy_status + 3), *(p_phy_status + 2), *(p_phy_status + 1), *(p_phy_status + 0));
dbg_print("DW1: 0x%02x%02x%02x%02x\n", *(p_phy_status + 7), *(p_phy_status + 6), *(p_phy_status + 5), *(p_phy_status + 4));
dbg_print("DW2: 0x%02x%02x%02x%02x\n", *(p_phy_status + 11), *(p_phy_status + 10), *(p_phy_status + 9), *(p_phy_status + 8));
dbg_print("DW3: 0x%02x%02x%02x%02x\n", *(p_phy_status + 15), *(p_phy_status + 14), *(p_phy_status + 13), *(p_phy_status + 12));
dbg_print("DW4: 0x%02x%02x%02x%02x\n", *(p_phy_status + 19), *(p_phy_status + 18), *(p_phy_status + 17), *(p_phy_status + 16));
dbg_print("DW5: 0x%02x%02x%02x%02x\n", *(p_phy_status + 23), *(p_phy_status + 22), *(p_phy_status + 21), *(p_phy_status + 20));
dbg_print("DW6: 0x%02x%02x%02x%02x\n", *(p_phy_status + 27), *(p_phy_status + 26), *(p_phy_status + 25), *(p_phy_status + 24));
*/
}
void
@ -3513,27 +3392,14 @@ phydm_rx_phy_status_new_type(
/* Phy status parsing */
switch (phy_status_type) {
case 0:
{
phydm_get_rx_phy_status_type0(p_phydm, p_phy_status, p_pktinfo, p_phy_info);
break;
}
case 1:
{
phydm_get_rx_phy_status_type1(p_phydm, p_phy_status, p_pktinfo, p_phy_info);
break;
}
case 2:
{
phydm_get_rx_phy_status_type2(p_phydm, p_phy_status, p_pktinfo, p_phy_info);
break;
}
#if 0
case 5:
{
phydm_get_rx_phy_status_type5(p_phy_status);
return;
}
#endif
default:
return;
}

728
hal/phydm/rtl8188e/halphyrf_8188e_ap.c
View file

@ -124,37 +124,8 @@ void do_iqk_8188e(
odm_reset_iqk_result(p_dm_odm);
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
#if USE_WORKITEM
platform_acquire_mutex(&p_hal_data->mx_chnl_bw_control);
#else
platform_acquire_spin_lock(adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK);
#endif
#elif ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
platform_acquire_mutex(&p_hal_data->mx_chnl_bw_control);
#endif
#endif
p_dm_odm->rf_calibrate_info.thermal_value_iqk = thermal_value;
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
phy_iq_calibrate_8188e(p_dm_odm, false);
#else
phy_iq_calibrate_8188e(adapter, false);
#endif
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
#if USE_WORKITEM
platform_release_mutex(&p_hal_data->mx_chnl_bw_control);
#else
platform_release_spin_lock(adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK);
#endif
#elif ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
platform_release_mutex(&p_hal_data->mx_chnl_bw_control);
#endif
#endif
}
/*-----------------------------------------------------------------------------
@ -359,18 +330,7 @@ phy_path_a_iqk_8188e(
RESTORE_INT(x);
#endif
#if 0
if (!(reg_eac & BIT(27)) && /* if Tx is OK, check whether Rx is OK */
(((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
(((reg_eac & 0x03FF0000) >> 16) != 0x36))
result |= 0x02;
else
RTPRINT(FINIT, INIT_IQK, ("path A Rx IQK fail!!\n"));
#endif
return result;
}
u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
@ -519,15 +479,6 @@ phy_path_a_rx_iqk(
reg_ea4 = odm_get_bb_reg(p_dm_odm, REG_RX_POWER_BEFORE_IQK_A_2, MASKDWORD);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", reg_ea4));
#if 0
if (!(reg_eac & BIT(28)) &&
(((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
(((reg_e9c & 0x03FF0000) >> 16) != 0x42))
result |= 0x01;
else /* if Tx not OK, ignore Rx */
return result;
#endif
if (!(reg_eac & BIT(27)) && /* if Tx is OK, check whether Rx is OK */
(((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
(((reg_eac & 0x03FF0000) >> 16) != 0x36))
@ -750,36 +701,6 @@ _phy_path_b_fill_iqk_matrix(
* 2011/07/26 MH Add an API for testing IQK fail case.
*
* MP Already declare in odm.c */
#if 0 /* !(DM_ODM_SUPPORT_TYPE & ODM_WIN) */ /* 0824 */
bool
odm_check_power_status(
struct _ADAPTER *adapter)
{
#if 0
/* HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); */
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
RT_RF_POWER_STATE rt_state;
PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo);
/* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */
if (p_mgnt_info->init_adpt_in_progress == true) {
ODM_RT_TRACE(p_dm_odm, COMP_INIT, DBG_LOUD, ("odm_check_power_status Return true, due to initadapter"));
return true;
}
/* */
/* 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. */
/* */
phydm_get_hw_reg_interface(p_dm_odm, HW_VAR_RF_STATE, (u8 *)(&rt_state));
if (adapter->is_driver_stopped || adapter->is_driver_is_going_to_pnp_set_power_sleep || rt_state == eRfOff) {
ODM_RT_TRACE(p_dm_odm, COMP_INIT, DBG_LOUD, ("odm_check_power_status Return false, due to %d/%d/%d\n",
adapter->is_driver_stopped, adapter->is_driver_is_going_to_pnp_set_power_sleep, rt_state));
return false;
}
#endif
return true;
}
#endif
void
_phy_save_adda_registers(
@ -1270,22 +1191,10 @@ _phy_iq_calibrate_8188e(
result[t][1] = (odm_get_bb_reg(p_dm_odm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
break;
}
#if 0
else if (i == (retry_count - 1) && path_aok == 0x01) { /* Tx IQK OK */
RTPRINT(FINIT, INIT_IQK, ("path A IQK Only Tx Success!!\n"));
result[t][0] = (odm_get_bb_reg(p_dm_odm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
result[t][1] = (odm_get_bb_reg(p_dm_odm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
}
#endif
}
for (i = 0 ; i < retry_count ; i++) {
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
path_aok = phy_path_a_rx_iqk(p_adapter, is2T);
#else
path_aok = phy_path_a_rx_iqk(p_dm_odm, is2T);
#endif
if (path_aok == 0x03) {
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A Rx IQK Success!!\n"));
/* result[t][0] = (odm_get_bb_reg(p_dm_odm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD)&0x3FF0000)>>16;
@ -1297,32 +1206,17 @@ _phy_iq_calibrate_8188e(
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A Rx IQK Fail!!\n"));
}
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
SAVE_INT_AND_CLI(x);
#endif
if (0x00 == path_aok)
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A IQK failed!!\n"));
if (is2T) {
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
_phy_path_a_stand_by(p_adapter);
/* Turn path B ADDA on */
_phy_path_adda_on(p_adapter, ADDA_REG, false, is2T);
#else
_phy_path_a_stand_by(p_dm_odm);
/* Turn path B ADDA on */
_phy_path_adda_on(p_dm_odm, ADDA_REG, false, is2T);
#endif
for (i = 0 ; i < retry_count ; i++) {
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
path_bok = phy_path_b_iqk_8188e(p_adapter);
#else
path_bok = phy_path_b_iqk_8188e(p_dm_odm);
#endif
if (path_bok == 0x03) {
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B IQK Success!!\n"));
result[t][4] = (odm_get_bb_reg(p_dm_odm, REG_TX_POWER_BEFORE_IQK_B, MASKDWORD) & 0x3FF0000) >> 16;
@ -2054,19 +1948,6 @@ phy_iq_calibrate_8188e(
}
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n"));
priv->pshare->IQK_total_cnt++;
#if 0/* Suggested by Edlu,120413 */
/* IQK on channel 7, should switch back when completed. */
/* origin_channel = p_hal_data->current_channel; */
origin_channel = *(p_dm_odm->p_channel);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
p_adapter->hal_func.sw_chnl_by_timer_handler(p_adapter, channel_to_iqk);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
p_adapter->hal_func.set_channel_handler(p_adapter, channel_to_iqk);
#endif
#endif
for (i = 0; i < 8; i++) {
result[0][i] = 0;
@ -2083,27 +1964,15 @@ phy_iq_calibrate_8188e(
for (i = 0; i < 3; i++) {
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
if (IS_92C_SERIAL(p_hal_data->version_id))
_phy_iq_calibrate_8188e(p_adapter, result, i, true);
else
#endif
{
else {
/* For 88C 1T1R */
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
_phy_iq_calibrate_8188e(p_adapter, result, i, false);
#else
_phy_iq_calibrate_8188e(p_dm_odm, result, i, false);
#endif
}
if (i == 1) {
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
is12simular = phy_simularity_compare_8188e(p_adapter, result, 0, 1);
#else
is12simular = phy_simularity_compare_8188e(p_dm_odm, result, 0, 1);
#endif
if (is12simular) {
final_candidate = 0;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n", final_candidate));
@ -2181,11 +2050,7 @@ phy_iq_calibrate_8188e(
}
if ((rege94 != 0)/*&&(regea4 != 0)*/) {
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
_phy_path_a_fill_iqk_matrix(p_adapter, is_patha_ok, result, final_candidate, (regea4 == 0));
#else
_phy_path_a_fill_iqk_matrix(p_dm_odm, is_patha_ok, result, final_candidate, (regea4 == 0));
#endif
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
@ -2195,11 +2060,7 @@ phy_iq_calibrate_8188e(
}
#endif
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
indexforchannel = odm_get_right_chnl_place_for_iqk(*p_dm_odm->p_channel);
#else
indexforchannel = 0;
#endif
/* To Fix BSOD when final_candidate is 0xff
* by sherry 20120321 */
@ -2210,57 +2071,25 @@ phy_iq_calibrate_8188e(
}
/* RTPRINT(FINIT, INIT_IQK, ("\nIQK OK indexforchannel %d.\n", indexforchannel)); */
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK indexforchannel %d.\n", indexforchannel));
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
_phy_save_adda_registers(p_adapter, IQK_BB_REG_92C, p_dm_odm->rf_calibrate_info.IQK_BB_backup_recover, 9);
#else
_phy_save_adda_registers(p_dm_odm, IQK_BB_REG_92C, p_dm_odm->rf_calibrate_info.IQK_BB_backup_recover, IQK_BB_REG_NUM);
#endif
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n"));
#if 0 /* Suggested by Edlu,120413 */
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
p_adapter->hal_func.sw_chnl_by_timer_handler(p_adapter, origin_channel);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
p_adapter->hal_func.set_channel_handler(p_adapter, origin_channel);
#endif
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
RESTORE_INT(x);
#endif
}
void
phy_lc_calibrate_8188e(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm
#else
struct _ADAPTER *p_adapter
#endif
)
{
bool /*is_start_cont_tx = false,*/ is_single_tone = false, is_carrier_suppression = false;
u32 timeout = 2000, timecount = 0;
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
#else /* (DM_ODM_SUPPORT_TYPE == ODM_CE) */
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv;
#endif
#if (MP_DRIVER == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PMPT_CONTEXT p_mpt_ctx = &(p_adapter->mpt_ctx);
#else/* (DM_ODM_SUPPORT_TYPE == ODM_CE) */
PMPT_CONTEXT p_mpt_ctx = &(p_adapter->mppriv.mpt_ctx);
#endif
#endif/* (MP_DRIVER == 1) */
#endif
@ -2338,32 +2167,6 @@ phy_ap_calibrate_8188e(
return;
#endif
#if 0
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
if (!(p_dm_odm->support_ability & ODM_RF_CALIBRATION))
return;
#endif
#if FOR_BRAZIL_PRETEST != 1
if (p_dm_odm->rf_calibrate_info.is_ap_kdone)
#endif
return;
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
if (IS_92C_SERIAL(p_hal_data->version_id))
_phy_ap_calibrate_8188e(p_adapter, delta, true);
else
#endif
{
/* For 88C 1T1R */
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
_phy_ap_calibrate_8188e(p_adapter, delta, false);
#else
_phy_ap_calibrate_8188e(p_dm_odm, delta, false);
#endif
}
#endif
}
void _phy_set_rf_path_switch_8188e(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm,
@ -2464,533 +2267,4 @@ void phy_set_rf_path_switch_8188e(
}
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
/* digital predistortion */
void
phy_digital_predistortion(
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
struct _ADAPTER *p_adapter,
#else
struct PHY_DM_STRUCT *p_dm_odm,
#endif
bool is2T
)
{
#if (RT_PLATFORM == PLATFORM_WINDOWS)
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv;
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
#endif
#endif
u32 tmp_reg, tmp_reg2, index, i;
u8 path, pathbound = PATH_NUM;
u32 AFE_backup[IQK_ADDA_REG_NUM];
u32 AFE_REG[IQK_ADDA_REG_NUM] = {
REG_FPGA0_XCD_SWITCH_CONTROL, REG_BLUE_TOOTH,
REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
REG_TX_OFDM_BBON, REG_TX_TO_RX,
REG_TX_TO_TX, REG_RX_CCK,
REG_RX_OFDM, REG_RX_WAIT_RIFS,
REG_RX_TO_RX, REG_STANDBY,
REG_SLEEP, REG_PMPD_ANAEN
};
u32 BB_backup[DP_BB_REG_NUM];
u32 BB_REG[DP_BB_REG_NUM] = {
REG_OFDM_0_TRX_PATH_ENABLE, REG_FPGA0_RFMOD,
REG_OFDM_0_TR_MUX_PAR, REG_FPGA0_XCD_RF_INTERFACE_SW,
REG_FPGA0_XAB_RF_INTERFACE_SW, REG_FPGA0_XA_RF_INTERFACE_OE,
REG_FPGA0_XB_RF_INTERFACE_OE
};
u32 BB_settings[DP_BB_REG_NUM] = {
0x00a05430, 0x02040000, 0x000800e4, 0x22208000,
0x0, 0x0, 0x0
};
u32 RF_backup[DP_PATH_NUM][DP_RF_REG_NUM];
u32 RF_REG[DP_RF_REG_NUM] = {
RF_TXBIAS_A
};
u32 MAC_backup[IQK_MAC_REG_NUM];
u32 MAC_REG[IQK_MAC_REG_NUM] = {
REG_TXPAUSE, REG_BCN_CTRL,
REG_BCN_CTRL_1, REG_GPIO_MUXCFG
};
u32 tx_agc[DP_DPK_NUM][DP_DPK_VALUE_NUM] = {
{0x1e1e1e1e, 0x03901e1e},
{0x18181818, 0x03901818},
{0x0e0e0e0e, 0x03900e0e}
};
u32 AFE_on_off[PATH_NUM] = {
0x04db25a4, 0x0b1b25a4
}; /* path A on path B off / path A off path B on */
u8 retry_count = 0;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_digital_predistortion()\n"));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_digital_predistortion for %s %s\n", (is2T ? "2T2R" : "1T1R")));
/* save BB default value */
for (index = 0; index < DP_BB_REG_NUM; index++)
BB_backup[index] = odm_get_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD);
/* save MAC default value */
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
_phy_save_mac_registers(p_adapter, BB_REG, MAC_backup);
#else
_phy_save_mac_registers(p_dm_odm, BB_REG, MAC_backup);
#endif
/* save RF default value */
for (path = 0; path < DP_PATH_NUM; path++) {
for (index = 0; index < DP_RF_REG_NUM; index++)
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
RF_backup[path][index] = phy_query_rf_reg(p_adapter, path, RF_REG[index], MASKDWORD);
#else
RF_backup[path][index] = odm_get_rf_reg(p_adapter, path, RF_REG[index], MASKDWORD);
#endif
}
/* save AFE default value */
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
_phy_save_adda_registers(p_adapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
#else
_phy_save_adda_registers(p_dm_odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
#endif
/* path A/B AFE all on */
for (index = 0; index < IQK_ADDA_REG_NUM ; index++)
odm_set_bb_reg(p_dm_odm, AFE_REG[index], MASKDWORD, 0x6fdb25a4);
/* BB register setting */
for (index = 0; index < DP_BB_REG_NUM; index++) {
if (index < 4)
odm_set_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD, BB_settings[index]);
else if (index == 4)
odm_set_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD, BB_backup[index] | BIT(10) | BIT(26));
else
odm_set_bb_reg(p_dm_odm, BB_REG[index], BIT(10), 0x00);
}
/* MAC register setting */
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
_phy_mac_setting_calibration(p_adapter, MAC_REG, MAC_backup);
#else
_phy_mac_setting_calibration(p_dm_odm, MAC_REG, MAC_backup);
#endif
/* PAGE-E IQC setting */
odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_A, MASKDWORD, 0x01008c00);
odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_A, MASKDWORD, 0x01008c00);
odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_B, MASKDWORD, 0x01008c00);
odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_B, MASKDWORD, 0x01008c00);
/* path_A DPK */
/* path B to standby mode */
odm_set_rf_reg(p_dm_odm, RF_PATH_B, RF_AC, MASKDWORD, 0x10000);
/* PA gain = 11 & PAD1 => tx_agc 1f ~11 */
/* PA gain = 11 & PAD2 => tx_agc 10~0e */
/* PA gain = 01 => tx_agc 0b~0d */
/* PA gain = 00 => tx_agc 0a~00 */
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x400000);
odm_set_bb_reg(p_dm_odm, 0xbc0, MASKDWORD, 0x0005361f);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0);
/* do inner loopback DPK 3 times */
for (i = 0; i < 3; i++) {
/* PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 */
for (index = 0; index < 3; index++)
odm_set_bb_reg(p_dm_odm, 0xe00 + index * 4, MASKDWORD, tx_agc[i][0]);
odm_set_bb_reg(p_dm_odm, 0xe00 + index * 4, MASKDWORD, tx_agc[i][1]);
for (index = 0; index < 4; index++)
odm_set_bb_reg(p_dm_odm, 0xe10 + index * 4, MASKDWORD, tx_agc[i][0]);
/* PAGE_B for path-A inner loopback DPK setting */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x02097098);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0xf76d9f84);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x0004ab87);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00880000);
/* ----send one shot signal---- */
/* path A */
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x80047788);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x00047788);
ODM_delay_ms(50);
}
/* PA gain = 11 => tx_agc = 1a */
for (index = 0; index < 3; index++)
odm_set_bb_reg(p_dm_odm, 0xe00 + index * 4, MASKDWORD, 0x34343434);
odm_set_bb_reg(p_dm_odm, 0xe08 + index * 4, MASKDWORD, 0x03903434);
for (index = 0; index < 4; index++)
odm_set_bb_reg(p_dm_odm, 0xe10 + index * 4, MASKDWORD, 0x34343434);
/* ==================================== */
/* PAGE_B for path-A DPK setting */
/* ==================================== */
/* open inner loopback @ b00[19]:10 od 0xb00 0x01097018 */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x02017098);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0xf76d9f84);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x0004ab87);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00880000);
/* rf_lpbk_setup */
/* 1.rf 00:5205a, rf 0d:0e52c */
odm_set_rf_reg(p_dm_odm, RF_PATH_A, 0x0c, MASKDWORD, 0x8992b);
odm_set_rf_reg(p_dm_odm, RF_PATH_A, 0x0d, MASKDWORD, 0x0e52c);
odm_set_rf_reg(p_dm_odm, RF_PATH_A, 0x00, MASKDWORD, 0x5205a);
/* ----send one shot signal---- */
/* path A */
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x800477c0);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x000477c0);
ODM_delay_ms(50);
while (retry_count < DP_RETRY_LIMIT && !p_dm_odm->rf_calibrate_info.is_dp_path_aok) {
/* ----read back measurement results---- */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x0c297018);
tmp_reg = odm_get_bb_reg(p_dm_odm, 0xbe0, MASKDWORD);
ODM_delay_ms(10);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x0c29701f);
tmp_reg2 = odm_get_bb_reg(p_dm_odm, 0xbe8, MASKDWORD);
ODM_delay_ms(10);
tmp_reg = (tmp_reg & MASKHWORD) >> 16;
tmp_reg2 = (tmp_reg2 & MASKHWORD) >> 16;
if (tmp_reg < 0xf0 || tmp_reg > 0x105 || tmp_reg2 > 0xff) {
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x02017098);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x800000);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x800477c0);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x000477c0);
ODM_delay_ms(50);
retry_count++;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK retry_count %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", retry_count, tmp_reg, tmp_reg2));
} else {
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n"));
p_dm_odm->rf_calibrate_info.is_dp_path_aok = true;
break;
}
}
retry_count = 0;
/* DPP path A */
if (p_dm_odm->rf_calibrate_info.is_dp_path_aok) {
/* DP settings */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x01017098);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0x776d9f84);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x0004ab87);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00880000);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x400000);
for (i = REG_PDP_ANT_A; i <= 0xb3c; i += 4) {
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x40004000);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i));
}
/* pwsf */
odm_set_bb_reg(p_dm_odm, 0xb40, MASKDWORD, 0x40404040);
odm_set_bb_reg(p_dm_odm, 0xb44, MASKDWORD, 0x28324040);
odm_set_bb_reg(p_dm_odm, 0xb48, MASKDWORD, 0x10141920);
for (i = 0xb4c; i <= 0xb5c; i += 4)
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x0c0c0c0c);
/* TX_AGC boundary */
odm_set_bb_reg(p_dm_odm, 0xbc0, MASKDWORD, 0x0005361f);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0);
} else {
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x00000000);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0x00000000);
}
/* DPK path B */
if (is2T) {
/* path A to standby mode */
odm_set_rf_reg(p_dm_odm, RF_PATH_A, RF_AC, MASKDWORD, 0x10000);
/* LUTs => tx_agc */
/* PA gain = 11 & PAD1, => tx_agc 1f ~11 */
/* PA gain = 11 & PAD2, => tx_agc 10 ~0e */
/* PA gain = 01 => tx_agc 0b ~0d */
/* PA gain = 00 => tx_agc 0a ~00 */
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x400000);
odm_set_bb_reg(p_dm_odm, 0xbc4, MASKDWORD, 0x0005361f);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0);
/* do inner loopback DPK 3 times */
for (i = 0; i < 3; i++) {
/* PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 */
for (index = 0; index < 4; index++)
odm_set_bb_reg(p_dm_odm, 0x830 + index * 4, MASKDWORD, tx_agc[i][0]);
for (index = 0; index < 2; index++)
odm_set_bb_reg(p_dm_odm, 0x848 + index * 4, MASKDWORD, tx_agc[i][0]);
for (index = 0; index < 2; index++)
odm_set_bb_reg(p_dm_odm, 0x868 + index * 4, MASKDWORD, tx_agc[i][0]);
/* PAGE_B for path-A inner loopback DPK setting */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x02097098);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0xf76d9f84);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x0004ab87);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_B, MASKDWORD, 0x00880000);
/* ----send one shot signal---- */
/* path B */
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x80047788);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x00047788);
ODM_delay_ms(50);
}
/* PA gain = 11 => tx_agc = 1a */
for (index = 0; index < 4; index++)
odm_set_bb_reg(p_dm_odm, 0x830 + index * 4, MASKDWORD, 0x34343434);
for (index = 0; index < 2; index++)
odm_set_bb_reg(p_dm_odm, 0x848 + index * 4, MASKDWORD, 0x34343434);
for (index = 0; index < 2; index++)
odm_set_bb_reg(p_dm_odm, 0x868 + index * 4, MASKDWORD, 0x34343434);
/* PAGE_B for path-B DPK setting */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x02017098);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0xf76d9f84);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x0004ab87);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_B, MASKDWORD, 0x00880000);
/* RF lpbk switches on */
odm_set_bb_reg(p_dm_odm, 0x840, MASKDWORD, 0x0101000f);
odm_set_bb_reg(p_dm_odm, 0x840, MASKDWORD, 0x01120103);
/* path-B RF lpbk */
odm_set_rf_reg(p_dm_odm, RF_PATH_B, 0x0c, MASKDWORD, 0x8992b);
odm_set_rf_reg(p_dm_odm, RF_PATH_B, 0x0d, MASKDWORD, 0x0e52c);
odm_set_rf_reg(p_dm_odm, RF_PATH_B, RF_AC, MASKDWORD, 0x5205a);
/* ----send one shot signal---- */
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x800477c0);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x000477c0);
ODM_delay_ms(50);
while (retry_count < DP_RETRY_LIMIT && !p_dm_odm->rf_calibrate_info.is_dp_path_bok) {
/* ----read back measurement results---- */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x0c297018);
tmp_reg = odm_get_bb_reg(p_dm_odm, 0xbf0, MASKDWORD);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x0c29701f);
tmp_reg2 = odm_get_bb_reg(p_dm_odm, 0xbf8, MASKDWORD);
tmp_reg = (tmp_reg & MASKHWORD) >> 16;
tmp_reg2 = (tmp_reg2 & MASKHWORD) >> 16;
if (tmp_reg < 0xf0 || tmp_reg > 0x105 || tmp_reg2 > 0xff) {
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x02017098);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x800000);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x800477c0);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x000477c0);
ODM_delay_ms(50);
retry_count++;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK retry_count %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", retry_count, tmp_reg, tmp_reg2));
} else {
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n"));
p_dm_odm->rf_calibrate_info.is_dp_path_bok = true;
break;
}
}
/* DPP path B */
if (p_dm_odm->rf_calibrate_info.is_dp_path_bok) {
/* DP setting */
/* LUT by SRAM */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x01017098);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0x776d9f84);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x0004ab87);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_B, MASKDWORD, 0x00880000);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x400000);
for (i = 0xb60; i <= 0xb9c; i += 4) {
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x40004000);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i));
}
/* PWSF */
odm_set_bb_reg(p_dm_odm, 0xba0, MASKDWORD, 0x40404040);
odm_set_bb_reg(p_dm_odm, 0xba4, MASKDWORD, 0x28324050);
odm_set_bb_reg(p_dm_odm, 0xba8, MASKDWORD, 0x0c141920);
for (i = 0xbac; i <= 0xbbc; i += 4)
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x0c0c0c0c);
/* tx_agc boundary */
odm_set_bb_reg(p_dm_odm, 0xbc4, MASKDWORD, 0x0005361f);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0);
} else {
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x00000000);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0x00000000);
}
}
/* reload BB default value */
for (index = 0; index < DP_BB_REG_NUM; index++)
odm_set_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD, BB_backup[index]);
/* reload RF default value */
for (path = 0; path < DP_PATH_NUM; path++) {
for (i = 0 ; i < DP_RF_REG_NUM ; i++)
odm_set_rf_reg(p_dm_odm, path, RF_REG[i], MASKDWORD, RF_backup[path][i]);
}
odm_set_rf_reg(p_dm_odm, RF_PATH_A, RF_MODE1, MASKDWORD, 0x1000f); /* standby mode */
odm_set_rf_reg(p_dm_odm, RF_PATH_A, RF_MODE2, MASKDWORD, 0x20101); /* RF lpbk switches off */
/* reload AFE default value */
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
_phy_reload_adda_registers(p_adapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
/* reload MAC default value */
_phy_reload_mac_registers(p_adapter, MAC_REG, MAC_backup);
#else
_phy_reload_adda_registers(p_dm_odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
/* reload MAC default value */
_phy_reload_mac_registers(p_dm_odm, MAC_REG, MAC_backup);
#endif
p_dm_odm->rf_calibrate_info.is_dp_done = true;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_digital_predistortion()\n"));
#endif
}
void
phy_digital_predistortion_8188e(
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
struct _ADAPTER *p_adapter
#else
struct PHY_DM_STRUCT *p_dm_odm
#endif
)
{
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv;
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
#endif
#endif
#ifdef DISABLE_BB_RF
return;
#endif
return;
if (p_dm_odm->rf_calibrate_info.is_dp_done)
return;
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
if (IS_92C_SERIAL(p_hal_data->version_id))
phy_digital_predistortion(p_adapter, true);
else
#endif
{
/* For 88C 1T1R */
phy_digital_predistortion(p_adapter, false);
}
}
/* return value true => Main; false => Aux */
bool _phy_query_rf_path_switch_8188e(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm,
#else
struct _ADAPTER *p_adapter,
#endif
bool is2T
)
{
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv;
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
#endif
#endif
if (!p_adapter->is_hw_init_ready) {
u8 u1b_tmp;
u1b_tmp = odm_read_1byte(p_dm_odm, REG_LEDCFG2) | BIT(7);
odm_write_1byte(p_dm_odm, REG_LEDCFG2, u1b_tmp);
/* odm_set_bb_reg(p_dm_odm, REG_LEDCFG0, BIT23, 0x01); */
odm_set_bb_reg(p_dm_odm, REG_FPGA0_XAB_RF_PARAMETER, BIT(13), 0x01);
}
if (is2T) {
if (odm_get_bb_reg(p_dm_odm, REG_FPGA0_XB_RF_INTERFACE_OE, BIT(5) | BIT(6)) == 0x01)
return true;
else
return false;
} else {
if ((odm_get_bb_reg(p_dm_odm, REG_FPGA0_XB_RF_INTERFACE_OE, BIT(5) | BIT(4) | BIT(3)) == 0x1))
return true;
else
return false;
}
}
/* return value true => Main; false => Aux */
bool phy_query_rf_path_switch_8188e(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm
#else
struct _ADAPTER *p_adapter
#endif
)
{
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
#ifdef DISABLE_BB_RF
return true;
#endif
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
/* if(IS_92C_SERIAL( p_hal_data->version_id)) { */
if (IS_2T2R(p_hal_data->version_id))
return _phy_query_rf_path_switch_8188e(p_adapter, true);
else
#endif
{
/* For 88C 1T1R */
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
return _phy_query_rf_path_switch_8188e(p_adapter, false);
#else
return _phy_query_rf_path_switch_8188e(p_dm_odm, false);
#endif
}
}
#endif

516
hal/phydm/rtl8188e/halphyrf_8188e_ce.c
View file

@ -21,20 +21,16 @@
#include "mp_precomp.h"
#include "../phydm_precomp.h"
/*---------------------------Define Local Constant---------------------------*/
/* 2010/04/25 MH Define the max tx power tracking tx agc power. */
#define ODM_TXPWRTRACK_MAX_IDX_88E 6
/*---------------------------Define Local Constant---------------------------*/
/* 3============================================================
* 3 Tx Power Tracking
* 3============================================================ */
static void set_iqk_matrix_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u8 OFDM_index,
@ -136,7 +132,6 @@ void do_iqk_8188e(
#endif
#endif
p_dm_odm->rf_calibrate_info.thermal_value_iqk = thermal_value;
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
phy_iq_calibrate_8188e(p_dm_odm, false);
@ -289,7 +284,6 @@ odm_tx_pwr_track_set_pwr88_e(
}
}
#endif
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
/* phy_rf6052_set_cck_tx_power(p_dm_odm->priv, *(p_dm_odm->p_channel)); */
@ -618,19 +612,7 @@ phy_path_a_iqk_8188e(
result |= 0x01;
else /* if Tx not OK, ignore Rx */
return result;
#if 0
if (!(reg_eac & BIT(27)) && /* if Tx is OK, check whether Rx is OK */
(((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
(((reg_eac & 0x03FF0000) >> 16) != 0x36))
result |= 0x02;
else
RT_DISP(FINIT, INIT_IQK, ("path A Rx IQK fail!!\n"));
#endif
return result;
}
static u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
@ -679,7 +661,6 @@ phy_path_a_rx_iqk(
/* platform_stall_execution(IQK_DELAY_TIME_88E*1000); */
ODM_delay_ms(IQK_DELAY_TIME_88E);
/* Check failed */
reg_eac = odm_get_bb_reg(p_dm_odm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", reg_eac));
@ -699,7 +680,6 @@ phy_path_a_rx_iqk(
odm_set_bb_reg(p_dm_odm, REG_TX_IQK, MASKDWORD, u4tmp);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", odm_get_bb_reg(p_dm_odm, REG_TX_IQK, MASKDWORD), u4tmp));
/* 1 RX IQK */
/* modify RXIQK mode table */
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path-A Rx IQK modify RXIQK mode table 2!\n"));
@ -743,15 +723,6 @@ phy_path_a_rx_iqk(
reg_ea4 = odm_get_bb_reg(p_dm_odm, REG_RX_POWER_BEFORE_IQK_A_2, MASKDWORD);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", reg_ea4));
#if 0
if (!(reg_eac & BIT(28)) &&
(((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
(((reg_e9c & 0x03FF0000) >> 16) != 0x42))
result |= 0x01;
else /* if Tx not OK, ignore Rx */
return result;
#endif
if (!(reg_eac & BIT(27)) && /* if Tx is OK, check whether Rx is OK */
(((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
(((reg_eac & 0x03FF0000) >> 16) != 0x36))
@ -760,8 +731,6 @@ phy_path_a_rx_iqk(
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A Rx IQK fail!!\n"));
return result;
}
static u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
@ -811,7 +780,6 @@ phy_path_b_iqk_8188e(
else
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B Rx IQK fail!!\n"));
return result;
}
@ -849,7 +817,6 @@ static void _phy_path_a_fill_iqk_matrix(
if ((Y & 0x00000200) != 0)
Y = Y | 0xFFFFFC00;
TX0_C = (Y * oldval_0) >> 8;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C));
odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XC_TX_AFE, 0xF0000000, ((TX0_C & 0x3C0) >> 6));
@ -957,7 +924,6 @@ _phy_save_adda_registers(
adda_backup[i] = odm_get_bb_reg(p_dm_odm, adda_reg[i], MASKDWORD);
}
static void _phy_save_mac_registers(
struct _ADAPTER *p_adapter,
u32 *mac_reg,
@ -974,7 +940,6 @@ static void _phy_save_mac_registers(
}
static void _phy_reload_adda_registers(
struct _ADAPTER *p_adapter,
u32 *adda_reg,
@ -1006,7 +971,6 @@ static void _phy_reload_mac_registers(
odm_write_4byte(p_dm_odm, mac_reg[i], mac_backup[i]);
}
void
_phy_path_adda_on(
struct _ADAPTER *p_adapter,
@ -1103,7 +1067,6 @@ static bool phy_simularity_compare_8188e(
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_simularity_compare_8188e c1 %d c2 %d!!!\n", c1, c2));
simularity_bit_map = 0;
for (i = 0; i < bound; i++) {
@ -1147,8 +1110,6 @@ static bool phy_simularity_compare_8188e(
}
static void _phy_iq_calibrate_8188e(
struct _ADAPTER *p_adapter,
s32 result[][8],
@ -1216,7 +1177,6 @@ static void _phy_iq_calibrate_8188e(
_phy_pi_mode_switch(p_adapter, true);
}
/* MAC settings */
_phy_mac_setting_calibration(p_adapter, IQK_MAC_REG, p_dm_odm->rf_calibrate_info.IQK_MAC_backup);
@ -1232,7 +1192,6 @@ static void _phy_iq_calibrate_8188e(
odm_set_bb_reg(p_dm_odm, REG_FPGA0_XA_RF_INTERFACE_OE, BIT(10), 0x00);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_XB_RF_INTERFACE_OE, BIT(10), 0x00);
if (is2T) {
odm_set_bb_reg(p_dm_odm, REG_FPGA0_XA_LSSI_PARAMETER, MASKDWORD, 0x00010000);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_XB_LSSI_PARAMETER, MASKDWORD, 0x00010000);
@ -1336,7 +1295,6 @@ static void _phy_iq_calibrate_8188e(
}
static void _phy_lc_calibrate_8188e(struct PHY_DM_STRUCT *p_dm_odm, bool is2T)
{
u8 tmp_reg;
@ -1376,7 +1334,6 @@ static void _phy_lc_calibrate_8188e(struct PHY_DM_STRUCT *p_dm_odm, bool is2T)
ODM_delay_ms(100);
/* Restore original situation */
if ((tmp_reg & 0x70) != 0) { /* Deal with contisuous TX case */
/* path-A */
@ -1737,7 +1694,6 @@ static void _phy_ap_calibrate_8188e(
tmp_reg = odm_get_bb_reg(p_dm_odm, REG_APK, 0xF8000000);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_phy_ap_calibrate_8188e() offset 0xbd8[25:21] %x\n", tmp_reg));
i++;
} while (tmp_reg > apkbound && i < 4);
@ -1775,7 +1731,6 @@ static void _phy_ap_calibrate_8188e(
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n"));
for (path = 0; path < pathbound; path++) {
odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3, MASKDWORD,
((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1]));
@ -1794,8 +1749,6 @@ static void _phy_ap_calibrate_8188e(
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==_phy_ap_calibrate_8188e()\n"));
}
#define DP_BB_REG_NUM 7
#define DP_RF_REG_NUM 1
#define DP_RETRY_LIMIT 10
@ -1803,10 +1756,6 @@ static void _phy_ap_calibrate_8188e(
#define DP_DPK_NUM 3
#define DP_DPK_VALUE_NUM 2
void
phy_iq_calibrate_8188e(
struct _ADAPTER *p_adapter,
@ -1869,18 +1818,13 @@ phy_iq_calibrate_8188e(
return;
}
odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK);
p_dm_odm->rf_calibrate_info.is_iqk_in_progress = true;
odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK);
start_time = odm_get_current_time(p_dm_odm);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n"));
for (i = 0; i < 8; i++) {
result[0][i] = 0;
result[1][i] = 0;
@ -1894,7 +1838,6 @@ phy_iq_calibrate_8188e(
is23simular = false;
is13simular = false;
for (i = 0; i < 3; i++) {
/* For 88C 1T1R */
_phy_iq_calibrate_8188e(p_adapter, result, i, false);
@ -1992,7 +1935,6 @@ phy_iq_calibrate_8188e(
}
void
phy_lc_calibrate_8188e(
void *p_dm_void
@ -2004,7 +1946,6 @@ phy_lc_calibrate_8188e(
s32 progressing_time;
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
struct _ADAPTER *p_adapter = p_dm_odm->adapter;
/* HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); */
@ -2018,7 +1959,6 @@ phy_lc_calibrate_8188e(
}
#endif
#if DISABLE_BB_RF
return;
#endif
@ -2100,17 +2040,11 @@ static void _phy_set_rf_path_switch_8188e(
}
}
void phy_set_rf_path_switch_8188e(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm,
#else
struct _ADAPTER *p_adapter,
#endif
bool is_main
)
{
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
#endif
#if DISABLE_BB_RF
return;
@ -2118,458 +2052,8 @@ void phy_set_rf_path_switch_8188e(
{
/* For 88C 1T1R */
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
_phy_set_rf_path_switch_8188e(p_adapter, is_main, false);
#else
_phy_set_rf_path_switch_8188e(p_dm_odm, is_main, false);
#endif
}
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
/* digital predistortion */
void
phy_digital_predistortion(
struct _ADAPTER *p_adapter,
bool is2T
)
{
#if (RT_PLATFORM == PLATFORM_WINDOWS)
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv;
u32 tmp_reg, tmp_reg2, index, i;
u8 path, pathbound = PATH_NUM;
u32 AFE_backup[IQK_ADDA_REG_NUM];
u32 AFE_REG[IQK_ADDA_REG_NUM] = {
REG_FPGA0_XCD_SWITCH_CONTROL, REG_BLUE_TOOTH,
REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
REG_TX_OFDM_BBON, REG_TX_TO_RX,
REG_TX_TO_TX, REG_RX_CCK,
REG_RX_OFDM, REG_RX_WAIT_RIFS,
REG_RX_TO_RX, REG_STANDBY,
REG_SLEEP, REG_PMPD_ANAEN
};
u32 BB_backup[DP_BB_REG_NUM];
u32 BB_REG[DP_BB_REG_NUM] = {
REG_OFDM_0_TRX_PATH_ENABLE, REG_FPGA0_RFMOD,
REG_OFDM_0_TR_MUX_PAR, REG_FPGA0_XCD_RF_INTERFACE_SW,
REG_FPGA0_XAB_RF_INTERFACE_SW, REG_FPGA0_XA_RF_INTERFACE_OE,
REG_FPGA0_XB_RF_INTERFACE_OE
};
u32 BB_settings[DP_BB_REG_NUM] = {
0x00a05430, 0x02040000, 0x000800e4, 0x22208000,
0x0, 0x0, 0x0
};
u32 RF_backup[DP_PATH_NUM][DP_RF_REG_NUM];
u32 RF_REG[DP_RF_REG_NUM] = {
RF_TXBIAS_A
};
u32 MAC_backup[IQK_MAC_REG_NUM];
u32 MAC_REG[IQK_MAC_REG_NUM] = {
REG_TXPAUSE, REG_BCN_CTRL,
REG_BCN_CTRL_1, REG_GPIO_MUXCFG
};
u32 tx_agc[DP_DPK_NUM][DP_DPK_VALUE_NUM] = {
{0x1e1e1e1e, 0x03901e1e},
{0x18181818, 0x03901818},
{0x0e0e0e0e, 0x03900e0e}
};
u32 AFE_on_off[PATH_NUM] = {
0x04db25a4, 0x0b1b25a4
}; /* path A on path B off / path A off path B on */
u8 retry_count = 0;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_digital_predistortion()\n"));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_digital_predistortion for %s\n", (is2T ? "2T2R" : "1T1R")));
/* save BB default value */
for (index = 0; index < DP_BB_REG_NUM; index++)
BB_backup[index] = odm_get_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD);
/* save MAC default value */
_phy_save_mac_registers(p_adapter, BB_REG, MAC_backup);
/* save RF default value */
for (path = 0; path < DP_PATH_NUM; path++) {
for (index = 0; index < DP_RF_REG_NUM; index++)
RF_backup[path][index] = phy_query_rf_reg(p_adapter, path, RF_REG[index], MASKDWORD);
}
/* save AFE default value */
_phy_save_adda_registers(p_adapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
/* path A/B AFE all on */
for (index = 0; index < IQK_ADDA_REG_NUM ; index++)
odm_set_bb_reg(p_dm_odm, AFE_REG[index], MASKDWORD, 0x6fdb25a4);
/* BB register setting */
for (index = 0; index < DP_BB_REG_NUM; index++) {
if (index < 4)
odm_set_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD, BB_settings[index]);
else if (index == 4)
odm_set_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD, BB_backup[index] | BIT(10) | BIT(26));
else
odm_set_bb_reg(p_dm_odm, BB_REG[index], BIT(10), 0x00);
}
/* MAC register setting */
_phy_mac_setting_calibration(p_adapter, MAC_REG, MAC_backup);
/* PAGE-E IQC setting */
odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_A, MASKDWORD, 0x01008c00);
odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_A, MASKDWORD, 0x01008c00);
odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_B, MASKDWORD, 0x01008c00);
odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_B, MASKDWORD, 0x01008c00);
/* path_A DPK */
/* path B to standby mode */
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, RF_AC, MASKDWORD, 0x10000);
/* PA gain = 11 & PAD1 => tx_agc 1f ~11 */
/* PA gain = 11 & PAD2 => tx_agc 10~0e */
/* PA gain = 01 => tx_agc 0b~0d */
/* PA gain = 00 => tx_agc 0a~00 */
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x400000);
odm_set_bb_reg(p_dm_odm, 0xbc0, MASKDWORD, 0x0005361f);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
/* do inner loopback DPK 3 times */
for (i = 0; i < 3; i++) {
/* PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 */
for (index = 0; index < 3; index++)
odm_set_bb_reg(p_dm_odm, 0xe00 + index * 4, MASKDWORD, tx_agc[i][0]);
odm_set_bb_reg(p_dm_odm, 0xe00 + index * 4, MASKDWORD, tx_agc[i][1]);
for (index = 0; index < 4; index++)
odm_set_bb_reg(p_dm_odm, 0xe10 + index * 4, MASKDWORD, tx_agc[i][0]);
/* PAGE_B for path-A inner loopback DPK setting */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x02097098);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0xf76d9f84);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x0004ab87);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00880000);
/* ----send one shot signal---- */
/* path A */
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x80047788);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x00047788);
ODM_delay_ms(50);
}
/* PA gain = 11 => tx_agc = 1a */
for (index = 0; index < 3; index++)
odm_set_bb_reg(p_dm_odm, 0xe00 + index * 4, MASKDWORD, 0x34343434);
odm_set_bb_reg(p_dm_odm, 0xe08 + index * 4, MASKDWORD, 0x03903434);
for (index = 0; index < 4; index++)
odm_set_bb_reg(p_dm_odm, 0xe10 + index * 4, MASKDWORD, 0x34343434);
/* ==================================== */
/* PAGE_B for path-A DPK setting */
/* ==================================== */
/* open inner loopback @ b00[19]:10 od 0xb00 0x01097018 */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x02017098);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0xf76d9f84);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x0004ab87);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00880000);
/* rf_lpbk_setup */
/* 1.rf 00:5205a, rf 0d:0e52c */
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0c, MASKDWORD, 0x8992b);
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0d, MASKDWORD, 0x0e52c);
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x00, MASKDWORD, 0x5205a);
/* ----send one shot signal---- */
/* path A */
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x800477c0);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x000477c0);
ODM_delay_ms(50);
while (retry_count < DP_RETRY_LIMIT && !p_dm_odm->rf_calibrate_info.is_dp_path_aok) {
/* ----read back measurement results---- */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x0c297018);
tmp_reg = odm_get_bb_reg(p_dm_odm, 0xbe0, MASKDWORD);
ODM_delay_ms(10);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x0c29701f);
tmp_reg2 = odm_get_bb_reg(p_dm_odm, 0xbe8, MASKDWORD);
ODM_delay_ms(10);
tmp_reg = (tmp_reg & MASKHWORD) >> 16;
tmp_reg2 = (tmp_reg2 & MASKHWORD) >> 16;
if (tmp_reg < 0xf0 || tmp_reg > 0x105 || tmp_reg2 > 0xff) {
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x02017098);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x800000);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x800477c0);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x000477c0);
ODM_delay_ms(50);
retry_count++;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK retry_count %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", retry_count, tmp_reg, tmp_reg2));
} else {
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n"));
p_dm_odm->rf_calibrate_info.is_dp_path_aok = true;
break;
}
}
retry_count = 0;
/* DPP path A */
if (p_dm_odm->rf_calibrate_info.is_dp_path_aok) {
/* DP settings */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x01017098);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0x776d9f84);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x0004ab87);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00880000);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x400000);
for (i = REG_PDP_ANT_A; i <= 0xb3c; i += 4) {
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x40004000);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i));
}
/* pwsf */
odm_set_bb_reg(p_dm_odm, 0xb40, MASKDWORD, 0x40404040);
odm_set_bb_reg(p_dm_odm, 0xb44, MASKDWORD, 0x28324040);
odm_set_bb_reg(p_dm_odm, 0xb48, MASKDWORD, 0x10141920);
for (i = 0xb4c; i <= 0xb5c; i += 4)
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x0c0c0c0c);
/* TX_AGC boundary */
odm_set_bb_reg(p_dm_odm, 0xbc0, MASKDWORD, 0x0005361f);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
} else {
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x00000000);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0x00000000);
}
/* DPK path B */
if (is2T) {
/* path A to standby mode */
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_AC, MASKDWORD, 0x10000);
/* LUTs => tx_agc */
/* PA gain = 11 & PAD1, => tx_agc 1f ~11 */
/* PA gain = 11 & PAD2, => tx_agc 10 ~0e */
/* PA gain = 01 => tx_agc 0b ~0d */
/* PA gain = 00 => tx_agc 0a ~00 */
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x400000);
odm_set_bb_reg(p_dm_odm, 0xbc4, MASKDWORD, 0x0005361f);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
/* do inner loopback DPK 3 times */
for (i = 0; i < 3; i++) {
/* PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 */
for (index = 0; index < 4; index++)
odm_set_bb_reg(p_dm_odm, 0x830 + index * 4, MASKDWORD, tx_agc[i][0]);
for (index = 0; index < 2; index++)
odm_set_bb_reg(p_dm_odm, 0x848 + index * 4, MASKDWORD, tx_agc[i][0]);
for (index = 0; index < 2; index++)
odm_set_bb_reg(p_dm_odm, 0x868 + index * 4, MASKDWORD, tx_agc[i][0]);
/* PAGE_B for path-A inner loopback DPK setting */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x02097098);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0xf76d9f84);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x0004ab87);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_B, MASKDWORD, 0x00880000);
/* ----send one shot signal---- */
/* path B */
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x80047788);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x00047788);
ODM_delay_ms(50);
}
/* PA gain = 11 => tx_agc = 1a */
for (index = 0; index < 4; index++)
odm_set_bb_reg(p_dm_odm, 0x830 + index * 4, MASKDWORD, 0x34343434);
for (index = 0; index < 2; index++)
odm_set_bb_reg(p_dm_odm, 0x848 + index * 4, MASKDWORD, 0x34343434);
for (index = 0; index < 2; index++)
odm_set_bb_reg(p_dm_odm, 0x868 + index * 4, MASKDWORD, 0x34343434);
/* PAGE_B for path-B DPK setting */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x02017098);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0xf76d9f84);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x0004ab87);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_B, MASKDWORD, 0x00880000);
/* RF lpbk switches on */
odm_set_bb_reg(p_dm_odm, 0x840, MASKDWORD, 0x0101000f);
odm_set_bb_reg(p_dm_odm, 0x840, MASKDWORD, 0x01120103);
/* path-B RF lpbk */
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x0c, MASKDWORD, 0x8992b);
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x0d, MASKDWORD, 0x0e52c);
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, RF_AC, MASKDWORD, 0x5205a);
/* ----send one shot signal---- */
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x800477c0);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x000477c0);
ODM_delay_ms(50);
while (retry_count < DP_RETRY_LIMIT && !p_dm_odm->rf_calibrate_info.is_dp_path_bok) {
/* ----read back measurement results---- */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x0c297018);
tmp_reg = odm_get_bb_reg(p_dm_odm, 0xbf0, MASKDWORD);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x0c29701f);
tmp_reg2 = odm_get_bb_reg(p_dm_odm, 0xbf8, MASKDWORD);
tmp_reg = (tmp_reg & MASKHWORD) >> 16;
tmp_reg2 = (tmp_reg2 & MASKHWORD) >> 16;
if (tmp_reg < 0xf0 || tmp_reg > 0x105 || tmp_reg2 > 0xff) {
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x02017098);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x800000);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x800477c0);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x000477c0);
ODM_delay_ms(50);
retry_count++;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK retry_count %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", retry_count, tmp_reg, tmp_reg2));
} else {
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n"));
p_dm_odm->rf_calibrate_info.is_dp_path_bok = true;
break;
}
}
/* DPP path B */
if (p_dm_odm->rf_calibrate_info.is_dp_path_bok) {
/* DP setting */
/* LUT by SRAM */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x01017098);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0x776d9f84);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x0004ab87);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_B, MASKDWORD, 0x00880000);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x400000);
for (i = 0xb60; i <= 0xb9c; i += 4) {
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x40004000);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i));
}
/* PWSF */
odm_set_bb_reg(p_dm_odm, 0xba0, MASKDWORD, 0x40404040);
odm_set_bb_reg(p_dm_odm, 0xba4, MASKDWORD, 0x28324050);
odm_set_bb_reg(p_dm_odm, 0xba8, MASKDWORD, 0x0c141920);
for (i = 0xbac; i <= 0xbbc; i += 4)
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x0c0c0c0c);
/* tx_agc boundary */
odm_set_bb_reg(p_dm_odm, 0xbc4, MASKDWORD, 0x0005361f);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, MASKH3BYTES, 0x000000);
} else {
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x00000000);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0x00000000);
}
}
/* reload BB default value */
for (index = 0; index < DP_BB_REG_NUM; index++)
odm_set_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD, BB_backup[index]);
/* reload RF default value */
for (path = 0; path < DP_PATH_NUM; path++) {
for (i = 0 ; i < DP_RF_REG_NUM ; i++)
odm_set_rf_reg(p_dm_odm, path, RF_REG[i], MASKDWORD, RF_backup[path][i]);
}
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_MODE1, MASKDWORD, 0x1000f); /* standby mode */
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_MODE2, MASKDWORD, 0x20101); /* RF lpbk switches off */
/* reload AFE default value */
_phy_reload_adda_registers(p_adapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
/* reload MAC default value */
_phy_reload_mac_registers(p_adapter, MAC_REG, MAC_backup);
p_dm_odm->rf_calibrate_info.is_dp_done = true;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_digital_predistortion()\n"));
#endif
}
void
phy_digital_predistortion_8188e(
struct _ADAPTER *p_adapter
)
{
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv;
return;
}
/* return value true => Main; false => Aux */
bool _phy_query_rf_path_switch_8188e(
struct _ADAPTER *p_adapter,
bool is2T
)
{
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv;
if (!p_adapter->is_hw_init_ready) {
u8 u1b_tmp;
u1b_tmp = odm_read_1byte(p_dm_odm, REG_LEDCFG2) | BIT(7);
odm_write_1byte(p_dm_odm, REG_LEDCFG2, u1b_tmp);
/* odm_set_bb_reg(p_dm_odm, REG_LEDCFG0, BIT23, 0x01); */
odm_set_bb_reg(p_dm_odm, REG_FPGA0_XAB_RF_PARAMETER, BIT(13), 0x01);
}
if (is2T) {
if (odm_get_bb_reg(p_dm_odm, REG_FPGA0_XB_RF_INTERFACE_OE, BIT(5) | BIT(6)) == 0x01)
return true;
else
return false;
} else {
if ((odm_get_bb_reg(p_dm_odm, REG_FPGA0_XB_RF_INTERFACE_OE, BIT(5) | BIT(4) | BIT(3)) == 0x1))
return true;
else
return false;
}
}
/* return value true => Main; false => Aux */
bool phy_query_rf_path_switch_8188e(
struct _ADAPTER *p_adapter
)
{
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
#if DISABLE_BB_RF
return true;
#endif
if (IS_2T2R(p_hal_data->version_id))
return _phy_query_rf_path_switch_8188e(p_adapter, true);
else
{
/* For 88C 1T1R */
return _phy_query_rf_path_switch_8188e(p_adapter, false);
}
}
#endif

418
hal/phydm/rtl8188e/halphyrf_8188e_win.c
View file

@ -2668,428 +2668,15 @@ phy_digital_predistortion(
bool is2T
)
{
#if (RT_PLATFORM == PLATFORM_WINDOWS)
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv;
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
#endif
#endif
struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
u32 tmp_reg, tmp_reg2, index, i;
u8 path, pathbound = PATH_NUM;
u32 AFE_backup[IQK_ADDA_REG_NUM];
u32 AFE_REG[IQK_ADDA_REG_NUM] = {
REG_FPGA0_XCD_SWITCH_CONTROL, REG_BLUE_TOOTH,
REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
REG_TX_OFDM_BBON, REG_TX_TO_RX,
REG_TX_TO_TX, REG_RX_CCK,
REG_RX_OFDM, REG_RX_WAIT_RIFS,
REG_RX_TO_RX, REG_STANDBY,
REG_SLEEP, REG_PMPD_ANAEN
};
u32 BB_backup[DP_BB_REG_NUM];
u32 BB_REG[DP_BB_REG_NUM] = {
REG_OFDM_0_TRX_PATH_ENABLE, REG_FPGA0_RFMOD,
REG_OFDM_0_TR_MUX_PAR, REG_FPGA0_XCD_RF_INTERFACE_SW,
REG_FPGA0_XAB_RF_INTERFACE_SW, REG_FPGA0_XA_RF_INTERFACE_OE,
REG_FPGA0_XB_RF_INTERFACE_OE
};
u32 BB_settings[DP_BB_REG_NUM] = {
0x00a05430, 0x02040000, 0x000800e4, 0x22208000,
0x0, 0x0, 0x0
};
u32 RF_backup[DP_PATH_NUM][DP_RF_REG_NUM];
u32 RF_REG[DP_RF_REG_NUM] = {
RF_TXBIAS_A
};
u32 MAC_backup[IQK_MAC_REG_NUM];
u32 MAC_REG[IQK_MAC_REG_NUM] = {
REG_TXPAUSE, REG_BCN_CTRL,
REG_BCN_CTRL_1, REG_GPIO_MUXCFG
};
u32 tx_agc[DP_DPK_NUM][DP_DPK_VALUE_NUM] = {
{0x1e1e1e1e, 0x03901e1e},
{0x18181818, 0x03901818},
{0x0e0e0e0e, 0x03900e0e}
};
u32 AFE_on_off[PATH_NUM] = {
0x04db25a4, 0x0b1b25a4
}; /* path A on path B off / path A off path B on */
u8 retry_count = 0;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_digital_predistortion()\n"));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_digital_predistortion for %s\n", (is2T ? "2T2R" : "1T1R")));
/* save BB default value */
for (index = 0; index < DP_BB_REG_NUM; index++)
BB_backup[index] = odm_get_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD);
/* save MAC default value */
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
_phy_save_mac_registers(p_adapter, BB_REG, MAC_backup);
#else
_phy_save_mac_registers(p_dm_odm, BB_REG, MAC_backup);
#endif
/* save RF default value */
for (path = 0; path < DP_PATH_NUM; path++) {
for (index = 0; index < DP_RF_REG_NUM; index++)
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
RF_backup[path][index] = odm_get_rf_reg(p_dm_odm, path, RF_REG[index], MASKDWORD);
#else
RF_backup[path][index] = odm_get_rf_reg(p_dm_odm, path, RF_REG[index], MASKDWORD);
#endif
}
/* save AFE default value */
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
_phy_save_adda_registers(p_adapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
#else
_phy_save_adda_registers(p_dm_odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
#endif
/* path A/B AFE all on */
for (index = 0; index < IQK_ADDA_REG_NUM ; index++)
odm_set_bb_reg(p_dm_odm, AFE_REG[index], MASKDWORD, 0x6fdb25a4);
/* BB register setting */
for (index = 0; index < DP_BB_REG_NUM; index++) {
if (index < 4)
odm_set_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD, BB_settings[index]);
else if (index == 4)
odm_set_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD, BB_backup[index] | BIT(10) | BIT(26));
else
odm_set_bb_reg(p_dm_odm, BB_REG[index], BIT(10), 0x00);
}
/* MAC register setting */
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
_phy_mac_setting_calibration(p_adapter, MAC_REG, MAC_backup);
#else
_phy_mac_setting_calibration(p_dm_odm, MAC_REG, MAC_backup);
#endif
/* PAGE-E IQC setting */
odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_A, MASKDWORD, 0x01008c00);
odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_A, MASKDWORD, 0x01008c00);
odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_B, MASKDWORD, 0x01008c00);
odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_B, MASKDWORD, 0x01008c00);
/* path_A DPK */
/* path B to standby mode */
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, RF_AC, MASKDWORD, 0x10000);
/* PA gain = 11 & PAD1 => tx_agc 1f ~11 */
/* PA gain = 11 & PAD2 => tx_agc 10~0e */
/* PA gain = 01 => tx_agc 0b~0d */
/* PA gain = 00 => tx_agc 0a~00 */
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x400000);
odm_set_bb_reg(p_dm_odm, 0xbc0, MASKDWORD, 0x0005361f);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
/* do inner loopback DPK 3 times */
for (i = 0; i < 3; i++) {
/* PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 */
for (index = 0; index < 3; index++)
odm_set_bb_reg(p_dm_odm, 0xe00 + index * 4, MASKDWORD, tx_agc[i][0]);
odm_set_bb_reg(p_dm_odm, 0xe00 + index * 4, MASKDWORD, tx_agc[i][1]);
for (index = 0; index < 4; index++)
odm_set_bb_reg(p_dm_odm, 0xe10 + index * 4, MASKDWORD, tx_agc[i][0]);
/* PAGE_B for path-A inner loopback DPK setting */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x02097098);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0xf76d9f84);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x0004ab87);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00880000);
/* ----send one shot signal---- */
/* path A */
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x80047788);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x00047788);
ODM_delay_ms(50);
}
/* PA gain = 11 => tx_agc = 1a */
for (index = 0; index < 3; index++)
odm_set_bb_reg(p_dm_odm, 0xe00 + index * 4, MASKDWORD, 0x34343434);
odm_set_bb_reg(p_dm_odm, 0xe08 + index * 4, MASKDWORD, 0x03903434);
for (index = 0; index < 4; index++)
odm_set_bb_reg(p_dm_odm, 0xe10 + index * 4, MASKDWORD, 0x34343434);
/* ==================================== */
/* PAGE_B for path-A DPK setting */
/* ==================================== */
/* open inner loopback @ b00[19]:10 od 0xb00 0x01097018 */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x02017098);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0xf76d9f84);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x0004ab87);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00880000);
/* rf_lpbk_setup */
/* 1.rf 00:5205a, rf 0d:0e52c */
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0c, MASKDWORD, 0x8992b);
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0d, MASKDWORD, 0x0e52c);
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x00, MASKDWORD, 0x5205a);
/* ----send one shot signal---- */
/* path A */
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x800477c0);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x000477c0);
ODM_delay_ms(50);
while (retry_count < DP_RETRY_LIMIT && !p_rf_calibrate_info->is_dp_path_aok) {
/* ----read back measurement results---- */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x0c297018);
tmp_reg = odm_get_bb_reg(p_dm_odm, 0xbe0, MASKDWORD);
ODM_delay_ms(10);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x0c29701f);
tmp_reg2 = odm_get_bb_reg(p_dm_odm, 0xbe8, MASKDWORD);
ODM_delay_ms(10);
tmp_reg = (tmp_reg & MASKHWORD) >> 16;
tmp_reg2 = (tmp_reg2 & MASKHWORD) >> 16;
if (tmp_reg < 0xf0 || tmp_reg > 0x105 || tmp_reg2 > 0xff) {
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x02017098);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x800000);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x800477c0);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x000477c0);
ODM_delay_ms(50);
retry_count++;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK retry_count %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", retry_count, tmp_reg, tmp_reg2));
} else {
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n"));
p_rf_calibrate_info->is_dp_path_aok = true;
break;
}
}
retry_count = 0;
/* DPP path A */
if (p_rf_calibrate_info->is_dp_path_aok) {
/* DP settings */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x01017098);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0x776d9f84);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_A, MASKDWORD, 0x0004ab87);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00880000);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x400000);
for (i = REG_PDP_ANT_A; i <= 0xb3c; i += 4) {
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x40004000);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i));
}
/* pwsf */
odm_set_bb_reg(p_dm_odm, 0xb40, MASKDWORD, 0x40404040);
odm_set_bb_reg(p_dm_odm, 0xb44, MASKDWORD, 0x28324040);
odm_set_bb_reg(p_dm_odm, 0xb48, MASKDWORD, 0x10141920);
for (i = 0xb4c; i <= 0xb5c; i += 4)
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x0c0c0c0c);
/* TX_AGC boundary */
odm_set_bb_reg(p_dm_odm, 0xbc0, MASKDWORD, 0x0005361f);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
} else {
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A, MASKDWORD, 0x00000000);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_A_4, MASKDWORD, 0x00000000);
}
/* DPK path B */
if (is2T) {
/* path A to standby mode */
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_AC, MASKDWORD, 0x10000);
/* LUTs => tx_agc */
/* PA gain = 11 & PAD1, => tx_agc 1f ~11 */
/* PA gain = 11 & PAD2, => tx_agc 10 ~0e */
/* PA gain = 01 => tx_agc 0b ~0d */
/* PA gain = 00 => tx_agc 0a ~00 */
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x400000);
odm_set_bb_reg(p_dm_odm, 0xbc4, MASKDWORD, 0x0005361f);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
/* do inner loopback DPK 3 times */
for (i = 0; i < 3; i++) {
/* PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 */
for (index = 0; index < 4; index++)
odm_set_bb_reg(p_dm_odm, 0x830 + index * 4, MASKDWORD, tx_agc[i][0]);
for (index = 0; index < 2; index++)
odm_set_bb_reg(p_dm_odm, 0x848 + index * 4, MASKDWORD, tx_agc[i][0]);
for (index = 0; index < 2; index++)
odm_set_bb_reg(p_dm_odm, 0x868 + index * 4, MASKDWORD, tx_agc[i][0]);
/* PAGE_B for path-A inner loopback DPK setting */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x02097098);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0xf76d9f84);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x0004ab87);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_B, MASKDWORD, 0x00880000);
/* ----send one shot signal---- */
/* path B */
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x80047788);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x00047788);
ODM_delay_ms(50);
}
/* PA gain = 11 => tx_agc = 1a */
for (index = 0; index < 4; index++)
odm_set_bb_reg(p_dm_odm, 0x830 + index * 4, MASKDWORD, 0x34343434);
for (index = 0; index < 2; index++)
odm_set_bb_reg(p_dm_odm, 0x848 + index * 4, MASKDWORD, 0x34343434);
for (index = 0; index < 2; index++)
odm_set_bb_reg(p_dm_odm, 0x868 + index * 4, MASKDWORD, 0x34343434);
/* PAGE_B for path-B DPK setting */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x02017098);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0xf76d9f84);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x0004ab87);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_B, MASKDWORD, 0x00880000);
/* RF lpbk switches on */
odm_set_bb_reg(p_dm_odm, 0x840, MASKDWORD, 0x0101000f);
odm_set_bb_reg(p_dm_odm, 0x840, MASKDWORD, 0x01120103);
/* path-B RF lpbk */
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x0c, MASKDWORD, 0x8992b);
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x0d, MASKDWORD, 0x0e52c);
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, RF_AC, MASKDWORD, 0x5205a);
/* ----send one shot signal---- */
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x800477c0);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x000477c0);
ODM_delay_ms(50);
while (retry_count < DP_RETRY_LIMIT && !p_rf_calibrate_info->is_dp_path_bok) {
/* ----read back measurement results---- */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x0c297018);
tmp_reg = odm_get_bb_reg(p_dm_odm, 0xbf0, MASKDWORD);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x0c29701f);
tmp_reg2 = odm_get_bb_reg(p_dm_odm, 0xbf8, MASKDWORD);
tmp_reg = (tmp_reg & MASKHWORD) >> 16;
tmp_reg2 = (tmp_reg2 & MASKHWORD) >> 16;
if (tmp_reg < 0xf0 || tmp_reg > 0x105 || tmp_reg2 > 0xff) {
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x02017098);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x800000);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x800477c0);
ODM_delay_ms(1);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x000477c0);
ODM_delay_ms(50);
retry_count++;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK retry_count %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", retry_count, tmp_reg, tmp_reg2));
} else {
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n"));
p_rf_calibrate_info->is_dp_path_bok = true;
break;
}
}
/* DPP path B */
if (p_rf_calibrate_info->is_dp_path_bok) {
/* DP setting */
/* LUT by SRAM */
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x01017098);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0x776d9f84);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_PMPD_ANT_B, MASKDWORD, 0x0004ab87);
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_B, MASKDWORD, 0x00880000);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x400000);
for (i = 0xb60; i <= 0xb9c; i += 4) {
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x40004000);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i));
}
/* PWSF */
odm_set_bb_reg(p_dm_odm, 0xba0, MASKDWORD, 0x40404040);
odm_set_bb_reg(p_dm_odm, 0xba4, MASKDWORD, 0x28324050);
odm_set_bb_reg(p_dm_odm, 0xba8, MASKDWORD, 0x0c141920);
for (i = 0xbac; i <= 0xbbc; i += 4)
odm_set_bb_reg(p_dm_odm, i, MASKDWORD, 0x0c0c0c0c);
/* tx_agc boundary */
odm_set_bb_reg(p_dm_odm, 0xbc4, MASKDWORD, 0x0005361f);
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
} else {
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B, MASKDWORD, 0x00000000);
odm_set_bb_reg(p_dm_odm, REG_PDP_ANT_B_4, MASKDWORD, 0x00000000);
}
}
/* reload BB default value */
for (index = 0; index < DP_BB_REG_NUM; index++)
odm_set_bb_reg(p_dm_odm, BB_REG[index], MASKDWORD, BB_backup[index]);
/* reload RF default value */
for (path = 0; path < DP_PATH_NUM; path++) {
for (i = 0 ; i < DP_RF_REG_NUM ; i++)
odm_set_rf_reg(p_dm_odm, path, RF_REG[i], MASKDWORD, RF_backup[path][i]);
}
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_MODE1, MASKDWORD, 0x1000f); /* standby mode */
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_MODE2, MASKDWORD, 0x20101); /* RF lpbk switches off */
/* reload AFE default value */
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
_phy_reload_adda_registers(p_adapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
/* reload MAC default value */
_phy_reload_mac_registers(p_adapter, MAC_REG, MAC_backup);
#else
_phy_reload_adda_registers(p_dm_odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
/* reload MAC default value */
_phy_reload_mac_registers(p_dm_odm, MAC_REG, MAC_backup);
#endif
p_rf_calibrate_info->is_dp_done = true;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_digital_predistortion()\n"));
#endif
}
void
phy_digital_predistortion_8188e(
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
struct _ADAPTER *p_adapter
#else
struct PHY_DM_STRUCT *p_dm_odm
#endif
)
{
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv;
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
#endif
#endif
struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
#if DISABLE_BB_RF
return;
@ -3099,13 +2686,10 @@ phy_digital_predistortion_8188e(
if (p_rf_calibrate_info->is_dp_done)
return;
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
if (IS_92C_SERIAL(p_hal_data->VersionID))
phy_digital_predistortion(p_adapter, true);
else
#endif
{
else {
/* For 88C 1T1R */
phy_digital_predistortion(p_adapter, false);
}

14
hal/rtl8188e/usb/rtl8188eu_xmit.c
View file

@ -28,11 +28,9 @@ s32 rtl8188eu_init_xmit_priv(_adapter *padapter)
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
#ifdef PLATFORM_LINUX
tasklet_init(&pxmitpriv->xmit_tasklet,
(void(*)(unsigned long))rtl8188eu_xmit_tasklet,
(unsigned long)padapter);
#endif
#ifdef CONFIG_TX_EARLY_MODE
pHalData->bEarlyModeEnable = padapter->registrypriv.early_mode;
#endif
@ -1157,9 +1155,7 @@ s32 rtl8188eu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmit
pxmitpriv->tx_drop++;
} else {
#ifdef PLATFORM_LINUX
tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
#endif
}
return err;
@ -1171,18 +1167,13 @@ s32 rtl8188eu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmit
static void rtl8188eu_hostap_mgnt_xmit_cb(struct urb *urb)
{
#ifdef PLATFORM_LINUX
struct sk_buff *skb = (struct sk_buff *)urb->context;
/* RTW_INFO("%s\n", __FUNCTION__); */
rtw_skb_free(skb);
#endif
}
s32 rtl8188eu_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
{
#ifdef PLATFORM_LINUX
u16 fc;
int rc, len, pipe;
unsigned int bmcst, tid, qsel;
@ -1197,8 +1188,6 @@ s32 rtl8188eu_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
/* RTW_INFO("%s\n", __FUNCTION__); */
skb = pkt;
len = skb->len;
@ -1289,9 +1278,6 @@ _exit:
rtw_skb_free(skb);
#endif
return 0;
}
#endif

446
hal/rtl8188e/usb/usb_halinit.c
View file

@ -29,7 +29,6 @@
#endif
static VOID
_ConfigNormalChipOutEP_8188E(
IN PADAPTER pAdapter,
@ -132,7 +131,6 @@ static u32 _InitPowerOn_8188EU(_adapter *padapter)
/* HW Power on sequence */
u8 bMacPwrCtrlOn = _FALSE;
rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
if (bMacPwrCtrlOn == _TRUE)
return _SUCCESS;
@ -146,7 +144,6 @@ static u32 _InitPowerOn_8188EU(_adapter *padapter)
/* Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */
rtw_write16(padapter, REG_CR, 0x00); /* suggseted by zhouzhou, by page, 20111230 */
/* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
value16 = rtw_read16(padapter, REG_CR);
value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
@ -162,7 +159,6 @@ static u32 _InitPowerOn_8188EU(_adapter *padapter)
}
static void _dbg_dump_macreg(_adapter *padapter)
{
u32 offset = 0;
@ -175,7 +171,6 @@ static void _dbg_dump_macreg(_adapter *padapter)
}
}
static void _InitPABias(_adapter *padapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
@ -185,7 +180,6 @@ static void _InitPABias(_adapter *padapter)
/* efuse_one_byte_read(padapter, 0x1FA, &pa_setting); */
efuse_OneByteRead(padapter, 0x1FA, &pa_setting, _FALSE);
if (!(pa_setting & BIT0)) {
phy_set_rf_reg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
phy_set_rf_reg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
@ -225,7 +219,6 @@ static void _InitBTCoexist(_adapter *padapter)
rtw_write8(padapter, 0x4fd, u1Tmp);
RTW_INFO("BT write 0x%x = 0x%x for non-isolation\n", 0x4fd, u1Tmp);
rtw_write32(padapter, REG_BT_COEX_TABLE + 4, 0xaaaa9aaa);
RTW_INFO("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE + 4, 0xaaaa9aaa);
@ -250,8 +243,6 @@ static void _InitBTCoexist(_adapter *padapter)
}
#endif
/* ---------------------------------------------------------------
*
* MAC init functions
@ -304,7 +295,6 @@ _InitInterrupt(
}
static VOID
_InitQueueReservedPage(
IN PADAPTER Adapter
@ -382,21 +372,9 @@ _InitPageBoundary(
rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E(Adapter) - 1;
#if 0
/* RX Page Boundary */
/* srand(static_cast<unsigned int>(time(NULL)) ); */
if (bSupportRemoteWakeUp) {
Offset = MAX_RX_DMA_BUFFER_SIZE_88E(Adapter) + MAX_TX_REPORT_BUFFER_SIZE - MAX_SUPPORT_WOL_PATTERN_NUM(Adapter) * WKFMCAM_SIZE;
Offset = Offset / 128; /* RX page size = 128 byte */
rxff_bndy = (Offset * 128) - 1;
} else
#endif
rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
}
static VOID
_InitNormalChipRegPriority(
IN PADAPTER Adapter,
@ -460,7 +438,6 @@ _InitNormalChipTwoOutEpPriority(
struct registry_priv *pregistrypriv = &Adapter->registrypriv;
u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
u16 valueHi = 0;
u16 valueLow = 0;
@ -550,11 +527,8 @@ _InitQueuePriority(
break;
}
}
static VOID
_InitHardwareDropIncorrectBulkOut(
IN PADAPTER Adapter
@ -582,7 +556,6 @@ _InitNetworkType(
/* RASSERT(pIoBase->rtw_read8(REG_CR + 2) == 0x2); */
}
static VOID
_InitDriverInfoSize(
IN PADAPTER Adapter,
@ -618,7 +591,6 @@ _InitWMACSetting(
rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF);
rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
/* Accept all data frames */
/* value16 = 0xFFFF; */
/* rtw_write16(Adapter, REG_RXFLTMAP2, value16); */
@ -678,7 +650,6 @@ _InitRateFallback(
}
static VOID
_InitEDCA(
IN PADAPTER Adapter
@ -701,7 +672,6 @@ _InitEDCA(
rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
}
static VOID
_InitBeaconMaxError(
IN PADAPTER Adapter,
@ -711,7 +681,6 @@ _InitBeaconMaxError(
}
#ifdef CONFIG_LED
static void _InitHWLed(PADAPTER Adapter)
{
@ -791,7 +760,6 @@ usb_AggSettingTxUpdate(
#endif
} /* usb_AggSettingTxUpdate */
/*-----------------------------------------------------------------------------
* Function: usb_AggSettingRxUpdate()
*
@ -912,33 +880,6 @@ HalRxAggr8188EUsb(
IN BOOLEAN Value
)
{
#if 0/* USB_RX_AGGREGATION_92C */
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
u1Byte valueDMATimeout;
u1Byte valueDMAPageCount;
u1Byte valueUSBTimeout;
u1Byte valueUSBBlockCount;
/* selection to prevent bad TP. */
if (IS_WIRELESS_MODE_B(Adapter) || IS_WIRELESS_MODE_G(Adapter) || IS_WIRELESS_MODE_A(Adapter) || pMgntInfo->bWiFiConfg) {
/* 2010.04.27 hpfan */
/* Adjust RxAggrTimeout to close to zero disable RxAggr, suggested by designer */
/* Timeout value is calculated by 34 / (2^n) */
valueDMATimeout = 0x0f;
valueDMAPageCount = 0x01;
valueUSBTimeout = 0x0f;
valueUSBBlockCount = 0x01;
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_PGTO, (pu1Byte)&valueDMATimeout);
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_PGTH, (pu1Byte)&valueDMAPageCount);
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTO, (pu1Byte)&valueUSBTimeout);
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTH, (pu1Byte)&valueUSBBlockCount);
} else {
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTO, (pu1Byte)&pMgntInfo->RegRxAggBlockTimeout);
rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTH, (pu1Byte)&pMgntInfo->RegRxAggBlockCount);
}
#endif
}
/*-----------------------------------------------------------------------------
@ -965,73 +906,6 @@ USB_AggModeSwitch(
IN PADAPTER Adapter
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
/* pHalData->UsbRxHighSpeedMode = FALSE; */
/* How to measure the RX speed? We assume that when traffic is more than */
if (pMgntInfo->bRegAggDMEnable == FALSE) {
return; /* Inf not support. */
}
if (pMgntInfo->LinkDetectInfo.bHigherBusyRxTraffic == TRUE &&
pHalData->UsbRxHighSpeedMode == FALSE) {
pHalData->UsbRxHighSpeedMode = TRUE;
} else if (pMgntInfo->LinkDetectInfo.bHigherBusyRxTraffic == FALSE &&
pHalData->UsbRxHighSpeedMode == TRUE) {
pHalData->UsbRxHighSpeedMode = FALSE;
} else
return;
#if USB_RX_AGGREGATION_92C
if (pHalData->UsbRxHighSpeedMode == TRUE) {
/* 2010/12/10 MH The parameter is tested by SD1 engineer and SD3 channel emulator. */
/* USB mode */
#if (RT_PLATFORM == PLATFORM_LINUX)
if (pMgntInfo->LinkDetectInfo.bTxBusyTraffic) {
pHalData->RxAggBlockCount = 16;
pHalData->RxAggBlockTimeout = 7;
} else
#endif
{
pHalData->RxAggBlockCount = 40;
pHalData->RxAggBlockTimeout = 5;
}
/* Mix mode */
pHalData->RxAggPageCount = 72;
pHalData->RxAggPageTimeout = 6;
} else {
/* USB mode */
pHalData->RxAggBlockCount = pMgntInfo->RegRxAggBlockCount;
pHalData->RxAggBlockTimeout = pMgntInfo->RegRxAggBlockTimeout;
/* Mix mode */
pHalData->RxAggPageCount = pMgntInfo->RegRxAggPageCount;
pHalData->RxAggPageTimeout = pMgntInfo->RegRxAggPageTimeout;
}
if (pHalData->RxAggBlockCount > MAX_RX_AGG_BLKCNT)
pHalData->RxAggBlockCount = MAX_RX_AGG_BLKCNT;
#if (OS_WIN_FROM_VISTA(OS_VERSION)) || (RT_PLATFORM == PLATFORM_LINUX) /* do not support WINXP to prevent usbehci.sys BSOD */
if (IS_WIRELESS_MODE_N_24G(Adapter) || IS_WIRELESS_MODE_N_5G(Adapter)) {
/* */
/* 2010/12/24 MH According to V1012 QC IOT test, XP BSOD happen when running chariot test */
/* with the aggregation dynamic change!! We need to disable the function to prevent it is broken */
/* in usbehci.sys. */
/* */
usb_AggSettingRxUpdate_8188E(Adapter);
/* 2010/12/27 MH According to designer's suggstion, we can only modify Timeout value. Otheriwse */
/* there might many HW incorrect behavior, the XP BSOD at usbehci.sys may be relative to the */
/* issue. Base on the newest test, we can not enable block cnt > 30, otherwise XP usbehci.sys may */
/* BSOD. */
}
#endif
#endif
#endif
} /* USB_AggModeSwitch */
static VOID
@ -1039,67 +913,8 @@ _InitOperationMode(
IN PADAPTER Adapter
)
{
#if 0/* gtest */
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
u1Byte regBwOpMode = 0;
u4Byte regRATR = 0, regRRSR = 0;
/* 1 This part need to modified according to the rate set we filtered!! */
/* */
/* Set RRSR, RATR, and REG_BWOPMODE registers */
/* */
switch (Adapter->RegWirelessMode) {
case WIRELESS_MODE_B:
regBwOpMode = BW_OPMODE_20MHZ;
regRATR = RATE_ALL_CCK;
regRRSR = RATE_ALL_CCK;
break;
case WIRELESS_MODE_A:
regBwOpMode = BW_OPMODE_5G | BW_OPMODE_20MHZ;
regRATR = RATE_ALL_OFDM_AG;
regRRSR = RATE_ALL_OFDM_AG;
break;
case WIRELESS_MODE_G:
regBwOpMode = BW_OPMODE_20MHZ;
regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
break;
case WIRELESS_MODE_AUTO:
if (Adapter->bInHctTest) {
regBwOpMode = BW_OPMODE_20MHZ;
regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
} else {
regBwOpMode = BW_OPMODE_20MHZ;
regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
}
break;
case WIRELESS_MODE_N_24G:
/* It support CCK rate by default. */
/* CCK rate will be filtered out only when associated AP does not support it. */
regBwOpMode = BW_OPMODE_20MHZ;
regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
break;
case WIRELESS_MODE_N_5G:
regBwOpMode = BW_OPMODE_5G;
regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
regRRSR = RATE_ALL_OFDM_AG;
break;
default: /* for MacOSX compiler warning. */
break;
}
/* Ziv ???????? */
/* PlatformEFIOWrite4Byte(Adapter, REG_INIRTS_RATE_SEL, regRRSR); */
PlatformEFIOWrite1Byte(Adapter, REG_BWOPMODE, regBwOpMode);
#endif
}
static VOID
_InitBeaconParameters(
IN PADAPTER Adapter
@ -1153,7 +968,6 @@ _InitRFType(
}
static VOID
_BeaconFunctionEnable(
IN PADAPTER Adapter,
@ -1167,7 +981,6 @@ _BeaconFunctionEnable(
rtw_write8(Adapter, REG_RD_CTRL + 1, 0x6F);
}
/* Set CCK and OFDM Block "ON" */
static VOID _BBTurnOnBlock(
IN PADAPTER Adapter
@ -1185,29 +998,6 @@ static VOID _RfPowerSave(
IN PADAPTER Adapter
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
u1Byte eRFPath;
#if (DISABLE_BB_RF)
return;
#endif
if (pMgntInfo->RegRfOff == TRUE) { /* User disable RF via registry. */
MgntActSet_RF_State(Adapter, eRfOff, RF_CHANGE_BY_SW);
/* Those action will be discard in MgntActSet_RF_State because off the same state */
for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)
phy_set_rf_reg(Adapter, eRFPath, 0x4, 0xC00, 0x0);
} else if (pMgntInfo->RfOffReason > RF_CHANGE_BY_PS) { /* H/W or S/W RF OFF before sleep. */
MgntActSet_RF_State(Adapter, eRfOff, pMgntInfo->RfOffReason);
} else {
pHalData->eRFPowerState = eRfOn;
pMgntInfo->RfOffReason = 0;
if (Adapter->bInSetPower || Adapter->bResetInProgress)
PlatformUsbEnableInPipes(Adapter);
}
#endif
}
enum {
@ -1240,88 +1030,7 @@ HalDetectSelectiveSuspendMode(
IN PADAPTER Adapter
)
{
#if 0
u8 tmpvalue;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);
/* If support HW radio detect, we need to enable WOL ability, otherwise, we */
/* can not use FW to notify host the power state switch. */
EFUSE_ShadowRead(Adapter, 1, EEPROM_USB_OPTIONAL1, (u32 *)&tmpvalue);
RTW_INFO("HalDetectSelectiveSuspendMode(): SS ");
if (tmpvalue & BIT1)
RTW_INFO("Enable\n");
else {
RTW_INFO("Disable\n");
pdvobjpriv->RegUsbSS = _FALSE;
}
/* 2010/09/01 MH According to Dongle Selective Suspend INF. We can switch SS mode. */
if (pdvobjpriv->RegUsbSS && !SUPPORT_HW_RADIO_DETECT(pHalData)) {
/* PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); */
/* if (!pMgntInfo->bRegDongleSS) */
/* { */
pdvobjpriv->RegUsbSS = _FALSE;
/* } */
}
#endif
} /* HalDetectSelectiveSuspendMode */
#if 0
/*-----------------------------------------------------------------------------
* Function: HwSuspendModeEnable92Cu()
*
* Overview: HW suspend mode switch.
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 08/23/2010 MHC HW suspend mode switch test..
*---------------------------------------------------------------------------*/
static VOID
HwSuspendModeEnable_88eu(
IN PADAPTER pAdapter,
IN u8 Type
)
{
/* PRT_USB_DEVICE pDevice = GET_RT_USB_DEVICE(pAdapter); */
u16 reg = rtw_read16(pAdapter, REG_GPIO_MUXCFG);
/* if (!pDevice->RegUsbSS) */
{
return;
}
/* */
/* 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW */
/* to enter suspend mode automatically. Otherwise, it will shut down major power */
/* domain and 8051 will stop. When we try to enter selective suspend mode, we */
/* need to prevent HW to enter D2 mode aumotmatically. Another way, Host will */
/* issue a S10 signal to power domain. Then it will cleat SIC setting(from Yngli). */
/* We need to enable HW suspend mode when enter S3/S4 or disable. We need */
/* to disable HW suspend mode for IPS/radio_off. */
/* */
if (Type == _FALSE) {
reg |= BIT14;
rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
reg |= BIT12;
rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
} else {
reg &= (~BIT12);
rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
reg &= (~BIT14);
rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
}
} /* HwSuspendModeEnable92Cu */
#endif
rt_rf_power_state RfOnOffDetect(IN PADAPTER pAdapter)
{
@ -1362,7 +1071,6 @@ u32 rtl8188eu_hal_init(PADAPTER Adapter)
u32 init_start_time = rtw_get_current_time();
#ifdef DBG_HAL_INIT_PROFILING
enum HAL_INIT_STAGES {
@ -1435,9 +1143,6 @@ u32 rtl8188eu_hal_init(PADAPTER Adapter)
#define HAL_INIT_PROFILE_TAG(stage) do {} while (0)
#endif /* DBG_HAL_INIT_PROFILING */
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
if (pwrctrlpriv->bkeepfwalive) {
@ -1460,7 +1165,6 @@ u32 rtl8188eu_hal_init(PADAPTER Adapter)
goto exit;
}
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
status = rtw_hal_power_on(Adapter);
if (status == _FAIL) {
@ -1499,8 +1203,6 @@ u32 rtl8188eu_hal_init(PADAPTER Adapter)
_InitTxBufferBoundary(Adapter, 0);
#endif
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
if (Adapter->registrypriv.mp_mode == 0) {
status = rtl8188e_FirmwareDownload(Adapter, _FALSE);
@ -1540,7 +1242,6 @@ u32 rtl8188eu_hal_init(PADAPTER Adapter)
}
#endif
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
#if (HAL_RF_ENABLE == 1)
status = PHY_RFConfig8188E(Adapter);
@ -1594,7 +1295,6 @@ u32 rtl8188eu_hal_init(PADAPTER Adapter)
_InitHardwareDropIncorrectBulkOut(Adapter);
if (pHalData->bRDGEnable)
_InitRDGSetting(Adapter);
@ -1614,10 +1314,6 @@ u32 rtl8188eu_hal_init(PADAPTER Adapter)
/* disable tx rpt */
rtw_write8(Adapter, REG_TX_RPT_CTRL + 1, 0); /* FOR sta mode ,0: bc/mc ,1:AP */
}
#if 0
if (pHTInfo->bRDGEnable)
_InitRDGSetting_8188E(Adapter);
#endif
#ifdef CONFIG_TX_EARLY_MODE
if (pHalData->bEarlyModeEnable) {
@ -1660,12 +1356,10 @@ u32 rtl8188eu_hal_init(PADAPTER Adapter)
#endif /* CONFIG_TX_MCAST2UNI */
#endif /* CONFIG_CONCURRENT_MODE || CONFIG_TX_MCAST2UNI */
#ifdef CONFIG_LED
_InitHWLed(Adapter);
#endif /* CONFIG_LED */
/* */
/* Joseph Note: Keep RfRegChnlVal for later use. */
/* */
@ -1737,7 +1431,6 @@ u32 rtl8188eu_hal_init(PADAPTER Adapter)
/* Suggested by SD1 pisa. Added by tynli. 2011.10.21. */
rtw_write8(Adapter, REG_EARLY_MODE_CONTROL + 3, 0x01); /* Pretx_en, for WEP/TKIP SEC */
/* enable tx DMA to drop the redundate data of packet */
rtw_write16(Adapter, REG_TXDMA_OFFSET_CHK, (rtw_read16(Adapter, REG_TXDMA_OFFSET_CHK) | DROP_DATA_EN));
@ -1755,7 +1448,6 @@ u32 rtl8188eu_hal_init(PADAPTER Adapter)
odm_txpowertracking_check(&pHalData->odmpriv);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
phy_lc_calibrate_8188e(&pHalData->odmpriv);
}
@ -1788,8 +1480,6 @@ exit:
}
#endif
return status;
}
@ -1805,7 +1495,6 @@ void _ps_close_RF(_adapter *padapter)
/* phy_SsPwrSwitch92CU(padapter, rf_off, 1); */
}
VOID
hal_poweroff_8188eu(
IN PADAPTER Adapter
@ -1821,7 +1510,6 @@ hal_poweroff_8188eu(
if (bMacPwrCtrlOn == _FALSE)
return ;
/* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */
val8 = rtw_read8(Adapter, REG_TX_RPT_CTRL);
rtw_write8(Adapter, REG_TX_RPT_CTRL, val8 & (~BIT1));
@ -1832,7 +1520,6 @@ hal_poweroff_8188eu(
/* Run LPS WL RFOFF flow */
HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_LPS_ENTER_FLOW);
/* 2. 0x1F[7:0] = 0 */ /* turn off RF */
/* rtw_write8(Adapter, REG_RF_CTRL, 0x00); */
@ -1868,11 +1555,6 @@ hal_poweroff_8188eu(
val8 = rtw_read8(Adapter, REG_RSV_CTRL + 1);
rtw_write8(Adapter, REG_RSV_CTRL + 1, val8 | BIT3);
#if 0
/* 7. RSV_CTRL 0x1C[7:0] = 0x0E */ /* lock ISO/CLK/Power control register */
rtw_write8(Adapter, REG_RSV_CTRL, 0x0e);
#endif
#if 1
/* YJ,test add, 111207. For Power Consumption. */
val8 = rtw_read8(Adapter, GPIO_IN);
rtw_write8(Adapter, GPIO_OUT, val8);
@ -1884,7 +1566,6 @@ hal_poweroff_8188eu(
val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL + 1);
rtw_write8(Adapter, REG_GPIO_IO_SEL + 1, val8 | 0x0F); /* Reg0x43 */
rtw_write32(Adapter, REG_BB_PAD_CTRL, 0x00080808);/* set LNA ,TRSW,EX_PA Pin to output mode */
#endif
Adapter->bFWReady = _FALSE;
@ -1932,7 +1613,6 @@ u32 rtl8188eu_hal_deinit(PADAPTER Adapter)
return _SUCCESS;
}
unsigned int rtl8188eu_inirp_init(PADAPTER Adapter)
{
u8 i;
@ -1947,12 +1627,10 @@ unsigned int rtl8188eu_inirp_init(PADAPTER Adapter)
u32(*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
#endif
_read_port = pintfhdl->io_ops._read_port;
status = _SUCCESS;
precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR;
/* issue Rx irp to receive data */
@ -1981,8 +1659,6 @@ unsigned int rtl8188eu_inirp_init(PADAPTER Adapter)
exit:
return status;
}
@ -1992,19 +1668,15 @@ unsigned int rtl8188eu_inirp_deinit(PADAPTER Adapter)
rtw_read_port_cancel(Adapter);
return _SUCCESS;
}
/* -------------------------------------------------------------------------
*
* EEPROM Power index mapping
*
* ------------------------------------------------------------------------- */
/* -------------------------------------------------------------------
*
* EEPROM/EFUSE Content Parsing
@ -2049,33 +1721,6 @@ hal_InitPGData(
IN OUT u8 *PROMContent
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
u32 i;
u16 value16;
if (_FALSE == pHalData->bautoload_fail_flag) {
/* autoload OK. */
if (_TRUE == pHalData->EepromOrEfuse) {
/* Read all Content from EEPROM or EFUSE. */
for (i = 0; i < HWSET_MAX_SIZE_88E; i += 2) {
/* value16 = EF2Byte(ReadEEprom(pAdapter, (u2Byte) (i>>1))); */
/* *((u16 *)(&PROMContent[i])) = value16; */
}
} else {
/* Read EFUSE real map to shadow. */
EFUSE_ShadowMapUpdate(pAdapter, EFUSE_WIFI, _FALSE);
_rtw_memcpy((void *)PROMContent, (void *)pHalData->efuse_eeprom_data, HWSET_MAX_SIZE_88E);
}
} else {
/* autoload fail */
pHalData->bautoload_fail_flag = _TRUE;
/* update to default value 0xFF */
if (_FALSE == pHalData->EepromOrEfuse)
EFUSE_ShadowMapUpdate(pAdapter, EFUSE_WIFI, _FALSE);
}
#endif
}
static void
Hal_EfuseParsePIDVID_8188EU(
@ -2115,46 +1760,6 @@ Hal_CustomizeByCustomerID_8188EU(
IN PADAPTER padapter
)
{
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
/* For customized behavior. */
if ((pHalData->EEPROMVID == 0x103C) && (pHalData->EEPROMVID == 0x1629)) /* HP Lite-On for RTL8188CUS Slim Combo. */
pHalData->CustomerID = RT_CID_819x_HP;
/* Decide CustomerID according to VID/DID or EEPROM */
switch (pHalData->EEPROMCustomerID) {
case EEPROM_CID_DEFAULT:
if ((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3308))
pHalData->CustomerID = RT_CID_DLINK;
else if ((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3309))
pHalData->CustomerID = RT_CID_DLINK;
else if ((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x330a))
pHalData->CustomerID = RT_CID_DLINK;
break;
case EEPROM_CID_WHQL:
padapter->bInHctTest = TRUE;
pMgntInfo->bSupportTurboMode = FALSE;
pMgntInfo->bAutoTurboBy8186 = FALSE;
pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
pMgntInfo->PowerSaveControl.bLeisurePsModeBackup = FALSE;
pMgntInfo->keepAliveLevel = 0;
padapter->bUnloadDriverwhenS3S4 = FALSE;
break;
default:
pHalData->CustomerID = RT_CID_DEFAULT;
break;
}
hal_CustomizedBehavior_8723U(padapter);
#endif
}
static VOID
@ -2162,7 +1767,6 @@ readAdapterInfo_8188EU(
IN PADAPTER padapter
)
{
#if 1
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
/* parse the eeprom/efuse content */
@ -2196,21 +1800,6 @@ readAdapterInfo_8188EU(
Hal_CustomizeByCustomerID_8188EU(padapter);
_ReadLEDSetting(padapter, pHalData->efuse_eeprom_data, pHalData->bautoload_fail_flag);
#else
#ifdef CONFIG_INTEL_PROXIM
/* for intel proximity */
if (pHalData->rf_type == RF_1T1R)
Adapter->proximity.proxim_support = _TRUE;
else if (pHalData->rf_type == RF_2T2R) {
if ((pHalData->EEPROMPID == 0x8186) &&
(pHalData->EEPROMVID == 0x0bda))
Adapter->proximity.proxim_support = _TRUE;
} else
Adapter->proximity.proxim_support = _FALSE;
#endif /* CONFIG_INTEL_PROXIM */
#endif
}
static void _ReadPROMContent(
@ -2225,7 +1814,6 @@ static void _ReadPROMContent(
pHalData->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE;
pHalData->bautoload_fail_flag = (eeValue & EEPROM_EN) ? _FALSE : _TRUE;
RTW_INFO("Boot from %s, Autoload %s !\n", (pHalData->EepromOrEfuse ? "EEPROM" : "EFUSE"),
(pHalData->bautoload_fail_flag ? "Fail" : "OK"));
@ -2235,8 +1823,6 @@ static void _ReadPROMContent(
readAdapterInfo_8188EU(Adapter);
}
static VOID
_ReadRFType(
IN PADAPTER Adapter
@ -2293,7 +1879,6 @@ void SetHwReg8188EU(PADAPTER Adapter, u8 variable, u8 *val)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
switch (variable) {
case HW_VAR_RXDMA_AGG_PG_TH:
@ -2377,9 +1962,6 @@ GetHalDefVar8188EUsb(
return bResult;
}
/*
* Description:
* Change default setting of specified variable.
@ -2402,33 +1984,7 @@ SetHalDefVar8188EUsb(
return bResult;
}
#if 0
u32 _update_92cu_basic_rate(_adapter *padapter, unsigned int mask)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
#ifdef CONFIG_BT_COEXIST
struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist);
#endif
unsigned int BrateCfg = 0;
#ifdef CONFIG_BT_COEXIST
if ((pbtpriv->BT_Coexist) && (pbtpriv->BT_CoexistType == BT_CSR_BC4))
BrateCfg = mask & 0x151;
else
#endif
{
/* if(pHalData->version_id != VERSION_TEST_CHIP_88C) */
BrateCfg = mask & 0x15F;
/* else //for 88CU 46PING setting, Disable CCK 2M, 5.5M, Others must tuning */
/* BrateCfg = mask & 0x159; */
}
BrateCfg |= 0x01; /* default enable 1M ACK rate */
return BrateCfg;
}
#endif
void _update_response_rate(_adapter *padapter, unsigned int mask)
{
u8 RateIndex = 0;
@ -2556,7 +2112,6 @@ void rtl8188eu_set_hal_ops(_adapter *padapter)
{
struct hal_ops *pHalFunc = &padapter->hal_func;
pHalFunc->hal_power_on = _InitPowerOn_8188EU;
pHalFunc->hal_power_off = hal_poweroff_8188eu;
@ -2593,7 +2148,6 @@ void rtl8188eu_set_hal_ops(_adapter *padapter)
pHalFunc->mgnt_xmit = &rtl8188eu_mgnt_xmit;
pHalFunc->hal_xmitframe_enqueue = &rtl8188eu_hal_xmitframe_enqueue;
#ifdef CONFIG_HOSTAPD_MLME
pHalFunc->hostap_mgnt_xmit_entry = &rtl8188eu_hostap_mgnt_xmit_entry;
#endif