mirror of
https://github.com/lwfinger/rtl8188eu.git
synced 2024-11-22 04:23:39 +00:00
rtl8188eu: Remove include files not used
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
parent
eac0a699d8
commit
058fa5a916
44 changed files with 35 additions and 14622 deletions
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@ -1,394 +0,0 @@
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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/*****************************************************************************
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* Module: __INC_HAL8192CPHYCFG_H
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*
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*
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* Note:
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*
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*
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* Export: Constants, macro, functions(API), global variables(None).
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*
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* Abbrev:
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*
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* History:
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* Data Who Remark
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* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
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* 2. Reorganize code architecture.
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*
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*****************************************************************************/
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/* Check to see if the file has been included already. */
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#ifndef __INC_HAL8192CPHYCFG_H
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#define __INC_HAL8192CPHYCFG_H
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/*--------------------------Define Parameters-------------------------------*/
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#define LOOP_LIMIT 5
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#define MAX_STALL_TIME 50 //us
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#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
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#define MAX_TXPWR_IDX_NMODE_92S 63
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#define Reset_Cnt_Limit 3
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#ifdef CONFIG_PCI_HCI
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#define MAX_AGGR_NUM 0x0A0A
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#else
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#define MAX_AGGR_NUM 0x0909
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#endif
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#ifdef CONFIG_PCI_HCI
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#define SET_RTL8192SE_RF_SLEEP(_pAdapter) \
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{ \
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u1Byte u1bTmp; \
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u1bTmp = PlatformEFIORead1Byte(_pAdapter, REG_LDOV12D_CTRL); \
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u1bTmp |= BIT0; \
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PlatformEFIOWrite1Byte(_pAdapter, REG_LDOV12D_CTRL, u1bTmp); \
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PlatformEFIOWrite1Byte(_pAdapter, REG_SPS_OCP_CFG, 0x0); \
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PlatformEFIOWrite1Byte(_pAdapter, TXPAUSE, 0xFF); \
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PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \
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delay_us(100); \
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PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \
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PlatformEFIOWrite1Byte(_pAdapter, PHY_CCA, 0x0); \
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delay_us(10); \
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PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x37FC); \
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delay_us(10); \
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PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \
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delay_us(10); \
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PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \
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}
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#endif
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/*--------------------------Define Parameters-------------------------------*/
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/*------------------------------Define structure----------------------------*/
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typedef enum _SwChnlCmdID{
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CmdID_End,
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CmdID_SetTxPowerLevel,
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CmdID_BBRegWrite10,
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CmdID_WritePortUlong,
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CmdID_WritePortUshort,
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CmdID_WritePortUchar,
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CmdID_RF_WriteReg,
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}SwChnlCmdID;
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/* 1. Switch channel related */
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typedef struct _SwChnlCmd{
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SwChnlCmdID CmdID;
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u32 Para1;
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u32 Para2;
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u32 msDelay;
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}SwChnlCmd;
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typedef enum _HW90_BLOCK{
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HW90_BLOCK_MAC = 0,
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HW90_BLOCK_PHY0 = 1,
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HW90_BLOCK_PHY1 = 2,
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HW90_BLOCK_RF = 3,
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HW90_BLOCK_MAXIMUM = 4, // Never use this
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}HW90_BLOCK_E, *PHW90_BLOCK_E;
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typedef enum _RF_RADIO_PATH{
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RF_PATH_A = 0, //Radio Path A
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RF_PATH_B = 1, //Radio Path B
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RF_PATH_C = 2, //Radio Path C
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RF_PATH_D = 3, //Radio Path D
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//RF_PATH_MAX //Max RF number 90 support
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}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E;
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#define RF_PATH_MAX 2
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#define CHANNEL_MAX_NUMBER 14 // 14 is the max channel number
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#define CHANNEL_GROUP_MAX 3 // ch1~3, ch4~9, ch10~14 total three groups
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typedef enum _WIRELESS_MODE {
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WIRELESS_MODE_UNKNOWN = 0x00,
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WIRELESS_MODE_A = BIT2,
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WIRELESS_MODE_B = BIT0,
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WIRELESS_MODE_G = BIT1,
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WIRELESS_MODE_AUTO = BIT5,
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WIRELESS_MODE_N_24G = BIT3,
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WIRELESS_MODE_N_5G = BIT4,
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WIRELESS_MODE_AC = BIT6
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} WIRELESS_MODE;
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typedef enum _BaseBand_Config_Type{
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BaseBand_Config_PHY_REG = 0, //Radio Path A
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BaseBand_Config_AGC_TAB = 1, //Radio Path B
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}BaseBand_Config_Type, *PBaseBand_Config_Type;
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typedef enum _PHY_Rate_Tx_Power_Offset_Area{
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RA_OFFSET_LEGACY_OFDM1,
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RA_OFFSET_LEGACY_OFDM2,
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RA_OFFSET_HT_OFDM1,
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RA_OFFSET_HT_OFDM2,
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RA_OFFSET_HT_OFDM3,
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RA_OFFSET_HT_OFDM4,
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RA_OFFSET_HT_CCK,
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}RA_OFFSET_AREA,*PRA_OFFSET_AREA;
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/* BB/RF related */
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typedef enum _RF_TYPE_8190P{
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RF_TYPE_MIN, // 0
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RF_8225=1, // 1 11b/g RF for verification only
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RF_8256=2, // 2 11b/g/n
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RF_8258=3, // 3 11a/b/g/n RF
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RF_6052=4, // 4 11b/g/n RF
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//RF_6052=5, // 4 11b/g/n RF
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// TODO: We sholud remove this psudo PHY RF after we get new RF.
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RF_PSEUDO_11N=5, // 5, It is a temporality RF.
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}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
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typedef struct _BB_REGISTER_DEFINITION{
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u32 rfintfs; // set software control:
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// 0x870~0x877[8 bytes]
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u32 rfintfi; // readback data:
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// 0x8e0~0x8e7[8 bytes]
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u32 rfintfo; // output data:
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// 0x860~0x86f [16 bytes]
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u32 rfintfe; // output enable:
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// 0x860~0x86f [16 bytes]
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u32 rf3wireOffset; // LSSI data:
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// 0x840~0x84f [16 bytes]
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u32 rfLSSI_Select; // BB Band Select:
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// 0x878~0x87f [8 bytes]
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u32 rfTxGainStage; // Tx gain stage:
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// 0x80c~0x80f [4 bytes]
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u32 rfHSSIPara1; // wire parameter control1 :
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// 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
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u32 rfHSSIPara2; // wire parameter control2 :
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// 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
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u32 rfSwitchControl; //Tx Rx antenna control :
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// 0x858~0x85f [16 bytes]
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u32 rfAGCControl1; //AGC parameter control1 :
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// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
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u32 rfAGCControl2; //AGC parameter control2 :
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// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
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u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
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// 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
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u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
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// 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
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u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
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// 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
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u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
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// 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
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u32 rfLSSIReadBack; //LSSI RF readback data SI mode
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// 0x8a0~0x8af [16 bytes]
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u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
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}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
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typedef struct _R_ANTENNA_SELECT_OFDM{
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u32 r_tx_antenna:4;
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u32 r_ant_l:4;
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u32 r_ant_non_ht:4;
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u32 r_ant_ht1:4;
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u32 r_ant_ht2:4;
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u32 r_ant_ht_s1:4;
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u32 r_ant_non_ht_s1:4;
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u32 OFDM_TXSC:2;
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u32 Reserved:2;
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}R_ANTENNA_SELECT_OFDM;
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typedef struct _R_ANTENNA_SELECT_CCK{
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u8 r_cckrx_enable_2:2;
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u8 r_cckrx_enable:2;
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u8 r_ccktx_enable:4;
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}R_ANTENNA_SELECT_CCK;
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/*------------------------------Define structure----------------------------*/
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/*------------------------Export global variable----------------------------*/
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/*------------------------Export global variable----------------------------*/
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/*------------------------Export Marco Definition---------------------------*/
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/*------------------------Export Marco Definition---------------------------*/
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/*--------------------------Exported Function prototype---------------------*/
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//
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// BB and RF register read/write
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//
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u32 rtl8192c_PHY_QueryBBReg( PADAPTER Adapter,
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u32 RegAddr,
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u32 BitMask );
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void rtl8192c_PHY_SetBBReg( PADAPTER Adapter,
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u32 RegAddr,
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u32 BitMask,
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u32 Data );
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u32 rtl8192c_PHY_QueryRFReg( PADAPTER Adapter,
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RF_RADIO_PATH_E eRFPath,
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u32 RegAddr,
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u32 BitMask );
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void rtl8192c_PHY_SetRFReg( PADAPTER Adapter,
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RF_RADIO_PATH_E eRFPath,
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u32 RegAddr,
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u32 BitMask,
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u32 Data );
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//
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// Initialization related function
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//
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/* MAC/BB/RF HAL config */
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int PHY_MACConfig8192C( PADAPTER Adapter );
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int PHY_BBConfig8192C( PADAPTER Adapter );
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int PHY_RFConfig8192C( PADAPTER Adapter );
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/* RF config */
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int rtl8192c_PHY_ConfigRFWithParaFile( PADAPTER Adapter,
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u8* pFileName,
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RF_RADIO_PATH_E eRFPath);
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int rtl8192c_PHY_ConfigRFWithHeaderFile( PADAPTER Adapter,
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RF_RADIO_PATH_E eRFPath);
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/* BB/RF readback check for making sure init OK */
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int rtl8192c_PHY_CheckBBAndRFOK( PADAPTER Adapter,
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HW90_BLOCK_E CheckBlock,
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RF_RADIO_PATH_E eRFPath );
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/* Read initi reg value for tx power setting. */
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void rtl8192c_PHY_GetHWRegOriginalValue( PADAPTER Adapter );
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//
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// RF Power setting
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//
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//extern bool PHY_SetRFPowerState( PADAPTER Adapter,
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// RT_RF_POWER_STATE eRFPowerState);
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//
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// BB TX Power R/W
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//
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void PHY_GetTxPowerLevel8192C( PADAPTER Adapter,
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OUT u32* powerlevel );
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void PHY_SetTxPowerLevel8192C( PADAPTER Adapter,
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u8 channel );
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bool PHY_UpdateTxPowerDbm8192C( PADAPTER Adapter,
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int powerInDbm );
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//
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void
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PHY_ScanOperationBackup8192C( PADAPTER Adapter,
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u8 Operation );
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//
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// Switch bandwidth for 8192S
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//
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//extern void PHY_SetBWModeCallback8192C( PRT_TIMER pTimer );
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void PHY_SetBWMode8192C( PADAPTER pAdapter,
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HT_CHANNEL_WIDTH ChnlWidth,
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unsigned char Offset );
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//
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// Set FW CMD IO for 8192S.
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//
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//extern bool HalSetIO8192C( PADAPTER Adapter,
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// IO_TYPE IOType);
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//
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// Set A2 entry to fw for 8192S
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//
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extern void FillA2Entry8192C( PADAPTER Adapter,
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u8 index,
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u8* val);
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//
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// channel switch related funciton
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//
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//extern void PHY_SwChnlCallback8192C( PRT_TIMER pTimer );
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void PHY_SwChnl8192C( PADAPTER pAdapter,
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u8 channel );
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// Call after initialization
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void PHY_SwChnlPhy8192C( PADAPTER pAdapter,
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u8 channel );
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void ChkFwCmdIoDone( PADAPTER Adapter);
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//
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// BB/MAC/RF other monitor API
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//
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void PHY_SetMonitorMode8192C( PADAPTER pAdapter,
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bool bEnableMonitorMode );
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bool PHY_CheckIsLegalRfPath8192C( PADAPTER pAdapter,
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u32 eRFPath );
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void rtl8192c_PHY_SetRFPathSwitch( PADAPTER pAdapter, bool bMain);
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//
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// Modify the value of the hw register when beacon interval be changed.
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//
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void
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rtl8192c_PHY_SetBeaconHwReg( PADAPTER Adapter,
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u16 BeaconInterval );
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extern void
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PHY_SwitchEphyParameter(
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PADAPTER Adapter
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);
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extern void
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PHY_EnableHostClkReq(
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PADAPTER Adapter
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);
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bool
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SetAntennaConfig92C(
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PADAPTER Adapter,
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u8 DefaultAnt
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);
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#ifdef RTL8192C_RECONFIG_TO_1T1R
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extern void PHY_Reconfig_To_1T1R(_adapter *padapter);
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#endif
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/*--------------------------Exported Function prototype---------------------*/
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#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtl8192c_PHY_QueryBBReg((Adapter), (RegAddr), (BitMask))
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#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtl8192c_PHY_SetBBReg((Adapter), (RegAddr), (BitMask), (Data))
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#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtl8192c_PHY_QueryRFReg((Adapter), (eRFPath), (RegAddr), (BitMask))
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#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtl8192c_PHY_SetRFReg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
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#define PHY_SetMacReg PHY_SetBBReg
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#endif // __INC_HAL8192CPHYCFG_H
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File diff suppressed because it is too large
Load diff
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@ -1,485 +0,0 @@
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/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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||||
*
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*
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******************************************************************************/
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/*****************************************************************************
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||||
*
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||||
* Module: __INC_HAL8192DPHYCFG_H
|
||||
*
|
||||
*
|
||||
* Note:
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||||
*
|
||||
*
|
||||
* Export: Constants, macro, functions(API), global variables(None).
|
||||
*
|
||||
* Abbrev:
|
||||
*
|
||||
* History:
|
||||
* Data Who Remark
|
||||
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
|
||||
* 2. Reorganize code architecture.
|
||||
*
|
||||
*****************************************************************************/
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||||
/* Check to see if the file has been included already. */
|
||||
#ifndef __INC_HAL8192DPHYCFG_H
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||||
#define __INC_HAL8192DPHYCFG_H
|
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|
||||
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/*--------------------------Define Parameters-------------------------------*/
|
||||
#define LOOP_LIMIT 5
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||||
#define MAX_STALL_TIME 50 //us
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||||
#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
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#define MAX_TXPWR_IDX_NMODE_92S 63
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#define Reset_Cnt_Limit 3
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||||
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||||
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#ifdef CONFIG_PCI_HCI
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||||
#define SET_RTL8192SE_RF_SLEEP(_pAdapter) \
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||||
{ \
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||||
u1Byte u1bTmp; \
|
||||
u1bTmp = PlatformEFIORead1Byte(_pAdapter, REG_LDOV12D_CTRL); \
|
||||
u1bTmp |= BIT0; \
|
||||
PlatformEFIOWrite1Byte(_pAdapter, REG_LDOV12D_CTRL, u1bTmp); \
|
||||
PlatformEFIOWrite1Byte(_pAdapter, REG_SPS_OCP_CFG, 0x0); \
|
||||
PlatformEFIOWrite1Byte(_pAdapter, TXPAUSE, 0xFF); \
|
||||
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \
|
||||
delay_us(100); \
|
||||
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \
|
||||
PlatformEFIOWrite1Byte(_pAdapter, PHY_CCA, 0x0); \
|
||||
delay_us(10); \
|
||||
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x37FC); \
|
||||
delay_us(10); \
|
||||
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \
|
||||
delay_us(10); \
|
||||
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
|
||||
|
||||
/*------------------------------Define structure----------------------------*/
|
||||
typedef enum _SwChnlCmdID{
|
||||
CmdID_End,
|
||||
CmdID_SetTxPowerLevel,
|
||||
CmdID_BBRegWrite10,
|
||||
CmdID_WritePortUlong,
|
||||
CmdID_WritePortUshort,
|
||||
CmdID_WritePortUchar,
|
||||
CmdID_RF_WriteReg,
|
||||
}SwChnlCmdID;
|
||||
|
||||
|
||||
/* 1. Switch channel related */
|
||||
typedef struct _SwChnlCmd{
|
||||
SwChnlCmdID CmdID;
|
||||
u32 Para1;
|
||||
u32 Para2;
|
||||
u32 msDelay;
|
||||
}SwChnlCmd;
|
||||
|
||||
typedef enum _HW90_BLOCK{
|
||||
HW90_BLOCK_MAC = 0,
|
||||
HW90_BLOCK_PHY0 = 1,
|
||||
HW90_BLOCK_PHY1 = 2,
|
||||
HW90_BLOCK_RF = 3,
|
||||
HW90_BLOCK_MAXIMUM = 4, // Never use this
|
||||
}HW90_BLOCK_E, *PHW90_BLOCK_E;
|
||||
|
||||
//vivi added this for read parameter from header, 20100908
|
||||
typedef enum _RF_CONTENT{
|
||||
radioa_txt = 0x1000,
|
||||
radiob_txt = 0x1001,
|
||||
radioc_txt = 0x1002,
|
||||
radiod_txt = 0x1003
|
||||
} RF_CONTENT;
|
||||
|
||||
typedef enum _RF_RADIO_PATH{
|
||||
RF_PATH_A = 0, //Radio Path A
|
||||
RF_PATH_B = 1, //Radio Path B
|
||||
RF_PATH_C = 2, //Radio Path C
|
||||
RF_PATH_D = 3, //Radio Path D
|
||||
//RF_PATH_MAX //Max RF number 90 support
|
||||
}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E;
|
||||
|
||||
#define RF_PATH_MAX 2
|
||||
|
||||
|
||||
typedef enum _WIRELESS_MODE {
|
||||
WIRELESS_MODE_UNKNOWN = 0x00,
|
||||
WIRELESS_MODE_A = 0x01,
|
||||
WIRELESS_MODE_B = 0x02,
|
||||
WIRELESS_MODE_G = 0x04,
|
||||
WIRELESS_MODE_AUTO = 0x08,
|
||||
WIRELESS_MODE_N_24G = 0x10,
|
||||
WIRELESS_MODE_N_5G = 0x20
|
||||
} WIRELESS_MODE;
|
||||
|
||||
|
||||
#if (TX_POWER_FOR_5G_BAND == 1)
|
||||
#define CHANNEL_MAX_NUMBER 14+24+21 // 14 is the max channel number
|
||||
#define CHANNEL_GROUP_MAX 3+9 // ch1~3, ch4~9, ch10~14 total three groups
|
||||
#define MAX_PG_GROUP 13
|
||||
#else
|
||||
#define CHANNEL_MAX_NUMBER 14 // 14 is the max channel number
|
||||
#define CHANNEL_GROUP_MAX 3 // ch1~3, ch4~9, ch10~14 total three groups
|
||||
#define MAX_PG_GROUP 7
|
||||
#endif
|
||||
#define CHANNEL_GROUP_MAX_2G 3
|
||||
#define CHANNEL_GROUP_IDX_5GL 3
|
||||
#define CHANNEL_GROUP_IDX_5GM 6
|
||||
#define CHANNEL_GROUP_IDX_5GH 9
|
||||
#define CHANNEL_GROUP_MAX_5G 9
|
||||
#define CHANNEL_MAX_NUMBER_2G 14
|
||||
|
||||
#if (RTL8192D_DUAL_MAC_MODE_SWITCH == 1)
|
||||
typedef enum _BaseBand_Config_Type{
|
||||
BaseBand_Config_PHY_REG = 0,
|
||||
BaseBand_Config_AGC_TAB = 1,
|
||||
BaseBand_Config_AGC_TAB_2G = 2,
|
||||
BaseBand_Config_AGC_TAB_5G = 3,
|
||||
}BaseBand_Config_Type, *PBaseBand_Config_Type;
|
||||
#else
|
||||
typedef enum _BaseBand_Config_Type{
|
||||
BaseBand_Config_PHY_REG = 0, //Radio Path A
|
||||
BaseBand_Config_AGC_TAB = 1, //Radio Path B
|
||||
}BaseBand_Config_Type, *PBaseBand_Config_Type;
|
||||
#endif
|
||||
|
||||
|
||||
typedef enum _MACPHY_MODE_8192D{
|
||||
SINGLEMAC_SINGLEPHY, //SMSP
|
||||
DUALMAC_DUALPHY, //DMDP
|
||||
DUALMAC_SINGLEPHY, //DMSP
|
||||
}MACPHY_MODE_8192D,*PMACPHY_MODE_8192D;
|
||||
|
||||
typedef enum _MACPHY_MODE_CHANGE_ACTION{
|
||||
DMDP2DMSP = 0,
|
||||
DMSP2DMDP = 1,
|
||||
DMDP2SMSP = 2,
|
||||
SMSP2DMDP = 3,
|
||||
DMSP2SMSP = 4,
|
||||
SMSP2DMSP = 5,
|
||||
MAXACTION
|
||||
}MACPHY_MODE_CHANGE_ACTION,*PMACPHY_MODE_CHANGE_ACTION;
|
||||
|
||||
typedef enum _BAND_TYPE{
|
||||
BAND_ON_2_4G = 1,
|
||||
BAND_ON_5G = 2,
|
||||
BAND_ON_BOTH,
|
||||
BANDMAX
|
||||
}BAND_TYPE,*PBAND_TYPE;
|
||||
|
||||
typedef enum _PHY_Rate_Tx_Power_Offset_Area{
|
||||
RA_OFFSET_LEGACY_OFDM1,
|
||||
RA_OFFSET_LEGACY_OFDM2,
|
||||
RA_OFFSET_HT_OFDM1,
|
||||
RA_OFFSET_HT_OFDM2,
|
||||
RA_OFFSET_HT_OFDM3,
|
||||
RA_OFFSET_HT_OFDM4,
|
||||
RA_OFFSET_HT_CCK,
|
||||
}RA_OFFSET_AREA,*PRA_OFFSET_AREA;
|
||||
|
||||
|
||||
/* BB/RF related */
|
||||
typedef enum _RF_TYPE_8190P{
|
||||
RF_TYPE_MIN, // 0
|
||||
RF_8225=1, // 1 11b/g RF for verification only
|
||||
RF_8256=2, // 2 11b/g/n
|
||||
RF_8258=3, // 3 11a/b/g/n RF
|
||||
RF_6052=4, // 4 11b/g/n RF
|
||||
//RF_6052=5, // 4 11b/g/n RF
|
||||
// TODO: We sholud remove this psudo PHY RF after we get new RF.
|
||||
RF_PSEUDO_11N=5, // 5, It is a temporality RF.
|
||||
}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
|
||||
|
||||
|
||||
|
||||
typedef struct _BB_REGISTER_DEFINITION{
|
||||
u32 rfintfs; // set software control:
|
||||
// 0x870~0x877[8 bytes]
|
||||
|
||||
u32 rfintfi; // readback data:
|
||||
// 0x8e0~0x8e7[8 bytes]
|
||||
|
||||
u32 rfintfo; // output data:
|
||||
// 0x860~0x86f [16 bytes]
|
||||
|
||||
u32 rfintfe; // output enable:
|
||||
// 0x860~0x86f [16 bytes]
|
||||
|
||||
u32 rf3wireOffset; // LSSI data:
|
||||
// 0x840~0x84f [16 bytes]
|
||||
|
||||
u32 rfLSSI_Select; // BB Band Select:
|
||||
// 0x878~0x87f [8 bytes]
|
||||
|
||||
u32 rfTxGainStage; // Tx gain stage:
|
||||
// 0x80c~0x80f [4 bytes]
|
||||
|
||||
u32 rfHSSIPara1; // wire parameter control1 :
|
||||
// 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
|
||||
|
||||
u32 rfHSSIPara2; // wire parameter control2 :
|
||||
// 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
|
||||
|
||||
u32 rfSwitchControl; //Tx Rx antenna control :
|
||||
// 0x858~0x85f [16 bytes]
|
||||
|
||||
u32 rfAGCControl1; //AGC parameter control1 :
|
||||
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
|
||||
|
||||
u32 rfAGCControl2; //AGC parameter control2 :
|
||||
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
|
||||
|
||||
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
|
||||
// 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
|
||||
|
||||
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
|
||||
// 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
|
||||
|
||||
u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
|
||||
// 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
|
||||
|
||||
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
|
||||
// 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
|
||||
|
||||
u32 rfLSSIReadBack; //LSSI RF readback data SI mode
|
||||
// 0x8a0~0x8af [16 bytes]
|
||||
|
||||
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
|
||||
|
||||
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
|
||||
|
||||
|
||||
typedef struct _R_ANTENNA_SELECT_OFDM{
|
||||
u32 r_tx_antenna:4;
|
||||
u32 r_ant_l:4;
|
||||
u32 r_ant_non_ht:4;
|
||||
u32 r_ant_ht1:4;
|
||||
u32 r_ant_ht2:4;
|
||||
u32 r_ant_ht_s1:4;
|
||||
u32 r_ant_non_ht_s1:4;
|
||||
u32 OFDM_TXSC:2;
|
||||
u32 Reserved:2;
|
||||
}R_ANTENNA_SELECT_OFDM;
|
||||
|
||||
typedef struct _R_ANTENNA_SELECT_CCK{
|
||||
u8 r_cckrx_enable_2:2;
|
||||
u8 r_cckrx_enable:2;
|
||||
u8 r_ccktx_enable:4;
|
||||
}R_ANTENNA_SELECT_CCK;
|
||||
|
||||
/*------------------------------Define structure----------------------------*/
|
||||
|
||||
|
||||
/*------------------------Export global variable----------------------------*/
|
||||
/*------------------------Export global variable----------------------------*/
|
||||
|
||||
|
||||
/*------------------------Export Marco Definition---------------------------*/
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
//
|
||||
// BB and RF register read/write
|
||||
//
|
||||
void rtl8192d_PHY_SetBBReg1Byte( PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data );
|
||||
u32 rtl8192d_PHY_QueryBBReg( PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask );
|
||||
void rtl8192d_PHY_SetBBReg( PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data );
|
||||
u32 rtl8192d_PHY_QueryRFReg( PADAPTER Adapter,
|
||||
RF_RADIO_PATH_E eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask );
|
||||
void rtl8192d_PHY_SetRFReg( PADAPTER Adapter,
|
||||
RF_RADIO_PATH_E eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data );
|
||||
|
||||
//
|
||||
// Initialization related function
|
||||
//
|
||||
/* MAC/BB/RF HAL config */
|
||||
extern int PHY_MACConfig8192D( PADAPTER Adapter );
|
||||
extern int PHY_BBConfig8192D( PADAPTER Adapter );
|
||||
extern int PHY_RFConfig8192D( PADAPTER Adapter );
|
||||
/* RF config */
|
||||
int rtl8192d_PHY_ConfigRFWithParaFile( PADAPTER Adapter,
|
||||
u8* pFileName,
|
||||
RF_RADIO_PATH_E eRFPath);
|
||||
int rtl8192d_PHY_ConfigRFWithHeaderFile( PADAPTER Adapter,
|
||||
RF_CONTENT Content,
|
||||
RF_RADIO_PATH_E eRFPath);
|
||||
/* BB/RF readback check for making sure init OK */
|
||||
int rtl8192d_PHY_CheckBBAndRFOK( PADAPTER Adapter,
|
||||
HW90_BLOCK_E CheckBlock,
|
||||
RF_RADIO_PATH_E eRFPath );
|
||||
/* Read initi reg value for tx power setting. */
|
||||
void rtl8192d_PHY_GetHWRegOriginalValue( PADAPTER Adapter );
|
||||
|
||||
//
|
||||
// RF Power setting
|
||||
//
|
||||
//extern bool PHY_SetRFPowerState( PADAPTER Adapter,
|
||||
// RT_RF_POWER_STATE eRFPowerState);
|
||||
|
||||
//
|
||||
// BB TX Power R/W
|
||||
//
|
||||
void PHY_GetTxPowerLevel8192D( PADAPTER Adapter,
|
||||
OUT u32* powerlevel );
|
||||
void PHY_SetTxPowerLevel8192D( PADAPTER Adapter,
|
||||
u8 channel );
|
||||
bool PHY_UpdateTxPowerDbm8192D( PADAPTER Adapter,
|
||||
int powerInDbm );
|
||||
|
||||
//
|
||||
void
|
||||
PHY_ScanOperationBackup8192D( PADAPTER Adapter,
|
||||
u8 Operation );
|
||||
|
||||
//
|
||||
// Switch bandwidth for 8192S
|
||||
//
|
||||
//void PHY_SetBWModeCallback8192C( PRT_TIMER pTimer );
|
||||
void PHY_SetBWMode8192D( PADAPTER pAdapter,
|
||||
HT_CHANNEL_WIDTH ChnlWidth,
|
||||
unsigned char Offset );
|
||||
|
||||
//
|
||||
// Set FW CMD IO for 8192S.
|
||||
//
|
||||
//extern bool HalSetIO8192C( PADAPTER Adapter,
|
||||
// IO_TYPE IOType);
|
||||
|
||||
//
|
||||
// Set A2 entry to fw for 8192S
|
||||
//
|
||||
extern void FillA2Entry8192C( PADAPTER Adapter,
|
||||
u8 index,
|
||||
u8* val);
|
||||
|
||||
|
||||
//
|
||||
// channel switch related funciton
|
||||
//
|
||||
//extern void PHY_SwChnlCallback8192C( PRT_TIMER pTimer );
|
||||
void PHY_SwChnl8192D( PADAPTER pAdapter,
|
||||
u8 channel );
|
||||
// Call after initialization
|
||||
void PHY_SwChnlPhy8192D( PADAPTER pAdapter,
|
||||
u8 channel );
|
||||
|
||||
extern void ChkFwCmdIoDone( PADAPTER Adapter);
|
||||
|
||||
|
||||
//
|
||||
// BB/MAC/RF other monitor API
|
||||
//
|
||||
void PHY_SetMonitorMode8192D( PADAPTER pAdapter,
|
||||
bool bEnableMonitorMode );
|
||||
|
||||
bool PHY_CheckIsLegalRfPath8192D( PADAPTER pAdapter,
|
||||
u32 eRFPath );
|
||||
|
||||
|
||||
//
|
||||
// Modify the value of the hw register when beacon interval be changed.
|
||||
//
|
||||
void
|
||||
rtl8192d_PHY_SetBeaconHwReg( PADAPTER Adapter,
|
||||
u16 BeaconInterval );
|
||||
|
||||
|
||||
extern void
|
||||
PHY_SwitchEphyParameter(
|
||||
PADAPTER Adapter
|
||||
);
|
||||
|
||||
extern void
|
||||
PHY_EnableHostClkReq(
|
||||
PADAPTER Adapter
|
||||
);
|
||||
|
||||
bool
|
||||
SetAntennaConfig92C(
|
||||
PADAPTER Adapter,
|
||||
u8 DefaultAnt
|
||||
);
|
||||
|
||||
void
|
||||
PHY_UpdateBBRFConfiguration8192D(
|
||||
IN PADAPTER Adapter,
|
||||
IN bool bisBandSwitch
|
||||
);
|
||||
|
||||
void PHY_ReadMacPhyMode92D(
|
||||
IN PADAPTER Adapter,
|
||||
IN bool AutoloadFail
|
||||
);
|
||||
|
||||
void PHY_ConfigMacPhyMode92D(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
void PHY_ConfigMacPhyModeInfo92D(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
void PHY_ConfigMacCoexist_RFPage92D(
|
||||
IN PADAPTER Adapter
|
||||
);
|
||||
|
||||
void
|
||||
rtl8192d_PHY_InitRxSetting(
|
||||
PADAPTER Adapter
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
rtl8192d_PHY_SetRFPathSwitch( PADAPTER pAdapter, bool bMain);
|
||||
|
||||
void
|
||||
HalChangeCCKStatus8192D(
|
||||
PADAPTER Adapter,
|
||||
bool bCCKDisable
|
||||
);
|
||||
|
||||
void
|
||||
PHY_InitPABias92D( PADAPTER Adapter);
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
|
||||
#define PHY_SetBBReg1Byte(Adapter, RegAddr, BitMask, Data) rtl8192d_PHY_SetBBReg1Byte((Adapter), (RegAddr), (BitMask), (Data))
|
||||
#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtl8192d_PHY_QueryBBReg((Adapter), (RegAddr), (BitMask))
|
||||
#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtl8192d_PHY_SetBBReg((Adapter), (RegAddr), (BitMask), (Data))
|
||||
#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtl8192d_PHY_QueryRFReg((Adapter), (eRFPath), (RegAddr), (BitMask))
|
||||
#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtl8192d_PHY_SetRFReg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
|
||||
|
||||
#define PHY_SetMacReg PHY_SetBBReg
|
||||
|
||||
#endif // __INC_HAL8192SPHYCFG_H
|
File diff suppressed because it is too large
Load diff
|
@ -1,29 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __INC_HAL8723PHYCFG_H__
|
||||
#define __INC_HAL8723PHYCFG_H__
|
||||
|
||||
#include <Hal8192CPhyCfg.h>
|
||||
/* MAC/BB/RF HAL config */
|
||||
int PHY_BBConfig8723A( PADAPTER Adapter );
|
||||
int PHY_RFConfig8723A( PADAPTER Adapter );
|
||||
s32 PHY_MACConfig8723A(PADAPTER padapter);
|
||||
|
||||
#endif
|
|
@ -1,73 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __INC_HAL8723APHYREG_H__
|
||||
#define __INC_HAL8723APHYREG_H__
|
||||
|
||||
#include <Hal8192CPhyReg.h>
|
||||
|
||||
//
|
||||
// PageB(0xB00)
|
||||
//
|
||||
#define rPdp_AntA 0xb00
|
||||
#define rPdp_AntA_4 0xb04
|
||||
#define rPdp_AntA_8 0xb08
|
||||
#define rPdp_AntA_C 0xb0c
|
||||
#define rPdp_AntA_10 0xb10
|
||||
#define rPdp_AntA_14 0xb14
|
||||
#define rPdp_AntA_18 0xb18
|
||||
#define rPdp_AntA_1C 0xb1c
|
||||
#define rPdp_AntA_20 0xb20
|
||||
#define rPdp_AntA_24 0xb24
|
||||
|
||||
#define rConfig_Pmpd_AntA 0xb28
|
||||
#define rConfig_ram64x16 0xb2c
|
||||
|
||||
#define rBndA 0xb30
|
||||
#define rHssiPar 0xb34
|
||||
|
||||
#define rConfig_AntA 0xb68
|
||||
#define rConfig_AntB 0xb6c
|
||||
|
||||
#define rPdp_AntB 0xb70
|
||||
#define rPdp_AntB_4 0xb74
|
||||
#define rPdp_AntB_8 0xb78
|
||||
#define rPdp_AntB_C 0xb7c
|
||||
#define rPdp_AntB_10 0xb80
|
||||
#define rPdp_AntB_14 0xb84
|
||||
#define rPdp_AntB_18 0xb88
|
||||
#define rPdp_AntB_1C 0xb8c
|
||||
#define rPdp_AntB_20 0xb90
|
||||
#define rPdp_AntB_24 0xb94
|
||||
|
||||
#define rConfig_Pmpd_AntB 0xb98
|
||||
|
||||
#define rBndB 0xba0
|
||||
|
||||
#define rAPK 0xbd8
|
||||
#define rPm_Rx0_AntA 0xbdc
|
||||
#define rPm_Rx1_AntA 0xbe0
|
||||
#define rPm_Rx2_AntA 0xbe4
|
||||
#define rPm_Rx3_AntA 0xbe8
|
||||
#define rPm_Rx0_AntB 0xbec
|
||||
#define rPm_Rx1_AntB 0xbf0
|
||||
#define rPm_Rx2_AntB 0xbf4
|
||||
#define rPm_Rx3_AntB 0xbf8
|
||||
|
||||
#endif
|
|
@ -1,170 +0,0 @@
|
|||
#ifndef __HAL8723PWRSEQ_H__
|
||||
#define __HAL8723PWRSEQ_H__
|
||||
/*
|
||||
Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
|
||||
There are 6 HW Power States:
|
||||
0: POFF--Power Off
|
||||
1: PDN--Power Down
|
||||
2: CARDEMU--Card Emulation
|
||||
3: ACT--Active Mode
|
||||
4: LPS--Low Power State
|
||||
5: SUS--Suspend
|
||||
|
||||
The transision from different states are defined below
|
||||
TRANS_CARDEMU_TO_ACT
|
||||
TRANS_ACT_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_SUS
|
||||
TRANS_SUS_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_PDN
|
||||
TRANS_ACT_TO_LPS
|
||||
TRANS_LPS_TO_ACT
|
||||
|
||||
TRANS_END
|
||||
*/
|
||||
#include "HalPwrSeqCmd.h"
|
||||
#include "rtl8723a_spec.h"
|
||||
|
||||
#define RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS 15
|
||||
#define RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS 15
|
||||
#define RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS 15
|
||||
#define RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS 15
|
||||
#define RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS 15
|
||||
#define RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS 15
|
||||
#define RTL8723A_TRANS_ACT_TO_LPS_STEPS 15
|
||||
#define RTL8723A_TRANS_LPS_TO_ACT_STEPS 15
|
||||
#define RTL8723A_TRANS_END_STEPS 1
|
||||
|
||||
|
||||
#define RTL8723A_TRANS_CARDEMU_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
|
||||
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
|
||||
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
|
||||
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \
|
||||
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 1},/*0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */\
|
||||
|
||||
#define RTL8723A_TRANS_ACT_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
|
||||
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
|
||||
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \
|
||||
|
||||
|
||||
#define RTL8723A_TRANS_CARDEMU_TO_SUS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8723A_TRANS_SUS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
|
||||
|
||||
#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
|
||||
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
|
||||
|
||||
|
||||
#define RTL8723A_TRANS_CARDEMU_TO_PDN \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
|
||||
|
||||
#define RTL8723A_TRANS_PDN_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
|
||||
|
||||
#define RTL8723A_TRANS_ACT_TO_LPS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
|
||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
|
||||
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
|
||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
|
||||
|
||||
|
||||
#define RTL8723A_TRANS_LPS_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
|
||||
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
|
||||
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
|
||||
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
||||
|
||||
#define RTL8723A_TRANS_END \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
|
||||
|
||||
|
||||
extern WLAN_PWR_CFG rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723A_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723A_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723A_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723A_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723A_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723A_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STEPS+RTL8723A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS];
|
||||
|
||||
#endif
|
|
@ -1,32 +0,0 @@
|
|||
#ifndef __CUSTOM_GPIO_H__
|
||||
#define __CUSTOM_GPIO_H___
|
||||
|
||||
#include <drv_conf.h>
|
||||
#include <osdep_service.h>
|
||||
|
||||
#ifdef PLATFORM_OS_XP
|
||||
#include <drv_types_xp.h>
|
||||
#endif
|
||||
|
||||
#ifdef PLATFORM_OS_CE
|
||||
#include <drv_types_ce.h>
|
||||
#endif
|
||||
|
||||
#ifdef PLATFORM_LINUX
|
||||
#include <drv_types_linux.h>
|
||||
#endif
|
||||
|
||||
typedef enum cust_gpio_modes {
|
||||
WLAN_PWDN_ON,
|
||||
WLAN_PWDN_OFF,
|
||||
WLAN_POWER_ON,
|
||||
WLAN_POWER_OFF,
|
||||
WLAN_BT_PWDN_ON,
|
||||
WLAN_BT_PWDN_OFF
|
||||
} cust_gpio_modes_t;
|
||||
|
||||
extern int rtw_wifi_gpio_init(void);
|
||||
extern int rtw_wifi_gpio_deinit(void);
|
||||
extern void rtw_wifi_gpio_wlan_ctrl(int onoff);
|
||||
|
||||
#endif
|
|
@ -1,81 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __DRV_TYPES_CE_H__
|
||||
#define __DRV_TYPES_CE_H__
|
||||
|
||||
#include <drv_conf.h>
|
||||
#include <osdep_service.h>
|
||||
|
||||
#include <Sdcardddk.h>
|
||||
|
||||
#define MAX_ACTIVE_REG_PATH 256
|
||||
|
||||
#define MAX_MCAST_LIST_NUM 32
|
||||
|
||||
|
||||
|
||||
//for ioctl
|
||||
#define MAKE_DRIVER_VERSION(_MainVer,_MinorVer) ((((u32)(_MainVer))<<16)+_MinorVer)
|
||||
|
||||
#define NIC_HEADER_SIZE 14 //!< can be moved to typedef.h
|
||||
#define NIC_MAX_PACKET_SIZE 1514 //!< can be moved to typedef.h
|
||||
#define NIC_MAX_SEND_PACKETS 10 // max number of send packets the MiniportSendPackets function can accept, can be moved to typedef.h
|
||||
#define NIC_VENDOR_DRIVER_VERSION MAKE_DRIVER_VERSION(0,001) //!< can be moved to typedef.h
|
||||
#define NIC_MAX_PACKET_SIZE 1514 //!< can be moved to typedef.h
|
||||
|
||||
typedef struct _MP_REG_ENTRY
|
||||
{
|
||||
|
||||
NDIS_STRING RegName; // variable name text
|
||||
bool bRequired; // 1 -> required, 0 -> optional
|
||||
|
||||
u8 Type; // NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString
|
||||
uint FieldOffset; // offset to MP_ADAPTER field
|
||||
uint FieldSize; // size (in bytes) of the field
|
||||
|
||||
#ifdef UNDER_AMD64
|
||||
u64 Default;
|
||||
#else
|
||||
u32 Default; // default value to use
|
||||
#endif
|
||||
|
||||
u32 Min; // minimum value allowed
|
||||
u32 Max; // maximum value allowed
|
||||
} MP_REG_ENTRY, *PMP_REG_ENTRY;
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
typedef struct _USB_EXTENSION {
|
||||
LPCUSB_FUNCS _lpUsbFuncs;
|
||||
USB_HANDLE _hDevice;
|
||||
void * pAdapter;
|
||||
} USB_EXTENSION, *PUSB_EXTENSION;
|
||||
#endif
|
||||
|
||||
|
||||
typedef struct _OCTET_STRING{
|
||||
u8 *Octet;
|
||||
u16 Length;
|
||||
} OCTET_STRING, *POCTET_STRING;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
|
@ -1,48 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __DRV_TYPES_GSPI_H__
|
||||
#define __DRV_TYPES_GSPI_H__
|
||||
|
||||
#include <drv_conf.h>
|
||||
#include <basic_types.h>
|
||||
|
||||
// SPI Header Files
|
||||
#ifdef PLATFORM_LINUX
|
||||
#include <linux/spi/spi.h>
|
||||
#endif
|
||||
|
||||
|
||||
typedef struct gspi_data
|
||||
{
|
||||
u8 func_number;
|
||||
|
||||
u8 tx_block_mode;
|
||||
u8 rx_block_mode;
|
||||
u32 block_transfer_len;
|
||||
|
||||
#ifdef PLATFORM_LINUX
|
||||
struct spi_device *func;
|
||||
|
||||
struct workqueue_struct *priv_wq;
|
||||
struct delayed_work irq_work;
|
||||
#endif
|
||||
} GSPI_DATA, *PGSPI_DATA;
|
||||
|
||||
#endif // #ifndef __DRV_TYPES_GSPI_H__
|
|
@ -1,70 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __DRV_TYPES_SDIO_H__
|
||||
#define __DRV_TYPES_SDIO_H__
|
||||
|
||||
#include <drv_conf.h>
|
||||
#include <basic_types.h>
|
||||
|
||||
// SDIO Header Files
|
||||
#ifdef PLATFORM_LINUX
|
||||
#include <linux/mmc/sdio_func.h>
|
||||
#endif
|
||||
#ifdef PLATFORM_OS_XP
|
||||
#include <wdm.h>
|
||||
#include <ntddsd.h>
|
||||
#endif
|
||||
#ifdef PLATFORM_OS_CE
|
||||
#include <sdcardddk.h>
|
||||
#endif
|
||||
|
||||
|
||||
typedef struct sdio_data
|
||||
{
|
||||
u8 func_number;
|
||||
|
||||
u8 tx_block_mode;
|
||||
u8 rx_block_mode;
|
||||
u32 block_transfer_len;
|
||||
|
||||
#ifdef PLATFORM_LINUX
|
||||
struct sdio_func *func;
|
||||
_thread_hdl_ sys_sdio_irq_thd;
|
||||
#endif
|
||||
|
||||
#ifdef PLATFORM_OS_XP
|
||||
PDEVICE_OBJECT pphysdevobj;
|
||||
PDEVICE_OBJECT pfuncdevobj;
|
||||
PDEVICE_OBJECT pnextdevobj;
|
||||
SDBUS_INTERFACE_STANDARD sdbusinft;
|
||||
u8 nextdevstacksz;
|
||||
#endif
|
||||
|
||||
#ifdef PLATFORM_OS_CE
|
||||
SD_DEVICE_HANDLE hDevice;
|
||||
SD_CARD_RCA sd_rca;
|
||||
SD_CARD_INTERFACE card_intf;
|
||||
bool enableIsarWithStatus;
|
||||
WCHAR active_path[MAX_ACTIVE_REG_PATH];
|
||||
SD_HOST_BLOCK_CAPABILITY sd_host_blk_cap;
|
||||
#endif
|
||||
} SDIO_DATA, *PSDIO_DATA;
|
||||
|
||||
#endif
|
|
@ -1,94 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __DRV_TYPES_XP_H__
|
||||
#define __DRV_TYPES_XP_H__
|
||||
|
||||
#include <drv_conf.h>
|
||||
#include <osdep_service.h>
|
||||
|
||||
|
||||
|
||||
#define MAX_MCAST_LIST_NUM 32
|
||||
|
||||
|
||||
|
||||
//for ioctl
|
||||
#define MAKE_DRIVER_VERSION(_MainVer,_MinorVer) ((((u32)(_MainVer))<<16)+_MinorVer)
|
||||
|
||||
#define NIC_HEADER_SIZE 14 //!< can be moved to typedef.h
|
||||
#define NIC_MAX_PACKET_SIZE 1514 //!< can be moved to typedef.h
|
||||
#define NIC_MAX_SEND_PACKETS 10 // max number of send packets the MiniportSendPackets function can accept, can be moved to typedef.h
|
||||
#define NIC_VENDOR_DRIVER_VERSION MAKE_DRIVER_VERSION(0,001) //!< can be moved to typedef.h
|
||||
#define NIC_MAX_PACKET_SIZE 1514 //!< can be moved to typedef.h
|
||||
|
||||
|
||||
#undef ON_VISTA
|
||||
//added by Jackson
|
||||
#ifndef ON_VISTA
|
||||
//
|
||||
// Bus driver versions
|
||||
//
|
||||
|
||||
#define SDBUS_DRIVER_VERSION_1 0x100
|
||||
#define SDBUS_DRIVER_VERSION_2 0x200
|
||||
|
||||
#define SDP_FUNCTION_TYPE 4
|
||||
#define SDP_BUS_DRIVER_VERSION 5
|
||||
#define SDP_BUS_WIDTH 6
|
||||
#define SDP_BUS_CLOCK 7
|
||||
#define SDP_BUS_INTERFACE_CONTROL 8
|
||||
#define SDP_HOST_BLOCK_LENGTH 9
|
||||
#define SDP_FUNCTION_BLOCK_LENGTH 10
|
||||
#define SDP_FN0_BLOCK_LENGTH 11
|
||||
#define SDP_FUNCTION_INT_ENABLE 12
|
||||
#endif
|
||||
|
||||
|
||||
typedef struct _MP_REG_ENTRY
|
||||
{
|
||||
|
||||
NDIS_STRING RegName; // variable name text
|
||||
bool bRequired; // 1 -> required, 0 -> optional
|
||||
|
||||
u8 Type; // NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString
|
||||
uint FieldOffset; // offset to MP_ADAPTER field
|
||||
uint FieldSize; // size (in bytes) of the field
|
||||
|
||||
#ifdef UNDER_AMD64
|
||||
u64 Default;
|
||||
#else
|
||||
u32 Default; // default value to use
|
||||
#endif
|
||||
|
||||
u32 Min; // minimum value allowed
|
||||
u32 Max; // maximum value allowed
|
||||
} MP_REG_ENTRY, *PMP_REG_ENTRY;
|
||||
|
||||
|
||||
typedef struct _OCTET_STRING{
|
||||
u8 *Octet;
|
||||
u16 Length;
|
||||
} OCTET_STRING, *POCTET_STRING;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
|
@ -20,10 +20,43 @@
|
|||
#ifndef __RTL8188E_RECV_H__
|
||||
#define __RTL8188E_RECV_H__
|
||||
|
||||
#include <rtl8192c_recv.h>
|
||||
|
||||
#define TX_RPT1_PKT_LEN 8
|
||||
|
||||
#define RECV_BLK_SZ 512
|
||||
#define RECV_BLK_CNT 16
|
||||
#define RECV_BLK_TH RECV_BLK_CNT
|
||||
#define RECV_BULK_IN_ADDR 0x80
|
||||
#define RECV_INT_IN_ADDR 0x81
|
||||
|
||||
#define NR_PREALLOC_RECV_SKB (8)
|
||||
|
||||
#ifdef CONFIG_SINGLE_RECV_BUF
|
||||
#define NR_RECVBUFF (1)
|
||||
#else
|
||||
#define NR_RECVBUFF (4)
|
||||
#endif //CONFIG_SINGLE_RECV_BUF
|
||||
|
||||
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
|
||||
#define MAX_RECVBUF_SZ (15360) // 15k < 16k
|
||||
#else
|
||||
#define MAX_RECVBUF_SZ (4000) // about 4K
|
||||
#endif
|
||||
|
||||
struct phy_stat {
|
||||
unsigned int phydw0;
|
||||
unsigned int phydw1;
|
||||
unsigned int phydw2;
|
||||
unsigned int phydw3;
|
||||
unsigned int phydw4;
|
||||
unsigned int phydw5;
|
||||
unsigned int phydw6;
|
||||
unsigned int phydw7;
|
||||
};
|
||||
|
||||
// Rx smooth factor
|
||||
#define Rx_Smooth_Factor (20)
|
||||
|
||||
|
||||
typedef enum _RX_PACKET_TYPE{
|
||||
NORMAL_RX,//Normal rx packet
|
||||
TX_REPORT1,//CCX
|
||||
|
|
|
@ -1,115 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __RTL8192C_CMD_H_
|
||||
#define __RTL8192C_CMD_H_
|
||||
|
||||
|
||||
enum cmd_msg_element_id
|
||||
{
|
||||
NONE_CMDMSG_EID,
|
||||
AP_OFFLOAD_EID=0,
|
||||
SET_PWRMODE_EID=1,
|
||||
JOINBSS_RPT_EID=2,
|
||||
RSVD_PAGE_EID=3,
|
||||
RSSI_4_EID = 4,
|
||||
RSSI_SETTING_EID=5,
|
||||
MACID_CONFIG_EID=6,
|
||||
MACID_PS_MODE_EID=7,
|
||||
P2P_PS_OFFLOAD_EID=8,
|
||||
SELECTIVE_SUSPEND_ROF_CMD=9,
|
||||
P2P_PS_CTW_CMD_EID=32,
|
||||
H2C_92C_IO_OFFLOAD=44,
|
||||
H2C_92C_TSF_SYNC=67,
|
||||
H2C_92C_DISABLE_BCN_FUNC=68,
|
||||
H2C_92C_RESET_TSF = 75,
|
||||
H2C_92C_CMD_MAX
|
||||
};
|
||||
|
||||
struct cmd_msg_parm {
|
||||
u8 eid; //element id
|
||||
u8 sz; // sz
|
||||
u8 buf[6];
|
||||
};
|
||||
|
||||
typedef struct _SETPWRMODE_PARM{
|
||||
u8 Mode;
|
||||
u8 SmartPS;
|
||||
u8 BcnPassTime; // unit: 100ms
|
||||
}SETPWRMODE_PARM, *PSETPWRMODE_PARM;
|
||||
|
||||
struct H2C_SS_RFOFF_PARAM{
|
||||
u8 ROFOn; // 1: on, 0:off
|
||||
u16 gpio_period; // unit: 1024 us
|
||||
}__attribute__ ((packed));
|
||||
|
||||
|
||||
typedef struct JOINBSSRPT_PARM{
|
||||
u8 OpMode; // RT_MEDIA_STATUS
|
||||
}JOINBSSRPT_PARM, *PJOINBSSRPT_PARM;
|
||||
|
||||
typedef struct _RSVDPAGE_LOC{
|
||||
u8 LocProbeRsp;
|
||||
u8 LocPsPoll;
|
||||
u8 LocNullData;
|
||||
}RSVDPAGE_LOC, *PRSVDPAGE_LOC;
|
||||
|
||||
struct P2P_PS_Offload_t {
|
||||
unsigned char Offload_En:1;
|
||||
unsigned char role:1; // 1: Owner, 0: Client
|
||||
unsigned char CTWindow_En:1;
|
||||
unsigned char NoA0_En:1;
|
||||
unsigned char NoA1_En:1;
|
||||
unsigned char AllStaSleep:1; // Only valid in Owner
|
||||
unsigned char discovery:1;
|
||||
unsigned char rsvd:1;
|
||||
};
|
||||
|
||||
struct P2P_PS_CTWPeriod_t {
|
||||
unsigned char CTWPeriod; //TU
|
||||
};
|
||||
|
||||
// host message to firmware cmd
|
||||
void rtl8192c_set_FwPwrMode_cmd(_adapter*padapter, u8 Mode);
|
||||
void rtl8192c_set_FwJoinBssReport_cmd(_adapter* padapter, u8 mstatus);
|
||||
u8 rtl8192c_set_rssi_cmd(_adapter*padapter, u8 *param);
|
||||
u8 rtl8192c_set_raid_cmd(_adapter*padapter, u32 mask, u8 arg);
|
||||
void rtl8192c_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8 arg, u8 rssi_level);
|
||||
u8 rtl8192c_set_FwSelectSuspend_cmd(_adapter*padapter,u8 bfwpoll, u16 period);
|
||||
#ifdef CONFIG_P2P
|
||||
void rtl8192c_set_p2p_ps_offload_cmd(_adapter* padapter, u8 p2p_ps_state);
|
||||
#endif //CONFIG_P2P
|
||||
|
||||
#ifdef CONFIG_IOL
|
||||
typedef struct _IO_OFFLOAD_LOC{
|
||||
u8 LocCmd;
|
||||
}IO_OFFLOAD_LOC, *PIO_OFFLOAD_LOC;
|
||||
int rtl8192c_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);
|
||||
#endif //CONFIG_IOL
|
||||
|
||||
#ifdef CONFIG_BEACON_DISABLE_OFFLOAD
|
||||
u8 rtl8192c_dis_beacon_fun_cmd(_adapter* padapter);
|
||||
#endif // CONFIG_BEACON_DISABLE_OFFLOAD
|
||||
|
||||
|
||||
#ifdef CONFIG_TSF_RESET_OFFLOAD
|
||||
u8 rtl8192c_reset_tsf(_adapter *padapter, u8 reset_port);
|
||||
#endif // CONFIG_TSF_RESET_OFFLOAD
|
||||
|
||||
#endif // __RTL8192C_CMD_H_
|
|
@ -1,262 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __RTL8192C_DM_H__
|
||||
#define __RTL8192C_DM_H__
|
||||
//============================================================
|
||||
// Description:
|
||||
//
|
||||
// This file is for 92CE/92CU dynamic mechanism only
|
||||
//
|
||||
//
|
||||
//============================================================
|
||||
|
||||
//============================================================
|
||||
// function prototype
|
||||
//============================================================
|
||||
#define DYNAMIC_FUNC_BT BIT(0)
|
||||
|
||||
enum{
|
||||
UP_LINK,
|
||||
DOWN_LINK,
|
||||
};
|
||||
typedef enum _BT_Ant_NUM{
|
||||
Ant_x2 = 0,
|
||||
Ant_x1 = 1
|
||||
} BT_Ant_NUM, *PBT_Ant_NUM;
|
||||
|
||||
typedef enum _BT_CoType{
|
||||
BT_2Wire = 0,
|
||||
BT_ISSC_3Wire = 1,
|
||||
BT_Accel = 2,
|
||||
BT_CSR_BC4 = 3,
|
||||
BT_CSR_BC8 = 4,
|
||||
BT_RTL8756 = 5,
|
||||
} BT_CoType, *PBT_CoType;
|
||||
|
||||
typedef enum _BT_CurState{
|
||||
BT_OFF = 0,
|
||||
BT_ON = 1,
|
||||
} BT_CurState, *PBT_CurState;
|
||||
|
||||
typedef enum _BT_ServiceType{
|
||||
BT_SCO = 0,
|
||||
BT_A2DP = 1,
|
||||
BT_HID = 2,
|
||||
BT_HID_Idle = 3,
|
||||
BT_Scan = 4,
|
||||
BT_Idle = 5,
|
||||
BT_OtherAction = 6,
|
||||
BT_Busy = 7,
|
||||
BT_OtherBusy = 8,
|
||||
BT_PAN = 9,
|
||||
} BT_ServiceType, *PBT_ServiceType;
|
||||
|
||||
typedef enum _BT_RadioShared{
|
||||
BT_Radio_Shared = 0,
|
||||
BT_Radio_Individual = 1,
|
||||
} BT_RadioShared, *PBT_RadioShared;
|
||||
|
||||
struct btcoexist_priv {
|
||||
u8 BT_Coexist;
|
||||
u8 BT_Ant_Num;
|
||||
u8 BT_CoexistType;
|
||||
u8 BT_State;
|
||||
u8 BT_CUR_State; //0:on, 1:off
|
||||
u8 BT_Ant_isolation; //0:good, 1:bad
|
||||
u8 BT_PapeCtrl; //0:SW, 1:SW/HW dynamic
|
||||
u8 BT_Service;
|
||||
u8 BT_Ampdu; // 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU.
|
||||
u8 BT_RadioSharedType;
|
||||
u32 Ratio_Tx;
|
||||
u32 Ratio_PRI;
|
||||
u8 BtRfRegOrigin1E;
|
||||
u8 BtRfRegOrigin1F;
|
||||
u8 BtRssiState;
|
||||
u32 BtEdcaUL;
|
||||
u32 BtEdcaDL;
|
||||
u32 BT_EDCA[2];
|
||||
u8 bCOBT;
|
||||
|
||||
u8 bInitSet;
|
||||
u8 bBTBusyTraffic;
|
||||
u8 bBTTrafficModeSet;
|
||||
u8 bBTNonTrafficModeSet;
|
||||
//BTTraffic BT21TrafficStatistics;
|
||||
u32 CurrentState;
|
||||
u32 PreviousState;
|
||||
u8 BtPreRssiState;
|
||||
u8 bFWCoexistAllOff;
|
||||
u8 bSWCoexistAllOff;
|
||||
};
|
||||
|
||||
//============================================================
|
||||
// structure and define
|
||||
//============================================================
|
||||
|
||||
//###### duplicate code,will move to ODM #########
|
||||
#define IQK_MAC_REG_NUM 4
|
||||
#define IQK_ADDA_REG_NUM 16
|
||||
#define IQK_BB_REG_NUM 9
|
||||
#define HP_THERMAL_NUM 8
|
||||
//###### duplicate code,will move to ODM #########
|
||||
struct dm_priv
|
||||
{
|
||||
u8 DM_Type;
|
||||
u8 DMFlag;
|
||||
u8 InitDMFlag;
|
||||
u32 InitODMFlag;
|
||||
|
||||
//* Upper and Lower Signal threshold for Rate Adaptive*/
|
||||
int UndecoratedSmoothedPWDB;
|
||||
int UndecoratedSmoothedCCK;
|
||||
int EntryMinUndecoratedSmoothedPWDB;
|
||||
int EntryMaxUndecoratedSmoothedPWDB;
|
||||
int MinUndecoratedPWDBForDM;
|
||||
int LastMinUndecoratedPWDBForDM;
|
||||
|
||||
//###### duplicate code,will move to ODM #########
|
||||
/*
|
||||
//for DIG
|
||||
u8 bDMInitialGainEnable;
|
||||
u8 binitialized; // for dm_initial_gain_Multi_STA use.
|
||||
DIG_T DM_DigTable;
|
||||
|
||||
PS_T DM_PSTable;
|
||||
|
||||
FALSE_ALARM_STATISTICS FalseAlmCnt;
|
||||
|
||||
//for rate adaptive, in fact, 88c/92c fw will handle this
|
||||
u8 bUseRAMask;
|
||||
RATE_ADAPTIVE RateAdaptive;
|
||||
*/
|
||||
//for High Power
|
||||
u8 bDynamicTxPowerEnable;
|
||||
u8 LastDTPLvl;
|
||||
u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06
|
||||
|
||||
//for tx power tracking
|
||||
u8 bTXPowerTracking;
|
||||
u8 TXPowercount;
|
||||
u8 bTXPowerTrackingInit;
|
||||
u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
|
||||
u8 TM_Trigger;
|
||||
|
||||
u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
|
||||
u8 ThermalValue;
|
||||
u8 ThermalValue_LCK;
|
||||
u8 ThermalValue_IQK;
|
||||
u8 ThermalValue_DPK;
|
||||
|
||||
u8 bRfPiEnable;
|
||||
|
||||
//for APK
|
||||
u32 APKoutput[2][2]; //path A/B; output1_1a/output1_2a
|
||||
u8 bAPKdone;
|
||||
u8 bAPKThermalMeterIgnore;
|
||||
u8 bDPdone;
|
||||
u8 bDPPathAOK;
|
||||
u8 bDPPathBOK;
|
||||
|
||||
//for IQK
|
||||
u32 RegC04;
|
||||
u32 Reg874;
|
||||
u32 RegC08;
|
||||
u32 RegB68;
|
||||
u32 RegB6C;
|
||||
u32 Reg870;
|
||||
u32 Reg860;
|
||||
u32 Reg864;
|
||||
u32 ADDA_backup[IQK_ADDA_REG_NUM];
|
||||
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
|
||||
u32 IQK_BB_backup_recover[9];
|
||||
u32 IQK_BB_backup[IQK_BB_REG_NUM];
|
||||
u8 PowerIndex_backup[6];
|
||||
|
||||
u8 bCCKinCH14;
|
||||
|
||||
u8 CCK_index;
|
||||
u8 OFDM_index[2];
|
||||
|
||||
u8 bDoneTxpower;
|
||||
u8 CCK_index_HP;
|
||||
u8 OFDM_index_HP[2];
|
||||
u8 ThermalValue_HP[HP_THERMAL_NUM];
|
||||
u8 ThermalValue_HP_index;
|
||||
|
||||
//for TxPwrTracking
|
||||
s32 RegE94;
|
||||
s32 RegE9C;
|
||||
s32 RegEB4;
|
||||
s32 RegEBC;
|
||||
|
||||
u32 TXPowerTrackingCallbackCnt; //cosa add for debug
|
||||
|
||||
u32 prv_traffic_idx; // edca turbo
|
||||
|
||||
/*
|
||||
// for dm_RF_Saving
|
||||
u8 initialize;
|
||||
u32 rf_saving_Reg874;
|
||||
u32 rf_saving_RegC70;
|
||||
u32 rf_saving_Reg85C;
|
||||
u32 rf_saving_RegA74;
|
||||
*/
|
||||
//for Antenna diversity
|
||||
#ifdef CONFIG_ANTENNA_DIVERSITY
|
||||
// SWAT_T DM_SWAT_Table;
|
||||
#endif
|
||||
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
|
||||
// _timer SwAntennaSwitchTimer;
|
||||
/*
|
||||
u64 lastTxOkCnt;
|
||||
u64 lastRxOkCnt;
|
||||
u64 TXByteCnt_A;
|
||||
u64 TXByteCnt_B;
|
||||
u64 RXByteCnt_A;
|
||||
u64 RXByteCnt_B;
|
||||
u8 DoubleComfirm;
|
||||
u8 TrafficLoad;
|
||||
*/
|
||||
#endif
|
||||
|
||||
s32 OFDM_Pkt_Cnt;
|
||||
u8 RSSI_Select;
|
||||
// u8 DIG_Dynamic_MIN ;
|
||||
//###### duplicate code,will move to ODM #########
|
||||
// Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas
|
||||
u8 INIDATA_RATE[32];
|
||||
};
|
||||
|
||||
|
||||
//============================================================
|
||||
// function prototype
|
||||
//============================================================
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
void rtl8192c_set_dm_bt_coexist(_adapter *padapter, u8 bStart);
|
||||
void rtl8192c_issue_delete_ba(_adapter *padapter, u8 dir);
|
||||
#endif
|
||||
|
||||
void rtl8192c_init_dm_priv(IN PADAPTER Adapter);
|
||||
void rtl8192c_deinit_dm_priv(IN PADAPTER Adapter);
|
||||
|
||||
void rtl8192c_InitHalDm( PADAPTER Adapter);
|
||||
void rtl8192c_HalDmWatchDog(IN PADAPTER Adapter);
|
||||
|
||||
#endif //__HAL8190PCIDM_H__
|
|
@ -1,26 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef _RTL8192C_EVENT_H_
|
||||
#define _RTL8192C_EVENT_H_
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
|
@ -1,849 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __RTL8192C_HAL_H__
|
||||
#define __RTL8192C_HAL_H__
|
||||
|
||||
#include "rtl8192c_spec.h"
|
||||
#include "Hal8192CPhyReg.h"
|
||||
#include "Hal8192CPhyCfg.h"
|
||||
#include "rtl8192c_rf.h"
|
||||
#include "rtl8192c_dm.h"
|
||||
#include "rtl8192c_recv.h"
|
||||
#include "rtl8192c_xmit.h"
|
||||
#include "rtl8192c_cmd.h"
|
||||
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
#include "rtl8192c_sreset.h"
|
||||
#endif
|
||||
#include "rtw_efuse.h"
|
||||
|
||||
#include "../hal/OUTSRC/odm_precomp.h"
|
||||
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
|
||||
#define RTL819X_DEFAULT_RF_TYPE RF_2T2R
|
||||
//#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
|
||||
#define RTL819X_TOTAL_RF_PATH 2
|
||||
|
||||
//2TODO: The following need to check!!
|
||||
#define RTL8192C_FW_TSMC_IMG "rtl8192CE\\rtl8192cfwT.bin"
|
||||
#define RTL8192C_FW_UMC_IMG "rtl8192CE\\rtl8192cfwU.bin"
|
||||
#define RTL8192C_FW_UMC_B_IMG "rtl8192CE\\rtl8192cfwU_B.bin"
|
||||
|
||||
#define RTL8188C_PHY_REG "rtl8192CE\\PHY_REG_1T.txt"
|
||||
#define RTL8188C_PHY_RADIO_A "rtl8192CE\\radio_a_1T.txt"
|
||||
#define RTL8188C_PHY_RADIO_B "rtl8192CE\\radio_b_1T.txt"
|
||||
#define RTL8188C_AGC_TAB "rtl8192CE\\AGC_TAB_1T.txt"
|
||||
#define RTL8188C_PHY_MACREG "rtl8192CE\\MACREG_1T.txt"
|
||||
|
||||
#define RTL8192C_PHY_REG "rtl8192CE\\PHY_REG_2T.txt"
|
||||
#define RTL8192C_PHY_RADIO_A "rtl8192CE\\radio_a_2T.txt"
|
||||
#define RTL8192C_PHY_RADIO_B "rtl8192CE\\radio_b_2T.txt"
|
||||
#define RTL8192C_AGC_TAB "rtl8192CE\\AGC_TAB_2T.txt"
|
||||
#define RTL8192C_PHY_MACREG "rtl8192CE\\MACREG_2T.txt"
|
||||
|
||||
#define RTL819X_PHY_MACPHY_REG "rtl8192CE\\MACPHY_reg.txt"
|
||||
#define RTL819X_PHY_MACPHY_REG_PG "rtl8192CE\\MACPHY_reg_PG.txt"
|
||||
#define RTL819X_PHY_MACREG "rtl8192CE\\MAC_REG.txt"
|
||||
#define RTL819X_PHY_REG "rtl8192CE\\PHY_REG.txt"
|
||||
#define RTL819X_PHY_REG_1T2R "rtl8192CE\\PHY_REG_1T2R.txt"
|
||||
#define RTL819X_PHY_REG_to1T1R "rtl8192CE\\phy_to1T1R_a.txt"
|
||||
#define RTL819X_PHY_REG_to1T2R "rtl8192CE\\phy_to1T2R.txt"
|
||||
#define RTL819X_PHY_REG_to2T2R "rtl8192CE\\phy_to2T2R.txt"
|
||||
#define RTL819X_PHY_REG_PG "rtl8192CE\\PHY_REG_PG.txt"
|
||||
#define RTL819X_AGC_TAB "rtl8192CE\\AGC_TAB.txt"
|
||||
#define RTL819X_PHY_RADIO_A "rtl8192CE\\radio_a.txt"
|
||||
#define RTL819X_PHY_RADIO_A_1T "rtl8192CE\\radio_a_1t.txt"
|
||||
#define RTL819X_PHY_RADIO_A_2T "rtl8192CE\\radio_a_2t.txt"
|
||||
#define RTL819X_PHY_RADIO_B "rtl8192CE\\radio_b.txt"
|
||||
#define RTL819X_PHY_RADIO_B_GM "rtl8192CE\\radio_b_gm.txt"
|
||||
#define RTL819X_PHY_RADIO_C "rtl8192CE\\radio_c.txt"
|
||||
#define RTL819X_PHY_RADIO_D "rtl8192CE\\radio_d.txt"
|
||||
#define RTL819X_EEPROM_MAP "rtl8192CE\\8192ce.map"
|
||||
#define RTL819X_EFUSE_MAP "rtl8192CE\\8192ce.map"
|
||||
|
||||
//---------------------------------------------------------------------
|
||||
// RTL8723E From file
|
||||
//---------------------------------------------------------------------
|
||||
|
||||
// The file name "_2T" is for 92CE, "_1T" is for 88CE. Modified by tynli. 2009.11.24.
|
||||
#define Rtl819XFwTSMCImageArray Rtl8192CEFwTSMCImgArray
|
||||
#define Rtl819XFwUMCACutImageArray Rtl8192CEFwUMCACutImgArray
|
||||
#define Rtl819XFwUMCBCutImageArray Rtl8192CEFwUMCBCutImgArray
|
||||
|
||||
// #define Rtl8723FwUMCImageArray Rtl8192CEFwUMC8723ImgArray
|
||||
#define Rtl819XMAC_Array Rtl8192CEMAC_2T_Array
|
||||
#define Rtl819XAGCTAB_2TArray Rtl8192CEAGCTAB_2TArray
|
||||
#define Rtl819XAGCTAB_1TArray Rtl8192CEAGCTAB_1TArray
|
||||
#define Rtl819XPHY_REG_2TArray Rtl8192CEPHY_REG_2TArray
|
||||
#define Rtl819XPHY_REG_1TArray Rtl8192CEPHY_REG_1TArray
|
||||
#define Rtl819XRadioA_2TArray Rtl8192CERadioA_2TArray
|
||||
#define Rtl819XRadioA_1TArray Rtl8192CERadioA_1TArray
|
||||
#define Rtl819XRadioB_2TArray Rtl8192CERadioB_2TArray
|
||||
#define Rtl819XRadioB_1TArray Rtl8192CERadioB_1TArray
|
||||
#define Rtl819XPHY_REG_Array_PG Rtl8192CEPHY_REG_Array_PG
|
||||
#define Rtl819XPHY_REG_Array_MP Rtl8192CEPHY_REG_Array_MP
|
||||
|
||||
#define PHY_REG_2TArrayLength Rtl8192CEPHY_REG_2TArrayLength
|
||||
#define PHY_REG_1TArrayLength Rtl8192CEPHY_REG_1TArrayLength
|
||||
#define PHY_ChangeTo_1T1RArrayLength Rtl8192CEPHY_ChangeTo_1T1RArrayLength
|
||||
#define PHY_ChangeTo_1T2RArrayLength Rtl8192CEPHY_ChangeTo_1T2RArrayLength
|
||||
#define PHY_ChangeTo_2T2RArrayLength Rtl8192CEPHY_ChangeTo_2T2RArrayLength
|
||||
#define PHY_REG_Array_PGLength Rtl8192CEPHY_REG_Array_PGLength
|
||||
//#define PHY_REG_Array_PG_mCardLength Rtl8192CEPHY_REG_Array_PG_mCardLength
|
||||
#define PHY_REG_Array_MPLength Rtl8192CEPHY_REG_Array_MPLength
|
||||
#define PHY_REG_Array_MPLength Rtl8192CEPHY_REG_Array_MPLength
|
||||
//#define PHY_REG_1T_mCardArrayLength Rtl8192CEPHY_REG_1T_mCardArrayLength
|
||||
//#define PHY_REG_2T_mCardArrayLength Rtl8192CEPHY_REG_2T_mCardArrayLength
|
||||
//#define PHY_REG_Array_PG_HPLength Rtl8192CEPHY_REG_Array_PG_HPLength
|
||||
#define RadioA_2TArrayLength Rtl8192CERadioA_2TArrayLength
|
||||
#define RadioB_2TArrayLength Rtl8192CERadioB_2TArrayLength
|
||||
#define RadioA_1TArrayLength Rtl8192CERadioA_1TArrayLength
|
||||
#define RadioB_1TArrayLength Rtl8192CERadioB_1TArrayLength
|
||||
//#define RadioA_1T_mCardArrayLength Rtl8192CERadioA_1T_mCardArrayLength
|
||||
//#define RadioB_1T_mCardArrayLength Rtl8192CERadioB_1T_mCardArrayLength
|
||||
//#define RadioA_1T_HPArrayLength Rtl8192CERadioA_1T_HPArrayLength
|
||||
#define RadioB_GM_ArrayLength Rtl8192CERadioB_GM_ArrayLength
|
||||
#define MAC_2T_ArrayLength Rtl8192CEMAC_2T_ArrayLength
|
||||
#define MACPHY_Array_PGLength Rtl8192CEMACPHY_Array_PGLength
|
||||
#define AGCTAB_2TArrayLength Rtl8192CEAGCTAB_2TArrayLength
|
||||
#define AGCTAB_1TArrayLength Rtl8192CEAGCTAB_1TArrayLength
|
||||
//#define AGCTAB_1T_HPArrayLength Rtl8192CEAGCTAB_1T_HPArrayLength
|
||||
|
||||
#elif defined(CONFIG_USB_HCI)
|
||||
|
||||
|
||||
//2TODO: We should define 8192S firmware related macro settings here!!
|
||||
#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
|
||||
#define RTL819X_TOTAL_RF_PATH 2
|
||||
|
||||
//TODO: The following need to check!!
|
||||
#define RTL8192C_FW_TSMC_IMG "rtl8192CU\\rtl8192cfwT.bin"
|
||||
#define RTL8192C_FW_UMC_IMG "rtl8192CU\\rtl8192cfwU.bin"
|
||||
#define RTL8192C_FW_UMC_B_IMG "rtl8192CU\\rtl8192cfwU_B.bin"
|
||||
|
||||
//#define RTL819X_FW_BOOT_IMG "rtl8192CU\\boot.img"
|
||||
//#define RTL819X_FW_MAIN_IMG "rtl8192CU\\main.img"
|
||||
//#define RTL819X_FW_DATA_IMG "rtl8192CU\\data.img"
|
||||
|
||||
#define RTL8188C_PHY_REG "rtl8188CU\\PHY_REG.txt"
|
||||
#define RTL8188C_PHY_RADIO_A "rtl8188CU\\radio_a.txt"
|
||||
#define RTL8188C_PHY_RADIO_B "rtl8188CU\\radio_b.txt"
|
||||
#define RTL8188C_PHY_RADIO_A_mCard "rtl8192CU\\radio_a_1T_mCard.txt"
|
||||
#define RTL8188C_PHY_RADIO_B_mCard "rtl8192CU\\radio_b_1T_mCard.txt"
|
||||
#define RTL8188C_PHY_RADIO_A_HP "rtl8192CU\\radio_a_1T_HP.txt"
|
||||
#define RTL8188C_AGC_TAB "rtl8188CU\\AGC_TAB.txt"
|
||||
#define RTL8188C_PHY_MACREG "rtl8188CU\\MACREG.txt"
|
||||
|
||||
#define RTL8192C_PHY_REG "rtl8192CU\\PHY_REG.txt"
|
||||
#define RTL8192C_PHY_RADIO_A "rtl8192CU\\radio_a.txt"
|
||||
#define RTL8192C_PHY_RADIO_B "rtl8192CU\\radio_b.txt"
|
||||
#define RTL8192C_AGC_TAB "rtl8192CU\\AGC_TAB.txt"
|
||||
#define RTL8192C_PHY_MACREG "rtl8192CU\\MACREG.txt"
|
||||
|
||||
#define RTL819X_PHY_REG_PG "rtl8192CU\\PHY_REG_PG.txt"
|
||||
|
||||
//---------------------------------------------------------------------
|
||||
// RTL8723U From file
|
||||
//---------------------------------------------------------------------
|
||||
|
||||
// The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24.
|
||||
#define Rtl819XFwImageArray Rtl8192CUFwTSMCImgArray
|
||||
#define Rtl819XFwTSMCImageArray Rtl8192CUFwTSMCImgArray
|
||||
#define Rtl819XFwUMCACutImageArray Rtl8192CUFwUMCACutImgArray
|
||||
#define Rtl819XFwUMCBCutImageArray Rtl8192CUFwUMCBCutImgArray
|
||||
|
||||
#define Rtl819XMAC_Array Rtl8192CUMAC_2T_Array
|
||||
#define Rtl819XAGCTAB_2TArray Rtl8192CUAGCTAB_2TArray
|
||||
#define Rtl819XAGCTAB_1TArray Rtl8192CUAGCTAB_1TArray
|
||||
#define Rtl819XAGCTAB_1T_HPArray Rtl8192CUAGCTAB_1T_HPArray
|
||||
#define Rtl819XPHY_REG_2TArray Rtl8192CUPHY_REG_2TArray
|
||||
#define Rtl819XPHY_REG_1TArray Rtl8192CUPHY_REG_1TArray
|
||||
#define Rtl819XPHY_REG_1T_mCardArray Rtl8192CUPHY_REG_1T_mCardArray
|
||||
#define Rtl819XPHY_REG_2T_mCardArray Rtl8192CUPHY_REG_2T_mCardArray
|
||||
#define Rtl819XPHY_REG_1T_HPArray Rtl8192CUPHY_REG_1T_HPArray
|
||||
#define Rtl819XRadioA_2TArray Rtl8192CURadioA_2TArray
|
||||
#define Rtl819XRadioA_1TArray Rtl8192CURadioA_1TArray
|
||||
#define Rtl819XRadioA_1T_mCardArray Rtl8192CURadioA_1T_mCardArray
|
||||
#define Rtl819XRadioB_2TArray Rtl8192CURadioB_2TArray
|
||||
#define Rtl819XRadioB_1TArray Rtl8192CURadioB_1TArray
|
||||
#define Rtl819XRadioB_1T_mCardArray Rtl8192CURadioB_1T_mCardArray
|
||||
#define Rtl819XRadioA_1T_HPArray Rtl8192CURadioA_1T_HPArray
|
||||
#define Rtl819XPHY_REG_Array_PG Rtl8192CUPHY_REG_Array_PG
|
||||
#define Rtl819XPHY_REG_Array_PG_mCard Rtl8192CUPHY_REG_Array_PG_mCard
|
||||
#define Rtl819XPHY_REG_Array_PG_HP Rtl8192CUPHY_REG_Array_PG_HP
|
||||
#define Rtl819XPHY_REG_Array_MP Rtl8192CUPHY_REG_Array_MP
|
||||
|
||||
#define PHY_REG_2TArrayLength Rtl8192CUPHY_REG_2TArrayLength
|
||||
#define PHY_REG_1TArrayLength Rtl8192CUPHY_REG_1TArrayLength
|
||||
#define PHY_ChangeTo_1T1RArrayLength Rtl8192CUPHY_ChangeTo_1T1RArrayLength
|
||||
#define PHY_ChangeTo_1T2RArrayLength Rtl8192CUPHY_ChangeTo_1T2RArrayLength
|
||||
#define PHY_ChangeTo_2T2RArrayLength Rtl8192CUPHY_ChangeTo_2T2RArrayLength
|
||||
#define PHY_REG_Array_PGLength Rtl8192CUPHY_REG_Array_PGLength
|
||||
#define PHY_REG_Array_PG_mCardLength Rtl8192CUPHY_REG_Array_PG_mCardLength
|
||||
#define PHY_REG_Array_MPLength Rtl8192CUPHY_REG_Array_MPLength
|
||||
#define PHY_REG_Array_MPLength Rtl8192CUPHY_REG_Array_MPLength
|
||||
#define PHY_REG_1T_mCardArrayLength Rtl8192CUPHY_REG_1T_mCardArrayLength
|
||||
#define PHY_REG_2T_mCardArrayLength Rtl8192CUPHY_REG_2T_mCardArrayLength
|
||||
#define PHY_REG_Array_PG_HPLength Rtl8192CUPHY_REG_Array_PG_HPLength
|
||||
#define RadioA_2TArrayLength Rtl8192CURadioA_2TArrayLength
|
||||
#define RadioB_2TArrayLength Rtl8192CURadioB_2TArrayLength
|
||||
#define RadioA_1TArrayLength Rtl8192CURadioA_1TArrayLength
|
||||
#define RadioB_1TArrayLength Rtl8192CURadioB_1TArrayLength
|
||||
#define RadioA_1T_mCardArrayLength Rtl8192CURadioA_1T_mCardArrayLength
|
||||
#define RadioB_1T_mCardArrayLength Rtl8192CURadioB_1T_mCardArrayLength
|
||||
#define RadioA_1T_HPArrayLength Rtl8192CURadioA_1T_HPArrayLength
|
||||
#define RadioB_GM_ArrayLength Rtl8192CURadioB_GM_ArrayLength
|
||||
#define MAC_2T_ArrayLength Rtl8192CUMAC_2T_ArrayLength
|
||||
#define MACPHY_Array_PGLength Rtl8192CUMACPHY_Array_PGLength
|
||||
#define AGCTAB_2TArrayLength Rtl8192CUAGCTAB_2TArrayLength
|
||||
#define AGCTAB_1TArrayLength Rtl8192CUAGCTAB_1TArrayLength
|
||||
#define AGCTAB_1T_HPArrayLength Rtl8192CUAGCTAB_1T_HPArrayLength
|
||||
#define PHY_REG_1T_HPArrayLength Rtl8192CUPHY_REG_1T_HPArrayLength
|
||||
|
||||
#endif
|
||||
|
||||
#define DRVINFO_SZ 4 // unit is 8bytes
|
||||
#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
|
||||
|
||||
#define FW_8192C_SIZE 16384+32//16k
|
||||
#define FW_8192C_START_ADDRESS 0x1000
|
||||
//#define FW_8192C_END_ADDRESS 0x3FFF //Filen said this is for test chip
|
||||
#define FW_8192C_END_ADDRESS 0x1FFF
|
||||
|
||||
#define MAX_PAGE_SIZE 4096 // @ page : 4k bytes
|
||||
|
||||
#define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
|
||||
(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\
|
||||
(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300)
|
||||
|
||||
typedef enum _FIRMWARE_SOURCE{
|
||||
FW_SOURCE_IMG_FILE = 0,
|
||||
FW_SOURCE_HEADER_FILE = 1, //from header file
|
||||
}FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;
|
||||
|
||||
typedef struct _RT_FIRMWARE{
|
||||
FIRMWARE_SOURCE eFWSource;
|
||||
u8* szFwBuffer;
|
||||
u32 ulFwLength;
|
||||
}RT_FIRMWARE, *PRT_FIRMWARE, RT_FIRMWARE_92C, *PRT_FIRMWARE_92C;
|
||||
|
||||
//
|
||||
// This structure must be cared byte-ordering
|
||||
//
|
||||
// Added by tynli. 2009.12.04.
|
||||
typedef struct _RT_8192C_FIRMWARE_HDR {//8-byte alinment required
|
||||
|
||||
//--- LONG WORD 0 ----
|
||||
u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut
|
||||
u8 Category; // AP/NIC and USB/PCI
|
||||
u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions
|
||||
u16 Version; // FW Version
|
||||
u8 Subversion; // FW Subversion, default 0x00
|
||||
u16 Rsvd1;
|
||||
|
||||
|
||||
//--- LONG WORD 1 ----
|
||||
u8 Month; // Release time Month field
|
||||
u8 Date; // Release time Date field
|
||||
u8 Hour; // Release time Hour field
|
||||
u8 Minute; // Release time Minute field
|
||||
u16 RamCodeSize; // The size of RAM code
|
||||
u16 Rsvd2;
|
||||
|
||||
//--- LONG WORD 2 ----
|
||||
u32 SvnIdx; // The SVN entry index
|
||||
u32 Rsvd3;
|
||||
|
||||
//--- LONG WORD 3 ----
|
||||
u32 Rsvd4;
|
||||
u32 Rsvd5;
|
||||
|
||||
}RT_8192C_FIRMWARE_HDR, *PRT_8192C_FIRMWARE_HDR;
|
||||
|
||||
#define DRIVER_EARLY_INT_TIME 0x05
|
||||
#define BCN_DMA_ATIME_INT_TIME 0x02
|
||||
|
||||
#ifdef CONFIG_USB_RX_AGGREGATION
|
||||
|
||||
typedef enum _USB_RX_AGG_MODE{
|
||||
USB_RX_AGG_DISABLE,
|
||||
USB_RX_AGG_DMA,
|
||||
USB_RX_AGG_USB,
|
||||
USB_RX_AGG_MIX
|
||||
}USB_RX_AGG_MODE;
|
||||
|
||||
#define MAX_RX_DMA_BUFFER_SIZE 10240 // 10K for 8192C RX DMA buffer
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#define TX_SELE_HQ BIT(0) // High Queue
|
||||
#define TX_SELE_LQ BIT(1) // Low Queue
|
||||
#define TX_SELE_NQ BIT(2) // Normal Queue
|
||||
|
||||
|
||||
// Note: We will divide number of page equally for each queue other than public queue!
|
||||
|
||||
#define TX_TOTAL_PAGE_NUMBER 0xF8
|
||||
#define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER + 1)
|
||||
|
||||
// For Normal Chip Setting
|
||||
// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER
|
||||
#define NORMAL_PAGE_NUM_PUBQ 0xE7
|
||||
#define NORMAL_PAGE_NUM_HPQ 0x0C
|
||||
#define NORMAL_PAGE_NUM_LPQ 0x02
|
||||
#define NORMAL_PAGE_NUM_NPQ 0x02
|
||||
|
||||
|
||||
// For Test Chip Setting
|
||||
// (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER
|
||||
#define TEST_PAGE_NUM_PUBQ 0x7E
|
||||
|
||||
|
||||
// For Test Chip Setting
|
||||
#define WMM_TEST_TX_TOTAL_PAGE_NUMBER 0xF5
|
||||
#define WMM_TEST_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
|
||||
|
||||
#define WMM_TEST_PAGE_NUM_PUBQ 0xA3
|
||||
#define WMM_TEST_PAGE_NUM_HPQ 0x29
|
||||
#define WMM_TEST_PAGE_NUM_LPQ 0x29
|
||||
|
||||
|
||||
//Note: For Normal Chip Setting ,modify later
|
||||
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5
|
||||
#define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
|
||||
|
||||
#define WMM_NORMAL_PAGE_NUM_PUBQ 0xB0
|
||||
#define WMM_NORMAL_PAGE_NUM_HPQ 0x29
|
||||
#define WMM_NORMAL_PAGE_NUM_LPQ 0x1C
|
||||
#define WMM_NORMAL_PAGE_NUM_NPQ 0x1C
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// Chip specific
|
||||
//-------------------------------------------------------------------------
|
||||
#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
|
||||
#define CHIP_BONDING_92C_1T2R 0x1
|
||||
#define CHIP_BONDING_88C_USB_MCARD 0x2
|
||||
#define CHIP_BONDING_88C_USB_HP 0x1
|
||||
|
||||
#include "HalVerDef.h"
|
||||
#include "hal_com.h"
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// Channel Plan
|
||||
//-------------------------------------------------------------------------
|
||||
enum ChannelPlan{
|
||||
CHPL_FCC = 0,
|
||||
CHPL_IC = 1,
|
||||
CHPL_ETSI = 2,
|
||||
CHPL_SPA = 3,
|
||||
CHPL_FRANCE = 4,
|
||||
CHPL_MKK = 5,
|
||||
CHPL_MKK1 = 6,
|
||||
CHPL_ISRAEL = 7,
|
||||
CHPL_TELEC = 8,
|
||||
CHPL_GLOBAL = 9,
|
||||
CHPL_WORLD = 10,
|
||||
};
|
||||
|
||||
typedef struct _TxPowerInfo{
|
||||
u8 CCKIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX];
|
||||
u8 HT40_1SIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX];
|
||||
u8 HT40_2SIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX];
|
||||
u8 HT20IndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX];
|
||||
u8 OFDMIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX];
|
||||
u8 HT40MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX];
|
||||
u8 HT20MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX];
|
||||
u8 TSSI_A;
|
||||
u8 TSSI_B;
|
||||
}TxPowerInfo, *PTxPowerInfo;
|
||||
|
||||
#define EFUSE_REAL_CONTENT_LEN 512
|
||||
#define EFUSE_MAP_LEN 128
|
||||
#define EFUSE_MAX_SECTION 16
|
||||
#define EFUSE_IC_ID_OFFSET 506 //For some inferiority IC purpose. added by Roger, 2009.09.02.
|
||||
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN)
|
||||
//
|
||||
// <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
|
||||
// 9bytes + 1byt + 5bytes and pre 1byte.
|
||||
// For worst case:
|
||||
// | 1byte|----8bytes----|1byte|--5bytes--|
|
||||
// | | Reserved(14bytes) |
|
||||
//
|
||||
#define EFUSE_OOB_PROTECT_BYTES 15 // PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte.
|
||||
|
||||
|
||||
#define EFUSE_MAP_LEN_8723 256
|
||||
#define EFUSE_MAX_SECTION_8723 32
|
||||
|
||||
//========================================================
|
||||
// EFUSE for BT definition
|
||||
//========================================================
|
||||
#define EFUSE_BT_REAL_CONTENT_LEN 1536 // 512*3
|
||||
#define EFUSE_BT_MAP_LEN 1024 // 1k bytes
|
||||
#define EFUSE_BT_MAX_SECTION 128 // 1024/8
|
||||
|
||||
#define EFUSE_PROTECT_BYTES_BANK 16
|
||||
|
||||
//
|
||||
// <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06.
|
||||
//
|
||||
typedef enum _RT_MULTI_FUNC{
|
||||
RT_MULTI_FUNC_NONE = 0x00,
|
||||
RT_MULTI_FUNC_WIFI = 0x01,
|
||||
RT_MULTI_FUNC_BT = 0x02,
|
||||
RT_MULTI_FUNC_GPS = 0x04,
|
||||
}RT_MULTI_FUNC,*PRT_MULTI_FUNC;
|
||||
|
||||
//
|
||||
// <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08.
|
||||
//
|
||||
typedef enum _RT_POLARITY_CTL{
|
||||
RT_POLARITY_LOW_ACT = 0,
|
||||
RT_POLARITY_HIGH_ACT = 1,
|
||||
}RT_POLARITY_CTL,*PRT_POLARITY_CTL;
|
||||
|
||||
// For RTL8723 regulator mode. by tynli. 2011.01.14.
|
||||
typedef enum _RT_REGULATOR_MODE{
|
||||
RT_SWITCHING_REGULATOR = 0,
|
||||
RT_LDO_REGULATOR = 1,
|
||||
}RT_REGULATOR_MODE,*PRT_REGULATOR_MODE;
|
||||
|
||||
enum c2h_id_8192c {
|
||||
C2H_DBG = 0,
|
||||
C2H_TSF = 1,
|
||||
C2H_AP_RPT_RSP = 2,
|
||||
C2H_CCX_TX_RPT = 3,
|
||||
C2H_BT_RSSI = 4,
|
||||
C2H_BT_OP_MODE = 5,
|
||||
C2H_EXT_RA_RPT = 6,
|
||||
C2H_HW_INFO_EXCH = 10,
|
||||
C2H_C2H_H2C_TEST = 11,
|
||||
C2H_BT_INFO = 12,
|
||||
C2H_BT_MP_INFO = 15,
|
||||
MAX_C2HEVENT
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
struct hal_data_8192ce
|
||||
{
|
||||
HAL_VERSION VersionID;
|
||||
RT_MULTI_FUNC MultiFunc; // For multi-function consideration.
|
||||
RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control.
|
||||
RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO
|
||||
u16 CustomerID;
|
||||
|
||||
u16 FirmwareVersion;
|
||||
u16 FirmwareVersionRev;
|
||||
u16 FirmwareSubVersion;
|
||||
|
||||
u32 IntrMask[2];
|
||||
u32 IntrMaskToSet[2];
|
||||
|
||||
u32 DisabledFunctions;
|
||||
|
||||
//current WIFI_PHY values
|
||||
u32 ReceiveConfig;
|
||||
u32 TransmitConfig;
|
||||
WIRELESS_MODE CurrentWirelessMode;
|
||||
HT_CHANNEL_WIDTH CurrentChannelBW;
|
||||
u8 CurrentChannel;
|
||||
u8 nCur40MhzPrimeSC;// Control channel sub-carrier
|
||||
|
||||
u16 BasicRateSet;
|
||||
|
||||
//rf_ctrl
|
||||
_lock rf_lock;
|
||||
u8 rf_chip;
|
||||
u8 rf_type;
|
||||
u8 NumTotalRFPath;
|
||||
|
||||
INTERFACE_SELECT_8192CPCIe InterfaceSel;
|
||||
|
||||
//
|
||||
// EEPROM setting.
|
||||
//
|
||||
u16 EEPROMVID;
|
||||
u16 EEPROMDID;
|
||||
u16 EEPROMSVID;
|
||||
u16 EEPROMSMID;
|
||||
u16 EEPROMChannelPlan;
|
||||
u16 EEPROMVersion;
|
||||
|
||||
u8 EEPROMChnlAreaTxPwrCCK[2][3];
|
||||
u8 EEPROMChnlAreaTxPwrHT40_1S[2][3];
|
||||
u8 EEPROMChnlAreaTxPwrHT40_2SDiff[2][3];
|
||||
u8 EEPROMPwrLimitHT20[3];
|
||||
u8 EEPROMPwrLimitHT40[3];
|
||||
|
||||
u8 bTXPowerDataReadFromEEPORM;
|
||||
u8 EEPROMThermalMeter;
|
||||
u8 EEPROMTSSI[2];
|
||||
|
||||
u8 EEPROMCustomerID;
|
||||
u8 EEPROMBoardType;
|
||||
u8 EEPROMRegulatory;
|
||||
|
||||
u8 bDefaultAntenna;
|
||||
u8 bIQKInitialized;
|
||||
|
||||
u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
|
||||
u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
|
||||
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
|
||||
u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
|
||||
u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
|
||||
// For power group
|
||||
u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
|
||||
u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
|
||||
|
||||
u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff
|
||||
|
||||
bool EepromOrEfuse;
|
||||
u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes)
|
||||
u8 EfuseUsedPercentage;
|
||||
EFUSE_HAL EfuseHal;
|
||||
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
struct btcoexist_priv bt_coexist;
|
||||
#endif
|
||||
|
||||
// Read/write are allow for following hardware information variables
|
||||
u8 framesync;
|
||||
u32 framesyncC34;
|
||||
u8 framesyncMonitor;
|
||||
u8 DefaultInitialGain[4];
|
||||
u8 pwrGroupCnt;
|
||||
u32 MCSTxPowerLevelOriginalOffset[7][16];
|
||||
u32 CCKTxPowerLevelOriginalOffset;
|
||||
|
||||
u32 AntennaTxPath; // Antenna path Tx
|
||||
u32 AntennaRxPath; // Antenna path Rx
|
||||
u8 BluetoothCoexist;
|
||||
u8 ExternalPA;
|
||||
|
||||
//u32 LedControlNum;
|
||||
//u32 LedControlMode;
|
||||
u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
|
||||
//u32 TxPowerTrackControl;
|
||||
u8 b1x1RecvCombine; // for 1T1R receive combining
|
||||
|
||||
u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo.
|
||||
|
||||
//vivi, for tx power tracking, 20080407
|
||||
//u16 TSSI_13dBm;
|
||||
//u32 Pwr_Track;
|
||||
// The current Tx Power Level
|
||||
u8 CurrentCckTxPwrIdx;
|
||||
u8 CurrentOfdm24GTxPwrIdx;
|
||||
|
||||
BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
|
||||
|
||||
u32 RfRegChnlVal[2];
|
||||
|
||||
//RDG enable
|
||||
bool bRDGEnable;
|
||||
|
||||
//for host message to fw
|
||||
u8 LastHMEBoxNum;
|
||||
|
||||
u8 fw_ractrl;
|
||||
u8 RegTxPause;
|
||||
// Beacon function related global variable.
|
||||
u32 RegBcnCtrlVal;
|
||||
u8 RegFwHwTxQCtrl;
|
||||
u8 RegReg542;
|
||||
u8 CurAntenna;
|
||||
|
||||
//### ODM-DUPLICATE CODE ###
|
||||
u8 AntDivCfg;
|
||||
/*
|
||||
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
|
||||
//SW Antenna Switch
|
||||
s32 RSSI_sum_A;
|
||||
s32 RSSI_sum_B;
|
||||
s32 RSSI_cnt_A;
|
||||
s32 RSSI_cnt_B;
|
||||
bool RSSI_test;
|
||||
#endif
|
||||
#ifdef CONFIG_HW_ANTENNA_DIVERSITY
|
||||
//Hybrid Antenna Diversity
|
||||
u32 CCK_Ant1_Cnt;
|
||||
u32 CCK_Ant2_Cnt;
|
||||
u32 OFDM_Ant1_Cnt;
|
||||
u32 OFDM_Ant2_Cnt;
|
||||
#endif
|
||||
*/
|
||||
//### ODM-DUPLICATE CODE ###
|
||||
struct dm_priv dmpriv;
|
||||
DM_ODM_T odmpriv;
|
||||
//_lock odm_stainfo_lock;
|
||||
u8 bDumpRxPkt;//for debug
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
struct sreset_priv srestpriv;
|
||||
#endif
|
||||
u8 bInterruptMigration;
|
||||
u8 bDisableTxInt;
|
||||
u8 bGpioHwWpsPbc;
|
||||
|
||||
u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
|
||||
|
||||
u16 EfuseUsedBytes;
|
||||
|
||||
#ifdef CONFIG_P2P
|
||||
struct P2P_PS_Offload_t p2p_ps_offload;
|
||||
#endif //CONFIG_P2P
|
||||
};
|
||||
|
||||
typedef struct hal_data_8192ce HAL_DATA_TYPE, *PHAL_DATA_TYPE;
|
||||
|
||||
//
|
||||
// Function disabled.
|
||||
//
|
||||
#define DF_TX_BIT BIT0
|
||||
#define DF_RX_BIT BIT1
|
||||
#define DF_IO_BIT BIT2
|
||||
#define DF_IO_D3_BIT BIT3
|
||||
|
||||
#define RT_DF_TYPE u32
|
||||
#define RT_DISABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions |= ((RT_DF_TYPE)(__FuncBits)))
|
||||
#define RT_ENABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions &= (~((RT_DF_TYPE)(__FuncBits))))
|
||||
#define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) )
|
||||
#define IS_MULTI_FUNC_CHIP(_Adapter) (((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? true : false)
|
||||
|
||||
void InterruptRecognized8192CE(PADAPTER Adapter, PRT_ISR_CONTENT pIsrContent);
|
||||
void UpdateInterruptMask8192CE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
struct hal_data_8192cu
|
||||
{
|
||||
HAL_VERSION VersionID;
|
||||
RT_MULTI_FUNC MultiFunc; // For multi-function consideration.
|
||||
RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control.
|
||||
RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO
|
||||
u16 CustomerID;
|
||||
|
||||
u16 FirmwareVersion;
|
||||
u16 FirmwareVersionRev;
|
||||
u16 FirmwareSubVersion;
|
||||
|
||||
//current WIFI_PHY values
|
||||
u32 ReceiveConfig;
|
||||
WIRELESS_MODE CurrentWirelessMode;
|
||||
HT_CHANNEL_WIDTH CurrentChannelBW;
|
||||
u8 CurrentChannel;
|
||||
u8 nCur40MhzPrimeSC;// Control channel sub-carrier
|
||||
|
||||
u16 BasicRateSet;
|
||||
|
||||
//rf_ctrl
|
||||
u8 rf_chip;
|
||||
u8 rf_type;
|
||||
u8 NumTotalRFPath;
|
||||
|
||||
u8 BoardType;
|
||||
//INTERFACE_SELECT_8192CUSB InterfaceSel;
|
||||
|
||||
//
|
||||
// EEPROM setting.
|
||||
//
|
||||
u16 EEPROMVID;
|
||||
u16 EEPROMPID;
|
||||
u16 EEPROMSVID;
|
||||
u16 EEPROMSDID;
|
||||
u8 EEPROMCustomerID;
|
||||
u8 EEPROMSubCustomerID;
|
||||
u8 EEPROMVersion;
|
||||
u8 EEPROMRegulatory;
|
||||
|
||||
u8 bTXPowerDataReadFromEEPORM;
|
||||
u8 EEPROMThermalMeter;
|
||||
|
||||
u8 bIQKInitialized;
|
||||
|
||||
u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
|
||||
u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
|
||||
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
|
||||
s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
|
||||
u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
|
||||
// For power group
|
||||
u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
|
||||
u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
|
||||
|
||||
u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff
|
||||
|
||||
// Read/write are allow for following hardware information variables
|
||||
u8 framesync;
|
||||
u32 framesyncC34;
|
||||
u8 framesyncMonitor;
|
||||
u8 DefaultInitialGain[4];
|
||||
u8 pwrGroupCnt;
|
||||
u32 MCSTxPowerLevelOriginalOffset[7][16];
|
||||
u32 CCKTxPowerLevelOriginalOffset;
|
||||
|
||||
u32 AntennaTxPath; // Antenna path Tx
|
||||
u32 AntennaRxPath; // Antenna path Rx
|
||||
u8 BluetoothCoexist;
|
||||
u8 ExternalPA;
|
||||
|
||||
u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
|
||||
|
||||
//u32 LedControlNum;
|
||||
//u32 LedControlMode;
|
||||
//u32 TxPowerTrackControl;
|
||||
u8 b1x1RecvCombine; // for 1T1R receive combining
|
||||
|
||||
u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo.
|
||||
|
||||
//vivi, for tx power tracking, 20080407
|
||||
//u16 TSSI_13dBm;
|
||||
//u32 Pwr_Track;
|
||||
// The current Tx Power Level
|
||||
u8 CurrentCckTxPwrIdx;
|
||||
u8 CurrentOfdm24GTxPwrIdx;
|
||||
|
||||
BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
|
||||
|
||||
u32 RfRegChnlVal[2];
|
||||
|
||||
//RDG enable
|
||||
bool bRDGEnable;
|
||||
|
||||
//for host message to fw
|
||||
u8 LastHMEBoxNum;
|
||||
|
||||
u8 fw_ractrl;
|
||||
u8 RegTxPause;
|
||||
// Beacon function related global variable.
|
||||
u32 RegBcnCtrlVal;
|
||||
u8 RegFwHwTxQCtrl;
|
||||
u8 RegReg542;
|
||||
|
||||
struct dm_priv dmpriv;
|
||||
DM_ODM_T odmpriv;
|
||||
//_lock odm_stainfo_lock;
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
struct sreset_priv srestpriv;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
struct btcoexist_priv bt_coexist;
|
||||
#endif
|
||||
u8 CurAntenna;
|
||||
|
||||
/*****ODM duplicate data********/
|
||||
u8 AntDivCfg;
|
||||
/*
|
||||
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
|
||||
|
||||
//SW Antenna Switch
|
||||
s32 RSSI_sum_A;
|
||||
s32 RSSI_sum_B;
|
||||
s32 RSSI_cnt_A;
|
||||
s32 RSSI_cnt_B;
|
||||
bool RSSI_test;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HW_ANTENNA_DIVERSITY
|
||||
//Hybrid Antenna Diversity
|
||||
u32 CCK_Ant1_Cnt;
|
||||
u32 CCK_Ant2_Cnt;
|
||||
u32 OFDM_Ant1_Cnt;
|
||||
u32 OFDM_Ant2_Cnt;
|
||||
#endif
|
||||
*/
|
||||
u8 bDumpRxPkt;//for debug
|
||||
u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
|
||||
|
||||
// 2010/08/09 MH Add CU power down mode.
|
||||
bool pwrdown;
|
||||
|
||||
// For 92C USB endpoint setting
|
||||
//
|
||||
|
||||
u32 UsbBulkOutSize;
|
||||
|
||||
// Add for dual MAC 0--Mac0 1--Mac1
|
||||
u32 interfaceIndex;
|
||||
|
||||
u8 OutEpQueueSel;
|
||||
u8 OutEpNumber;
|
||||
|
||||
#ifdef CONFIG_USB_TX_AGGREGATION
|
||||
u8 UsbTxAggMode;
|
||||
u8 UsbTxAggDescNum;
|
||||
#endif
|
||||
#ifdef CONFIG_USB_RX_AGGREGATION
|
||||
u16 HwRxPageSize; // Hardware setting
|
||||
u32 MaxUsbRxAggBlock;
|
||||
|
||||
USB_RX_AGG_MODE UsbRxAggMode;
|
||||
u8 UsbRxAggBlockCount; // USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed
|
||||
u8 UsbRxAggBlockTimeout;
|
||||
u8 UsbRxAggPageCount; // 8192C DMA page count
|
||||
u8 UsbRxAggPageTimeout;
|
||||
#endif
|
||||
|
||||
// 2010/12/10 MH Add for USB aggreation mode dynamic shceme.
|
||||
bool UsbRxHighSpeedMode;
|
||||
|
||||
// 2010/11/22 MH Add for slim combo debug mode selective.
|
||||
// This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock.
|
||||
bool SlimComboDbg;
|
||||
|
||||
u16 EfuseUsedBytes;
|
||||
|
||||
bool EepromOrEfuse;
|
||||
u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes)
|
||||
u8 EfuseUsedPercentage;
|
||||
EFUSE_HAL EfuseHal;
|
||||
|
||||
|
||||
#ifdef CONFIG_P2P
|
||||
struct P2P_PS_Offload_t p2p_ps_offload;
|
||||
#endif //CONFIG_P2P
|
||||
};
|
||||
|
||||
typedef struct hal_data_8192cu HAL_DATA_TYPE, *PHAL_DATA_TYPE;
|
||||
#endif
|
||||
|
||||
#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData))
|
||||
#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type)
|
||||
|
||||
#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
|
||||
#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
|
||||
|
||||
void rtl8192c_FirmwareSelfReset(IN PADAPTER Adapter);
|
||||
int FirmwareDownload92C(IN PADAPTER Adapter);
|
||||
void InitializeFirmwareVars92C(PADAPTER Adapter);
|
||||
u8 GetEEPROMSize8192C(PADAPTER Adapter);
|
||||
void rtl8192c_EfuseParseChnlPlan(PADAPTER padapter, u8 *hwinfo, bool AutoLoadFail);
|
||||
|
||||
HAL_VERSION rtl8192c_ReadChipVersion(IN PADAPTER Adapter);
|
||||
void rtl8192c_ReadBluetoothCoexistInfo(PADAPTER Adapter, u8 *PROMContent, bool AutoloadFail);
|
||||
//void rtl8192c_free_hal_data(_adapter * padapter);
|
||||
void rtl8192c_EfuseParseIDCode(PADAPTER pAdapter, u8 *hwinfo);
|
||||
void rtl8192c_set_hal_ops(struct hal_ops *pHalFunc);
|
||||
void rtl8192c_clone_haldata(_adapter* dst_adapter, _adapter* src_adapter);
|
||||
|
||||
s32 c2h_id_filter_ccx_8192c(u8 id);
|
||||
#endif
|
|
@ -1,41 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __RTL8192C_LED_H_
|
||||
#define __RTL8192C_LED_H_
|
||||
|
||||
#include <drv_conf.h>
|
||||
#include <osdep_service.h>
|
||||
#include <drv_types.h>
|
||||
|
||||
|
||||
//================================================================================
|
||||
// Interface to manipulate LED objects.
|
||||
//================================================================================
|
||||
#ifdef CONFIG_USB_HCI
|
||||
void rtl8192cu_InitSwLeds(_adapter *padapter);
|
||||
void rtl8192cu_DeInitSwLeds(_adapter *padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
void rtl8192ce_gen_RefreshLedState(PADAPTER Adapter);
|
||||
void rtl8192ce_InitSwLeds(_adapter *padapter);
|
||||
void rtl8192ce_DeInitSwLeds(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#endif
|
|
@ -1,142 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef _RTL8192C_RECV_H_
|
||||
#define _RTL8192C_RECV_H_
|
||||
|
||||
#include <drv_conf.h>
|
||||
#include <osdep_service.h>
|
||||
#include <drv_types.h>
|
||||
|
||||
|
||||
#ifdef PLATFORM_OS_XP
|
||||
#define NR_RECVBUFF (16)
|
||||
#elif defined(PLATFORM_OS_CE)
|
||||
#define NR_RECVBUFF (4)
|
||||
#else
|
||||
|
||||
#if defined(CONFIG_GSPI_HCI)
|
||||
#define NR_RECVBUFF (32)
|
||||
#elif defined(CONFIG_SDIO_HCI)
|
||||
#define NR_RECVBUFF (8)
|
||||
#else
|
||||
#ifdef CONFIG_SINGLE_RECV_BUF
|
||||
#define NR_RECVBUFF (1)
|
||||
#else
|
||||
#define NR_RECVBUFF (4)
|
||||
#endif //CONFIG_SINGLE_RECV_BUF
|
||||
#endif
|
||||
|
||||
#define NR_PREALLOC_RECV_SKB (8)
|
||||
#endif
|
||||
|
||||
|
||||
#define RECV_BLK_SZ 512
|
||||
#define RECV_BLK_CNT 16
|
||||
#define RECV_BLK_TH RECV_BLK_CNT
|
||||
|
||||
#if defined(CONFIG_USB_HCI)
|
||||
|
||||
#ifdef PLATFORM_OS_CE
|
||||
#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k
|
||||
#else
|
||||
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
|
||||
//#define MAX_RECVBUF_SZ (32768) // 32k
|
||||
//#define MAX_RECVBUF_SZ (16384) //16K
|
||||
//#define MAX_RECVBUF_SZ (10240) //10K
|
||||
#define MAX_RECVBUF_SZ (15360) // 15k < 16k
|
||||
//#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k
|
||||
#else
|
||||
#define MAX_RECVBUF_SZ (4000) // about 4K
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#elif defined(CONFIG_PCI_HCI)
|
||||
//#ifndef CONFIG_MINIMAL_MEMORY_USAGE
|
||||
// #define MAX_RECVBUF_SZ (9100)
|
||||
//#else
|
||||
#define MAX_RECVBUF_SZ (4000) // about 4K
|
||||
//#endif
|
||||
|
||||
#define RX_MPDU_QUEUE 0
|
||||
#define RX_CMD_QUEUE 1
|
||||
#define RX_MAX_QUEUE 2
|
||||
|
||||
#elif defined(CONFIG_SDIO_HCI)
|
||||
|
||||
#define MAX_RECVBUF_SZ (10240)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#define RECV_BULK_IN_ADDR 0x80
|
||||
#define RECV_INT_IN_ADDR 0x81
|
||||
|
||||
#define PHY_RSSI_SLID_WIN_MAX 100
|
||||
#define PHY_LINKQUALITY_SLID_WIN_MAX 20
|
||||
|
||||
|
||||
struct phy_stat
|
||||
{
|
||||
unsigned int phydw0;
|
||||
|
||||
unsigned int phydw1;
|
||||
|
||||
unsigned int phydw2;
|
||||
|
||||
unsigned int phydw3;
|
||||
|
||||
unsigned int phydw4;
|
||||
|
||||
unsigned int phydw5;
|
||||
|
||||
unsigned int phydw6;
|
||||
|
||||
unsigned int phydw7;
|
||||
};
|
||||
|
||||
// Rx smooth factor
|
||||
#define Rx_Smooth_Factor (20)
|
||||
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
typedef struct _INTERRUPT_MSG_FORMAT_EX{
|
||||
unsigned int C2H_MSG0;
|
||||
unsigned int C2H_MSG1;
|
||||
unsigned int C2H_MSG2;
|
||||
unsigned int C2H_MSG3;
|
||||
unsigned int HISR; // from HISR Reg0x124, read to clear
|
||||
unsigned int HISRE;// from HISRE Reg0x12c, read to clear
|
||||
unsigned int MSG_EX;
|
||||
}INTERRUPT_MSG_FORMAT_EX,*PINTERRUPT_MSG_FORMAT_EX;
|
||||
|
||||
void rtl8192cu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
|
||||
int rtl8192cu_init_recv_priv(_adapter * padapter);
|
||||
void rtl8192cu_free_recv_priv(_adapter * padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
int rtl8192ce_init_recv_priv(_adapter * padapter);
|
||||
void rtl8192ce_free_recv_priv(_adapter * padapter);
|
||||
#endif
|
||||
|
||||
void rtl8192c_translate_rx_signal_stuff(union recv_frame *precvframe, struct phy_stat *pphy_status);
|
||||
void rtl8192c_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *pdesc);
|
||||
|
||||
#endif
|
|
@ -1,91 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
*
|
||||
*
|
||||
* Module: rtl8192c_rf.h ( Header File)
|
||||
*
|
||||
* Note: Collect every HAL RF type exter API or constant.
|
||||
*
|
||||
* Function:
|
||||
*
|
||||
* Export:
|
||||
*
|
||||
* Abbrev:
|
||||
*
|
||||
* History:
|
||||
* Data Who Remark
|
||||
*
|
||||
* 09/25/2008 MHC Create initial version.
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef _RTL8192C_RF_H_
|
||||
#define _RTL8192C_RF_H_
|
||||
/* Check to see if the file has been included already. */
|
||||
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
|
||||
//
|
||||
// For RF 6052 Series
|
||||
//
|
||||
#define RF6052_MAX_TX_PWR 0x3F
|
||||
#define RF6052_MAX_REG 0x3F
|
||||
#define RF6052_MAX_PATH 2
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
|
||||
|
||||
/*------------------------------Define structure----------------------------*/
|
||||
|
||||
/*------------------------------Define structure----------------------------*/
|
||||
|
||||
|
||||
/*------------------------Export global variable----------------------------*/
|
||||
/*------------------------Export global variable----------------------------*/
|
||||
|
||||
/*------------------------Export Marco Definition---------------------------*/
|
||||
|
||||
/*------------------------Export Marco Definition---------------------------*/
|
||||
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
|
||||
//
|
||||
// RF RL6052 Series API
|
||||
//
|
||||
void rtl8192c_RF_ChangeTxPath( PADAPTER Adapter,
|
||||
u16 DataRate);
|
||||
void rtl8192c_PHY_RF6052SetBandwidth(
|
||||
PADAPTER Adapter,
|
||||
HT_CHANNEL_WIDTH Bandwidth);
|
||||
void rtl8192c_PHY_RF6052SetCckTxPower(
|
||||
PADAPTER Adapter,
|
||||
u8* pPowerlevel);
|
||||
void rtl8192c_PHY_RF6052SetOFDMTxPower(
|
||||
PADAPTER Adapter,
|
||||
u8* pPowerLevel,
|
||||
u8 Channel);
|
||||
int PHY_RF6052_Config8192C( PADAPTER Adapter );
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
|
||||
|
||||
#endif/* End of HalRf.h */
|
File diff suppressed because it is too large
Load diff
|
@ -1,33 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef _RTL8192C_SRESET_C_
|
||||
#define _RTL8192C_SRESET_C_
|
||||
|
||||
#include <drv_conf.h>
|
||||
#include <osdep_service.h>
|
||||
#include <drv_types.h>
|
||||
#include <rtw_sreset.h>
|
||||
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
extern void rtl8192c_silentreset_for_specific_platform(_adapter *padapter);
|
||||
extern void rtl8192c_sreset_xmit_status_check(_adapter *padapter);
|
||||
extern void rtl8192c_sreset_linked_status_check(_adapter *padapter);
|
||||
#endif
|
||||
#endif
|
|
@ -1,164 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef _RTL8192C_XMIT_H_
|
||||
#define _RTL8192C_XMIT_H_
|
||||
|
||||
//
|
||||
//defined for TX DESC Operation
|
||||
//
|
||||
|
||||
#define MAX_TID (15)
|
||||
|
||||
//OFFSET 0
|
||||
#define OFFSET_SZ 0
|
||||
#define OFFSET_SHT 16
|
||||
#define BMC BIT(24)
|
||||
#define LSG BIT(26)
|
||||
#define FSG BIT(27)
|
||||
#define OWN BIT(31)
|
||||
|
||||
|
||||
//OFFSET 4
|
||||
#define PKT_OFFSET_SZ 0
|
||||
#define BK BIT(6)
|
||||
#define QSEL_SHT 8
|
||||
#define Rate_ID_SHT 16
|
||||
#define NAVUSEHDR BIT(20)
|
||||
#define PKT_OFFSET_SHT 26
|
||||
#define HWPC BIT(31)
|
||||
|
||||
//OFFSET 8
|
||||
#define AGG_EN BIT(29)
|
||||
|
||||
//OFFSET 12
|
||||
#define SEQ_SHT 16
|
||||
|
||||
//OFFSET 16
|
||||
#define QoS BIT(6)
|
||||
#define HW_SEQ_EN BIT(7)
|
||||
#define USERATE BIT(8)
|
||||
#define DISDATAFB BIT(10)
|
||||
#define DATA_SHORT BIT(24)
|
||||
#define DATA_BW BIT(25)
|
||||
|
||||
//OFFSET 20
|
||||
#define SGI BIT(6)
|
||||
|
||||
//
|
||||
// Queue Select Value in TxDesc
|
||||
//
|
||||
#define QSLT_BK 0x2//0x01
|
||||
#define QSLT_BE 0x0
|
||||
#define QSLT_VI 0x5//0x4
|
||||
#define QSLT_VO 0x7//0x6
|
||||
#define QSLT_BEACON 0x10
|
||||
#define QSLT_HIGH 0x11
|
||||
#define QSLT_MGNT 0x12
|
||||
#define QSLT_CMD 0x13
|
||||
|
||||
struct txrpt_ccx_8192c {
|
||||
/* offset 0 */
|
||||
u8 retry_cnt:6;
|
||||
u8 rsvd_0:2;
|
||||
|
||||
/* offset 1 */
|
||||
u8 rts_retry_cnt:6;
|
||||
u8 rsvd_1:2;
|
||||
|
||||
/* offset 2 */
|
||||
u8 ccx_qtime0;
|
||||
u8 ccx_qtime1;
|
||||
|
||||
/* offset 4 */
|
||||
u8 missed_pkt_num:5;
|
||||
u8 rsvd_4:3;
|
||||
|
||||
/* offset 5 */
|
||||
u8 mac_id:5;
|
||||
u8 des1_fragssn:3;
|
||||
|
||||
/* offset 6 */
|
||||
u8 rpt_pkt_num:5;
|
||||
u8 pkt_drop:1;
|
||||
u8 lifetime_over:1;
|
||||
u8 retry_over:1;
|
||||
|
||||
/* offset 7*/
|
||||
u8 edca_tx_queue:4;
|
||||
u8 rsvd_7:1;
|
||||
u8 bmc:1;
|
||||
u8 pkt_ok:1;
|
||||
u8 int_ccx:1;
|
||||
};
|
||||
|
||||
#define txrpt_ccx_qtime_8192c(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
|
||||
|
||||
#ifdef CONFIG_XMIT_ACK
|
||||
void dump_txrpt_ccx_8192c(void *buf);
|
||||
void handle_txrpt_ccx_8192c(_adapter *adapter, void *buf);
|
||||
#else
|
||||
#define dump_txrpt_ccx_8192c(buf) do {} while (0)
|
||||
#define handle_txrpt_ccx_8192c(adapter, buf) do {} while (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
|
||||
#ifdef CONFIG_USB_TX_AGGREGATION
|
||||
#define MAX_TX_AGG_PACKET_NUMBER 0xFF
|
||||
#endif
|
||||
|
||||
s32 rtl8192cu_init_xmit_priv(_adapter * padapter);
|
||||
|
||||
void rtl8192cu_free_xmit_priv(_adapter * padapter);
|
||||
|
||||
void rtl8192cu_cal_txdesc_chksum(struct tx_desc *ptxdesc);
|
||||
|
||||
s32 rtl8192cu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
|
||||
|
||||
s32 rtl8192cu_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);
|
||||
|
||||
s32 rtl8192cu_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
|
||||
#ifdef CONFIG_HOSTAPD_MLME
|
||||
s32 rtl8192cu_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
s32 rtl8192ce_init_xmit_priv(_adapter * padapter);
|
||||
void rtl8192ce_free_xmit_priv(_adapter * padapter);
|
||||
|
||||
s32 rtl8192ce_enqueue_xmitbuf(struct rtw_tx_ring *ring, struct xmit_buf *pxmitbuf);
|
||||
struct xmit_buf *rtl8192ce_dequeue_xmitbuf(struct rtw_tx_ring *ring);
|
||||
|
||||
void rtl8192ce_xmitframe_resume(_adapter *padapter);
|
||||
|
||||
s32 rtl8192ce_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);
|
||||
|
||||
s32 rtl8192ce_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
|
||||
#ifdef CONFIG_HOSTAPD_MLME
|
||||
s32 rtl8192ce_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
|
@ -1,101 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __RTL8192D_CMD_H_
|
||||
#define __RTL8192D_CMD_H_
|
||||
|
||||
|
||||
//--------------------------------------------
|
||||
//3 Host Message Box
|
||||
//--------------------------------------------
|
||||
|
||||
// User Define Message [31:8]
|
||||
|
||||
//_SETPWRMODE_PARM
|
||||
#define SET_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
#define SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
|
||||
//JOINBSSRPT_PARM
|
||||
#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
|
||||
//_RSVDPAGE_LOC
|
||||
#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
|
||||
//P2P_PS_OFFLOAD
|
||||
|
||||
struct P2P_PS_Offload_t {
|
||||
unsigned char Offload_En:1;
|
||||
unsigned char role:1; // 1: Owner, 0: Client
|
||||
unsigned char CTWindow_En:1;
|
||||
unsigned char NoA0_En:1;
|
||||
unsigned char NoA1_En:1;
|
||||
unsigned char AllStaSleep:1; // Only valid in Owner
|
||||
unsigned char discovery:1;
|
||||
unsigned char rsvd:1;
|
||||
};
|
||||
|
||||
#define SET_H2CCMD_P2P_PS_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
|
||||
#define SET_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
|
||||
#define SET_H2CCMD_P2P_PS_OFFLOAD_CTW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
|
||||
#define SET_H2CCMD_P2P_PS_OFFLOAD_NOA0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
|
||||
#define SET_H2CCMD_P2P_PS_OFFLOAD_NOA1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
|
||||
#define SET_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
|
||||
#define SET_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
|
||||
|
||||
// Description: Determine the types of H2C commands that are the same in driver and Fw.
|
||||
// Fisrt constructed by tynli. 2009.10.09.
|
||||
typedef enum _RTL8192D_H2C_CMD
|
||||
{
|
||||
H2C_AP_OFFLOAD = 0, /*0*/
|
||||
H2C_SETPWRMODE = 1, /*1*/
|
||||
H2C_JOINBSSRPT = 2, /*2*/
|
||||
H2C_RSVDPAGE = 3,
|
||||
H2C_RSSI_REPORT = 5,
|
||||
H2C_RA_MASK = 6,
|
||||
H2C_P2P_PS_OFFLOAD = 8,
|
||||
H2C_MAC_MODE_SEL = 9,
|
||||
H2C_PWRM=15,
|
||||
H2C_P2P_PS_CTW_CMD = 24,
|
||||
H2C_PathDiv = 26, //PathDiv--NeilChen--2011.07.15
|
||||
H2C_CMD_MAX
|
||||
}RTL8192D_H2C_CMD;
|
||||
|
||||
struct cmd_msg_parm {
|
||||
u8 eid; //element id
|
||||
u8 sz; // sz
|
||||
u8 buf[6];
|
||||
};
|
||||
|
||||
|
||||
void FillH2CCmd92D(_adapter* padapter, u8 ElementID, u32 CmdLen, u8* pCmdBuffer);
|
||||
|
||||
// host message to firmware cmd
|
||||
void rtl8192d_set_FwPwrMode_cmd(_adapter*padapter, u8 Mode);
|
||||
void rtl8192d_set_FwJoinBssReport_cmd(_adapter* padapter, u8 mstatus);
|
||||
u8 rtl8192d_set_rssi_cmd(_adapter*padapter, u8 *param);
|
||||
u8 rtl8192d_set_raid_cmd(_adapter*padapter, u32 mask, u8 arg);
|
||||
void rtl8192d_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8 arg, u8 rssi_level);
|
||||
#ifdef CONFIG_P2P
|
||||
void rtl8192d_set_p2p_ps_offload_cmd(_adapter* padapter, u8 p2p_ps_state);
|
||||
#endif //CONFIG_P2P
|
||||
|
||||
#endif
|
|
@ -1,182 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __RTL8192D_DM_H__
|
||||
#define __RTL8192D_DM_H__
|
||||
//============================================================
|
||||
// Description:
|
||||
//
|
||||
// This file is for 92CE/92CU dynamic mechanism only
|
||||
//
|
||||
//
|
||||
//============================================================
|
||||
enum{
|
||||
UP_LINK,
|
||||
DOWN_LINK,
|
||||
};
|
||||
/*------------------------Export global variable----------------------------*/
|
||||
/*------------------------Export global variable----------------------------*/
|
||||
/*------------------------Export Marco Definition---------------------------*/
|
||||
//#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;}
|
||||
//============================================================
|
||||
// structure and define
|
||||
//============================================================
|
||||
|
||||
//###### duplicate code,will move to ODM #########
|
||||
#define IQK_MAC_REG_NUM 4
|
||||
#define IQK_ADDA_REG_NUM 16
|
||||
#define IQK_BB_REG_NUM 10
|
||||
#define IQK_BB_REG_NUM_92C 9
|
||||
#define IQK_BB_REG_NUM_92D 10
|
||||
#define IQK_BB_REG_NUM_test 6
|
||||
#define index_mapping_NUM 13
|
||||
#define Rx_index_mapping_NUM 15
|
||||
#define AVG_THERMAL_NUM 8
|
||||
#define IQK_Matrix_REG_NUM 8
|
||||
#define IQK_Matrix_Settings_NUM 1+24+21
|
||||
//###### duplicate code,will move to ODM #########
|
||||
struct dm_priv
|
||||
{
|
||||
u8 DM_Type;
|
||||
u8 DMFlag;
|
||||
u8 InitDMFlag;
|
||||
u32 InitODMFlag;
|
||||
|
||||
//* Upper and Lower Signal threshold for Rate Adaptive*/
|
||||
int UndecoratedSmoothedPWDB;
|
||||
int EntryMinUndecoratedSmoothedPWDB;
|
||||
int EntryMaxUndecoratedSmoothedPWDB;
|
||||
int MinUndecoratedPWDBForDM;
|
||||
int LastMinUndecoratedPWDBForDM;
|
||||
//###### duplicate code,will move to ODM #########
|
||||
/*
|
||||
//for DIG
|
||||
u8 bDMInitialGainEnable;
|
||||
//u8 binitialized; // for dm_initial_gain_Multi_STA use.
|
||||
DIG_T DM_DigTable;
|
||||
|
||||
PS_T DM_PSTable;
|
||||
|
||||
FALSE_ALARM_STATISTICS FalseAlmCnt;
|
||||
|
||||
//for rate adaptive, in fact, 88c/92c fw will handle this
|
||||
u8 bUseRAMask;
|
||||
RATE_ADAPTIVE RateAdaptive;
|
||||
*/
|
||||
|
||||
//for High Power
|
||||
u8 bDynamicTxPowerEnable;
|
||||
u8 LastDTPLvl;
|
||||
u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06
|
||||
|
||||
//for tx power tracking
|
||||
u8 bTXPowerTracking;
|
||||
u8 TXPowercount;
|
||||
u8 bTXPowerTrackingInit;
|
||||
u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
|
||||
u8 TM_Trigger;
|
||||
|
||||
u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
|
||||
u8 ThermalValue;
|
||||
u8 ThermalValue_LCK;
|
||||
u8 ThermalValue_IQK;
|
||||
u8 ThermalValue_AVG[AVG_THERMAL_NUM];
|
||||
u8 ThermalValue_AVG_index;
|
||||
u8 ThermalValue_RxGain;
|
||||
u8 ThermalValue_Crystal;
|
||||
u8 Delta_IQK;
|
||||
u8 Delta_LCK;
|
||||
u8 bRfPiEnable;
|
||||
u8 bReloadtxpowerindex;
|
||||
u8 bDoneTxpower;
|
||||
|
||||
//for APK
|
||||
u32 APKoutput[2][2]; //path A/B; output1_1a/output1_2a
|
||||
u8 bAPKdone;
|
||||
u8 bAPKThermalMeterIgnore;
|
||||
u32 RegA24;
|
||||
|
||||
//for IQK
|
||||
u32 Reg874;
|
||||
u32 RegC08;
|
||||
u32 Reg88C;
|
||||
u8 Reg522;
|
||||
u8 Reg550;
|
||||
u8 Reg551;
|
||||
u32 Reg870;
|
||||
u32 ADDA_backup[IQK_ADDA_REG_NUM];
|
||||
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
|
||||
u32 IQK_BB_backup[IQK_BB_REG_NUM];
|
||||
|
||||
u8 bCCKinCH14;
|
||||
|
||||
char CCK_index;
|
||||
//u8 Record_CCK_20Mindex;
|
||||
//u8 Record_CCK_40Mindex;
|
||||
char OFDM_index[2];
|
||||
|
||||
bool bDPKdone[2];
|
||||
|
||||
u8 PowerIndex_backup[6];
|
||||
|
||||
//for Antenna diversity
|
||||
//#ifdef CONFIG_ANTENNA_DIVERSITY
|
||||
//SWAT_T DM_SWAT_Table;
|
||||
//#endif
|
||||
//Neil Chen----2011--06--23-----
|
||||
//3 Path Diversity
|
||||
bool bPathDiv_Enable; //For 92D Non-interrupt Antenna Diversity by Neil ,add by wl.2011.07.19
|
||||
bool RSSI_test;
|
||||
s32 RSSI_sum_A;
|
||||
s32 RSSI_cnt_A;
|
||||
s32 RSSI_sum_B;
|
||||
s32 RSSI_cnt_B;
|
||||
struct sta_info *RSSI_target;
|
||||
_timer PathDivSwitchTimer;
|
||||
|
||||
//for TxPwrTracking
|
||||
int RegE94;
|
||||
int RegE9C;
|
||||
int RegEB4;
|
||||
int RegEBC;
|
||||
#if MP_DRIVER == 1
|
||||
u8 RegC04_MP;
|
||||
u32 RegD04_MP;
|
||||
#endif
|
||||
u32 TXPowerTrackingCallbackCnt; //cosa add for debug
|
||||
|
||||
u32 prv_traffic_idx; // edca turbo
|
||||
|
||||
u32 RegRF3C[2]; //pathA / pathB
|
||||
//###### duplicate code,will move to ODM #########
|
||||
// Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas
|
||||
u8 INIDATA_RATE[32];
|
||||
};
|
||||
|
||||
|
||||
//============================================================
|
||||
// function prototype
|
||||
//============================================================
|
||||
void rtl8192d_init_dm_priv(IN PADAPTER Adapter);
|
||||
void rtl8192d_deinit_dm_priv(IN PADAPTER Adapter);
|
||||
|
||||
void rtl8192d_InitHalDm(IN PADAPTER Adapter);
|
||||
void rtl8192d_HalDmWatchDog(IN PADAPTER Adapter);
|
||||
|
||||
#endif //__HAL8190PCIDM_H__
|
|
@ -1,854 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __RTL8192D_HAL_H__
|
||||
#define __RTL8192D_HAL_H__
|
||||
|
||||
#include "rtl8192d_spec.h"
|
||||
#include "Hal8192DPhyReg.h"
|
||||
#include "Hal8192DPhyCfg.h"
|
||||
#include "rtl8192d_rf.h"
|
||||
#include "rtl8192d_dm.h"
|
||||
#include "rtl8192d_recv.h"
|
||||
#include "rtl8192d_xmit.h"
|
||||
#include "rtl8192d_cmd.h"
|
||||
#include "rtw_efuse.h"
|
||||
|
||||
#include "../hal/OUTSRC/odm_precomp.h"
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#include <pci_ops.h>
|
||||
|
||||
#define RTL819X_DEFAULT_RF_TYPE RF_2T2R
|
||||
|
||||
//---------------------------------------------------------------------
|
||||
// RTL8192DE From file
|
||||
//---------------------------------------------------------------------
|
||||
#define RTL8192D_FW_IMG "rtl8192DE\\rtl8192dfw.bin"
|
||||
|
||||
#define RTL8192D_PHY_REG "rtl8192DE\\PHY_REG.txt"
|
||||
#define RTL8192D_PHY_REG_PG "rtl8192DE\\PHY_REG_PG.txt"
|
||||
#define RTL8192D_PHY_REG_MP "rtl8192DE\\PHY_REG_MP.txt"
|
||||
|
||||
#define RTL8192D_AGC_TAB "rtl8192DE\\AGC_TAB.txt"
|
||||
#define RTL8192D_AGC_TAB_2G "rtl8192DE\\AGC_TAB_2G.txt"
|
||||
#define RTL8192D_AGC_TAB_5G "rtl8192DE\\AGC_TAB_5G.txt"
|
||||
#define RTL8192D_PHY_RADIO_A "rtl8192DE\\radio_a.txt"
|
||||
#define RTL8192D_PHY_RADIO_B "rtl8192DE\\radio_b.txt"
|
||||
#define RTL8192D_PHY_RADIO_A_intPA "rtl8192DE\\radio_a_intPA.txt"
|
||||
#define RTL8192D_PHY_RADIO_B_intPA "rtl8192DE\\radio_b_intPA.txt"
|
||||
#define RTL8192D_PHY_MACREG "rtl8192DE\\MAC_REG.txt"
|
||||
|
||||
//---------------------------------------------------------------------
|
||||
// RTL8192DE From header
|
||||
//---------------------------------------------------------------------
|
||||
// Fw Array
|
||||
#define Rtl8192D_FwImageArray Rtl8192DEFwImgArray
|
||||
|
||||
// MAC/BB/PHY Array
|
||||
#define Rtl8192D_MAC_Array Rtl8192DEMAC_2T_Array
|
||||
#define Rtl8192D_AGCTAB_Array Rtl8192DEAGCTAB_Array
|
||||
#define Rtl8192D_AGCTAB_5GArray Rtl8192DEAGCTAB_5GArray
|
||||
#define Rtl8192D_AGCTAB_2GArray Rtl8192DEAGCTAB_2GArray
|
||||
#define Rtl8192D_AGCTAB_2TArray Rtl8192DEAGCTAB_2TArray
|
||||
#define Rtl8192D_AGCTAB_1TArray Rtl8192DEAGCTAB_1TArray
|
||||
#define Rtl8192D_PHY_REG_2TArray Rtl8192DEPHY_REG_2TArray
|
||||
#define Rtl8192D_PHY_REG_1TArray Rtl8192DEPHY_REG_1TArray
|
||||
#define Rtl8192D_PHY_REG_Array_PG Rtl8192DEPHY_REG_Array_PG
|
||||
#define Rtl8192D_PHY_REG_Array_MP Rtl8192DEPHY_REG_Array_MP
|
||||
#define Rtl8192D_RadioA_2TArray Rtl8192DERadioA_2TArray
|
||||
#define Rtl8192D_RadioA_1TArray Rtl8192DERadioA_1TArray
|
||||
#define Rtl8192D_RadioB_2TArray Rtl8192DERadioB_2TArray
|
||||
#define Rtl8192D_RadioB_1TArray Rtl8192DERadioB_1TArray
|
||||
#define Rtl8192D_RadioA_2T_intPAArray Rtl8192DERadioA_2T_intPAArray
|
||||
#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DERadioB_2T_intPAArray
|
||||
|
||||
// Array length
|
||||
#define Rtl8192D_FwImageArrayLength Rtl8192DEImgArrayLength
|
||||
#define Rtl8192D_MAC_ArrayLength Rtl8192DEMAC_2T_ArrayLength
|
||||
#define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DEAGCTAB_5GArrayLength
|
||||
#define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DEAGCTAB_2GArrayLength
|
||||
#define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DEAGCTAB_2TArrayLength
|
||||
#define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DEAGCTAB_1TArrayLength
|
||||
#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DEAGCTAB_ArrayLength
|
||||
#define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DEPHY_REG_2TArrayLength
|
||||
#define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DEPHY_REG_1TArrayLength
|
||||
#define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DEPHY_REG_Array_PGLength
|
||||
#define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DEPHY_REG_Array_MPLength
|
||||
#define Rtl8192D_RadioA_2TArrayLength Rtl8192DERadioA_2TArrayLength
|
||||
#define Rtl8192D_RadioB_2TArrayLength Rtl8192DERadioB_2TArrayLength
|
||||
#define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DERadioA_2T_intPAArrayLength
|
||||
#define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DERadioB_2T_intPAArrayLength
|
||||
|
||||
#elif defined(CONFIG_USB_HCI)
|
||||
|
||||
|
||||
#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
|
||||
|
||||
//---------------------------------------------------------------------
|
||||
// RTL8192DU From file
|
||||
//---------------------------------------------------------------------
|
||||
#define RTL8192D_FW_IMG "rtl8192DU\\rtl8192dfw.bin"
|
||||
|
||||
#define RTL8192D_PHY_REG "rtl8192DU\\PHY_REG.txt"
|
||||
#define RTL8192D_PHY_REG_PG "rtl8192DU\\PHY_REG_PG.txt"
|
||||
#define RTL8192D_PHY_REG_MP "rtl8192DU\\PHY_REG_MP.txt"
|
||||
|
||||
#define RTL8192D_AGC_TAB "rtl8192DU\\AGC_TAB.txt"
|
||||
#define RTL8192D_AGC_TAB_2G "rtl8192DU\\AGC_TAB_2G.txt"
|
||||
#define RTL8192D_AGC_TAB_5G "rtl8192DU\\AGC_TAB_5G.txt"
|
||||
#define RTL8192D_PHY_RADIO_A "rtl8192DU\\radio_a.txt"
|
||||
#define RTL8192D_PHY_RADIO_B "rtl8192DU\\radio_b.txt"
|
||||
#define RTL8192D_PHY_RADIO_A_intPA "rtl8192DU\\radio_a_intPA.txt"
|
||||
#define RTL8192D_PHY_RADIO_B_intPA "rtl8192DU\\radio_b_intPA.txt"
|
||||
#define RTL8192D_PHY_MACREG "rtl8192DU\\MAC_REG.txt"
|
||||
|
||||
//---------------------------------------------------------------------
|
||||
// RTL8192DU From header
|
||||
//---------------------------------------------------------------------
|
||||
|
||||
// Fw Array
|
||||
#define Rtl8192D_FwImageArray Rtl8192DUFwImgArray
|
||||
|
||||
// MAC/BB/PHY Array
|
||||
#define Rtl8192D_MAC_Array Rtl8192DUMAC_2T_Array
|
||||
#define Rtl8192D_AGCTAB_Array Rtl8192DUAGCTAB_Array
|
||||
#define Rtl8192D_AGCTAB_5GArray Rtl8192DUAGCTAB_5GArray
|
||||
#define Rtl8192D_AGCTAB_2GArray Rtl8192DUAGCTAB_2GArray
|
||||
#define Rtl8192D_AGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
|
||||
#define Rtl8192D_AGCTAB_1TArray Rtl8192DUAGCTAB_1TArray
|
||||
#define Rtl8192D_PHY_REG_2TArray Rtl8192DUPHY_REG_2TArray
|
||||
#define Rtl8192D_PHY_REG_1TArray Rtl8192DUPHY_REG_1TArray
|
||||
#define Rtl8192D_PHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
|
||||
#define Rtl8192D_PHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
|
||||
#define Rtl8192D_RadioA_2TArray Rtl8192DURadioA_2TArray
|
||||
#define Rtl8192D_RadioA_1TArray Rtl8192DURadioA_1TArray
|
||||
#define Rtl8192D_RadioB_2TArray Rtl8192DURadioB_2TArray
|
||||
#define Rtl8192D_RadioB_1TArray Rtl8192DURadioB_1TArray
|
||||
#define Rtl8192D_RadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
|
||||
#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
|
||||
|
||||
// Array length
|
||||
#define Rtl8192D_FwImageArrayLength Rtl8192DUImgArrayLength
|
||||
#define Rtl8192D_MAC_ArrayLength Rtl8192DUMAC_2T_ArrayLength
|
||||
#define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DUAGCTAB_5GArrayLength
|
||||
#define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DUAGCTAB_2GArrayLength
|
||||
#define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DUAGCTAB_2TArrayLength
|
||||
#define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DUAGCTAB_1TArrayLength
|
||||
#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DUAGCTAB_ArrayLength
|
||||
#define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DUPHY_REG_2TArrayLength
|
||||
#define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DUPHY_REG_1TArrayLength
|
||||
#define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DUPHY_REG_Array_PGLength
|
||||
#define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DUPHY_REG_Array_MPLength
|
||||
#define Rtl8192D_RadioA_2TArrayLength Rtl8192DURadioA_2TArrayLength
|
||||
#define Rtl8192D_RadioB_2TArrayLength Rtl8192DURadioB_2TArrayLength
|
||||
#define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DURadioA_2T_intPAArrayLength
|
||||
#define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DURadioB_2T_intPAArrayLength
|
||||
|
||||
// The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24.
|
||||
/* #define Rtl819XFwImageArray Rtl8192DUFwImgArray
|
||||
#define Rtl819XMAC_Array Rtl8192DUMAC_2TArray
|
||||
#define Rtl819XAGCTAB_Array Rtl8192DUAGCTAB_Array
|
||||
#define Rtl819XAGCTAB_5GArray Rtl8192DUAGCTAB_5GArray
|
||||
#define Rtl819XAGCTAB_2GArray Rtl8192DUAGCTAB_2GArray
|
||||
#define Rtl819XPHY_REG_2TArray Rtl8192DUPHY_REG_2TArray
|
||||
#define Rtl819XPHY_REG_1TArray Rtl8192DUPHY_REG_1TArray
|
||||
#define Rtl819XRadioA_2TArray Rtl8192DURadioA_2TArray
|
||||
#define Rtl819XRadioA_1TArray Rtl8192DURadioA_1TArray
|
||||
#define Rtl819XRadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
|
||||
#define Rtl819XRadioB_2TArray Rtl8192DURadioB_2TArray
|
||||
#define Rtl819XRadioB_1TArray Rtl8192DURadioB_1TArray
|
||||
#define Rtl819XRadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
|
||||
#define Rtl819XPHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
|
||||
#define Rtl819XPHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
|
||||
|
||||
#define Rtl819XAGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
|
||||
#define Rtl819XAGCTAB_1TArray Rtl8192DUAGCTAB_1TArray*/
|
||||
|
||||
#endif
|
||||
|
||||
#define DRVINFO_SZ 4 // unit is 8bytes
|
||||
#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
|
||||
|
||||
//
|
||||
// Check if FW header exists. We do not consider the lower 4 bits in this case.
|
||||
// By tynli. 2009.12.04.
|
||||
//
|
||||
#define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
|
||||
(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\
|
||||
(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D0 ||\
|
||||
(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D1 ||\
|
||||
(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D2 ||\
|
||||
(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D3 )
|
||||
|
||||
#define FW_8192D_SIZE 0x8020 // Max FW len = 32k + 32(FW header length).
|
||||
#define FW_8192D_START_ADDRESS 0x1000
|
||||
#define FW_8192D_END_ADDRESS 0x1FFF
|
||||
|
||||
#define MAX_PAGE_SIZE 4096 // @ page : 4k bytes
|
||||
|
||||
typedef enum _FIRMWARE_SOURCE{
|
||||
FW_SOURCE_IMG_FILE = 0,
|
||||
FW_SOURCE_HEADER_FILE = 1, //from header file
|
||||
}FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;
|
||||
|
||||
typedef struct _RT_FIRMWARE{
|
||||
FIRMWARE_SOURCE eFWSource;
|
||||
u8* szFwBuffer;
|
||||
u32 ulFwLength;
|
||||
}RT_FIRMWARE, *PRT_FIRMWARE, RT_FIRMWARE_92D, *PRT_FIRMWARE_92D;
|
||||
|
||||
//
|
||||
// This structure must be cared byte-ordering
|
||||
//
|
||||
// Added by tynli. 2009.12.04.
|
||||
typedef struct _RT_8192D_FIRMWARE_HDR {//8-byte alinment required
|
||||
|
||||
//--- LONG WORD 0 ----
|
||||
u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut
|
||||
u8 Category; // AP/NIC and USB/PCI
|
||||
u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions
|
||||
u16 Version; // FW Version
|
||||
u8 Subversion; // FW Subversion, default 0x00
|
||||
u8 Rsvd1;
|
||||
|
||||
|
||||
//--- LONG WORD 1 ----
|
||||
u8 Month; // Release time Month field
|
||||
u8 Date; // Release time Date field
|
||||
u8 Hour; // Release time Hour field
|
||||
u8 Minute; // Release time Minute field
|
||||
u16 RamCodeSize; // The size of RAM code
|
||||
u16 Rsvd2;
|
||||
|
||||
//--- LONG WORD 2 ----
|
||||
u32 SvnIdx; // The SVN entry index
|
||||
u32 Rsvd3;
|
||||
|
||||
//--- LONG WORD 3 ----
|
||||
u32 Rsvd4;
|
||||
u32 Rsvd5;
|
||||
|
||||
}RT_8192D_FIRMWARE_HDR, *PRT_8192D_FIRMWARE_HDR;
|
||||
|
||||
#define DRIVER_EARLY_INT_TIME 0x05
|
||||
#define BCN_DMA_ATIME_INT_TIME 0x02
|
||||
|
||||
typedef enum _BT_CoType{
|
||||
BT_2Wire = 0,
|
||||
BT_ISSC_3Wire = 1,
|
||||
BT_Accel = 2,
|
||||
BT_CSR = 3,
|
||||
BT_CSR_ENHAN = 4,
|
||||
BT_RTL8756 = 5,
|
||||
} BT_CoType, *PBT_CoType;
|
||||
|
||||
typedef enum _BT_CurState{
|
||||
BT_OFF = 0,
|
||||
BT_ON = 1,
|
||||
} BT_CurState, *PBT_CurState;
|
||||
|
||||
typedef enum _BT_ServiceType{
|
||||
BT_SCO = 0,
|
||||
BT_A2DP = 1,
|
||||
BT_HID = 2,
|
||||
BT_HID_Idle = 3,
|
||||
BT_Scan = 4,
|
||||
BT_Idle = 5,
|
||||
BT_OtherAction = 6,
|
||||
BT_Busy = 7,
|
||||
BT_OtherBusy = 8,
|
||||
} BT_ServiceType, *PBT_ServiceType;
|
||||
|
||||
typedef enum _BT_RadioShared{
|
||||
BT_Radio_Shared = 0,
|
||||
BT_Radio_Individual = 1,
|
||||
} BT_RadioShared, *PBT_RadioShared;
|
||||
|
||||
typedef struct _BT_COEXIST_STR{
|
||||
u8 BluetoothCoexist;
|
||||
u8 BT_Ant_Num;
|
||||
u8 BT_CoexistType;
|
||||
u8 BT_State;
|
||||
u8 BT_CUR_State; //0:on, 1:off
|
||||
u8 BT_Ant_isolation; //0:good, 1:bad
|
||||
u8 BT_PapeCtrl; //0:SW, 1:SW/HW dynamic
|
||||
u8 BT_Service;
|
||||
u8 BT_RadioSharedType;
|
||||
u8 Ratio_Tx;
|
||||
u8 Ratio_PRI;
|
||||
}BT_COEXIST_STR, *PBT_COEXIST_STR;
|
||||
|
||||
|
||||
#ifdef CONFIG_USB_RX_AGGREGATION
|
||||
|
||||
typedef enum _USB_RX_AGG_MODE{
|
||||
USB_RX_AGG_DISABLE,
|
||||
USB_RX_AGG_DMA,
|
||||
USB_RX_AGG_USB,
|
||||
USB_RX_AGG_DMA_USB
|
||||
}USB_RX_AGG_MODE;
|
||||
|
||||
#define MAX_RX_DMA_BUFFER_SIZE 10240 // 10K for 8192C RX DMA buffer
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#define TX_SELE_HQ BIT(0) // High Queue
|
||||
#define TX_SELE_LQ BIT(1) // Low Queue
|
||||
#define TX_SELE_NQ BIT(2) // Normal Queue
|
||||
|
||||
|
||||
// Note: We will divide number of page equally for each queue other than public queue!
|
||||
|
||||
#define TX_TOTAL_PAGE_NUMBER 0xF8
|
||||
#define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER + 1)
|
||||
|
||||
// For Normal Chip Setting
|
||||
// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER
|
||||
#define NORMAL_PAGE_NUM_PUBQ 0x56
|
||||
|
||||
|
||||
// For Test Chip Setting
|
||||
// (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER
|
||||
#define TEST_PAGE_NUM_PUBQ 0x89
|
||||
#define TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC 0x7A
|
||||
#define NORMAL_PAGE_NUM_PUBQ_92D_DUAL_MAC 0x5A
|
||||
#define NORMAL_PAGE_NUM_HPQ_92D_DUAL_MAC 0x10
|
||||
#define NORMAL_PAGE_NUM_LPQ_92D_DUAL_MAC 0x10
|
||||
#define NORMAL_PAGE_NUM_NORMALQ_92D_DUAL_MAC 0
|
||||
|
||||
#define TX_PAGE_BOUNDARY_DUAL_MAC (TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC + 1)
|
||||
|
||||
// For Test Chip Setting
|
||||
#define WMM_TEST_TX_TOTAL_PAGE_NUMBER 0xF5
|
||||
#define WMM_TEST_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
|
||||
|
||||
#define WMM_TEST_PAGE_NUM_PUBQ 0xA3
|
||||
#define WMM_TEST_PAGE_NUM_HPQ 0x29
|
||||
#define WMM_TEST_PAGE_NUM_LPQ 0x29
|
||||
|
||||
|
||||
//Note: For Normal Chip Setting ,modify later
|
||||
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5
|
||||
#define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
|
||||
|
||||
#define WMM_NORMAL_PAGE_NUM_PUBQ 0xB0
|
||||
#define WMM_NORMAL_PAGE_NUM_HPQ 0x29
|
||||
#define WMM_NORMAL_PAGE_NUM_LPQ 0x1C
|
||||
#define WMM_NORMAL_PAGE_NUM_NPQ 0x1C
|
||||
|
||||
#define WMM_NORMAL_PAGE_NUM_PUBQ_92D 0X65//0x82
|
||||
#define WMM_NORMAL_PAGE_NUM_HPQ_92D 0X30//0x29
|
||||
#define WMM_NORMAL_PAGE_NUM_LPQ_92D 0X30
|
||||
#define WMM_NORMAL_PAGE_NUM_NPQ_92D 0X30
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// Chip specific
|
||||
//-------------------------------------------------------------------------
|
||||
|
||||
#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
|
||||
#define CHIP_BONDING_92C_1T2R 0x1
|
||||
#define CHIP_BONDING_88C_USB_MCARD 0x2
|
||||
#define CHIP_BONDING_88C_USB_HP 0x1
|
||||
|
||||
#include "HalVerDef.h"
|
||||
#include "hal_com.h"
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// Channel Plan
|
||||
//-------------------------------------------------------------------------
|
||||
enum ChannelPlan{
|
||||
CHPL_FCC = 0,
|
||||
CHPL_IC = 1,
|
||||
CHPL_ETSI = 2,
|
||||
CHPL_SPA = 3,
|
||||
CHPL_FRANCE = 4,
|
||||
CHPL_MKK = 5,
|
||||
CHPL_MKK1 = 6,
|
||||
CHPL_ISRAEL = 7,
|
||||
CHPL_TELEC = 8,
|
||||
CHPL_GLOBAL = 9,
|
||||
CHPL_WORLD = 10,
|
||||
};
|
||||
|
||||
typedef struct _TxPowerInfo{
|
||||
u8 CCKIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX];
|
||||
u8 HT40_1SIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX];
|
||||
u8 HT40_2SIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX];
|
||||
s8 HT20IndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX];
|
||||
u8 OFDMIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX];
|
||||
u8 HT40MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX];
|
||||
u8 HT20MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX];
|
||||
u8 TSSI_A[3];
|
||||
u8 TSSI_B[3];
|
||||
u8 TSSI_A_5G[3]; //5GL/5GM/5GH
|
||||
u8 TSSI_B_5G[3];
|
||||
}TxPowerInfo, *PTxPowerInfo;
|
||||
|
||||
#define EFUSE_REAL_CONTENT_LEN 1024
|
||||
#define EFUSE_MAP_LEN 256
|
||||
#define EFUSE_MAX_SECTION 32
|
||||
#define EFUSE_MAX_SECTION_BASE 16
|
||||
// <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
|
||||
// 9bytes + 1byt + 5bytes and pre 1byte.
|
||||
// For worst case:
|
||||
// | 2byte|----8bytes----|1byte|--7bytes--| //92D
|
||||
#define EFUSE_OOB_PROTECT_BYTES 18 // PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte.
|
||||
|
||||
typedef enum _PA_MODE {
|
||||
PA_MODE_EXTERNAL = 0x00,
|
||||
PA_MODE_INTERNAL_SP3T = 0x01,
|
||||
PA_MODE_INTERNAL_SPDT = 0x02
|
||||
} PA_MODE;
|
||||
|
||||
/* Copy from rtl8192c */
|
||||
enum c2h_id_8192d {
|
||||
C2H_DBG = 0,
|
||||
C2H_TSF = 1,
|
||||
C2H_AP_RPT_RSP = 2,
|
||||
C2H_CCX_TX_RPT = 3,
|
||||
C2H_BT_RSSI = 4,
|
||||
C2H_BT_OP_MODE = 5,
|
||||
C2H_EXT_RA_RPT = 6,
|
||||
C2H_HW_INFO_EXCH = 10,
|
||||
C2H_C2H_H2C_TEST = 11,
|
||||
C2H_BT_INFO = 12,
|
||||
C2H_BT_MP_INFO = 15,
|
||||
MAX_C2HEVENT
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
struct hal_data_8192de
|
||||
{
|
||||
HAL_VERSION VersionID;
|
||||
// add for 92D Phy mode/mac/Band mode
|
||||
MACPHY_MODE_8192D MacPhyMode92D;
|
||||
BAND_TYPE CurrentBandType92D; //0:2.4G, 1:5G
|
||||
BAND_TYPE BandSet92D;
|
||||
bool bIsVS;
|
||||
bool bSupportRemoteWakeUp;
|
||||
u8 AutoLoadStatusFor8192D;
|
||||
|
||||
bool bNOPG;
|
||||
|
||||
bool bMasterOfDMSP;
|
||||
bool bSlaveOfDMSP;
|
||||
|
||||
u16 CustomerID;
|
||||
|
||||
u16 FirmwareVersion;
|
||||
u16 FirmwareVersionRev;
|
||||
u16 FirmwareSubVersion;
|
||||
|
||||
u32 IntrMask[2];
|
||||
u32 IntrMaskToSet[2];
|
||||
|
||||
u32 DisabledFunctions;
|
||||
|
||||
//current WIFI_PHY values
|
||||
u32 ReceiveConfig;
|
||||
u32 TransmitConfig;
|
||||
WIRELESS_MODE CurrentWirelessMode;
|
||||
HT_CHANNEL_WIDTH CurrentChannelBW;
|
||||
u8 CurrentChannel;
|
||||
u8 nCur40MhzPrimeSC;// Control channel sub-carrier
|
||||
u16 BasicRateSet;
|
||||
|
||||
//rf_ctrl
|
||||
u8 rf_chip;
|
||||
u8 rf_type;
|
||||
u8 NumTotalRFPath;
|
||||
|
||||
//
|
||||
// EEPROM setting.
|
||||
//
|
||||
u16 EEPROMVID;
|
||||
u16 EEPROMDID;
|
||||
u16 EEPROMSVID;
|
||||
u16 EEPROMSMID;
|
||||
u16 EEPROMChannelPlan;
|
||||
u16 EEPROMVersion;
|
||||
|
||||
u8 EEPROMCustomerID;
|
||||
u8 EEPROMBoardType;
|
||||
u8 EEPROMRegulatory;
|
||||
|
||||
u8 EEPROMThermalMeter;
|
||||
|
||||
u8 EEPROMC9;
|
||||
u8 EEPROMCC;
|
||||
u8 PAMode;
|
||||
|
||||
u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER_2G];
|
||||
u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
|
||||
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
|
||||
s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
|
||||
u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
|
||||
// For power group
|
||||
u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
|
||||
u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
|
||||
|
||||
u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff
|
||||
|
||||
u8 CrystalCap; // CrystalCap.
|
||||
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
struct btcoexist_priv bt_coexist;
|
||||
#endif
|
||||
|
||||
// Read/write are allow for following hardware information variables
|
||||
u8 framesync;
|
||||
u32 framesyncC34;
|
||||
u8 framesyncMonitor;
|
||||
u8 DefaultInitialGain[4];
|
||||
u8 pwrGroupCnt;
|
||||
u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
|
||||
u32 CCKTxPowerLevelOriginalOffset;
|
||||
|
||||
u32 AntennaTxPath; // Antenna path Tx
|
||||
u32 AntennaRxPath; // Antenna path Rx
|
||||
u8 BluetoothCoexist;
|
||||
u8 ExternalPA;
|
||||
u8 InternalPA5G[2]; //pathA / pathB
|
||||
|
||||
//u32 LedControlNum;
|
||||
//u32 LedControlMode;
|
||||
//u32 TxPowerTrackControl;
|
||||
u8 b1x1RecvCombine; // for 1T1R receive combining
|
||||
|
||||
u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo.
|
||||
|
||||
//vivi, for tx power tracking, 20080407
|
||||
//u16 TSSI_13dBm;
|
||||
//u32 Pwr_Track;
|
||||
// The current Tx Power Level
|
||||
u8 CurrentCckTxPwrIdx;
|
||||
u8 CurrentOfdm24GTxPwrIdx;
|
||||
|
||||
BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
|
||||
|
||||
u32 RfRegChnlVal[2];
|
||||
|
||||
|
||||
bool bPhyValueInitReady;
|
||||
|
||||
bool bTXPowerDataReadFromEEPORM;
|
||||
|
||||
bool bInSetPower;
|
||||
|
||||
//RDG enable
|
||||
bool bRDGEnable;
|
||||
|
||||
bool bLoadIMRandIQKSettingFor2G;// True if IMR or IQK have done for 2.4G in scan progress
|
||||
bool bNeedIQK;
|
||||
|
||||
bool bLCKInProgress;
|
||||
|
||||
bool bEarlyModeEnable;
|
||||
|
||||
#if 1
|
||||
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
|
||||
#else
|
||||
//regc80、regc94、regc4c、regc88、regc9c、regc14、regca0、regc1c、regc78
|
||||
u4Byte IQKMatrixReg[IQK_Matrix_REG_NUM];
|
||||
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; // 1->2G,24->5G 20M channel,21->5G 40M channel.
|
||||
#endif
|
||||
|
||||
//for host message to fw
|
||||
u8 LastHMEBoxNum;
|
||||
|
||||
u8 fw_ractrl;
|
||||
// Beacon function related global variable.
|
||||
u32 RegBcnCtrlVal;
|
||||
u8 RegTxPause;
|
||||
u8 RegFwHwTxQCtrl;
|
||||
u8 RegReg542;
|
||||
u8 RegCR_1;
|
||||
|
||||
struct dm_priv dmpriv;
|
||||
DM_ODM_T odmpriv;
|
||||
//_lock odm_stainfo_lock;
|
||||
u8 bInterruptMigration;
|
||||
|
||||
u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
|
||||
|
||||
// Add for dual MAC 0--Mac0 1--Mac1
|
||||
u32 interfaceIndex;
|
||||
|
||||
u16 RegRRSR;
|
||||
|
||||
u16 EfuseUsedBytes;
|
||||
|
||||
bool EepromOrEfuse;
|
||||
u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes)
|
||||
u8 EfuseUsedPercentage;
|
||||
EFUSE_HAL EfuseHal;
|
||||
|
||||
u8 RTSInitRate; // 2010.11.24.by tynli.
|
||||
#ifdef CONFIG_P2P
|
||||
struct P2P_PS_Offload_t p2p_ps_offload;
|
||||
#endif //CONFIG_P2P
|
||||
};
|
||||
|
||||
typedef struct hal_data_8192de HAL_DATA_TYPE, *PHAL_DATA_TYPE;
|
||||
|
||||
//
|
||||
// Function disabled.
|
||||
//
|
||||
#define DF_TX_BIT BIT0
|
||||
#define DF_RX_BIT BIT1
|
||||
#define DF_IO_BIT BIT2
|
||||
#define DF_IO_D3_BIT BIT3
|
||||
|
||||
#define RT_DF_TYPE u32
|
||||
#define RT_DISABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions |= ((RT_DF_TYPE)(__FuncBits)))
|
||||
#define RT_ENABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions &= (~((RT_DF_TYPE)(__FuncBits))))
|
||||
#define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) )
|
||||
|
||||
void InterruptRecognized8192DE(PADAPTER Adapter, PRT_ISR_CONTENT pIsrContent);
|
||||
void UpdateInterruptMask8192DE(PADAPTER Adapter, u32 AddMSR, u32 RemoveMSR);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
|
||||
//should be renamed and moved to another file
|
||||
typedef enum _INTERFACE_SELECT_8192DUSB{
|
||||
INTF_SEL0_USB = 0, // USB
|
||||
INTF_SEL1_MINICARD = 1, // Minicard
|
||||
INTF_SEL2_EKB_PRO = 2, // Eee keyboard proprietary
|
||||
INTF_SEL3_PRO = 3, // Customized proprietary
|
||||
} INTERFACE_SELECT_8192DUSB, *PINTERFACE_SELECT_8192DUSB;
|
||||
|
||||
typedef INTERFACE_SELECT_8192DUSB INTERFACE_SELECT_USB;
|
||||
|
||||
struct hal_data_8192du
|
||||
{
|
||||
HAL_VERSION VersionID;
|
||||
|
||||
// add for 92D Phy mode/mac/Band mode
|
||||
MACPHY_MODE_8192D MacPhyMode92D;
|
||||
BAND_TYPE CurrentBandType92D; //0:2.4G, 1:5G
|
||||
BAND_TYPE BandSet92D;
|
||||
bool bIsVS;
|
||||
|
||||
bool bNOPG;
|
||||
|
||||
bool bSupportRemoteWakeUp;
|
||||
bool bMasterOfDMSP;
|
||||
bool bSlaveOfDMSP;
|
||||
#ifdef CONFIG_DUALMAC_CONCURRENT
|
||||
bool bInModeSwitchProcess;
|
||||
#endif
|
||||
|
||||
u16 CustomerID;
|
||||
|
||||
u16 FirmwareVersion;
|
||||
u16 FirmwareVersionRev;
|
||||
u16 FirmwareSubVersion;
|
||||
|
||||
//current WIFI_PHY values
|
||||
u32 ReceiveConfig;
|
||||
WIRELESS_MODE CurrentWirelessMode;
|
||||
HT_CHANNEL_WIDTH CurrentChannelBW;
|
||||
u8 CurrentChannel;
|
||||
u8 nCur40MhzPrimeSC;// Control channel sub-carrier
|
||||
u16 BasicRateSet;
|
||||
|
||||
INTERFACE_SELECT_8192DUSB InterfaceSel;
|
||||
|
||||
//rf_ctrl
|
||||
u8 rf_chip;
|
||||
u8 rf_type;
|
||||
u8 NumTotalRFPath;
|
||||
|
||||
//
|
||||
// EEPROM setting.
|
||||
//
|
||||
u8 EEPROMVersion;
|
||||
u16 EEPROMVID;
|
||||
u16 EEPROMPID;
|
||||
u16 EEPROMSVID;
|
||||
u16 EEPROMSDID;
|
||||
u8 EEPROMCustomerID;
|
||||
u8 EEPROMSubCustomerID;
|
||||
u8 EEPROMRegulatory;
|
||||
|
||||
u8 EEPROMThermalMeter;
|
||||
|
||||
u8 EEPROMC9;
|
||||
u8 EEPROMCC;
|
||||
u8 PAMode;
|
||||
|
||||
u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER_2G];
|
||||
u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
|
||||
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
|
||||
s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
|
||||
u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
|
||||
// For power group
|
||||
u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
|
||||
u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
|
||||
|
||||
u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff
|
||||
|
||||
u8 CrystalCap; // CrystalCap.
|
||||
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
struct btcoexist_priv bt_coexist;
|
||||
#endif
|
||||
|
||||
// Read/write are allow for following hardware information variables
|
||||
u8 framesync;
|
||||
u32 framesyncC34;
|
||||
u8 framesyncMonitor;
|
||||
u8 DefaultInitialGain[4];
|
||||
u8 pwrGroupCnt;
|
||||
u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
|
||||
u32 CCKTxPowerLevelOriginalOffset;
|
||||
|
||||
u32 AntennaTxPath; // Antenna path Tx
|
||||
u32 AntennaRxPath; // Antenna path Rx
|
||||
u8 BluetoothCoexist;
|
||||
u8 ExternalPA;
|
||||
u8 InternalPA5G[2]; //pathA / pathB
|
||||
|
||||
//u32 LedControlNum;
|
||||
//u32 LedControlMode;
|
||||
//u32 TxPowerTrackControl;
|
||||
u8 b1x1RecvCombine; // for 1T1R receive combining
|
||||
|
||||
u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo.
|
||||
|
||||
//vivi, for tx power tracking, 20080407
|
||||
//u16 TSSI_13dBm;
|
||||
//u32 Pwr_Track;
|
||||
// The current Tx Power Level
|
||||
u8 CurrentCckTxPwrIdx;
|
||||
u8 CurrentOfdm24GTxPwrIdx;
|
||||
|
||||
BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
|
||||
|
||||
|
||||
u32 RfRegChnlVal[2];
|
||||
|
||||
|
||||
bool bPhyValueInitReady;
|
||||
|
||||
bool bTXPowerDataReadFromEEPORM;
|
||||
|
||||
bool bInSetPower;
|
||||
|
||||
//RDG enable
|
||||
bool bRDGEnable;
|
||||
|
||||
bool bLoadIMRandIQKSettingFor2G;// True if IMR or IQK have done for 2.4G in scan progress
|
||||
bool bNeedIQK;
|
||||
|
||||
bool bLCKInProgress;
|
||||
|
||||
bool bEarlyModeEnable;
|
||||
|
||||
#if 1
|
||||
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
|
||||
#else
|
||||
//regc80、regc94、regc4c、regc88、regc9c、regc14、regca0、regc1c、regc78
|
||||
u4Byte IQKMatrixReg[IQK_Matrix_REG_NUM];
|
||||
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; // 1->2G,24->5G 20M channel,21->5G 40M channel.
|
||||
#endif
|
||||
|
||||
//for host message to fw
|
||||
u8 LastHMEBoxNum;
|
||||
|
||||
u8 fw_ractrl;
|
||||
// Beacon function related global variable.
|
||||
u32 RegBcnCtrlVal;
|
||||
u8 RegTxPause;
|
||||
u8 RegFwHwTxQCtrl;
|
||||
u8 RegReg542;
|
||||
u8 RegCR_1;
|
||||
|
||||
struct dm_priv dmpriv;
|
||||
DM_ODM_T odmpriv;
|
||||
//_lock odm_stainfo_lock;
|
||||
u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
|
||||
|
||||
//Query RF by FW
|
||||
bool bReadRFbyFW;
|
||||
|
||||
// For 92C USB endpoint setting
|
||||
//
|
||||
|
||||
u32 UsbBulkOutSize;
|
||||
|
||||
// Add for dual MAC 0--Mac0 1--Mac1
|
||||
u32 interfaceIndex;
|
||||
|
||||
u8 OutEpQueueSel;
|
||||
u8 OutEpNumber;
|
||||
|
||||
#ifdef CONFIG_USB_TX_AGGREGATION
|
||||
u8 UsbTxAggMode;
|
||||
u8 UsbTxAggDescNum;
|
||||
#endif
|
||||
#ifdef CONFIG_USB_RX_AGGREGATION
|
||||
u16 HwRxPageSize; // Hardware setting
|
||||
u32 MaxUsbRxAggBlock;
|
||||
|
||||
USB_RX_AGG_MODE UsbRxAggMode;
|
||||
u8 UsbRxAggBlockCount; // USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed
|
||||
u8 UsbRxAggBlockTimeout;
|
||||
u8 UsbRxAggPageCount; // 8192C DMA page count
|
||||
u8 UsbRxAggPageTimeout;
|
||||
#endif
|
||||
|
||||
u16 RegRRSR;
|
||||
|
||||
u16 EfuseUsedBytes;
|
||||
|
||||
bool EepromOrEfuse;
|
||||
u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes)
|
||||
u8 EfuseUsedPercentage;
|
||||
EFUSE_HAL EfuseHal;
|
||||
|
||||
u8 RTSInitRate; // 2010.11.24.by tynli.
|
||||
#ifdef CONFIG_P2P
|
||||
struct P2P_PS_Offload_t p2p_ps_offload;
|
||||
#endif //CONFIG_P2P
|
||||
};
|
||||
|
||||
typedef struct hal_data_8192du HAL_DATA_TYPE, *PHAL_DATA_TYPE;
|
||||
#endif
|
||||
|
||||
#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData))
|
||||
#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type)
|
||||
|
||||
int FirmwareDownload92D(IN PADAPTER Adapter);
|
||||
void rtl8192d_FirmwareSelfReset(IN PADAPTER Adapter);
|
||||
void rtl8192d_ReadChipVersion(IN PADAPTER Adapter);
|
||||
void rtl8192d_EfuseParseChnlPlan(PADAPTER Adapter, u8 *hwinfo, bool AutoLoadFail);
|
||||
void rtl8192d_ReadTxPowerInfo(PADAPTER Adapter, u8* PROMContent, bool AutoLoadFail);
|
||||
void rtl8192d_ResetDualMacSwitchVariables(IN PADAPTER Adapter);
|
||||
u8 GetEEPROMSize8192D(PADAPTER Adapter);
|
||||
bool PHY_CheckPowerOffFor8192D(PADAPTER Adapter);
|
||||
void PHY_SetPowerOnFor8192D(PADAPTER Adapter);
|
||||
//void PHY_ConfigMacPhyMode92D(PADAPTER Adapter);
|
||||
void rtl8192d_free_hal_data(_adapter * padapter);
|
||||
void rtl8192d_set_hal_ops(struct hal_ops *pHalFunc);
|
||||
void rtl8192d_clone_haldata(_adapter* dst_adapter, _adapter* src_adapter);
|
||||
#endif
|
|
@ -1,42 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __RTL8192D_LED_H_
|
||||
#define __RTL8192D_LED_H_
|
||||
|
||||
#include <drv_conf.h>
|
||||
#include <osdep_service.h>
|
||||
#include <drv_types.h>
|
||||
|
||||
|
||||
//================================================================================
|
||||
// Interface to manipulate LED objects.
|
||||
//================================================================================
|
||||
#ifdef CONFIG_USB_HCI
|
||||
void rtl8192du_InitSwLeds(_adapter *padapter);
|
||||
void rtl8192du_DeInitSwLeds(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
void rtl8192de_gen_RefreshLedState(PADAPTER Adapter);
|
||||
void rtl8192de_InitSwLeds(_adapter *padapter);
|
||||
void rtl8192de_DeInitSwLeds(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#endif
|
|
@ -1,134 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef _RTL8192D_RECV_H_
|
||||
#define _RTL8192D_RECV_H_
|
||||
|
||||
#include <drv_conf.h>
|
||||
#include <osdep_service.h>
|
||||
#include <drv_types.h>
|
||||
|
||||
|
||||
#ifdef PLATFORM_OS_XP
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
#define NR_RECVBUFF 1024//512//128
|
||||
#else
|
||||
#define NR_RECVBUFF (16)
|
||||
#endif
|
||||
#elif defined(PLATFORM_OS_CE)
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
#define NR_RECVBUFF (128)
|
||||
#else
|
||||
#define NR_RECVBUFF (4)
|
||||
#endif
|
||||
#else
|
||||
#ifdef CONFIG_SINGLE_RECV_BUF
|
||||
#define NR_RECVBUFF (1)
|
||||
#else
|
||||
#define NR_RECVBUFF (4)
|
||||
#endif //CONFIG_SINGLE_RECV_BUF
|
||||
#define NR_PREALLOC_RECV_SKB (8)
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#define RECV_BLK_SZ 512
|
||||
#define RECV_BLK_CNT 16
|
||||
#define RECV_BLK_TH RECV_BLK_CNT
|
||||
|
||||
#if defined(CONFIG_USB_HCI)
|
||||
|
||||
#ifdef PLATFORM_OS_CE
|
||||
#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k
|
||||
#else
|
||||
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
|
||||
//#define MAX_RECVBUF_SZ (32768) // 32k
|
||||
//#define MAX_RECVBUF_SZ (16384) //16K
|
||||
//#define MAX_RECVBUF_SZ (10240) //10K
|
||||
#define MAX_RECVBUF_SZ (15360) // 15k < 16k
|
||||
#else
|
||||
#define MAX_RECVBUF_SZ (4000) // about 4K
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#elif defined(CONFIG_PCI_HCI)
|
||||
//#ifndef CONFIG_MINIMAL_MEMORY_USAGE
|
||||
// #define MAX_RECVBUF_SZ (9100)
|
||||
//#else
|
||||
#define MAX_RECVBUF_SZ (4000) // about 4K
|
||||
//#endif
|
||||
|
||||
#define RX_MPDU_QUEUE 0
|
||||
#define RX_CMD_QUEUE 1
|
||||
#define RX_MAX_QUEUE 2
|
||||
#endif
|
||||
|
||||
#define RECV_BULK_IN_ADDR 0x80
|
||||
#define RECV_INT_IN_ADDR 0x81
|
||||
|
||||
#define PHY_RSSI_SLID_WIN_MAX 100
|
||||
#define PHY_LINKQUALITY_SLID_WIN_MAX 20
|
||||
|
||||
struct phy_stat
|
||||
{
|
||||
unsigned int phydw0;
|
||||
|
||||
unsigned int phydw1;
|
||||
|
||||
unsigned int phydw2;
|
||||
|
||||
unsigned int phydw3;
|
||||
|
||||
unsigned int phydw4;
|
||||
|
||||
unsigned int phydw5;
|
||||
|
||||
unsigned int phydw6;
|
||||
|
||||
unsigned int phydw7;
|
||||
};
|
||||
|
||||
// Rx smooth factor
|
||||
#define Rx_Smooth_Factor (20)
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
typedef struct _INTERRUPT_MSG_FORMAT_EX{
|
||||
unsigned int C2H_MSG0;
|
||||
unsigned int C2H_MSG1;
|
||||
unsigned int C2H_MSG2;
|
||||
unsigned int C2H_MSG3;
|
||||
unsigned int HISR; // from HISR Reg0x124, read to clear
|
||||
unsigned int HISRE;// from HISRE Reg0x12c, read to clear
|
||||
unsigned int MSG_EX;
|
||||
}INTERRUPT_MSG_FORMAT_EX,*PINTERRUPT_MSG_FORMAT_EX;
|
||||
|
||||
void rtl8192du_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
|
||||
int rtl8192du_init_recv_priv(_adapter * padapter);
|
||||
void rtl8192du_free_recv_priv(_adapter * padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
int rtl8192de_init_recv_priv(_adapter * padapter);
|
||||
void rtl8192de_free_recv_priv(_adapter * padapter);
|
||||
#endif
|
||||
|
||||
void rtl8192d_translate_rx_signal_stuff(union recv_frame *precvframe, struct phy_stat *pphy_status);
|
||||
void rtl8192d_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *pdesc);
|
||||
|
||||
#endif
|
|
@ -1,96 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
*
|
||||
*
|
||||
* Module: rtl8192d_rf.h ( Header File)
|
||||
*
|
||||
* Note: Collect every HAL RF type exter API or constant.
|
||||
*
|
||||
* Function:
|
||||
*
|
||||
* Export:
|
||||
*
|
||||
* Abbrev:
|
||||
*
|
||||
* History:
|
||||
* Data Who Remark
|
||||
*
|
||||
* 09/25/2008 MHC Create initial version.
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef _RTL8192D_RF_H_
|
||||
#define _RTL8192D_RF_H_
|
||||
/* Check to see if the file has been included already. */
|
||||
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
|
||||
//
|
||||
// For RF 6052 Series
|
||||
//
|
||||
#define RF6052_MAX_TX_PWR 0x3F
|
||||
#define RF6052_MAX_REG 0x3F
|
||||
#define RF6052_MAX_PATH 2
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
|
||||
|
||||
/*------------------------------Define structure----------------------------*/
|
||||
|
||||
/*------------------------------Define structure----------------------------*/
|
||||
|
||||
|
||||
/*------------------------Export global variable----------------------------*/
|
||||
/*------------------------Export global variable----------------------------*/
|
||||
|
||||
/*------------------------Export Marco Definition---------------------------*/
|
||||
|
||||
/*------------------------Export Marco Definition---------------------------*/
|
||||
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
|
||||
//
|
||||
// RF RL6052 Series API
|
||||
//
|
||||
void rtl8192d_RF_ChangeTxPath( PADAPTER Adapter,
|
||||
u16 DataRate);
|
||||
void rtl8192d_PHY_RF6052SetBandwidth(
|
||||
PADAPTER Adapter,
|
||||
HT_CHANNEL_WIDTH Bandwidth);
|
||||
void rtl8192d_PHY_RF6052SetCckTxPower(
|
||||
PADAPTER Adapter,
|
||||
u8* pPowerlevel);
|
||||
void rtl8192d_PHY_RF6052SetOFDMTxPower(
|
||||
PADAPTER Adapter,
|
||||
u8* pPowerLevel,
|
||||
u8 Channel);
|
||||
int PHY_RF6052_Config8192D( PADAPTER Adapter );
|
||||
|
||||
bool rtl8192d_PHY_EnableAnotherPHY( PADAPTER Adapter, bool bMac0);
|
||||
|
||||
void rtl8192d_PHY_PowerDownAnotherPHY(IN PADAPTER Adapter, IN bool bMac0);
|
||||
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
|
||||
|
||||
#endif/* End of HalRf.h */
|
File diff suppressed because it is too large
Load diff
|
@ -1,180 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef _RTL8192D_XMIT_H_
|
||||
#define _RTL8192D_XMIT_H_
|
||||
|
||||
//
|
||||
//defined for TX DESC Operation
|
||||
//
|
||||
|
||||
#define MAX_TID (15)
|
||||
|
||||
//OFFSET 0
|
||||
#define OFFSET_SZ 0
|
||||
#define OFFSET_SHT 16
|
||||
#define BMC BIT(24)
|
||||
#define LSG BIT(26)
|
||||
#define FSG BIT(27)
|
||||
#define OWN BIT(31)
|
||||
|
||||
|
||||
//OFFSET 4
|
||||
#define PKT_OFFSET_SZ 0
|
||||
#define BK BIT(6)
|
||||
#define QSEL_SHT 8
|
||||
#define Rate_ID_SHT 16
|
||||
#define NAVUSEHDR BIT(20)
|
||||
#define PKT_OFFSET_SHT 26
|
||||
#define HWPC BIT(31)
|
||||
|
||||
//OFFSET 8
|
||||
#define AGG_EN BIT(29)
|
||||
|
||||
//OFFSET 12
|
||||
#define SEQ_SHT 16
|
||||
|
||||
//OFFSET 16
|
||||
#define QoS BIT(6)
|
||||
#define HW_SEQ_EN BIT(7)
|
||||
#define USERATE BIT(8)
|
||||
#define DISDATAFB BIT(10)
|
||||
#define DATA_SHORT BIT(24)
|
||||
#define DATA_BW BIT(25)
|
||||
|
||||
//OFFSET 20
|
||||
#define SGI BIT(6)
|
||||
|
||||
//
|
||||
// Queue Select Value in TxDesc
|
||||
//
|
||||
#define QSLT_BK 0x2//0x01
|
||||
#define QSLT_BE 0x0
|
||||
#define QSLT_VI 0x5//0x4
|
||||
#define QSLT_VO 0x7//0x6
|
||||
#define QSLT_BEACON 0x10
|
||||
#define QSLT_HIGH 0x11
|
||||
#define QSLT_MGNT 0x12
|
||||
#define QSLT_CMD 0x13
|
||||
|
||||
//Because we open EM for normal case, we just always insert 2*8 bytes.by wl
|
||||
#define USB_92D_DUMMY_OFFSET 2
|
||||
#define USB_92D_DUMMY_LENGTH (USB_92D_DUMMY_OFFSET * PACKET_OFFSET_SZ)
|
||||
#define USB_HWDESC_HEADER_LEN (TXDESC_SIZE + USB_92D_DUMMY_LENGTH)
|
||||
|
||||
//For 92D early mode
|
||||
#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
|
||||
#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
|
||||
#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
|
||||
#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)
|
||||
#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)
|
||||
#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
|
||||
#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
|
||||
|
||||
/* Copy from rtl8192c */
|
||||
struct txrpt_ccx_8192d {
|
||||
/* offset 0 */
|
||||
u8 retry_cnt:6;
|
||||
u8 rsvd_0:2;
|
||||
|
||||
/* offset 1 */
|
||||
u8 rts_retry_cnt:6;
|
||||
u8 rsvd_1:2;
|
||||
|
||||
/* offset 2 */
|
||||
u8 ccx_qtime0;
|
||||
u8 ccx_qtime1;
|
||||
|
||||
/* offset 4 */
|
||||
u8 missed_pkt_num:5;
|
||||
u8 rsvd_4:3;
|
||||
|
||||
/* offset 5 */
|
||||
u8 mac_id:5;
|
||||
u8 des1_fragssn:3;
|
||||
|
||||
/* offset 6 */
|
||||
u8 rpt_pkt_num:5;
|
||||
u8 pkt_drop:1;
|
||||
u8 lifetime_over:1;
|
||||
u8 retry_over:1;
|
||||
|
||||
/* offset 7*/
|
||||
u8 edca_tx_queue:4;
|
||||
u8 rsvd_7:1;
|
||||
u8 bmc:1;
|
||||
u8 pkt_ok:1;
|
||||
u8 int_ccx:1;
|
||||
};
|
||||
|
||||
#define txrpt_ccx_qtime_8192d(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
|
||||
|
||||
#ifdef CONFIG_XMIT_ACK
|
||||
void dump_txrpt_ccx_8192d(void *buf);
|
||||
void handle_txrpt_ccx_8192d(_adapter *adapter, void *buf);
|
||||
#else
|
||||
#define dump_txrpt_ccx_8192d(buf) do {} while (0)
|
||||
#define handle_txrpt_ccx_8192d(adapter, buf) do {} while (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
|
||||
#ifdef CONFIG_USB_TX_AGGREGATION
|
||||
#define MAX_TX_AGG_PACKET_NUMBER 0xFF
|
||||
#endif
|
||||
|
||||
s32 rtl8192du_init_xmit_priv(_adapter * padapter);
|
||||
|
||||
void rtl8192du_free_xmit_priv(_adapter * padapter);
|
||||
|
||||
void rtl8192du_cal_txdesc_chksum(struct tx_desc *ptxdesc);
|
||||
|
||||
s32 rtl8192du_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
|
||||
|
||||
s32 rtl8192du_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);
|
||||
|
||||
s32 rtl8192du_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
|
||||
#ifdef CONFIG_HOSTAPD_MLME
|
||||
s32 rtl8192du_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
s32 rtl8192de_init_xmit_priv(_adapter * padapter);
|
||||
void rtl8192de_free_xmit_priv(_adapter * padapter);
|
||||
|
||||
s32 rtl8192de_enqueue_xmitbuf(struct rtw_tx_ring *ring, struct xmit_buf *pxmitbuf);
|
||||
struct xmit_buf *rtl8192de_dequeue_xmitbuf(struct rtw_tx_ring *ring);
|
||||
|
||||
void rtl8192de_xmitframe_resume(_adapter *padapter);
|
||||
|
||||
s32 rtl8192de_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);
|
||||
|
||||
s32 rtl8192de_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
|
||||
#ifdef CONFIG_HOSTAPD_MLME
|
||||
s32 rtl8192de_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
File diff suppressed because it is too large
Load diff
|
@ -1,173 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __RTL8723A_CMD_H__
|
||||
#define __RTL8723A_CMD_H__
|
||||
|
||||
|
||||
#define H2C_BT_FW_PATCH_LEN 3
|
||||
#define H2C_BT_PWR_FORCE_LEN 3
|
||||
|
||||
enum cmd_msg_element_id
|
||||
{
|
||||
NONE_CMDMSG_EID,
|
||||
AP_OFFLOAD_EID = 0,
|
||||
SET_PWRMODE_EID = 1,
|
||||
JOINBSS_RPT_EID = 2,
|
||||
RSVD_PAGE_EID = 3,
|
||||
RSSI_4_EID = 4,
|
||||
RSSI_SETTING_EID = 5,
|
||||
MACID_CONFIG_EID = 6,
|
||||
MACID_PS_MODE_EID = 7,
|
||||
P2P_PS_OFFLOAD_EID = 8,
|
||||
SELECTIVE_SUSPEND_ROF_CMD = 9,
|
||||
BT_QUEUE_PKT_EID = 17,
|
||||
BT_ANT_TDMA_EID = 20,
|
||||
BT_2ANT_HID_EID = 21,
|
||||
P2P_PS_CTW_CMD_EID = 32,
|
||||
FORCE_BT_TX_PWR_EID = 33,
|
||||
SET_TDMA_WLAN_ACT_TIME_EID = 34,
|
||||
SET_BT_TX_RETRY_INDEX_EID = 35,
|
||||
HID_PROFILE_ENABLE_EID = 36,
|
||||
BT_IGNORE_WLAN_ACT_EID = 37,
|
||||
BT_PTA_MANAGER_UPDATE_ENABLE_EID = 38,
|
||||
DAC_SWING_VALUE_EID = 41,
|
||||
TRADITIONAL_TDMA_EN_EID = 51,
|
||||
H2C_BT_FW_PATCH = 54,
|
||||
B_TYPE_TDMA_EID = 58,
|
||||
SCAN_EN_EID = 59,
|
||||
LOWPWR_LPS_EID = 71,
|
||||
H2C_RESET_TSF = 75,
|
||||
MAX_CMDMSG_EID
|
||||
};
|
||||
|
||||
struct cmd_msg_parm {
|
||||
u8 eid; //element id
|
||||
u8 sz; // sz
|
||||
u8 buf[6];
|
||||
};
|
||||
|
||||
typedef struct _SETPWRMODE_PARM
|
||||
{
|
||||
u8 Mode;
|
||||
u8 SmartPS;
|
||||
u8 AwakeInterval; // unit: beacon interval
|
||||
u8 bAllQueueUAPSD;
|
||||
|
||||
#define SETPM_LOWRXBCN BIT(0)
|
||||
#define SETPM_AUTOANTSWITCH BIT(1)
|
||||
#define SETPM_PSALLOWBTHIGHPRI BIT(2)
|
||||
u8 BcnAntMode;
|
||||
}__attribute__((__packed__)) SETPWRMODE_PARM, *PSETPWRMODE_PARM;
|
||||
|
||||
struct H2C_SS_RFOFF_PARAM{
|
||||
u8 ROFOn; // 1: on, 0:off
|
||||
u16 gpio_period; // unit: 1024 us
|
||||
}__attribute__ ((packed));
|
||||
|
||||
|
||||
typedef struct JOINBSSRPT_PARM{
|
||||
u8 OpMode; // RT_MEDIA_STATUS
|
||||
}JOINBSSRPT_PARM, *PJOINBSSRPT_PARM;
|
||||
|
||||
typedef struct _RSVDPAGE_LOC {
|
||||
u8 LocProbeRsp;
|
||||
u8 LocPsPoll;
|
||||
u8 LocNullData;
|
||||
u8 LocQosNull;
|
||||
u8 LocBTQosNull;
|
||||
} RSVDPAGE_LOC, *PRSVDPAGE_LOC;
|
||||
|
||||
struct P2P_PS_Offload_t {
|
||||
u8 Offload_En:1;
|
||||
u8 role:1; // 1: Owner, 0: Client
|
||||
u8 CTWindow_En:1;
|
||||
u8 NoA0_En:1;
|
||||
u8 NoA1_En:1;
|
||||
u8 AllStaSleep:1; // Only valid in Owner
|
||||
u8 discovery:1;
|
||||
u8 rsvd:1;
|
||||
};
|
||||
|
||||
struct P2P_PS_CTWPeriod_t {
|
||||
u8 CTWPeriod; //TU
|
||||
};
|
||||
|
||||
|
||||
typedef struct _B_TYPE_TDMA_PARM
|
||||
{
|
||||
#define B_TDMA_EN BIT(0)
|
||||
#define B_TDMA_FIXANTINBT BIT(1)
|
||||
#define B_TDMA_TXPSPOLL BIT(2)
|
||||
#define B_TDMA_VAL870 BIT(3)
|
||||
#define B_TDMA_AUTOWAKEUP BIT(4)
|
||||
#define B_TDMA_NOPS BIT(5)
|
||||
#define B_TDMA_WLANHIGHPRI BIT(6)
|
||||
u8 option;
|
||||
|
||||
u8 TBTTOnPeriod;
|
||||
u8 MedPeriod;
|
||||
u8 rsvd30;
|
||||
}__attribute__((__packed__)) B_TYPE_TDMA_PARM, *PB_TYPE_TDMA_PARM;
|
||||
|
||||
typedef struct _SCAN_EN_PARM {
|
||||
u8 En;
|
||||
}__attribute__((__packed__)) SCAN_EN_PARM, *PSCAN_EN_PARM;
|
||||
|
||||
// BT_PWR
|
||||
#define SET_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value)
|
||||
|
||||
// BT_FW_PATCH
|
||||
#define SET_H2CCMD_BT_FW_PATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_4BYTE(__pH2CCmd, 0, 8, __Value) // SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_4BYTE(__pH2CCmd, 8, 16, __Value) // SET_BITS_TO_LE_2BYTE((__pH2CCmd)+1, 0, 16, __Value)
|
||||
|
||||
typedef struct _LOWPWR_LPS_PARM
|
||||
{
|
||||
u8 bcn_count:4;
|
||||
u8 tb_bcn_threshold:3;
|
||||
u8 enable:1;
|
||||
u8 bcn_interval;
|
||||
u8 drop_threshold;
|
||||
u8 max_early_period;
|
||||
u8 max_bcn_timeout_period;
|
||||
}__attribute__((__packed__)) LOWPWR_LPS_PARM, *PLOWPWR_LPS_PARM;
|
||||
|
||||
|
||||
// host message to firmware cmd
|
||||
void rtl8723a_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
|
||||
void rtl8723a_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
void rtl8723a_set_BTCoex_AP_mode_FwRsvdPkt_cmd(PADAPTER padapter);
|
||||
#endif
|
||||
u8 rtl8192c_set_rssi_cmd(PADAPTER padapter, u8 *param);
|
||||
u8 rtl8192c_set_raid_cmd(PADAPTER padapter, u32 mask, u8 arg);
|
||||
void rtl8192c_Add_RateATid(PADAPTER padapter, u32 bitmap, u8 arg, u8 rssi_level);
|
||||
u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period);
|
||||
|
||||
#ifdef CONFIG_P2P
|
||||
void rtl8192c_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
|
||||
#endif //CONFIG_P2P
|
||||
|
||||
void CheckFwRsvdPageContent(PADAPTER padapter);
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TSF_RESET_OFFLOAD
|
||||
u8 rtl8723c_reset_tsf(_adapter *padapter, u8 reset_port);
|
||||
#endif // CONFIG_TSF_RESET_OFFLOAD
|
|
@ -1,193 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __RTL8723A_DM_H__
|
||||
#define __RTL8723A_DM_H__
|
||||
//============================================================
|
||||
// Description:
|
||||
//
|
||||
// This file is for 8723A dynamic mechanism only
|
||||
//
|
||||
//
|
||||
//============================================================
|
||||
#define DYNAMIC_FUNC_BT BIT(0)
|
||||
|
||||
enum{
|
||||
UP_LINK,
|
||||
DOWN_LINK,
|
||||
};
|
||||
//============================================================
|
||||
// structure and define
|
||||
//============================================================
|
||||
|
||||
//###### duplicate code,will move to ODM #########
|
||||
#define IQK_MAC_REG_NUM 4
|
||||
#define IQK_ADDA_REG_NUM 16
|
||||
#define IQK_BB_REG_NUM 9
|
||||
#define HP_THERMAL_NUM 8
|
||||
//###### duplicate code,will move to ODM #########
|
||||
struct dm_priv
|
||||
{
|
||||
u8 DM_Type;
|
||||
u8 DMFlag;
|
||||
u8 InitDMFlag;
|
||||
u32 InitODMFlag;
|
||||
|
||||
//* Upper and Lower Signal threshold for Rate Adaptive*/
|
||||
int UndecoratedSmoothedPWDB;
|
||||
int UndecoratedSmoothedCCK;
|
||||
int EntryMinUndecoratedSmoothedPWDB;
|
||||
int EntryMaxUndecoratedSmoothedPWDB;
|
||||
int MinUndecoratedPWDBForDM;
|
||||
int LastMinUndecoratedPWDBForDM;
|
||||
|
||||
s32 UndecoratedSmoothedBeacon;
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
s32 BT_EntryMinUndecoratedSmoothedPWDB;
|
||||
s32 BT_EntryMaxUndecoratedSmoothedPWDB;
|
||||
#endif
|
||||
|
||||
//###### duplicate code,will move to ODM #########
|
||||
/*
|
||||
//for DIG
|
||||
u8 bDMInitialGainEnable;
|
||||
u8 binitialized; // for dm_initial_gain_Multi_STA use.
|
||||
DIG_T DM_DigTable;
|
||||
|
||||
PS_T DM_PSTable;
|
||||
|
||||
FALSE_ALARM_STATISTICS FalseAlmCnt;
|
||||
|
||||
//for rate adaptive, in fact, 88c/92c fw will handle this
|
||||
u8 bUseRAMask;
|
||||
RATE_ADAPTIVE RateAdaptive;
|
||||
*/
|
||||
//for High Power
|
||||
u8 bDynamicTxPowerEnable;
|
||||
u8 LastDTPLvl;
|
||||
u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06
|
||||
|
||||
//for tx power tracking
|
||||
u8 bTXPowerTracking;
|
||||
u8 TXPowercount;
|
||||
u8 bTXPowerTrackingInit;
|
||||
u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
|
||||
u8 TM_Trigger;
|
||||
|
||||
u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
|
||||
u8 ThermalValue;
|
||||
u8 ThermalValue_LCK;
|
||||
u8 ThermalValue_IQK;
|
||||
u8 ThermalValue_DPK;
|
||||
|
||||
u8 bRfPiEnable;
|
||||
|
||||
//for APK
|
||||
u32 APKoutput[2][2]; //path A/B; output1_1a/output1_2a
|
||||
u8 bAPKdone;
|
||||
u8 bAPKThermalMeterIgnore;
|
||||
u8 bDPdone;
|
||||
u8 bDPPathAOK;
|
||||
u8 bDPPathBOK;
|
||||
|
||||
//for IQK
|
||||
u32 RegC04;
|
||||
u32 Reg874;
|
||||
u32 RegC08;
|
||||
u32 RegB68;
|
||||
u32 RegB6C;
|
||||
u32 Reg870;
|
||||
u32 Reg860;
|
||||
u32 Reg864;
|
||||
u32 ADDA_backup[IQK_ADDA_REG_NUM];
|
||||
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
|
||||
u32 IQK_BB_backup_recover[9];
|
||||
u32 IQK_BB_backup[IQK_BB_REG_NUM];
|
||||
u8 PowerIndex_backup[6];
|
||||
|
||||
u8 bCCKinCH14;
|
||||
|
||||
u8 CCK_index;
|
||||
u8 OFDM_index[2];
|
||||
|
||||
u8 bDoneTxpower;
|
||||
u8 CCK_index_HP;
|
||||
u8 OFDM_index_HP[2];
|
||||
u8 ThermalValue_HP[HP_THERMAL_NUM];
|
||||
u8 ThermalValue_HP_index;
|
||||
|
||||
//for TxPwrTracking
|
||||
s32 RegE94;
|
||||
s32 RegE9C;
|
||||
s32 RegEB4;
|
||||
s32 RegEBC;
|
||||
|
||||
u32 TXPowerTrackingCallbackCnt; //cosa add for debug
|
||||
|
||||
u32 prv_traffic_idx; // edca turbo
|
||||
|
||||
/*
|
||||
// for dm_RF_Saving
|
||||
u8 initialize;
|
||||
u32 rf_saving_Reg874;
|
||||
u32 rf_saving_RegC70;
|
||||
u32 rf_saving_Reg85C;
|
||||
u32 rf_saving_RegA74;
|
||||
*/
|
||||
//for Antenna diversity
|
||||
#ifdef CONFIG_ANTENNA_DIVERSITY
|
||||
// SWAT_T DM_SWAT_Table;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
|
||||
// _timer SwAntennaSwitchTimer;
|
||||
/*
|
||||
u64 lastTxOkCnt;
|
||||
u64 lastRxOkCnt;
|
||||
u64 TXByteCnt_A;
|
||||
u64 TXByteCnt_B;
|
||||
u64 RXByteCnt_A;
|
||||
u64 RXByteCnt_B;
|
||||
u8 DoubleComfirm;
|
||||
u8 TrafficLoad;
|
||||
*/
|
||||
#endif
|
||||
|
||||
s32 OFDM_Pkt_Cnt;
|
||||
u8 RSSI_Select;
|
||||
// u8 DIG_Dynamic_MIN ;
|
||||
//###### duplicate code,will move to ODM #########
|
||||
// Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas
|
||||
u8 INIDATA_RATE[32];
|
||||
};
|
||||
|
||||
|
||||
//============================================================
|
||||
// function prototype
|
||||
//============================================================
|
||||
|
||||
void rtl8723a_init_dm_priv(PADAPTER padapter);
|
||||
void rtl8723a_deinit_dm_priv(PADAPTER padapter);
|
||||
|
||||
void rtl8723a_InitHalDm(PADAPTER padapter);
|
||||
void rtl8723a_HalDmWatchDog(PADAPTER padapter);
|
||||
|
||||
|
||||
|
||||
#endif
|
|
@ -1,835 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __RTL8723A_HAL_H__
|
||||
#define __RTL8723A_HAL_H__
|
||||
|
||||
#include "rtl8723a_spec.h"
|
||||
#include "rtl8723a_pg.h"
|
||||
#include "Hal8723APhyReg.h"
|
||||
#include "Hal8723APhyCfg.h"
|
||||
#include "rtl8723a_rf.h"
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
#include "rtl8723a_bt-coexist.h"
|
||||
#endif
|
||||
#include "rtl8723a_dm.h"
|
||||
#include "rtl8723a_recv.h"
|
||||
#include "rtl8723a_xmit.h"
|
||||
#include "rtl8723a_cmd.h"
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
#include "rtl8723a_sreset.h"
|
||||
#endif
|
||||
#include "rtw_efuse.h"
|
||||
|
||||
#include "../hal/OUTSRC/odm_precomp.h"
|
||||
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
|
||||
//2TODO: We should define 8192S firmware related macro settings here!!
|
||||
#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
|
||||
#define RTL819X_TOTAL_RF_PATH 2
|
||||
|
||||
//---------------------------------------------------------------------
|
||||
// RTL8723S From file
|
||||
//---------------------------------------------------------------------
|
||||
#define RTL8723_FW_UMC_IMG "rtl8723S\\rtl8723fw.bin"
|
||||
#define RTL8723_FW_UMC_B_IMG "rtl8723S\\rtl8723fw_B.bin"
|
||||
#define RTL8723_PHY_REG "rtl8723S\\PHY_REG_1T.txt"
|
||||
#define RTL8723_PHY_RADIO_A "rtl8723S\\radio_a_1T.txt"
|
||||
#define RTL8723_PHY_RADIO_B "rtl8723S\\radio_b_1T.txt"
|
||||
#define RTL8723_AGC_TAB "rtl8723S\\AGC_TAB_1T.txt"
|
||||
#define RTL8723_PHY_MACREG "rtl8723S\\MAC_REG.txt"
|
||||
#define RTL8723_PHY_REG_PG "rtl8723S\\PHY_REG_PG.txt"
|
||||
#define RTL8723_PHY_REG_MP "rtl8723S\\PHY_REG_MP.txt"
|
||||
|
||||
//---------------------------------------------------------------------
|
||||
// RTL8723S From header
|
||||
//---------------------------------------------------------------------
|
||||
|
||||
// Fw Array
|
||||
#define Rtl8723_FwImageArray Rtl8723SFwImgArray
|
||||
#define Rtl8723_FwUMCBCutImageArray Rtl8723SFwUMCBCutImgArray
|
||||
|
||||
#define Rtl8723_ImgArrayLength Rtl8723SImgArrayLength
|
||||
#define Rtl8723_UMCBCutImgArrayLength Rtl8723SUMCBCutImgArrayLength
|
||||
|
||||
#define Rtl8723_PHY_REG_Array_PG Rtl8723SPHY_REG_Array_PG
|
||||
#define Rtl8723_PHY_REG_Array_PGLength Rtl8723SPHY_REG_Array_PGLength
|
||||
#if MP_DRIVER == 1
|
||||
#define Rtl8723E_FwBTImgArray Rtl8723EFwBTImgArray
|
||||
#define Rtl8723E_FwBTImgArrayLength Rtl8723EBTImgArrayLength
|
||||
|
||||
#define Rtl8723_FwUMCBCutMPImageArray Rtl8723SFwUMCBCutMPImgArray
|
||||
#define Rtl8723_UMCBCutMPImgArrayLength Rtl8723SUMCBCutMPImgArrayLength
|
||||
|
||||
#define Rtl8723_PHY_REG_Array_MP Rtl8723SPHY_REG_Array_MP
|
||||
#define Rtl8723_PHY_REG_Array_MPLength Rtl8723SPHY_REG_Array_MPLength
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PHY_SETTING_WITH_ODM
|
||||
// MAC/BB/PHY Array
|
||||
#define Rtl8723_MAC_Array Rtl8723SMAC_2T_Array
|
||||
//#define Rtl8723_AGCTAB_2TArray Rtl8723SAGCTAB_2TArray
|
||||
#define Rtl8723_AGCTAB_1TArray Rtl8723SAGCTAB_1TArray
|
||||
//#define Rtl8723_PHY_REG_2TArray Rtl8723SPHY_REG_2TArray
|
||||
#define Rtl8723_PHY_REG_1TArray Rtl8723SPHY_REG_1TArray
|
||||
//#define Rtl8723_RadioA_2TArray Rtl8723SRadioA_2TArray
|
||||
#define Rtl8723_RadioA_1TArray Rtl8723SRadioA_1TArray
|
||||
//#define Rtl8723_RadioB_2TArray Rtl8723SRadioB_2TArray
|
||||
#define Rtl8723_RadioB_1TArray Rtl8723SRadioB_1TArray
|
||||
|
||||
// Array length
|
||||
#define Rtl8723_MAC_ArrayLength Rtl8723SMAC_2T_ArrayLength
|
||||
#define Rtl8723_AGCTAB_1TArrayLength Rtl8723SAGCTAB_1TArrayLength
|
||||
#define Rtl8723_PHY_REG_1TArrayLength Rtl8723SPHY_REG_1TArrayLength
|
||||
|
||||
#define Rtl8723_RadioA_1TArrayLength Rtl8723SRadioA_1TArrayLength
|
||||
#define Rtl8723_RadioB_1TArrayLength Rtl8723SRadioB_1TArrayLength
|
||||
#endif // CONFIG_PHY_SETTING_WITH_ODM
|
||||
#endif // CONFIG_SDIO_HCI
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
|
||||
//2TODO: We should define 8192S firmware related macro settings here!!
|
||||
#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
|
||||
#define RTL819X_TOTAL_RF_PATH 2
|
||||
|
||||
//TODO: The following need to check!!
|
||||
#define RTL8723_FW_UMC_IMG "rtl8192CU\\rtl8723fw.bin"
|
||||
#define RTL8723_FW_UMC_B_IMG "rtl8192CU\\rtl8723fw_B.bin"
|
||||
#define RTL8723_PHY_REG "rtl8723S\\PHY_REG_1T.txt"
|
||||
#define RTL8723_PHY_RADIO_A "rtl8723S\\radio_a_1T.txt"
|
||||
#define RTL8723_PHY_RADIO_B "rtl8723S\\radio_b_1T.txt"
|
||||
#define RTL8723_AGC_TAB "rtl8723S\\AGC_TAB_1T.txt"
|
||||
#define RTL8723_PHY_MACREG "rtl8723S\\MAC_REG.txt"
|
||||
#define RTL8723_PHY_REG_PG "rtl8723S\\PHY_REG_PG.txt"
|
||||
#define RTL8723_PHY_REG_MP "rtl8723S\\PHY_REG_MP.txt"
|
||||
|
||||
//---------------------------------------------------------------------
|
||||
// RTL8723S From header
|
||||
//---------------------------------------------------------------------
|
||||
|
||||
// Fw Array
|
||||
#define Rtl8723_FwImageArray Rtl8723UFwImgArray
|
||||
#define Rtl8723_FwUMCBCutImageArray Rtl8723UFwUMCBCutImgArray
|
||||
|
||||
#define Rtl8723_ImgArrayLength Rtl8723UImgArrayLength
|
||||
#define Rtl8723_UMCBCutImgArrayLength Rtl8723UUMCBCutImgArrayLength
|
||||
|
||||
#define Rtl8723_PHY_REG_Array_PG Rtl8723UPHY_REG_Array_PG
|
||||
#define Rtl8723_PHY_REG_Array_PGLength Rtl8723UPHY_REG_Array_PGLength
|
||||
|
||||
#if MP_DRIVER == 1
|
||||
#define Rtl8723E_FwBTImgArray Rtl8723EFwBTImgArray
|
||||
#define Rtl8723E_FwBTImgArrayLength Rtl8723EBTImgArrayLength
|
||||
|
||||
#define Rtl8723_FwUMCBCutMPImageArray Rtl8723SFwUMCBCutMPImgArray
|
||||
#define Rtl8723_UMCBCutMPImgArrayLength Rtl8723SUMCBCutMPImgArrayLength
|
||||
|
||||
#define Rtl8723_PHY_REG_Array_MP Rtl8723UPHY_REG_Array_MP
|
||||
#define Rtl8723_PHY_REG_Array_MPLength Rtl8723UPHY_REG_Array_MPLength
|
||||
#endif
|
||||
#ifndef CONFIG_PHY_SETTING_WITH_ODM
|
||||
// MAC/BB/PHY Array
|
||||
#define Rtl8723_MAC_Array Rtl8723UMAC_2T_Array
|
||||
//#define Rtl8723_AGCTAB_2TArray Rtl8723UAGCTAB_2TArray
|
||||
#define Rtl8723_AGCTAB_1TArray Rtl8723UAGCTAB_1TArray
|
||||
//#define Rtl8723_PHY_REG_2TArray Rtl8723UPHY_REG_2TArray
|
||||
#define Rtl8723_PHY_REG_1TArray Rtl8723UPHY_REG_1TArray
|
||||
//#define Rtl8723_RadioA_2TArray Rtl8723URadioA_2TArray
|
||||
#define Rtl8723_RadioA_1TArray Rtl8723URadioA_1TArray
|
||||
//#define Rtl8723_RadioB_2TArray Rtl8723URadioB_2TArray
|
||||
#define Rtl8723_RadioB_1TArray Rtl8723URadioB_1TArray
|
||||
|
||||
|
||||
|
||||
// Array length
|
||||
|
||||
#define Rtl8723_MAC_ArrayLength Rtl8723UMAC_2T_ArrayLength
|
||||
#define Rtl8723_AGCTAB_1TArrayLength Rtl8723UAGCTAB_1TArrayLength
|
||||
#define Rtl8723_PHY_REG_1TArrayLength Rtl8723UPHY_REG_1TArrayLength
|
||||
|
||||
|
||||
#define Rtl8723_RadioA_1TArrayLength Rtl8723URadioA_1TArrayLength
|
||||
#define Rtl8723_RadioB_1TArrayLength Rtl8723URadioB_1TArrayLength
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define DRVINFO_SZ 4 // unit is 8bytes
|
||||
#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
|
||||
|
||||
#define FW_8723A_SIZE 0x8000
|
||||
#define FW_8723A_START_ADDRESS 0x1000
|
||||
#define FW_8723A_END_ADDRESS 0x1FFF //0x5FFF
|
||||
|
||||
#define MAX_PAGE_SIZE 4096 // @ page : 4k bytes
|
||||
|
||||
#define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
|
||||
(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\
|
||||
(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300)
|
||||
|
||||
typedef enum _FIRMWARE_SOURCE {
|
||||
FW_SOURCE_IMG_FILE = 0,
|
||||
FW_SOURCE_HEADER_FILE = 1, //from header file
|
||||
} FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;
|
||||
|
||||
typedef struct _RT_FIRMWARE {
|
||||
FIRMWARE_SOURCE eFWSource;
|
||||
#ifdef CONFIG_EMBEDDED_FWIMG
|
||||
u8* szFwBuffer;
|
||||
#else
|
||||
u8 szFwBuffer[FW_8723A_SIZE];
|
||||
#endif
|
||||
u32 ulFwLength;
|
||||
|
||||
#ifdef CONFIG_EMBEDDED_FWIMG
|
||||
u8* szBTFwBuffer;
|
||||
#else
|
||||
u8 szBTFwBuffer[FW_8723A_SIZE];
|
||||
#endif
|
||||
u32 ulBTFwLength;
|
||||
} RT_FIRMWARE, *PRT_FIRMWARE, RT_FIRMWARE_8723A, *PRT_FIRMWARE_8723A;
|
||||
|
||||
//
|
||||
// This structure must be cared byte-ordering
|
||||
//
|
||||
// Added by tynli. 2009.12.04.
|
||||
typedef struct _RT_8723A_FIRMWARE_HDR
|
||||
{
|
||||
// 8-byte alinment required
|
||||
|
||||
//--- LONG WORD 0 ----
|
||||
u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut
|
||||
u8 Category; // AP/NIC and USB/PCI
|
||||
u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions
|
||||
u16 Version; // FW Version
|
||||
u8 Subversion; // FW Subversion, default 0x00
|
||||
u16 Rsvd1;
|
||||
|
||||
|
||||
//--- LONG WORD 1 ----
|
||||
u8 Month; // Release time Month field
|
||||
u8 Date; // Release time Date field
|
||||
u8 Hour; // Release time Hour field
|
||||
u8 Minute; // Release time Minute field
|
||||
u16 RamCodeSize; // The size of RAM code
|
||||
u16 Rsvd2;
|
||||
|
||||
//--- LONG WORD 2 ----
|
||||
u32 SvnIdx; // The SVN entry index
|
||||
u32 Rsvd3;
|
||||
|
||||
//--- LONG WORD 3 ----
|
||||
u32 Rsvd4;
|
||||
u32 Rsvd5;
|
||||
}RT_8723A_FIRMWARE_HDR, *PRT_8723A_FIRMWARE_HDR;
|
||||
|
||||
#define DRIVER_EARLY_INT_TIME 0x05
|
||||
#define BCN_DMA_ATIME_INT_TIME 0x02
|
||||
|
||||
#ifdef CONFIG_USB_RX_AGGREGATION
|
||||
|
||||
typedef enum _USB_RX_AGG_MODE{
|
||||
USB_RX_AGG_DISABLE,
|
||||
USB_RX_AGG_DMA,
|
||||
USB_RX_AGG_USB,
|
||||
USB_RX_AGG_MIX
|
||||
}USB_RX_AGG_MODE;
|
||||
|
||||
#define MAX_RX_DMA_BUFFER_SIZE 10240 // 10K for 8192C RX DMA buffer
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
// BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
|
||||
#define MAX_TX_QUEUE 9
|
||||
|
||||
#define TX_SELE_HQ BIT(0) // High Queue
|
||||
#define TX_SELE_LQ BIT(1) // Low Queue
|
||||
#define TX_SELE_NQ BIT(2) // Normal Queue
|
||||
|
||||
// Note: We will divide number of page equally for each queue other than public queue!
|
||||
#define TX_TOTAL_PAGE_NUMBER 0xF8
|
||||
#define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER + 1)
|
||||
|
||||
// For Normal Chip Setting
|
||||
// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER
|
||||
#define NORMAL_PAGE_NUM_PUBQ 0xE7
|
||||
#define NORMAL_PAGE_NUM_HPQ 0x0C
|
||||
#define NORMAL_PAGE_NUM_LPQ 0x02
|
||||
#define NORMAL_PAGE_NUM_NPQ 0x02
|
||||
|
||||
// For Test Chip Setting
|
||||
// (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER
|
||||
#define TEST_PAGE_NUM_PUBQ 0x7E
|
||||
|
||||
// For Test Chip Setting
|
||||
#define WMM_TEST_TX_TOTAL_PAGE_NUMBER 0xF5
|
||||
#define WMM_TEST_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
|
||||
|
||||
#define WMM_TEST_PAGE_NUM_PUBQ 0xA3
|
||||
#define WMM_TEST_PAGE_NUM_HPQ 0x29
|
||||
#define WMM_TEST_PAGE_NUM_LPQ 0x29
|
||||
|
||||
// Note: For Normal Chip Setting, modify later
|
||||
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5
|
||||
#define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
|
||||
|
||||
#define WMM_NORMAL_PAGE_NUM_PUBQ 0xB0
|
||||
#define WMM_NORMAL_PAGE_NUM_HPQ 0x29
|
||||
#define WMM_NORMAL_PAGE_NUM_LPQ 0x1C
|
||||
#define WMM_NORMAL_PAGE_NUM_NPQ 0x1C
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// Chip specific
|
||||
//-------------------------------------------------------------------------
|
||||
#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
|
||||
#define CHIP_BONDING_92C_1T2R 0x1
|
||||
#define CHIP_BONDING_88C_USB_MCARD 0x2
|
||||
#define CHIP_BONDING_88C_USB_HP 0x1
|
||||
|
||||
#include "HalVerDef.h"
|
||||
#include "hal_com.h"
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// Channel Plan
|
||||
//-------------------------------------------------------------------------
|
||||
enum ChannelPlan
|
||||
{
|
||||
CHPL_FCC = 0,
|
||||
CHPL_IC = 1,
|
||||
CHPL_ETSI = 2,
|
||||
CHPL_SPA = 3,
|
||||
CHPL_FRANCE = 4,
|
||||
CHPL_MKK = 5,
|
||||
CHPL_MKK1 = 6,
|
||||
CHPL_ISRAEL = 7,
|
||||
CHPL_TELEC = 8,
|
||||
CHPL_GLOBAL = 9,
|
||||
CHPL_WORLD = 10,
|
||||
};
|
||||
|
||||
#define HAL_EFUSE_MEMORY
|
||||
|
||||
#define EFUSE_REAL_CONTENT_LEN 512
|
||||
#define EFUSE_MAP_LEN 128
|
||||
#define EFUSE_MAX_SECTION 16
|
||||
#define EFUSE_IC_ID_OFFSET 506 //For some inferiority IC purpose. added by Roger, 2009.09.02.
|
||||
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN)
|
||||
//
|
||||
// <Roger_Notes>
|
||||
// To prevent out of boundary programming case,
|
||||
// leave 1byte and program full section
|
||||
// 9bytes + 1byt + 5bytes and pre 1byte.
|
||||
// For worst case:
|
||||
// | 1byte|----8bytes----|1byte|--5bytes--|
|
||||
// | | Reserved(14bytes) |
|
||||
//
|
||||
|
||||
// PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte.
|
||||
#define EFUSE_OOB_PROTECT_BYTES 15
|
||||
|
||||
#define EFUSE_REAL_CONTENT_LEN_8723A 512
|
||||
#define EFUSE_MAP_LEN_8723A 256
|
||||
#define EFUSE_MAX_SECTION_8723A 32
|
||||
|
||||
//========================================================
|
||||
// EFUSE for BT definition
|
||||
//========================================================
|
||||
#define EFUSE_BT_REAL_BANK_CONTENT_LEN 512
|
||||
#define EFUSE_BT_REAL_CONTENT_LEN 1536 // 512*3
|
||||
#define EFUSE_BT_MAP_LEN 1024 // 1k bytes
|
||||
#define EFUSE_BT_MAX_SECTION 128 // 1024/8
|
||||
|
||||
#define EFUSE_PROTECT_BYTES_BANK 16
|
||||
|
||||
//
|
||||
// <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06.
|
||||
//
|
||||
typedef enum _RT_MULTI_FUNC {
|
||||
RT_MULTI_FUNC_NONE = 0x00,
|
||||
RT_MULTI_FUNC_WIFI = 0x01,
|
||||
RT_MULTI_FUNC_BT = 0x02,
|
||||
RT_MULTI_FUNC_GPS = 0x04,
|
||||
} RT_MULTI_FUNC, *PRT_MULTI_FUNC;
|
||||
|
||||
//
|
||||
// <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08.
|
||||
//
|
||||
typedef enum _RT_POLARITY_CTL {
|
||||
RT_POLARITY_LOW_ACT = 0,
|
||||
RT_POLARITY_HIGH_ACT = 1,
|
||||
} RT_POLARITY_CTL, *PRT_POLARITY_CTL;
|
||||
|
||||
// For RTL8723 regulator mode. by tynli. 2011.01.14.
|
||||
typedef enum _RT_REGULATOR_MODE {
|
||||
RT_SWITCHING_REGULATOR = 0,
|
||||
RT_LDO_REGULATOR = 1,
|
||||
} RT_REGULATOR_MODE, *PRT_REGULATOR_MODE;
|
||||
|
||||
// Description: Determine the types of C2H events that are the same in driver and Fw.
|
||||
// Fisrt constructed by tynli. 2009.10.09.
|
||||
typedef enum _RTL8192C_C2H_EVT
|
||||
{
|
||||
C2H_DBG = 0,
|
||||
C2H_TSF = 1,
|
||||
C2H_AP_RPT_RSP = 2,
|
||||
C2H_CCX_TX_RPT = 3, // The FW notify the report of the specific tx packet.
|
||||
C2H_BT_RSSI = 4,
|
||||
C2H_BT_OP_MODE = 5,
|
||||
C2H_EXT_RA_RPT = 6,
|
||||
C2H_HW_INFO_EXCH = 10,
|
||||
C2H_C2H_H2C_TEST = 11,
|
||||
C2H_BT_INFO = 12,
|
||||
C2H_BT_MP_INFO = 15,
|
||||
MAX_C2HEVENT
|
||||
} RTL8192C_C2H_EVT;
|
||||
|
||||
typedef struct hal_data_8723a
|
||||
{
|
||||
HAL_VERSION VersionID;
|
||||
RT_CUSTOMER_ID CustomerID;
|
||||
|
||||
u16 FirmwareVersion;
|
||||
u16 FirmwareVersionRev;
|
||||
u16 FirmwareSubVersion;
|
||||
u16 FirmwareSignature;
|
||||
|
||||
//current WIFI_PHY values
|
||||
u32 ReceiveConfig;
|
||||
WIRELESS_MODE CurrentWirelessMode;
|
||||
HT_CHANNEL_WIDTH CurrentChannelBW;
|
||||
u8 CurrentChannel;
|
||||
u8 nCur40MhzPrimeSC;// Control channel sub-carrier
|
||||
|
||||
u16 BasicRateSet;
|
||||
|
||||
//rf_ctrl
|
||||
u8 rf_chip;
|
||||
u8 rf_type;
|
||||
u8 NumTotalRFPath;
|
||||
|
||||
u8 BoardType;
|
||||
u8 CrystalCap;
|
||||
//
|
||||
// EEPROM setting.
|
||||
//
|
||||
u8 EEPROMVersion;
|
||||
u16 EEPROMVID;
|
||||
u16 EEPROMPID;
|
||||
u16 EEPROMSVID;
|
||||
u16 EEPROMSDID;
|
||||
u8 EEPROMCustomerID;
|
||||
u8 EEPROMSubCustomerID;
|
||||
u8 EEPROMRegulatory;
|
||||
u8 EEPROMThermalMeter;
|
||||
u8 EEPROMBluetoothCoexist;
|
||||
u8 EEPROMBluetoothType;
|
||||
u8 EEPROMBluetoothAntNum;
|
||||
u8 EEPROMBluetoothAntIsolation;
|
||||
u8 EEPROMBluetoothRadioShared;
|
||||
|
||||
u8 bTXPowerDataReadFromEEPORM;
|
||||
u8 bAPKThermalMeterIgnore;
|
||||
|
||||
u8 bIQKInitialized;
|
||||
u8 bAntennaDetected;
|
||||
|
||||
u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
|
||||
u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
|
||||
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
|
||||
u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
|
||||
u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
|
||||
// For power group
|
||||
u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
|
||||
u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
|
||||
|
||||
u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff
|
||||
|
||||
// Read/write are allow for following hardware information variables
|
||||
u8 framesync;
|
||||
u32 framesyncC34;
|
||||
u8 framesyncMonitor;
|
||||
u8 DefaultInitialGain[4];
|
||||
u8 pwrGroupCnt;
|
||||
u32 MCSTxPowerLevelOriginalOffset[7][16];
|
||||
u32 CCKTxPowerLevelOriginalOffset;
|
||||
|
||||
u32 AntennaTxPath; // Antenna path Tx
|
||||
u32 AntennaRxPath; // Antenna path Rx
|
||||
u8 ExternalPA;
|
||||
|
||||
u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
|
||||
|
||||
//u32 LedControlNum;
|
||||
//u32 LedControlMode;
|
||||
//u32 TxPowerTrackControl;
|
||||
u8 b1x1RecvCombine; // for 1T1R receive combining
|
||||
|
||||
// For EDCA Turbo mode
|
||||
// u8 bIsAnyNonBEPkts; // Adapter->recvpriv.bIsAnyNonBEPkts
|
||||
// u8 bCurrentTurboEDCA;
|
||||
// u8 bForcedDisableTurboEDCA;
|
||||
// u8 bIsCurRDLState; // pdmpriv->prv_traffic_idx
|
||||
|
||||
u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo.
|
||||
|
||||
//vivi, for tx power tracking, 20080407
|
||||
//u16 TSSI_13dBm;
|
||||
//u32 Pwr_Track;
|
||||
// The current Tx Power Level
|
||||
u8 CurrentCckTxPwrIdx;
|
||||
u8 CurrentOfdm24GTxPwrIdx;
|
||||
|
||||
BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
|
||||
|
||||
bool bRFPathRxEnable[4]; // We support 4 RF path now.
|
||||
|
||||
u32 RfRegChnlVal[2];
|
||||
|
||||
u8 bCckHighPower;
|
||||
|
||||
//RDG enable
|
||||
bool bRDGEnable;
|
||||
|
||||
//for host message to fw
|
||||
u8 LastHMEBoxNum;
|
||||
|
||||
u8 fw_ractrl;
|
||||
u8 RegTxPause;
|
||||
// Beacon function related global variable.
|
||||
u32 RegBcnCtrlVal;
|
||||
u8 RegFwHwTxQCtrl;
|
||||
u8 RegReg542;
|
||||
|
||||
struct dm_priv dmpriv;
|
||||
DM_ODM_T odmpriv;
|
||||
//_lock odm_stainfo_lock;
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
struct sreset_priv srestpriv;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
u8 bBTMode;
|
||||
// BT only.
|
||||
BT30Info BtInfo;
|
||||
// For bluetooth co-existance
|
||||
BT_COEXIST_STR bt_coexist;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ANTENNA_DIVERSITY
|
||||
u8 CurAntenna;
|
||||
|
||||
// SW Antenna Switch
|
||||
s32 RSSI_sum_A;
|
||||
s32 RSSI_sum_B;
|
||||
s32 RSSI_cnt_A;
|
||||
s32 RSSI_cnt_B;
|
||||
u8 RSSI_test;
|
||||
u8 AntDivCfg;
|
||||
#endif
|
||||
|
||||
u8 bDumpRxPkt;//for debug
|
||||
u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
|
||||
|
||||
// 2010/08/09 MH Add CU power down mode.
|
||||
u8 pwrdown;
|
||||
|
||||
// Add for dual MAC 0--Mac0 1--Mac1
|
||||
u32 interfaceIndex;
|
||||
|
||||
u8 OutEpQueueSel;
|
||||
u8 OutEpNumber;
|
||||
|
||||
// 2010/12/10 MH Add for USB aggreation mode dynamic shceme.
|
||||
bool UsbRxHighSpeedMode;
|
||||
|
||||
// 2010/11/22 MH Add for slim combo debug mode selective.
|
||||
// This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock.
|
||||
bool SlimComboDbg;
|
||||
|
||||
//
|
||||
// Add For EEPROM Efuse switch and Efuse Shadow map Setting
|
||||
//
|
||||
u8 EepromOrEfuse;
|
||||
// u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes)
|
||||
u16 EfuseUsedBytes;
|
||||
u8 EfuseUsedPercentage;
|
||||
#ifdef HAL_EFUSE_MEMORY
|
||||
EFUSE_HAL EfuseHal;
|
||||
#endif
|
||||
|
||||
// Interrupt relatd register information.
|
||||
u32 SysIntrStatus;
|
||||
u32 SysIntrMask;
|
||||
|
||||
//
|
||||
// 2011/02/23 MH Add for 8723 mylti function definition. The define should be moved to an
|
||||
// independent file in the future.
|
||||
//
|
||||
//------------------------8723-----------------------------------------//
|
||||
RT_MULTI_FUNC MultiFunc; // For multi-function consideration.
|
||||
RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control.
|
||||
RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO
|
||||
//------------------------8723-----------------------------------------//
|
||||
//
|
||||
// 2011/02/23 MH Add for 8723 mylti function definition. The define should be moved to an
|
||||
// independent file in the future.
|
||||
|
||||
bool bMACFuncEnable;
|
||||
|
||||
#ifdef CONFIG_P2P
|
||||
struct P2P_PS_Offload_t p2p_ps_offload;
|
||||
#endif
|
||||
|
||||
|
||||
//
|
||||
// For USB Interface HAL related
|
||||
//
|
||||
#ifdef CONFIG_USB_HCI
|
||||
u32 UsbBulkOutSize;
|
||||
|
||||
// Interrupt relatd register information.
|
||||
u32 IntArray[2];
|
||||
u32 IntrMask[2];
|
||||
#endif
|
||||
|
||||
|
||||
//
|
||||
// For SDIO Interface HAL related
|
||||
//
|
||||
|
||||
// Auto FSM to Turn On, include clock, isolation, power control for MAC only
|
||||
u8 bMacPwrCtrlOn;
|
||||
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
//
|
||||
// SDIO ISR Related
|
||||
//
|
||||
// u32 IntrMask[1];
|
||||
// u32 IntrMaskToSet[1];
|
||||
// LOG_INTERRUPT InterruptLog;
|
||||
u32 sdio_himr;
|
||||
u32 sdio_hisr;
|
||||
|
||||
//
|
||||
// SDIO Tx FIFO related.
|
||||
//
|
||||
// HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg
|
||||
u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
|
||||
_lock SdioTxFIFOFreePageLock;
|
||||
_thread_hdl_ SdioXmitThread;
|
||||
_sema SdioXmitSema;
|
||||
_sema SdioXmitTerminateSema;
|
||||
|
||||
//
|
||||
// SDIO Rx FIFO related.
|
||||
//
|
||||
u8 SdioRxFIFOCnt;
|
||||
u16 SdioRxFIFOSize;
|
||||
#endif
|
||||
} HAL_DATA_8723A, *PHAL_DATA_8723A;
|
||||
|
||||
typedef struct hal_data_8723a HAL_DATA_TYPE, *PHAL_DATA_TYPE;
|
||||
|
||||
#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData))
|
||||
#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type)
|
||||
|
||||
#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
|
||||
#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
|
||||
|
||||
typedef struct rxreport_8723a
|
||||
{
|
||||
u32 pktlen:14;
|
||||
u32 crc32:1;
|
||||
u32 icverr:1;
|
||||
u32 drvinfosize:4;
|
||||
u32 security:3;
|
||||
u32 qos:1;
|
||||
u32 shift:2;
|
||||
u32 physt:1;
|
||||
u32 swdec:1;
|
||||
u32 ls:1;
|
||||
u32 fs:1;
|
||||
u32 eor:1;
|
||||
u32 own:1;
|
||||
|
||||
u32 macid:5;
|
||||
u32 tid:4;
|
||||
u32 hwrsvd:4;
|
||||
u32 amsdu:1;
|
||||
u32 paggr:1;
|
||||
u32 faggr:1;
|
||||
u32 a1fit:4;
|
||||
u32 a2fit:4;
|
||||
u32 pam:1;
|
||||
u32 pwr:1;
|
||||
u32 md:1;
|
||||
u32 mf:1;
|
||||
u32 type:2;
|
||||
u32 mc:1;
|
||||
u32 bc:1;
|
||||
|
||||
u32 seq:12;
|
||||
u32 frag:4;
|
||||
u32 nextpktlen:14;
|
||||
u32 nextind:1;
|
||||
u32 rsvd0831:1;
|
||||
|
||||
u32 rxmcs:6;
|
||||
u32 rxht:1;
|
||||
u32 gf:1;
|
||||
u32 splcp:1;
|
||||
u32 bw:1;
|
||||
u32 htc:1;
|
||||
u32 eosp:1;
|
||||
u32 bssidfit:2;
|
||||
u32 rsvd1214:16;
|
||||
u32 unicastwake:1;
|
||||
u32 magicwake:1;
|
||||
|
||||
u32 pattern0match:1;
|
||||
u32 pattern1match:1;
|
||||
u32 pattern2match:1;
|
||||
u32 pattern3match:1;
|
||||
u32 pattern4match:1;
|
||||
u32 pattern5match:1;
|
||||
u32 pattern6match:1;
|
||||
u32 pattern7match:1;
|
||||
u32 pattern8match:1;
|
||||
u32 pattern9match:1;
|
||||
u32 patternamatch:1;
|
||||
u32 patternbmatch:1;
|
||||
u32 patterncmatch:1;
|
||||
u32 rsvd1613:19;
|
||||
|
||||
u32 tsfl;
|
||||
|
||||
u32 bassn:12;
|
||||
u32 bavld:1;
|
||||
u32 rsvd2413:19;
|
||||
} RXREPORT, *PRXREPORT;
|
||||
|
||||
typedef struct phystatus_8723a
|
||||
{
|
||||
u32 rxgain_a:7;
|
||||
u32 trsw_a:1;
|
||||
u32 rxgain_b:7;
|
||||
u32 trsw_b:1;
|
||||
u32 chcorr_l:16;
|
||||
|
||||
u32 sigqualcck:8;
|
||||
u32 cfo_a:8;
|
||||
u32 cfo_b:8;
|
||||
u32 chcorr_h:8;
|
||||
|
||||
u32 noisepwrdb_h:8;
|
||||
u32 cfo_tail_a:8;
|
||||
u32 cfo_tail_b:8;
|
||||
u32 rsvd0824:8;
|
||||
|
||||
u32 rsvd1200:8;
|
||||
u32 rxevm_a:8;
|
||||
u32 rxevm_b:8;
|
||||
u32 rxsnr_a:8;
|
||||
|
||||
u32 rxsnr_b:8;
|
||||
u32 noisepwrdb_l:8;
|
||||
u32 rsvd1616:8;
|
||||
u32 postsnr_a:8;
|
||||
|
||||
u32 postsnr_b:8;
|
||||
u32 csi_a:8;
|
||||
u32 csi_b:8;
|
||||
u32 targetcsi_a:8;
|
||||
|
||||
u32 targetcsi_b:8;
|
||||
u32 sigevm:8;
|
||||
u32 maxexpwr:8;
|
||||
u32 exintflag:1;
|
||||
u32 sgien:1;
|
||||
u32 rxsc:2;
|
||||
u32 idlelong:1;
|
||||
u32 anttrainen:1;
|
||||
u32 antselb:1;
|
||||
u32 antsel:1;
|
||||
} PHYSTATUS, *PPHYSTATUS;
|
||||
|
||||
|
||||
// rtl8723a_hal_init.c
|
||||
s32 rtl8723a_FirmwareDownload(PADAPTER padapter);
|
||||
void rtl8723a_FirmwareSelfReset(PADAPTER padapter);
|
||||
void rtl8723a_InitializeFirmwareVars(PADAPTER padapter);
|
||||
|
||||
void rtl8723a_InitAntenna_Selection(PADAPTER padapter);
|
||||
void rtl8723a_DeinitAntenna_Selection(PADAPTER padapter);
|
||||
void rtl8723a_CheckAntenna_Selection(PADAPTER padapter);
|
||||
void rtl8723a_init_default_value(PADAPTER padapter);
|
||||
|
||||
s32 InitLLTTable(PADAPTER padapter, u32 boundary);
|
||||
|
||||
s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
|
||||
s32 CardDisableWithoutHWSM(PADAPTER padapter);
|
||||
|
||||
// EFuse
|
||||
u8 GetEEPROMSize8723A(PADAPTER padapter);
|
||||
void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
|
||||
void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
|
||||
void Hal_EfuseParseTxPowerInfo_8723A(PADAPTER padapter, u8 *PROMContent, bool AutoLoadFail);
|
||||
void Hal_EfuseParseBTCoexistInfo_8723A(PADAPTER padapter, u8 *hwinfo, bool AutoLoadFail);
|
||||
void Hal_EfuseParseEEPROMVer(PADAPTER padapter, u8 *hwinfo, bool AutoLoadFail);
|
||||
void rtl8723a_EfuseParseChnlPlan(PADAPTER padapter, u8 *hwinfo, bool AutoLoadFail);
|
||||
void Hal_EfuseParseCustomerID(PADAPTER padapter, u8 *hwinfo, bool AutoLoadFail);
|
||||
void Hal_EfuseParseAntennaDiversity(PADAPTER padapter, u8 *hwinfo, bool AutoLoadFail);
|
||||
void Hal_EfuseParseRateIndicationOption(PADAPTER padapter, u8 *hwinfo, bool AutoLoadFail);
|
||||
void Hal_EfuseParseXtal_8723A(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
|
||||
void Hal_EfuseParseThermalMeter_8723A(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
|
||||
|
||||
//RT_CHANNEL_DOMAIN rtl8723a_HalMapChannelPlan(PADAPTER padapter, u8 HalChannelPlan);
|
||||
//VERSION_8192C rtl8723a_ReadChipVersion(PADAPTER padapter);
|
||||
//void rtl8723a_ReadBluetoothCoexistInfo(PADAPTER padapter, u8 *PROMContent, bool AutoloadFail);
|
||||
void Hal_InitChannelPlan(PADAPTER padapter);
|
||||
|
||||
void rtl8723a_set_hal_ops(struct hal_ops *pHalFunc);
|
||||
void SetHwReg8723A(PADAPTER padapter, u8 variable, u8 *val);
|
||||
void GetHwReg8723A(PADAPTER padapter, u8 variable, u8 *val);
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
void rtl8723a_SingleDualAntennaDetection(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
// register
|
||||
void SetBcnCtrlReg(PADAPTER padapter, u8 SetBits, u8 ClearBits);
|
||||
void rtl8723a_InitBeaconParameters(PADAPTER padapter);
|
||||
void rtl8723a_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
|
||||
|
||||
void rtl8723a_clone_haldata(_adapter *dst_adapter, _adapter *src_adapter);
|
||||
void rtl8723a_start_thread(_adapter *padapter);
|
||||
void rtl8723a_stop_thread(_adapter *padapter);
|
||||
|
||||
s32 c2h_id_filter_ccx_8723a(u8 id);
|
||||
|
||||
|
||||
#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
|
||||
void rtl8723a_init_checkbthang_workqueue(_adapter * padapter);
|
||||
void rtl8723a_free_checkbthang_workqueue(_adapter * padapter);
|
||||
void rtl8723a_cancel_checkbthang_workqueue(_adapter * padapter);
|
||||
void rtl8723a_hal_check_bt_hang(_adapter * padapter);
|
||||
#endif
|
||||
#endif
|
|
@ -1,49 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __RTL8723A_LED_H__
|
||||
#define __RTL8723A_LED_H__
|
||||
|
||||
#include <drv_conf.h>
|
||||
#include <osdep_service.h>
|
||||
#include <drv_types.h>
|
||||
|
||||
|
||||
//================================================================================
|
||||
// Interface to manipulate LED objects.
|
||||
//================================================================================
|
||||
#ifdef CONFIG_USB_HCI
|
||||
void rtl8723au_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8723au_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
void rtl8723ae_gen_RefreshLedState(PADAPTER Adapter);
|
||||
void rtl8723ae_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8723ae_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
void rtl8723as_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8723as_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_GSPI_HCI
|
||||
void rtl8723as_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8723as_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
#endif
|
|
@ -1,114 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __RTL8723A_PG_H__
|
||||
#define __RTL8723A_PG_H__
|
||||
|
||||
//====================================================
|
||||
// EEPROM/Efuse PG Offset for 8723E/8723U/8723S
|
||||
//====================================================
|
||||
#define EEPROM_CCK_TX_PWR_INX_8723A 0x10
|
||||
#define EEPROM_HT40_1S_TX_PWR_INX_8723A 0x16
|
||||
#define EEPROM_HT20_TX_PWR_INX_DIFF_8723A 0x1C
|
||||
#define EEPROM_OFDM_TX_PWR_INX_DIFF_8723A 0x1F
|
||||
#define EEPROM_HT40_MAX_PWR_OFFSET_8723A 0x22
|
||||
#define EEPROM_HT20_MAX_PWR_OFFSET_8723A 0x25
|
||||
|
||||
#define EEPROM_ChannelPlan_8723A 0x28
|
||||
#define EEPROM_TSSI_A_8723A 0x29
|
||||
#define EEPROM_THERMAL_METER_8723A 0x2A
|
||||
#define RF_OPTION1_8723A 0x2B
|
||||
#define RF_OPTION2_8723A 0x2C
|
||||
#define RF_OPTION3_8723A 0x2D
|
||||
#define RF_OPTION4_8723A 0x2E
|
||||
#define EEPROM_VERSION_8723A 0x30
|
||||
#define EEPROM_CustomID_8723A 0x31
|
||||
#define EEPROM_SubCustomID_8723A 0x32
|
||||
#define EEPROM_XTAL_K_8723A 0x33
|
||||
#define EEPROM_Chipset_8723A 0x34
|
||||
|
||||
// RTL8723AE
|
||||
#define EEPROM_VID_8723AE 0x49
|
||||
#define EEPROM_DID_8723AE 0x4B
|
||||
#define EEPROM_SVID_8723AE 0x4D
|
||||
#define EEPROM_SMID_8723AE 0x4F
|
||||
#define EEPROM_MAC_ADDR_8723AE 0x67
|
||||
|
||||
// RTL8723AU
|
||||
#define EEPROM_MAC_ADDR_8723AU 0xC6
|
||||
#define EEPROM_VID_8723AU 0xB7
|
||||
#define EEPROM_PID_8723AU 0xB9
|
||||
|
||||
// RTL8723AS
|
||||
#define EEPROM_MAC_ADDR_8723AS 0xAA
|
||||
|
||||
//====================================================
|
||||
// EEPROM/Efuse Value Type
|
||||
//====================================================
|
||||
#define EETYPE_TX_PWR 0x0
|
||||
|
||||
//====================================================
|
||||
// EEPROM/Efuse Default Value
|
||||
//====================================================
|
||||
#define EEPROM_Default_CrystalCap_8723A 0x20
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// EEPROM/EFUSE data structure definition.
|
||||
//----------------------------------------------------------------------------
|
||||
#define MAX_RF_PATH_NUM 2
|
||||
#define MAX_CHNL_GROUP 3+9
|
||||
typedef struct _TxPowerInfo
|
||||
{
|
||||
u8 CCKIndex[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];
|
||||
u8 HT40_1SIndex[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];
|
||||
u8 HT40_2SIndexDiff[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];
|
||||
u8 HT20IndexDiff[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];
|
||||
u8 OFDMIndexDiff[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];
|
||||
u8 HT40MaxOffset[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];
|
||||
u8 HT20MaxOffset[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];
|
||||
u8 TSSI_A[3];
|
||||
u8 TSSI_B[3];
|
||||
u8 TSSI_A_5G[3]; //5GL/5GM/5GH
|
||||
u8 TSSI_B_5G[3];
|
||||
} TxPowerInfo, *PTxPowerInfo;
|
||||
|
||||
typedef enum _BT_Ant_NUM
|
||||
{
|
||||
Ant_x2 = 0,
|
||||
Ant_x1 = 1
|
||||
} BT_Ant_NUM, *PBT_Ant_NUM;
|
||||
|
||||
typedef enum _BT_CoType
|
||||
{
|
||||
BT_2Wire = 0,
|
||||
BT_ISSC_3Wire = 1,
|
||||
BT_Accel = 2,
|
||||
BT_CSR_BC4 = 3,
|
||||
BT_CSR_BC8 = 4,
|
||||
BT_RTL8756 = 5,
|
||||
BT_RTL8723A = 6
|
||||
} BT_CoType, *PBT_CoType;
|
||||
|
||||
typedef enum _BT_RadioShared
|
||||
{
|
||||
BT_Radio_Shared = 0,
|
||||
BT_Radio_Individual = 1,
|
||||
} BT_RadioShared, *PBT_RadioShared;
|
||||
#endif
|
|
@ -1,40 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __RTL8723A_RECV_H__
|
||||
#define __RTL8723A_RECV_H__
|
||||
|
||||
#include <rtl8192c_recv.h>
|
||||
|
||||
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
#ifdef CONFIG_DIRECT_RECV
|
||||
void rtl8723as_recv(PADAPTER padapter, struct recv_buf *precvbuf);
|
||||
#endif
|
||||
s32 rtl8723as_init_recv_priv(PADAPTER padapter);
|
||||
void rtl8723as_free_recv_priv(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
void rtl8192c_query_rx_phy_status(union recv_frame *prframe, struct phy_stat *pphy_stat);
|
||||
void rtl8192c_process_phy_info(PADAPTER padapter, void *prframe);
|
||||
#ifdef CONFIG_USB_HCI
|
||||
void update_recvframe_attrib(union recv_frame *precvframe, struct recv_stat *prxstat);
|
||||
void update_recvframe_phyinfo(union recv_frame *precvframe, struct phy_stat *pphy_info);
|
||||
#endif
|
||||
#endif
|
|
@ -1,26 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __RTL8723A_RF_H__
|
||||
#define __RTL8723A_RF_H__
|
||||
|
||||
#include "rtl8192c_rf.h"
|
||||
int PHY_RF6052_Config8723A( PADAPTER Adapter );
|
||||
|
||||
#endif
|
|
@ -1,530 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef __RTL8723A_SPEC_H__
|
||||
#define __RTL8723A_SPEC_H__
|
||||
|
||||
#include <rtl8192c_spec.h>
|
||||
|
||||
|
||||
//============================================================================
|
||||
// 8723A Regsiter offset definition
|
||||
//============================================================================
|
||||
#define HAL_8723A_NAV_UPPER_UNIT 128 // micro-second
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0000h ~ 0x00FFh System Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
#define REG_SYSON_REG_LOCK 0x001C
|
||||
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0100h ~ 0x01FFh MACTOP General Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
#define REG_FTIMR 0x0138
|
||||
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0200h ~ 0x027Fh TXDMA Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0280h ~ 0x02FFh RXDMA Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0300h ~ 0x03FFh PCIe
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0400h ~ 0x047Fh Protocol Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
#define REG_EARLY_MODE_CONTROL 0x4D0
|
||||
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0500h ~ 0x05FFh EDCA Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
|
||||
//2 BCN_CTRL
|
||||
#define DIS_ATIM BIT(0)
|
||||
#define DIS_BCNQ_SUB BIT(1)
|
||||
#define DIS_TSF_UDT BIT(4)
|
||||
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0600h ~ 0x07FFh WMAC Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// Note:
|
||||
// The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. The default value is
|
||||
// always too small, but the WiFi TestPlan test by 25,000 microseconds of NAV through sending
|
||||
// CTS in the air. We must update this value greater than 25,000 microseconds to pass the item.
|
||||
// The offset of NAV_UPPER in 8192C Spec is incorrect, and the offset should be 0x0652. Commented
|
||||
// by SD1 Scott.
|
||||
// By Bruce, 2011-07-18.
|
||||
//
|
||||
#define REG_NAV_UPPER 0x0652 // unit of 128
|
||||
|
||||
|
||||
//============================================================================
|
||||
// 8723 Regsiter Bit and Content definition
|
||||
//============================================================================
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0000h ~ 0x00FFh System Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
|
||||
//2 SPS0_CTRL
|
||||
|
||||
//2 SYS_ISO_CTRL
|
||||
|
||||
//2 SYS_FUNC_EN
|
||||
|
||||
//2 APS_FSMCO
|
||||
#define EN_WLON BIT(16)
|
||||
|
||||
//2 SYS_CLKR
|
||||
|
||||
//2 9346CR
|
||||
|
||||
//2 AFE_MISC
|
||||
|
||||
//2 SPS0_CTRL
|
||||
|
||||
//2 SPS_OCP_CFG
|
||||
|
||||
//2 SYSON_REG_LOCK
|
||||
#define WLOCK_ALL BIT(0)
|
||||
#define WLOCK_00 BIT(1)
|
||||
#define WLOCK_04 BIT(2)
|
||||
#define WLOCK_08 BIT(3)
|
||||
#define WLOCK_40 BIT(4)
|
||||
#define WLOCK_1C_B6 BIT(5)
|
||||
#define R_DIS_PRST_1 BIT(6)
|
||||
#define LOCK_ALL_EN BIT(7)
|
||||
|
||||
//2 RF_CTRL
|
||||
|
||||
//2 LDOA15_CTRL
|
||||
|
||||
//2 LDOV12D_CTRL
|
||||
|
||||
//2 AFE_XTAL_CTRL
|
||||
|
||||
//2 AFE_PLL_CTRL
|
||||
|
||||
//2 EFUSE_CTRL
|
||||
|
||||
//2 EFUSE_TEST (For RTL8723 partially)
|
||||
|
||||
//2 PWR_DATA
|
||||
|
||||
//2 CAL_TIMER
|
||||
|
||||
//2 ACLK_MON
|
||||
|
||||
//2 GPIO_MUXCFG
|
||||
|
||||
//2 GPIO_PIN_CTRL
|
||||
|
||||
//2 GPIO_INTM
|
||||
|
||||
//2 LEDCFG
|
||||
|
||||
//2 FSIMR
|
||||
|
||||
//2 FSISR
|
||||
|
||||
//2 HSIMR
|
||||
// 8723 Host System Interrupt Mask Register (offset 0x58, 32 byte)
|
||||
#define HSIMR_GPIO12_0_INT_EN BIT(0)
|
||||
#define HSIMR_SPS_OCP_INT_EN BIT(5)
|
||||
#define HSIMR_RON_INT_EN BIT(6)
|
||||
#define HSIMR_PDNINT_EN BIT(7)
|
||||
#define HSIMR_GPIO9_INT_EN BIT(25)
|
||||
|
||||
//2 HSISR
|
||||
// 8723 Host System Interrupt Status Register (offset 0x5C, 32 byte)
|
||||
#define HSISR_GPIO12_0_INT BIT(0)
|
||||
#define HSISR_SPS_OCP_INT BIT(5)
|
||||
#define HSISR_RON_INT BIT(6)
|
||||
#define HSISR_PDNINT BIT(7)
|
||||
#define HSISR_GPIO9_INT BIT(25)
|
||||
|
||||
// interrupt mask which needs to clear
|
||||
#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\
|
||||
HSISR_SPS_OCP_INT |\
|
||||
HSISR_RON_INT |\
|
||||
HSISR_PDNINT |\
|
||||
HSISR_GPIO9_INT)
|
||||
|
||||
//2 MCUFWDL
|
||||
#define RAM_DL_SEL BIT7 // 1:RAM, 0:ROM
|
||||
|
||||
//2 HPON_FSM
|
||||
|
||||
//2 SYS_CFG
|
||||
#define RTL_ID BIT(23) // TestChip ID, 1:Test(RLE); 0:MP(RL)
|
||||
#define SPS_SEL BIT(24) // 1:LDO regulator mode; 0:Switching regulator mode
|
||||
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0100h ~ 0x01FFh MACTOP General Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
|
||||
//2 Function Enable Registers
|
||||
|
||||
//2 CR
|
||||
#define CALTMR_EN BIT(10)
|
||||
|
||||
//2 PBP - Page Size Register
|
||||
|
||||
//2 TX/RXDMA
|
||||
|
||||
//2 TRXFF_BNDY
|
||||
|
||||
//2 LLT_INIT
|
||||
|
||||
//2 BB_ACCESS_CTRL
|
||||
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0200h ~ 0x027Fh TXDMA Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
|
||||
//2 RQPN
|
||||
|
||||
//2 TDECTRL
|
||||
|
||||
//2 TDECTL
|
||||
|
||||
//2 TXDMA_OFFSET_CHK
|
||||
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0400h ~ 0x047Fh Protocol Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
|
||||
//2 FWHW_TXQ_CTRL
|
||||
|
||||
//2 INIRTSMCS_SEL
|
||||
|
||||
//2 SPEC SIFS
|
||||
|
||||
//2 RRSR
|
||||
|
||||
//2 ARFR
|
||||
|
||||
//2 AGGLEN_LMT_L
|
||||
|
||||
//2 RL
|
||||
|
||||
//2 DARFRC
|
||||
|
||||
//2 RARFRC
|
||||
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0500h ~ 0x05FFh EDCA Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
|
||||
//2 EDCA setting
|
||||
|
||||
//2 EDCA_VO_PARAM
|
||||
|
||||
//2 SIFS_CCK
|
||||
|
||||
//2 SIFS_OFDM
|
||||
|
||||
//2 TBTT PROHIBIT
|
||||
|
||||
//2 REG_RD_CTRL
|
||||
|
||||
//2 BCN_CTRL
|
||||
|
||||
//2 ACMHWCTRL
|
||||
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0x0600h ~ 0x07FFh WMAC Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
|
||||
//2 APSD_CTRL
|
||||
|
||||
//2 BWOPMODE
|
||||
|
||||
//2 TCR
|
||||
|
||||
//2 RCR
|
||||
|
||||
//2 RX_PKT_LIMIT
|
||||
|
||||
//2 RX_DLK_TIME
|
||||
|
||||
//2 MBIDCAMCFG
|
||||
|
||||
//2 AMPDU_MIN_SPACE
|
||||
|
||||
//2 RXERR_RPT
|
||||
|
||||
//2 SECCFG
|
||||
|
||||
|
||||
//-----------------------------------------------------
|
||||
//
|
||||
// 0xFE00h ~ 0xFE55h RTL8723 SDIO Configuration
|
||||
//
|
||||
//-----------------------------------------------------
|
||||
|
||||
// I/O bus domain address mapping
|
||||
#define SDIO_LOCAL_BASE 0x10250000
|
||||
#define WLAN_IOREG_BASE 0x10260000
|
||||
#define FIRMWARE_FIFO_BASE 0x10270000
|
||||
#define TX_HIQ_BASE 0x10310000
|
||||
#define TX_MIQ_BASE 0x10320000
|
||||
#define TX_LOQ_BASE 0x10330000
|
||||
#define RX_RX0FF_BASE 0x10340000
|
||||
|
||||
// SDIO host local register space mapping.
|
||||
#define SDIO_LOCAL_MSK 0x0FFF
|
||||
#define WLAN_IOREG_MSK 0x7FFF
|
||||
#define WLAN_FIFO_MSK 0x1FFF // Aggregation Length[12:0]
|
||||
#define WLAN_RX0FF_MSK 0x0003
|
||||
|
||||
#define SDIO_WITHOUT_REF_DEVICE_ID 0 // Without reference to the SDIO Device ID
|
||||
#define SDIO_LOCAL_DEVICE_ID 0 // 0b[16], 000b[15:13]
|
||||
#define WLAN_TX_HIQ_DEVICE_ID 4 // 0b[16], 100b[15:13]
|
||||
#define WLAN_TX_MIQ_DEVICE_ID 5 // 0b[16], 101b[15:13]
|
||||
#define WLAN_TX_LOQ_DEVICE_ID 6 // 0b[16], 110b[15:13]
|
||||
#define WLAN_RX0FF_DEVICE_ID 7 // 0b[16], 111b[15:13]
|
||||
#define WLAN_IOREG_DEVICE_ID 8 // 1b[16]
|
||||
|
||||
// SDIO Tx Free Page Index
|
||||
#define HI_QUEUE_IDX 0
|
||||
#define MID_QUEUE_IDX 1
|
||||
#define LOW_QUEUE_IDX 2
|
||||
#define PUBLIC_QUEUE_IDX 3
|
||||
|
||||
#define SDIO_MAX_TX_QUEUE 3 // HIQ, MIQ and LOQ
|
||||
#define SDIO_MAX_RX_QUEUE 1
|
||||
|
||||
#define SDIO_REG_TX_CTRL 0x0000 // SDIO Tx Control
|
||||
#define SDIO_REG_HIMR 0x0014 // SDIO Host Interrupt Mask
|
||||
#define SDIO_REG_HISR 0x0018 // SDIO Host Interrupt Service Routine
|
||||
#define SDIO_REG_HCPWM 0x0019 // HCI Current Power Mode
|
||||
#define SDIO_REG_RX0_REQ_LEN 0x001C // RXDMA Request Length
|
||||
#define SDIO_REG_FREE_TXPG 0x0020 // Free Tx Buffer Page
|
||||
#define SDIO_REG_HCPWM1 0x0024 // HCI Current Power Mode 1
|
||||
#define SDIO_REG_HCPWM2 0x0026 // HCI Current Power Mode 2
|
||||
#define SDIO_REG_HTSFR_INFO 0x0030 // HTSF Informaion
|
||||
#define SDIO_REG_HRPWM1 0x0080 // HCI Request Power Mode 1
|
||||
#define SDIO_REG_HRPWM2 0x0082 // HCI Request Power Mode 2
|
||||
#define SDIO_REG_HPS_CLKR 0x0084 // HCI Power Save Clock
|
||||
#define SDIO_REG_HSUS_CTRL 0x0086 // SDIO HCI Suspend Control
|
||||
#define SDIO_REG_HIMR_ON 0x0090 // SDIO Host Extension Interrupt Mask Always
|
||||
#define SDIO_REG_HISR_ON 0x0091 // SDIO Host Extension Interrupt Status Always
|
||||
|
||||
#define SDIO_HIMR_DISABLED 0
|
||||
|
||||
// SDIO Host Interrupt Mask Register
|
||||
#define SDIO_HIMR_RX_REQUEST_MSK BIT0
|
||||
#define SDIO_HIMR_AVAL_MSK BIT1
|
||||
#define SDIO_HIMR_TXERR_MSK BIT2
|
||||
#define SDIO_HIMR_RXERR_MSK BIT3
|
||||
#define SDIO_HIMR_TXFOVW_MSK BIT4
|
||||
#define SDIO_HIMR_RXFOVW_MSK BIT5
|
||||
#define SDIO_HIMR_TXBCNOK_MSK BIT6
|
||||
#define SDIO_HIMR_TXBCNERR_MSK BIT7
|
||||
#define SDIO_HIMR_BCNERLY_INT_MSK BIT16
|
||||
#define SDIO_HIMR_C2HCMD_MSK BIT17
|
||||
#define SDIO_HIMR_CPWM1_MSK BIT18
|
||||
#define SDIO_HIMR_CPWM2_MSK BIT19
|
||||
#define SDIO_HIMR_HSISR_IND_MSK BIT20
|
||||
#define SDIO_HIMR_GTINT3_IND_MSK BIT21
|
||||
#define SDIO_HIMR_GTINT4_IND_MSK BIT22
|
||||
#define SDIO_HIMR_PSTIMEOUT_MSK BIT23
|
||||
#define SDIO_HIMR_OCPINT_MSK BIT24
|
||||
#define SDIO_HIMR_ATIMEND_MSK BIT25
|
||||
#define SDIO_HIMR_ATIMEND_E_MSK BIT26
|
||||
#define SDIO_HIMR_CTWEND_MSK BIT27
|
||||
|
||||
// SDIO Host Interrupt Service Routine
|
||||
#define SDIO_HISR_RX_REQUEST BIT0
|
||||
#define SDIO_HISR_AVAL BIT1
|
||||
#define SDIO_HISR_TXERR BIT2
|
||||
#define SDIO_HISR_RXERR BIT3
|
||||
#define SDIO_HISR_TXFOVW BIT4
|
||||
#define SDIO_HISR_RXFOVW BIT5
|
||||
#define SDIO_HISR_TXBCNOK BIT6
|
||||
#define SDIO_HISR_TXBCNERR BIT7
|
||||
#define SDIO_HISR_BCNERLY_INT BIT16
|
||||
#define SDIO_HISR_C2HCMD BIT17
|
||||
#define SDIO_HISR_CPWM1 BIT18
|
||||
#define SDIO_HISR_CPWM2 BIT19
|
||||
#define SDIO_HISR_HSISR_IND BIT20
|
||||
#define SDIO_HISR_GTINT3_IND BIT21
|
||||
#define SDIO_HISR_GTINT4_IND BIT22
|
||||
#define SDIO_HISR_PSTIME BIT23
|
||||
#define SDIO_HISR_OCPINT BIT24
|
||||
#define SDIO_HISR_ATIMEND BIT25
|
||||
#define SDIO_HISR_ATIMEND_E BIT26
|
||||
#define SDIO_HISR_CTWEND BIT27
|
||||
|
||||
#define MASK_SDIO_HISR_CLEAR (SDIO_HISR_TXERR |\
|
||||
SDIO_HISR_RXERR |\
|
||||
SDIO_HISR_TXFOVW |\
|
||||
SDIO_HISR_RXFOVW |\
|
||||
SDIO_HISR_TXBCNOK |\
|
||||
SDIO_HISR_TXBCNERR |\
|
||||
SDIO_HISR_C2HCMD |\
|
||||
SDIO_HISR_CPWM1 |\
|
||||
SDIO_HISR_CPWM2 |\
|
||||
SDIO_HISR_HSISR_IND |\
|
||||
SDIO_HISR_GTINT3_IND |\
|
||||
SDIO_HISR_GTINT4_IND |\
|
||||
SDIO_HISR_PSTIMEOUT |\
|
||||
SDIO_HISR_OCPINT)
|
||||
|
||||
// SDIO HCI Suspend Control Register
|
||||
#define HCI_RESUME_PWR_RDY BIT1
|
||||
#define HCI_SUS_CTRL BIT0
|
||||
|
||||
// SDIO Tx FIFO related
|
||||
#define SDIO_TX_FREE_PG_QUEUE 4 // The number of Tx FIFO free page
|
||||
#define SDIO_TX_FIFO_PAGE_SZ 128
|
||||
|
||||
// vivi added for new cam search flow, 20091028
|
||||
#define SCR_TxUseBroadcastDK BIT6 // Force Tx Use Broadcast Default Key
|
||||
#define SCR_RxUseBroadcastDK BIT7 // Force Rx Use Broadcast Default Key
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// 8723 EFUSE
|
||||
//----------------------------------------------------------------------------
|
||||
#ifdef HWSET_MAX_SIZE
|
||||
#undef HWSET_MAX_SIZE
|
||||
#endif
|
||||
#define HWSET_MAX_SIZE 256
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
//USB interrupt
|
||||
//-----------------------------------------------------------------------------
|
||||
#define UHIMR_TIMEOUT2 BIT31
|
||||
#define UHIMR_TIMEOUT1 BIT30
|
||||
#define UHIMR_PSTIME BIT29
|
||||
#define UHIMR_GTINT4 BIT28
|
||||
#define UHIMR_GTINT3 BIT27
|
||||
#define UHIMR_TXBCNERR BIT26
|
||||
#define UHIMR_TXBCNOK BIT25
|
||||
#define UHIMR_TSF_BIT32_TOGGLE BIT24
|
||||
#define UHIMR_BCNDMAINT3 BIT23
|
||||
#define UHIMR_BCNDMAINT2 BIT22
|
||||
#define UHIMR_BCNDMAINT1 BIT21
|
||||
#define UHIMR_BCNDMAINT0 BIT20
|
||||
#define UHIMR_BCNDOK3 BIT19
|
||||
#define UHIMR_BCNDOK2 BIT18
|
||||
#define UHIMR_BCNDOK1 BIT17
|
||||
#define UHIMR_BCNDOK0 BIT16
|
||||
#define UHIMR_HSISR_IND BIT15
|
||||
#define UHIMR_BCNDMAINT_E BIT14
|
||||
//RSVD BIT13
|
||||
#define UHIMR_CTW_END BIT12
|
||||
//RSVD BIT11
|
||||
#define UHIMR_C2HCMD BIT10
|
||||
#define UHIMR_CPWM2 BIT9
|
||||
#define UHIMR_CPWM BIT8
|
||||
#define UHIMR_HIGHDOK BIT7 // High Queue DMA OK Interrupt
|
||||
#define UHIMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt
|
||||
#define UHIMR_BKDOK BIT5 // AC_BK DMA OK Interrupt
|
||||
#define UHIMR_BEDOK BIT4 // AC_BE DMA OK Interrupt
|
||||
#define UHIMR_VIDOK BIT3 // AC_VI DMA OK Interrupt
|
||||
#define UHIMR_VODOK BIT2 // AC_VO DMA Interrupt
|
||||
#define UHIMR_RDU BIT1 // Receive Descriptor Unavailable
|
||||
#define UHIMR_ROK BIT0 // Receive DMA OK Interrupt
|
||||
|
||||
// USB Host Interrupt Status Extension bit
|
||||
#define UHIMR_BCNDMAINT7 BIT23
|
||||
#define UHIMR_BCNDMAINT6 BIT22
|
||||
#define UHIMR_BCNDMAINT5 BIT21
|
||||
#define UHIMR_BCNDMAINT4 BIT20
|
||||
#define UHIMR_BCNDOK7 BIT19
|
||||
#define UHIMR_BCNDOK6 BIT18
|
||||
#define UHIMR_BCNDOK5 BIT17
|
||||
#define UHIMR_BCNDOK4 BIT16
|
||||
// bit14-15: RSVD
|
||||
#define UHIMR_ATIMEND_E BIT13
|
||||
#define UHIMR_ATIMEND BIT12
|
||||
#define UHIMR_TXERR BIT11
|
||||
#define UHIMR_RXERR BIT10
|
||||
#define UHIMR_TXFOVW BIT9
|
||||
#define UHIMR_RXFOVW BIT8
|
||||
// bit2-7: RSVD
|
||||
#define UHIMR_OCPINT BIT1
|
||||
// bit0: RSVD
|
||||
|
||||
#define REG_USB_HIMR 0xFE38
|
||||
#define REG_USB_HIMRE 0xFE3C
|
||||
#define REG_USB_HISR 0xFE78
|
||||
#define REG_USB_HISRE 0xFE7C
|
||||
|
||||
#define USB_INTR_CPWM_OFFSET 16
|
||||
#define USB_INTR_CONTENT_HISR_OFFSET 48
|
||||
#define USB_INTR_CONTENT_HISRE_OFFSET 52
|
||||
#define USB_INTR_CONTENT_LENGTH 56
|
||||
#define USB_C2H_CMDID_OFFSET 0
|
||||
#define USB_C2H_SEQ_OFFSET 1
|
||||
#define USB_C2H_EVENT_OFFSET 2
|
||||
//============================================================================
|
||||
// General definitions
|
||||
//============================================================================
|
||||
|
||||
|
||||
#endif
|
|
@ -1,33 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef _RTL8188E_SRESET_H_
|
||||
#define _RTL8188E_SRESET_H_
|
||||
|
||||
#include <drv_conf.h>
|
||||
#include <osdep_service.h>
|
||||
#include <drv_types.h>
|
||||
#include <rtw_sreset.h>
|
||||
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
extern void rtl8723a_silentreset_for_specific_platform(_adapter *padapter);
|
||||
extern void rtl8723a_sreset_xmit_status_check(_adapter *padapter);
|
||||
extern void rtl8723a_sreset_linked_status_check(_adapter *padapter);
|
||||
#endif
|
||||
#endif
|
|
@ -1,235 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __RTL8723A_XMIT_H__
|
||||
#define __RTL8723A_XMIT_H__
|
||||
|
||||
#include <rtl8192c_xmit.h>
|
||||
|
||||
//
|
||||
//defined for TX DESC Operation
|
||||
//
|
||||
|
||||
#define MAX_TID (15)
|
||||
|
||||
//OFFSET 0
|
||||
#define OFFSET_SZ 0
|
||||
#define OFFSET_SHT 16
|
||||
#define BMC BIT(24)
|
||||
#define LSG BIT(26)
|
||||
#define FSG BIT(27)
|
||||
#define OWN BIT(31)
|
||||
|
||||
|
||||
//OFFSET 4
|
||||
#define PKT_OFFSET_SZ 0
|
||||
#define BK BIT(6)
|
||||
#define QSEL_SHT 8
|
||||
#define Rate_ID_SHT 16
|
||||
#define NAVUSEHDR BIT(20)
|
||||
#define PKT_OFFSET_SHT 26
|
||||
#define HWPC BIT(31)
|
||||
|
||||
//OFFSET 8
|
||||
#define AGG_EN BIT(29)
|
||||
|
||||
//OFFSET 12
|
||||
#define SEQ_SHT 16
|
||||
|
||||
//OFFSET 16
|
||||
#define QoS BIT(6)
|
||||
#define HW_SEQ_EN BIT(7)
|
||||
#define USERATE BIT(8)
|
||||
#define DISDATAFB BIT(10)
|
||||
#define DATA_SHORT BIT(24)
|
||||
#define DATA_BW BIT(25)
|
||||
|
||||
//OFFSET 20
|
||||
#define SGI BIT(6)
|
||||
|
||||
typedef struct txdesc_8723a
|
||||
{
|
||||
u32 pktlen:16;
|
||||
u32 offset:8;
|
||||
u32 bmc:1;
|
||||
u32 htc:1;
|
||||
u32 ls:1;
|
||||
u32 fs:1;
|
||||
u32 linip:1;
|
||||
u32 noacm:1;
|
||||
u32 gf:1;
|
||||
u32 own:1;
|
||||
|
||||
u32 macid:5;
|
||||
u32 agg_en:1;
|
||||
u32 bk:1;
|
||||
u32 rd_en:1;
|
||||
u32 qsel:5;
|
||||
u32 rd_nav_ext:1;
|
||||
u32 lsig_txop_en:1;
|
||||
u32 pifs:1;
|
||||
u32 rate_id:4;
|
||||
u32 navusehdr:1;
|
||||
u32 en_desc_id:1;
|
||||
u32 sectype:2;
|
||||
u32 rsvd0424:2;
|
||||
u32 pkt_offset:5; // unit: 8 bytes
|
||||
u32 rsvd0431:1;
|
||||
|
||||
u32 rts_rc:6;
|
||||
u32 data_rc:6;
|
||||
u32 rsvd0812:2;
|
||||
u32 bar_rty_th:2;
|
||||
u32 rsvd0816:1;
|
||||
u32 morefrag:1;
|
||||
u32 raw:1;
|
||||
u32 ccx:1;
|
||||
u32 ampdu_density:3;
|
||||
u32 bt_null:1;
|
||||
u32 ant_sel_a:1;
|
||||
u32 ant_sel_b:1;
|
||||
u32 tx_ant_cck:2;
|
||||
u32 tx_antl:2;
|
||||
u32 tx_ant_ht:2;
|
||||
|
||||
u32 nextheadpage:8;
|
||||
u32 tailpage:8;
|
||||
u32 seq:12;
|
||||
u32 cpu_handle:1;
|
||||
u32 tag1:1;
|
||||
u32 trigger_int:1;
|
||||
u32 hwseq_en:1;
|
||||
|
||||
u32 rtsrate:5;
|
||||
u32 ap_dcfe:1;
|
||||
u32 hwseq_sel:2;
|
||||
u32 userate:1;
|
||||
u32 disrtsfb:1;
|
||||
u32 disdatafb:1;
|
||||
u32 cts2self:1;
|
||||
u32 rtsen:1;
|
||||
u32 hw_rts_en:1;
|
||||
u32 port_id:1;
|
||||
u32 rsvd1615:3;
|
||||
u32 wait_dcts:1;
|
||||
u32 cts2ap_en:1;
|
||||
u32 data_sc:2;
|
||||
u32 data_stbc:2;
|
||||
u32 data_short:1;
|
||||
u32 data_bw:1;
|
||||
u32 rts_short:1;
|
||||
u32 rts_bw:1;
|
||||
u32 rts_sc:2;
|
||||
u32 vcs_stbc:2;
|
||||
|
||||
u32 datarate:6;
|
||||
u32 sgi:1;
|
||||
u32 try_rate:1;
|
||||
u32 data_ratefb_lmt:5;
|
||||
u32 rts_ratefb_lmt:4;
|
||||
u32 rty_lmt_en:1;
|
||||
u32 data_rt_lmt:6;
|
||||
u32 usb_txagg_num:8;
|
||||
|
||||
u32 txagg_a:5;
|
||||
u32 txagg_b:5;
|
||||
u32 use_max_len:1;
|
||||
u32 max_agg_num:5;
|
||||
u32 mcsg1_max_len:4;
|
||||
u32 mcsg2_max_len:4;
|
||||
u32 mcsg3_max_len:4;
|
||||
u32 mcs7_sgi_max_len:4;
|
||||
|
||||
u32 checksum:16; // TxBuffSize(PCIe)/CheckSum(USB)
|
||||
u32 mcsg4_max_len:4;
|
||||
u32 mcsg5_max_len:4;
|
||||
u32 mcsg6_max_len:4;
|
||||
u32 mcs15_sgi_max_len:4;
|
||||
}TXDESC, *PTXDESC;
|
||||
|
||||
#define txdesc_set_ccx_sw_8723a(txdesc, value) \
|
||||
do { \
|
||||
((struct txdesc_8723a *)(txdesc))->mcsg4_max_len = (((value)>>8) & 0x0f); \
|
||||
((struct txdesc_8723a *)(txdesc))->mcs15_sgi_max_len= (((value)>>4) & 0x0f); \
|
||||
((struct txdesc_8723a *)(txdesc))->mcsg6_max_len = ((value) & 0x0f); \
|
||||
} while (0)
|
||||
|
||||
struct txrpt_ccx_8723a {
|
||||
/* offset 0 */
|
||||
u8 tag1:1;
|
||||
u8 rsvd:4;
|
||||
u8 int_bt:1;
|
||||
u8 int_tri:1;
|
||||
u8 int_ccx:1;
|
||||
|
||||
/* offset 1 */
|
||||
u8 mac_id:5;
|
||||
u8 pkt_drop:1;
|
||||
u8 pkt_ok:1;
|
||||
u8 bmc:1;
|
||||
|
||||
/* offset 2 */
|
||||
u8 retry_cnt:6;
|
||||
u8 lifetime_over:1;
|
||||
u8 retry_over:1;
|
||||
|
||||
/* offset 3 */
|
||||
u8 ccx_qtime0;
|
||||
u8 ccx_qtime1;
|
||||
|
||||
/* offset 5 */
|
||||
u8 final_data_rate;
|
||||
|
||||
/* offset 6 */
|
||||
u8 sw1:4;
|
||||
u8 qsel:4;
|
||||
|
||||
/* offset 7 */
|
||||
u8 sw0;
|
||||
};
|
||||
|
||||
#define txrpt_ccx_sw_8723a(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8))
|
||||
#define txrpt_ccx_qtime_8723a(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
|
||||
|
||||
#ifdef CONFIG_XMIT_ACK
|
||||
void dump_txrpt_ccx_8723a(void *buf);
|
||||
void handle_txrpt_ccx_8723a(_adapter *adapter, void *buf);
|
||||
#else
|
||||
#define dump_txrpt_ccx_8723a(buf) do {} while (0)
|
||||
#define handle_txrpt_ccx_8723a(adapter, buf) do {} while (0)
|
||||
#endif //CONFIG_XMIT_ACK
|
||||
|
||||
void rtl8723a_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
|
||||
void rtl8723a_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull);
|
||||
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
s32 rtl8723as_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8723as_free_xmit_priv(PADAPTER padapter);
|
||||
s32 rtl8723as_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8723as_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
s32 rtl8723as_xmit_buf_handler(PADAPTER padapter);
|
||||
thread_return rtl8723as_xmit_thread(thread_context context);
|
||||
#define hal_xmit_handler rtl8723as_xmit_buf_handler
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
s32 rtl8723au_xmit_buf_handler(PADAPTER padapter);
|
||||
#define hal_xmit_handler rtl8723au_xmit_buf_handler
|
||||
#endif
|
||||
#endif
|
|
@ -182,19 +182,7 @@ struct mp_tx
|
|||
_thread_hdl_ PktTxThread;
|
||||
};
|
||||
|
||||
#if defined(CONFIG_RTL8192C) || defined(CONFIG_RTL8192D) || defined(CONFIG_RTL8723A) || defined(CONFIG_RTL8188E)
|
||||
#ifdef CONFIG_RTL8192C
|
||||
#include <Hal8192CPhyCfg.h>
|
||||
#endif
|
||||
#ifdef CONFIG_RTL8192D
|
||||
#include <Hal8192DPhyCfg.h>
|
||||
#endif
|
||||
#ifdef CONFIG_RTL8723A
|
||||
#include <Hal8723APhyCfg.h>
|
||||
#endif
|
||||
#ifdef CONFIG_RTL8188E
|
||||
#include <Hal8188EPhyCfg.h>
|
||||
#endif
|
||||
|
||||
#define MP_MAX_LINES 1000
|
||||
#define MP_MAX_LINES_BYTES 256
|
||||
|
@ -335,10 +323,7 @@ typedef struct _MPT_CONTEXT
|
|||
u1Byte mptOutBuf[100];
|
||||
|
||||
}MPT_CONTEXT, *PMPT_CONTEXT;
|
||||
#endif
|
||||
//#endif
|
||||
|
||||
//#define RTPRIV_IOCTL_MP ( SIOCIWFIRSTPRIV + 0x17)
|
||||
enum {
|
||||
WRITE_REG = 1,
|
||||
READ_REG,
|
||||
|
|
|
@ -32,18 +32,7 @@ struct sreset_priv {
|
|||
unsigned long last_tx_complete_time;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_RTL8192C
|
||||
#include <rtl8192c_hal.h>
|
||||
#endif
|
||||
#ifdef CONFIG_RTL8192D
|
||||
#include <rtl8192d_hal.h>
|
||||
#endif
|
||||
#ifdef CONFIG_RTL8723A
|
||||
#include <rtl8723a_hal.h>
|
||||
#endif
|
||||
#ifdef CONFIG_RTL8188E
|
||||
#include <rtl8188e_hal.h>
|
||||
#endif
|
||||
|
||||
#define WIFI_STATUS_SUCCESS 0
|
||||
#define USB_VEN_REQ_CMD_FAIL BIT0
|
||||
|
|
Loading…
Reference in a new issue