mirror of
https://github.com/lwfinger/rtl8188eu.git
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rtl8188eu: Remove unused header files
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
parent
b2720d8002
commit
067adff3fd
11 changed files with 0 additions and 3485 deletions
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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/*****************************************************************************
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* Module: __INC_HAL8192CPHYCFG_H
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*
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*
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* Note:
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*
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*
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* Export: Constants, macro, functions(API), global variables(None).
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*
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* Abbrev:
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*
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* History:
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* Data Who Remark
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* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
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* 2. Reorganize code architecture.
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*
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*****************************************************************************/
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/* Check to see if the file has been included already. */
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#ifndef __INC_HAL8192CPHYCFG_H
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#define __INC_HAL8192CPHYCFG_H
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/*--------------------------Define Parameters-------------------------------*/
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#define LOOP_LIMIT 5
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#define MAX_STALL_TIME 50 /* us */
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#define AntennaDiversityValue 0x80 /* Adapter->bSoftwareAntennaDiversity ? 0x00:0x80) */
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#define MAX_TXPWR_IDX_NMODE_92S 63
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#define Reset_Cnt_Limit 3
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#define MAX_AGGR_NUM 0x0909
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/*--------------------------Define Parameters-------------------------------*/
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/*------------------------------Define structure----------------------------*/
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typedef enum _SwChnlCmdID{
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CmdID_End,
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CmdID_SetTxPowerLevel,
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CmdID_BBRegWrite10,
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CmdID_WritePortUlong,
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CmdID_WritePortUshort,
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CmdID_WritePortUchar,
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CmdID_RF_WriteReg,
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}SwChnlCmdID;
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/* 1. Switch channel related */
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typedef struct _SwChnlCmd{
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SwChnlCmdID CmdID;
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u32 Para1;
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u32 Para2;
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u32 msDelay;
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}SwChnlCmd;
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typedef enum _HW90_BLOCK{
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HW90_BLOCK_MAC = 0,
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HW90_BLOCK_PHY0 = 1,
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HW90_BLOCK_PHY1 = 2,
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HW90_BLOCK_RF = 3,
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HW90_BLOCK_MAXIMUM = 4, /* Never use this */
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}HW90_BLOCK_E, *PHW90_BLOCK_E;
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typedef enum _RF_RADIO_PATH{
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RF_PATH_A = 0, /* Radio Path A */
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RF_PATH_B = 1, /* Radio Path B */
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RF_PATH_C = 2, /* Radio Path C */
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RF_PATH_D = 3, /* Radio Path D */
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/* RF_PATH_MAX Max RF number 90 support */
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}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E;
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#define RF_PATH_MAX 2
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#define CHANNEL_MAX_NUMBER 14 /* 14 is the max channel number */
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#define CHANNEL_GROUP_MAX 3 /* ch1~3, ch4~9, ch10~14 total three groups */
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typedef enum _WIRELESS_MODE {
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WIRELESS_MODE_UNKNOWN = 0x00,
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WIRELESS_MODE_A = BIT2,
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WIRELESS_MODE_B = BIT0,
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WIRELESS_MODE_G = BIT1,
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WIRELESS_MODE_AUTO = BIT5,
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WIRELESS_MODE_N_24G = BIT3,
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WIRELESS_MODE_N_5G = BIT4,
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WIRELESS_MODE_AC = BIT6
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} WIRELESS_MODE;
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typedef enum _BaseBand_Config_Type{
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BaseBand_Config_PHY_REG = 0, /* Radio Path A */
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BaseBand_Config_AGC_TAB = 1, /* Radio Path B */
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}BaseBand_Config_Type, *PBaseBand_Config_Type;
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typedef enum _PHY_Rate_Tx_Power_Offset_Area{
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RA_OFFSET_LEGACY_OFDM1,
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RA_OFFSET_LEGACY_OFDM2,
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RA_OFFSET_HT_OFDM1,
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RA_OFFSET_HT_OFDM2,
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RA_OFFSET_HT_OFDM3,
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RA_OFFSET_HT_OFDM4,
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RA_OFFSET_HT_CCK,
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}RA_OFFSET_AREA,*PRA_OFFSET_AREA;
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/* BB/RF related */
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typedef enum _RF_TYPE_8190P{
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RF_TYPE_MIN, /* 0 */
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RF_8225=1, /* 1 11b/g RF for verification only */
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RF_8256=2, /* 2 11b/g/n */
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RF_8258=3, /* 3 11a/b/g/n RF */
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RF_6052=4, /* 4 11b/g/n RF */
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/* TODO: We should remove this psudo PHY RF after we get new RF. */
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RF_PSEUDO_11N=5, /* 5, It is a temporality RF. */
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}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
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typedef struct _BB_REGISTER_DEFINITION{
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u32 rfintfs; /* set software control: */
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/* 0x870~0x877[8 bytes] */
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u32 rfintfi; /* readback data: */
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/* 0x8e0~0x8e7[8 bytes] */
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u32 rfintfo; /* output data: */
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/* 0x860~0x86f [16 bytes] */
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u32 rfintfe; /* output enable: */
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/* 0x860~0x86f [16 bytes] */
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u32 rf3wireOffset; /* LSSI data: */
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/* 0x840~0x84f [16 bytes] */
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u32 rfLSSI_Select; /* BB Band Select: */
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/* 0x878~0x87f [8 bytes] */
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u32 rfTxGainStage; /* Tx gain stage: */
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/* 0x80c~0x80f [4 bytes] */
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u32 rfHSSIPara1; /* wire parameter control1 : */
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/* 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] */
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u32 rfHSSIPara2; /* wire parameter control2 : */
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/* 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] */
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u32 rfSwitchControl; /* Tx Rx antenna control : */
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/* 0x858~0x85f [16 bytes] */
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u32 rfAGCControl1; /* AGC parameter control1 : */
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/* 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] */
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u32 rfAGCControl2; /* AGC parameter control2 : */
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/* 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] */
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u32 rfRxIQImbalance; /* OFDM Rx IQ imbalance matrix : */
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/* 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] */
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u32 rfRxAFE; /* Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : */
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/* 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] */
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u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */
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/* 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] */
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u32 rfTxAFE; /* Tx IQ DC Offset and Tx DFIR type */
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/* 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] */
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u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */
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/* 0x8a0~0x8af [16 bytes] */
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u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for Path A and B */
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}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
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typedef struct _R_ANTENNA_SELECT_OFDM{
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u32 r_tx_antenna:4;
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u32 r_ant_l:4;
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u32 r_ant_non_ht:4;
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u32 r_ant_ht1:4;
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u32 r_ant_ht2:4;
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u32 r_ant_ht_s1:4;
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u32 r_ant_non_ht_s1:4;
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u32 OFDM_TXSC:2;
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u32 Reserved:2;
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}R_ANTENNA_SELECT_OFDM;
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typedef struct _R_ANTENNA_SELECT_CCK{
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u8 r_cckrx_enable_2:2;
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u8 r_cckrx_enable:2;
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u8 r_ccktx_enable:4;
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}R_ANTENNA_SELECT_CCK;
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/*------------------------------Define structure----------------------------*/
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/*------------------------Export global variable----------------------------*/
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/*------------------------Export global variable----------------------------*/
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/*------------------------Export Marco Definition---------------------------*/
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/*------------------------Export Marco Definition---------------------------*/
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/*--------------------------Exported Function prototype---------------------*/
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/* */
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/* BB and RF register read/write */
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/* */
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u32 rtl8192c_PHY_QueryBBReg( IN struct adapter *Adapter,
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IN u32 RegAddr,
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IN u32 BitMask );
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void rtl8192c_PHY_SetBBReg( IN struct adapter *Adapter,
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IN u32 RegAddr,
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IN u32 BitMask,
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IN u32 Data );
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u32 rtl8192c_PHY_QueryRFReg( IN struct adapter * Adapter,
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IN RF_RADIO_PATH_E eRFPath,
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IN u32 RegAddr,
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IN u32 BitMask );
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void rtl8192c_PHY_SetRFReg( IN struct adapter * Adapter,
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IN RF_RADIO_PATH_E eRFPath,
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IN u32 RegAddr,
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IN u32 BitMask,
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IN u32 Data );
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/* */
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/* Initialization related function */
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/* */
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/* MAC/BB/RF HAL config */
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int PHY_MACConfig8192C( IN struct adapter *Adapter );
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int PHY_BBConfig8192C( IN struct adapter *Adapter );
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int PHY_RFConfig8192C( IN struct adapter *Adapter );
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/* RF config */
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int rtl8192c_PHY_ConfigRFWithParaFile( IN struct adapter *Adapter,
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IN u8* pFileName,
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IN RF_RADIO_PATH_E eRFPath);
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int rtl8192c_PHY_ConfigRFWithHeaderFile( IN struct adapter * Adapter,
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IN RF_RADIO_PATH_E eRFPath);
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/* BB/RF readback check for making sure init OK */
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int rtl8192c_PHY_CheckBBAndRFOK( IN struct adapter * Adapter,
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IN HW90_BLOCK_E CheckBlock,
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IN RF_RADIO_PATH_E eRFPath );
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/* Read initi reg value for tx power setting. */
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void rtl8192c_PHY_GetHWRegOriginalValue( IN struct adapter * Adapter );
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/* */
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/* RF Power setting */
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/* */
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/* extern bool PHY_SetRFPowerState(IN struct adapter * Adapter, */
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/* IN RT_RF_POWER_STATE eRFPowerState); */
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/* */
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/* BB TX Power R/W */
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/* */
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void PHY_GetTxPowerLevel8192C( IN struct adapter * Adapter,
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OUT u32* powerlevel );
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void PHY_SetTxPowerLevel8192C( IN struct adapter * Adapter,
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IN u8 channel );
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bool PHY_UpdateTxPowerDbm8192C( IN struct adapter *Adapter,
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IN int powerInDbm );
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/* */
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void
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PHY_ScanOperationBackup8192C(IN struct adapter *Adapter,
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IN u8 Operation );
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/* */
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/* Switch bandwidth for 8192S */
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/* */
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/* extern void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer ); */
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void PHY_SetBWMode8192C( IN struct adapter * pAdapter,
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IN HT_CHANNEL_WIDTH ChnlWidth,
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IN unsigned char Offset );
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/* */
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/* Set FW CMD IO for 8192S. */
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/* */
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/* extern bool HalSetIO8192C( IN struct adapter * Adapter, */
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/* IN IO_TYPE IOType); */
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/* */
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/* Set A2 entry to fw for 8192S */
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/* */
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extern void FillA2Entry8192C( IN struct adapter * Adapter,
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IN u8 index,
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IN u8* val);
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/* */
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/* channel switch related funciton */
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/* */
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/* extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer ); */
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void PHY_SwChnl8192C( IN struct adapter * pAdapter,
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IN u8 channel );
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/* Call after initialization */
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void PHY_SwChnlPhy8192C( IN struct adapter * pAdapter,
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IN u8 channel );
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void ChkFwCmdIoDone( IN struct adapter *Adapter);
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/* */
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/* BB/MAC/RF other monitor API */
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/* */
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void PHY_SetMonitorMode8192C(IN struct adapter *pAdapter,
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IN bool bEnableMonitorMode );
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bool PHY_CheckIsLegalRfPath8192C(IN struct adapter *pAdapter,
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IN u32 eRFPath );
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void rtl8192c_PHY_SetRFPathSwitch(IN struct adapter *pAdapter, IN bool bMain);
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/* */
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/* Modify the value of the hw register when beacon interval be changed. */
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/* */
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void
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rtl8192c_PHY_SetBeaconHwReg( IN struct adapter * Adapter,
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IN u16 BeaconInterval );
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extern void
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PHY_SwitchEphyParameter(
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IN struct adapter * Adapter
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);
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extern void
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PHY_EnableHostClkReq(
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IN struct adapter * Adapter
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);
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bool
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SetAntennaConfig92C(
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IN struct adapter *Adapter,
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IN u8 DefaultAnt
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);
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/*--------------------------Exported Function prototype---------------------*/
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#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtl8192c_PHY_QueryBBReg((Adapter), (RegAddr), (BitMask))
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#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtl8192c_PHY_SetBBReg((Adapter), (RegAddr), (BitMask), (Data))
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#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtl8192c_PHY_QueryRFReg((Adapter), (eRFPath), (RegAddr), (BitMask))
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#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtl8192c_PHY_SetRFReg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
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#define PHY_SetMacReg PHY_SetBBReg
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#define PHY_QueryMacReg PHY_QueryBBReg
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|
||||||
|
|
||||||
#endif /* __INC_HAL8192CPHYCFG_H */
|
|
||||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,462 +0,0 @@
|
||||||
/******************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify it
|
|
||||||
* under the terms of version 2 of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
|
||||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
||||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
||||||
* more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License along with
|
|
||||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
|
||||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
|
||||||
*
|
|
||||||
*
|
|
||||||
******************************************************************************/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Module: __INC_HAL8192DPHYCFG_H
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* Note:
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* Export: Constants, macro, functions(API), global variables(None).
|
|
||||||
*
|
|
||||||
* Abbrev:
|
|
||||||
*
|
|
||||||
* History:
|
|
||||||
* Data Who Remark
|
|
||||||
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
|
|
||||||
* 2. Reorganize code architecture.
|
|
||||||
*
|
|
||||||
*****************************************************************************/
|
|
||||||
/* Check to see if the file has been included already. */
|
|
||||||
#ifndef __INC_HAL8192DPHYCFG_H
|
|
||||||
#define __INC_HAL8192DPHYCFG_H
|
|
||||||
|
|
||||||
|
|
||||||
/*--------------------------Define Parameters-------------------------------*/
|
|
||||||
#define LOOP_LIMIT 5
|
|
||||||
#define MAX_STALL_TIME 50 /* us */
|
|
||||||
#define AntennaDiversityValue 0x80 /* Adapter->bSoftwareAntennaDiversity ? 0x00:0x80) */
|
|
||||||
#define MAX_TXPWR_IDX_NMODE_92S 63
|
|
||||||
#define Reset_Cnt_Limit 3
|
|
||||||
|
|
||||||
|
|
||||||
/*--------------------------Define Parameters-------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
/*------------------------------Define structure----------------------------*/
|
|
||||||
typedef enum _SwChnlCmdID{
|
|
||||||
CmdID_End,
|
|
||||||
CmdID_SetTxPowerLevel,
|
|
||||||
CmdID_BBRegWrite10,
|
|
||||||
CmdID_WritePortUlong,
|
|
||||||
CmdID_WritePortUshort,
|
|
||||||
CmdID_WritePortUchar,
|
|
||||||
CmdID_RF_WriteReg,
|
|
||||||
}SwChnlCmdID;
|
|
||||||
|
|
||||||
|
|
||||||
/* 1. Switch channel related */
|
|
||||||
typedef struct _SwChnlCmd{
|
|
||||||
SwChnlCmdID CmdID;
|
|
||||||
u32 Para1;
|
|
||||||
u32 Para2;
|
|
||||||
u32 msDelay;
|
|
||||||
}SwChnlCmd;
|
|
||||||
|
|
||||||
typedef enum _HW90_BLOCK{
|
|
||||||
HW90_BLOCK_MAC = 0,
|
|
||||||
HW90_BLOCK_PHY0 = 1,
|
|
||||||
HW90_BLOCK_PHY1 = 2,
|
|
||||||
HW90_BLOCK_RF = 3,
|
|
||||||
HW90_BLOCK_MAXIMUM = 4, /* Never use this */
|
|
||||||
}HW90_BLOCK_E, *PHW90_BLOCK_E;
|
|
||||||
|
|
||||||
/* vivi added this for read parameter from header, 20100908 */
|
|
||||||
typedef enum _RF_CONTENT{
|
|
||||||
radioa_txt = 0x1000,
|
|
||||||
radiob_txt = 0x1001,
|
|
||||||
radioc_txt = 0x1002,
|
|
||||||
radiod_txt = 0x1003
|
|
||||||
} RF_CONTENT;
|
|
||||||
|
|
||||||
typedef enum _RF_RADIO_PATH{
|
|
||||||
RF_PATH_A = 0, /* Radio Path A */
|
|
||||||
RF_PATH_B = 1, /* Radio Path B */
|
|
||||||
RF_PATH_C = 2, /* Radio Path C */
|
|
||||||
RF_PATH_D = 3, /* Radio Path D */
|
|
||||||
/* RF_PATH_MAX Max RF number 90 support */
|
|
||||||
}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E;
|
|
||||||
|
|
||||||
#define RF_PATH_MAX 2
|
|
||||||
|
|
||||||
|
|
||||||
typedef enum _WIRELESS_MODE {
|
|
||||||
WIRELESS_MODE_UNKNOWN = 0x00,
|
|
||||||
WIRELESS_MODE_A = 0x01,
|
|
||||||
WIRELESS_MODE_B = 0x02,
|
|
||||||
WIRELESS_MODE_G = 0x04,
|
|
||||||
WIRELESS_MODE_AUTO = 0x08,
|
|
||||||
WIRELESS_MODE_N_24G = 0x10,
|
|
||||||
WIRELESS_MODE_N_5G = 0x20
|
|
||||||
} WIRELESS_MODE;
|
|
||||||
|
|
||||||
|
|
||||||
#if(TX_POWER_FOR_5G_BAND == 1)
|
|
||||||
#define CHANNEL_MAX_NUMBER 14+24+21 /* 14 is the max channel number */
|
|
||||||
#define CHANNEL_GROUP_MAX 3+9 /* ch1~3, ch4~9, ch10~14 total three groups */
|
|
||||||
#define MAX_PG_GROUP 13
|
|
||||||
#else
|
|
||||||
#define CHANNEL_MAX_NUMBER 14 /* 14 is the max channel number */
|
|
||||||
#define CHANNEL_GROUP_MAX 3 /* ch1~3, ch4~9, ch10~14 total three groups */
|
|
||||||
#define MAX_PG_GROUP 7
|
|
||||||
#endif
|
|
||||||
#define CHANNEL_GROUP_MAX_2G 3
|
|
||||||
#define CHANNEL_GROUP_IDX_5GL 3
|
|
||||||
#define CHANNEL_GROUP_IDX_5GM 6
|
|
||||||
#define CHANNEL_GROUP_IDX_5GH 9
|
|
||||||
#define CHANNEL_GROUP_MAX_5G 9
|
|
||||||
#define CHANNEL_MAX_NUMBER_2G 14
|
|
||||||
|
|
||||||
#if (RTL8192D_DUAL_MAC_MODE_SWITCH == 1)
|
|
||||||
typedef enum _BaseBand_Config_Type{
|
|
||||||
BaseBand_Config_PHY_REG = 0,
|
|
||||||
BaseBand_Config_AGC_TAB = 1,
|
|
||||||
BaseBand_Config_AGC_TAB_2G = 2,
|
|
||||||
BaseBand_Config_AGC_TAB_5G = 3,
|
|
||||||
}BaseBand_Config_Type, *PBaseBand_Config_Type;
|
|
||||||
#else
|
|
||||||
typedef enum _BaseBand_Config_Type{
|
|
||||||
BaseBand_Config_PHY_REG = 0, /* Radio Path A */
|
|
||||||
BaseBand_Config_AGC_TAB = 1, /* Radio Path B */
|
|
||||||
}BaseBand_Config_Type, *PBaseBand_Config_Type;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
typedef enum _MACPHY_MODE_8192D{
|
|
||||||
SINGLEMAC_SINGLEPHY, /* SMSP */
|
|
||||||
DUALMAC_DUALPHY, /* DMDP */
|
|
||||||
DUALMAC_SINGLEPHY, /* DMSP */
|
|
||||||
}MACPHY_MODE_8192D,*PMACPHY_MODE_8192D;
|
|
||||||
|
|
||||||
typedef enum _MACPHY_MODE_CHANGE_ACTION{
|
|
||||||
DMDP2DMSP = 0,
|
|
||||||
DMSP2DMDP = 1,
|
|
||||||
DMDP2SMSP = 2,
|
|
||||||
SMSP2DMDP = 3,
|
|
||||||
DMSP2SMSP = 4,
|
|
||||||
SMSP2DMSP = 5,
|
|
||||||
MAXACTION
|
|
||||||
}MACPHY_MODE_CHANGE_ACTION,*PMACPHY_MODE_CHANGE_ACTION;
|
|
||||||
|
|
||||||
typedef enum _BAND_TYPE{
|
|
||||||
BAND_ON_2_4G = 1,
|
|
||||||
BAND_ON_5G = 2,
|
|
||||||
BAND_ON_BOTH,
|
|
||||||
BANDMAX
|
|
||||||
}BAND_TYPE,*PBAND_TYPE;
|
|
||||||
|
|
||||||
typedef enum _PHY_Rate_Tx_Power_Offset_Area{
|
|
||||||
RA_OFFSET_LEGACY_OFDM1,
|
|
||||||
RA_OFFSET_LEGACY_OFDM2,
|
|
||||||
RA_OFFSET_HT_OFDM1,
|
|
||||||
RA_OFFSET_HT_OFDM2,
|
|
||||||
RA_OFFSET_HT_OFDM3,
|
|
||||||
RA_OFFSET_HT_OFDM4,
|
|
||||||
RA_OFFSET_HT_CCK,
|
|
||||||
}RA_OFFSET_AREA,*PRA_OFFSET_AREA;
|
|
||||||
|
|
||||||
|
|
||||||
/* BB/RF related */
|
|
||||||
typedef enum _RF_TYPE_8190P{
|
|
||||||
RF_TYPE_MIN, /* 0 */
|
|
||||||
RF_8225=1, /* 1 11b/g RF for verification only */
|
|
||||||
RF_8256=2, /* 2 11b/g/n */
|
|
||||||
RF_8258=3, /* 3 11a/b/g/n RF */
|
|
||||||
RF_6052=4, /* 4 11b/g/n RF */
|
|
||||||
/* TODO: We sholud remove this psudo PHY RF after we get new RF. */
|
|
||||||
RF_PSEUDO_11N=5, /* 5, It is a temporality RF. */
|
|
||||||
}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
typedef struct _BB_REGISTER_DEFINITION{
|
|
||||||
u32 rfintfs; /* set software control: */
|
|
||||||
/* 0x870~0x877[8 bytes] */
|
|
||||||
|
|
||||||
u32 rfintfi; /* readback data: */
|
|
||||||
/* 0x8e0~0x8e7[8 bytes] */
|
|
||||||
|
|
||||||
u32 rfintfo; /* output data: */
|
|
||||||
/* 0x860~0x86f [16 bytes] */
|
|
||||||
|
|
||||||
u32 rfintfe; /* output enable: */
|
|
||||||
/* 0x860~0x86f [16 bytes] */
|
|
||||||
|
|
||||||
u32 rf3wireOffset; /* LSSI data: */
|
|
||||||
/* 0x840~0x84f [16 bytes] */
|
|
||||||
|
|
||||||
u32 rfLSSI_Select; /* BB Band Select: */
|
|
||||||
/* 0x878~0x87f [8 bytes] */
|
|
||||||
|
|
||||||
u32 rfTxGainStage; /* Tx gain stage: */
|
|
||||||
/* 0x80c~0x80f [4 bytes] */
|
|
||||||
|
|
||||||
u32 rfHSSIPara1; /* wire parameter control1 : */
|
|
||||||
/* 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] */
|
|
||||||
|
|
||||||
u32 rfHSSIPara2; /* wire parameter control2 : */
|
|
||||||
/* 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] */
|
|
||||||
|
|
||||||
u32 rfSwitchControl; /* Tx Rx antenna control : */
|
|
||||||
/* 0x858~0x85f [16 bytes] */
|
|
||||||
|
|
||||||
u32 rfAGCControl1; /* AGC parameter control1 : */
|
|
||||||
/* 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] */
|
|
||||||
|
|
||||||
u32 rfAGCControl2; /* AGC parameter control2 : */
|
|
||||||
/* 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] */
|
|
||||||
|
|
||||||
u32 rfRxIQImbalance; /* OFDM Rx IQ imbalance matrix : */
|
|
||||||
/* 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] */
|
|
||||||
|
|
||||||
u32 rfRxAFE; /* Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : */
|
|
||||||
/* 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] */
|
|
||||||
|
|
||||||
u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */
|
|
||||||
/* 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] */
|
|
||||||
|
|
||||||
u32 rfTxAFE; /* Tx IQ DC Offset and Tx DFIR type */
|
|
||||||
/* 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] */
|
|
||||||
|
|
||||||
u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */
|
|
||||||
/* 0x8a0~0x8af [16 bytes] */
|
|
||||||
|
|
||||||
u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for Path A and B */
|
|
||||||
|
|
||||||
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
|
|
||||||
|
|
||||||
|
|
||||||
typedef struct _R_ANTENNA_SELECT_OFDM{
|
|
||||||
u32 r_tx_antenna:4;
|
|
||||||
u32 r_ant_l:4;
|
|
||||||
u32 r_ant_non_ht:4;
|
|
||||||
u32 r_ant_ht1:4;
|
|
||||||
u32 r_ant_ht2:4;
|
|
||||||
u32 r_ant_ht_s1:4;
|
|
||||||
u32 r_ant_non_ht_s1:4;
|
|
||||||
u32 OFDM_TXSC:2;
|
|
||||||
u32 Reserved:2;
|
|
||||||
}R_ANTENNA_SELECT_OFDM;
|
|
||||||
|
|
||||||
typedef struct _R_ANTENNA_SELECT_CCK{
|
|
||||||
u8 r_cckrx_enable_2:2;
|
|
||||||
u8 r_cckrx_enable:2;
|
|
||||||
u8 r_ccktx_enable:4;
|
|
||||||
}R_ANTENNA_SELECT_CCK;
|
|
||||||
|
|
||||||
/*------------------------------Define structure----------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
/*------------------------Export global variable----------------------------*/
|
|
||||||
/*------------------------Export global variable----------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
/*------------------------Export Marco Definition---------------------------*/
|
|
||||||
|
|
||||||
/*--------------------------Exported Function prototype---------------------*/
|
|
||||||
/* */
|
|
||||||
/* BB and RF register read/write */
|
|
||||||
/* */
|
|
||||||
void rtl8192d_PHY_SetBBReg1Byte( IN struct adapter *Adapter,
|
|
||||||
IN u32 RegAddr,
|
|
||||||
IN u32 BitMask,
|
|
||||||
IN u32 Data );
|
|
||||||
u32 rtl8192d_PHY_QueryBBReg( IN struct adapter *Adapter,
|
|
||||||
IN u32 RegAddr,
|
|
||||||
IN u32 BitMask );
|
|
||||||
void rtl8192d_PHY_SetBBReg( IN struct adapter *Adapter,
|
|
||||||
IN u32 RegAddr,
|
|
||||||
IN u32 BitMask,
|
|
||||||
IN u32 Data );
|
|
||||||
u32 rtl8192d_PHY_QueryRFReg( IN struct adapter * Adapter,
|
|
||||||
IN RF_RADIO_PATH_E eRFPath,
|
|
||||||
IN u32 RegAddr,
|
|
||||||
IN u32 BitMask );
|
|
||||||
void rtl8192d_PHY_SetRFReg( IN struct adapter * Adapter,
|
|
||||||
IN RF_RADIO_PATH_E eRFPath,
|
|
||||||
IN u32 RegAddr,
|
|
||||||
IN u32 BitMask,
|
|
||||||
IN u32 Data );
|
|
||||||
|
|
||||||
/* */
|
|
||||||
/* Initialization related function */
|
|
||||||
/* */
|
|
||||||
/* MAC/BB/RF HAL config */
|
|
||||||
extern int PHY_MACConfig8192D( IN struct adapter *Adapter );
|
|
||||||
extern int PHY_BBConfig8192D( IN struct adapter *Adapter );
|
|
||||||
extern int PHY_RFConfig8192D( IN struct adapter *Adapter );
|
|
||||||
/* RF config */
|
|
||||||
int rtl8192d_PHY_ConfigRFWithParaFile( IN struct adapter *Adapter,
|
|
||||||
IN u8* pFileName,
|
|
||||||
IN RF_RADIO_PATH_E eRFPath);
|
|
||||||
int rtl8192d_PHY_ConfigRFWithHeaderFile( IN struct adapter * Adapter,
|
|
||||||
IN RF_CONTENT Content,
|
|
||||||
IN RF_RADIO_PATH_E eRFPath);
|
|
||||||
/* BB/RF readback check for making sure init OK */
|
|
||||||
int rtl8192d_PHY_CheckBBAndRFOK( IN struct adapter * Adapter,
|
|
||||||
IN HW90_BLOCK_E CheckBlock,
|
|
||||||
IN RF_RADIO_PATH_E eRFPath );
|
|
||||||
/* Read initi reg value for tx power setting. */
|
|
||||||
void rtl8192d_PHY_GetHWRegOriginalValue( IN struct adapter * Adapter );
|
|
||||||
|
|
||||||
/* */
|
|
||||||
/* RF Power setting */
|
|
||||||
/* */
|
|
||||||
/* extern bool PHY_SetRFPowerState(IN struct adapter * Adapter, */
|
|
||||||
/* IN RT_RF_POWER_STATE eRFPowerState); */
|
|
||||||
|
|
||||||
/* */
|
|
||||||
/* BB TX Power R/W */
|
|
||||||
/* */
|
|
||||||
void PHY_GetTxPowerLevel8192D( IN struct adapter * Adapter,
|
|
||||||
OUT u32* powerlevel );
|
|
||||||
void PHY_SetTxPowerLevel8192D( IN struct adapter * Adapter,
|
|
||||||
IN u8 channel );
|
|
||||||
bool PHY_UpdateTxPowerDbm8192D( IN struct adapter *Adapter,
|
|
||||||
IN int powerInDbm );
|
|
||||||
|
|
||||||
/* */
|
|
||||||
void
|
|
||||||
PHY_ScanOperationBackup8192D(IN struct adapter *Adapter,
|
|
||||||
IN u8 Operation );
|
|
||||||
|
|
||||||
/* */
|
|
||||||
/* Switch bandwidth for 8192S */
|
|
||||||
/* */
|
|
||||||
/* void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer ); */
|
|
||||||
void PHY_SetBWMode8192D( IN struct adapter * pAdapter,
|
|
||||||
IN HT_CHANNEL_WIDTH ChnlWidth,
|
|
||||||
IN unsigned char Offset );
|
|
||||||
|
|
||||||
/* */
|
|
||||||
/* Set FW CMD IO for 8192S. */
|
|
||||||
/* */
|
|
||||||
/* extern bool HalSetIO8192C( IN struct adapter * Adapter, */
|
|
||||||
/* IN IO_TYPE IOType); */
|
|
||||||
|
|
||||||
/* */
|
|
||||||
/* Set A2 entry to fw for 8192S */
|
|
||||||
/* */
|
|
||||||
extern void FillA2Entry8192C( IN struct adapter * Adapter,
|
|
||||||
IN u8 index,
|
|
||||||
IN u8* val);
|
|
||||||
|
|
||||||
|
|
||||||
/* */
|
|
||||||
/* channel switch related funciton */
|
|
||||||
/* */
|
|
||||||
/* extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer ); */
|
|
||||||
void PHY_SwChnl8192D( IN struct adapter * pAdapter,
|
|
||||||
IN u8 channel );
|
|
||||||
/* Call after initialization */
|
|
||||||
void PHY_SwChnlPhy8192D( IN struct adapter * pAdapter,
|
|
||||||
IN u8 channel );
|
|
||||||
|
|
||||||
extern void ChkFwCmdIoDone( IN struct adapter *Adapter);
|
|
||||||
|
|
||||||
|
|
||||||
/* */
|
|
||||||
/* BB/MAC/RF other monitor API */
|
|
||||||
/* */
|
|
||||||
void PHY_SetMonitorMode8192D(IN struct adapter *pAdapter,
|
|
||||||
IN bool bEnableMonitorMode );
|
|
||||||
|
|
||||||
bool PHY_CheckIsLegalRfPath8192D(IN struct adapter *pAdapter,
|
|
||||||
IN u32 eRFPath );
|
|
||||||
|
|
||||||
|
|
||||||
/* */
|
|
||||||
/* Modify the value of the hw register when beacon interval be changed. */
|
|
||||||
/* */
|
|
||||||
void
|
|
||||||
rtl8192d_PHY_SetBeaconHwReg( IN struct adapter * Adapter,
|
|
||||||
IN u16 BeaconInterval );
|
|
||||||
|
|
||||||
|
|
||||||
extern void
|
|
||||||
PHY_SwitchEphyParameter(
|
|
||||||
IN struct adapter * Adapter
|
|
||||||
);
|
|
||||||
|
|
||||||
extern void
|
|
||||||
PHY_EnableHostClkReq(
|
|
||||||
IN struct adapter * Adapter
|
|
||||||
);
|
|
||||||
|
|
||||||
bool
|
|
||||||
SetAntennaConfig92C(
|
|
||||||
IN struct adapter *Adapter,
|
|
||||||
IN u8 DefaultAnt
|
|
||||||
);
|
|
||||||
|
|
||||||
void
|
|
||||||
PHY_UpdateBBRFConfiguration8192D(
|
|
||||||
IN struct adapter *Adapter,
|
|
||||||
IN bool bisBandSwitch
|
|
||||||
);
|
|
||||||
|
|
||||||
void PHY_ReadMacPhyMode92D(
|
|
||||||
IN struct adapter *Adapter,
|
|
||||||
IN bool AutoloadFail
|
|
||||||
);
|
|
||||||
|
|
||||||
void PHY_ConfigMacPhyMode92D(
|
|
||||||
IN struct adapter *Adapter
|
|
||||||
);
|
|
||||||
|
|
||||||
void PHY_ConfigMacPhyModeInfo92D(
|
|
||||||
IN struct adapter *Adapter
|
|
||||||
);
|
|
||||||
|
|
||||||
void PHY_ConfigMacCoexist_RFPage92D(
|
|
||||||
IN struct adapter *Adapter
|
|
||||||
);
|
|
||||||
|
|
||||||
void
|
|
||||||
rtl8192d_PHY_InitRxSetting(
|
|
||||||
IN struct adapter *Adapter
|
|
||||||
);
|
|
||||||
|
|
||||||
|
|
||||||
void
|
|
||||||
rtl8192d_PHY_SetRFPathSwitch(IN struct adapter *pAdapter, IN bool bMain);
|
|
||||||
|
|
||||||
void
|
|
||||||
HalChangeCCKStatus8192D(
|
|
||||||
IN struct adapter *Adapter,
|
|
||||||
IN bool bCCKDisable
|
|
||||||
);
|
|
||||||
|
|
||||||
void
|
|
||||||
PHY_InitPABias92D(IN struct adapter *Adapter);
|
|
||||||
|
|
||||||
/*--------------------------Exported Function prototype---------------------*/
|
|
||||||
|
|
||||||
#define PHY_SetBBReg1Byte(Adapter, RegAddr, BitMask, Data) rtl8192d_PHY_SetBBReg1Byte((Adapter), (RegAddr), (BitMask), (Data))
|
|
||||||
#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtl8192d_PHY_QueryBBReg((Adapter), (RegAddr), (BitMask))
|
|
||||||
#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtl8192d_PHY_SetBBReg((Adapter), (RegAddr), (BitMask), (Data))
|
|
||||||
#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtl8192d_PHY_QueryRFReg((Adapter), (eRFPath), (RegAddr), (BitMask))
|
|
||||||
#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtl8192d_PHY_SetRFReg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
|
|
||||||
|
|
||||||
#define PHY_SetMacReg PHY_SetBBReg
|
|
||||||
#define PHY_QueryMacReg PHY_QueryBBReg
|
|
||||||
|
|
||||||
#endif /* __INC_HAL8192SPHYCFG_H */
|
|
||||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,29 +0,0 @@
|
||||||
/******************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify it
|
|
||||||
* under the terms of version 2 of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
|
||||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
||||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
||||||
* more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License along with
|
|
||||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
|
||||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
|
||||||
*
|
|
||||||
*
|
|
||||||
******************************************************************************/
|
|
||||||
#ifndef __INC_HAL8723PHYCFG_H__
|
|
||||||
#define __INC_HAL8723PHYCFG_H__
|
|
||||||
|
|
||||||
#include <Hal8192CPhyCfg.h>
|
|
||||||
/* MAC/BB/RF HAL config */
|
|
||||||
int PHY_BBConfig8723A( IN struct adapter *Adapter );
|
|
||||||
int PHY_RFConfig8723A( IN struct adapter *Adapter );
|
|
||||||
s32 PHY_MACConfig8723A(struct adapter *padapter);
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,73 +0,0 @@
|
||||||
/******************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify it
|
|
||||||
* under the terms of version 2 of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
|
||||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
||||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
||||||
* more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License along with
|
|
||||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
|
||||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
|
||||||
*
|
|
||||||
*
|
|
||||||
******************************************************************************/
|
|
||||||
#ifndef __INC_HAL8723APHYREG_H__
|
|
||||||
#define __INC_HAL8723APHYREG_H__
|
|
||||||
|
|
||||||
#include <Hal8192CPhyReg.h>
|
|
||||||
|
|
||||||
/* */
|
|
||||||
/* PageB(0xB00) */
|
|
||||||
/* */
|
|
||||||
#define rPdp_AntA 0xb00
|
|
||||||
#define rPdp_AntA_4 0xb04
|
|
||||||
#define rPdp_AntA_8 0xb08
|
|
||||||
#define rPdp_AntA_C 0xb0c
|
|
||||||
#define rPdp_AntA_10 0xb10
|
|
||||||
#define rPdp_AntA_14 0xb14
|
|
||||||
#define rPdp_AntA_18 0xb18
|
|
||||||
#define rPdp_AntA_1C 0xb1c
|
|
||||||
#define rPdp_AntA_20 0xb20
|
|
||||||
#define rPdp_AntA_24 0xb24
|
|
||||||
|
|
||||||
#define rConfig_Pmpd_AntA 0xb28
|
|
||||||
#define rConfig_ram64x16 0xb2c
|
|
||||||
|
|
||||||
#define rBndA 0xb30
|
|
||||||
#define rHssiPar 0xb34
|
|
||||||
|
|
||||||
#define rConfig_AntA 0xb68
|
|
||||||
#define rConfig_AntB 0xb6c
|
|
||||||
|
|
||||||
#define rPdp_AntB 0xb70
|
|
||||||
#define rPdp_AntB_4 0xb74
|
|
||||||
#define rPdp_AntB_8 0xb78
|
|
||||||
#define rPdp_AntB_C 0xb7c
|
|
||||||
#define rPdp_AntB_10 0xb80
|
|
||||||
#define rPdp_AntB_14 0xb84
|
|
||||||
#define rPdp_AntB_18 0xb88
|
|
||||||
#define rPdp_AntB_1C 0xb8c
|
|
||||||
#define rPdp_AntB_20 0xb90
|
|
||||||
#define rPdp_AntB_24 0xb94
|
|
||||||
|
|
||||||
#define rConfig_Pmpd_AntB 0xb98
|
|
||||||
|
|
||||||
#define rBndB 0xba0
|
|
||||||
|
|
||||||
#define rAPK 0xbd8
|
|
||||||
#define rPm_Rx0_AntA 0xbdc
|
|
||||||
#define rPm_Rx1_AntA 0xbe0
|
|
||||||
#define rPm_Rx2_AntA 0xbe4
|
|
||||||
#define rPm_Rx3_AntA 0xbe8
|
|
||||||
#define rPm_Rx0_AntB 0xbec
|
|
||||||
#define rPm_Rx1_AntB 0xbf0
|
|
||||||
#define rPm_Rx2_AntB 0xbf4
|
|
||||||
#define rPm_Rx3_AntB 0xbf8
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,170 +0,0 @@
|
||||||
#ifndef __HAL8723PWRSEQ_H__
|
|
||||||
#define __HAL8723PWRSEQ_H__
|
|
||||||
/*
|
|
||||||
Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
|
|
||||||
There are 6 HW Power States:
|
|
||||||
0: POFF--Power Off
|
|
||||||
1: PDN--Power Down
|
|
||||||
2: CARDEMU--Card Emulation
|
|
||||||
3: ACT--Active Mode
|
|
||||||
4: LPS--Low Power State
|
|
||||||
5: SUS--Suspend
|
|
||||||
|
|
||||||
The transision from different states are defined below
|
|
||||||
TRANS_CARDEMU_TO_ACT
|
|
||||||
TRANS_ACT_TO_CARDEMU
|
|
||||||
TRANS_CARDEMU_TO_SUS
|
|
||||||
TRANS_SUS_TO_CARDEMU
|
|
||||||
TRANS_CARDEMU_TO_PDN
|
|
||||||
TRANS_ACT_TO_LPS
|
|
||||||
TRANS_LPS_TO_ACT
|
|
||||||
|
|
||||||
TRANS_END
|
|
||||||
*/
|
|
||||||
#include "HalPwrSeqCmd.h"
|
|
||||||
#include "rtl8723a_spec.h"
|
|
||||||
|
|
||||||
#define RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS 15
|
|
||||||
#define RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS 15
|
|
||||||
#define RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS 15
|
|
||||||
#define RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS 15
|
|
||||||
#define RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS 15
|
|
||||||
#define RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS 15
|
|
||||||
#define RTL8723A_TRANS_ACT_TO_LPS_STEPS 15
|
|
||||||
#define RTL8723A_TRANS_LPS_TO_ACT_STEPS 15
|
|
||||||
#define RTL8723A_TRANS_END_STEPS 1
|
|
||||||
|
|
||||||
|
|
||||||
#define RTL8723A_TRANS_CARDEMU_TO_ACT \
|
|
||||||
/* format */ \
|
|
||||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
|
||||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
|
|
||||||
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
|
|
||||||
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
|
|
||||||
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
|
|
||||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
|
|
||||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
|
|
||||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
|
|
||||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
|
|
||||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \
|
|
||||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
|
|
||||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \
|
|
||||||
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 1},/*0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */\
|
|
||||||
|
|
||||||
#define RTL8723A_TRANS_ACT_TO_CARDEMU \
|
|
||||||
/* format */ \
|
|
||||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
|
||||||
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
|
|
||||||
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
|
|
||||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
|
|
||||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
|
|
||||||
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
|
|
||||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \
|
|
||||||
|
|
||||||
|
|
||||||
#define RTL8723A_TRANS_CARDEMU_TO_SUS \
|
|
||||||
/* format */ \
|
|
||||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
|
||||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
|
||||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
|
||||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
|
||||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
|
|
||||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
|
||||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
|
||||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
|
||||||
|
|
||||||
#define RTL8723A_TRANS_SUS_TO_CARDEMU \
|
|
||||||
/* format */ \
|
|
||||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
|
||||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
|
|
||||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
|
||||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
|
||||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
|
|
||||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
|
|
||||||
|
|
||||||
#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS \
|
|
||||||
/* format */ \
|
|
||||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
|
||||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \
|
|
||||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
|
||||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
|
|
||||||
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
|
|
||||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
|
||||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
|
||||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
|
||||||
|
|
||||||
#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU \
|
|
||||||
/* format */ \
|
|
||||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
|
||||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
|
|
||||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
|
||||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
|
||||||
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
|
|
||||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
|
|
||||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
|
|
||||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
|
|
||||||
|
|
||||||
|
|
||||||
#define RTL8723A_TRANS_CARDEMU_TO_PDN \
|
|
||||||
/* format */ \
|
|
||||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
|
||||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
|
||||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
|
|
||||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
|
|
||||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
|
|
||||||
|
|
||||||
#define RTL8723A_TRANS_PDN_TO_CARDEMU \
|
|
||||||
/* format */ \
|
|
||||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
|
||||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
|
|
||||||
|
|
||||||
#define RTL8723A_TRANS_ACT_TO_LPS \
|
|
||||||
/* format */ \
|
|
||||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
|
||||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
|
|
||||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
|
|
||||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
|
||||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
|
||||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
|
||||||
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
|
||||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
|
|
||||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
|
||||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
|
|
||||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
|
|
||||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
|
|
||||||
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
|
|
||||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
|
|
||||||
|
|
||||||
|
|
||||||
#define RTL8723A_TRANS_LPS_TO_ACT \
|
|
||||||
/* format */ \
|
|
||||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
|
||||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
|
|
||||||
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
|
|
||||||
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
|
|
||||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
|
|
||||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
|
|
||||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
|
|
||||||
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
|
|
||||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
|
|
||||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
|
|
||||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
|
|
||||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
|
||||||
|
|
||||||
#define RTL8723A_TRANS_END \
|
|
||||||
/* format */ \
|
|
||||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
|
||||||
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0},
|
|
||||||
|
|
||||||
|
|
||||||
extern struct wl_pwr_cfg rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS];
|
|
||||||
extern struct wl_pwr_cfg rtl8723A_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_END_STEPS];
|
|
||||||
extern struct wl_pwr_cfg rtl8723A_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
|
|
||||||
extern struct wl_pwr_cfg rtl8723A_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
|
|
||||||
extern struct wl_pwr_cfg rtl8723A_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS];
|
|
||||||
extern struct wl_pwr_cfg rtl8723A_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS];
|
|
||||||
extern struct wl_pwr_cfg rtl8723A_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
|
|
||||||
extern struct wl_pwr_cfg rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STEPS+RTL8723A_TRANS_END_STEPS];
|
|
||||||
extern struct wl_pwr_cfg rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS];
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -31,8 +31,6 @@
|
||||||
#include <osdep_service.h>
|
#include <osdep_service.h>
|
||||||
#include <wlan_bssdef.h>
|
#include <wlan_bssdef.h>
|
||||||
|
|
||||||
#include <drv_types_linux.h>
|
|
||||||
|
|
||||||
enum _NIC_VERSION {
|
enum _NIC_VERSION {
|
||||||
|
|
||||||
RTL8711_NIC,
|
RTL8711_NIC,
|
||||||
|
|
|
||||||
|
|
@ -1,24 +0,0 @@
|
||||||
/******************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify it
|
|
||||||
* under the terms of version 2 of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
|
||||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
||||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
||||||
* more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License along with
|
|
||||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
|
||||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
|
||||||
*
|
|
||||||
*
|
|
||||||
******************************************************************************/
|
|
||||||
#ifndef __DRV_TYPES_LINUX_H__
|
|
||||||
#define __DRV_TYPES_LINUX_H__
|
|
||||||
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,42 +0,0 @@
|
||||||
/******************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify it
|
|
||||||
* under the terms of version 2 of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
|
||||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
||||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
||||||
* more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License along with
|
|
||||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
|
||||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
|
||||||
*
|
|
||||||
*
|
|
||||||
******************************************************************************/
|
|
||||||
#ifndef __PCI_OPS_H_
|
|
||||||
#define __PCI_OPS_H_
|
|
||||||
|
|
||||||
#include <drv_conf.h>
|
|
||||||
#include <osdep_service.h>
|
|
||||||
#include <drv_types.h>
|
|
||||||
#include <osdep_intf.h>
|
|
||||||
|
|
||||||
|
|
||||||
u32 rtl8188ee_init_desc_ring(struct adapter * padapter);
|
|
||||||
u32 rtl8188ee_free_desc_ring(struct adapter * padapter);
|
|
||||||
void rtl8188ee_reset_desc_ring(struct adapter * padapter);
|
|
||||||
#ifdef CONFIG_64BIT_DMA
|
|
||||||
u8 PlatformEnable88EEDMA64(struct adapter *Adapter);
|
|
||||||
#endif
|
|
||||||
int rtl8188ee_interrupt(struct adapter *Adapter);
|
|
||||||
void rtl8188ee_xmit_tasklet(void *priv);
|
|
||||||
void rtl8188ee_recv_tasklet(void *priv);
|
|
||||||
void rtl8188ee_prepare_bcn_tasklet(void *priv);
|
|
||||||
void rtl8188ee_set_intf_ops(struct _io_ops *pops);
|
|
||||||
#define pci_set_intf_ops rtl8188ee_set_intf_ops
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,32 +0,0 @@
|
||||||
/******************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify it
|
|
||||||
* under the terms of version 2 of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
|
||||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
||||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
||||||
* more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License along with
|
|
||||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
|
||||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
|
||||||
*
|
|
||||||
*
|
|
||||||
******************************************************************************/
|
|
||||||
#ifndef __PCI_OSINTF_H
|
|
||||||
#define __PCI_OSINTF_H
|
|
||||||
|
|
||||||
#include <drv_conf.h>
|
|
||||||
#include <osdep_service.h>
|
|
||||||
#include <drv_types.h>
|
|
||||||
|
|
||||||
|
|
||||||
void rtw_pci_disable_aspm(struct adapter *padapter);
|
|
||||||
void rtw_pci_enable_aspm(struct adapter *padapter);
|
|
||||||
|
|
||||||
|
|
||||||
#endif
|
|
||||||
Loading…
Reference in a new issue