skyfall/rtl8188eu
1
0
Fork 0
mirror of https://github.com/lwfinger/rtl8188eu.git synced 2025-05-08 14:33:05 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

rtl8188eu: Change "){" to ") {"

Browse source 
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2015-08-15 13:24:16 -05:00
parent c137ff21e5
commit 0a97479cee
46 changed files with 464 additions and 464 deletions
Download patch file Download diff file Expand all files Collapse all files

32
hal/Hal8188ERateAdaptive.c
View file

@ -182,11 +182,11 @@ odm_RateDown_8188E(
RateID = LowestRate;
}
RateDownFinish:
if (pRaInfo->RAWaitingCounter==1){
if (pRaInfo->RAWaitingCounter==1) {
pRaInfo->RAWaitingCounter+=1;
pRaInfo->RAPendingCounter+=1;
}
else if (pRaInfo->RAWaitingCounter== 0){
else if (pRaInfo->RAWaitingCounter== 0) {
}
else{
pRaInfo->RAWaitingCounter=0;
@ -225,11 +225,11 @@ odm_RateUp_8188E(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,
(" RateID=%d HighestRate=%d\n",
RateID, HighestRate));
if (pRaInfo->RAWaitingCounter==1){
if (pRaInfo->RAWaitingCounter==1) {
pRaInfo->RAWaitingCounter=0;
pRaInfo->RAPendingCounter=0;
}
else if (pRaInfo->RAWaitingCounter>1){
else if (pRaInfo->RAWaitingCounter>1) {
pRaInfo->PreRssiStaRA=pRaInfo->RssiStaRA;
goto RateUpfinish;
}
@ -273,7 +273,7 @@ RateUpfinish:
return 0;
}
static void odm_ResetRaCounter_8188E(PODM_RA_INFO_T pRaInfo){
static void odm_ResetRaCounter_8188E(PODM_RA_INFO_T pRaInfo) {
u8 RateID;
RateID=pRaInfo->DecisionRate;
pRaInfo->NscUp=(N_THRESHOLD_HIGH[RateID]+N_THRESHOLD_LOW[RateID])>>1;
@ -294,7 +294,7 @@ odm_RateDecision_8188E(
if (pRaInfo->Active && (pRaInfo->TOTAL > 0)) /* STA used and data packet exits */
{
if ( (pRaInfo->RssiStaRA<(pRaInfo->PreRssiStaRA-3))|| (pRaInfo->RssiStaRA>(pRaInfo->PreRssiStaRA+3))){
if ( (pRaInfo->RssiStaRA<(pRaInfo->PreRssiStaRA-3))|| (pRaInfo->RssiStaRA>(pRaInfo->PreRssiStaRA+3))) {
pRaInfo->RAWaitingCounter=0;
pRaInfo->RAPendingCounter=0;
}
@ -381,7 +381,7 @@ odm_ARFBRefresh_8188E(
u32 MaskFromReg;
s8 i;
switch (pRaInfo->RateID){
switch (pRaInfo->RateID) {
case RATR_INX_WIRELESS_NGB:
pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff015;
break;
@ -425,10 +425,10 @@ odm_ARFBRefresh_8188E(
break;
}
/* Highest rate */
if (pRaInfo->RAUseRate){
if (pRaInfo->RAUseRate) {
for (i=RATESIZE;i>=0;i--)
{
if ((pRaInfo->RAUseRate)&BIT(i)){
if ((pRaInfo->RAUseRate)&BIT(i)) {
pRaInfo->HighestRate=i;
break;
}
@ -438,7 +438,7 @@ odm_ARFBRefresh_8188E(
pRaInfo->HighestRate=0;
}
/* Lowest rate */
if (pRaInfo->RAUseRate){
if (pRaInfo->RAUseRate) {
for (i=0;i<RATESIZE;i++)
{
if ((pRaInfo->RAUseRate)&BIT(i))
@ -588,7 +588,7 @@ odm_RATxRPTTimerSetting(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,(" =====>odm_RATxRPTTimerSetting()\n"));
if (pDM_Odm->CurrminRptTime != minRptTime){
if (pDM_Odm->CurrminRptTime != minRptTime) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD,
(" CurrminRptTime =0x%04x minRptTime=0x%04x\n", pDM_Odm->CurrminRptTime, minRptTime));
rtw_rpt_timer_cfg_cmd(pDM_Odm->Adapter,minRptTime);
@ -622,11 +622,11 @@ ODM_RAInfo_Init(
PODM_RA_INFO_T pRaInfo = &pDM_Odm->RAInfo[MacID];
u8 WirelessMode=0xFF; /* invalid value */
u8 max_rate_idx = 0x13; /* MCS7 */
if (pDM_Odm->pWirelessMode!=NULL){
if (pDM_Odm->pWirelessMode!=NULL) {
WirelessMode=*(pDM_Odm->pWirelessMode);
}
if (WirelessMode != 0xFF ){
if (WirelessMode != 0xFF ) {
if (WirelessMode & ODM_WM_N24G)
max_rate_idx = 0x13;
else if (WirelessMode & ODM_WM_G)
@ -854,11 +854,11 @@ ODM_RA_TxRPT2Handle_8188E(
MacIDValidEntry0 ,
MacIDValidEntry1));
#if POWER_TRAINING_ACTIVE == 1
if (pRAInfo->PTActive){
if (pRAInfo->RAstage<5){
if (pRAInfo->PTActive) {
if (pRAInfo->RAstage<5) {
odm_RateDecision_8188E(pDM_Odm,pRAInfo);
}
else if (pRAInfo->RAstage==5){ /* Power training try state */
else if (pRAInfo->RAstage==5) { /* Power training try state */
odm_PTTryState_8188E(pRAInfo);
}
else {/* RAstage==6 */

40
hal/HalPhyRf_8188e.c
View file

@ -263,7 +263,7 @@ odm_TxPwrTrackSetPwr88E(
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr88E CH=%d\n", *(pDM_Odm->pChannel)));
/* if (MP_DRIVER != 1) */
if ( *(pDM_Odm->mp_mode) != 1){
if ( *(pDM_Odm->mp_mode) != 1) {
PHY_SetTxPowerLevel8188E(pDM_Odm->Adapter, *pDM_Odm->pChannel);
}
else
@ -539,7 +539,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
}
/* if ((delta_IQK > pHalData->Delta_IQK) && (pHalData->Delta_IQK != 0)) */
if ((delta_IQK >= 8)){ /* Delta temperature is equal to or larger than 20 centigrade. */
if ((delta_IQK >= 8)) { /* Delta temperature is equal to or larger than 20 centigrade. */
/* printk("delta_IQK(%d) >=8 do_IQK\n",delta_IQK); */
doIQK(pDM_Odm, delta_IQK, ThermalValue, 8);
}
@ -942,7 +942,7 @@ _PHY_SaveADDARegisters(
if (ODM_CheckPowerStatus(pAdapter) == false)
return;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n"));
for ( i = 0 ; i < RegisterNum ; i++){
for ( i = 0 ; i < RegisterNum ; i++) {
ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord);
}
}
@ -960,7 +960,7 @@ _PHY_SaveMACRegisters(
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n"));
for ( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){
for ( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) {
MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]);
}
MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]);
@ -999,7 +999,7 @@ _PHY_ReloadMACRegisters(
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n"));
for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){
for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) {
ODM_Write1Byte(pDM_Odm, MACReg[i], (u8)MACBackup[i]);
}
ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]);
@ -1022,7 +1022,7 @@ _PHY_PathADDAOn(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n"));
pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4;
if (false == is2T){
if (false == is2T) {
pathOn = 0x0bdb25a0;
ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0b1b25a0);
}
@ -1030,7 +1030,7 @@ _PHY_PathADDAOn(
ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn);
}
for ( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){
for ( i = 1 ; i < IQK_ADDA_REG_NUM ; i++) {
ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn);
}
@ -1051,7 +1051,7 @@ _PHY_MACSettingCalibration(
ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F);
for (i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){
for (i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++) {
ODM_Write1Byte(pDM_Odm, MACReg[i], (u8)(MACBackup[i]&(~BIT3)));
}
ODM_Write1Byte(pDM_Odm, MACReg[i], (u8)(MACBackup[i]&(~BIT5)));
@ -1272,7 +1272,7 @@ else
pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u8)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8));
}
if (!pDM_Odm->RFCalibrateInfo.bRfPiEnable){
if (!pDM_Odm->RFCalibrateInfo.bRfPiEnable) {
/* Switch BB to PI mode to do IQ Calibration. */
_PHY_PIModeSwitch(pAdapter, true);
}
@ -1314,9 +1314,9 @@ else
ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800);
for (i = 0 ; i < retryCount ; i++){
for (i = 0 ; i < retryCount ; i++) {
PathAOK = phy_PathA_IQK_8188E(pAdapter, is2T);
if (PathAOK == 0x01){
if (PathAOK == 0x01) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n"));
result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
@ -1324,9 +1324,9 @@ else
}
}
for (i = 0 ; i < retryCount ; i++){
for (i = 0 ; i < retryCount ; i++) {
PathAOK = phy_PathA_RxIQK(pAdapter, is2T);
if (PathAOK == 0x03){
if (PathAOK == 0x03) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n"));
result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
@ -1336,19 +1336,19 @@ else
}
}
if (0x00 == PathAOK){
if (0x00 == PathAOK) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n"));
}
if (is2T){
if (is2T) {
_PHY_PathAStandBy(pAdapter);
/* Turn Path B ADDA on */
_PHY_PathADDAOn(pAdapter, ADDA_REG, false, is2T);
for (i = 0 ; i < retryCount ; i++){
for (i = 0 ; i < retryCount ; i++) {
PathBOK = phy_PathB_IQK_8188E(pAdapter);
if (PathBOK == 0x03){
if (PathBOK == 0x03) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK Success!!\n"));
result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16;
result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16;
@ -1364,7 +1364,7 @@ else
}
}
if (0x00 == PathBOK){
if (0x00 == PathBOK) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n"));
}
}
@ -1374,7 +1374,7 @@ else
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0);
if (t!=0) {
if (!pDM_Odm->RFCalibrateInfo.bRfPiEnable){
if (!pDM_Odm->RFCalibrateInfo.bRfPiEnable) {
/* Switch back BB to SI mode after finish IQ Calibration. */
_PHY_PIModeSwitch(pAdapter, false);
}
@ -1390,7 +1390,7 @@ else
/* Restore RX initial gain */
ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3);
if (is2T){
if (is2T) {
ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3);
}

12
hal/hal_com.c
View file

@ -33,16 +33,16 @@ void dump_chip_info(struct hal_version ChipVersion)
int cnt = 0;
u8 buf[128];
if (IS_81XXC(ChipVersion)){
if (IS_81XXC(ChipVersion)) {
cnt += sprintf((buf+cnt), "Chip Version Info: %s_", IS_92C_SERIAL(ChipVersion)?"CHIP_8192C":"CHIP_8188C");
}
else if (IS_92D(ChipVersion)){
else if (IS_92D(ChipVersion)) {
cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8192D_");
}
else if (IS_8723_SERIES(ChipVersion)){
else if (IS_8723_SERIES(ChipVersion)) {
cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8723A_");
}
else if (IS_8188E(ChipVersion)){
else if (IS_8188E(ChipVersion)) {
cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8188E_");
}
@ -198,7 +198,7 @@ _TwoOutPipeMapping(
{
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
if (bWIFICfg){ /* WMM */
if (bWIFICfg) { /* WMM */
/* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */
/* 0, 1, 0, 1, 0, 0, 0, 0, 0 }; */
@ -243,7 +243,7 @@ static void _ThreeOutPipeMapping(
{
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
if (bWIFICfg){/* for WMM */
if (bWIFICfg) {/* for WMM */
/* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */
/* 1, 2, 1, 0, 0, 0, 0, 0, 0 }; */

10
hal/hal_intf.c
View file

@ -105,7 +105,7 @@ uint rtw_hal_init(struct adapter *padapter)
status = padapter->HalFunc.hal_init(padapter);
if (status == _SUCCESS){
if (status == _SUCCESS) {
for (i = 0; i<dvobj->iface_nums; i++) {
padapter = dvobj->padapters[i];
padapter->hw_init_completed = true;
@ -140,14 +140,14 @@ uint rtw_hal_deinit(struct adapter *padapter)
int i;
;
if (!is_primary_adapter(padapter)){
if (!is_primary_adapter(padapter)) {
DBG_871X(" rtw_hal_deinit: Secondary adapter return l\n");
return status;
}
status = padapter->HalFunc.hal_deinit(padapter);
if (status == _SUCCESS){
if (status == _SUCCESS) {
for (i = 0; i<dvobj->iface_nums; i++) {
padapter = dvobj->padapters[i];
padapter->hw_init_completed = false;
@ -200,7 +200,7 @@ void rtw_hal_get_odm_var(struct adapter *padapter, enum HAL_ODM_VARIABLE eVariab
void rtw_hal_enable_interrupt(struct adapter *padapter)
{
if (!is_primary_adapter(padapter)){
if (!is_primary_adapter(padapter)) {
DBG_871X(" rtw_hal_enable_interrupt: Secondary adapter return l\n");
return;
}
@ -214,7 +214,7 @@ void rtw_hal_enable_interrupt(struct adapter *padapter)
void rtw_hal_disable_interrupt(struct adapter *padapter)
{
if (!is_primary_adapter(padapter)){
if (!is_primary_adapter(padapter)) {
DBG_871X(" rtw_hal_disable_interrupt: Secondary adapter return l\n");
return;
}

24
hal/odm.c
View file

@ -1579,7 +1579,7 @@ odm_DIG(
}
else
{
if ((pDM_Odm->SupportICType & (ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8812|ODM_RTL8821)) && (pDM_Odm->bBtLimitedDig==1)){
if ((pDM_Odm->SupportICType & (ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8812|ODM_RTL8821)) && (pDM_Odm->bBtLimitedDig==1)) {
/* 2 Modify DIG upper bound for 92E, 8723B, 8821 & 8812 BT */
if ((pDM_Odm->RSSI_Min + 10) > dm_dig_max )
pDM_DigTable->rx_gain_range_max = dm_dig_max;
@ -2141,7 +2141,7 @@ ODM_RF_Saving(
Rssi_Up_bound = 50 ;
Rssi_Low_bound = 45;
}
if (pDM_PSTable->initialize == 0){
if (pDM_PSTable->initialize == 0) {
pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14;
pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3;
@ -2412,7 +2412,7 @@ odm_RefreshRateAdaptiveMaskCE(
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n"));
return;
}
for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++){
for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++) {
PSTA_INFO_T pstat = pDM_Odm->pODM_StaInfo[i];
if (IS_STA_VALID(pstat) ) {
if (IS_MCAST( pstat->hwaddr)) /* if (psta->mac_id ==1) */
@ -2780,7 +2780,7 @@ odm_RSSIMonitorCheckCE(
for (i=0; i< sta_cnt; i++)
{
if (PWDB_rssi[i] != (0)){
if (PWDB_rssi[i] != (0)) {
if (pHalData->fw_ractrl == true)/* Report every sta's RSSI to FW */
{
}
@ -2998,9 +2998,9 @@ void odm_SwAntDivChkAntSwitch(
PDM_ODM_T pDM_Odm,
u8 Step
) {}
static void ODM_SwAntDivResetBeforeLink( PDM_ODM_T pDM_Odm ){}
void ODM_SwAntDivRestAfterLink( PDM_ODM_T pDM_Odm ){}
void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext){}
static void ODM_SwAntDivResetBeforeLink( PDM_ODM_T pDM_Odm ) {}
void ODM_SwAntDivRestAfterLink( PDM_ODM_T pDM_Odm ) {}
void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext) {}
/* 3============================================================ */
/* 3 SW Antenna Diversity */
@ -3029,7 +3029,7 @@ odm_InitHybridAntDiv_88C_92D(
ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_CTRL_11N, BIT8|BIT9, 0x01); /* 0x01: left antenna, 0x02: right antenna */
/* only AP support different path selection temperarly */
if (!bTxPathSel){ /* PATH-A */
if (!bTxPathSel) { /* PATH-A */
ODM_SetBBReg(pDM_Odm,ODM_REG_PIN_CTRL_11N, BIT8|BIT9, 0 ); /* ANTSEL as HW control */
ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PATH_11N, BIT13, 1); /* select TX ANTESEL from path A */
}
@ -3111,7 +3111,7 @@ odm_StaDefAntSel(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("CCK_Ant1_Cnt:%d, CCK_Ant2_Cnt:%d\n",CCK_Ant1_Cnt,CCK_Ant2_Cnt));
if (((OFDM_Ant1_Cnt+OFDM_Ant2_Cnt)== 0)&&((CCK_Ant1_Cnt + CCK_Ant2_Cnt) <10)){
if (((OFDM_Ant1_Cnt+OFDM_Ant2_Cnt)== 0)&&((CCK_Ant1_Cnt + CCK_Ant2_Cnt) <10)) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_StaDefAntSelect Fail: No enough packet info!\n"));
return false;
}
@ -3161,7 +3161,7 @@ odm_SetRxIdleAnt(
ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF, 0x569a); /* left-side antenna */
/* for path-B */
if (bDualPath){
if (bDualPath) {
if (Ant== 0)
ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF0000, 0x65a9); /* right-side antenna */
else
@ -3270,7 +3270,7 @@ odm_HwAntDiv_92C_92D(
&pDM_SWAT_Table->TxAnt[i]);
/* if Tx antenna selection: successful */
if (bRet){
if (bRet) {
pDM_SWAT_Table->RSSI_Ant1_Sum[i] = 0;
pDM_SWAT_Table->RSSI_Ant2_Sum[i] = 0;
pDM_SWAT_Table->OFDM_Ant1_Cnt[i] = 0;
@ -3566,7 +3566,7 @@ odm_PHY_SaveAFERegisters(
u32 i;
/* RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n")); */
for ( i = 0 ; i < RegisterNum ; i++){
for ( i = 0 ; i < RegisterNum ; i++) {
AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord);
}
}

10
hal/odm_HWConfig.c
View file

@ -377,7 +377,7 @@ odm_RxPhyStatus92CSeries_Parsing(
/* Modification for ext-LNA board */
if (pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA))
{
if ((cck_agc_rpt>>7) == 0){
if ((cck_agc_rpt>>7) == 0) {
PWDB_ALL = (PWDB_ALL>94)?100:(PWDB_ALL +6);
}
else
@ -413,10 +413,10 @@ odm_RxPhyStatus92CSeries_Parsing(
{
u8 SQ,SQ_rpt;
if ((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)){/* pMgntInfo->CustomerID == RT_CID_819x_Lenovo */
if ((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)) {/* pMgntInfo->CustomerID == RT_CID_819x_Lenovo */
SQ = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm,isCCKrate,PWDB_ALL,0,0);
}
else if (pPhyInfo->RxPWDBAll > 40 && !pDM_Odm->bInHctTest){
else if (pPhyInfo->RxPWDBAll > 40 && !pDM_Odm->bInHctTest) {
SQ = 100;
}
else{
@ -502,7 +502,7 @@ odm_RxPhyStatus92CSeries_Parsing(
pPhyInfo->RxPower = rx_pwr_all;
pPhyInfo->RecvSignalPower = rx_pwr_all;
if ((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)){
if ((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)) {
/* do nothing */
} else{/* pMgntInfo->CustomerID != RT_CID_819x_Lenovo */
/* */
@ -636,7 +636,7 @@ odm_Process_RSSIForDM(
if (!isCCKrate)/* ofdm rate */
{
if (pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B] == 0){
if (pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B] == 0) {
RSSI_Ave = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A];
pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A];
pDM_Odm->RSSI_B = 0;

24
hal/odm_RegConfig8188E.c
View file

@ -127,17 +127,17 @@ odm_ConfigBB_PHY_REG_PG_8188E(
u32 Data
)
{
if (Addr == 0xfe){
if (Addr == 0xfe) {
ODM_sleep_ms(50);
} else if (Addr == 0xfd){
} else if (Addr == 0xfd) {
ODM_delay_ms(5);
} else if (Addr == 0xfc){
} else if (Addr == 0xfc) {
ODM_delay_ms(1);
} else if (Addr == 0xfb){
} else if (Addr == 0xfb) {
ODM_delay_us(50);
} else if (Addr == 0xfa){
} else if (Addr == 0xfa) {
ODM_delay_us(5);
} else if (Addr == 0xf9){
} else if (Addr == 0xf9) {
ODM_delay_us(1);
} else{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> @@@@@@@ ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data));
@ -155,22 +155,22 @@ odm_ConfigBB_PHY_8188E(
u32 Data
)
{
if (Addr == 0xfe){
if (Addr == 0xfe) {
ODM_sleep_ms(50);
}
else if (Addr == 0xfd){
else if (Addr == 0xfd) {
ODM_delay_ms(5);
}
else if (Addr == 0xfc){
else if (Addr == 0xfc) {
ODM_delay_ms(1);
}
else if (Addr == 0xfb){
else if (Addr == 0xfb) {
ODM_delay_us(50);
}
else if (Addr == 0xfa){
else if (Addr == 0xfa) {
ODM_delay_us(5);
}
else if (Addr == 0xf9){
else if (Addr == 0xf9) {
ODM_delay_us(1);
}
else{

14
hal/rtl8188e_cmd.c
View file

@ -50,7 +50,7 @@ static u8 _is_fw_read_cmd_down(struct adapter* padapter, u8 msgbox_num)
do{
valid = rtw_read8(padapter,REG_HMETFR) & BIT(msgbox_num);
if (0 == valid ){
if (0 == valid ) {
read_down = true;
}
}while ( (!read_down) && (retry_cnts--));
@ -109,7 +109,7 @@ static s32 FillH2CCmd_88E(struct adapter *padapter, u8 ElementID, u32 CmdLen, u8
do{
h2c_box_num = pHalData->LastHMEBoxNum;
if (!_is_fw_read_cmd_down(padapter, h2c_box_num)){
if (!_is_fw_read_cmd_down(padapter, h2c_box_num)) {
DBG_8192C(" fw read cmd failed...\n");
goto exit;
}
@ -128,7 +128,7 @@ static s32 FillH2CCmd_88E(struct adapter *padapter, u8 ElementID, u32 CmdLen, u8
/* Write Ext command */
msgbox_ex_addr = REG_HMEBOX_EXT_0 + (h2c_box_num *RTL88E_EX_MESSAGE_BOX_SIZE);
#ifdef CONFIG_H2C_EF
for (cmd_idx=0;cmd_idx<ext_cmd_len;cmd_idx++ ){
for (cmd_idx=0;cmd_idx<ext_cmd_len;cmd_idx++ ) {
rtw_write8(padapter,msgbox_ex_addr+cmd_idx,*((u8*)(&h2c_cmd_ex)+cmd_idx));
}
#else
@ -139,7 +139,7 @@ static s32 FillH2CCmd_88E(struct adapter *padapter, u8 ElementID, u32 CmdLen, u8
/* Write command */
msgbox_addr =REG_HMEBOX_0 + (h2c_box_num *RTL88E_MESSAGE_BOX_SIZE);
#ifdef CONFIG_H2C_EF
for (cmd_idx=0;cmd_idx<RTL88E_MESSAGE_BOX_SIZE;cmd_idx++ ){
for (cmd_idx=0;cmd_idx<RTL88E_MESSAGE_BOX_SIZE;cmd_idx++ ) {
rtw_write8(padapter,msgbox_addr+cmd_idx,*((u8*)(&h2c_cmd)+cmd_idx));
}
#else
@ -169,7 +169,7 @@ u8 rtl8188e_set_rssi_cmd(struct adapter*padapter, u8 *param)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
;
if (pHalData->fw_ractrl == true){
if (pHalData->fw_ractrl == true) {
}else{
DBG_8192C("==>%s fw dont support RA\n",__FUNCTION__);
res=_FAIL;
@ -183,7 +183,7 @@ u8 rtl8188e_set_raid_cmd(struct adapter*padapter, u32 mask)
u8 res=_SUCCESS;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
;
if (pHalData->fw_ractrl == true){
if (pHalData->fw_ractrl == true) {
__le32 lmask;
memset(buf, 0, 3);
@ -312,7 +312,7 @@ void rtl8188e_set_FwMediaStatus_cmd(struct adapter *padapter, __le16 mstatus_rpt
DBG_871X("### %s: MStatus=%x MACID=%d\n", __FUNCTION__,opmode,macid);
FillH2CCmd_88E(padapter, H2C_COM_MEDIA_STATUS_RPT, sizeof(mst_rpt), (u8 *)&mst_rpt);
if (macid > 31){
if (macid > 31) {
macid = macid-32;
reg_macid_no_link = REG_MACID_NO_LINK_1;
}

8
hal/rtl8188e_dm.c
View file

@ -161,13 +161,13 @@ static void Init_ODM_ComInfo_88E(struct adapter *Adapter)
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_BWIFI_TEST,Adapter->registrypriv.wifi_spec);
if (pHalData->rf_type == RF_1T1R){
if (pHalData->rf_type == RF_1T1R) {
ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_1T1R);
}
else if (pHalData->rf_type == RF_2T2R){
else if (pHalData->rf_type == RF_2T2R) {
ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_2T2R);
}
else if (pHalData->rf_type == RF_1T2R){
else if (pHalData->rf_type == RF_1T2R) {
ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_1T2R);
}
@ -390,7 +390,7 @@ u8 AntDivBeforeLink8188E(struct adapter *Adapter )
}
if (pDM_SWAT_Table->SWAS_NoLink_State == 0){
if (pDM_SWAT_Table->SWAS_NoLink_State == 0) {
/* switch channel */
pDM_SWAT_Table->SWAS_NoLink_State = 1;
pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A;

48
hal/rtl8188e_hal_init.c
View file

@ -408,7 +408,7 @@ s32 rtl8188e_iol_efuse_patch(struct adapter *padapter)
s32 result = _SUCCESS;
printk("==> %s\n",__FUNCTION__);
if (rtw_IOL_applied(padapter)){
if (rtw_IOL_applied(padapter)) {
iol_mode_enable(padapter, 1);
result = iol_execute(padapter, CMD_READ_EFUSE_MAP);
if (result == _SUCCESS)
@ -458,7 +458,7 @@ static int rtl8188e_IOL_exec_cmds_sync(struct adapter *adapter, struct xmit_fram
t1= rtw_get_current_time();
iol_mode_enable(adapter, 1);
for (i=0;i<bndy_cnt;i++){
for (i=0;i<bndy_cnt;i++) {
u8 page_no = 0;
page_no = i*2 ;
/* printk(" i = %d, page_no = %d\n",i,page_no); */
@ -486,8 +486,8 @@ void rtw_IOL_cmd_tx_pkt_buf_dump(struct adapter *Adapter,int data_len)
printk("###### %s ######\n",__FUNCTION__);
rtw_write8(Adapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT);
if (pbuf){
for (addr=0;addr< data_cnts;addr++){
if (pbuf) {
for (addr=0;addr< data_cnts;addr++) {
/* printk("==> addr:0x%02x\n",addr); */
rtw_write32(Adapter,0x140,addr);
rtw_usleep_os(2);
@ -495,7 +495,7 @@ void rtw_IOL_cmd_tx_pkt_buf_dump(struct adapter *Adapter,int data_len)
do{
rstatus=(reg_140=rtw_read32(Adapter,REG_PKTBUF_DBG_CTRL)&BIT24);
/* printk("rstatus = %02x, reg_140:0x%08x\n",rstatus,reg_140); */
if (rstatus){
if (rstatus) {
fifo_data = rtw_read32(Adapter,REG_PKTBUF_DBG_DATA_L);
/* printk("fifo_data_144:0x%08x\n",fifo_data); */
memcpy(pbuf+(addr*8),&fifo_data , 4);
@ -613,7 +613,7 @@ _BlockWrite(
("_BlockWrite: [P3] buffSize_p3(%d) blockSize_p3(%d) blockCount_p3(%d)\n",
(buffSize-offset), blockSize_p3, blockCount_p3));
for (i = 0 ; i < blockCount_p3 ; i++){
for (i = 0 ; i < blockCount_p3 ; i++) {
ret =rtw_write8(padapter, (FW_8188E_START_ADDRESS + offset + i), *(bufferPtr + offset + i));
if (ret == _FAIL)
@ -705,7 +705,7 @@ static void _MCUIO_Reset88E(struct adapter *padapter,u8 bReset)
{
u8 u1bTmp;
if (bReset==true){
if (bReset==true) {
/* Reset MCU IO Wrapper- sugggest by SD1-Gimmy */
u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1);
rtw_write8(padapter,REG_RSV_CTRL+1, (u1bTmp&(~BIT3)));
@ -956,20 +956,20 @@ hal_EfusePowerSwitch_RTL8188E(
/* 1.2V Power: From VDDON with Power Cut(0x0000h[15]), defualt valid */
tmpV16 = rtw_read16(pAdapter,REG_SYS_ISO_CTRL);
if ( ! (tmpV16 & PWC_EV12V ) ){
if ( ! (tmpV16 & PWC_EV12V ) ) {
tmpV16 |= PWC_EV12V ;
rtw_write16(pAdapter,REG_SYS_ISO_CTRL,tmpV16);
}
/* Reset: 0x0000h[28], default valid */
tmpV16 = rtw_read16(pAdapter,REG_SYS_FUNC_EN);
if ( !(tmpV16 & FEN_ELDR) ){
if ( !(tmpV16 & FEN_ELDR) ) {
tmpV16 |= FEN_ELDR ;
rtw_write16(pAdapter,REG_SYS_FUNC_EN,tmpV16);
}
/* Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid */
tmpV16 = rtw_read16(pAdapter,REG_SYS_CLKR);
if ( (!(tmpV16 & LOADER_CLK_EN) ) ||(!(tmpV16 & ANA8M) ) ){
if ( (!(tmpV16 & LOADER_CLK_EN) ) ||(!(tmpV16 & ANA8M) ) ) {
tmpV16 |= (LOADER_CLK_EN |ANA8M ) ;
rtw_write16(pAdapter,REG_SYS_CLKR,tmpV16);
}
@ -987,7 +987,7 @@ hal_EfusePowerSwitch_RTL8188E(
{
rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
if (bWrite == true){
if (bWrite == true) {
/* Disable LDO 2.5V after read/write action */
tempval = rtw_read8(pAdapter, EFUSE_TEST+3);
rtw_write8(pAdapter, EFUSE_TEST+3, (tempval & 0x7F));
@ -1563,7 +1563,7 @@ Hal_EfuseWordEnableDataWrite(struct adapter *pAdapter,
efuse_OneByteRead(pAdapter,tmpaddr, &tmpdata[0], bPseudoTest);
efuse_OneByteRead(pAdapter,tmpaddr+1, &tmpdata[1], bPseudoTest);
if ((data[0]!=tmpdata[0])||(data[1]!=tmpdata[1])){
if ((data[0]!=tmpdata[0])||(data[1]!=tmpdata[1])) {
badworden &= (~BIT0);
}
}
@ -1575,7 +1575,7 @@ Hal_EfuseWordEnableDataWrite(struct adapter *pAdapter,
efuse_OneByteRead(pAdapter,tmpaddr , &tmpdata[2], bPseudoTest);
efuse_OneByteRead(pAdapter,tmpaddr+1, &tmpdata[3], bPseudoTest);
if ((data[2]!=tmpdata[2])||(data[3]!=tmpdata[3])){
if ((data[2]!=tmpdata[2])||(data[3]!=tmpdata[3])) {
badworden &=( ~BIT1);
}
}
@ -1587,7 +1587,7 @@ Hal_EfuseWordEnableDataWrite(struct adapter *pAdapter,
efuse_OneByteRead(pAdapter,tmpaddr, &tmpdata[4], bPseudoTest);
efuse_OneByteRead(pAdapter,tmpaddr+1, &tmpdata[5], bPseudoTest);
if ((data[4]!=tmpdata[4])||(data[5]!=tmpdata[5])){
if ((data[4]!=tmpdata[4])||(data[5]!=tmpdata[5])) {
badworden &=( ~BIT2);
}
}
@ -1599,7 +1599,7 @@ Hal_EfuseWordEnableDataWrite(struct adapter *pAdapter,
efuse_OneByteRead(pAdapter,tmpaddr, &tmpdata[6], bPseudoTest);
efuse_OneByteRead(pAdapter,tmpaddr+1, &tmpdata[7], bPseudoTest);
if ((data[6]!=tmpdata[6])||(data[7]!=tmpdata[7])){
if ((data[6]!=tmpdata[6])||(data[7]!=tmpdata[7])) {
badworden &=( ~BIT3);
}
}
@ -1828,7 +1828,7 @@ hal_EfusePgPacketRead_8188e(
}
}
}
if (bDataEmpty==false){
if (bDataEmpty==false) {
ReadState = PG_STATE_DATA;
}else{/* read next header */
efuse_addr = efuse_addr + (word_cnts*2)+1;
@ -2520,10 +2520,10 @@ ReadChipVersion8188E(struct adapter *padapter)
pHalData->VersionID = ChipVersion;
if (IS_1T2R(ChipVersion)){
if (IS_1T2R(ChipVersion)) {
pHalData->rf_type = RF_1T2R;
pHalData->NumTotalRFPath = 2;
} else if (IS_2T2R(ChipVersion)){
} else if (IS_2T2R(ChipVersion)) {
pHalData->rf_type = RF_2T2R;
pHalData->NumTotalRFPath = 2;
} else{
@ -2549,7 +2549,7 @@ static void rtl8188e_GetHalODMVar(
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
PDM_ODM_T podmpriv = &pHalData->odmpriv;
switch (eVariable){
switch (eVariable) {
case HAL_ODM_STA_INFO:
break;
default:
@ -2566,11 +2566,11 @@ static void rtl8188e_SetHalODMVar(
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
PDM_ODM_T podmpriv = &pHalData->odmpriv;
/* _irqL irqL; */
switch (eVariable){
switch (eVariable) {
case HAL_ODM_STA_INFO:
{
struct sta_info *psta = (struct sta_info *)pValue1;
if (bSet){
if (bSet) {
DBG_8192C("### Set STA_(%d) info\n",psta->mac_id);
ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS,psta->mac_id,psta);
#if (RATE_ADAPTIVE_SUPPORT==1)
@ -3112,7 +3112,7 @@ void Hal_ReadPowerSavingMode88E(
struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
u8 tmpvalue;
if (AutoLoadFail){
if (AutoLoadFail) {
pwrctl->bHWPowerdown = false;
pwrctl->bSupportRemoteWakeup = false;
}
@ -3203,7 +3203,7 @@ Hal_ReadTxPowerInfo88E(
if (!AutoLoadFail)
{
struct registry_priv *registry_par = &padapter->registrypriv;
if ( registry_par->regulatory_tid == 0xff){
if ( registry_par->regulatory_tid == 0xff) {
if (PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION&0x7); /* bit0~2 */
else
@ -3268,7 +3268,7 @@ Hal_EfuseParseEEPROMVer88E(
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
if (!AutoLoadFail){
if (!AutoLoadFail) {
pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_88E];
if (pHalData->EEPROMVersion == 0xFF)
pHalData->EEPROMVersion = EEPROM_Default_Version;

18
hal/rtl8188e_phycfg.c
View file

@ -145,7 +145,7 @@ sic_Read4Byte(
/* RTPRINT(FPHY, PHY_SICR, ("write cmdreg 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_READ)); */
retry = 4;
while (retry--){
while (retry--) {
rtw_udelay_os(50);
/* PlatformStallExecution(50); */
}
@ -179,7 +179,7 @@ sic_Write4Byte(
rtw_write8(Adapter, SIC_ADDR_REG+1, (u8)((offset&0xff00)>>8));
rtw_write32(Adapter, SIC_DATA_REG, (u32)data);
rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_WRITE);
while (retry--){
while (retry--) {
rtw_udelay_os(50);
}
}
@ -205,7 +205,7 @@ SIC_SetBBReg(
/* RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg(), mask=0x%x, addr[0x%x]=0x%x\n", BitMask, RegAddr, Data)); */
if (BitMask!= bMaskDWord){/* if not "double word" write */
if (BitMask!= bMaskDWord) {/* if not "double word" write */
OriginalValue = sic_Read4Byte(Adapter, RegAddr);
/* BitShift = sic_CalculateBitShift(BitMask); */
BitShift = phy_CalculateBitShift(BitMask);
@ -360,7 +360,7 @@ rtl8188e_PHY_SetBBReg(
return;
#endif
if (BitMask!= bMaskDWord){/* if not "double word" write */
if (BitMask!= bMaskDWord) {/* if not "double word" write */
OriginalValue = rtw_read32(Adapter, RegAddr);
BitShift = phy_CalculateBitShift(BitMask);
Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask));
@ -1066,7 +1066,7 @@ phy_BB8188E_Config_ParaFile(
if (HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
rtStatus = _FAIL;
if (rtStatus != _SUCCESS){
if (rtStatus != _SUCCESS) {
/* RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!")); */
goto phy_BB8190_Config_ParaFile_Fail;
}
@ -1090,7 +1090,7 @@ phy_BB8188E_Config_ParaFile(
rtStatus = _FAIL;
}
if (rtStatus != _SUCCESS){
if (rtStatus != _SUCCESS) {
/* RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!")); */
goto phy_BB8190_Config_ParaFile_Fail;
}
@ -1098,7 +1098,7 @@ phy_BB8188E_Config_ParaFile(
/* 3. BB AGC table Initialization */
if (HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
rtStatus = _FAIL;
if (rtStatus != _SUCCESS){
if (rtStatus != _SUCCESS) {
/* RT_TRACE(COMP_FPGA, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():AGC Table Fail\n")); */
goto phy_BB8190_Config_ParaFile_Fail;
}
@ -1899,7 +1899,7 @@ static void phy_SpurCalibration_8188E(
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
/* DbgPrint("===> phy_SpurCalibration_8188E CurrentChannelBW = %d, CurrentChannel = %d\n", pHalData->CurrentChannelBW, pHalData->CurrentChannel); */
if (pHalData->CurrentChannelBW == 0 && pHalData->CurrentChannel == 13){
if (pHalData->CurrentChannelBW == 0 && pHalData->CurrentChannel == 13) {
PHY_SetBBReg(Adapter, rOFDM1_CFOTracking, BIT(28), 0x1); /* enable CSI Mask */
PHY_SetBBReg(Adapter, rOFDM1_csi_fix_mask, BIT(26)|BIT(25), 0x3); /* Fix CSI Mask Tone */
}
@ -2220,7 +2220,7 @@ _PHY_DumpRFReg(struct adapter *pAdapter)
/* RTPRINT(FINIT, INIT_RF, ("PHY_DumpRFReg()====>\n")); */
for (rfRegOffset = 0x00;rfRegOffset<=0x30;rfRegOffset++){
for (rfRegOffset = 0x00;rfRegOffset<=0x30;rfRegOffset++) {
rfRegValue = PHY_QueryRFReg(pAdapter,RF_PATH_A, rfRegOffset, bMaskDWord);
/* RTPRINT(FINIT, INIT_RF, (" 0x%02x = 0x%08x\n",rfRegOffset,rfRegValue)); */
}

2
hal/rtl8188e_rf6052.c
View file

@ -674,7 +674,7 @@ phy_RF6052_Config_ParaFile(
break;
}
if (rtStatus != _SUCCESS){
if (rtStatus != _SUCCESS) {
/* RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); */
goto phy_RF6052_Config_ParaFile_Fail;
}

6
hal/rtl8188e_rxdesc.c
View file

@ -61,7 +61,7 @@ static void process_link_qual(struct adapter *padapter,union recv_frame *prframe
struct rx_pkt_attrib *pattrib;
struct signal_stat * signal_stat;
if (prframe == NULL || padapter== NULL){
if (prframe == NULL || padapter== NULL) {
return;
}
@ -211,8 +211,8 @@ void update_recvframe_phyinfo_88e(
pkt_info.bPacketBeacon = pkt_info.bPacketMatchBSSID && (GetFrameSubType(wlanhdr) == WIFI_BEACON);
if (pkt_info.bPacketBeacon){
if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == true){
if (pkt_info.bPacketBeacon) {
if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == true) {
sa = padapter->mlmepriv.cur_network.network.MacAddress;
}
else

4
hal/rtl8188e_sreset.c
View file

@ -32,7 +32,7 @@ void rtl8188e_sreset_xmit_status_check(struct adapter *padapter)
unsigned int diff_time;
u32 txdma_status;
if ( (txdma_status=rtw_read32(padapter, REG_TXDMA_STATUS)) !=0x00){
if ( (txdma_status=rtw_read32(padapter, REG_TXDMA_STATUS)) !=0x00) {
DBG_871X("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status);
rtw_hal_sreset_reset(padapter);
}
@ -77,7 +77,7 @@ void rtl8188e_sreset_linked_status_check(struct adapter *padapter)
u32 rx_dma_status = 0;
u8 fw_status=0;
rx_dma_status = rtw_read32(padapter,REG_RXDMA_STATUS);
if (rx_dma_status!= 0x00){
if (rx_dma_status!= 0x00) {
DBG_8192C("%s REG_RXDMA_STATUS:0x%08x\n",__FUNCTION__,rx_dma_status);
rtw_write32(padapter,REG_RXDMA_STATUS,rx_dma_status);
}

12
hal/rtl8188e_xmit.c
View file

@ -67,22 +67,22 @@ void _dbg_dump_tx_info(struct adapter *padapter,int frame_tag,struct tx_desc *pt
u8 bDumpTxDesc = false;
rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DUMP_TXPKT, &(bDumpTxPkt));
if (bDumpTxPkt ==1){/* dump txdesc for data frame */
if (bDumpTxPkt ==1) {/* dump txdesc for data frame */
DBG_871X("dump tx_desc for data frame\n");
if ((frame_tag&0x0f) == DATA_FRAMETAG){
if ((frame_tag&0x0f) == DATA_FRAMETAG) {
bDumpTxDesc = true;
}
}
else if (bDumpTxPkt ==2){/* dump txdesc for mgnt frame */
else if (bDumpTxPkt ==2) {/* dump txdesc for mgnt frame */
DBG_871X("dump tx_desc for mgnt frame\n");
if ((frame_tag&0x0f) == MGNT_FRAMETAG){
if ((frame_tag&0x0f) == MGNT_FRAMETAG) {
bDumpTxDesc = true;
}
}
else if (bDumpTxPkt ==3){/* dump early info */
else if (bDumpTxPkt ==3) {/* dump early info */
}
if (bDumpTxDesc){
if (bDumpTxDesc) {
DBG_8192C("=====================================\n");
DBG_8192C("txdw0(0x%08x)\n",ptxdesc->txdw0);
DBG_8192C("txdw1(0x%08x)\n",ptxdesc->txdw1);

6
hal/rtl8188eu_recv.c
View file

@ -64,13 +64,13 @@ int rtl8188eu_init_recv_priv(struct adapter *padapter)
#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
precvpriv->int_in_urb = usb_alloc_urb(0, GFP_KERNEL);
if (precvpriv->int_in_urb == NULL){
if (precvpriv->int_in_urb == NULL) {
res= _FAIL;
DBG_8192C("alloc_urb for interrupt in endpoint fail !!!!\n");
goto exit;
}
precvpriv->int_in_buf = rtw_zmalloc(INTERRUPT_MSG_FORMAT_LEN);
if (precvpriv->int_in_buf == NULL){
if (precvpriv->int_in_buf == NULL) {
res= _FAIL;
DBG_8192C("alloc_mem for interrupt in endpoint fail !!!!\n");
goto exit;
@ -81,7 +81,7 @@ int rtl8188eu_init_recv_priv(struct adapter *padapter)
_rtw_init_queue(&precvpriv->free_recv_buf_queue);
precvpriv->pallocated_recv_buf = rtw_zmalloc(NR_RECVBUFF *sizeof(struct recv_buf) + 4);
if (precvpriv->pallocated_recv_buf== NULL){
if (precvpriv->pallocated_recv_buf== NULL) {
res= _FAIL;
RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("alloc recv_buf fail!\n"));
goto exit;

20
hal/rtl8188eu_xmit.c
View file

@ -62,7 +62,7 @@ static void rtl8188eu_cal_txdesc_chksum(struct tx_desc *ptxdesc)
/* Clear first */
ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
for (index = 0 ; index < count ; index++){
for (index = 0 ; index < count ; index++) {
checksum = checksum ^ le16_to_cpu(*(__le16 *)(usPtr + index));
}
@ -267,7 +267,7 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bag
fill_txdesc_sectype(pattrib, ptxdesc);
if (pattrib->ampdu_en==true){
if (pattrib->ampdu_en==true) {
ptxdesc->txdw2 |= cpu_to_le32(AGG_EN);/* AGG EN */
ptxdesc->txdw6 = cpu_to_le32(0x6666f800);
} else{
@ -286,7 +286,7 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bag
ptxdesc->txdw4 |= cpu_to_le32(QOS);/* QoS */
/* offset 20 */
if (pxmitframe->agg_num > 1){
if (pxmitframe->agg_num > 1) {
/* DBG_8192C("%s agg_num:%d\n",__FUNCTION__,pxmitframe->agg_num ); */
ptxdesc->txdw5 |= cpu_to_le32((pxmitframe->agg_num << USB_TXAGG_NUM_SHT) & 0xFF000000);
}
@ -305,14 +305,14 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bag
ptxdesc->txdw5 |= cpu_to_le32(0x0001ff00);/* DATA/RTS Rate FB LMT */
#if (RATE_ADAPTIVE_SUPPORT == 1)
if (pattrib->ht_en){
if (pattrib->ht_en) {
if ( ODM_RA_GetShortGI_8188E(&pHalData->odmpriv,pattrib->mac_id))
ptxdesc->txdw5 |= cpu_to_le32(SGI);/* SGI */
}
data_rate =ODM_RA_GetDecisionRate_8188E(&pHalData->odmpriv,pattrib->mac_id);
/* for debug */
if (padapter->fix_rate!= 0xFF){
if (padapter->fix_rate!= 0xFF) {
data_rate = padapter->fix_rate;
ptxdesc->txdw4 |= cpu_to_le32(DISDATAFB);
@ -330,7 +330,7 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bag
ptxdesc->txdw5 |= cpu_to_le32(SGI);/* SGI */
data_rate = 0x13; /* default rate: MCS7 */
if (padapter->fix_rate!= 0xFF){/* rate control by iwpriv */
if (padapter->fix_rate!= 0xFF) {/* rate control by iwpriv */
data_rate = padapter->fix_rate;
ptxdesc->txdw4 | cpu_to_le32(DISDATAFB);
}
@ -384,7 +384,7 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bag
ptxdesc->txdw5 |= cpu_to_le32(0x00300000);/* retry limit = 12 */
#ifdef CONFIG_INTEL_PROXIM
if ((padapter->proximity.proxim_on==true)&&(pattrib->intel_proxim==true)){
if ((padapter->proximity.proxim_on==true)&&(pattrib->intel_proxim==true)) {
DBG_871X("\n %s pattrib->rate=%d\n",__FUNCTION__,pattrib->rate);
ptxdesc->txdw5 |= cpu_to_le32( pattrib->rate);
}
@ -567,7 +567,7 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm
/* check xmitbuffer is ok */
if (pxmitbuf == NULL) {
pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
if (pxmitbuf == NULL){
if (pxmitbuf == NULL) {
/* DBG_871X("%s #1, connot alloc xmitbuf!!!!\n",__FUNCTION__); */
return false;
}
@ -643,13 +643,13 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm
/* dequeue same priority packet from station tx queue */
/* psta = pfirstframe->attrib.psta; */
psta = rtw_get_stainfo(&padapter->stapriv, pfirstframe->attrib.ra);
if (pfirstframe->attrib.psta != psta){
if (pfirstframe->attrib.psta != psta) {
DBG_871X("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pfirstframe->attrib.psta, psta);
}
if (psta == NULL) {
DBG_8192C("rtw_xmit_classifier: psta == NULL\n");
}
if (!(psta->state &_FW_LINKED)){
if (!(psta->state &_FW_LINKED)) {
DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state);
}

64
hal/usb_halinit.c
View file

@ -50,7 +50,7 @@ _ConfigNormalChipOutEP_8188E(
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
switch (NumOutPipe){
switch (NumOutPipe) {
case 3:
pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_LQ|TX_SELE_NQ;
pHalData->OutEpNumber=3;
@ -83,14 +83,14 @@ static bool HalUsbSetQueuePipeMapping8188EUsb(
_ConfigNormalChipOutEP_8188E(pAdapter, NumOutPipe);
/* Normal chip with one IN and one OUT doesn't have interrupt IN EP. */
if (1 == pHalData->OutEpNumber){
if (1 != NumInPipe){
if (1 == pHalData->OutEpNumber) {
if (1 != NumInPipe) {
return result;
}
}
/* All config other than above support one Bulk IN and one Interrupt IN. */
/* if (2 != NumInPipe){ */
/* if (2 != NumInPipe) { */
/* return result; */
/* */
@ -285,7 +285,7 @@ _SetMacID(
)
{
u32 i;
for (i=0 ; i< MAC_ADDR_LEN ; i++){
for (i=0 ; i< MAC_ADDR_LEN ; i++) {
rtw_write32(Adapter, REG_MACID+i, MacID[i]);
}
}
@ -296,7 +296,7 @@ _SetBSSID(
)
{
u32 i;
for (i=0 ; i< MAC_ADDR_LEN ; i++){
for (i=0 ; i< MAC_ADDR_LEN ; i++) {
rtw_write32(Adapter, REG_BSSID+i, BSSID[i]);
}
}
@ -509,7 +509,7 @@ _InitNormalChipTwoOutEpPriority(
break;
}
if (!pregistrypriv->wifi_spec ){
if (!pregistrypriv->wifi_spec ) {
beQ = valueLow;
bkQ = valueLow;
viQ = valueHi;
@ -538,7 +538,7 @@ _InitNormalChipThreeOutEpPriority(
struct registry_priv *pregistrypriv = &Adapter->registrypriv;
u16 beQ,bkQ,viQ,voQ,mgtQ,hiQ;
if (!pregistrypriv->wifi_spec ){/* typical setting */
if (!pregistrypriv->wifi_spec ) {/* typical setting */
beQ = QUEUE_LOW;
bkQ = QUEUE_LOW;
viQ = QUEUE_NORMAL;
@ -806,7 +806,7 @@ usb_AggSettingTxUpdate(
if (Adapter->registrypriv.wifi_spec)
pHalData->UsbTxAggMode = false;
if (pHalData->UsbTxAggMode){
if (pHalData->UsbTxAggMode) {
value32 = rtw_read32(Adapter, REG_TDECTRL);
value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
value32 |= ((pHalData->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
@ -1012,7 +1012,7 @@ _InitRFType(
pHalData->rf_chip = RF_6052;
if (false == is92CU){
if (false == is92CU) {
pHalData->rf_type = RF_1T1R;
DBG_8192C("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n");
return;
@ -1242,7 +1242,7 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter)
{
_ps_open_RF(Adapter);
if (pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized){
if (pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized) {
PHY_IQCalibrate_8188E(Adapter,true);
}
else
@ -1260,7 +1260,7 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter)
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
status = InitPowerOn_rtl8188eu(Adapter);
if (status == _FAIL){
if (status == _FAIL) {
RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n"));
goto exit;
}
@ -1269,7 +1269,7 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter)
pHalData->CurrentChannel = 6;/* default set to 6 */
if (pwrctrlpriv->reg_rfoff == true){
if (pwrctrlpriv->reg_rfoff == true) {
pwrctrlpriv->rf_pwrstate = rf_off;
}
@ -1348,7 +1348,7 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter)
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_EFUSE_PATCH);
status = rtl8188e_iol_efuse_patch(Adapter);
if (status == _FAIL){
if (status == _FAIL) {
DBG_871X("%s rtl8188e_iol_efuse_patch failed\n",__FUNCTION__);
goto exit;
}
@ -1357,7 +1357,7 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter)
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
status = InitLLTTable(Adapter, txpktbuf_bndy);
if (status == _FAIL){
if (status == _FAIL) {
RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n"));
goto exit;
}
@ -1391,7 +1391,7 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter)
_InitHardwareDropIncorrectBulkOut(Adapter);
if (pHalData->bRDGEnable){
if (pHalData->bRDGEnable) {
_InitRDGSetting(Adapter);
}
@ -1495,7 +1495,7 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter)
/* 2010/08/26 MH Merge from 8192CE. */
if (pwrctrlpriv->rf_pwrstate == rf_on)
{
if (pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized){
if (pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized) {
PHY_IQCalibrate_8188E(Adapter,true);
} else {
PHY_IQCalibrate_8188E(Adapter,false);
@ -1640,7 +1640,7 @@ static u32 rtl8188eu_hal_deinit(struct adapter *Adapter)
if ((pwrctl->bHWPwrPindetect) && (pwrctl->bHWPowerdown))
rtl8188eu_hw_power_down(Adapter);
} else {
if (Adapter->hw_init_completed == true){
if (Adapter->hw_init_completed == true) {
hal_poweroff_rtl8188eu(Adapter);
if ((pwrctl->bHWPwrPindetect ) && (pwrctl->bHWPowerdown))
@ -2524,7 +2524,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
/* ); */
break;
case HW_VAR_DM_FUNC_SET:
if (*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE){
if (*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE) {
pdmpriv->DMFlag = pdmpriv->InitDMFlag;
podmpriv->SupportAbility = pdmpriv->InitODMFlag;
}
@ -2647,7 +2647,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
break;
}
if (MinSpacingToSet < SecMinSpace){
if (MinSpacingToSet < SecMinSpace) {
MinSpacingToSet = SecMinSpace;
}
@ -2738,7 +2738,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
DIG_T *pDigTable = &podmpriv->DM_DigTable;
u32 rx_gain = ((u32 *)(val))[0];
if (rx_gain == 0xff){/* restore rx gain */
if (rx_gain == 0xff) {/* restore rx gain */
ODM_Write_DIG(podmpriv,pDigTable->BackupIGValue);
}
else{
@ -3014,11 +3014,11 @@ static u8 GetHalDefVar8188EUsb(
if (rtw_linked_check(Adapter))
bLinked = true;
if (bLinked){
if (bLinked) {
DBG_871X("============ RA status check ===================\n");
if (Adapter->bRxRSSIDisplay >30)
Adapter->bRxRSSIDisplay = 1;
for (i=0;i< Adapter->bRxRSSIDisplay;i++){
for (i=0;i< Adapter->bRxRSSIDisplay;i++) {
DBG_8192C("Mac_id:%d ,RSSI:%d,RateID = %d,RAUseRate = 0x%08x,RateSGI = %d, DecisionRate = 0x%02x ,PTStage = %d, RetryOver drop:%d, LifeTimeOver drop:%d\n",
i,
podmpriv->RAInfo[i].RssiStaRA,
@ -3074,24 +3074,24 @@ static u8 SetHalDefVar8188EUsb(
{
u8 dm_func = *(( u8*)pValue);
if (dm_func == 0){ /* disable all dynamic func */
if (dm_func == 0) { /* disable all dynamic func */
podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE;
DBG_8192C("==> Disable all dynamic function...\n");
}
else if (dm_func == 1){/* disable DIG */
else if (dm_func == 1) {/* disable DIG */
podmpriv->SupportAbility &= (~DYNAMIC_BB_DIG);
DBG_8192C("==> Disable DIG...\n");
}
else if (dm_func == 2){/* disable High power */
else if (dm_func == 2) {/* disable High power */
podmpriv->SupportAbility &= (~DYNAMIC_BB_DYNAMIC_TXPWR);
}
else if (dm_func == 3){/* disable tx power tracking */
else if (dm_func == 3) {/* disable tx power tracking */
podmpriv->SupportAbility &= (~DYNAMIC_RF_CALIBRATION);
DBG_8192C("==> Disable tx power tracking...\n");
} else if (dm_func == 5){/* disable antenna diversity */
} else if (dm_func == 5) {/* disable antenna diversity */
podmpriv->SupportAbility &= (~DYNAMIC_BB_ANT_DIV);
}
else if (dm_func == 6){/* turn on all dynamic func */
else if (dm_func == 6) {/* turn on all dynamic func */
if (!(podmpriv->SupportAbility & DYNAMIC_BB_DIG))
{
DIG_T *pDigTable = &podmpriv->DM_DigTable;
@ -3224,7 +3224,7 @@ static void UpdateHalRAMask8188EUsb(struct adapter *padapter, u32 mac_id, u8 rss
DBG_871X("update raid entry, mask=0x%x, arg=0x%x\n", mask, arg);
psta->ra_mask=mask;
#ifdef CONFIG_INTEL_PROXIM
if (padapter->proximity.proxim_on ==true){
if (padapter->proximity.proxim_on ==true) {
arg &= ~BIT(6);
}
else {
@ -3350,7 +3350,7 @@ static void rtl8188eu_init_default_value(struct adapter * padapter)
static u8 rtl8188eu_ps_func(struct adapter *Adapter, enum HAL_INTF_PS_FUNC efunc_id, u8 *val)
{
u8 bResult = true;
switch (efunc_id){
switch (efunc_id) {
#if defined(CONFIG_AUTOSUSPEND)
case HAL_USB_SELECT_SUSPEND:
@ -3370,7 +3370,7 @@ void rtl8188eu_set_hal_ops(struct adapter * padapter)
padapter->HalData = rtw_zmalloc(sizeof(HAL_DATA_TYPE));
if (padapter->HalData == NULL){
if (padapter->HalData == NULL) {
DBG_8192C("cant not alloc memory for HAL DATA\n");
}

16
hal/usb_ops_linux.c
View file

@ -40,13 +40,13 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u
u8 *pIo_buf;
int vendorreq_times = 0;
if ((padapter->bSurpriseRemoved) ||(dvobj_to_pwrctl(pdvobjpriv)->pnp_bstop_trx)){
if ((padapter->bSurpriseRemoved) ||(dvobj_to_pwrctl(pdvobjpriv)->pnp_bstop_trx)) {
RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usbctrl_vendorreq:(padapter->bSurpriseRemoved ||pwrctl->pnp_bstop_trx)!!!\n"));
status = -EPERM;
goto exit;
}
if (len>MAX_VENDOR_REQ_CMD_SIZE){
if (len>MAX_VENDOR_REQ_CMD_SIZE) {
DBG_8192C( "[%s] Buffer len error ,vendor request failed\n", __FUNCTION__ );
status = -EINVAL;
goto exit;
@ -112,7 +112,7 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u
}
}
if (rtw_inc_and_chk_continual_io_error(pdvobjpriv) == true ){
if (rtw_inc_and_chk_continual_io_error(pdvobjpriv) == true ) {
padapter->bSurpriseRemoved = true;
break;
}
@ -310,7 +310,7 @@ static void interrupt_handler_8188eu(struct adapter *padapter,u16 pkt_len,u8 *pb
DBG_871X("===> %s Receive FIFO Overflow\n",__FUNCTION__);
/* C2H Event */
if (pbuf[0]!= 0){
if (pbuf[0]!= 0) {
memcpy(&(pHalData->C2hArray[0]), &(pbuf[USB_INTR_CONTENT_C2H_OFFSET]), 16);
/* rtw_c2h_wk_cmd(padapter); to do.. */
}
@ -498,7 +498,7 @@ static int recvbuf2recvframe(struct adapter *padapter, struct sk_buff *pskb)
/* for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. */
/* modify alloc_sz for recvive crc error packet by thomas 2011-06-02 */
if ((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){
if ((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)) {
if (skb_len <= 1650)
alloc_sz = 1664;
else
@ -576,12 +576,12 @@ static int recvbuf2recvframe(struct adapter *padapter, struct sk_buff *pskb)
}
} else{ /* pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP */
/* enqueue recvframe to txrtp queue */
if (pattrib->pkt_rpt_type == TX_REPORT1){
if (pattrib->pkt_rpt_type == TX_REPORT1) {
/* DBG_8192C("rx CCX\n"); */
/* CCX-TXRPT ack for xmit mgmt frames. */
handle_txrpt_ccx_88e(padapter, precvframe->u.hdr.rx_data);
}
else if (pattrib->pkt_rpt_type == TX_REPORT2){
else if (pattrib->pkt_rpt_type == TX_REPORT2) {
/* DBG_8192C("rx TX RPT\n"); */
ODM_RA_TxRPT2Handle_8188E(
&pHalData->odmpriv,
@ -703,7 +703,7 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs)
DBG_8192C("###=> usb_read_port_complete => urb status(%d)\n", purb->status);
if (rtw_inc_and_chk_continual_io_error(adapter_to_dvobj(padapter)) == true ){
if (rtw_inc_and_chk_continual_io_error(adapter_to_dvobj(padapter)) == true ) {
padapter->bSurpriseRemoved = true;
}