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rtl8188eu: Remove all macros and tests of the type IS_HARDWARE_TYPE_XXX

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Only IS_HARDWARE_TYPE_8188E is kept.

Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2018-11-12 12:10:32 -06:00
parent 4ff88c48d1
commit 0c57c68d3e
12 changed files with 144 additions and 793 deletions
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29
core/rtw_efuse.c
View file

@ -989,10 +989,8 @@ efuse_OneByteRead(
u8 readbyte;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
if (IS_HARDWARE_TYPE_8723B(pAdapter) ||
(IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||
(IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))
) {
if ((IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) ||
(IS_CHIP_VENDOR_SMIC(pHalData->version_id))) {
/* <20130121, Kordan> For SMIC EFUSE specificatoin. */
/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */
/* phy_set_mac_reg(pAdapter, 0x34, BIT11, 0); */
@ -1314,11 +1312,6 @@ ReadEFuseByte(
Efuse_Read1ByteFromFakeContent(Adapter, _offset, pbuf);
return;
}
if (IS_HARDWARE_TYPE_8723B(Adapter)) {
/* <20130121, Kordan> For SMIC S55 EFUSE specificatoin. */
/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */
phy_set_mac_reg(Adapter, EFUSE_TEST, BIT11, 0);
}
/* Write Address */
rtw_write8(Adapter, EFUSE_CTRL + 1, (_offset & 0xff));
readbyte = rtw_read8(Adapter, EFUSE_CTRL + 2);
@ -1423,10 +1416,8 @@ efuse_OneByteRead(
return bResult;
}
if (IS_HARDWARE_TYPE_8723B(pAdapter) ||
(IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||
(IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))
) {
if ((IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) ||
(IS_CHIP_VENDOR_SMIC(pHalData->version_id))) {
/* <20130121, Kordan> For SMIC EFUSE specificatoin. */
/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */
/* phy_set_mac_reg(pAdapter, 0x34, BIT11, 0); */
@ -1494,10 +1485,8 @@ efuse_OneByteWrite(
efuseValue |= ((addr << 8 | data) & 0x3FFFF);
/* <20130227, Kordan> 8192E MP chip A-cut had better not set 0x34[11] until B-Cut. */
if (IS_HARDWARE_TYPE_8723B(pAdapter) ||
(IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||
(IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))
) {
if ((IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) ||
(IS_CHIP_VENDOR_SMIC(pHalData->version_id))) {
/* <20130121, Kordan> For SMIC EFUSE specificatoin. */
/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */
/* phy_set_mac_reg(pAdapter, 0x34, BIT11, 1); */
@ -1523,10 +1512,8 @@ efuse_OneByteWrite(
}
/* disable Efuse program enable */
if (IS_HARDWARE_TYPE_8723B(pAdapter) ||
(IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||
(IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))
)
if ((IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) ||
(IS_CHIP_VENDOR_SMIC(pHalData->version_id)))
phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT(11), 0);
Efuse_PowerSwitch(pAdapter, _TRUE, _FALSE);

2
core/rtw_mp.c
View file

@ -320,8 +320,6 @@ static VOID PHY_SetRFPathSwitch_default(
static void mpt_InitHWConfig(PADAPTER Adapter)
{
if (IS_HARDWARE_TYPE_8188ES(Adapter))
phy_set_mac_reg(Adapter, 0x4C , BIT23, 0); /*select DPDT_P and DPDT_N as output pin*/
}
static void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery)

37
core/rtw_rf.c
View file

@ -1022,13 +1022,8 @@ static s8 rtw_rf_get_kfree_tx_gain_offset(_adapter *padapter, u8 path, u8 ch)
if (kfree_data->flag & KFREE_FLAG_ON) {
kfree_offset = kfree_data->bb_gain[bb_gain_sel][path];
if (IS_HARDWARE_TYPE_8723D(padapter))
RTW_INFO("%s path:%s, ch:%u, bb_gain_sel:%d, kfree_offset:%d\n"
, __func__, (path == 0)?"S1":"S0",
ch, bb_gain_sel, kfree_offset);
else
RTW_INFO("%s path:%u, ch:%u, bb_gain_sel:%d, kfree_offset:%d\n"
, __func__, path, ch, bb_gain_sel, kfree_offset);
RTW_INFO("%s path:%u, ch:%u, bb_gain_sel:%d, kfree_offset:%d\n",
__func__, path, ch, bb_gain_sel, kfree_offset);
}
exit:
#endif /* CONFIG_RF_POWER_TRIM */
@ -1041,18 +1036,8 @@ void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset)
u8 target_path = 0;
u32 val32 = 0;
if (IS_HARDWARE_TYPE_8723D(adapter)) {
target_path = RF_PATH_A; /*in 8723D case path means S0/S1*/
if (path == PPG_8723D_S1)
RTW_INFO("kfree gain_offset 0x55:0x%x ",
rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff));
else if (path == PPG_8723D_S0)
RTW_INFO("kfree gain_offset 0x65:0x%x ",
rtw_hal_read_rfreg(adapter, target_path, 0x65, 0xffffffff));
} else {
target_path = path;
RTW_INFO("kfree gain_offset 0x55:0x%x ", rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff));
}
target_path = path;
RTW_INFO("kfree gain_offset 0x55:0x%x ", rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff));
switch (rtw_get_chip_type(adapter)) {
default:
@ -1060,14 +1045,7 @@ void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset)
break;
}
if (IS_HARDWARE_TYPE_8723D(adapter)) {
if (path == PPG_8723D_S1)
val32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff);
else if (path == PPG_8723D_S0)
val32 = rtw_hal_read_rfreg(adapter, target_path, 0x65, 0xffffffff);
} else {
val32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff);
}
val32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff);
RTW_INFO(" after :0x%x\n", val32);
}
@ -1079,10 +1057,7 @@ void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch)
s8 total_offset;
int i, total = 0;
if (IS_HARDWARE_TYPE_8723D(adapter))
total = 2; /* S1 and S0 */
else
total = hal_data->NumTotalRFPath;
total = hal_data->NumTotalRFPath;
for (i = 0; i < total; i++) {
kfree_offset = rtw_rf_get_kfree_tx_gain_offset(adapter, i, ch);

2
core/rtw_xmit.c
View file

@ -797,7 +797,7 @@ static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitf
/* to do list: check MIMO power save condition. */
/* check AMPDU aggregation for TXOP */
if ((pattrib->ampdu_en == _TRUE) && (!IS_HARDWARE_TYPE_8812(padapter))) {
if ((pattrib->ampdu_en == _TRUE)) {
pattrib->vcs_mode = RTS_CTS;
break;
}