mirror of
https://github.com/lwfinger/rtl8188eu.git
synced 2024-11-14 17:09:36 +00:00
rtl8188eu: Remove all macros and tests of the type IS_HARDWARE_TYPE_XXX
Only IS_HARDWARE_TYPE_8188E is kept. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
parent
4ff88c48d1
commit
0c57c68d3e
12 changed files with 144 additions and 793 deletions
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@ -989,10 +989,8 @@ efuse_OneByteRead(
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u8 readbyte;
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
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if (IS_HARDWARE_TYPE_8723B(pAdapter) ||
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(IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||
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(IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))
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) {
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if ((IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) ||
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(IS_CHIP_VENDOR_SMIC(pHalData->version_id))) {
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/* <20130121, Kordan> For SMIC EFUSE specificatoin. */
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/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */
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/* phy_set_mac_reg(pAdapter, 0x34, BIT11, 0); */
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@ -1314,11 +1312,6 @@ ReadEFuseByte(
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Efuse_Read1ByteFromFakeContent(Adapter, _offset, pbuf);
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return;
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}
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if (IS_HARDWARE_TYPE_8723B(Adapter)) {
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/* <20130121, Kordan> For SMIC S55 EFUSE specificatoin. */
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/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */
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phy_set_mac_reg(Adapter, EFUSE_TEST, BIT11, 0);
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}
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/* Write Address */
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rtw_write8(Adapter, EFUSE_CTRL + 1, (_offset & 0xff));
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readbyte = rtw_read8(Adapter, EFUSE_CTRL + 2);
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@ -1423,10 +1416,8 @@ efuse_OneByteRead(
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return bResult;
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}
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if (IS_HARDWARE_TYPE_8723B(pAdapter) ||
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(IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||
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(IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))
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) {
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if ((IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) ||
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(IS_CHIP_VENDOR_SMIC(pHalData->version_id))) {
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/* <20130121, Kordan> For SMIC EFUSE specificatoin. */
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/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */
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/* phy_set_mac_reg(pAdapter, 0x34, BIT11, 0); */
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@ -1494,10 +1485,8 @@ efuse_OneByteWrite(
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efuseValue |= ((addr << 8 | data) & 0x3FFFF);
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/* <20130227, Kordan> 8192E MP chip A-cut had better not set 0x34[11] until B-Cut. */
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if (IS_HARDWARE_TYPE_8723B(pAdapter) ||
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(IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||
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(IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))
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) {
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if ((IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) ||
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(IS_CHIP_VENDOR_SMIC(pHalData->version_id))) {
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/* <20130121, Kordan> For SMIC EFUSE specificatoin. */
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/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */
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/* phy_set_mac_reg(pAdapter, 0x34, BIT11, 1); */
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@ -1523,10 +1512,8 @@ efuse_OneByteWrite(
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}
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/* disable Efuse program enable */
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if (IS_HARDWARE_TYPE_8723B(pAdapter) ||
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(IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||
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(IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))
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)
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if ((IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) ||
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(IS_CHIP_VENDOR_SMIC(pHalData->version_id)))
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phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT(11), 0);
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Efuse_PowerSwitch(pAdapter, _TRUE, _FALSE);
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@ -320,8 +320,6 @@ static VOID PHY_SetRFPathSwitch_default(
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static void mpt_InitHWConfig(PADAPTER Adapter)
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{
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if (IS_HARDWARE_TYPE_8188ES(Adapter))
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phy_set_mac_reg(Adapter, 0x4C , BIT23, 0); /*select DPDT_P and DPDT_N as output pin*/
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}
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static void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery)
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@ -1022,13 +1022,8 @@ static s8 rtw_rf_get_kfree_tx_gain_offset(_adapter *padapter, u8 path, u8 ch)
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if (kfree_data->flag & KFREE_FLAG_ON) {
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kfree_offset = kfree_data->bb_gain[bb_gain_sel][path];
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if (IS_HARDWARE_TYPE_8723D(padapter))
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RTW_INFO("%s path:%s, ch:%u, bb_gain_sel:%d, kfree_offset:%d\n"
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, __func__, (path == 0)?"S1":"S0",
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ch, bb_gain_sel, kfree_offset);
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else
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RTW_INFO("%s path:%u, ch:%u, bb_gain_sel:%d, kfree_offset:%d\n"
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, __func__, path, ch, bb_gain_sel, kfree_offset);
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RTW_INFO("%s path:%u, ch:%u, bb_gain_sel:%d, kfree_offset:%d\n",
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__func__, path, ch, bb_gain_sel, kfree_offset);
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}
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exit:
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#endif /* CONFIG_RF_POWER_TRIM */
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@ -1041,18 +1036,8 @@ void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset)
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u8 target_path = 0;
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u32 val32 = 0;
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if (IS_HARDWARE_TYPE_8723D(adapter)) {
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target_path = RF_PATH_A; /*in 8723D case path means S0/S1*/
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if (path == PPG_8723D_S1)
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RTW_INFO("kfree gain_offset 0x55:0x%x ",
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rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff));
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else if (path == PPG_8723D_S0)
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RTW_INFO("kfree gain_offset 0x65:0x%x ",
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rtw_hal_read_rfreg(adapter, target_path, 0x65, 0xffffffff));
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} else {
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target_path = path;
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RTW_INFO("kfree gain_offset 0x55:0x%x ", rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff));
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}
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switch (rtw_get_chip_type(adapter)) {
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default:
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@ -1060,14 +1045,7 @@ void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset)
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break;
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}
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if (IS_HARDWARE_TYPE_8723D(adapter)) {
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if (path == PPG_8723D_S1)
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val32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff);
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else if (path == PPG_8723D_S0)
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val32 = rtw_hal_read_rfreg(adapter, target_path, 0x65, 0xffffffff);
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} else {
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val32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff);
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}
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RTW_INFO(" after :0x%x\n", val32);
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}
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@ -1079,9 +1057,6 @@ void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch)
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s8 total_offset;
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int i, total = 0;
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if (IS_HARDWARE_TYPE_8723D(adapter))
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total = 2; /* S1 and S0 */
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else
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total = hal_data->NumTotalRFPath;
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for (i = 0; i < total; i++) {
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@ -797,7 +797,7 @@ static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitf
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/* to do list: check MIMO power save condition. */
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/* check AMPDU aggregation for TXOP */
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if ((pattrib->ampdu_en == _TRUE) && (!IS_HARDWARE_TYPE_8812(padapter))) {
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if ((pattrib->ampdu_en == _TRUE)) {
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pattrib->vcs_mode = RTS_CTS;
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break;
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}
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131
hal/hal_com.c
131
hal/hal_com.c
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@ -2758,15 +2758,6 @@ void hw_var_port_switch(_adapter *adapter)
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rtw_write8(adapter, REG_BSSID1 + i, bssid[i]);
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/* write bcn ctl */
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#ifdef CONFIG_BT_COEXIST
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/* always enable port0 beacon function for PSTDMA */
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if (IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8703B(adapter)
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|| IS_HARDWARE_TYPE_8723D(adapter))
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bcn_ctrl_1 |= EN_BCN_FUNCTION;
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/* always disable port1 beacon function for PSTDMA */
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if (IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8703B(adapter))
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bcn_ctrl &= ~EN_BCN_FUNCTION;
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#endif
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rtw_write8(adapter, REG_BCN_CTRL, bcn_ctrl_1);
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rtw_write8(adapter, REG_BCN_CTRL_1, bcn_ctrl);
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@ -3841,8 +3832,7 @@ static u8 rtw_hal_set_remote_wake_ctrl_cmd(_adapter *adapter, u8 enable)
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SET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN(
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u1H2CRemoteWakeCtrlParm, enable);
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if (IS_HARDWARE_TYPE_8188E(adapter) ||
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IS_HARDWARE_TYPE_8812(adapter)) {
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if (IS_HARDWARE_TYPE_8188E(adapter)) {
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SET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN(
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u1H2CRemoteWakeCtrlParm, 0);
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SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(
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@ -6132,10 +6122,8 @@ static void rtw_hal_construct_ARPRsp(
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*pLength += 28;
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if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) {
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if (IS_HARDWARE_TYPE_8188E(padapter) ||
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IS_HARDWARE_TYPE_8812(padapter)) {
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if (IS_HARDWARE_TYPE_8188E(padapter))
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rtw_hal_append_tkip_mic(padapter, pframe, arp_offset);
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}
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*pLength += 8;
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}
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}
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@ -6513,7 +6501,7 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
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rsvd_page_loc->LocGTKInfo = *page_num;
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RTW_INFO("LocGTKInfo: %d\n", rsvd_page_loc->LocGTKInfo);
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if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_8812(adapter)) {
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if (IS_HARDWARE_TYPE_8188E(adapter)) {
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struct security_priv *psecpriv = NULL;
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psecpriv = &adapter->securitypriv;
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@ -7508,9 +7496,6 @@ static void rtw_hal_wow_enable(_adapter *adapter)
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if (psecuritypriv->binstallKCK_KEK == _TRUE)
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rtw_hal_fw_sync_cam_id(adapter);
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#endif
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if (IS_HARDWARE_TYPE_8723B(adapter))
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rtw_hal_backup_rate(adapter);
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/* RX DMA stop */
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if (IS_HARDWARE_TYPE_8188E(adapter))
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rtw_hal_disable_tx_report(adapter);
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@ -8655,18 +8640,6 @@ u8 rtw_hal_query_txbfer_rf_num(_adapter *adapter)
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struct registry_priv *pregistrypriv = &adapter->registrypriv;
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HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
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if ((pregistrypriv->beamformer_rf_num) && (IS_HARDWARE_TYPE_8814AE(adapter) || IS_HARDWARE_TYPE_8814AU(adapter) || IS_HARDWARE_TYPE_8822BU(adapter) || IS_HARDWARE_TYPE_8821C(adapter)))
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return pregistrypriv->beamformer_rf_num;
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else if (IS_HARDWARE_TYPE_8814AE(adapter)
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) {
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/*BF cap provided by Yu Chen, Sean, 2015, 01 */
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if (hal_data->rf_type == RF_3T3R)
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return 2;
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else if (hal_data->rf_type == RF_4T4R)
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return 3;
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else
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return 1;
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} else
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return 1;
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}
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@ -8678,16 +8651,7 @@ u8 rtw_hal_query_txbfee_rf_num(_adapter *adapter)
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HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
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if ((pregistrypriv->beamformee_rf_num) && (IS_HARDWARE_TYPE_8814AE(adapter) || IS_HARDWARE_TYPE_8814AU(adapter) || IS_HARDWARE_TYPE_8822BU(adapter) || IS_HARDWARE_TYPE_8821C(adapter)))
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return pregistrypriv->beamformee_rf_num;
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else if (IS_HARDWARE_TYPE_8814AE(adapter) || IS_HARDWARE_TYPE_8814AU(adapter)) {
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if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM)
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return 2;
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else
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return 2;/*TODO: May be 3 in the future, by ChenYu. */
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} else
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return 1;
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}
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#endif
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@ -9896,42 +9860,9 @@ void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer)
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u8 cur_wireless_mode = WIRELESS_INVALID;
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#ifdef CONFIG_USB_RX_AGGREGATION
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if (IS_HARDWARE_TYPE_8821U(padapter)) { /* || IS_HARDWARE_TYPE_8192EU(padapter)) */
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/* This AGG_PH_TH only for UsbRxAggMode == USB_RX_AGG_USB */
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if ((pHalData->rxagg_mode == RX_AGG_USB) && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) {
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if (pdvobjpriv->traffic_stat.cur_tx_tp > 2 && pdvobjpriv->traffic_stat.cur_rx_tp < 30)
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rtw_write16(padapter , REG_RXDMA_AGG_PG_TH , 0x1010);
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else if (pdvobjpriv->traffic_stat.last_tx_bytes > 220000 && pdvobjpriv->traffic_stat.cur_rx_tp < 30)
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rtw_write16(padapter , REG_RXDMA_AGG_PG_TH , 0x1006);
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else
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rtw_write16(padapter, REG_RXDMA_AGG_PG_TH, 0x2005); /* dmc agg th 20K */
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/* RTW_INFO("TX_TP=%u, RX_TP=%u\n", pdvobjpriv->traffic_stat.cur_tx_tp, pdvobjpriv->traffic_stat.cur_rx_tp); */
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}
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} else if (IS_HARDWARE_TYPE_8812(padapter)) {
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#ifdef CONFIG_CONCURRENT_MODE
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u8 i;
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_adapter *iface;
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u8 bassocaed = _FALSE;
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struct mlme_ext_priv *mlmeext;
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for (i = 0; i < pdvobjpriv->iface_nums; i++) {
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iface = pdvobjpriv->padapters[i];
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mlmeext = &iface->mlmeextpriv;
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if (rtw_linked_check(iface) == _TRUE) {
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if (mlmeext->cur_wireless_mode >= cur_wireless_mode)
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cur_wireless_mode = mlmeext->cur_wireless_mode;
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bassocaed = _TRUE;
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}
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}
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if (bassocaed)
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#endif
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rtw_set_usb_agg_by_mode(padapter, cur_wireless_mode);
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#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
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} else {
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rtw_set_usb_agg_by_mode(padapter, cur_wireless_mode);
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#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */
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}
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#endif
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}
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@ -10253,9 +10184,6 @@ void rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_coun
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rtw_warn_on(1);
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return;
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}
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if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter))
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phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/
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phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x3);
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mac_cck_ok = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
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phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x0);
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@ -10263,12 +10191,6 @@ void rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_coun
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phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x6);
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mac_ht_ok = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
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mac_vht_ok = 0;
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if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
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phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x0);
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phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x1);
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mac_vht_ok = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]*/
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phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/
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}
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phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x4);
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mac_cck_err = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
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@ -10277,12 +10199,6 @@ void rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_coun
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phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x7);
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mac_ht_err = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
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mac_vht_err = 0;
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if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
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phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x1);
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phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x1);
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mac_vht_err = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]*/
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phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/
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}
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|
||||
phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x5);
|
||||
mac_cck_fa = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
|
||||
|
|
@ -10304,13 +10220,6 @@ void rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_coun
|
|||
}
|
||||
void rtw_reset_mac_rx_counters(_adapter *padapter)
|
||||
{
|
||||
|
||||
/* If no packet rx, MaxRx clock be gating ,BIT_DISGCLK bit19 set 1 for fix*/
|
||||
if (IS_HARDWARE_TYPE_8703B(padapter) ||
|
||||
IS_HARDWARE_TYPE_8723D(padapter) ||
|
||||
IS_HARDWARE_TYPE_8188F(padapter))
|
||||
phy_set_mac_reg(padapter, REG_RCR, BIT19, 0x1);
|
||||
|
||||
/* reset mac counter */
|
||||
phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT27, 0x1);
|
||||
phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT27, 0x0);
|
||||
|
|
@ -10323,18 +10232,6 @@ void rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_coun
|
|||
rtw_warn_on(1);
|
||||
return;
|
||||
}
|
||||
if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
|
||||
cckok = phy_query_bb_reg(padapter, 0xF04, 0x3FFF); /* [13:0] */
|
||||
ofdmok = phy_query_bb_reg(padapter, 0xF14, 0x3FFF); /* [13:0] */
|
||||
htok = phy_query_bb_reg(padapter, 0xF10, 0x3FFF); /* [13:0] */
|
||||
vht_ok = phy_query_bb_reg(padapter, 0xF0C, 0x3FFF); /* [13:0] */
|
||||
cckcrc = phy_query_bb_reg(padapter, 0xF04, 0x3FFF0000); /* [29:16] */
|
||||
ofdmcrc = phy_query_bb_reg(padapter, 0xF14, 0x3FFF0000); /* [29:16] */
|
||||
htcrc = phy_query_bb_reg(padapter, 0xF10, 0x3FFF0000); /* [29:16] */
|
||||
vht_err = phy_query_bb_reg(padapter, 0xF0C, 0x3FFF0000); /* [29:16] */
|
||||
CCK_FA = phy_query_bb_reg(padapter, 0xA5C, bMaskLWord);
|
||||
OFDM_FA = phy_query_bb_reg(padapter, 0xF48, bMaskLWord);
|
||||
} else {
|
||||
cckok = phy_query_bb_reg(padapter, 0xF88, bMaskDWord);
|
||||
ofdmok = phy_query_bb_reg(padapter, 0xF94, bMaskLWord);
|
||||
htok = phy_query_bb_reg(padapter, 0xF90, bMaskLWord);
|
||||
|
|
@ -10348,7 +10245,6 @@ void rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_coun
|
|||
phy_query_bb_reg(padapter, 0xDA6, bMaskLWord) + phy_query_bb_reg(padapter, 0xDA8, bMaskLWord);
|
||||
|
||||
CCK_FA = (rtw_read8(padapter, 0xA5B) << 8) | (rtw_read8(padapter, 0xA5C));
|
||||
}
|
||||
|
||||
rx_counter->rx_pkt_ok = cckok + ofdmok + htok + vht_ok;
|
||||
rx_counter->rx_pkt_crc_error = cckcrc + ofdmcrc + htcrc + vht_err;
|
||||
|
|
@ -10359,23 +10255,11 @@ void rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_coun
|
|||
|
||||
void rtw_reset_phy_trx_ok_counters(_adapter *padapter)
|
||||
{
|
||||
if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
|
||||
phy_set_bb_reg(padapter, 0xB58, BIT0, 0x1);
|
||||
phy_set_bb_reg(padapter, 0xB58, BIT0, 0x0);
|
||||
}
|
||||
}
|
||||
|
||||
void rtw_reset_phy_rx_counters(_adapter *padapter)
|
||||
{
|
||||
/* reset phy counter */
|
||||
if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
|
||||
rtw_reset_phy_trx_ok_counters(padapter);
|
||||
|
||||
phy_set_bb_reg(padapter, 0x9A4, BIT17, 0x1);/* reset OFDA FA counter */
|
||||
phy_set_bb_reg(padapter, 0x9A4, BIT17, 0x0);
|
||||
|
||||
phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x0);/* reset CCK FA counter */
|
||||
phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x1);
|
||||
} else {
|
||||
phy_set_bb_reg(padapter, 0xF14, BIT16, 0x1);
|
||||
rtw_msleep_os(10);
|
||||
phy_set_bb_reg(padapter, 0xF14, BIT16, 0x0);
|
||||
|
|
@ -10387,8 +10271,8 @@ void rtw_reset_phy_rx_counters(_adapter *padapter)
|
|||
|
||||
phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x0);/* reset CCK FA counter */
|
||||
phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x1);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef DBG_RX_COUNTER_DUMP
|
||||
void rtw_dump_drv_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter)
|
||||
{
|
||||
|
|
@ -10864,12 +10748,7 @@ void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode)
|
|||
/*enable BCN0 Function for if1*/
|
||||
/*don't enable update TSF0 for if1 (due to TSF update when beacon,probe rsp are received)*/
|
||||
rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT | EN_BCN_FUNCTION | EN_TXBCN_RPT | DIS_BCNQ_SUB));
|
||||
|
||||
if (IS_HARDWARE_TYPE_8821(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter))/* select BCN on port 0 for DualBeacon*/
|
||||
rtw_write8(Adapter, REG_CCK_CHECK, rtw_read8(Adapter, REG_CCK_CHECK) & (~BIT_BCN_PORT_SEL));
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1110,7 +1110,7 @@ static bool rtw_regsty_chk_target_tx_power_valid(_adapter *adapter)
|
|||
if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
|
||||
continue;
|
||||
|
||||
if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
|
||||
if (IS_VHT_RATE_SECTION(rs))
|
||||
continue;
|
||||
|
||||
target = rtw_regsty_get_target_tx_power(adapter, band, path, rs);
|
||||
|
|
@ -1330,7 +1330,7 @@ phy_StoreTxPowerByRateBase(
|
|||
if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
|
||||
continue;
|
||||
|
||||
if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
|
||||
if (IS_VHT_RATE_SECTION(rs))
|
||||
continue;
|
||||
|
||||
if (regsty->target_tx_pwr_valid == _TRUE)
|
||||
|
|
@ -2572,20 +2572,8 @@ phy_set_tx_power_level_by_path(
|
|||
phy_set_tx_power_index_by_rate_section(Adapter, path, channel, OFDM);
|
||||
phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS0_MCS7);
|
||||
|
||||
if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter))
|
||||
phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_1SSMCS0_1SSMCS9);
|
||||
|
||||
if (pHalData->NumTotalRFPath >= 2) {
|
||||
if (pHalData->NumTotalRFPath >= 2)
|
||||
phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS8_MCS15);
|
||||
|
||||
if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter))
|
||||
phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_2SSMCS0_2SSMCS9);
|
||||
|
||||
if (IS_HARDWARE_TYPE_8814A(Adapter)) {
|
||||
phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS16_MCS23);
|
||||
phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_3SSMCS0_3SSMCS9);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -3241,31 +3229,6 @@ PHY_ConvertTxPowerLimitToPowerIndex(
|
|||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(Adapter)) {
|
||||
|
||||
for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
|
||||
|
||||
for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) {
|
||||
|
||||
for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {
|
||||
|
||||
for (rateSection = OFDM; rateSection <= VHT_4SS; ++rateSection) {
|
||||
tempPwrLmt = pHalData->TxPwrLimit_5G[regulation][bw][rateSection][channel][RF_PATH_A];
|
||||
|
||||
if (tempPwrLmt != MAX_POWER_INDEX) {
|
||||
|
||||
for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH; ++rfPath) {
|
||||
base = PHY_GetTxPowerByRateBase(Adapter, BAND_ON_5G, rfPath, rate_section_to_tx_num(rateSection), rateSection);
|
||||
tempValue = tempPwrLmt - base;
|
||||
pHalData->TxPwrLimit_5G[regulation][bw][rateSection][channel][rfPath] = tempValue;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -3448,42 +3411,8 @@ PHY_SetTxPowerIndex(
|
|||
IN u8 Rate
|
||||
)
|
||||
{
|
||||
if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
PHY_SetTxPowerIndex_8814A(pAdapter, PowerIndex, RFPath, Rate);
|
||||
#endif
|
||||
} else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
|
||||
#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
|
||||
PHY_SetTxPowerIndex_8812A(pAdapter, PowerIndex, RFPath, Rate);
|
||||
#endif
|
||||
} else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
|
||||
#if (RTL8723B_SUPPORT == 1)
|
||||
PHY_SetTxPowerIndex_8723B(pAdapter, PowerIndex, RFPath, Rate);
|
||||
#endif
|
||||
} else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
|
||||
#if (RTL8703B_SUPPORT == 1)
|
||||
PHY_SetTxPowerIndex_8703B(pAdapter, PowerIndex, RFPath, Rate);
|
||||
#endif
|
||||
} else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
|
||||
#if (RTL8723D_SUPPORT == 1)
|
||||
PHY_SetTxPowerIndex_8723D(pAdapter, PowerIndex, RFPath, Rate);
|
||||
#endif
|
||||
} else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
|
||||
#if (RTL8192E_SUPPORT == 1)
|
||||
PHY_SetTxPowerIndex_8192E(pAdapter, PowerIndex, RFPath, Rate);
|
||||
#endif
|
||||
} else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
|
||||
#if (RTL8188E_SUPPORT == 1)
|
||||
if (IS_HARDWARE_TYPE_8188E(pAdapter))
|
||||
PHY_SetTxPowerIndex_8188E(pAdapter, PowerIndex, RFPath, Rate);
|
||||
#endif
|
||||
} else if (IS_HARDWARE_TYPE_8188F(pAdapter)) {
|
||||
#if (RTL8188F_SUPPORT == 1)
|
||||
PHY_SetTxPowerIndex_8188F(pAdapter, PowerIndex, RFPath, Rate);
|
||||
#endif
|
||||
} else if (IS_HARDWARE_TYPE_8822B(pAdapter))
|
||||
rtw_hal_set_tx_power_index(pAdapter, PowerIndex, RFPath, Rate);
|
||||
else if (IS_HARDWARE_TYPE_8821C(pAdapter))
|
||||
rtw_hal_set_tx_power_index(pAdapter, PowerIndex, RFPath, Rate);
|
||||
}
|
||||
|
||||
void dump_tx_power_idx_title(void *sel, _adapter *adapter)
|
||||
|
|
@ -3526,7 +3455,7 @@ void dump_tx_power_idx_by_path_rs(void *sel, _adapter *adapter, u8 rfpath, u8 rs
|
|||
if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
|
||||
return;
|
||||
|
||||
if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
|
||||
if (IS_VHT_RATE_SECTION(rs))
|
||||
return;
|
||||
|
||||
for (i = 0; i < rates_by_sections[rs].rate_num; i++) {
|
||||
|
|
@ -3739,7 +3668,7 @@ void dump_target_tx_power(void *sel, _adapter *adapter)
|
|||
if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
|
||||
continue;
|
||||
|
||||
if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
|
||||
if (IS_VHT_RATE_SECTION(rs))
|
||||
continue;
|
||||
|
||||
target = PHY_GetTxPowerByRateBase(adapter, band, path, rate_section_to_tx_num(rs), rs);
|
||||
|
|
@ -3783,12 +3712,9 @@ void dump_tx_power_by_rate(void *sel, _adapter *adapter)
|
|||
if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
|
||||
continue;
|
||||
|
||||
if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
|
||||
if (IS_VHT_RATE_SECTION(rs))
|
||||
continue;
|
||||
|
||||
if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
|
||||
max_rate_num = 10;
|
||||
else
|
||||
max_rate_num = 8;
|
||||
rate_num = rate_section_rate_num(rs);
|
||||
base = PHY_GetTxPowerByRateBase(adapter, band, path, tx_num, rs);
|
||||
|
|
@ -3830,9 +3756,6 @@ void dump_tx_power_limit(void *sel, _adapter *adapter)
|
|||
int bw, band, ch_num, rs, i, path;
|
||||
u8 ch, n, rd, rfpath_num;
|
||||
|
||||
if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
|
||||
RTW_PRINT_SEL(sel, "tx_pwr_lmt_5g_20_40_ref:0x%02x\n", hal_data->tx_pwr_lmt_5g_20_40_ref);
|
||||
|
||||
for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
|
||||
if (!hal_is_band_support(adapter, band))
|
||||
continue;
|
||||
|
|
@ -3870,7 +3793,7 @@ void dump_tx_power_limit(void *sel, _adapter *adapter)
|
|||
if (rate_section_to_tx_num(rs) >= hal_spec->tx_nss_num)
|
||||
continue;
|
||||
|
||||
if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
|
||||
if (IS_VHT_RATE_SECTION(rs))
|
||||
continue;
|
||||
|
||||
/* by pass 5G 20M, 40M pure reference */
|
||||
|
|
|
|||
|
|
@ -1247,20 +1247,6 @@ u8 rtw_hal_ops_check(_adapter *padapter)
|
|||
ret = _FAIL;
|
||||
}
|
||||
|
||||
if ((IS_HARDWARE_TYPE_8814A(padapter)
|
||||
|| IS_HARDWARE_TYPE_8822BU(padapter) || IS_HARDWARE_TYPE_8822BS(padapter))
|
||||
&& NULL == padapter->hal_func.fw_correct_bcn) {
|
||||
rtw_hal_error_msg("fw_correct_bcn");
|
||||
ret = _FAIL;
|
||||
}
|
||||
|
||||
if (IS_HARDWARE_TYPE_8822B(padapter) || IS_HARDWARE_TYPE_8821C(padapter)) {
|
||||
if (!padapter->hal_func.set_tx_power_index_handler) {
|
||||
rtw_hal_error_msg("set_tx_power_index_handler");
|
||||
ret = _FAIL;
|
||||
}
|
||||
}
|
||||
|
||||
if (!padapter->hal_func.get_tx_power_index_handler) {
|
||||
rtw_hal_error_msg("get_tx_power_index_handler");
|
||||
ret = _FAIL;
|
||||
|
|
|
|||
238
hal/hal_mp.c
238
hal/hal_mp.c
|
|
@ -58,27 +58,7 @@ void hal_mpt_SwitchRfSetting(PADAPTER pAdapter)
|
|||
ULONG ulbandwidth = pMptCtx->MptBandWidth;
|
||||
|
||||
/* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/
|
||||
if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&
|
||||
(ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) {
|
||||
pMptCtx->backup0x52_RF_A = (u1Byte)phy_query_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0);
|
||||
pMptCtx->backup0x52_RF_B = (u1Byte)phy_query_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0);
|
||||
|
||||
if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) {
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB);
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB);
|
||||
} else {
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xD);
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xD);
|
||||
}
|
||||
} else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/
|
||||
if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) {
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
|
||||
} else {
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
|
||||
}
|
||||
} else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
|
||||
if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A);
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B);
|
||||
}
|
||||
|
|
@ -126,10 +106,6 @@ void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
|
|||
ULONG ulRateIdx = pMptCtx->mpt_rate_index;
|
||||
u1Byte DataRate = 0xFF;
|
||||
|
||||
/* Do not modify CCK TX filter parameters for 8822B*/
|
||||
if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) || IS_HARDWARE_TYPE_8723D(Adapter))
|
||||
return;
|
||||
|
||||
DataRate = mpt_to_mgnt_rate(ulRateIdx);
|
||||
|
||||
if (u1Channel == 14 && IS_CCK_RATE(DataRate))
|
||||
|
|
@ -137,94 +113,6 @@ void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
|
|||
else
|
||||
pHalData->bCCKinCH14 = FALSE;
|
||||
|
||||
if (IS_HARDWARE_TYPE_8703B(Adapter)) {
|
||||
if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) {
|
||||
/* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */
|
||||
phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0);
|
||||
phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskLWord, 0);
|
||||
|
||||
} else {
|
||||
/* Normal setting for 8703B, just recover to the default setting. */
|
||||
/* This hardcore values reference from the parameter which BB team gave. */
|
||||
for (i = 0 ; i < 2 ; ++i)
|
||||
phy_set_bb_reg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);
|
||||
|
||||
}
|
||||
} else if (IS_HARDWARE_TYPE_8723D(Adapter)) {
|
||||
/* 2.4G CCK TX DFIR */
|
||||
/* 2016.01.20 Suggest from RS BB mingzhi*/
|
||||
if ((u1Channel == 14)) {
|
||||
phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C);
|
||||
phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000000);
|
||||
phy_set_bb_reg(Adapter, 0xAAC, bMaskDWord, 0x00003667);
|
||||
} else {
|
||||
for (i = 0 ; i < 3 ; ++i) {
|
||||
phy_set_bb_reg(Adapter,
|
||||
pHalData->RegForRecover[i].offset,
|
||||
bMaskDWord,
|
||||
pHalData->RegForRecover[i].value);
|
||||
}
|
||||
}
|
||||
} else if (IS_HARDWARE_TYPE_8188F(Adapter)) {
|
||||
/* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
|
||||
CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
|
||||
CCKSwingIndex = 20; /* default index */
|
||||
|
||||
if (!pHalData->bCCKinCH14) {
|
||||
/* Readback the current bb cck swing value and compare with the table to */
|
||||
/* get the current swing index */
|
||||
for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
|
||||
if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13_88f[i][0]) &&
|
||||
(((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13_88f[i][1])) {
|
||||
CCKSwingIndex = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][0]);
|
||||
write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][1]);
|
||||
write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][2]);
|
||||
write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][3]);
|
||||
write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][4]);
|
||||
write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][5]);
|
||||
write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][6]);
|
||||
write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][7]);
|
||||
write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][8]);
|
||||
write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][9]);
|
||||
write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][10]);
|
||||
write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][11]);
|
||||
write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][12]);
|
||||
write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][13]);
|
||||
write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][14]);
|
||||
write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][15]);
|
||||
RTW_INFO("%s , cck_swing_table_ch1_ch13_88f[%d]\n", __func__, CCKSwingIndex);
|
||||
} else {
|
||||
for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
|
||||
if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14_88f[i][0]) &&
|
||||
(((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14_88f[i][1])) {
|
||||
CCKSwingIndex = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][0]);
|
||||
write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][1]);
|
||||
write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][2]);
|
||||
write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][3]);
|
||||
write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][4]);
|
||||
write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][5]);
|
||||
write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][6]);
|
||||
write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][7]);
|
||||
write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][8]);
|
||||
write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][9]);
|
||||
write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][10]);
|
||||
write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][11]);
|
||||
write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][12]);
|
||||
write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][13]);
|
||||
write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][14]);
|
||||
write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][15]);
|
||||
RTW_INFO("%s , cck_swing_table_ch14_88f[%d]\n", __func__, CCKSwingIndex);
|
||||
}
|
||||
} else {
|
||||
|
||||
/* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
|
||||
CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
|
||||
|
||||
|
|
@ -284,8 +172,6 @@ void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
|
|||
write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
|
||||
write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
|
||||
write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void hal_mpt_SetChannel(PADAPTER pAdapter)
|
||||
|
|
@ -396,11 +282,6 @@ mpt_SetTxPower(
|
|||
u1Byte path = 0 , i = 0, MaxRate = MGN_6M;
|
||||
u1Byte StartPath = ODM_RF_PATH_A, EndPath = ODM_RF_PATH_B;
|
||||
|
||||
if (IS_HARDWARE_TYPE_8814A(pAdapter))
|
||||
EndPath = ODM_RF_PATH_D;
|
||||
else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter))
|
||||
EndPath = ODM_RF_PATH_A;
|
||||
|
||||
switch (Rate) {
|
||||
case MPT_CCK: {
|
||||
u1Byte rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
|
||||
|
|
@ -486,11 +367,7 @@ void hal_mpt_SetTxPower(PADAPTER pAdapter)
|
|||
struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv;
|
||||
|
||||
if (pHalData->rf_chip < RF_TYPE_MAX) {
|
||||
if (IS_HARDWARE_TYPE_8188E(pAdapter) ||
|
||||
IS_HARDWARE_TYPE_8723B(pAdapter) ||
|
||||
IS_HARDWARE_TYPE_8192E(pAdapter) ||
|
||||
IS_HARDWARE_TYPE_8703B(pAdapter) ||
|
||||
IS_HARDWARE_TYPE_8188F(pAdapter)) {
|
||||
if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
|
||||
u8 path = (pHalData->antenna_tx_path == ANTENNA_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B);
|
||||
|
||||
RTW_INFO("===> MPT_ProSetTxPower: Old\n");
|
||||
|
|
@ -504,7 +381,6 @@ void hal_mpt_SetTxPower(PADAPTER pAdapter)
|
|||
mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);
|
||||
mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel);
|
||||
mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);
|
||||
|
||||
}
|
||||
} else
|
||||
RTW_INFO("RFChipID < RF_TYPE_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
|
||||
|
|
@ -558,7 +434,6 @@ static void mpt_SetRFPath_819X(PADAPTER pAdapter)
|
|||
p_cck_txrx->r_ccktx_enable = 0x8;
|
||||
chgTx = 1;
|
||||
/*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
|
||||
/*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
|
||||
{
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
|
||||
|
|
@ -585,7 +460,6 @@ static void mpt_SetRFPath_819X(PADAPTER pAdapter)
|
|||
p_cck_txrx->r_ccktx_enable = 0x4;
|
||||
chgTx = 1;
|
||||
/*/ From SD3 Willis suggestion !!! Set RF A as standby*/
|
||||
/*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
|
||||
{
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
|
||||
|
|
@ -612,7 +486,6 @@ static void mpt_SetRFPath_819X(PADAPTER pAdapter)
|
|||
p_cck_txrx->r_ccktx_enable = 0xC;
|
||||
chgTx = 1;
|
||||
/*/ From SD3Willis suggestion !!! Set RF B as standby*/
|
||||
/*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
|
||||
{
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
|
||||
|
|
@ -672,10 +545,6 @@ static void mpt_SetRFPath_819X(PADAPTER pAdapter)
|
|||
phy_set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /*/OFDM Tx*/
|
||||
phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
|
||||
phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
|
||||
if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
|
||||
phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
|
||||
phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
|
||||
}
|
||||
phy_set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/
|
||||
break;
|
||||
|
||||
|
|
@ -822,89 +691,16 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
|
|||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
|
||||
} else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
|
||||
/*/Set MAC REG 88C: Prevent SingleTone Fail*/
|
||||
phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0xF);
|
||||
phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO disabled*/
|
||||
phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
|
||||
} else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
|
||||
if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) {
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/
|
||||
} else {
|
||||
/*/ S0/S1 both use PATH A to configure*/
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/
|
||||
}
|
||||
} else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
|
||||
if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) {
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */
|
||||
}
|
||||
} else if (IS_HARDWARE_TYPE_8188F(pAdapter)) {
|
||||
/*Set BB REG 88C: Prevent SingleTone Fail*/
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF);
|
||||
phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1);
|
||||
phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2);
|
||||
|
||||
} else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
|
||||
if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) {
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x0);
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, BIT0, 0x1);
|
||||
} else {/* S0/S1 both use PATH A to configure */
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x0);
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x63, BIT0, 0x1);
|
||||
}
|
||||
} else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) {
|
||||
} else { /*/ Turn On SingleTone and turn off the other test modes.*/
|
||||
phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone);
|
||||
}
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
|
||||
} else {/*/ Stop Single Ton e.*/
|
||||
|
||||
if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, lna_low_gain_3, bRFRegOffsetMask, regRF);
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
|
||||
} else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
|
||||
phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/
|
||||
phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0);/*/ RF LO disabled */
|
||||
/*/ RESTORE MAC REG 88C: Enable RF Functions*/
|
||||
phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0x0);
|
||||
} else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
|
||||
if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) {
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/
|
||||
} else {
|
||||
/*/ S0/S1 both use PATH A to configure*/
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/
|
||||
}
|
||||
} else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
|
||||
if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) {
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */
|
||||
}
|
||||
} else if (IS_HARDWARE_TYPE_8188F(pAdapter)) {
|
||||
phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /*Tx mode*/
|
||||
phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0); /*RF LO disabled*/
|
||||
/*Set BB REG 88C: Prevent SingleTone Fail*/
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc);
|
||||
} else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
|
||||
if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) {
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x1);
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, BIT0, 0x0);
|
||||
} else { /* S0/S1 both use PATH A to configure */
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x1);
|
||||
phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x63, BIT0, 0x0);
|
||||
}
|
||||
} else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) {
|
||||
}
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
|
||||
|
|
@ -925,9 +721,6 @@ void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
|
|||
write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
|
||||
|
||||
/*/Turn Off All Test Mode*/
|
||||
if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
|
||||
phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/
|
||||
else
|
||||
phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
|
||||
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/
|
||||
|
|
@ -993,15 +786,6 @@ static VOID mpt_StopCckContTx(
|
|||
phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
|
||||
phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
|
||||
|
||||
if (!IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
|
||||
phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 2b00*/
|
||||
phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
|
||||
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 0);
|
||||
phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 0);
|
||||
}
|
||||
|
||||
/*BB Reset*/
|
||||
phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
|
||||
phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
|
||||
|
|
@ -1024,18 +808,10 @@ static VOID mpt_StopOfdmContTx(
|
|||
pMptCtx->bCckContTx = FALSE;
|
||||
pMptCtx->bOfdmContTx = FALSE;
|
||||
|
||||
if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter))
|
||||
phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
|
||||
else
|
||||
phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
|
||||
|
||||
rtw_mdelay_os(10);
|
||||
|
||||
if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
|
||||
phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 0*/
|
||||
phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
|
||||
}
|
||||
|
||||
/*BB Reset*/
|
||||
phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
|
||||
phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
|
||||
|
|
@ -1058,9 +834,6 @@ static VOID mpt_StartCckContTx(
|
|||
phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/
|
||||
|
||||
/*Turn Off All Test Mode*/
|
||||
if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
|
||||
phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
|
||||
else
|
||||
phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
|
||||
|
||||
cckrate = pAdapter->mppriv.rateidx;
|
||||
|
|
@ -1070,13 +843,11 @@ static VOID mpt_StartCckContTx(
|
|||
phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*transmit mode*/
|
||||
phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
|
||||
|
||||
if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) {
|
||||
phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 11 force cck rxiq = 0*/
|
||||
phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 1);
|
||||
phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 1);
|
||||
}
|
||||
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
|
|
@ -1104,15 +875,10 @@ static VOID mpt_StartOfdmContTx(
|
|||
/* 3. turn on scramble setting*/
|
||||
phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
|
||||
|
||||
if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
|
||||
phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 2b'11*/
|
||||
phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/
|
||||
}
|
||||
|
||||
/* 4. Turn On Continue Tx and turn off the other test modes.*/
|
||||
if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter))
|
||||
phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx);
|
||||
else
|
||||
phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);
|
||||
|
||||
phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
|
|
|
|||
|
|
@ -1077,17 +1077,12 @@ SwLedBlink9(
|
|||
if (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS)
|
||||
SwLedOff(Adapter, pLed);
|
||||
else {
|
||||
if (IS_HARDWARE_TYPE_8812AU(Adapter)) {
|
||||
pLed->BlinkingLedState = RTW_LED_ON;
|
||||
pLed->CurrLedState = LED_BLINK_ALWAYS_ON;
|
||||
} else {
|
||||
pLed->bLedNoLinkBlinkInProgress = _TRUE;
|
||||
pLed->CurrLedState = LED_BLINK_SLOWLY;
|
||||
if (pLed->bLedOn)
|
||||
pLed->BlinkingLedState = RTW_LED_OFF;
|
||||
else
|
||||
pLed->BlinkingLedState = RTW_LED_ON;
|
||||
}
|
||||
_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
|
||||
}
|
||||
pLed->bLedBlinkInProgress = _FALSE;
|
||||
|
|
@ -1095,14 +1090,10 @@ SwLedBlink9(
|
|||
if (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) {
|
||||
SwLedOff(Adapter, pLed);
|
||||
} else {
|
||||
if (IS_HARDWARE_TYPE_8812AU(Adapter))
|
||||
pLed->BlinkingLedState = RTW_LED_ON;
|
||||
else {
|
||||
if (pLed->bLedOn)
|
||||
pLed->BlinkingLedState = RTW_LED_OFF;
|
||||
else
|
||||
pLed->BlinkingLedState = RTW_LED_ON;
|
||||
}
|
||||
_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
|
||||
}
|
||||
}
|
||||
|
|
@ -1277,17 +1268,12 @@ SwLedBlink10(
|
|||
if (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS)
|
||||
SwLedOff(Adapter, pLed);
|
||||
else {
|
||||
if (IS_HARDWARE_TYPE_8812AU(Adapter)) {
|
||||
pLed->BlinkingLedState = RTW_LED_ON;
|
||||
pLed->CurrLedState = LED_BLINK_ALWAYS_ON;
|
||||
} else {
|
||||
pLed->bLedNoLinkBlinkInProgress = _TRUE;
|
||||
pLed->CurrLedState = LED_BLINK_SLOWLY;
|
||||
if (pLed->bLedOn)
|
||||
pLed->BlinkingLedState = RTW_LED_OFF;
|
||||
else
|
||||
pLed->BlinkingLedState = RTW_LED_ON;
|
||||
}
|
||||
_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
|
||||
}
|
||||
pLed->bLedBlinkInProgress = _FALSE;
|
||||
|
|
@ -1295,14 +1281,10 @@ SwLedBlink10(
|
|||
if (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) {
|
||||
SwLedOff(Adapter, pLed);
|
||||
} else {
|
||||
if (IS_HARDWARE_TYPE_8812AU(Adapter))
|
||||
pLed->BlinkingLedState = RTW_LED_ON;
|
||||
else {
|
||||
if (pLed->bLedOn)
|
||||
pLed->BlinkingLedState = RTW_LED_OFF;
|
||||
else
|
||||
pLed->BlinkingLedState = RTW_LED_ON;
|
||||
}
|
||||
_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
|
||||
}
|
||||
}
|
||||
|
|
@ -1576,15 +1558,9 @@ SwLedBlink14(
|
|||
else {
|
||||
if (pLed->bLedOn) {
|
||||
pLed->BlinkingLedState = RTW_LED_OFF;
|
||||
if (IS_HARDWARE_TYPE_8812AU(Adapter))
|
||||
_set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
|
||||
else
|
||||
_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
|
||||
} else {
|
||||
pLed->BlinkingLedState = RTW_LED_ON;
|
||||
if (IS_HARDWARE_TYPE_8812AU(Adapter))
|
||||
_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
|
||||
else
|
||||
_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
|
||||
}
|
||||
}
|
||||
|
|
@ -3175,24 +3151,11 @@ SwLedControlMode9(
|
|||
}
|
||||
|
||||
pLed->bLedNoLinkBlinkInProgress = _TRUE;
|
||||
if (IS_HARDWARE_TYPE_8812AU(Adapter)) {
|
||||
if (LedAction == LED_CTL_LINK) {
|
||||
pLed->BlinkingLedState = RTW_LED_ON;
|
||||
pLed->CurrLedState = LED_BLINK_SLOWLY;
|
||||
} else {
|
||||
pLed->CurrLedState = LED_BLINK_SLOWLY;
|
||||
if (pLed->bLedOn)
|
||||
pLed->BlinkingLedState = RTW_LED_OFF;
|
||||
else
|
||||
pLed->BlinkingLedState = RTW_LED_ON;
|
||||
}
|
||||
} else {
|
||||
pLed->CurrLedState = LED_BLINK_SLOWLY;
|
||||
if (pLed->bLedOn)
|
||||
pLed->BlinkingLedState = RTW_LED_OFF;
|
||||
else
|
||||
pLed->BlinkingLedState = RTW_LED_ON;
|
||||
}
|
||||
_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
|
||||
}
|
||||
|
||||
|
|
@ -3940,10 +3903,7 @@ SwLedControlMode14(
|
|||
|
||||
case LED_CTL_LINK:
|
||||
case LED_CTL_NO_LINK:
|
||||
if (IS_HARDWARE_TYPE_8812AU(Adapter))
|
||||
SwLedOn(Adapter, pLed);
|
||||
break;
|
||||
|
||||
case LED_CTL_TX:
|
||||
case LED_CTL_RX:
|
||||
if (pLed->bLedBlinkInProgress == _FALSE) {
|
||||
|
|
@ -3952,15 +3912,9 @@ SwLedControlMode14(
|
|||
pLed->BlinkTimes = 2;
|
||||
if (pLed->bLedOn) {
|
||||
pLed->BlinkingLedState = RTW_LED_OFF;
|
||||
if (IS_HARDWARE_TYPE_8812AU(Adapter))
|
||||
_set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
|
||||
else
|
||||
_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
|
||||
} else {
|
||||
pLed->BlinkingLedState = RTW_LED_ON;
|
||||
if (IS_HARDWARE_TYPE_8812AU(Adapter))
|
||||
_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
|
||||
else
|
||||
_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -546,14 +546,6 @@ odm_txpowertracking_callback_thermal_meter(
|
|||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********End Xtal Tracking**********\n"));
|
||||
}
|
||||
if (!IS_HARDWARE_TYPE_8723B(adapter)) {
|
||||
/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
|
||||
if (delta_IQK >= c.threshold_iqk) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk));
|
||||
if (!p_rf_calibrate_info->is_iqk_in_progress)
|
||||
(*c.do_iqk)(p_dm_odm, delta_IQK, thermal_value, 8);
|
||||
}
|
||||
}
|
||||
if (p_rf_calibrate_info->dpk_thermal[ODM_RF_PATH_A] != 0) {
|
||||
if (diff_DPK[ODM_RF_PATH_A] >= c.threshold_dpk) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
|
||||
|
|
@ -629,9 +621,6 @@ static void odm_iq_calibrate(struct PHY_DM_STRUCT *p_dm_odm)
|
|||
{
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
|
||||
if (IS_HARDWARE_TYPE_8812AU(adapter))
|
||||
return;
|
||||
|
||||
if (p_dm_odm->is_linked) {
|
||||
if ((*p_dm_odm->p_channel != p_dm_odm->pre_channel) && (!*p_dm_odm->p_is_scan_in_process)) {
|
||||
p_dm_odm->pre_channel = *p_dm_odm->p_channel;
|
||||
|
|
@ -640,11 +629,6 @@ static void odm_iq_calibrate(struct PHY_DM_STRUCT *p_dm_odm)
|
|||
|
||||
if (p_dm_odm->linked_interval < 3)
|
||||
p_dm_odm->linked_interval++;
|
||||
|
||||
if (p_dm_odm->linked_interval == 2) {
|
||||
if (IS_HARDWARE_TYPE_8814A(adapter)) {
|
||||
}
|
||||
}
|
||||
} else
|
||||
p_dm_odm->linked_interval = 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -629,11 +629,7 @@ odm_txpowertracking_check_ce(
|
|||
|
||||
if (!p_dm_odm->rf_calibrate_info.tm_trigger) {
|
||||
|
||||
if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8192E(adapter)
|
||||
|| IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8814A(adapter)
|
||||
|| IS_HARDWARE_TYPE_8703B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8822B(adapter)
|
||||
|| IS_HARDWARE_TYPE_8821C(adapter)
|
||||
)
|
||||
if (IS_HARDWARE_TYPE_8188E(adapter))
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_T_METER_NEW, (BIT(17) | BIT(16)), 0x03);
|
||||
else
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_T_METER_OLD, RFREGOFFSETMASK, 0x60);
|
||||
|
|
|
|||
|
|
@ -474,105 +474,8 @@ typedef enum _HARDWARE_TYPE {
|
|||
/*
|
||||
* RTL8188E Series
|
||||
* */
|
||||
#define IS_HARDWARE_TYPE_8188EE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188EE)
|
||||
#define IS_HARDWARE_TYPE_8188EU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188EU)
|
||||
#define IS_HARDWARE_TYPE_8188ES(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188ES)
|
||||
#define IS_HARDWARE_TYPE_8188E(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8188EE(_Adapter) || IS_HARDWARE_TYPE_8188EU(_Adapter) || IS_HARDWARE_TYPE_8188ES(_Adapter))
|
||||
|
||||
/* RTL8812 Series */
|
||||
#define IS_HARDWARE_TYPE_8812E(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8812E)
|
||||
#define IS_HARDWARE_TYPE_8812AU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8812AU)
|
||||
#define IS_HARDWARE_TYPE_8812(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8812E(_Adapter) || IS_HARDWARE_TYPE_8812AU(_Adapter))
|
||||
|
||||
/* RTL8821 Series */
|
||||
#define IS_HARDWARE_TYPE_8821E(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821E)
|
||||
#define IS_HARDWARE_TYPE_8811AU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8811AU)
|
||||
#define IS_HARDWARE_TYPE_8821U(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821U || \
|
||||
rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8811AU)
|
||||
#define IS_HARDWARE_TYPE_8821S(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821S)
|
||||
#define IS_HARDWARE_TYPE_8821(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8821E(_Adapter) || IS_HARDWARE_TYPE_8821U(_Adapter) || IS_HARDWARE_TYPE_8821S(_Adapter))
|
||||
|
||||
#define IS_HARDWARE_TYPE_JAGUAR(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8812(_Adapter) || IS_HARDWARE_TYPE_8821(_Adapter))
|
||||
|
||||
/* RTL8192E Series */
|
||||
#define IS_HARDWARE_TYPE_8192EE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192EE)
|
||||
#define IS_HARDWARE_TYPE_8192EU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192EU)
|
||||
#define IS_HARDWARE_TYPE_8192ES(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192ES)
|
||||
|
||||
#define IS_HARDWARE_TYPE_8192E(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8192EE(_Adapter) || IS_HARDWARE_TYPE_8192EU(_Adapter) || IS_HARDWARE_TYPE_8192ES(_Adapter))
|
||||
|
||||
#define IS_HARDWARE_TYPE_8723BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BE)
|
||||
#define IS_HARDWARE_TYPE_8723BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BU)
|
||||
#define IS_HARDWARE_TYPE_8723BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BS)
|
||||
|
||||
#define IS_HARDWARE_TYPE_8723B(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8723BE(_Adapter) || IS_HARDWARE_TYPE_8723BU(_Adapter) || IS_HARDWARE_TYPE_8723BS(_Adapter))
|
||||
|
||||
/* RTL8814A Series */
|
||||
#define IS_HARDWARE_TYPE_8814AE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AE)
|
||||
#define IS_HARDWARE_TYPE_8814AU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AU)
|
||||
#define IS_HARDWARE_TYPE_8814AS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AS)
|
||||
|
||||
#define IS_HARDWARE_TYPE_8814A(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8814AE(_Adapter) || IS_HARDWARE_TYPE_8814AU(_Adapter) || IS_HARDWARE_TYPE_8814AS(_Adapter))
|
||||
|
||||
/* RTL8703B Series */
|
||||
#define IS_HARDWARE_TYPE_8703BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BE)
|
||||
#define IS_HARDWARE_TYPE_8703BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BS)
|
||||
#define IS_HARDWARE_TYPE_8703BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BU)
|
||||
#define IS_HARDWARE_TYPE_8703B(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8703BE(_Adapter) || IS_HARDWARE_TYPE_8703BU(_Adapter) || IS_HARDWARE_TYPE_8703BS(_Adapter))
|
||||
|
||||
/* RTL8723D Series */
|
||||
#define IS_HARDWARE_TYPE_8723DE(_Adapter)\
|
||||
(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DE)
|
||||
#define IS_HARDWARE_TYPE_8723DS(_Adapter)\
|
||||
(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DS)
|
||||
#define IS_HARDWARE_TYPE_8723DU(_Adapter)\
|
||||
(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DU)
|
||||
#define IS_HARDWARE_TYPE_8723D(_Adapter)\
|
||||
(IS_HARDWARE_TYPE_8723DE(_Adapter) || \
|
||||
IS_HARDWARE_TYPE_8723DU(_Adapter) || \
|
||||
IS_HARDWARE_TYPE_8723DS(_Adapter))
|
||||
|
||||
/* RTL8188F Series */
|
||||
#define IS_HARDWARE_TYPE_8188FE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FE)
|
||||
#define IS_HARDWARE_TYPE_8188FS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FS)
|
||||
#define IS_HARDWARE_TYPE_8188FU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FU)
|
||||
#define IS_HARDWARE_TYPE_8188F(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8188FE(_Adapter) || IS_HARDWARE_TYPE_8188FU(_Adapter) || IS_HARDWARE_TYPE_8188FS(_Adapter))
|
||||
|
||||
#define IS_HARDWARE_TYPE_8821BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BE)
|
||||
#define IS_HARDWARE_TYPE_8821BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BU)
|
||||
#define IS_HARDWARE_TYPE_8821BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BS)
|
||||
|
||||
#define IS_HARDWARE_TYPE_8821B(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8821BE(_Adapter) || IS_HARDWARE_TYPE_8821BU(_Adapter) || IS_HARDWARE_TYPE_8821BS(_Adapter))
|
||||
|
||||
#define IS_HARDWARE_TYPE_8822BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BE)
|
||||
#define IS_HARDWARE_TYPE_8822BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BU)
|
||||
#define IS_HARDWARE_TYPE_8822BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BS)
|
||||
#define IS_HARDWARE_TYPE_8822B(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8822BE(_Adapter) || IS_HARDWARE_TYPE_8822BU(_Adapter) || IS_HARDWARE_TYPE_8822BS(_Adapter))
|
||||
|
||||
#define IS_HARDWARE_TYPE_8821CE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CE)
|
||||
#define IS_HARDWARE_TYPE_8821CU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CU)
|
||||
#define IS_HARDWARE_TYPE_8821CS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CS)
|
||||
#define IS_HARDWARE_TYPE_8821C(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8821CE(_Adapter) || IS_HARDWARE_TYPE_8821CU(_Adapter) || IS_HARDWARE_TYPE_8821CS(_Adapter))
|
||||
|
||||
#define IS_HARDWARE_TYPE_JAGUAR2(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8814A(_Adapter) || IS_HARDWARE_TYPE_8821B(_Adapter) || IS_HARDWARE_TYPE_8822B(_Adapter) || IS_HARDWARE_TYPE_8821C(_Adapter))
|
||||
|
||||
#define IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_JAGUAR(_Adapter) || IS_HARDWARE_TYPE_JAGUAR2(_Adapter))
|
||||
|
||||
|
||||
#define IS_HARDWARE_TYPE_8188E(_Adapter) IS_HARDWARE_TYPE_8188EU(_Adapter)
|
||||
|
||||
typedef enum _wowlan_subcode {
|
||||
WOWLAN_ENABLE = 0,
|
||||
|
|
|
|||
Loading…
Reference in a new issue