diff --git a/include/Hal8192EPhyCfg.h b/include/Hal8192EPhyCfg.h deleted file mode 100644 index 17dd982..0000000 --- a/include/Hal8192EPhyCfg.h +++ /dev/null @@ -1,153 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_HAL8192EPHYCFG_H__ -#define __INC_HAL8192EPHYCFG_H__ - - -/*--------------------------Define Parameters-------------------------------*/ -#define LOOP_LIMIT 5 -#define MAX_STALL_TIME 50 /* us */ -#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */ -#define MAX_TXPWR_IDX_NMODE_92S 63 -#define Reset_Cnt_Limit 3 - -#ifdef CONFIG_PCI_HCI - #define MAX_AGGR_NUM 0x0B -#else - #define MAX_AGGR_NUM 0x07 -#endif /* CONFIG_PCI_HCI */ - - -/*--------------------------Define Parameters-------------------------------*/ - -/*------------------------------Define structure----------------------------*/ - -/* BB/RF related */ - -/*------------------------------Define structure----------------------------*/ - - -/*------------------------Export global variable----------------------------*/ -/*------------------------Export global variable----------------------------*/ - - -/*------------------------Export Marco Definition---------------------------*/ -/*------------------------Export Marco Definition---------------------------*/ - - -/*--------------------------Exported Function prototype---------------------*/ -/* - * BB and RF register read/write - * */ -u32 PHY_QueryBBReg8192E(IN PADAPTER Adapter, - IN u32 RegAddr, - IN u32 BitMask); -void PHY_SetBBReg8192E(IN PADAPTER Adapter, - IN u32 RegAddr, - IN u32 BitMask, - IN u32 Data); -u32 PHY_QueryRFReg8192E(IN PADAPTER Adapter, - IN u8 eRFPath, - IN u32 RegAddr, - IN u32 BitMask); -void PHY_SetRFReg8192E(IN PADAPTER Adapter, - IN u8 eRFPath, - IN u32 RegAddr, - IN u32 BitMask, - IN u32 Data); - -/* - * Initialization related function - * - * MAC/BB/RF HAL config */ -int PHY_MACConfig8192E(IN PADAPTER Adapter); -int PHY_BBConfig8192E(IN PADAPTER Adapter); -int PHY_RFConfig8192E(IN PADAPTER Adapter); - -/* RF config */ - - -/* - * BB TX Power R/W - * */ -void PHY_GetTxPowerLevel8192E(IN PADAPTER Adapter, OUT s32 *powerlevel); -void PHY_SetTxPowerLevel8192E(IN PADAPTER Adapter, IN u8 channel); -BOOLEAN PHY_UpdateTxPowerDbm8192E(IN PADAPTER Adapter, IN int powerInDbm); - -VOID -PHY_SetTxPowerIndex_8192E( - IN PADAPTER Adapter, - IN u32 PowerIndex, - IN u8 RFPath, - IN u8 Rate -); - -u8 -PHY_GetTxPowerIndex_8192E( - IN PADAPTER pAdapter, - IN u8 RFPath, - IN u8 Rate, - IN u8 BandWidth, - IN u8 Channel, - struct txpwr_idx_comp *tic -); - -/* - * channel switch related funciton - * */ -VOID -PHY_SetSwChnlBWMode8192E( - IN PADAPTER Adapter, - IN u8 channel, - IN CHANNEL_WIDTH Bandwidth, - IN u8 Offset40, - IN u8 Offset80 -); - -VOID -PHY_SetRFEReg_8192E( - IN PADAPTER Adapter -); - -void -phy_SpurCalibration_8192E( - IN PADAPTER Adapter, - IN enum spur_cal_method method -); -void PHY_SpurCalibration_8192E(IN PADAPTER Adapter); - -#ifdef CONFIG_SPUR_CAL_NBI -void -phy_SpurCalibration_8192E_NBI( - IN PADAPTER Adapter -); -#endif -/* - * BB/MAC/RF other monitor API - * */ - -VOID -phy_set_rf_path_switch_8192e( - IN PADAPTER pAdapter, - IN bool bMain -); - -/*--------------------------Exported Function prototype---------------------*/ -#endif /* __INC_HAL8192CPHYCFG_H */ diff --git a/include/Hal8192EPhyReg.h b/include/Hal8192EPhyReg.h deleted file mode 100644 index cd13c22..0000000 --- a/include/Hal8192EPhyReg.h +++ /dev/null @@ -1,1132 +0,0 @@ -/***************************************************************************** - * Copyright(c) 2008, RealTEK Technology Inc. All Right Reserved. - * - * Module: __INC_HAL8192SPHYREG_H - * - * - * Note: 1. Define PMAC/BB register map - * 2. Define RF register map - * 3. PMAC/BB register bit mask. - * 4. RF reg bit mask. - * 5. Other BB/RF relative definition. - * - * - * Export: Constants, macro, functions(API), global variables(None). - * - * Abbrev: - * - * History: - * Data Who Remark - * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. - * 2. Reorganize code architecture. - * 09/25/2008 MH 1. Add RL6052 register definition - * - *****************************************************************************/ -#ifndef __INC_HAL8192EPHYREG_H -#define __INC_HAL8192EPHYREG_H - - -/*--------------------------Define Parameters-------------------------------*/ - -/* ************************************************************ - * 8192S Regsiter offset definition - * ************************************************************ */ - -/* - * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF - * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF - * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 - * 3. RF register 0x00-2E - * 4. Bit Mask for BB/RF register - * 5. Other defintion for BB/RF R/W - * */ - - -/* - * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF - * 1. Page1(0x100) - * */ -#define rPMAC_Reset 0x100 -#define rPMAC_TxStart 0x104 -#define rPMAC_TxLegacySIG 0x108 -#define rPMAC_TxHTSIG1 0x10c -#define rPMAC_TxHTSIG2 0x110 -#define rPMAC_PHYDebug 0x114 -#define rPMAC_TxPacketNum 0x118 -#define rPMAC_TxIdle 0x11c -#define rPMAC_TxMACHeader0 0x120 -#define rPMAC_TxMACHeader1 0x124 -#define rPMAC_TxMACHeader2 0x128 -#define rPMAC_TxMACHeader3 0x12c -#define rPMAC_TxMACHeader4 0x130 -#define rPMAC_TxMACHeader5 0x134 -#define rPMAC_TxDataType 0x138 -#define rPMAC_TxRandomSeed 0x13c -#define rPMAC_CCKPLCPPreamble 0x140 -#define rPMAC_CCKPLCPHeader 0x144 -#define rPMAC_CCKCRC16 0x148 -#define rPMAC_OFDMRxCRC32OK 0x170 -#define rPMAC_OFDMRxCRC32Er 0x174 -#define rPMAC_OFDMRxParityEr 0x178 -#define rPMAC_OFDMRxCRC8Er 0x17c -#define rPMAC_CCKCRxRC16Er 0x180 -#define rPMAC_CCKCRxRC32Er 0x184 -#define rPMAC_CCKCRxRC32OK 0x188 -#define rPMAC_TxStatus 0x18c - - -/* - * 3. Page8(0x800) - * */ -#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */ - -#define rFPGA0_TxInfo 0x804 /* Status report?? */ -#define rFPGA0_PSDFunction 0x808 - -#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ - -#define rFPGA0_RFTiming1 0x810 /* Useless now */ -#define rFPGA0_RFTiming2 0x814 - -#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ -#define rFPGA0_XA_HSSIParameter2 0x824 -#define rFPGA0_XB_HSSIParameter1 0x828 -#define rFPGA0_XB_HSSIParameter2 0x82c - -#define rFPGA0_XA_LSSIParameter 0x840 -#define rFPGA0_XB_LSSIParameter 0x844 - -#define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ -#define rFPGA0_RFSleepUpParameter 0x854 - -#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ -#define rFPGA0_XCD_SwitchControl 0x85c - -#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ -#define rFPGA0_XB_RFInterfaceOE 0x864 - -#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ -#define rFPGA0_XCD_RFInterfaceSW 0x874 - -#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ -#define rFPGA0_XCD_RFParameter 0x87c - -#define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ -#define rFPGA0_AnalogParameter2 0x884 -#define rFPGA0_AnalogParameter3 0x888 -#define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */ -#define rFPGA0_AnalogParameter4 0x88c - -#define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ -#define rFPGA0_XB_LSSIReadBack 0x8a4 -#define rFPGA0_XC_LSSIReadBack 0x8a8 -#define rFPGA0_XD_LSSIReadBack 0x8ac - -#define rFPGA0_PSDReport 0x8b4 /* Useless now */ -#define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ -#define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ -#define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ /* RF Interface Readback Value */ -#define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ - -/* - * 4. Page9(0x900) - * */ -#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */ - -#define rFPGA1_TxBlock 0x904 /* Useless now */ -#define rFPGA1_DebugSelect 0x908 /* Useless now */ -#define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */ - -/* - * 5. PageA(0xA00) - * - * Set Control channel to upper or lower. These settings are required only for 40MHz */ -#define rCCK0_System 0xa00 - -#define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */ -#define rCCK0_CCA 0xa08 /* Disable init gain now */ /* Init gain */ - -#define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ -#define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ - -#define rCCK0_RxHP 0xa14 - -#define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ -#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ - -#define rCCK0_TxFilter1 0xa20 -#define rCCK0_TxFilter2 0xa24 -#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ -#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ -#define rCCK0_TRSSIReport 0xa50 -#define rCCK0_RxReport 0xa54 /* 0xa57 */ -#define rCCK0_FACounterLower 0xa5c /* 0xa5b */ -#define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ - -/* - * PageB(0xB00) - * */ -#define rPdp_AntA 0xb00 -#define rPdp_AntA_4 0xb04 -#define rConfig_Pmpd_AntA 0xb28 -#define rConfig_ram64x16 0xb2c - -#define rConfig_AntA 0xb68 -#define rConfig_AntB 0xb6c -#define rPdp_AntB 0xb70 -#define rPdp_AntB_4 0xb74 -#define rConfig_Pmpd_AntB 0xb98 -#define rAPK 0xbd8 - - - -/* - * 6. PageC(0xC00) - * */ -#define rOFDM0_LSTF 0xc00 - -#define rOFDM0_TRxPathEnable 0xc04 -#define rOFDM0_TRMuxPar 0xc08 -#define rOFDM0_TRSWIsolation 0xc0c - -#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ -#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ -#define rOFDM0_XBRxAFE 0xc18 -#define rOFDM0_XBRxIQImbalance 0xc1c -#define rOFDM0_XCRxAFE 0xc20 -#define rOFDM0_XCRxIQImbalance 0xc24 -#define rOFDM0_XDRxAFE 0xc28 -#define rOFDM0_XDRxIQImbalance 0xc2c - -#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */ -#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ -#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ -#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ - -#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ -#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ -#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ -#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ - -#define rOFDM0_XAAGCCore1 0xc50 /* DIG */ -#define rOFDM0_XAAGCCore2 0xc54 -#define rOFDM0_XBAGCCore1 0xc58 -#define rOFDM0_XBAGCCore2 0xc5c -#define rOFDM0_XCAGCCore1 0xc60 -#define rOFDM0_XCAGCCore2 0xc64 -#define rOFDM0_XDAGCCore1 0xc68 -#define rOFDM0_XDAGCCore2 0xc6c - -#define rOFDM0_AGCParameter1 0xc70 -#define rOFDM0_AGCParameter2 0xc74 -#define rOFDM0_AGCRSSITable 0xc78 -#define rOFDM0_HTSTFAGC 0xc7c - -#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ -#define rOFDM0_XATxAFE 0xc84 -#define rOFDM0_XBTxIQImbalance 0xc88 -#define rOFDM0_XBTxAFE 0xc8c -#define rOFDM0_XCTxIQImbalance 0xc90 -#define rOFDM0_XCTxAFE 0xc94 -#define rOFDM0_XDTxIQImbalance 0xc98 -#define rOFDM0_XDTxAFE 0xc9c - -#define rOFDM0_RxIQExtAnta 0xca0 -#define rOFDM0_TxCoeff1 0xca4 -#define rOFDM0_TxCoeff2 0xca8 -#define rOFDM0_TxCoeff3 0xcac -#define rOFDM0_TxCoeff4 0xcb0 -#define rOFDM0_TxCoeff5 0xcb4 -#define rOFDM0_RxHPParameter 0xce0 -#define rOFDM0_TxPseudoNoiseWgt 0xce4 -#define rOFDM0_FrameSync 0xcf0 -#define rOFDM0_DFSReport 0xcf4 - - -/* - * 7. PageD(0xD00) - * */ -#define rOFDM1_LSTF 0xd00 -#define rOFDM1_TRxPathEnable 0xd04 - -#define rOFDM1_CFO 0xd08 /* No setting now */ -#define rOFDM1_CSI1 0xd10 -#define rOFDM1_SBD 0xd14 -#define rOFDM1_CSI2 0xd18 -#define rOFDM1_CFOTracking 0xd2c -#define rOFDM1_TRxMesaure1 0xd34 -#define rOFDM1_IntfDet 0xd3c -#define rOFDM1_PseudoNoiseStateAB 0xd50 -#define rOFDM1_PseudoNoiseStateCD 0xd54 -#define rOFDM1_RxPseudoNoiseWgt 0xd58 - -#define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ -#define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ -#define rOFDM_PHYCounter3 0xda8 /* MCS not support */ - -#define rOFDM_ShortCFOAB 0xdac /* No setting now */ -#define rOFDM_ShortCFOCD 0xdb0 -#define rOFDM_LongCFOAB 0xdb4 -#define rOFDM_LongCFOCD 0xdb8 -#define rOFDM_TailCFOAB 0xdbc -#define rOFDM_TailCFOCD 0xdc0 -#define rOFDM_PWMeasure1 0xdc4 -#define rOFDM_PWMeasure2 0xdc8 -#define rOFDM_BWReport 0xdcc -#define rOFDM_AGCReport 0xdd0 -#define rOFDM_RxSNR 0xdd4 -#define rOFDM_RxEVMCSI 0xdd8 -#define rOFDM_SIGReport 0xddc - - -/* - * 8. PageE(0xE00) - * */ -#define rTxAGC_A_Rate18_06 0xe00 -#define rTxAGC_A_Rate54_24 0xe04 -#define rTxAGC_A_CCK1_Mcs32 0xe08 -#define rTxAGC_A_Mcs03_Mcs00 0xe10 -#define rTxAGC_A_Mcs07_Mcs04 0xe14 -#define rTxAGC_A_Mcs11_Mcs08 0xe18 -#define rTxAGC_A_Mcs15_Mcs12 0xe1c - -#define rTxAGC_B_Rate18_06 0x830 -#define rTxAGC_B_Rate54_24 0x834 -#define rTxAGC_B_CCK1_55_Mcs32 0x838 -#define rTxAGC_B_Mcs03_Mcs00 0x83c -#define rTxAGC_B_Mcs07_Mcs04 0x848 -#define rTxAGC_B_Mcs11_Mcs08 0x84c -#define rTxAGC_B_Mcs15_Mcs12 0x868 -#define rTxAGC_B_CCK11_A_CCK2_11 0x86c - -#define rFPGA0_IQK 0xe28 -#define rTx_IQK_Tone_A 0xe30 -#define rRx_IQK_Tone_A 0xe34 -#define rTx_IQK_PI_A 0xe38 -#define rRx_IQK_PI_A 0xe3c - -#define rTx_IQK 0xe40 -#define rRx_IQK 0xe44 -#define rIQK_AGC_Pts 0xe48 -#define rIQK_AGC_Rsp 0xe4c -#define rTx_IQK_Tone_B 0xe50 -#define rRx_IQK_Tone_B 0xe54 -#define rTx_IQK_PI_B 0xe58 -#define rRx_IQK_PI_B 0xe5c -#define rIQK_AGC_Cont 0xe60 - -#define rBlue_Tooth 0xe6c -#define rRx_Wait_CCA 0xe70 -#define rTx_CCK_RFON 0xe74 -#define rTx_CCK_BBON 0xe78 -#define rTx_OFDM_RFON 0xe7c -#define rTx_OFDM_BBON 0xe80 -#define rTx_To_Rx 0xe84 -#define rTx_To_Tx 0xe88 -#define rRx_CCK 0xe8c - -#define rTx_Power_Before_IQK_A 0xe94 -#define rTx_Power_After_IQK_A 0xe9c - -#define rRx_Power_Before_IQK_A 0xea0 -#define rRx_Power_Before_IQK_A_2 0xea4 -#define rRx_Power_After_IQK_A 0xea8 -#define rRx_Power_After_IQK_A_2 0xeac - -#define rTx_Power_Before_IQK_B 0xeb4 -#define rTx_Power_After_IQK_B 0xebc - -#define rRx_Power_Before_IQK_B 0xec0 -#define rRx_Power_Before_IQK_B_2 0xec4 -#define rRx_Power_After_IQK_B 0xec8 -#define rRx_Power_After_IQK_B_2 0xecc - -#define rRx_OFDM 0xed0 -#define rRx_Wait_RIFS 0xed4 -#define rRx_TO_Rx 0xed8 -#define rStandby 0xedc -#define rSleep 0xee0 -#define rPMPD_ANAEN 0xeec - -/* - * 7. RF Register 0x00-0x2E (RF 8256) - * RF-0222D 0x00-3F - * - * Zebra1 */ -#define rZebra1_HSSIEnable 0x0 /* Useless now */ -#define rZebra1_TRxEnable1 0x1 -#define rZebra1_TRxEnable2 0x2 -#define rZebra1_AGC 0x4 -#define rZebra1_ChargePump 0x5 -#define rZebra1_Channel 0x7 /* RF channel switch */ - -/* #endif */ -#define rZebra1_TxGain 0x8 /* Useless now */ -#define rZebra1_TxLPF 0x9 -#define rZebra1_RxLPF 0xb -#define rZebra1_RxHPFCorner 0xc - -/* Zebra4 */ -#define rGlobalCtrl 0 /* Useless now */ -#define rRTL8256_TxLPF 19 -#define rRTL8256_RxLPF 11 - -/* RTL8258 */ -#define rRTL8258_TxLPF 0x11 /* Useless now */ -#define rRTL8258_RxLPF 0x13 -#define rRTL8258_RSSILPF 0xa - -/* - * RL6052 Register definition - * */ -#define RF_AC 0x00 /* */ - -#define RF_IQADJ_G1 0x01 /* */ -#define RF_IQADJ_G2 0x02 /* */ - -#define RF_POW_TRSW 0x05 /* */ - -#define RF_GAIN_RX 0x06 /* */ -#define RF_GAIN_TX 0x07 /* */ - -#define RF_TXM_IDAC 0x08 /* */ -#define RF_IPA_G 0x09 /* */ -#define RF_TXBIAS_G 0x0A -#define RF_TXPA_AG 0x0B -#define RF_IPA_A 0x0C /* */ -#define RF_TXBIAS_A 0x0D -#define RF_BS_PA_APSET_G9_G11 0x0E -#define RF_BS_IQGEN 0x0F /* */ - -#define RF_MODE1 0x10 /* */ -#define RF_MODE2 0x11 /* */ - -#define RF_RX_AGC_HP 0x12 /* */ -#define RF_TX_AGC 0x13 /* */ -#define RF_BIAS 0x14 /* */ -#define RF_IPA 0x15 /* */ -#define RF_TXBIAS 0x16 -#define RF_POW_ABILITY 0x17 /* */ -#define RF_CHNLBW 0x18 /* RF channel and BW switch */ -#define RF_TOP 0x19 /* */ - -#define RF_RX_G1 0x1A /* */ -#define RF_RX_G2 0x1B /* */ - -#define RF_RX_BB2 0x1C /* */ -#define RF_RX_BB1 0x1D /* */ - -#define RF_RCK1 0x1E /* */ -#define RF_RCK2 0x1F /* */ - -#define RF_TX_G1 0x20 /* */ -#define RF_TX_G2 0x21 /* */ -#define RF_TX_G3 0x22 /* */ - -#define RF_TX_BB1 0x23 /* */ - -#define RF_T_METER_8192E 0x42 /* */ -#define RF_T_METER_88E 0x42 -#define RF_T_METER 0x24 /* */ - -/* #endif */ - -#define RF_SYN_G1 0x25 /* RF TX Power control */ -#define RF_SYN_G2 0x26 /* RF TX Power control */ -#define RF_SYN_G3 0x27 /* RF TX Power control */ -#define RF_SYN_G4 0x28 /* RF TX Power control */ -#define RF_SYN_G5 0x29 /* RF TX Power control */ -#define RF_SYN_G6 0x2A /* RF TX Power control */ -#define RF_SYN_G7 0x2B /* RF TX Power control */ -#define RF_SYN_G8 0x2C /* RF TX Power control */ - -#define RF_RCK_OS 0x30 /* RF TX PA control */ -#define RF_TXPA_G1 0x31 /* RF TX PA control */ -#define RF_TXPA_G2 0x32 /* RF TX PA control */ -#define RF_TXPA_G3 0x33 /* RF TX PA control */ -#define RF_TX_BIAS_A 0x35 -#define RF_TX_BIAS_D 0x36 -#define RF_LOBF_9 0x38 -#define RF_RXRF_A3 0x3C /* */ -#define RF_TRSW 0x3F - -#define RF_TXRF_A2 0x41 -#define RF_TXPA_G4 0x46 -#define RF_TXPA_A4 0x4B -#define RF_0x52 0x52 -#define RF_LDO 0xB1 -#define RF_WE_LUT 0xEF - - -/* - * Bit Mask - * - * 1. Page1(0x100) */ -#define bBBResetB 0x100 /* Useless now? */ -#define bGlobalResetB 0x200 -#define bOFDMTxStart 0x4 -#define bCCKTxStart 0x8 -#define bCRC32Debug 0x100 -#define bPMACLoopback 0x10 -#define bTxLSIG 0xffffff -#define bOFDMTxRate 0xf -#define bOFDMTxReserved 0x10 -#define bOFDMTxLength 0x1ffe0 -#define bOFDMTxParity 0x20000 -#define bTxHTSIG1 0xffffff -#define bTxHTMCSRate 0x7f -#define bTxHTBW 0x80 -#define bTxHTLength 0xffff00 -#define bTxHTSIG2 0xffffff -#define bTxHTSmoothing 0x1 -#define bTxHTSounding 0x2 -#define bTxHTReserved 0x4 -#define bTxHTAggreation 0x8 -#define bTxHTSTBC 0x30 -#define bTxHTAdvanceCoding 0x40 -#define bTxHTShortGI 0x80 -#define bTxHTNumberHT_LTF 0x300 -#define bTxHTCRC8 0x3fc00 -#define bCounterReset 0x10000 -#define bNumOfOFDMTx 0xffff -#define bNumOfCCKTx 0xffff0000 -#define bTxIdleInterval 0xffff -#define bOFDMService 0xffff0000 -#define bTxMACHeader 0xffffffff -#define bTxDataInit 0xff -#define bTxHTMode 0x100 -#define bTxDataType 0x30000 -#define bTxRandomSeed 0xffffffff -#define bCCKTxPreamble 0x1 -#define bCCKTxSFD 0xffff0000 -#define bCCKTxSIG 0xff -#define bCCKTxService 0xff00 -#define bCCKLengthExt 0x8000 -#define bCCKTxLength 0xffff0000 -#define bCCKTxCRC16 0xffff -#define bCCKTxStatus 0x1 -#define bOFDMTxStatus 0x2 - -#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) -#define RF_TX_GAIN_OFFSET_8192E(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0)) - - -/* 2. Page8(0x800) */ -#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ -#define bJapanMode 0x2 -#define bCCKTxSC 0x30 -#define bCCKEn 0x1000000 -#define bOFDMEn 0x2000000 - -#define bOFDMRxADCPhase 0x10000 /* Useless now */ -#define bOFDMTxDACPhase 0x40000 -#define bXATxAGC 0x3f - -#define bAntennaSelect 0x0300 - -#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ -#define bXCTxAGC 0xf000 -#define bXDTxAGC 0xf0000 - -#define bPAStart 0xf0000000 /* Useless now */ -#define bTRStart 0x00f00000 -#define bRFStart 0x0000f000 -#define bBBStart 0x000000f0 -#define bBBCCKStart 0x0000000f -#define bPAEnd 0xf /* Reg0x814 */ -#define bTREnd 0x0f000000 -#define bRFEnd 0x000f0000 -#define bCCAMask 0x000000f0 /* T2R */ -#define bR2RCCAMask 0x00000f00 -#define bHSSI_R2TDelay 0xf8000000 -#define bHSSI_T2RDelay 0xf80000 -#define bContTxHSSI 0x400 /* chane gain at continue Tx */ -#define bIGFromCCK 0x200 -#define bAGCAddress 0x3f -#define bRxHPTx 0x7000 -#define bRxHPT2R 0x38000 -#define bRxHPCCKIni 0xc0000 -#define bAGCTxCode 0xc00000 -#define bAGCRxCode 0x300000 - -#define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ -#define b3WireAddressLength 0x400 - -#define b3WireRFPowerDown 0x1 /* Useless now - * #define bHWSISelect 0x8 */ -#define b5GPAPEPolarity 0x40000000 -#define b2GPAPEPolarity 0x80000000 -#define bRFSW_TxDefaultAnt 0x3 -#define bRFSW_TxOptionAnt 0x30 -#define bRFSW_RxDefaultAnt 0x300 -#define bRFSW_RxOptionAnt 0x3000 -#define bRFSI_3WireData 0x1 -#define bRFSI_3WireClock 0x2 -#define bRFSI_3WireLoad 0x4 -#define bRFSI_3WireRW 0x8 -#define bRFSI_3Wire 0xf - -#define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ - -#define bRFSI_TRSW 0x20 /* Useless now */ -#define bRFSI_TRSWB 0x40 -#define bRFSI_ANTSW 0x100 -#define bRFSI_ANTSWB 0x200 -#define bRFSI_PAPE 0x400 -#define bRFSI_PAPE5G 0x800 -#define bBandSelect 0x1 -#define bHTSIG2_GI 0x80 -#define bHTSIG2_Smoothing 0x01 -#define bHTSIG2_Sounding 0x02 -#define bHTSIG2_Aggreaton 0x08 -#define bHTSIG2_STBC 0x30 -#define bHTSIG2_AdvCoding 0x40 -#define bHTSIG2_NumOfHTLTF 0x300 -#define bHTSIG2_CRC8 0x3fc -#define bHTSIG1_MCS 0x7f -#define bHTSIG1_BandWidth 0x80 -#define bHTSIG1_HTLength 0xffff -#define bLSIG_Rate 0xf -#define bLSIG_Reserved 0x10 -#define bLSIG_Length 0x1fffe -#define bLSIG_Parity 0x20 -#define bCCKRxPhase 0x4 - -#define bLSSIReadAddress 0x7f800000 /* T65 RF */ - -#define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ - -#define bLSSIReadBackData 0xfffff /* T65 RF */ - -#define bLSSIReadOKFlag 0x1000 /* Useless now */ -#define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ -#define bRegulator0Standby 0x1 -#define bRegulatorPLLStandby 0x2 -#define bRegulator1Standby 0x4 -#define bPLLPowerUp 0x8 -#define bDPLLPowerUp 0x10 -#define bDA10PowerUp 0x20 -#define bAD7PowerUp 0x200 -#define bDA6PowerUp 0x2000 -#define bXtalPowerUp 0x4000 -#define b40MDClkPowerUP 0x8000 -#define bDA6DebugMode 0x20000 -#define bDA6Swing 0x380000 - -#define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ - -#define b80MClkDelay 0x18000000 /* Useless */ -#define bAFEWatchDogEnable 0x20000000 - -#define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ -#define bXtalCap23 0x3 -#define bXtalCap92x 0x0f000000 -#define bXtalCap 0x0f000000 - -#define bIntDifClkEnable 0x400 /* Useless */ -#define bExtSigClkEnable 0x800 -#define bBandgapMbiasPowerUp 0x10000 -#define bAD11SHGain 0xc0000 -#define bAD11InputRange 0x700000 -#define bAD11OPCurrent 0x3800000 -#define bIPathLoopback 0x4000000 -#define bQPathLoopback 0x8000000 -#define bAFELoopback 0x10000000 -#define bDA10Swing 0x7e0 -#define bDA10Reverse 0x800 -#define bDAClkSource 0x1000 -#define bAD7InputRange 0x6000 -#define bAD7Gain 0x38000 -#define bAD7OutputCMMode 0x40000 -#define bAD7InputCMMode 0x380000 -#define bAD7Current 0xc00000 -#define bRegulatorAdjust 0x7000000 -#define bAD11PowerUpAtTx 0x1 -#define bDA10PSAtTx 0x10 -#define bAD11PowerUpAtRx 0x100 -#define bDA10PSAtRx 0x1000 -#define bCCKRxAGCFormat 0x200 -#define bPSDFFTSamplepPoint 0xc000 -#define bPSDAverageNum 0x3000 -#define bIQPathControl 0xc00 -#define bPSDFreq 0x3ff -#define bPSDAntennaPath 0x30 -#define bPSDIQSwitch 0x40 -#define bPSDRxTrigger 0x400000 -#define bPSDTxTrigger 0x80000000 -#define bPSDSineToneScale 0x7f000000 -#define bPSDReport 0xffff - -/* 3. Page9(0x900) */ -#define bOFDMTxSC 0x30000000 /* Useless */ -#define bCCKTxOn 0x1 -#define bOFDMTxOn 0x2 -#define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ -#define bDebugItem 0xff /* reset debug page and LWord */ -#define bAntL 0x10 -#define bAntNonHT 0x100 -#define bAntHT1 0x1000 -#define bAntHT2 0x10000 -#define bAntHT1S1 0x100000 -#define bAntNonHTS1 0x1000000 - -/* 4. PageA(0xA00) */ -#define bCCKBBMode 0x3 /* Useless */ -#define bCCKTxPowerSaving 0x80 -#define bCCKRxPowerSaving 0x40 - -#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ - -#define bCCKScramble 0x8 /* Useless */ -#define bCCKAntDiversity 0x8000 -#define bCCKCarrierRecovery 0x4000 -#define bCCKTxRate 0x3000 -#define bCCKDCCancel 0x0800 -#define bCCKISICancel 0x0400 -#define bCCKMatchFilter 0x0200 -#define bCCKEqualizer 0x0100 -#define bCCKPreambleDetect 0x800000 -#define bCCKFastFalseCCA 0x400000 -#define bCCKChEstStart 0x300000 -#define bCCKCCACount 0x080000 -#define bCCKcs_lim 0x070000 -#define bCCKBistMode 0x80000000 -#define bCCKCCAMask 0x40000000 -#define bCCKTxDACPhase 0x4 -#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ -#define bCCKr_cp_mode0 0x0100 -#define bCCKTxDCOffset 0xf0 -#define bCCKRxDCOffset 0xf -#define bCCKCCAMode 0xc000 -#define bCCKFalseCS_lim 0x3f00 -#define bCCKCS_ratio 0xc00000 -#define bCCKCorgBit_sel 0x300000 -#define bCCKPD_lim 0x0f0000 -#define bCCKNewCCA 0x80000000 -#define bCCKRxHPofIG 0x8000 -#define bCCKRxIG 0x7f00 -#define bCCKLNAPolarity 0x800000 -#define bCCKRx1stGain 0x7f0000 -#define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ -#define bCCKRxAGCSatLevel 0x1f000000 -#define bCCKRxAGCSatCount 0xe0 -#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ -#define bCCKFixedRxAGC 0x8000 -/* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ -#define bCCKAntennaPolarity 0x2000 -#define bCCKTxFilterType 0x0c00 -#define bCCKRxAGCReportType 0x0300 -#define bCCKRxDAGCEn 0x80000000 -#define bCCKRxDAGCPeriod 0x20000000 -#define bCCKRxDAGCSatLevel 0x1f000000 -#define bCCKTimingRecovery 0x800000 -#define bCCKTxC0 0x3f0000 -#define bCCKTxC1 0x3f000000 -#define bCCKTxC2 0x3f -#define bCCKTxC3 0x3f00 -#define bCCKTxC4 0x3f0000 -#define bCCKTxC5 0x3f000000 -#define bCCKTxC6 0x3f -#define bCCKTxC7 0x3f00 -#define bCCKDebugPort 0xff0000 -#define bCCKDACDebug 0x0f000000 -#define bCCKFalseAlarmEnable 0x8000 -#define bCCKFalseAlarmRead 0x4000 -#define bCCKTRSSI 0x7f -#define bCCKRxAGCReport 0xfe -#define bCCKRxReport_AntSel 0x80000000 -#define bCCKRxReport_MFOff 0x40000000 -#define bCCKRxRxReport_SQLoss 0x20000000 -#define bCCKRxReport_Pktloss 0x10000000 -#define bCCKRxReport_Lockedbit 0x08000000 -#define bCCKRxReport_RateError 0x04000000 -#define bCCKRxReport_RxRate 0x03000000 -#define bCCKRxFACounterLower 0xff -#define bCCKRxFACounterUpper 0xff000000 -#define bCCKRxHPAGCStart 0xe000 -#define bCCKRxHPAGCFinal 0x1c00 -#define bCCKRxFalseAlarmEnable 0x8000 -#define bCCKFACounterFreeze 0x4000 -#define bCCKTxPathSel 0x10000000 -#define bCCKDefaultRxPath 0xc000000 -#define bCCKOptionRxPath 0x3000000 - -/* 5. PageC(0xC00) */ -#define bNumOfSTF 0x3 /* Useless */ -#define bShift_L 0xc0 -#define bGI_TH 0xc -#define bRxPathA 0x1 -#define bRxPathB 0x2 -#define bRxPathC 0x4 -#define bRxPathD 0x8 -#define bTxPathA 0x1 -#define bTxPathB 0x2 -#define bTxPathC 0x4 -#define bTxPathD 0x8 -#define bTRSSIFreq 0x200 -#define bADCBackoff 0x3000 -#define bDFIRBackoff 0xc000 -#define bTRSSILatchPhase 0x10000 -#define bRxIDCOffset 0xff -#define bRxQDCOffset 0xff00 -#define bRxDFIRMode 0x1800000 -#define bRxDCNFType 0xe000000 -#define bRXIQImb_A 0x3ff -#define bRXIQImb_B 0xfc00 -#define bRXIQImb_C 0x3f0000 -#define bRXIQImb_D 0xffc00000 -#define bDC_dc_Notch 0x60000 -#define bRxNBINotch 0x1f000000 -#define bPD_TH 0xf -#define bPD_TH_Opt2 0xc000 -#define bPWED_TH 0x700 -#define bIfMF_Win_L 0x800 -#define bPD_Option 0x1000 -#define bMF_Win_L 0xe000 -#define bBW_Search_L 0x30000 -#define bwin_enh_L 0xc0000 -#define bBW_TH 0x700000 -#define bED_TH2 0x3800000 -#define bBW_option 0x4000000 -#define bRatio_TH 0x18000000 -#define bWindow_L 0xe0000000 -#define bSBD_Option 0x1 -#define bFrame_TH 0x1c -#define bFS_Option 0x60 -#define bDC_Slope_check 0x80 -#define bFGuard_Counter_DC_L 0xe00 -#define bFrame_Weight_Short 0x7000 -#define bSub_Tune 0xe00000 -#define bFrame_DC_Length 0xe000000 -#define bSBD_start_offset 0x30000000 -#define bFrame_TH_2 0x7 -#define bFrame_GI2_TH 0x38 -#define bGI2_Sync_en 0x40 -#define bSarch_Short_Early 0x300 -#define bSarch_Short_Late 0xc00 -#define bSarch_GI2_Late 0x70000 -#define bCFOAntSum 0x1 -#define bCFOAcc 0x2 -#define bCFOStartOffset 0xc -#define bCFOLookBack 0x70 -#define bCFOSumWeight 0x80 -#define bDAGCEnable 0x10000 -#define bTXIQImb_A 0x3ff -#define bTXIQImb_B 0xfc00 -#define bTXIQImb_C 0x3f0000 -#define bTXIQImb_D 0xffc00000 -#define bTxIDCOffset 0xff -#define bTxQDCOffset 0xff00 -#define bTxDFIRMode 0x10000 -#define bTxPesudoNoiseOn 0x4000000 -#define bTxPesudoNoise_A 0xff -#define bTxPesudoNoise_B 0xff00 -#define bTxPesudoNoise_C 0xff0000 -#define bTxPesudoNoise_D 0xff000000 -#define bCCADropOption 0x20000 -#define bCCADropThres 0xfff00000 -#define bEDCCA_H 0xf -#define bEDCCA_L 0xf0 -#define bLambda_ED 0x300 -#define bRxInitialGain 0x7f -#define bRxAntDivEn 0x80 -#define bRxAGCAddressForLNA 0x7f00 -#define bRxHighPowerFlow 0x8000 -#define bRxAGCFreezeThres 0xc0000 -#define bRxFreezeStep_AGC1 0x300000 -#define bRxFreezeStep_AGC2 0xc00000 -#define bRxFreezeStep_AGC3 0x3000000 -#define bRxFreezeStep_AGC0 0xc000000 -#define bRxRssi_Cmp_En 0x10000000 -#define bRxQuickAGCEn 0x20000000 -#define bRxAGCFreezeThresMode 0x40000000 -#define bRxOverFlowCheckType 0x80000000 -#define bRxAGCShift 0x7f -#define bTRSW_Tri_Only 0x80 -#define bPowerThres 0x300 -#define bRxAGCEn 0x1 -#define bRxAGCTogetherEn 0x2 -#define bRxAGCMin 0x4 -#define bRxHP_Ini 0x7 -#define bRxHP_TRLNA 0x70 -#define bRxHP_RSSI 0x700 -#define bRxHP_BBP1 0x7000 -#define bRxHP_BBP2 0x70000 -#define bRxHP_BBP3 0x700000 -#define bRSSI_H 0x7f0000 /* the threshold for high power */ -#define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ -#define bRxSettle_TRSW 0x7 -#define bRxSettle_LNA 0x38 -#define bRxSettle_RSSI 0x1c0 -#define bRxSettle_BBP 0xe00 -#define bRxSettle_RxHP 0x7000 -#define bRxSettle_AntSW_RSSI 0x38000 -#define bRxSettle_AntSW 0xc0000 -#define bRxProcessTime_DAGC 0x300000 -#define bRxSettle_HSSI 0x400000 -#define bRxProcessTime_BBPPW 0x800000 -#define bRxAntennaPowerShift 0x3000000 -#define bRSSITableSelect 0xc000000 -#define bRxHP_Final 0x7000000 -#define bRxHTSettle_BBP 0x7 -#define bRxHTSettle_HSSI 0x8 -#define bRxHTSettle_RxHP 0x70 -#define bRxHTSettle_BBPPW 0x80 -#define bRxHTSettle_Idle 0x300 -#define bRxHTSettle_Reserved 0x1c00 -#define bRxHTRxHPEn 0x8000 -#define bRxHTAGCFreezeThres 0x30000 -#define bRxHTAGCTogetherEn 0x40000 -#define bRxHTAGCMin 0x80000 -#define bRxHTAGCEn 0x100000 -#define bRxHTDAGCEn 0x200000 -#define bRxHTRxHP_BBP 0x1c00000 -#define bRxHTRxHP_Final 0xe0000000 -#define bRxPWRatioTH 0x3 -#define bRxPWRatioEn 0x4 -#define bRxMFHold 0x3800 -#define bRxPD_Delay_TH1 0x38 -#define bRxPD_Delay_TH2 0x1c0 -#define bRxPD_DC_COUNT_MAX 0x600 -/* #define bRxMF_Hold 0x3800 */ -#define bRxPD_Delay_TH 0x8000 -#define bRxProcess_Delay 0xf0000 -#define bRxSearchrange_GI2_Early 0x700000 -#define bRxFrame_Guard_Counter_L 0x3800000 -#define bRxSGI_Guard_L 0xc000000 -#define bRxSGI_Search_L 0x30000000 -#define bRxSGI_TH 0xc0000000 -#define bDFSCnt0 0xff -#define bDFSCnt1 0xff00 -#define bDFSFlag 0xf0000 -#define bMFWeightSum 0x300000 -#define bMinIdxTH 0x7f000000 -#define bDAFormat 0x40000 -#define bTxChEmuEnable 0x01000000 -#define bTRSWIsolation_A 0x7f -#define bTRSWIsolation_B 0x7f00 -#define bTRSWIsolation_C 0x7f0000 -#define bTRSWIsolation_D 0x7f000000 -#define bExtLNAGain 0x7c00 - -/* 6. PageE(0xE00) */ -#define bSTBCEn 0x4 /* Useless */ -#define bAntennaMapping 0x10 -#define bNss 0x20 -#define bCFOAntSumD 0x200 -#define bPHYCounterReset 0x8000000 -#define bCFOReportGet 0x4000000 -#define bOFDMContinueTx 0x10000000 -#define bOFDMSingleCarrier 0x20000000 -#define bOFDMSingleTone 0x40000000 -/* #define bRxPath1 0x01 */ -/* #define bRxPath2 0x02 */ -/* #define bRxPath3 0x04 */ -/* #define bRxPath4 0x08 */ -/* #define bTxPath1 0x10 */ -/* #define bTxPath2 0x20 */ -#define bHTDetect 0x100 -#define bCFOEn 0x10000 -#define bCFOValue 0xfff00000 -#define bSigTone_Re 0x3f -#define bSigTone_Im 0x7f00 -#define bCounter_CCA 0xffff -#define bCounter_ParityFail 0xffff0000 -#define bCounter_RateIllegal 0xffff -#define bCounter_CRC8Fail 0xffff0000 -#define bCounter_MCSNoSupport 0xffff -#define bCounter_FastSync 0xffff -#define bShortCFO 0xfff -#define bShortCFOTLength 12 /* total */ -#define bShortCFOFLength 11 /* fraction */ -#define bLongCFO 0x7ff -#define bLongCFOTLength 11 -#define bLongCFOFLength 11 -#define bTailCFO 0x1fff -#define bTailCFOTLength 13 -#define bTailCFOFLength 12 -#define bmax_en_pwdB 0xffff -#define bCC_power_dB 0xffff0000 -#define bnoise_pwdB 0xffff -#define bPowerMeasTLength 10 -#define bPowerMeasFLength 3 -#define bRx_HT_BW 0x1 -#define bRxSC 0x6 -#define bRx_HT 0x8 -#define bNB_intf_det_on 0x1 -#define bIntf_win_len_cfg 0x30 -#define bNB_Intf_TH_cfg 0x1c0 -#define bRFGain 0x3f -#define bTableSel 0x40 -#define bTRSW 0x80 -#define bRxSNR_A 0xff -#define bRxSNR_B 0xff00 -#define bRxSNR_C 0xff0000 -#define bRxSNR_D 0xff000000 -#define bSNREVMTLength 8 -#define bSNREVMFLength 1 -#define bCSI1st 0xff -#define bCSI2nd 0xff00 -#define bRxEVM1st 0xff0000 -#define bRxEVM2nd 0xff000000 -#define bSIGEVM 0xff -#define bPWDB 0xff00 -#define bSGIEN 0x10000 - -#define bSFactorQAM1 0xf /* Useless */ -#define bSFactorQAM2 0xf0 -#define bSFactorQAM3 0xf00 -#define bSFactorQAM4 0xf000 -#define bSFactorQAM5 0xf0000 -#define bSFactorQAM6 0xf0000 -#define bSFactorQAM7 0xf00000 -#define bSFactorQAM8 0xf000000 -#define bSFactorQAM9 0xf0000000 -#define bCSIScheme 0x100000 - -#define bNoiseLvlTopSet 0x3 /* Useless */ -#define bChSmooth 0x4 -#define bChSmoothCfg1 0x38 -#define bChSmoothCfg2 0x1c0 -#define bChSmoothCfg3 0xe00 -#define bChSmoothCfg4 0x7000 -#define bMRCMode 0x800000 -#define bTHEVMCfg 0x7000000 - -#define bLoopFitType 0x1 /* Useless */ -#define bUpdCFO 0x40 -#define bUpdCFOOffData 0x80 -#define bAdvUpdCFO 0x100 -#define bAdvTimeCtrl 0x800 -#define bUpdClko 0x1000 -#define bFC 0x6000 -#define bTrackingMode 0x8000 -#define bPhCmpEnable 0x10000 -#define bUpdClkoLTF 0x20000 -#define bComChCFO 0x40000 -#define bCSIEstiMode 0x80000 -#define bAdvUpdEqz 0x100000 -#define bUChCfg 0x7000000 -#define bUpdEqz 0x8000000 - -/* Rx Pseduo noise */ -#define bRxPesudoNoiseOn 0x20000000 /* Useless */ -#define bRxPesudoNoise_A 0xff -#define bRxPesudoNoise_B 0xff00 -#define bRxPesudoNoise_C 0xff0000 -#define bRxPesudoNoise_D 0xff000000 -#define bPesudoNoiseState_A 0xffff -#define bPesudoNoiseState_B 0xffff0000 -#define bPesudoNoiseState_C 0xffff -#define bPesudoNoiseState_D 0xffff0000 - -/* 7. RF Register - * Zebra1 */ -#define bZebra1_HSSIEnable 0x8 /* Useless */ -#define bZebra1_TRxControl 0xc00 -#define bZebra1_TRxGainSetting 0x07f -#define bZebra1_RxCorner 0xc00 -#define bZebra1_TxChargePump 0x38 -#define bZebra1_RxChargePump 0x7 -#define bZebra1_ChannelNum 0xf80 -#define bZebra1_TxLPFBW 0x400 -#define bZebra1_RxLPFBW 0x600 - -/* Zebra4 */ -#define bRTL8256RegModeCtrl1 0x100 /* Useless */ -#define bRTL8256RegModeCtrl0 0x40 -#define bRTL8256_TxLPFBW 0x18 -#define bRTL8256_RxLPFBW 0x600 - -/* RTL8258 */ -#define bRTL8258_TxLPFBW 0xc /* Useless */ -#define bRTL8258_RxLPFBW 0xc00 -#define bRTL8258_RSSILPFBW 0xc0 - - -/* - * Other Definition - * */ - -/* byte endable for sb_write */ -#define bByte0 0x1 /* Useless */ -#define bByte1 0x2 -#define bByte2 0x4 -#define bByte3 0x8 -#define bWord0 0x3 -#define bWord1 0xc -#define bDWord 0xf - -/* for PutRegsetting & GetRegSetting BitMask */ -#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ -#define bMaskByte1 0xff00 -#define bMaskByte2 0xff0000 -#define bMaskByte3 0xff000000 -#define bMaskHWord 0xffff0000 -#define bMaskLWord 0x0000ffff -#define bMaskDWord 0xffffffff -#define bMaskH3Bytes 0xffffff00 -#define bMask12Bits 0xfff -#define bMaskH4Bits 0xf0000000 -#define bMaskOFDM_D 0xffc00000 -#define bMaskCCK 0x3f3f3f3f - -/* for PutRFRegsetting & GetRFRegSetting BitMask - * #define bMask12Bits 0xfffff */ /* RF Reg mask bits - * #define bMask20Bits 0xfffff */ /* RF Reg mask bits T65 RF */ -#define bRFRegOffsetMask 0xfffff - -#define bEnable 0x1 /* Useless */ -#define bDisable 0x0 - -#define LeftAntenna 0x0 /* Useless */ -#define RightAntenna 0x1 - -#define tCheckTxStatus 500 /* 500ms */ /* Useless */ -#define tUpdateRxCounter 100 /* 100ms */ - -#define rateCCK 0 /* Useless */ -#define rateOFDM 1 -#define rateHT 2 - -/* define Register-End */ -#define bPMAC_End 0x1ff /* Useless */ -#define bFPGAPHY0_End 0x8ff -#define bFPGAPHY1_End 0x9ff -#define bCCKPHY0_End 0xaff -#define bOFDMPHY0_End 0xcff -#define bOFDMPHY1_End 0xdff - -/* define max debug item in each debug page - * #define bMaxItem_FPGA_PHY0 0x9 - * #define bMaxItem_FPGA_PHY1 0x3 - * #define bMaxItem_PHY_11B 0x16 - * #define bMaxItem_OFDM_PHY0 0x29 - * #define bMaxItem_OFDM_PHY1 0x0 */ - -#define bPMACControl 0x0 /* Useless */ -#define bWMACControl 0x1 -#define bWNICControl 0x2 - -#define PathA 0x0 /* Useless */ -#define PathB 0x1 -#define PathC 0x2 -#define PathD 0x3 - - -/* RSSI Dump Message */ -#define rA_RSSIDump_92E 0xcb0 -#define rB_RSSIDump_92E 0xcb1 -#define rS1_RXevmDump_92E 0xcb2 -#define rS2_RXevmDump_92E 0xcb3 -#define rA_RXsnrDump_92E 0xcb4 -#define rB_RXsnrDump_92E 0xcb5 -#define rA_CfoShortDump_92E 0xcb6 -#define rB_CfoShortDump_92E 0xcb8 -#define rA_CfoLongDump_92E 0xcba -#define rB_CfoLongDump_92E 0xcbc - -/*--------------------------Define Parameters-------------------------------*/ - - -#endif /* __INC_HAL8188EPHYREG_H */ diff --git a/include/Hal8192EPwrSeq.h b/include/Hal8192EPwrSeq.h deleted file mode 100644 index 12bb2fb..0000000 --- a/include/Hal8192EPwrSeq.h +++ /dev/null @@ -1,155 +0,0 @@ -#ifndef REALTEK_POWER_SEQUENCE_8192E -#define REALTEK_POWER_SEQUENCE_8192E - -#include "HalPwrSeqCmd.h" -/* - Check document WM-20110607-Paul-RTL8192E_Power_Architecture-R02.vsd - There are 6 HW Power States: - 0: POFF--Power Off - 1: PDN--Power Down - 2: CARDEMU--Card Emulation - 3: ACT--Active Mode - 4: LPS--Low Power State - 5: SUS--Suspend - - The transision from different states are defined below - TRANS_CARDEMU_TO_ACT - TRANS_ACT_TO_CARDEMU - TRANS_CARDEMU_TO_SUS - TRANS_SUS_TO_CARDEMU - TRANS_CARDEMU_TO_PDN - TRANS_ACT_TO_LPS - TRANS_LPS_TO_ACT - - TRANS_END -*/ -#define RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS 18 -#define RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS 18 -#define RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS 18 -#define RTL8192E_TRANS_SUS_TO_CARDEMU_STEPS 18 -#define RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS 18 -#define RTL8192E_TRANS_PDN_TO_CARDEMU_STEPS 18 -#define RTL8192E_TRANS_ACT_TO_LPS_STEPS 23 -#define RTL8192E_TRANS_LPS_TO_ACT_STEPS 23 -#define RTL8192E_TRANS_END_STEPS 1 - - -#define RTL8192E_TRANS_CARDEMU_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \ - - -#define RTL8192E_TRANS_ACT_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ - {0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ - - -#define RTL8192E_TRANS_CARDEMU_TO_SUS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ - -#define RTL8192E_TRANS_SUS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ - -#define RTL8192E_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \ - {0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*Unlock small LDO Register*/ \ - {0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*Disable small LDO*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ - -#define RTL8192E_TRANS_CARDDIS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ - {0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*Enable small LDO*/ \ - {0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*Lock small LDO Register*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\ - - -#define RTL8192E_TRANS_CARDEMU_TO_PDN \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ - -#define RTL8192E_TRANS_PDN_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ - -#define RTL8192E_TRANS_ACT_TO_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ - {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ - {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \ - {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \ - - -#define RTL8192E_TRANS_LPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM, For Repeatly In and out, Taggle bit should be changed*/\ - {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ - {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ - {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/\ - {0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*Clear ISR*/ - -#define RTL8192E_TRANS_END \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0}, - - - extern WLAN_PWR_CFG rtl8192E_power_on_flow[RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8192E_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8192E_radio_off_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8192E_card_disable_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8192E_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8192E_card_enable_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8192E_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8192E_suspend_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8192E_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8192E_resume_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8192E_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8192E_hwpdn_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8192E_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8192E_enter_lps_flow[RTL8192E_TRANS_ACT_TO_LPS_STEPS + RTL8192E_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8192E_leave_lps_flow[RTL8192E_TRANS_LPS_TO_ACT_STEPS + RTL8192E_TRANS_END_STEPS]; - -#endif diff --git a/include/Hal8703BPhyCfg.h b/include/Hal8703BPhyCfg.h deleted file mode 100644 index a038bcc..0000000 --- a/include/Hal8703BPhyCfg.h +++ /dev/null @@ -1,137 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_HAL8703BPHYCFG_H__ -#define __INC_HAL8703BPHYCFG_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#define LOOP_LIMIT 5 -#define MAX_STALL_TIME 50 /* us */ -#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */ -#define MAX_TXPWR_IDX_NMODE_92S 63 -#define Reset_Cnt_Limit 3 - -#ifdef CONFIG_PCI_HCI - #define MAX_AGGR_NUM 0x0B -#else - #define MAX_AGGR_NUM 0x07 -#endif /* CONFIG_PCI_HCI */ - - -/*--------------------------Define Parameters End-------------------------------*/ - - -/*------------------------------Define structure----------------------------*/ - -/*------------------------------Define structure End----------------------------*/ - -/*--------------------------Exported Function prototype---------------------*/ -u32 -PHY_QueryBBReg_8703B( - IN PADAPTER Adapter, - IN u32 RegAddr, - IN u32 BitMask -); - -VOID -PHY_SetBBReg_8703B( - IN PADAPTER Adapter, - IN u32 RegAddr, - IN u32 BitMask, - IN u32 Data -); - -u32 -PHY_QueryRFReg_8703B( - IN PADAPTER Adapter, - IN u8 eRFPath, - IN u32 RegAddr, - IN u32 BitMask -); - -VOID -PHY_SetRFReg_8703B( - IN PADAPTER Adapter, - IN u8 eRFPath, - IN u32 RegAddr, - IN u32 BitMask, - IN u32 Data -); - -/* MAC/BB/RF HAL config */ -int PHY_BBConfig8703B(PADAPTER Adapter); - -int PHY_RFConfig8703B(PADAPTER Adapter); - -s32 PHY_MACConfig8703B(PADAPTER padapter); - -int -PHY_ConfigRFWithParaFile_8703B( - IN PADAPTER Adapter, - IN u8 *pFileName, - RF_PATH eRFPath -); - -VOID -PHY_SetTxPowerIndex_8703B( - IN PADAPTER Adapter, - IN u32 PowerIndex, - IN u8 RFPath, - IN u8 Rate -); - -u8 -PHY_GetTxPowerIndex_8703B( - IN PADAPTER pAdapter, - IN u8 RFPath, - IN u8 Rate, - IN u8 BandWidth, - IN u8 Channel, - struct txpwr_idx_comp *tic -); - -VOID -PHY_GetTxPowerLevel8703B( - IN PADAPTER Adapter, - OUT s32 *powerlevel -); - -VOID -PHY_SetTxPowerLevel8703B( - IN PADAPTER Adapter, - IN u8 channel -); - -VOID -PHY_SetSwChnlBWMode8703B( - IN PADAPTER Adapter, - IN u8 channel, - IN CHANNEL_WIDTH Bandwidth, - IN u8 Offset40, - IN u8 Offset80 -); - -VOID phy_set_rf_path_switch_8703b( - IN PADAPTER pAdapter, - IN bool bMain -); - -/*--------------------------Exported Function prototype End---------------------*/ - -#endif diff --git a/include/Hal8703BPhyReg.h b/include/Hal8703BPhyReg.h deleted file mode 100644 index e8eb664..0000000 --- a/include/Hal8703BPhyReg.h +++ /dev/null @@ -1,1138 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_HAL8703BPHYREG_H__ -#define __INC_HAL8703BPHYREG_H__ - -#define rSYM_WLBT_PAPE_SEL 0x64 -/* - * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF - * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF - * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 - * 3. RF register 0x00-2E - * 4. Bit Mask for BB/RF register - * 5. Other defintion for BB/RF R/W - * */ - - -/* - * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF - * 1. Page1(0x100) - * */ -#define rPMAC_Reset 0x100 -#define rPMAC_TxStart 0x104 -#define rPMAC_TxLegacySIG 0x108 -#define rPMAC_TxHTSIG1 0x10c -#define rPMAC_TxHTSIG2 0x110 -#define rPMAC_PHYDebug 0x114 -#define rPMAC_TxPacketNum 0x118 -#define rPMAC_TxIdle 0x11c -#define rPMAC_TxMACHeader0 0x120 -#define rPMAC_TxMACHeader1 0x124 -#define rPMAC_TxMACHeader2 0x128 -#define rPMAC_TxMACHeader3 0x12c -#define rPMAC_TxMACHeader4 0x130 -#define rPMAC_TxMACHeader5 0x134 -#define rPMAC_TxDataType 0x138 -#define rPMAC_TxRandomSeed 0x13c -#define rPMAC_CCKPLCPPreamble 0x140 -#define rPMAC_CCKPLCPHeader 0x144 -#define rPMAC_CCKCRC16 0x148 -#define rPMAC_OFDMRxCRC32OK 0x170 -#define rPMAC_OFDMRxCRC32Er 0x174 -#define rPMAC_OFDMRxParityEr 0x178 -#define rPMAC_OFDMRxCRC8Er 0x17c -#define rPMAC_CCKCRxRC16Er 0x180 -#define rPMAC_CCKCRxRC32Er 0x184 -#define rPMAC_CCKCRxRC32OK 0x188 -#define rPMAC_TxStatus 0x18c - -/* - * 2. Page2(0x200) - * - * The following two definition are only used for USB interface. */ -#define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */ -#define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */ - -/* - * 3. Page8(0x800) - * */ -#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */ - -#define rFPGA0_TxInfo 0x804 /* Status report?? */ -#define rFPGA0_PSDFunction 0x808 - -#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ - -#define rFPGA0_RFTiming1 0x810 /* Useless now */ -#define rFPGA0_RFTiming2 0x814 - -#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ -#define rFPGA0_XA_HSSIParameter2 0x824 -#define rFPGA0_XB_HSSIParameter1 0x828 -#define rFPGA0_XB_HSSIParameter2 0x82c -#define rTxAGC_B_Rate18_06 0x830 -#define rTxAGC_B_Rate54_24 0x834 -#define rTxAGC_B_CCK1_55_Mcs32 0x838 -#define rTxAGC_B_Mcs03_Mcs00 0x83c - -#define rTxAGC_B_Mcs07_Mcs04 0x848 -#define rTxAGC_B_Mcs11_Mcs08 0x84c - -#define rFPGA0_XA_LSSIParameter 0x840 -#define rFPGA0_XB_LSSIParameter 0x844 - -#define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ -#define rFPGA0_RFSleepUpParameter 0x854 - -#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ -#define rFPGA0_XCD_SwitchControl 0x85c - -#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ -#define rFPGA0_XB_RFInterfaceOE 0x864 - -#define rTxAGC_B_Mcs15_Mcs12 0x868 -#define rTxAGC_B_CCK11_A_CCK2_11 0x86c - -#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ -#define rFPGA0_XCD_RFInterfaceSW 0x874 - -#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ -#define rFPGA0_XCD_RFParameter 0x87c - -#define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ -#define rFPGA0_AnalogParameter2 0x884 -#define rFPGA0_AnalogParameter3 0x888 /* Useless now */ -#define rFPGA0_AnalogParameter4 0x88c - -#define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ -#define rFPGA0_XB_LSSIReadBack 0x8a4 -#define rFPGA0_XC_LSSIReadBack 0x8a8 -#define rFPGA0_XD_LSSIReadBack 0x8ac - -#define rFPGA0_PSDReport 0x8b4 /* Useless now */ -#define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ -#define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ -#define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ /* RF Interface Readback Value */ -#define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ - -/* - * 4. Page9(0x900) - * */ -#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */ -#define rFPGA1_TxBlock 0x904 /* Useless now */ -#define rFPGA1_DebugSelect 0x908 /* Useless now */ -#define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */ -#define rDPDT_control 0x92c -#define rfe_ctrl_anta_src 0x930 -#define rS0S1_PathSwitch 0x948 -#define rBBrx_DFIR 0x954 - -/* - * 5. PageA(0xA00) - * - * Set Control channel to upper or lower. These settings are required only for 40MHz */ -#define rCCK0_System 0xa00 - -#define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */ -#define rCCK0_CCA 0xa08 /* Disable init gain now */ /* Init gain */ - -#define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ -#define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ - -#define rCCK0_RxHP 0xa14 - -#define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ -#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ - -#define rCCK0_TxFilter1 0xa20 -#define rCCK0_TxFilter2 0xa24 -#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ -#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ -#define rCCK0_TRSSIReport 0xa50 -#define rCCK0_RxReport 0xa54 /* 0xa57 */ -#define rCCK0_FACounterLower 0xa5c /* 0xa5b */ -#define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ - -/* - * PageB(0xB00) - * */ -#define rPdp_AntA 0xb00 -#define rPdp_AntA_4 0xb04 -#define rPdp_AntA_8 0xb08 -#define rPdp_AntA_C 0xb0c -#define rPdp_AntA_10 0xb10 -#define rPdp_AntA_14 0xb14 -#define rPdp_AntA_18 0xb18 -#define rPdp_AntA_1C 0xb1c -#define rPdp_AntA_20 0xb20 -#define rPdp_AntA_24 0xb24 - -#define rConfig_Pmpd_AntA 0xb28 -#define rConfig_ram64x16 0xb2c - -#define rBndA 0xb30 -#define rHssiPar 0xb34 - -#define rConfig_AntA 0xb68 -#define rConfig_AntB 0xb6c - -#define rPdp_AntB 0xb70 -#define rPdp_AntB_4 0xb74 -#define rPdp_AntB_8 0xb78 -#define rPdp_AntB_C 0xb7c -#define rPdp_AntB_10 0xb80 -#define rPdp_AntB_14 0xb84 -#define rPdp_AntB_18 0xb88 -#define rPdp_AntB_1C 0xb8c -#define rPdp_AntB_20 0xb90 -#define rPdp_AntB_24 0xb94 - -#define rConfig_Pmpd_AntB 0xb98 - -#define rBndB 0xba0 - -#define rAPK 0xbd8 -#define rPm_Rx0_AntA 0xbdc -#define rPm_Rx1_AntA 0xbe0 -#define rPm_Rx2_AntA 0xbe4 -#define rPm_Rx3_AntA 0xbe8 -#define rPm_Rx0_AntB 0xbec -#define rPm_Rx1_AntB 0xbf0 -#define rPm_Rx2_AntB 0xbf4 -#define rPm_Rx3_AntB 0xbf8 -/* - * 6. PageC(0xC00) - * */ -#define rOFDM0_LSTF 0xc00 - -#define rOFDM0_TRxPathEnable 0xc04 -#define rOFDM0_TRMuxPar 0xc08 -#define rOFDM0_TRSWIsolation 0xc0c - -#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ -#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ -#define rOFDM0_XBRxAFE 0xc18 -#define rOFDM0_XBRxIQImbalance 0xc1c -#define rOFDM0_XCRxAFE 0xc20 -#define rOFDM0_XCRxIQImbalance 0xc24 -#define rOFDM0_XDRxAFE 0xc28 -#define rOFDM0_XDRxIQImbalance 0xc2c - -#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */ -#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ -#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ -#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ - -#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ -#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ -#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ -#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ - -#define rOFDM0_XAAGCCore1 0xc50 /* DIG */ -#define rOFDM0_XAAGCCore2 0xc54 -#define rOFDM0_XBAGCCore1 0xc58 -#define rOFDM0_XBAGCCore2 0xc5c -#define rOFDM0_XCAGCCore1 0xc60 -#define rOFDM0_XCAGCCore2 0xc64 -#define rOFDM0_XDAGCCore1 0xc68 -#define rOFDM0_XDAGCCore2 0xc6c - -#define rOFDM0_AGCParameter1 0xc70 -#define rOFDM0_AGCParameter2 0xc74 -#define rOFDM0_AGCRSSITable 0xc78 -#define rOFDM0_HTSTFAGC 0xc7c - -#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ -#define rOFDM0_XATxAFE 0xc84 -#define rOFDM0_XBTxIQImbalance 0xc88 -#define rOFDM0_XBTxAFE 0xc8c -#define rOFDM0_XCTxIQImbalance 0xc90 -#define rOFDM0_XCTxAFE 0xc94 -#define rOFDM0_XDTxIQImbalance 0xc98 -#define rOFDM0_XDTxAFE 0xc9c - -#define rOFDM0_RxIQExtAnta 0xca0 -#define rOFDM0_TxCoeff1 0xca4 -#define rOFDM0_TxCoeff2 0xca8 -#define rOFDM0_TxCoeff3 0xcac -#define rOFDM0_TxCoeff4 0xcb0 -#define rOFDM0_TxCoeff5 0xcb4 -#define rOFDM0_TxCoeff6 0xcb8 -#define rOFDM0_RxHPParameter 0xce0 -#define rOFDM0_TxPseudoNoiseWgt 0xce4 -#define rOFDM0_FrameSync 0xcf0 -#define rOFDM0_DFSReport 0xcf4 - -/* - * 7. PageD(0xD00) - * */ -#define rOFDM1_LSTF 0xd00 -#define rOFDM1_TRxPathEnable 0xd04 - -#define rOFDM1_CFO 0xd08 /* No setting now */ -#define rOFDM1_CSI1 0xd10 -#define rOFDM1_SBD 0xd14 -#define rOFDM1_CSI2 0xd18 -#define rOFDM1_CFOTracking 0xd2c -#define rOFDM1_TRxMesaure1 0xd34 -#define rOFDM1_IntfDet 0xd3c -#define rOFDM1_PseudoNoiseStateAB 0xd50 -#define rOFDM1_PseudoNoiseStateCD 0xd54 -#define rOFDM1_RxPseudoNoiseWgt 0xd58 - -#define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ -#define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ -#define rOFDM_PHYCounter3 0xda8 /* MCS not support */ - -#define rOFDM_ShortCFOAB 0xdac /* No setting now */ -#define rOFDM_ShortCFOCD 0xdb0 -#define rOFDM_LongCFOAB 0xdb4 -#define rOFDM_LongCFOCD 0xdb8 -#define rOFDM_TailCFOAB 0xdbc -#define rOFDM_TailCFOCD 0xdc0 -#define rOFDM_PWMeasure1 0xdc4 -#define rOFDM_PWMeasure2 0xdc8 -#define rOFDM_BWReport 0xdcc -#define rOFDM_AGCReport 0xdd0 -#define rOFDM_RxSNR 0xdd4 -#define rOFDM_RxEVMCSI 0xdd8 -#define rOFDM_SIGReport 0xddc - - -/* - * 8. PageE(0xE00) - * */ -#define rTxAGC_A_Rate18_06 0xe00 -#define rTxAGC_A_Rate54_24 0xe04 -#define rTxAGC_A_CCK1_Mcs32 0xe08 -#define rTxAGC_A_Mcs03_Mcs00 0xe10 -#define rTxAGC_A_Mcs07_Mcs04 0xe14 -#define rTxAGC_A_Mcs11_Mcs08 0xe18 -#define rTxAGC_A_Mcs15_Mcs12 0xe1c - -#define rFPGA0_IQK 0xe28 -#define rTx_IQK_Tone_A 0xe30 -#define rRx_IQK_Tone_A 0xe34 -#define rTx_IQK_PI_A 0xe38 -#define rRx_IQK_PI_A 0xe3c - -#define rTx_IQK 0xe40 -#define rRx_IQK 0xe44 -#define rIQK_AGC_Pts 0xe48 -#define rIQK_AGC_Rsp 0xe4c -#define rTx_IQK_Tone_B 0xe50 -#define rRx_IQK_Tone_B 0xe54 -#define rTx_IQK_PI_B 0xe58 -#define rRx_IQK_PI_B 0xe5c -#define rIQK_AGC_Cont 0xe60 - -#define rBlue_Tooth 0xe6c -#define rRx_Wait_CCA 0xe70 -#define rTx_CCK_RFON 0xe74 -#define rTx_CCK_BBON 0xe78 -#define rTx_OFDM_RFON 0xe7c -#define rTx_OFDM_BBON 0xe80 -#define rTx_To_Rx 0xe84 -#define rTx_To_Tx 0xe88 -#define rRx_CCK 0xe8c - -#define rTx_Power_Before_IQK_A 0xe94 -#define rTx_Power_After_IQK_A 0xe9c - -#define rRx_Power_Before_IQK_A 0xea0 -#define rRx_Power_Before_IQK_A_2 0xea4 -#define rRx_Power_After_IQK_A 0xea8 -#define rRx_Power_After_IQK_A_2 0xeac - -#define rTx_Power_Before_IQK_B 0xeb4 -#define rTx_Power_After_IQK_B 0xebc - -#define rRx_Power_Before_IQK_B 0xec0 -#define rRx_Power_Before_IQK_B_2 0xec4 -#define rRx_Power_After_IQK_B 0xec8 -#define rRx_Power_After_IQK_B_2 0xecc - -#define rRx_OFDM 0xed0 -#define rRx_Wait_RIFS 0xed4 -#define rRx_TO_Rx 0xed8 -#define rStandby 0xedc -#define rSleep 0xee0 -#define rPMPD_ANAEN 0xeec - -/* - * 7. RF Register 0x00-0x2E (RF 8256) - * RF-0222D 0x00-3F - * - * Zebra1 */ -#define rZebra1_HSSIEnable 0x0 /* Useless now */ -#define rZebra1_TRxEnable1 0x1 -#define rZebra1_TRxEnable2 0x2 -#define rZebra1_AGC 0x4 -#define rZebra1_ChargePump 0x5 -#define rZebra1_Channel 0x7 /* RF channel switch */ - -/* #endif */ -#define rZebra1_TxGain 0x8 /* Useless now */ -#define rZebra1_TxLPF 0x9 -#define rZebra1_RxLPF 0xb -#define rZebra1_RxHPFCorner 0xc - -/* Zebra4 */ -#define rGlobalCtrl 0 /* Useless now */ -#define rRTL8256_TxLPF 19 -#define rRTL8256_RxLPF 11 - -/* RTL8258 */ -#define rRTL8258_TxLPF 0x11 /* Useless now */ -#define rRTL8258_RxLPF 0x13 -#define rRTL8258_RSSILPF 0xa - -/* - * RL6052 Register definition - * */ -#define RF_AC 0x00 /* */ - -#define RF_IQADJ_G1 0x01 /* */ -#define RF_IQADJ_G2 0x02 /* */ -#define RF_BS_PA_APSET_G1_G4 0x03 -#define RF_BS_PA_APSET_G5_G8 0x04 -#define RF_POW_TRSW 0x05 /* */ - -#define RF_GAIN_RX 0x06 /* */ -#define RF_GAIN_TX 0x07 /* */ - -#define RF_TXM_IDAC 0x08 /* */ -#define RF_IPA_G 0x09 /* */ -#define RF_TXBIAS_G 0x0A -#define RF_TXPA_AG 0x0B -#define RF_IPA_A 0x0C /* */ -#define RF_TXBIAS_A 0x0D -#define RF_BS_PA_APSET_G9_G11 0x0E -#define RF_BS_IQGEN 0x0F /* */ - -#define RF_MODE1 0x10 /* */ -#define RF_MODE2 0x11 /* */ - -#define RF_RX_AGC_HP 0x12 /* */ -#define RF_TX_AGC 0x13 /* */ -#define RF_BIAS 0x14 /* */ -#define RF_IPA 0x15 /* */ -#define RF_TXBIAS 0x16 -#define RF_POW_ABILITY 0x17 /* */ -#define RF_MODE_AG 0x18 /* */ -#define rRfChannel 0x18 /* RF channel and BW switch */ -#define RF_CHNLBW 0x18 /* RF channel and BW switch */ -#define RF_TOP 0x19 /* */ - -#define RF_RX_G1 0x1A /* */ -#define RF_RX_G2 0x1B /* */ - -#define RF_RX_BB2 0x1C /* */ -#define RF_RX_BB1 0x1D /* */ - -#define RF_RCK1 0x1E /* */ -#define RF_RCK2 0x1F /* */ - -#define RF_TX_G1 0x20 /* */ -#define RF_TX_G2 0x21 /* */ -#define RF_TX_G3 0x22 /* */ - -#define RF_TX_BB1 0x23 /* */ - -#define RF_T_METER 0x24 /* */ - -#define RF_SYN_G1 0x25 /* RF TX Power control */ -#define RF_SYN_G2 0x26 /* RF TX Power control */ -#define RF_SYN_G3 0x27 /* RF TX Power control */ -#define RF_SYN_G4 0x28 /* RF TX Power control */ -#define RF_SYN_G5 0x29 /* RF TX Power control */ -#define RF_SYN_G6 0x2A /* RF TX Power control */ -#define RF_SYN_G7 0x2B /* RF TX Power control */ -#define RF_SYN_G8 0x2C /* RF TX Power control */ - -#define RF_RCK_OS 0x30 /* RF TX PA control */ - -#define RF_TXPA_G1 0x31 /* RF TX PA control */ -#define RF_TXPA_G2 0x32 /* RF TX PA control */ -#define RF_TXPA_G3 0x33 /* RF TX PA control */ -#define RF_TX_BIAS_A 0x35 -#define RF_TX_BIAS_D 0x36 -#define RF_LOBF_9 0x38 -#define RF_RXRF_A3 0x3C /* */ -#define RF_TRSW 0x3F - -#define RF_TXRF_A2 0x41 -#define RF_TXPA_G4 0x46 -#define RF_TXPA_A4 0x4B -#define RF_0x52 0x52 -#define RF_WE_LUT 0xEF -#define RF_S0S1 0xB0 - -/* - * Bit Mask - * - * 1. Page1(0x100) */ -#define bBBResetB 0x100 /* Useless now? */ -#define bGlobalResetB 0x200 -#define bOFDMTxStart 0x4 -#define bCCKTxStart 0x8 -#define bCRC32Debug 0x100 -#define bPMACLoopback 0x10 -#define bTxLSIG 0xffffff -#define bOFDMTxRate 0xf -#define bOFDMTxReserved 0x10 -#define bOFDMTxLength 0x1ffe0 -#define bOFDMTxParity 0x20000 -#define bTxHTSIG1 0xffffff -#define bTxHTMCSRate 0x7f -#define bTxHTBW 0x80 -#define bTxHTLength 0xffff00 -#define bTxHTSIG2 0xffffff -#define bTxHTSmoothing 0x1 -#define bTxHTSounding 0x2 -#define bTxHTReserved 0x4 -#define bTxHTAggreation 0x8 -#define bTxHTSTBC 0x30 -#define bTxHTAdvanceCoding 0x40 -#define bTxHTShortGI 0x80 -#define bTxHTNumberHT_LTF 0x300 -#define bTxHTCRC8 0x3fc00 -#define bCounterReset 0x10000 -#define bNumOfOFDMTx 0xffff -#define bNumOfCCKTx 0xffff0000 -#define bTxIdleInterval 0xffff -#define bOFDMService 0xffff0000 -#define bTxMACHeader 0xffffffff -#define bTxDataInit 0xff -#define bTxHTMode 0x100 -#define bTxDataType 0x30000 -#define bTxRandomSeed 0xffffffff -#define bCCKTxPreamble 0x1 -#define bCCKTxSFD 0xffff0000 -#define bCCKTxSIG 0xff -#define bCCKTxService 0xff00 -#define bCCKLengthExt 0x8000 -#define bCCKTxLength 0xffff0000 -#define bCCKTxCRC16 0xffff -#define bCCKTxStatus 0x1 -#define bOFDMTxStatus 0x2 - -#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) -#define RF_TX_GAIN_OFFSET_8703B(_val) (abs((_val)) | (((_val) > 0) ? BIT5 : 0)) - -/* 2. Page8(0x800) */ -#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ -#define bJapanMode 0x2 -#define bCCKTxSC 0x30 -#define bCCKEn 0x1000000 -#define bOFDMEn 0x2000000 - -#define bOFDMRxADCPhase 0x10000 /* Useless now */ -#define bOFDMTxDACPhase 0x40000 -#define bXATxAGC 0x3f - -#define bAntennaSelect 0x0300 - -#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ -#define bXCTxAGC 0xf000 -#define bXDTxAGC 0xf0000 - -#define bPAStart 0xf0000000 /* Useless now */ -#define bTRStart 0x00f00000 -#define bRFStart 0x0000f000 -#define bBBStart 0x000000f0 -#define bBBCCKStart 0x0000000f -#define bPAEnd 0xf /* Reg0x814 */ -#define bTREnd 0x0f000000 -#define bRFEnd 0x000f0000 -#define bCCAMask 0x000000f0 /* T2R */ -#define bR2RCCAMask 0x00000f00 -#define bHSSI_R2TDelay 0xf8000000 -#define bHSSI_T2RDelay 0xf80000 -#define bContTxHSSI 0x400 /* chane gain at continue Tx */ -#define bIGFromCCK 0x200 -#define bAGCAddress 0x3f -#define bRxHPTx 0x7000 -#define bRxHPT2R 0x38000 -#define bRxHPCCKIni 0xc0000 -#define bAGCTxCode 0xc00000 -#define bAGCRxCode 0x300000 - -#define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ -#define b3WireAddressLength 0x400 - -#define b3WireRFPowerDown 0x1 /* Useless now - * #define bHWSISelect 0x8 */ -#define b5GPAPEPolarity 0x40000000 -#define b2GPAPEPolarity 0x80000000 -#define bRFSW_TxDefaultAnt 0x3 -#define bRFSW_TxOptionAnt 0x30 -#define bRFSW_RxDefaultAnt 0x300 -#define bRFSW_RxOptionAnt 0x3000 -#define bRFSI_3WireData 0x1 -#define bRFSI_3WireClock 0x2 -#define bRFSI_3WireLoad 0x4 -#define bRFSI_3WireRW 0x8 -#define bRFSI_3Wire 0xf - -#define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ - -#define bRFSI_TRSW 0x20 /* Useless now */ -#define bRFSI_TRSWB 0x40 -#define bRFSI_ANTSW 0x100 -#define bRFSI_ANTSWB 0x200 -#define bRFSI_PAPE 0x400 -#define bRFSI_PAPE5G 0x800 -#define bBandSelect 0x1 -#define bHTSIG2_GI 0x80 -#define bHTSIG2_Smoothing 0x01 -#define bHTSIG2_Sounding 0x02 -#define bHTSIG2_Aggreaton 0x08 -#define bHTSIG2_STBC 0x30 -#define bHTSIG2_AdvCoding 0x40 -#define bHTSIG2_NumOfHTLTF 0x300 -#define bHTSIG2_CRC8 0x3fc -#define bHTSIG1_MCS 0x7f -#define bHTSIG1_BandWidth 0x80 -#define bHTSIG1_HTLength 0xffff -#define bLSIG_Rate 0xf -#define bLSIG_Reserved 0x10 -#define bLSIG_Length 0x1fffe -#define bLSIG_Parity 0x20 -#define bCCKRxPhase 0x4 - -#define bLSSIReadAddress 0x7f800000 /* T65 RF */ - -#define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ - -#define bLSSIReadBackData 0xfffff /* T65 RF */ - -#define bLSSIReadOKFlag 0x1000 /* Useless now */ -#define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ -#define bRegulator0Standby 0x1 -#define bRegulatorPLLStandby 0x2 -#define bRegulator1Standby 0x4 -#define bPLLPowerUp 0x8 -#define bDPLLPowerUp 0x10 -#define bDA10PowerUp 0x20 -#define bAD7PowerUp 0x200 -#define bDA6PowerUp 0x2000 -#define bXtalPowerUp 0x4000 -#define b40MDClkPowerUP 0x8000 -#define bDA6DebugMode 0x20000 -#define bDA6Swing 0x380000 - -#define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ - -#define b80MClkDelay 0x18000000 /* Useless */ -#define bAFEWatchDogEnable 0x20000000 - -#define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ -#define bXtalCap23 0x3 -#define bXtalCap92x 0x0f000000 -#define bXtalCap 0x0f000000 - -#define bIntDifClkEnable 0x400 /* Useless */ -#define bExtSigClkEnable 0x800 -#define bBandgapMbiasPowerUp 0x10000 -#define bAD11SHGain 0xc0000 -#define bAD11InputRange 0x700000 -#define bAD11OPCurrent 0x3800000 -#define bIPathLoopback 0x4000000 -#define bQPathLoopback 0x8000000 -#define bAFELoopback 0x10000000 -#define bDA10Swing 0x7e0 -#define bDA10Reverse 0x800 -#define bDAClkSource 0x1000 -#define bAD7InputRange 0x6000 -#define bAD7Gain 0x38000 -#define bAD7OutputCMMode 0x40000 -#define bAD7InputCMMode 0x380000 -#define bAD7Current 0xc00000 -#define bRegulatorAdjust 0x7000000 -#define bAD11PowerUpAtTx 0x1 -#define bDA10PSAtTx 0x10 -#define bAD11PowerUpAtRx 0x100 -#define bDA10PSAtRx 0x1000 -#define bCCKRxAGCFormat 0x200 -#define bPSDFFTSamplepPoint 0xc000 -#define bPSDAverageNum 0x3000 -#define bIQPathControl 0xc00 -#define bPSDFreq 0x3ff -#define bPSDAntennaPath 0x30 -#define bPSDIQSwitch 0x40 -#define bPSDRxTrigger 0x400000 -#define bPSDTxTrigger 0x80000000 -#define bPSDSineToneScale 0x7f000000 -#define bPSDReport 0xffff - -/* 3. Page9(0x900) */ -#define bOFDMTxSC 0x30000000 /* Useless */ -#define bCCKTxOn 0x1 -#define bOFDMTxOn 0x2 -#define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ -#define bDebugItem 0xff /* reset debug page and LWord */ -#define bAntL 0x10 -#define bAntNonHT 0x100 -#define bAntHT1 0x1000 -#define bAntHT2 0x10000 -#define bAntHT1S1 0x100000 -#define bAntNonHTS1 0x1000000 - -/* 4. PageA(0xA00) */ -#define bCCKBBMode 0x3 /* Useless */ -#define bCCKTxPowerSaving 0x80 -#define bCCKRxPowerSaving 0x40 - -#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ - -#define bCCKScramble 0x8 /* Useless */ -#define bCCKAntDiversity 0x8000 -#define bCCKCarrierRecovery 0x4000 -#define bCCKTxRate 0x3000 -#define bCCKDCCancel 0x0800 -#define bCCKISICancel 0x0400 -#define bCCKMatchFilter 0x0200 -#define bCCKEqualizer 0x0100 -#define bCCKPreambleDetect 0x800000 -#define bCCKFastFalseCCA 0x400000 -#define bCCKChEstStart 0x300000 -#define bCCKCCACount 0x080000 -#define bCCKcs_lim 0x070000 -#define bCCKBistMode 0x80000000 -#define bCCKCCAMask 0x40000000 -#define bCCKTxDACPhase 0x4 -#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ -#define bCCKr_cp_mode0 0x0100 -#define bCCKTxDCOffset 0xf0 -#define bCCKRxDCOffset 0xf -#define bCCKCCAMode 0xc000 -#define bCCKFalseCS_lim 0x3f00 -#define bCCKCS_ratio 0xc00000 -#define bCCKCorgBit_sel 0x300000 -#define bCCKPD_lim 0x0f0000 -#define bCCKNewCCA 0x80000000 -#define bCCKRxHPofIG 0x8000 -#define bCCKRxIG 0x7f00 -#define bCCKLNAPolarity 0x800000 -#define bCCKRx1stGain 0x7f0000 -#define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ -#define bCCKRxAGCSatLevel 0x1f000000 -#define bCCKRxAGCSatCount 0xe0 -#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ -#define bCCKFixedRxAGC 0x8000 -/* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ -#define bCCKAntennaPolarity 0x2000 -#define bCCKTxFilterType 0x0c00 -#define bCCKRxAGCReportType 0x0300 -#define bCCKRxDAGCEn 0x80000000 -#define bCCKRxDAGCPeriod 0x20000000 -#define bCCKRxDAGCSatLevel 0x1f000000 -#define bCCKTimingRecovery 0x800000 -#define bCCKTxC0 0x3f0000 -#define bCCKTxC1 0x3f000000 -#define bCCKTxC2 0x3f -#define bCCKTxC3 0x3f00 -#define bCCKTxC4 0x3f0000 -#define bCCKTxC5 0x3f000000 -#define bCCKTxC6 0x3f -#define bCCKTxC7 0x3f00 -#define bCCKDebugPort 0xff0000 -#define bCCKDACDebug 0x0f000000 -#define bCCKFalseAlarmEnable 0x8000 -#define bCCKFalseAlarmRead 0x4000 -#define bCCKTRSSI 0x7f -#define bCCKRxAGCReport 0xfe -#define bCCKRxReport_AntSel 0x80000000 -#define bCCKRxReport_MFOff 0x40000000 -#define bCCKRxRxReport_SQLoss 0x20000000 -#define bCCKRxReport_Pktloss 0x10000000 -#define bCCKRxReport_Lockedbit 0x08000000 -#define bCCKRxReport_RateError 0x04000000 -#define bCCKRxReport_RxRate 0x03000000 -#define bCCKRxFACounterLower 0xff -#define bCCKRxFACounterUpper 0xff000000 -#define bCCKRxHPAGCStart 0xe000 -#define bCCKRxHPAGCFinal 0x1c00 -#define bCCKRxFalseAlarmEnable 0x8000 -#define bCCKFACounterFreeze 0x4000 -#define bCCKTxPathSel 0x10000000 -#define bCCKDefaultRxPath 0xc000000 -#define bCCKOptionRxPath 0x3000000 - -/* 5. PageC(0xC00) */ -#define bNumOfSTF 0x3 /* Useless */ -#define bShift_L 0xc0 -#define bGI_TH 0xc -#define bRxPathA 0x1 -#define bRxPathB 0x2 -#define bRxPathC 0x4 -#define bRxPathD 0x8 -#define bTxPathA 0x1 -#define bTxPathB 0x2 -#define bTxPathC 0x4 -#define bTxPathD 0x8 -#define bTRSSIFreq 0x200 -#define bADCBackoff 0x3000 -#define bDFIRBackoff 0xc000 -#define bTRSSILatchPhase 0x10000 -#define bRxIDCOffset 0xff -#define bRxQDCOffset 0xff00 -#define bRxDFIRMode 0x1800000 -#define bRxDCNFType 0xe000000 -#define bRXIQImb_A 0x3ff -#define bRXIQImb_B 0xfc00 -#define bRXIQImb_C 0x3f0000 -#define bRXIQImb_D 0xffc00000 -#define bDC_dc_Notch 0x60000 -#define bRxNBINotch 0x1f000000 -#define bPD_TH 0xf -#define bPD_TH_Opt2 0xc000 -#define bPWED_TH 0x700 -#define bIfMF_Win_L 0x800 -#define bPD_Option 0x1000 -#define bMF_Win_L 0xe000 -#define bBW_Search_L 0x30000 -#define bwin_enh_L 0xc0000 -#define bBW_TH 0x700000 -#define bED_TH2 0x3800000 -#define bBW_option 0x4000000 -#define bRatio_TH 0x18000000 -#define bWindow_L 0xe0000000 -#define bSBD_Option 0x1 -#define bFrame_TH 0x1c -#define bFS_Option 0x60 -#define bDC_Slope_check 0x80 -#define bFGuard_Counter_DC_L 0xe00 -#define bFrame_Weight_Short 0x7000 -#define bSub_Tune 0xe00000 -#define bFrame_DC_Length 0xe000000 -#define bSBD_start_offset 0x30000000 -#define bFrame_TH_2 0x7 -#define bFrame_GI2_TH 0x38 -#define bGI2_Sync_en 0x40 -#define bSarch_Short_Early 0x300 -#define bSarch_Short_Late 0xc00 -#define bSarch_GI2_Late 0x70000 -#define bCFOAntSum 0x1 -#define bCFOAcc 0x2 -#define bCFOStartOffset 0xc -#define bCFOLookBack 0x70 -#define bCFOSumWeight 0x80 -#define bDAGCEnable 0x10000 -#define bTXIQImb_A 0x3ff -#define bTXIQImb_B 0xfc00 -#define bTXIQImb_C 0x3f0000 -#define bTXIQImb_D 0xffc00000 -#define bTxIDCOffset 0xff -#define bTxQDCOffset 0xff00 -#define bTxDFIRMode 0x10000 -#define bTxPesudoNoiseOn 0x4000000 -#define bTxPesudoNoise_A 0xff -#define bTxPesudoNoise_B 0xff00 -#define bTxPesudoNoise_C 0xff0000 -#define bTxPesudoNoise_D 0xff000000 -#define bCCADropOption 0x20000 -#define bCCADropThres 0xfff00000 -#define bEDCCA_H 0xf -#define bEDCCA_L 0xf0 -#define bLambda_ED 0x300 -#define bRxInitialGain 0x7f -#define bRxAntDivEn 0x80 -#define bRxAGCAddressForLNA 0x7f00 -#define bRxHighPowerFlow 0x8000 -#define bRxAGCFreezeThres 0xc0000 -#define bRxFreezeStep_AGC1 0x300000 -#define bRxFreezeStep_AGC2 0xc00000 -#define bRxFreezeStep_AGC3 0x3000000 -#define bRxFreezeStep_AGC0 0xc000000 -#define bRxRssi_Cmp_En 0x10000000 -#define bRxQuickAGCEn 0x20000000 -#define bRxAGCFreezeThresMode 0x40000000 -#define bRxOverFlowCheckType 0x80000000 -#define bRxAGCShift 0x7f -#define bTRSW_Tri_Only 0x80 -#define bPowerThres 0x300 -#define bRxAGCEn 0x1 -#define bRxAGCTogetherEn 0x2 -#define bRxAGCMin 0x4 -#define bRxHP_Ini 0x7 -#define bRxHP_TRLNA 0x70 -#define bRxHP_RSSI 0x700 -#define bRxHP_BBP1 0x7000 -#define bRxHP_BBP2 0x70000 -#define bRxHP_BBP3 0x700000 -#define bRSSI_H 0x7f0000 /* the threshold for high power */ -#define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ -#define bRxSettle_TRSW 0x7 -#define bRxSettle_LNA 0x38 -#define bRxSettle_RSSI 0x1c0 -#define bRxSettle_BBP 0xe00 -#define bRxSettle_RxHP 0x7000 -#define bRxSettle_AntSW_RSSI 0x38000 -#define bRxSettle_AntSW 0xc0000 -#define bRxProcessTime_DAGC 0x300000 -#define bRxSettle_HSSI 0x400000 -#define bRxProcessTime_BBPPW 0x800000 -#define bRxAntennaPowerShift 0x3000000 -#define bRSSITableSelect 0xc000000 -#define bRxHP_Final 0x7000000 -#define bRxHTSettle_BBP 0x7 -#define bRxHTSettle_HSSI 0x8 -#define bRxHTSettle_RxHP 0x70 -#define bRxHTSettle_BBPPW 0x80 -#define bRxHTSettle_Idle 0x300 -#define bRxHTSettle_Reserved 0x1c00 -#define bRxHTRxHPEn 0x8000 -#define bRxHTAGCFreezeThres 0x30000 -#define bRxHTAGCTogetherEn 0x40000 -#define bRxHTAGCMin 0x80000 -#define bRxHTAGCEn 0x100000 -#define bRxHTDAGCEn 0x200000 -#define bRxHTRxHP_BBP 0x1c00000 -#define bRxHTRxHP_Final 0xe0000000 -#define bRxPWRatioTH 0x3 -#define bRxPWRatioEn 0x4 -#define bRxMFHold 0x3800 -#define bRxPD_Delay_TH1 0x38 -#define bRxPD_Delay_TH2 0x1c0 -#define bRxPD_DC_COUNT_MAX 0x600 -/* #define bRxMF_Hold 0x3800 */ -#define bRxPD_Delay_TH 0x8000 -#define bRxProcess_Delay 0xf0000 -#define bRxSearchrange_GI2_Early 0x700000 -#define bRxFrame_Guard_Counter_L 0x3800000 -#define bRxSGI_Guard_L 0xc000000 -#define bRxSGI_Search_L 0x30000000 -#define bRxSGI_TH 0xc0000000 -#define bDFSCnt0 0xff -#define bDFSCnt1 0xff00 -#define bDFSFlag 0xf0000 -#define bMFWeightSum 0x300000 -#define bMinIdxTH 0x7f000000 -#define bDAFormat 0x40000 -#define bTxChEmuEnable 0x01000000 -#define bTRSWIsolation_A 0x7f -#define bTRSWIsolation_B 0x7f00 -#define bTRSWIsolation_C 0x7f0000 -#define bTRSWIsolation_D 0x7f000000 -#define bExtLNAGain 0x7c00 - -/* 6. PageE(0xE00) */ -#define bSTBCEn 0x4 /* Useless */ -#define bAntennaMapping 0x10 -#define bNss 0x20 -#define bCFOAntSumD 0x200 -#define bPHYCounterReset 0x8000000 -#define bCFOReportGet 0x4000000 -#define bOFDMContinueTx 0x10000000 -#define bOFDMSingleCarrier 0x20000000 -#define bOFDMSingleTone 0x40000000 -/* #define bRxPath1 0x01 */ -/* #define bRxPath2 0x02 */ -/* #define bRxPath3 0x04 */ -/* #define bRxPath4 0x08 */ -/* #define bTxPath1 0x10 */ -/* #define bTxPath2 0x20 */ -#define bHTDetect 0x100 -#define bCFOEn 0x10000 -#define bCFOValue 0xfff00000 -#define bSigTone_Re 0x3f -#define bSigTone_Im 0x7f00 -#define bCounter_CCA 0xffff -#define bCounter_ParityFail 0xffff0000 -#define bCounter_RateIllegal 0xffff -#define bCounter_CRC8Fail 0xffff0000 -#define bCounter_MCSNoSupport 0xffff -#define bCounter_FastSync 0xffff -#define bShortCFO 0xfff -#define bShortCFOTLength 12 /* total */ -#define bShortCFOFLength 11 /* fraction */ -#define bLongCFO 0x7ff -#define bLongCFOTLength 11 -#define bLongCFOFLength 11 -#define bTailCFO 0x1fff -#define bTailCFOTLength 13 -#define bTailCFOFLength 12 -#define bmax_en_pwdB 0xffff -#define bCC_power_dB 0xffff0000 -#define bnoise_pwdB 0xffff -#define bPowerMeasTLength 10 -#define bPowerMeasFLength 3 -#define bRx_HT_BW 0x1 -#define bRxSC 0x6 -#define bRx_HT 0x8 -#define bNB_intf_det_on 0x1 -#define bIntf_win_len_cfg 0x30 -#define bNB_Intf_TH_cfg 0x1c0 -#define bRFGain 0x3f -#define bTableSel 0x40 -#define bTRSW 0x80 -#define bRxSNR_A 0xff -#define bRxSNR_B 0xff00 -#define bRxSNR_C 0xff0000 -#define bRxSNR_D 0xff000000 -#define bSNREVMTLength 8 -#define bSNREVMFLength 1 -#define bCSI1st 0xff -#define bCSI2nd 0xff00 -#define bRxEVM1st 0xff0000 -#define bRxEVM2nd 0xff000000 -#define bSIGEVM 0xff -#define bPWDB 0xff00 -#define bSGIEN 0x10000 - -#define bSFactorQAM1 0xf /* Useless */ -#define bSFactorQAM2 0xf0 -#define bSFactorQAM3 0xf00 -#define bSFactorQAM4 0xf000 -#define bSFactorQAM5 0xf0000 -#define bSFactorQAM6 0xf0000 -#define bSFactorQAM7 0xf00000 -#define bSFactorQAM8 0xf000000 -#define bSFactorQAM9 0xf0000000 -#define bCSIScheme 0x100000 - -#define bNoiseLvlTopSet 0x3 /* Useless */ -#define bChSmooth 0x4 -#define bChSmoothCfg1 0x38 -#define bChSmoothCfg2 0x1c0 -#define bChSmoothCfg3 0xe00 -#define bChSmoothCfg4 0x7000 -#define bMRCMode 0x800000 -#define bTHEVMCfg 0x7000000 - -#define bLoopFitType 0x1 /* Useless */ -#define bUpdCFO 0x40 -#define bUpdCFOOffData 0x80 -#define bAdvUpdCFO 0x100 -#define bAdvTimeCtrl 0x800 -#define bUpdClko 0x1000 -#define bFC 0x6000 -#define bTrackingMode 0x8000 -#define bPhCmpEnable 0x10000 -#define bUpdClkoLTF 0x20000 -#define bComChCFO 0x40000 -#define bCSIEstiMode 0x80000 -#define bAdvUpdEqz 0x100000 -#define bUChCfg 0x7000000 -#define bUpdEqz 0x8000000 - -/* Rx Pseduo noise */ -#define bRxPesudoNoiseOn 0x20000000 /* Useless */ -#define bRxPesudoNoise_A 0xff -#define bRxPesudoNoise_B 0xff00 -#define bRxPesudoNoise_C 0xff0000 -#define bRxPesudoNoise_D 0xff000000 -#define bPesudoNoiseState_A 0xffff -#define bPesudoNoiseState_B 0xffff0000 -#define bPesudoNoiseState_C 0xffff -#define bPesudoNoiseState_D 0xffff0000 - -/* 7. RF Register - * Zebra1 */ -#define bZebra1_HSSIEnable 0x8 /* Useless */ -#define bZebra1_TRxControl 0xc00 -#define bZebra1_TRxGainSetting 0x07f -#define bZebra1_RxCorner 0xc00 -#define bZebra1_TxChargePump 0x38 -#define bZebra1_RxChargePump 0x7 -#define bZebra1_ChannelNum 0xf80 -#define bZebra1_TxLPFBW 0x400 -#define bZebra1_RxLPFBW 0x600 - -/* Zebra4 */ -#define bRTL8256RegModeCtrl1 0x100 /* Useless */ -#define bRTL8256RegModeCtrl0 0x40 -#define bRTL8256_TxLPFBW 0x18 -#define bRTL8256_RxLPFBW 0x600 - -/* RTL8258 */ -#define bRTL8258_TxLPFBW 0xc /* Useless */ -#define bRTL8258_RxLPFBW 0xc00 -#define bRTL8258_RSSILPFBW 0xc0 - - -/* - * Other Definition - * */ - -/* byte endable for sb_write */ -#define bByte0 0x1 /* Useless */ -#define bByte1 0x2 -#define bByte2 0x4 -#define bByte3 0x8 -#define bWord0 0x3 -#define bWord1 0xc -#define bDWord 0xf - -/* for PutRegsetting & GetRegSetting BitMask */ -#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ -#define bMaskByte1 0xff00 -#define bMaskByte2 0xff0000 -#define bMaskByte3 0xff000000 -#define bMaskHWord 0xffff0000 -#define bMaskLWord 0x0000ffff -#define bMaskDWord 0xffffffff -#define bMaskH3Bytes 0xffffff00 -#define bMask12Bits 0xfff -#define bMaskH4Bits 0xf0000000 -#define bMaskOFDM_D 0xffc00000 -#define bMaskCCK 0x3f3f3f3f - - -#define bEnable 0x1 /* Useless */ -#define bDisable 0x0 - -#define LeftAntenna 0x0 /* Useless */ -#define RightAntenna 0x1 - -#define tCheckTxStatus 500 /* 500ms */ /* Useless */ -#define tUpdateRxCounter 100 /* 100ms */ - -#define rateCCK 0 /* Useless */ -#define rateOFDM 1 -#define rateHT 2 - -/* define Register-End */ -#define bPMAC_End 0x1ff /* Useless */ -#define bFPGAPHY0_End 0x8ff -#define bFPGAPHY1_End 0x9ff -#define bCCKPHY0_End 0xaff -#define bOFDMPHY0_End 0xcff -#define bOFDMPHY1_End 0xdff - -/* define max debug item in each debug page - * #define bMaxItem_FPGA_PHY0 0x9 - * #define bMaxItem_FPGA_PHY1 0x3 - * #define bMaxItem_PHY_11B 0x16 - * #define bMaxItem_OFDM_PHY0 0x29 - * #define bMaxItem_OFDM_PHY1 0x0 */ - -#define bPMACControl 0x0 /* Useless */ -#define bWMACControl 0x1 -#define bWNICControl 0x2 - -#define PathA 0x0 /* Useless */ -#define PathB 0x1 -#define PathC 0x2 -#define PathD 0x3 - -#endif diff --git a/include/Hal8703BPwrSeq.h b/include/Hal8703BPwrSeq.h deleted file mode 100644 index a53ca9a..0000000 --- a/include/Hal8703BPwrSeq.h +++ /dev/null @@ -1,184 +0,0 @@ -#ifndef REALTEK_POWER_SEQUENCE_8703B -#define REALTEK_POWER_SEQUENCE_8703B - -#include "HalPwrSeqCmd.h" - -/* - Check document WM-20140402-JackieLau-RTL8703B_Power_Architecture v09.vsd - There are 6 HW Power States: - 0: POFF--Power Off - 1: PDN--Power Down - 2: CARDEMU--Card Emulation - 3: ACT--Active Mode - 4: LPS--Low Power State - 5: SUS--Suspend - - The transision from different states are defined below - TRANS_CARDEMU_TO_ACT - TRANS_ACT_TO_CARDEMU - TRANS_CARDEMU_TO_SUS - TRANS_SUS_TO_CARDEMU - TRANS_CARDEMU_TO_PDN - TRANS_ACT_TO_LPS - TRANS_LPS_TO_ACT - - TRANS_END -*/ -#define RTL8703B_TRANS_CARDEMU_TO_ACT_STEPS 23 -#define RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS 15 -#define RTL8703B_TRANS_CARDEMU_TO_SUS_STEPS 15 -#define RTL8703B_TRANS_SUS_TO_CARDEMU_STEPS 15 -#define RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS 15 -#define RTL8703B_TRANS_PDN_TO_CARDEMU_STEPS 15 -#define RTL8703B_TRANS_ACT_TO_LPS_STEPS 15 -#define RTL8703B_TRANS_LPS_TO_ACT_STEPS 15 -#define RTL8703B_TRANS_END_STEPS 1 - - -#define RTL8703B_TRANS_CARDEMU_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ - {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \ - {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \ - {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3 | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \ - {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */ \ - {0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 , BIT3},/* enabled usb resume */ \ - {0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 , 0},/* disable usb resume */ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ - {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \ - {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/ \ - {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\ - {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\ - {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\ - {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\ - {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\ - {0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 internal pull high setting by test chip*/\ - {0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\ - - -#define RTL8703B_TRANS_ACT_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ - {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ - {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/\ - {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \ - {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\ - - -#define RTL8703B_TRANS_CARDEMU_TO_SUS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ - -#define RTL8703B_TRANS_SUS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ - -#define RTL8703B_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \ - {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ - -#define RTL8703B_TRANS_CARDDIS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ - {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ - - -#define RTL8703B_TRANS_CARDEMU_TO_PDN \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ - -#define RTL8703B_TRANS_PDN_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ - -#define RTL8703B_TRANS_ACT_TO_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ - {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ - {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \ - {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \ - - -#define RTL8703B_TRANS_LPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ - {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ - {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ - {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ - {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ - -#define RTL8703B_TRANS_END \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0}, - - - extern WLAN_PWR_CFG rtl8703B_power_on_flow[RTL8703B_TRANS_CARDEMU_TO_ACT_STEPS + RTL8703B_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8703B_radio_off_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8703B_card_disable_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8703B_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8703B_card_enable_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8703B_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8703B_suspend_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8703B_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8703B_resume_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8703B_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8703B_hwpdn_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8703B_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8703B_enter_lps_flow[RTL8703B_TRANS_ACT_TO_LPS_STEPS + RTL8703B_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8703B_leave_lps_flow[RTL8703B_TRANS_LPS_TO_ACT_STEPS + RTL8703B_TRANS_END_STEPS]; - -#endif diff --git a/include/Hal8723BPhyCfg.h b/include/Hal8723BPhyCfg.h deleted file mode 100644 index 0fa8964..0000000 --- a/include/Hal8723BPhyCfg.h +++ /dev/null @@ -1,137 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_HAL8723BPHYCFG_H__ -#define __INC_HAL8723BPHYCFG_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#define LOOP_LIMIT 5 -#define MAX_STALL_TIME 50 /* us */ -#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */ -#define MAX_TXPWR_IDX_NMODE_92S 63 -#define Reset_Cnt_Limit 3 - -#ifdef CONFIG_PCI_HCI - #define MAX_AGGR_NUM 0x0B -#else - #define MAX_AGGR_NUM 0x07 -#endif /* CONFIG_PCI_HCI */ - - -/*--------------------------Define Parameters End-------------------------------*/ - - -/*------------------------------Define structure----------------------------*/ - -/*------------------------------Define structure End----------------------------*/ - -/*--------------------------Exported Function prototype---------------------*/ -u32 -PHY_QueryBBReg_8723B( - IN PADAPTER Adapter, - IN u32 RegAddr, - IN u32 BitMask -); - -VOID -PHY_SetBBReg_8723B( - IN PADAPTER Adapter, - IN u32 RegAddr, - IN u32 BitMask, - IN u32 Data -); - -u32 -PHY_QueryRFReg_8723B( - IN PADAPTER Adapter, - IN u8 eRFPath, - IN u32 RegAddr, - IN u32 BitMask -); - -VOID -PHY_SetRFReg_8723B( - IN PADAPTER Adapter, - IN u8 eRFPath, - IN u32 RegAddr, - IN u32 BitMask, - IN u32 Data -); - -/* MAC/BB/RF HAL config */ -int PHY_BBConfig8723B(PADAPTER Adapter); - -int PHY_RFConfig8723B(PADAPTER Adapter); - -s32 PHY_MACConfig8723B(PADAPTER padapter); - -int -PHY_ConfigRFWithParaFile_8723B( - IN PADAPTER Adapter, - IN u8 *pFileName, - RF_PATH eRFPath -); - -VOID -PHY_SetTxPowerIndex_8723B( - IN PADAPTER Adapter, - IN u32 PowerIndex, - IN u8 RFPath, - IN u8 Rate -); - -u8 -PHY_GetTxPowerIndex_8723B( - IN PADAPTER pAdapter, - IN u8 RFPath, - IN u8 Rate, - IN u8 BandWidth, - IN u8 Channel, - struct txpwr_idx_comp *tic -); - -VOID -PHY_GetTxPowerLevel8723B( - IN PADAPTER Adapter, - OUT s32 *powerlevel -); - -VOID -PHY_SetTxPowerLevel8723B( - IN PADAPTER Adapter, - IN u8 channel -); - -VOID -PHY_SetSwChnlBWMode8723B( - IN PADAPTER Adapter, - IN u8 channel, - IN CHANNEL_WIDTH Bandwidth, - IN u8 Offset40, - IN u8 Offset80 -); - -VOID phy_set_rf_path_switch_8723b( - IN PADAPTER pAdapter, - IN bool bMain -); - -/*--------------------------Exported Function prototype End---------------------*/ - -#endif diff --git a/include/Hal8723BPhyReg.h b/include/Hal8723BPhyReg.h deleted file mode 100644 index 551c0a5..0000000 --- a/include/Hal8723BPhyReg.h +++ /dev/null @@ -1,1136 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_HAL8723BPHYREG_H__ -#define __INC_HAL8723BPHYREG_H__ - -#define rSYM_WLBT_PAPE_SEL 0x64 -/* - * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF - * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF - * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 - * 3. RF register 0x00-2E - * 4. Bit Mask for BB/RF register - * 5. Other defintion for BB/RF R/W - * */ - - -/* - * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF - * 1. Page1(0x100) - * */ -#define rPMAC_Reset 0x100 -#define rPMAC_TxStart 0x104 -#define rPMAC_TxLegacySIG 0x108 -#define rPMAC_TxHTSIG1 0x10c -#define rPMAC_TxHTSIG2 0x110 -#define rPMAC_PHYDebug 0x114 -#define rPMAC_TxPacketNum 0x118 -#define rPMAC_TxIdle 0x11c -#define rPMAC_TxMACHeader0 0x120 -#define rPMAC_TxMACHeader1 0x124 -#define rPMAC_TxMACHeader2 0x128 -#define rPMAC_TxMACHeader3 0x12c -#define rPMAC_TxMACHeader4 0x130 -#define rPMAC_TxMACHeader5 0x134 -#define rPMAC_TxDataType 0x138 -#define rPMAC_TxRandomSeed 0x13c -#define rPMAC_CCKPLCPPreamble 0x140 -#define rPMAC_CCKPLCPHeader 0x144 -#define rPMAC_CCKCRC16 0x148 -#define rPMAC_OFDMRxCRC32OK 0x170 -#define rPMAC_OFDMRxCRC32Er 0x174 -#define rPMAC_OFDMRxParityEr 0x178 -#define rPMAC_OFDMRxCRC8Er 0x17c -#define rPMAC_CCKCRxRC16Er 0x180 -#define rPMAC_CCKCRxRC32Er 0x184 -#define rPMAC_CCKCRxRC32OK 0x188 -#define rPMAC_TxStatus 0x18c - -/* - * 2. Page2(0x200) - * - * The following two definition are only used for USB interface. */ -#define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */ -#define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */ - -/* - * 3. Page8(0x800) - * */ -#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */ - -#define rFPGA0_TxInfo 0x804 /* Status report?? */ -#define rFPGA0_PSDFunction 0x808 - -#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ - -#define rFPGA0_RFTiming1 0x810 /* Useless now */ -#define rFPGA0_RFTiming2 0x814 - -#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ -#define rFPGA0_XA_HSSIParameter2 0x824 -#define rFPGA0_XB_HSSIParameter1 0x828 -#define rFPGA0_XB_HSSIParameter2 0x82c -#define rTxAGC_B_Rate18_06 0x830 -#define rTxAGC_B_Rate54_24 0x834 -#define rTxAGC_B_CCK1_55_Mcs32 0x838 -#define rTxAGC_B_Mcs03_Mcs00 0x83c - -#define rTxAGC_B_Mcs07_Mcs04 0x848 -#define rTxAGC_B_Mcs11_Mcs08 0x84c - -#define rFPGA0_XA_LSSIParameter 0x840 -#define rFPGA0_XB_LSSIParameter 0x844 - -#define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ -#define rFPGA0_RFSleepUpParameter 0x854 - -#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ -#define rFPGA0_XCD_SwitchControl 0x85c - -#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ -#define rFPGA0_XB_RFInterfaceOE 0x864 - -#define rTxAGC_B_Mcs15_Mcs12 0x868 -#define rTxAGC_B_CCK11_A_CCK2_11 0x86c - -#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ -#define rFPGA0_XCD_RFInterfaceSW 0x874 - -#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ -#define rFPGA0_XCD_RFParameter 0x87c - -#define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ -#define rFPGA0_AnalogParameter2 0x884 -#define rFPGA0_AnalogParameter3 0x888 /* Useless now */ -#define rFPGA0_AnalogParameter4 0x88c - -#define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ -#define rFPGA0_XB_LSSIReadBack 0x8a4 -#define rFPGA0_XC_LSSIReadBack 0x8a8 -#define rFPGA0_XD_LSSIReadBack 0x8ac - -#define rFPGA0_PSDReport 0x8b4 /* Useless now */ -#define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ -#define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ -#define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ /* RF Interface Readback Value */ -#define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ - -/* - * 4. Page9(0x900) - * */ -#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */ -#define rFPGA1_TxBlock 0x904 /* Useless now */ -#define rFPGA1_DebugSelect 0x908 /* Useless now */ -#define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */ -#define rDPDT_control 0x92c -#define rfe_ctrl_anta_src 0x930 -#define rS0S1_PathSwitch 0x948 - -/* - * 5. PageA(0xA00) - * - * Set Control channel to upper or lower. These settings are required only for 40MHz */ -#define rCCK0_System 0xa00 - -#define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */ -#define rCCK0_CCA 0xa08 /* Disable init gain now */ /* Init gain */ - -#define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ -#define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ - -#define rCCK0_RxHP 0xa14 - -#define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ -#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ - -#define rCCK0_TxFilter1 0xa20 -#define rCCK0_TxFilter2 0xa24 -#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ -#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ -#define rCCK0_TRSSIReport 0xa50 -#define rCCK0_RxReport 0xa54 /* 0xa57 */ -#define rCCK0_FACounterLower 0xa5c /* 0xa5b */ -#define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ - -/* - * PageB(0xB00) - * */ -#define rPdp_AntA 0xb00 -#define rPdp_AntA_4 0xb04 -#define rPdp_AntA_8 0xb08 -#define rPdp_AntA_C 0xb0c -#define rPdp_AntA_10 0xb10 -#define rPdp_AntA_14 0xb14 -#define rPdp_AntA_18 0xb18 -#define rPdp_AntA_1C 0xb1c -#define rPdp_AntA_20 0xb20 -#define rPdp_AntA_24 0xb24 - -#define rConfig_Pmpd_AntA 0xb28 -#define rConfig_ram64x16 0xb2c - -#define rBndA 0xb30 -#define rHssiPar 0xb34 - -#define rConfig_AntA 0xb68 -#define rConfig_AntB 0xb6c - -#define rPdp_AntB 0xb70 -#define rPdp_AntB_4 0xb74 -#define rPdp_AntB_8 0xb78 -#define rPdp_AntB_C 0xb7c -#define rPdp_AntB_10 0xb80 -#define rPdp_AntB_14 0xb84 -#define rPdp_AntB_18 0xb88 -#define rPdp_AntB_1C 0xb8c -#define rPdp_AntB_20 0xb90 -#define rPdp_AntB_24 0xb94 - -#define rConfig_Pmpd_AntB 0xb98 - -#define rBndB 0xba0 - -#define rAPK 0xbd8 -#define rPm_Rx0_AntA 0xbdc -#define rPm_Rx1_AntA 0xbe0 -#define rPm_Rx2_AntA 0xbe4 -#define rPm_Rx3_AntA 0xbe8 -#define rPm_Rx0_AntB 0xbec -#define rPm_Rx1_AntB 0xbf0 -#define rPm_Rx2_AntB 0xbf4 -#define rPm_Rx3_AntB 0xbf8 -/* - * 6. PageC(0xC00) - * */ -#define rOFDM0_LSTF 0xc00 - -#define rOFDM0_TRxPathEnable 0xc04 -#define rOFDM0_TRMuxPar 0xc08 -#define rOFDM0_TRSWIsolation 0xc0c - -#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ -#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ -#define rOFDM0_XBRxAFE 0xc18 -#define rOFDM0_XBRxIQImbalance 0xc1c -#define rOFDM0_XCRxAFE 0xc20 -#define rOFDM0_XCRxIQImbalance 0xc24 -#define rOFDM0_XDRxAFE 0xc28 -#define rOFDM0_XDRxIQImbalance 0xc2c - -#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */ -#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ -#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ -#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ - -#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ -#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ -#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ -#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ - -#define rOFDM0_XAAGCCore1 0xc50 /* DIG */ -#define rOFDM0_XAAGCCore2 0xc54 -#define rOFDM0_XBAGCCore1 0xc58 -#define rOFDM0_XBAGCCore2 0xc5c -#define rOFDM0_XCAGCCore1 0xc60 -#define rOFDM0_XCAGCCore2 0xc64 -#define rOFDM0_XDAGCCore1 0xc68 -#define rOFDM0_XDAGCCore2 0xc6c - -#define rOFDM0_AGCParameter1 0xc70 -#define rOFDM0_AGCParameter2 0xc74 -#define rOFDM0_AGCRSSITable 0xc78 -#define rOFDM0_HTSTFAGC 0xc7c - -#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ -#define rOFDM0_XATxAFE 0xc84 -#define rOFDM0_XBTxIQImbalance 0xc88 -#define rOFDM0_XBTxAFE 0xc8c -#define rOFDM0_XCTxIQImbalance 0xc90 -#define rOFDM0_XCTxAFE 0xc94 -#define rOFDM0_XDTxIQImbalance 0xc98 -#define rOFDM0_XDTxAFE 0xc9c - -#define rOFDM0_RxIQExtAnta 0xca0 -#define rOFDM0_TxCoeff1 0xca4 -#define rOFDM0_TxCoeff2 0xca8 -#define rOFDM0_TxCoeff3 0xcac -#define rOFDM0_TxCoeff4 0xcb0 -#define rOFDM0_TxCoeff5 0xcb4 -#define rOFDM0_TxCoeff6 0xcb8 -#define rOFDM0_RxHPParameter 0xce0 -#define rOFDM0_TxPseudoNoiseWgt 0xce4 -#define rOFDM0_FrameSync 0xcf0 -#define rOFDM0_DFSReport 0xcf4 - -/* - * 7. PageD(0xD00) - * */ -#define rOFDM1_LSTF 0xd00 -#define rOFDM1_TRxPathEnable 0xd04 - -#define rOFDM1_CFO 0xd08 /* No setting now */ -#define rOFDM1_CSI1 0xd10 -#define rOFDM1_SBD 0xd14 -#define rOFDM1_CSI2 0xd18 -#define rOFDM1_CFOTracking 0xd2c -#define rOFDM1_TRxMesaure1 0xd34 -#define rOFDM1_IntfDet 0xd3c -#define rOFDM1_PseudoNoiseStateAB 0xd50 -#define rOFDM1_PseudoNoiseStateCD 0xd54 -#define rOFDM1_RxPseudoNoiseWgt 0xd58 - -#define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ -#define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ -#define rOFDM_PHYCounter3 0xda8 /* MCS not support */ - -#define rOFDM_ShortCFOAB 0xdac /* No setting now */ -#define rOFDM_ShortCFOCD 0xdb0 -#define rOFDM_LongCFOAB 0xdb4 -#define rOFDM_LongCFOCD 0xdb8 -#define rOFDM_TailCFOAB 0xdbc -#define rOFDM_TailCFOCD 0xdc0 -#define rOFDM_PWMeasure1 0xdc4 -#define rOFDM_PWMeasure2 0xdc8 -#define rOFDM_BWReport 0xdcc -#define rOFDM_AGCReport 0xdd0 -#define rOFDM_RxSNR 0xdd4 -#define rOFDM_RxEVMCSI 0xdd8 -#define rOFDM_SIGReport 0xddc - - -/* - * 8. PageE(0xE00) - * */ -#define rTxAGC_A_Rate18_06 0xe00 -#define rTxAGC_A_Rate54_24 0xe04 -#define rTxAGC_A_CCK1_Mcs32 0xe08 -#define rTxAGC_A_Mcs03_Mcs00 0xe10 -#define rTxAGC_A_Mcs07_Mcs04 0xe14 -#define rTxAGC_A_Mcs11_Mcs08 0xe18 -#define rTxAGC_A_Mcs15_Mcs12 0xe1c - -#define rFPGA0_IQK 0xe28 -#define rTx_IQK_Tone_A 0xe30 -#define rRx_IQK_Tone_A 0xe34 -#define rTx_IQK_PI_A 0xe38 -#define rRx_IQK_PI_A 0xe3c - -#define rTx_IQK 0xe40 -#define rRx_IQK 0xe44 -#define rIQK_AGC_Pts 0xe48 -#define rIQK_AGC_Rsp 0xe4c -#define rTx_IQK_Tone_B 0xe50 -#define rRx_IQK_Tone_B 0xe54 -#define rTx_IQK_PI_B 0xe58 -#define rRx_IQK_PI_B 0xe5c -#define rIQK_AGC_Cont 0xe60 - -#define rBlue_Tooth 0xe6c -#define rRx_Wait_CCA 0xe70 -#define rTx_CCK_RFON 0xe74 -#define rTx_CCK_BBON 0xe78 -#define rTx_OFDM_RFON 0xe7c -#define rTx_OFDM_BBON 0xe80 -#define rTx_To_Rx 0xe84 -#define rTx_To_Tx 0xe88 -#define rRx_CCK 0xe8c - -#define rTx_Power_Before_IQK_A 0xe94 -#define rTx_Power_After_IQK_A 0xe9c - -#define rRx_Power_Before_IQK_A 0xea0 -#define rRx_Power_Before_IQK_A_2 0xea4 -#define rRx_Power_After_IQK_A 0xea8 -#define rRx_Power_After_IQK_A_2 0xeac - -#define rTx_Power_Before_IQK_B 0xeb4 -#define rTx_Power_After_IQK_B 0xebc - -#define rRx_Power_Before_IQK_B 0xec0 -#define rRx_Power_Before_IQK_B_2 0xec4 -#define rRx_Power_After_IQK_B 0xec8 -#define rRx_Power_After_IQK_B_2 0xecc - -#define rRx_OFDM 0xed0 -#define rRx_Wait_RIFS 0xed4 -#define rRx_TO_Rx 0xed8 -#define rStandby 0xedc -#define rSleep 0xee0 -#define rPMPD_ANAEN 0xeec - -/* - * 7. RF Register 0x00-0x2E (RF 8256) - * RF-0222D 0x00-3F - * - * Zebra1 */ -#define rZebra1_HSSIEnable 0x0 /* Useless now */ -#define rZebra1_TRxEnable1 0x1 -#define rZebra1_TRxEnable2 0x2 -#define rZebra1_AGC 0x4 -#define rZebra1_ChargePump 0x5 -#define rZebra1_Channel 0x7 /* RF channel switch */ - -/* #endif */ -#define rZebra1_TxGain 0x8 /* Useless now */ -#define rZebra1_TxLPF 0x9 -#define rZebra1_RxLPF 0xb -#define rZebra1_RxHPFCorner 0xc - -/* Zebra4 */ -#define rGlobalCtrl 0 /* Useless now */ -#define rRTL8256_TxLPF 19 -#define rRTL8256_RxLPF 11 - -/* RTL8258 */ -#define rRTL8258_TxLPF 0x11 /* Useless now */ -#define rRTL8258_RxLPF 0x13 -#define rRTL8258_RSSILPF 0xa - -/* - * RL6052 Register definition - * */ -#define RF_AC 0x00 /* */ - -#define RF_IQADJ_G1 0x01 /* */ -#define RF_IQADJ_G2 0x02 /* */ -#define RF_BS_PA_APSET_G1_G4 0x03 -#define RF_BS_PA_APSET_G5_G8 0x04 -#define RF_POW_TRSW 0x05 /* */ - -#define RF_GAIN_RX 0x06 /* */ -#define RF_GAIN_TX 0x07 /* */ - -#define RF_TXM_IDAC 0x08 /* */ -#define RF_IPA_G 0x09 /* */ -#define RF_TXBIAS_G 0x0A -#define RF_TXPA_AG 0x0B -#define RF_IPA_A 0x0C /* */ -#define RF_TXBIAS_A 0x0D -#define RF_BS_PA_APSET_G9_G11 0x0E -#define RF_BS_IQGEN 0x0F /* */ - -#define RF_MODE1 0x10 /* */ -#define RF_MODE2 0x11 /* */ - -#define RF_RX_AGC_HP 0x12 /* */ -#define RF_TX_AGC 0x13 /* */ -#define RF_BIAS 0x14 /* */ -#define RF_IPA 0x15 /* */ -#define RF_TXBIAS 0x16 -#define RF_POW_ABILITY 0x17 /* */ -#define RF_MODE_AG 0x18 /* */ -#define rRfChannel 0x18 /* RF channel and BW switch */ -#define RF_CHNLBW 0x18 /* RF channel and BW switch */ -#define RF_TOP 0x19 /* */ - -#define RF_RX_G1 0x1A /* */ -#define RF_RX_G2 0x1B /* */ - -#define RF_RX_BB2 0x1C /* */ -#define RF_RX_BB1 0x1D /* */ - -#define RF_RCK1 0x1E /* */ -#define RF_RCK2 0x1F /* */ - -#define RF_TX_G1 0x20 /* */ -#define RF_TX_G2 0x21 /* */ -#define RF_TX_G3 0x22 /* */ - -#define RF_TX_BB1 0x23 /* */ - -#define RF_T_METER 0x24 /* */ - -#define RF_SYN_G1 0x25 /* RF TX Power control */ -#define RF_SYN_G2 0x26 /* RF TX Power control */ -#define RF_SYN_G3 0x27 /* RF TX Power control */ -#define RF_SYN_G4 0x28 /* RF TX Power control */ -#define RF_SYN_G5 0x29 /* RF TX Power control */ -#define RF_SYN_G6 0x2A /* RF TX Power control */ -#define RF_SYN_G7 0x2B /* RF TX Power control */ -#define RF_SYN_G8 0x2C /* RF TX Power control */ - -#define RF_RCK_OS 0x30 /* RF TX PA control */ - -#define RF_TXPA_G1 0x31 /* RF TX PA control */ -#define RF_TXPA_G2 0x32 /* RF TX PA control */ -#define RF_TXPA_G3 0x33 /* RF TX PA control */ -#define RF_TX_BIAS_A 0x35 -#define RF_TX_BIAS_D 0x36 -#define RF_LOBF_9 0x38 -#define RF_RXRF_A3 0x3C /* */ -#define RF_TRSW 0x3F - -#define RF_TXRF_A2 0x41 -#define RF_TXPA_G4 0x46 -#define RF_TXPA_A4 0x4B -#define RF_0x52 0x52 -#define RF_WE_LUT 0xEF -#define RF_S0S1 0xB0 - -/* - * Bit Mask - * - * 1. Page1(0x100) */ -#define bBBResetB 0x100 /* Useless now? */ -#define bGlobalResetB 0x200 -#define bOFDMTxStart 0x4 -#define bCCKTxStart 0x8 -#define bCRC32Debug 0x100 -#define bPMACLoopback 0x10 -#define bTxLSIG 0xffffff -#define bOFDMTxRate 0xf -#define bOFDMTxReserved 0x10 -#define bOFDMTxLength 0x1ffe0 -#define bOFDMTxParity 0x20000 -#define bTxHTSIG1 0xffffff -#define bTxHTMCSRate 0x7f -#define bTxHTBW 0x80 -#define bTxHTLength 0xffff00 -#define bTxHTSIG2 0xffffff -#define bTxHTSmoothing 0x1 -#define bTxHTSounding 0x2 -#define bTxHTReserved 0x4 -#define bTxHTAggreation 0x8 -#define bTxHTSTBC 0x30 -#define bTxHTAdvanceCoding 0x40 -#define bTxHTShortGI 0x80 -#define bTxHTNumberHT_LTF 0x300 -#define bTxHTCRC8 0x3fc00 -#define bCounterReset 0x10000 -#define bNumOfOFDMTx 0xffff -#define bNumOfCCKTx 0xffff0000 -#define bTxIdleInterval 0xffff -#define bOFDMService 0xffff0000 -#define bTxMACHeader 0xffffffff -#define bTxDataInit 0xff -#define bTxHTMode 0x100 -#define bTxDataType 0x30000 -#define bTxRandomSeed 0xffffffff -#define bCCKTxPreamble 0x1 -#define bCCKTxSFD 0xffff0000 -#define bCCKTxSIG 0xff -#define bCCKTxService 0xff00 -#define bCCKLengthExt 0x8000 -#define bCCKTxLength 0xffff0000 -#define bCCKTxCRC16 0xffff -#define bCCKTxStatus 0x1 -#define bOFDMTxStatus 0x2 - -#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) - -/* 2. Page8(0x800) */ -#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ -#define bJapanMode 0x2 -#define bCCKTxSC 0x30 -#define bCCKEn 0x1000000 -#define bOFDMEn 0x2000000 - -#define bOFDMRxADCPhase 0x10000 /* Useless now */ -#define bOFDMTxDACPhase 0x40000 -#define bXATxAGC 0x3f - -#define bAntennaSelect 0x0300 - -#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ -#define bXCTxAGC 0xf000 -#define bXDTxAGC 0xf0000 - -#define bPAStart 0xf0000000 /* Useless now */ -#define bTRStart 0x00f00000 -#define bRFStart 0x0000f000 -#define bBBStart 0x000000f0 -#define bBBCCKStart 0x0000000f -#define bPAEnd 0xf /* Reg0x814 */ -#define bTREnd 0x0f000000 -#define bRFEnd 0x000f0000 -#define bCCAMask 0x000000f0 /* T2R */ -#define bR2RCCAMask 0x00000f00 -#define bHSSI_R2TDelay 0xf8000000 -#define bHSSI_T2RDelay 0xf80000 -#define bContTxHSSI 0x400 /* chane gain at continue Tx */ -#define bIGFromCCK 0x200 -#define bAGCAddress 0x3f -#define bRxHPTx 0x7000 -#define bRxHPT2R 0x38000 -#define bRxHPCCKIni 0xc0000 -#define bAGCTxCode 0xc00000 -#define bAGCRxCode 0x300000 - -#define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ -#define b3WireAddressLength 0x400 - -#define b3WireRFPowerDown 0x1 /* Useless now - * #define bHWSISelect 0x8 */ -#define b5GPAPEPolarity 0x40000000 -#define b2GPAPEPolarity 0x80000000 -#define bRFSW_TxDefaultAnt 0x3 -#define bRFSW_TxOptionAnt 0x30 -#define bRFSW_RxDefaultAnt 0x300 -#define bRFSW_RxOptionAnt 0x3000 -#define bRFSI_3WireData 0x1 -#define bRFSI_3WireClock 0x2 -#define bRFSI_3WireLoad 0x4 -#define bRFSI_3WireRW 0x8 -#define bRFSI_3Wire 0xf - -#define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ - -#define bRFSI_TRSW 0x20 /* Useless now */ -#define bRFSI_TRSWB 0x40 -#define bRFSI_ANTSW 0x100 -#define bRFSI_ANTSWB 0x200 -#define bRFSI_PAPE 0x400 -#define bRFSI_PAPE5G 0x800 -#define bBandSelect 0x1 -#define bHTSIG2_GI 0x80 -#define bHTSIG2_Smoothing 0x01 -#define bHTSIG2_Sounding 0x02 -#define bHTSIG2_Aggreaton 0x08 -#define bHTSIG2_STBC 0x30 -#define bHTSIG2_AdvCoding 0x40 -#define bHTSIG2_NumOfHTLTF 0x300 -#define bHTSIG2_CRC8 0x3fc -#define bHTSIG1_MCS 0x7f -#define bHTSIG1_BandWidth 0x80 -#define bHTSIG1_HTLength 0xffff -#define bLSIG_Rate 0xf -#define bLSIG_Reserved 0x10 -#define bLSIG_Length 0x1fffe -#define bLSIG_Parity 0x20 -#define bCCKRxPhase 0x4 - -#define bLSSIReadAddress 0x7f800000 /* T65 RF */ - -#define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ - -#define bLSSIReadBackData 0xfffff /* T65 RF */ - -#define bLSSIReadOKFlag 0x1000 /* Useless now */ -#define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ -#define bRegulator0Standby 0x1 -#define bRegulatorPLLStandby 0x2 -#define bRegulator1Standby 0x4 -#define bPLLPowerUp 0x8 -#define bDPLLPowerUp 0x10 -#define bDA10PowerUp 0x20 -#define bAD7PowerUp 0x200 -#define bDA6PowerUp 0x2000 -#define bXtalPowerUp 0x4000 -#define b40MDClkPowerUP 0x8000 -#define bDA6DebugMode 0x20000 -#define bDA6Swing 0x380000 - -#define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ - -#define b80MClkDelay 0x18000000 /* Useless */ -#define bAFEWatchDogEnable 0x20000000 - -#define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ -#define bXtalCap23 0x3 -#define bXtalCap92x 0x0f000000 -#define bXtalCap 0x0f000000 - -#define bIntDifClkEnable 0x400 /* Useless */ -#define bExtSigClkEnable 0x800 -#define bBandgapMbiasPowerUp 0x10000 -#define bAD11SHGain 0xc0000 -#define bAD11InputRange 0x700000 -#define bAD11OPCurrent 0x3800000 -#define bIPathLoopback 0x4000000 -#define bQPathLoopback 0x8000000 -#define bAFELoopback 0x10000000 -#define bDA10Swing 0x7e0 -#define bDA10Reverse 0x800 -#define bDAClkSource 0x1000 -#define bAD7InputRange 0x6000 -#define bAD7Gain 0x38000 -#define bAD7OutputCMMode 0x40000 -#define bAD7InputCMMode 0x380000 -#define bAD7Current 0xc00000 -#define bRegulatorAdjust 0x7000000 -#define bAD11PowerUpAtTx 0x1 -#define bDA10PSAtTx 0x10 -#define bAD11PowerUpAtRx 0x100 -#define bDA10PSAtRx 0x1000 -#define bCCKRxAGCFormat 0x200 -#define bPSDFFTSamplepPoint 0xc000 -#define bPSDAverageNum 0x3000 -#define bIQPathControl 0xc00 -#define bPSDFreq 0x3ff -#define bPSDAntennaPath 0x30 -#define bPSDIQSwitch 0x40 -#define bPSDRxTrigger 0x400000 -#define bPSDTxTrigger 0x80000000 -#define bPSDSineToneScale 0x7f000000 -#define bPSDReport 0xffff - -/* 3. Page9(0x900) */ -#define bOFDMTxSC 0x30000000 /* Useless */ -#define bCCKTxOn 0x1 -#define bOFDMTxOn 0x2 -#define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ -#define bDebugItem 0xff /* reset debug page and LWord */ -#define bAntL 0x10 -#define bAntNonHT 0x100 -#define bAntHT1 0x1000 -#define bAntHT2 0x10000 -#define bAntHT1S1 0x100000 -#define bAntNonHTS1 0x1000000 - -/* 4. PageA(0xA00) */ -#define bCCKBBMode 0x3 /* Useless */ -#define bCCKTxPowerSaving 0x80 -#define bCCKRxPowerSaving 0x40 - -#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ - -#define bCCKScramble 0x8 /* Useless */ -#define bCCKAntDiversity 0x8000 -#define bCCKCarrierRecovery 0x4000 -#define bCCKTxRate 0x3000 -#define bCCKDCCancel 0x0800 -#define bCCKISICancel 0x0400 -#define bCCKMatchFilter 0x0200 -#define bCCKEqualizer 0x0100 -#define bCCKPreambleDetect 0x800000 -#define bCCKFastFalseCCA 0x400000 -#define bCCKChEstStart 0x300000 -#define bCCKCCACount 0x080000 -#define bCCKcs_lim 0x070000 -#define bCCKBistMode 0x80000000 -#define bCCKCCAMask 0x40000000 -#define bCCKTxDACPhase 0x4 -#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ -#define bCCKr_cp_mode0 0x0100 -#define bCCKTxDCOffset 0xf0 -#define bCCKRxDCOffset 0xf -#define bCCKCCAMode 0xc000 -#define bCCKFalseCS_lim 0x3f00 -#define bCCKCS_ratio 0xc00000 -#define bCCKCorgBit_sel 0x300000 -#define bCCKPD_lim 0x0f0000 -#define bCCKNewCCA 0x80000000 -#define bCCKRxHPofIG 0x8000 -#define bCCKRxIG 0x7f00 -#define bCCKLNAPolarity 0x800000 -#define bCCKRx1stGain 0x7f0000 -#define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ -#define bCCKRxAGCSatLevel 0x1f000000 -#define bCCKRxAGCSatCount 0xe0 -#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ -#define bCCKFixedRxAGC 0x8000 -/* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ -#define bCCKAntennaPolarity 0x2000 -#define bCCKTxFilterType 0x0c00 -#define bCCKRxAGCReportType 0x0300 -#define bCCKRxDAGCEn 0x80000000 -#define bCCKRxDAGCPeriod 0x20000000 -#define bCCKRxDAGCSatLevel 0x1f000000 -#define bCCKTimingRecovery 0x800000 -#define bCCKTxC0 0x3f0000 -#define bCCKTxC1 0x3f000000 -#define bCCKTxC2 0x3f -#define bCCKTxC3 0x3f00 -#define bCCKTxC4 0x3f0000 -#define bCCKTxC5 0x3f000000 -#define bCCKTxC6 0x3f -#define bCCKTxC7 0x3f00 -#define bCCKDebugPort 0xff0000 -#define bCCKDACDebug 0x0f000000 -#define bCCKFalseAlarmEnable 0x8000 -#define bCCKFalseAlarmRead 0x4000 -#define bCCKTRSSI 0x7f -#define bCCKRxAGCReport 0xfe -#define bCCKRxReport_AntSel 0x80000000 -#define bCCKRxReport_MFOff 0x40000000 -#define bCCKRxRxReport_SQLoss 0x20000000 -#define bCCKRxReport_Pktloss 0x10000000 -#define bCCKRxReport_Lockedbit 0x08000000 -#define bCCKRxReport_RateError 0x04000000 -#define bCCKRxReport_RxRate 0x03000000 -#define bCCKRxFACounterLower 0xff -#define bCCKRxFACounterUpper 0xff000000 -#define bCCKRxHPAGCStart 0xe000 -#define bCCKRxHPAGCFinal 0x1c00 -#define bCCKRxFalseAlarmEnable 0x8000 -#define bCCKFACounterFreeze 0x4000 -#define bCCKTxPathSel 0x10000000 -#define bCCKDefaultRxPath 0xc000000 -#define bCCKOptionRxPath 0x3000000 - -/* 5. PageC(0xC00) */ -#define bNumOfSTF 0x3 /* Useless */ -#define bShift_L 0xc0 -#define bGI_TH 0xc -#define bRxPathA 0x1 -#define bRxPathB 0x2 -#define bRxPathC 0x4 -#define bRxPathD 0x8 -#define bTxPathA 0x1 -#define bTxPathB 0x2 -#define bTxPathC 0x4 -#define bTxPathD 0x8 -#define bTRSSIFreq 0x200 -#define bADCBackoff 0x3000 -#define bDFIRBackoff 0xc000 -#define bTRSSILatchPhase 0x10000 -#define bRxIDCOffset 0xff -#define bRxQDCOffset 0xff00 -#define bRxDFIRMode 0x1800000 -#define bRxDCNFType 0xe000000 -#define bRXIQImb_A 0x3ff -#define bRXIQImb_B 0xfc00 -#define bRXIQImb_C 0x3f0000 -#define bRXIQImb_D 0xffc00000 -#define bDC_dc_Notch 0x60000 -#define bRxNBINotch 0x1f000000 -#define bPD_TH 0xf -#define bPD_TH_Opt2 0xc000 -#define bPWED_TH 0x700 -#define bIfMF_Win_L 0x800 -#define bPD_Option 0x1000 -#define bMF_Win_L 0xe000 -#define bBW_Search_L 0x30000 -#define bwin_enh_L 0xc0000 -#define bBW_TH 0x700000 -#define bED_TH2 0x3800000 -#define bBW_option 0x4000000 -#define bRatio_TH 0x18000000 -#define bWindow_L 0xe0000000 -#define bSBD_Option 0x1 -#define bFrame_TH 0x1c -#define bFS_Option 0x60 -#define bDC_Slope_check 0x80 -#define bFGuard_Counter_DC_L 0xe00 -#define bFrame_Weight_Short 0x7000 -#define bSub_Tune 0xe00000 -#define bFrame_DC_Length 0xe000000 -#define bSBD_start_offset 0x30000000 -#define bFrame_TH_2 0x7 -#define bFrame_GI2_TH 0x38 -#define bGI2_Sync_en 0x40 -#define bSarch_Short_Early 0x300 -#define bSarch_Short_Late 0xc00 -#define bSarch_GI2_Late 0x70000 -#define bCFOAntSum 0x1 -#define bCFOAcc 0x2 -#define bCFOStartOffset 0xc -#define bCFOLookBack 0x70 -#define bCFOSumWeight 0x80 -#define bDAGCEnable 0x10000 -#define bTXIQImb_A 0x3ff -#define bTXIQImb_B 0xfc00 -#define bTXIQImb_C 0x3f0000 -#define bTXIQImb_D 0xffc00000 -#define bTxIDCOffset 0xff -#define bTxQDCOffset 0xff00 -#define bTxDFIRMode 0x10000 -#define bTxPesudoNoiseOn 0x4000000 -#define bTxPesudoNoise_A 0xff -#define bTxPesudoNoise_B 0xff00 -#define bTxPesudoNoise_C 0xff0000 -#define bTxPesudoNoise_D 0xff000000 -#define bCCADropOption 0x20000 -#define bCCADropThres 0xfff00000 -#define bEDCCA_H 0xf -#define bEDCCA_L 0xf0 -#define bLambda_ED 0x300 -#define bRxInitialGain 0x7f -#define bRxAntDivEn 0x80 -#define bRxAGCAddressForLNA 0x7f00 -#define bRxHighPowerFlow 0x8000 -#define bRxAGCFreezeThres 0xc0000 -#define bRxFreezeStep_AGC1 0x300000 -#define bRxFreezeStep_AGC2 0xc00000 -#define bRxFreezeStep_AGC3 0x3000000 -#define bRxFreezeStep_AGC0 0xc000000 -#define bRxRssi_Cmp_En 0x10000000 -#define bRxQuickAGCEn 0x20000000 -#define bRxAGCFreezeThresMode 0x40000000 -#define bRxOverFlowCheckType 0x80000000 -#define bRxAGCShift 0x7f -#define bTRSW_Tri_Only 0x80 -#define bPowerThres 0x300 -#define bRxAGCEn 0x1 -#define bRxAGCTogetherEn 0x2 -#define bRxAGCMin 0x4 -#define bRxHP_Ini 0x7 -#define bRxHP_TRLNA 0x70 -#define bRxHP_RSSI 0x700 -#define bRxHP_BBP1 0x7000 -#define bRxHP_BBP2 0x70000 -#define bRxHP_BBP3 0x700000 -#define bRSSI_H 0x7f0000 /* the threshold for high power */ -#define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ -#define bRxSettle_TRSW 0x7 -#define bRxSettle_LNA 0x38 -#define bRxSettle_RSSI 0x1c0 -#define bRxSettle_BBP 0xe00 -#define bRxSettle_RxHP 0x7000 -#define bRxSettle_AntSW_RSSI 0x38000 -#define bRxSettle_AntSW 0xc0000 -#define bRxProcessTime_DAGC 0x300000 -#define bRxSettle_HSSI 0x400000 -#define bRxProcessTime_BBPPW 0x800000 -#define bRxAntennaPowerShift 0x3000000 -#define bRSSITableSelect 0xc000000 -#define bRxHP_Final 0x7000000 -#define bRxHTSettle_BBP 0x7 -#define bRxHTSettle_HSSI 0x8 -#define bRxHTSettle_RxHP 0x70 -#define bRxHTSettle_BBPPW 0x80 -#define bRxHTSettle_Idle 0x300 -#define bRxHTSettle_Reserved 0x1c00 -#define bRxHTRxHPEn 0x8000 -#define bRxHTAGCFreezeThres 0x30000 -#define bRxHTAGCTogetherEn 0x40000 -#define bRxHTAGCMin 0x80000 -#define bRxHTAGCEn 0x100000 -#define bRxHTDAGCEn 0x200000 -#define bRxHTRxHP_BBP 0x1c00000 -#define bRxHTRxHP_Final 0xe0000000 -#define bRxPWRatioTH 0x3 -#define bRxPWRatioEn 0x4 -#define bRxMFHold 0x3800 -#define bRxPD_Delay_TH1 0x38 -#define bRxPD_Delay_TH2 0x1c0 -#define bRxPD_DC_COUNT_MAX 0x600 -/* #define bRxMF_Hold 0x3800 */ -#define bRxPD_Delay_TH 0x8000 -#define bRxProcess_Delay 0xf0000 -#define bRxSearchrange_GI2_Early 0x700000 -#define bRxFrame_Guard_Counter_L 0x3800000 -#define bRxSGI_Guard_L 0xc000000 -#define bRxSGI_Search_L 0x30000000 -#define bRxSGI_TH 0xc0000000 -#define bDFSCnt0 0xff -#define bDFSCnt1 0xff00 -#define bDFSFlag 0xf0000 -#define bMFWeightSum 0x300000 -#define bMinIdxTH 0x7f000000 -#define bDAFormat 0x40000 -#define bTxChEmuEnable 0x01000000 -#define bTRSWIsolation_A 0x7f -#define bTRSWIsolation_B 0x7f00 -#define bTRSWIsolation_C 0x7f0000 -#define bTRSWIsolation_D 0x7f000000 -#define bExtLNAGain 0x7c00 - -/* 6. PageE(0xE00) */ -#define bSTBCEn 0x4 /* Useless */ -#define bAntennaMapping 0x10 -#define bNss 0x20 -#define bCFOAntSumD 0x200 -#define bPHYCounterReset 0x8000000 -#define bCFOReportGet 0x4000000 -#define bOFDMContinueTx 0x10000000 -#define bOFDMSingleCarrier 0x20000000 -#define bOFDMSingleTone 0x40000000 -/* #define bRxPath1 0x01 */ -/* #define bRxPath2 0x02 */ -/* #define bRxPath3 0x04 */ -/* #define bRxPath4 0x08 */ -/* #define bTxPath1 0x10 */ -/* #define bTxPath2 0x20 */ -#define bHTDetect 0x100 -#define bCFOEn 0x10000 -#define bCFOValue 0xfff00000 -#define bSigTone_Re 0x3f -#define bSigTone_Im 0x7f00 -#define bCounter_CCA 0xffff -#define bCounter_ParityFail 0xffff0000 -#define bCounter_RateIllegal 0xffff -#define bCounter_CRC8Fail 0xffff0000 -#define bCounter_MCSNoSupport 0xffff -#define bCounter_FastSync 0xffff -#define bShortCFO 0xfff -#define bShortCFOTLength 12 /* total */ -#define bShortCFOFLength 11 /* fraction */ -#define bLongCFO 0x7ff -#define bLongCFOTLength 11 -#define bLongCFOFLength 11 -#define bTailCFO 0x1fff -#define bTailCFOTLength 13 -#define bTailCFOFLength 12 -#define bmax_en_pwdB 0xffff -#define bCC_power_dB 0xffff0000 -#define bnoise_pwdB 0xffff -#define bPowerMeasTLength 10 -#define bPowerMeasFLength 3 -#define bRx_HT_BW 0x1 -#define bRxSC 0x6 -#define bRx_HT 0x8 -#define bNB_intf_det_on 0x1 -#define bIntf_win_len_cfg 0x30 -#define bNB_Intf_TH_cfg 0x1c0 -#define bRFGain 0x3f -#define bTableSel 0x40 -#define bTRSW 0x80 -#define bRxSNR_A 0xff -#define bRxSNR_B 0xff00 -#define bRxSNR_C 0xff0000 -#define bRxSNR_D 0xff000000 -#define bSNREVMTLength 8 -#define bSNREVMFLength 1 -#define bCSI1st 0xff -#define bCSI2nd 0xff00 -#define bRxEVM1st 0xff0000 -#define bRxEVM2nd 0xff000000 -#define bSIGEVM 0xff -#define bPWDB 0xff00 -#define bSGIEN 0x10000 - -#define bSFactorQAM1 0xf /* Useless */ -#define bSFactorQAM2 0xf0 -#define bSFactorQAM3 0xf00 -#define bSFactorQAM4 0xf000 -#define bSFactorQAM5 0xf0000 -#define bSFactorQAM6 0xf0000 -#define bSFactorQAM7 0xf00000 -#define bSFactorQAM8 0xf000000 -#define bSFactorQAM9 0xf0000000 -#define bCSIScheme 0x100000 - -#define bNoiseLvlTopSet 0x3 /* Useless */ -#define bChSmooth 0x4 -#define bChSmoothCfg1 0x38 -#define bChSmoothCfg2 0x1c0 -#define bChSmoothCfg3 0xe00 -#define bChSmoothCfg4 0x7000 -#define bMRCMode 0x800000 -#define bTHEVMCfg 0x7000000 - -#define bLoopFitType 0x1 /* Useless */ -#define bUpdCFO 0x40 -#define bUpdCFOOffData 0x80 -#define bAdvUpdCFO 0x100 -#define bAdvTimeCtrl 0x800 -#define bUpdClko 0x1000 -#define bFC 0x6000 -#define bTrackingMode 0x8000 -#define bPhCmpEnable 0x10000 -#define bUpdClkoLTF 0x20000 -#define bComChCFO 0x40000 -#define bCSIEstiMode 0x80000 -#define bAdvUpdEqz 0x100000 -#define bUChCfg 0x7000000 -#define bUpdEqz 0x8000000 - -/* Rx Pseduo noise */ -#define bRxPesudoNoiseOn 0x20000000 /* Useless */ -#define bRxPesudoNoise_A 0xff -#define bRxPesudoNoise_B 0xff00 -#define bRxPesudoNoise_C 0xff0000 -#define bRxPesudoNoise_D 0xff000000 -#define bPesudoNoiseState_A 0xffff -#define bPesudoNoiseState_B 0xffff0000 -#define bPesudoNoiseState_C 0xffff -#define bPesudoNoiseState_D 0xffff0000 - -/* 7. RF Register - * Zebra1 */ -#define bZebra1_HSSIEnable 0x8 /* Useless */ -#define bZebra1_TRxControl 0xc00 -#define bZebra1_TRxGainSetting 0x07f -#define bZebra1_RxCorner 0xc00 -#define bZebra1_TxChargePump 0x38 -#define bZebra1_RxChargePump 0x7 -#define bZebra1_ChannelNum 0xf80 -#define bZebra1_TxLPFBW 0x400 -#define bZebra1_RxLPFBW 0x600 - -/* Zebra4 */ -#define bRTL8256RegModeCtrl1 0x100 /* Useless */ -#define bRTL8256RegModeCtrl0 0x40 -#define bRTL8256_TxLPFBW 0x18 -#define bRTL8256_RxLPFBW 0x600 - -/* RTL8258 */ -#define bRTL8258_TxLPFBW 0xc /* Useless */ -#define bRTL8258_RxLPFBW 0xc00 -#define bRTL8258_RSSILPFBW 0xc0 - - -/* - * Other Definition - * */ - -/* byte endable for sb_write */ -#define bByte0 0x1 /* Useless */ -#define bByte1 0x2 -#define bByte2 0x4 -#define bByte3 0x8 -#define bWord0 0x3 -#define bWord1 0xc -#define bDWord 0xf - -/* for PutRegsetting & GetRegSetting BitMask */ -#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ -#define bMaskByte1 0xff00 -#define bMaskByte2 0xff0000 -#define bMaskByte3 0xff000000 -#define bMaskHWord 0xffff0000 -#define bMaskLWord 0x0000ffff -#define bMaskDWord 0xffffffff -#define bMaskH3Bytes 0xffffff00 -#define bMask12Bits 0xfff -#define bMaskH4Bits 0xf0000000 -#define bMaskOFDM_D 0xffc00000 -#define bMaskCCK 0x3f3f3f3f - - -#define bEnable 0x1 /* Useless */ -#define bDisable 0x0 - -#define LeftAntenna 0x0 /* Useless */ -#define RightAntenna 0x1 - -#define tCheckTxStatus 500 /* 500ms */ /* Useless */ -#define tUpdateRxCounter 100 /* 100ms */ - -#define rateCCK 0 /* Useless */ -#define rateOFDM 1 -#define rateHT 2 - -/* define Register-End */ -#define bPMAC_End 0x1ff /* Useless */ -#define bFPGAPHY0_End 0x8ff -#define bFPGAPHY1_End 0x9ff -#define bCCKPHY0_End 0xaff -#define bOFDMPHY0_End 0xcff -#define bOFDMPHY1_End 0xdff - -/* define max debug item in each debug page - * #define bMaxItem_FPGA_PHY0 0x9 - * #define bMaxItem_FPGA_PHY1 0x3 - * #define bMaxItem_PHY_11B 0x16 - * #define bMaxItem_OFDM_PHY0 0x29 - * #define bMaxItem_OFDM_PHY1 0x0 */ - -#define bPMACControl 0x0 /* Useless */ -#define bWMACControl 0x1 -#define bWNICControl 0x2 - -#define PathA 0x0 /* Useless */ -#define PathB 0x1 -#define PathC 0x2 -#define PathD 0x3 - -#endif diff --git a/include/Hal8723BPwrSeq.h b/include/Hal8723BPwrSeq.h deleted file mode 100644 index 6b89562..0000000 --- a/include/Hal8723BPwrSeq.h +++ /dev/null @@ -1,232 +0,0 @@ -#ifndef REALTEK_POWER_SEQUENCE_8723B -#define REALTEK_POWER_SEQUENCE_8723B - -#include "HalPwrSeqCmd.h" - -/* - Check document WM-20130815-JackieLau-RTL8723B_Power_Architecture v08.vsd - There are 6 HW Power States: - 0: POFF--Power Off - 1: PDN--Power Down - 2: CARDEMU--Card Emulation - 3: ACT--Active Mode - 4: LPS--Low Power State - 5: SUS--Suspend - - The transision from different states are defined below - TRANS_CARDEMU_TO_ACT - TRANS_ACT_TO_CARDEMU - TRANS_CARDEMU_TO_SUS - TRANS_SUS_TO_CARDEMU - TRANS_CARDEMU_TO_PDN - TRANS_ACT_TO_LPS - TRANS_LPS_TO_ACT - - TRANS_END -*/ -#define RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS 26 -#define RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS 15 -#define RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS 15 -#define RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS 15 -#define RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS 15 -#define RTL8723B_TRANS_PDN_TO_CARDEMU_STEPS 15 -#define RTL8723B_TRANS_ACT_TO_LPS_STEPS 15 -#define RTL8723B_TRANS_LPS_TO_ACT_STEPS 15 -#define RTL8723B_TRANS_ACT_TO_SWLPS_STEPS 22 -#define RTL8723B_TRANS_SWLPS_TO_ACT_STEPS 15 -#define RTL8723B_TRANS_END_STEPS 1 - - -#define RTL8723B_TRANS_CARDEMU_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ - {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \ - {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \ - {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3 | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \ - {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ - {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \ - {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/ \ - {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\ - {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\ - {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\ - {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\ - {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\ - {0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 internal pull high setting by test chip*/\ - {0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\ - - -#define RTL8723B_TRANS_ACT_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ - {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ - {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/\ - {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \ - {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\ - - -#define RTL8723B_TRANS_CARDEMU_TO_SUS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ - -#define RTL8723B_TRANS_SUS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ - -#define RTL8723B_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \ - {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ - -#define RTL8723B_TRANS_CARDDIS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ - {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ - - -#define RTL8723B_TRANS_CARDEMU_TO_PDN \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ - -#define RTL8723B_TRANS_PDN_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ - -#define RTL8723B_TRANS_ACT_TO_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ - {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ - {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \ - {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \ - - -#define RTL8723B_TRANS_LPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ - {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ - {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ - {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ - {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ - - -#define RTL8723B_TRANS_ACT_TO_SWLPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable 32 K source*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*disable security engine*/ \ - {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x40},/*When driver enter Sus/ Disable, enable LOP for BT*/ \ - {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*reset dual TSF*/ \ - {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*Reset CPU*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*Reset MCUFWDL register*/ \ - {0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/ \ - {0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*Reset CPU IO Wrapper*/ \ - {0x0287, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*polling RXFF packet number = 0 */ \ - {0x0286, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/*polling RXDMA idle */ \ - {0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Clear FW RPWM interrupt */\ - {0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Set FW RPWM interrupt source*/\ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*switch TSF to 32K*/\ - {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/*polling TSF stable*/\ - {0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Set FW LPS*/ \ - {0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/*polling FW LPS ready */ - - -#define RTL8723B_TRANS_SWLPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/*switch TSF to 32K*/\ - {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*polling TSF stable*/\ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1, enable security engine*/\ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ - {0x06B7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x09}, /*. reset MAC rx state machine*/\ - {0x06B4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x86}, /*. reset MAC rx state machine*/\ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/* set CPU RAM code ready*/ \ - {0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/ \ - {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/ \ - {0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable CPU IO Wrapper*/ \ - {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, BIT7},/*polling FW init ready */ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT6, BIT6},/*polling FW init ready */ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ - -#define RTL8723B_TRANS_END \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0}, - - - extern WLAN_PWR_CFG rtl8723B_power_on_flow[RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723B_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723B_radio_off_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723B_card_disable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723B_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723B_card_enable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723B_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723B_suspend_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723B_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723B_resume_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723B_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723B_hwpdn_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723B_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723B_enter_lps_flow[RTL8723B_TRANS_ACT_TO_LPS_STEPS + RTL8723B_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723B_leave_lps_flow[RTL8723B_TRANS_LPS_TO_ACT_STEPS + RTL8723B_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723B_enter_swlps_flow[RTL8723B_TRANS_ACT_TO_SWLPS_STEPS + RTL8723B_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723B_leave_swlps_flow[RTL8723B_TRANS_SWLPS_TO_ACT_STEPS + RTL8723B_TRANS_END_STEPS]; -#endif diff --git a/include/Hal8723DPhyCfg.h b/include/Hal8723DPhyCfg.h deleted file mode 100644 index f3ce170..0000000 --- a/include/Hal8723DPhyCfg.h +++ /dev/null @@ -1,136 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_HAL8723DPHYCFG_H__ -#define __INC_HAL8723DPHYCFG_H__ - -/*--------------------------Define Parameters-------------------------------*/ -#define LOOP_LIMIT 5 -#define MAX_STALL_TIME 50 /* us */ -#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */ -#define MAX_TXPWR_IDX_NMODE_92S 63 -#define Reset_Cnt_Limit 3 - -#ifdef CONFIG_PCI_HCI - #define MAX_AGGR_NUM 0x0B -#else - #define MAX_AGGR_NUM 0x07 -#endif /* CONFIG_PCI_HCI */ - - -/*--------------------------Define Parameters End-------------------------------*/ - - -/*------------------------------Define structure----------------------------*/ - -/*------------------------------Define structure End----------------------------*/ - -/*--------------------------Exported Function prototype---------------------*/ -u32 -PHY_QueryBBReg_8723D( - IN PADAPTER Adapter, - IN u32 RegAddr, - IN u32 BitMask -); - -VOID -PHY_SetBBReg_8723D( - IN PADAPTER Adapter, - IN u32 RegAddr, - IN u32 BitMask, - IN u32 Data -); - -u32 -PHY_QueryRFReg_8723D( - IN PADAPTER Adapter, - IN u8 eRFPath, - IN u32 RegAddr, - IN u32 BitMask -); - -VOID -PHY_SetRFReg_8723D( - IN PADAPTER Adapter, - IN u8 eRFPath, - IN u32 RegAddr, - IN u32 BitMask, - IN u32 Data -); - -/* MAC/BB/RF HAL config */ -int PHY_BBConfig8723D(PADAPTER Adapter); - -int PHY_RFConfig8723D(PADAPTER Adapter); - -s32 PHY_MACConfig8723D(PADAPTER padapter); - -int -PHY_ConfigRFWithParaFile_8723D( - IN PADAPTER Adapter, - IN u8 *pFileName, - RF_PATH eRFPath -); - -VOID -PHY_SetTxPowerIndex_8723D( - IN PADAPTER Adapter, - IN u32 PowerIndex, - IN u8 RFPath, - IN u8 Rate -); - -u8 -PHY_GetTxPowerIndex_8723D( - IN PADAPTER pAdapter, - IN u8 RFPath, - IN u8 Rate, - IN u8 BandWidth, - IN u8 Channel, - struct txpwr_idx_comp *tic -); - -VOID -PHY_GetTxPowerLevel8723D( - IN PADAPTER Adapter, - OUT s32 *powerlevel -); - -VOID -PHY_SetTxPowerLevel8723D( - IN PADAPTER Adapter, - IN u8 channel -); - -VOID -PHY_SetSwChnlBWMode8723D( - IN PADAPTER Adapter, - IN u8 channel, - IN CHANNEL_WIDTH Bandwidth, - IN u8 Offset40, - IN u8 Offset80 -); - -VOID phy_set_rf_path_switch_8723d( - IN PADAPTER pAdapter, - IN bool bMain -); -/*--------------------------Exported Function prototype End---------------------*/ - -#endif diff --git a/include/Hal8723DPhyReg.h b/include/Hal8723DPhyReg.h deleted file mode 100644 index 9fb0cc1..0000000 --- a/include/Hal8723DPhyReg.h +++ /dev/null @@ -1,1139 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_HAL8723DPHYREG_H__ -#define __INC_HAL8723DPHYREG_H__ - -#define rSYM_WLBT_PAPE_SEL 0x64 -/* - * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF - * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF - * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 - * 3. RF register 0x00-2E - * 4. Bit Mask for BB/RF register - * 5. Other definition for BB/RF R/W - * */ - - -/* - * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF - * 1. Page1(0x100) - * */ -#define rPMAC_Reset 0x100 -#define rPMAC_TxStart 0x104 -#define rPMAC_TxLegacySIG 0x108 -#define rPMAC_TxHTSIG1 0x10c -#define rPMAC_TxHTSIG2 0x110 -#define rPMAC_PHYDebug 0x114 -#define rPMAC_TxPacketNum 0x118 -#define rPMAC_TxIdle 0x11c -#define rPMAC_TxMACHeader0 0x120 -#define rPMAC_TxMACHeader1 0x124 -#define rPMAC_TxMACHeader2 0x128 -#define rPMAC_TxMACHeader3 0x12c -#define rPMAC_TxMACHeader4 0x130 -#define rPMAC_TxMACHeader5 0x134 -#define rPMAC_TxDataType 0x138 -#define rPMAC_TxRandomSeed 0x13c -#define rPMAC_CCKPLCPPreamble 0x140 -#define rPMAC_CCKPLCPHeader 0x144 -#define rPMAC_CCKCRC16 0x148 -#define rPMAC_OFDMRxCRC32OK 0x170 -#define rPMAC_OFDMRxCRC32Er 0x174 -#define rPMAC_OFDMRxParityEr 0x178 -#define rPMAC_OFDMRxCRC8Er 0x17c -#define rPMAC_CCKCRxRC16Er 0x180 -#define rPMAC_CCKCRxRC32Er 0x184 -#define rPMAC_CCKCRxRC32OK 0x188 -#define rPMAC_TxStatus 0x18c - -/* - * 2. Page2(0x200) - * - * The following two definition are only used for USB interface. */ -#define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */ -#define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */ - -/* - * 3. Page8(0x800) - * */ -#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC // RF BW Setting?? */ - -#define rFPGA0_TxInfo 0x804 /* Status report?? */ -#define rFPGA0_PSDFunction 0x808 - -#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ - -#define rFPGA0_RFTiming1 0x810 /* Useless now */ -#define rFPGA0_RFTiming2 0x814 - -#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ -#define rFPGA0_XA_HSSIParameter2 0x824 -#define rFPGA0_XB_HSSIParameter1 0x828 -#define rFPGA0_XB_HSSIParameter2 0x82c -#define rTxAGC_B_Rate18_06 0x830 -#define rTxAGC_B_Rate54_24 0x834 -#define rTxAGC_B_CCK1_55_Mcs32 0x838 -#define rTxAGC_B_Mcs03_Mcs00 0x83c - -#define rTxAGC_B_Mcs07_Mcs04 0x848 -#define rTxAGC_B_Mcs11_Mcs08 0x84c - -#define rFPGA0_XA_LSSIParameter 0x840 -#define rFPGA0_XB_LSSIParameter 0x844 - -#define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ -#define rFPGA0_RFSleepUpParameter 0x854 - -#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ -#define rFPGA0_XCD_SwitchControl 0x85c - -#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ -#define rFPGA0_XB_RFInterfaceOE 0x864 - -#define rTxAGC_B_Mcs15_Mcs12 0x868 -#define rTxAGC_B_CCK11_A_CCK2_11 0x86c - -#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ -#define rFPGA0_XCD_RFInterfaceSW 0x874 - -#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ -#define rFPGA0_XCD_RFParameter 0x87c - -#define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ -#define rFPGA0_AnalogParameter2 0x884 -#define rFPGA0_AnalogParameter3 0x888 /* Useless now */ -#define rFPGA0_AnalogParameter4 0x88c - -#define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ -#define rFPGA0_XB_LSSIReadBack 0x8a4 -#define rFPGA0_XC_LSSIReadBack 0x8a8 -#define rFPGA0_XD_LSSIReadBack 0x8ac - -#define rFPGA0_PSDReport 0x8b4 /* Useless now */ -#define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ -#define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ -#define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now // RF Interface Readback Value */ -#define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ - -/* - * 4. Page9(0x900) - * */ -#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC // RF BW Setting?? */ -#define rFPGA1_TxBlock 0x904 /* Useless now */ -#define rFPGA1_DebugSelect 0x908 /* Useless now */ -#define rFPGA1_TxInfo 0x90c /* Useless now // Status report?? */ -#define rDPDT_control 0x92c -#define rfe_ctrl_anta_src 0x930 -#define rS0S1_PathSwitch 0x948 -#define rBBrx_DFIR 0x954 - -/* - * 5. PageA(0xA00) - * - * Set Control channel to upper or lower. These settings are required only for 40MHz */ -#define rCCK0_System 0xa00 - -#define rCCK0_AFESetting 0xa04 /* Disable init gain now // Select RX path by RSSI */ -#define rCCK0_CCA 0xa08 /* Disable init gain now // Init gain */ - -#define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ -#define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ - -#define rCCK0_RxHP 0xa14 - -#define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ -#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ - -#define rCCK0_TxFilter1 0xa20 -#define rCCK0_TxFilter2 0xa24 -#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ -#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ -#define rCCK0_TRSSIReport 0xa50 -#define rCCK0_RxReport 0xa54 /* 0xa57 */ -#define rCCK0_FACounterLower 0xa5c /* 0xa5b */ -#define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ - -/* - * PageB(0xB00) - * */ -#define rPdp_AntA 0xb00 -#define rPdp_AntA_4 0xb04 -#define rPdp_AntA_8 0xb08 -#define rPdp_AntA_C 0xb0c -#define rPdp_AntA_10 0xb10 -#define rPdp_AntA_14 0xb14 -#define rPdp_AntA_18 0xb18 -#define rPdp_AntA_1C 0xb1c -#define rPdp_AntA_20 0xb20 -#define rPdp_AntA_24 0xb24 - -#define rConfig_Pmpd_AntA 0xb28 -#define rConfig_ram64x16 0xb2c - -#define rBndA 0xb30 -#define rHssiPar 0xb34 - -#define rConfig_AntA 0xb68 -#define rConfig_AntB 0xb6c - -#define rPdp_AntB 0xb70 -#define rPdp_AntB_4 0xb74 -#define rPdp_AntB_8 0xb78 -#define rPdp_AntB_C 0xb7c -#define rPdp_AntB_10 0xb80 -#define rPdp_AntB_14 0xb84 -#define rPdp_AntB_18 0xb88 -#define rPdp_AntB_1C 0xb8c -#define rPdp_AntB_20 0xb90 -#define rPdp_AntB_24 0xb94 - -#define rConfig_Pmpd_AntB 0xb98 - -#define rBndB 0xba0 - -#define rAPK 0xbd8 -#define rPm_Rx0_AntA 0xbdc -#define rPm_Rx1_AntA 0xbe0 -#define rPm_Rx2_AntA 0xbe4 -#define rPm_Rx3_AntA 0xbe8 -#define rPm_Rx0_AntB 0xbec -#define rPm_Rx1_AntB 0xbf0 -#define rPm_Rx2_AntB 0xbf4 -#define rPm_Rx3_AntB 0xbf8 -/* - * 6. PageC(0xC00) - * */ -#define rOFDM0_LSTF 0xc00 - -#define rOFDM0_TRxPathEnable 0xc04 -#define rOFDM0_TRMuxPar 0xc08 -#define rOFDM0_TRSWIsolation 0xc0c - -#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ -#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imbalance matrix */ -#define rOFDM0_XBRxAFE 0xc18 -#define rOFDM0_XBRxIQImbalance 0xc1c -#define rOFDM0_XCRxAFE 0xc20 -#define rOFDM0_XCRxIQImbalance 0xc24 -#define rOFDM0_XDRxAFE 0xc28 -#define rOFDM0_XDRxIQImbalance 0xc2c - -#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD // DM tune init gain */ -#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ -#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ -#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ - -#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ -#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ -#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ -#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ - -#define rOFDM0_XAAGCCore1 0xc50 /* DIG */ -#define rOFDM0_XAAGCCore2 0xc54 -#define rOFDM0_XBAGCCore1 0xc58 -#define rOFDM0_XBAGCCore2 0xc5c -#define rOFDM0_XCAGCCore1 0xc60 -#define rOFDM0_XCAGCCore2 0xc64 -#define rOFDM0_XDAGCCore1 0xc68 -#define rOFDM0_XDAGCCore2 0xc6c - -#define rOFDM0_AGCParameter1 0xc70 -#define rOFDM0_AGCParameter2 0xc74 -#define rOFDM0_AGCRSSITable 0xc78 -#define rOFDM0_HTSTFAGC 0xc7c - -#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ -#define rOFDM0_XATxAFE 0xc84 -#define rOFDM0_XBTxIQImbalance 0xc88 -#define rOFDM0_XBTxAFE 0xc8c -#define rOFDM0_XCTxIQImbalance 0xc90 -#define rOFDM0_XCTxAFE 0xc94 -#define rOFDM0_XDTxIQImbalance 0xc98 -#define rOFDM0_XDTxAFE 0xc9c - -#define rOFDM0_RxIQExtAnta 0xca0 -#define rOFDM0_TxCoeff1 0xca4 -#define rOFDM0_TxCoeff2 0xca8 -#define rOFDM0_TxCoeff3 0xcac -#define rOFDM0_TxCoeff4 0xcb0 -#define rOFDM0_TxCoeff5 0xcb4 -#define rOFDM0_TxCoeff6 0xcb8 -#define rOFDM0_RxHPParameter 0xce0 -#define rOFDM0_TxPseudoNoiseWgt 0xce4 -#define rOFDM0_FrameSync 0xcf0 -#define rOFDM0_DFSReport 0xcf4 - -/* - * 7. PageD(0xD00) - * */ -#define rOFDM1_LSTF 0xd00 -#define rOFDM1_TRxPathEnable 0xd04 - -#define rOFDM1_CFO 0xd08 /* No setting now */ -#define rOFDM1_CSI1 0xd10 -#define rOFDM1_SBD 0xd14 -#define rOFDM1_CSI2 0xd18 -#define rOFDM1_CFOTracking 0xd2c -#define rOFDM1_TRxMesaure1 0xd34 -#define rOFDM1_IntfDet 0xd3c -#define rOFDM1_PseudoNoiseStateAB 0xd50 -#define rOFDM1_PseudoNoiseStateCD 0xd54 -#define rOFDM1_RxPseudoNoiseWgt 0xd58 - -#define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ -#define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ -#define rOFDM_PHYCounter3 0xda8 /* MCS not support */ - -#define rOFDM_ShortCFOAB 0xdac /* No setting now */ -#define rOFDM_ShortCFOCD 0xdb0 -#define rOFDM_LongCFOAB 0xdb4 -#define rOFDM_LongCFOCD 0xdb8 -#define rOFDM_TailCFOAB 0xdbc -#define rOFDM_TailCFOCD 0xdc0 -#define rOFDM_PWMeasure1 0xdc4 -#define rOFDM_PWMeasure2 0xdc8 -#define rOFDM_BWReport 0xdcc -#define rOFDM_AGCReport 0xdd0 -#define rOFDM_RxSNR 0xdd4 -#define rOFDM_RxEVMCSI 0xdd8 -#define rOFDM_SIGReport 0xddc - - -/* - * 8. PageE(0xE00) - * */ -#define rTxAGC_A_Rate18_06 0xe00 -#define rTxAGC_A_Rate54_24 0xe04 -#define rTxAGC_A_CCK1_Mcs32 0xe08 -#define rTxAGC_A_Mcs03_Mcs00 0xe10 -#define rTxAGC_A_Mcs07_Mcs04 0xe14 -#define rTxAGC_A_Mcs11_Mcs08 0xe18 -#define rTxAGC_A_Mcs15_Mcs12 0xe1c - -#define rFPGA0_IQK 0xe28 -#define rTx_IQK_Tone_A 0xe30 -#define rRx_IQK_Tone_A 0xe34 -#define rTx_IQK_PI_A 0xe38 -#define rRx_IQK_PI_A 0xe3c - -#define rTx_IQK 0xe40 -#define rRx_IQK 0xe44 -#define rIQK_AGC_Pts 0xe48 -#define rIQK_AGC_Rsp 0xe4c -#define rTx_IQK_Tone_B 0xe50 -#define rRx_IQK_Tone_B 0xe54 -#define rTx_IQK_PI_B 0xe58 -#define rRx_IQK_PI_B 0xe5c -#define rIQK_AGC_Cont 0xe60 - -#define rBlue_Tooth 0xe6c -#define rRx_Wait_CCA 0xe70 -#define rTx_CCK_RFON 0xe74 -#define rTx_CCK_BBON 0xe78 -#define rTx_OFDM_RFON 0xe7c -#define rTx_OFDM_BBON 0xe80 -#define rTx_To_Rx 0xe84 -#define rTx_To_Tx 0xe88 -#define rRx_CCK 0xe8c - -#define rTx_Power_Before_IQK_A 0xe94 -#define rTx_Power_After_IQK_A 0xe9c - -#define rRx_Power_Before_IQK_A 0xea0 -#define rRx_Power_Before_IQK_A_2 0xea4 -#define rRx_Power_After_IQK_A 0xea8 -#define rRx_Power_After_IQK_A_2 0xeac - -#define rTx_Power_Before_IQK_B 0xeb4 -#define rTx_Power_After_IQK_B 0xebc - -#define rRx_Power_Before_IQK_B 0xec0 -#define rRx_Power_Before_IQK_B_2 0xec4 -#define rRx_Power_After_IQK_B 0xec8 -#define rRx_Power_After_IQK_B_2 0xecc - -#define rRx_OFDM 0xed0 -#define rRx_Wait_RIFS 0xed4 -#define rRx_TO_Rx 0xed8 -#define rStandby 0xedc -#define rSleep 0xee0 -#define rPMPD_ANAEN 0xeec - -/* - * 7. RF Register 0x00-0x2E (RF 8256) - * RF-0222D 0x00-3F - * - * Zebra1 */ -#define rZebra1_HSSIEnable 0x0 /* Useless now */ -#define rZebra1_TRxEnable1 0x1 -#define rZebra1_TRxEnable2 0x2 -#define rZebra1_AGC 0x4 -#define rZebra1_ChargePump 0x5 -#define rZebra1_Channel 0x7 /* RF channel switch */ - -/* #endif */ -#define rZebra1_TxGain 0x8 /* Useless now */ -#define rZebra1_TxLPF 0x9 -#define rZebra1_RxLPF 0xb -#define rZebra1_RxHPFCorner 0xc - -/* Zebra4 */ -#define rGlobalCtrl 0 /* Useless now */ -#define rRTL8256_TxLPF 19 -#define rRTL8256_RxLPF 11 - -/* RTL8258 */ -#define rRTL8258_TxLPF 0x11 /* Useless now */ -#define rRTL8258_RxLPF 0x13 -#define rRTL8258_RSSILPF 0xa - -/* - * RL6052 Register definition - * */ -#define RF_AC 0x00 /* */ - -#define RF_IQADJ_G1 0x01 /* */ -#define RF_IQADJ_G2 0x02 /* */ -#define RF_BS_PA_APSET_G1_G4 0x03 -#define RF_BS_PA_APSET_G5_G8 0x04 -#define RF_POW_TRSW 0x05 /* */ - -#define RF_GAIN_RX 0x06 /* */ -#define RF_GAIN_TX 0x07 /* */ - -#define RF_TXM_IDAC 0x08 /* */ -#define RF_IPA_G 0x09 /* */ -#define RF_TXBIAS_G 0x0A -#define RF_TXPA_AG 0x0B -#define RF_IPA_A 0x0C /* */ -#define RF_TXBIAS_A 0x0D -#define RF_BS_PA_APSET_G9_G11 0x0E -#define RF_BS_IQGEN 0x0F /* */ - -#define RF_MODE1 0x10 /* */ -#define RF_MODE2 0x11 /* */ - -#define RF_RX_AGC_HP 0x12 /* */ -#define RF_TX_AGC 0x13 /* */ -#define RF_BIAS 0x14 /* */ -#define RF_IPA 0x15 /* */ -#define RF_TXBIAS 0x16 -#define RF_POW_ABILITY 0x17 /* */ -#define RF_MODE_AG 0x18 /* */ -#define rRfChannel 0x18 /* RF channel and BW switch */ -#define RF_CHNLBW 0x18 /* RF channel and BW switch */ -#define RF_TOP 0x19 /* */ - -#define RF_RX_G1 0x1A /* */ -#define RF_RX_G2 0x1B /* */ - -#define RF_RX_BB2 0x1C /* */ -#define RF_RX_BB1 0x1D /* */ - -#define RF_RCK1 0x1E /* */ -#define RF_RCK2 0x1F /* */ - -#define RF_TX_G1 0x20 /* */ -#define RF_TX_G2 0x21 /* */ -#define RF_TX_G3 0x22 /* */ - -#define RF_TX_BB1 0x23 /* */ - -#define RF_T_METER 0x24 /* */ - -#define RF_SYN_G1 0x25 /* RF TX Power control */ -#define RF_SYN_G2 0x26 /* RF TX Power control */ -#define RF_SYN_G3 0x27 /* RF TX Power control */ -#define RF_SYN_G4 0x28 /* RF TX Power control */ -#define RF_SYN_G5 0x29 /* RF TX Power control */ -#define RF_SYN_G6 0x2A /* RF TX Power control */ -#define RF_SYN_G7 0x2B /* RF TX Power control */ -#define RF_SYN_G8 0x2C /* RF TX Power control */ - -#define RF_RCK_OS 0x30 /* RF TX PA control */ - -#define RF_TXPA_G1 0x31 /* RF TX PA control */ -#define RF_TXPA_G2 0x32 /* RF TX PA control */ -#define RF_TXPA_G3 0x33 /* RF TX PA control */ -#define RF_TX_BIAS_A 0x35 -#define RF_TX_BIAS_D 0x36 -#define RF_LOBF_9 0x38 -#define RF_RXRF_A3 0x3C /* */ -#define RF_TRSW 0x3F - -#define RF_TXRF_A2 0x41 -#define RF_T_METER_88E 0x42 -#define RF_TXPA_G4 0x46 -#define RF_TXPA_A4 0x4B -#define RF_0x52 0x52 -#define RF_WE_LUT 0xEF -#define RF_S0S1 0xB0 - -/* - * Bit Mask - * - * 1. Page1(0x100) */ -#define bBBResetB 0x100 /* Useless now? */ -#define bGlobalResetB 0x200 -#define bOFDMTxStart 0x4 -#define bCCKTxStart 0x8 -#define bCRC32Debug 0x100 -#define bPMACLoopback 0x10 -#define bTxLSIG 0xffffff -#define bOFDMTxRate 0xf -#define bOFDMTxReserved 0x10 -#define bOFDMTxLength 0x1ffe0 -#define bOFDMTxParity 0x20000 -#define bTxHTSIG1 0xffffff -#define bTxHTMCSRate 0x7f -#define bTxHTBW 0x80 -#define bTxHTLength 0xffff00 -#define bTxHTSIG2 0xffffff -#define bTxHTSmoothing 0x1 -#define bTxHTSounding 0x2 -#define bTxHTReserved 0x4 -#define bTxHTAggreation 0x8 -#define bTxHTSTBC 0x30 -#define bTxHTAdvanceCoding 0x40 -#define bTxHTShortGI 0x80 -#define bTxHTNumberHT_LTF 0x300 -#define bTxHTCRC8 0x3fc00 -#define bCounterReset 0x10000 -#define bNumOfOFDMTx 0xffff -#define bNumOfCCKTx 0xffff0000 -#define bTxIdleInterval 0xffff -#define bOFDMService 0xffff0000 -#define bTxMACHeader 0xffffffff -#define bTxDataInit 0xff -#define bTxHTMode 0x100 -#define bTxDataType 0x30000 -#define bTxRandomSeed 0xffffffff -#define bCCKTxPreamble 0x1 -#define bCCKTxSFD 0xffff0000 -#define bCCKTxSIG 0xff -#define bCCKTxService 0xff00 -#define bCCKLengthExt 0x8000 -#define bCCKTxLength 0xffff0000 -#define bCCKTxCRC16 0xffff -#define bCCKTxStatus 0x1 -#define bOFDMTxStatus 0x2 - -#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) -#define RF_TX_GAIN_OFFSET_8723D(_val) (abs((_val)) | (((_val) > 0) ? BIT(4) : 0)) - -/* 2. Page8(0x800) */ -#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ -#define bJapanMode 0x2 -#define bCCKTxSC 0x30 -#define bCCKEn 0x1000000 -#define bOFDMEn 0x2000000 - -#define bOFDMRxADCPhase 0x10000 /* Useless now */ -#define bOFDMTxDACPhase 0x40000 -#define bXATxAGC 0x3f - -#define bAntennaSelect 0x0300 - -#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ -#define bXCTxAGC 0xf000 -#define bXDTxAGC 0xf0000 - -#define bPAStart 0xf0000000 /* Useless now */ -#define bTRStart 0x00f00000 -#define bRFStart 0x0000f000 -#define bBBStart 0x000000f0 -#define bBBCCKStart 0x0000000f -#define bPAEnd 0xf /* Reg0x814 */ -#define bTREnd 0x0f000000 -#define bRFEnd 0x000f0000 -#define bCCAMask 0x000000f0 /* T2R */ -#define bR2RCCAMask 0x00000f00 -#define bHSSI_R2TDelay 0xf8000000 -#define bHSSI_T2RDelay 0xf80000 -#define bContTxHSSI 0x400 /* chane gain at continue Tx */ -#define bIGFromCCK 0x200 -#define bAGCAddress 0x3f -#define bRxHPTx 0x7000 -#define bRxHPT2R 0x38000 -#define bRxHPCCKIni 0xc0000 -#define bAGCTxCode 0xc00000 -#define bAGCRxCode 0x300000 - -#define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ -#define b3WireAddressLength 0x400 - -#define b3WireRFPowerDown 0x1 /* Useless now - * #define bHWSISelect 0x8 */ -#define b5GPAPEPolarity 0x40000000 -#define b2GPAPEPolarity 0x80000000 -#define bRFSW_TxDefaultAnt 0x3 -#define bRFSW_TxOptionAnt 0x30 -#define bRFSW_RxDefaultAnt 0x300 -#define bRFSW_RxOptionAnt 0x3000 -#define bRFSI_3WireData 0x1 -#define bRFSI_3WireClock 0x2 -#define bRFSI_3WireLoad 0x4 -#define bRFSI_3WireRW 0x8 -#define bRFSI_3Wire 0xf - -#define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ - -#define bRFSI_TRSW 0x20 /* Useless now */ -#define bRFSI_TRSWB 0x40 -#define bRFSI_ANTSW 0x100 -#define bRFSI_ANTSWB 0x200 -#define bRFSI_PAPE 0x400 -#define bRFSI_PAPE5G 0x800 -#define bBandSelect 0x1 -#define bHTSIG2_GI 0x80 -#define bHTSIG2_Smoothing 0x01 -#define bHTSIG2_Sounding 0x02 -#define bHTSIG2_Aggreaton 0x08 -#define bHTSIG2_STBC 0x30 -#define bHTSIG2_AdvCoding 0x40 -#define bHTSIG2_NumOfHTLTF 0x300 -#define bHTSIG2_CRC8 0x3fc -#define bHTSIG1_MCS 0x7f -#define bHTSIG1_BandWidth 0x80 -#define bHTSIG1_HTLength 0xffff -#define bLSIG_Rate 0xf -#define bLSIG_Reserved 0x10 -#define bLSIG_Length 0x1fffe -#define bLSIG_Parity 0x20 -#define bCCKRxPhase 0x4 - -#define bLSSIReadAddress 0x7f800000 /* T65 RF */ - -#define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ - -#define bLSSIReadBackData 0xfffff /* T65 RF */ - -#define bLSSIReadOKFlag 0x1000 /* Useless now */ -#define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ -#define bRegulator0Standby 0x1 -#define bRegulatorPLLStandby 0x2 -#define bRegulator1Standby 0x4 -#define bPLLPowerUp 0x8 -#define bDPLLPowerUp 0x10 -#define bDA10PowerUp 0x20 -#define bAD7PowerUp 0x200 -#define bDA6PowerUp 0x2000 -#define bXtalPowerUp 0x4000 -#define b40MDClkPowerUP 0x8000 -#define bDA6DebugMode 0x20000 -#define bDA6Swing 0x380000 - -#define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ - -#define b80MClkDelay 0x18000000 /* Useless */ -#define bAFEWatchDogEnable 0x20000000 - -#define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ -#define bXtalCap23 0x3 -#define bXtalCap92x 0x0f000000 -#define bXtalCap 0x0f000000 - -#define bIntDifClkEnable 0x400 /* Useless */ -#define bExtSigClkEnable 0x800 -#define bBandgapMbiasPowerUp 0x10000 -#define bAD11SHGain 0xc0000 -#define bAD11InputRange 0x700000 -#define bAD11OPCurrent 0x3800000 -#define bIPathLoopback 0x4000000 -#define bQPathLoopback 0x8000000 -#define bAFELoopback 0x10000000 -#define bDA10Swing 0x7e0 -#define bDA10Reverse 0x800 -#define bDAClkSource 0x1000 -#define bAD7InputRange 0x6000 -#define bAD7Gain 0x38000 -#define bAD7OutputCMMode 0x40000 -#define bAD7InputCMMode 0x380000 -#define bAD7Current 0xc00000 -#define bRegulatorAdjust 0x7000000 -#define bAD11PowerUpAtTx 0x1 -#define bDA10PSAtTx 0x10 -#define bAD11PowerUpAtRx 0x100 -#define bDA10PSAtRx 0x1000 -#define bCCKRxAGCFormat 0x200 -#define bPSDFFTSamplepPoint 0xc000 -#define bPSDAverageNum 0x3000 -#define bIQPathControl 0xc00 -#define bPSDFreq 0x3ff -#define bPSDAntennaPath 0x30 -#define bPSDIQSwitch 0x40 -#define bPSDRxTrigger 0x400000 -#define bPSDTxTrigger 0x80000000 -#define bPSDSineToneScale 0x7f000000 -#define bPSDReport 0xffff - -/* 3. Page9(0x900) */ -#define bOFDMTxSC 0x30000000 /* Useless */ -#define bCCKTxOn 0x1 -#define bOFDMTxOn 0x2 -#define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ -#define bDebugItem 0xff /* reset debug page and LWord */ -#define bAntL 0x10 -#define bAntNonHT 0x100 -#define bAntHT1 0x1000 -#define bAntHT2 0x10000 -#define bAntHT1S1 0x100000 -#define bAntNonHTS1 0x1000000 - -/* 4. PageA(0xA00) */ -#define bCCKBBMode 0x3 /* Useless */ -#define bCCKTxPowerSaving 0x80 -#define bCCKRxPowerSaving 0x40 - -#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ - -#define bCCKScramble 0x8 /* Useless */ -#define bCCKAntDiversity 0x8000 -#define bCCKCarrierRecovery 0x4000 -#define bCCKTxRate 0x3000 -#define bCCKDCCancel 0x0800 -#define bCCKISICancel 0x0400 -#define bCCKMatchFilter 0x0200 -#define bCCKEqualizer 0x0100 -#define bCCKPreambleDetect 0x800000 -#define bCCKFastFalseCCA 0x400000 -#define bCCKChEstStart 0x300000 -#define bCCKCCACount 0x080000 -#define bCCKcs_lim 0x070000 -#define bCCKBistMode 0x80000000 -#define bCCKCCAMask 0x40000000 -#define bCCKTxDACPhase 0x4 -#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ -#define bCCKr_cp_mode0 0x0100 -#define bCCKTxDCOffset 0xf0 -#define bCCKRxDCOffset 0xf -#define bCCKCCAMode 0xc000 -#define bCCKFalseCS_lim 0x3f00 -#define bCCKCS_ratio 0xc00000 -#define bCCKCorgBit_sel 0x300000 -#define bCCKPD_lim 0x0f0000 -#define bCCKNewCCA 0x80000000 -#define bCCKRxHPofIG 0x8000 -#define bCCKRxIG 0x7f00 -#define bCCKLNAPolarity 0x800000 -#define bCCKRx1stGain 0x7f0000 -#define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ -#define bCCKRxAGCSatLevel 0x1f000000 -#define bCCKRxAGCSatCount 0xe0 -#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ -#define bCCKFixedRxAGC 0x8000 -/* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ -#define bCCKAntennaPolarity 0x2000 -#define bCCKTxFilterType 0x0c00 -#define bCCKRxAGCReportType 0x0300 -#define bCCKRxDAGCEn 0x80000000 -#define bCCKRxDAGCPeriod 0x20000000 -#define bCCKRxDAGCSatLevel 0x1f000000 -#define bCCKTimingRecovery 0x800000 -#define bCCKTxC0 0x3f0000 -#define bCCKTxC1 0x3f000000 -#define bCCKTxC2 0x3f -#define bCCKTxC3 0x3f00 -#define bCCKTxC4 0x3f0000 -#define bCCKTxC5 0x3f000000 -#define bCCKTxC6 0x3f -#define bCCKTxC7 0x3f00 -#define bCCKDebugPort 0xff0000 -#define bCCKDACDebug 0x0f000000 -#define bCCKFalseAlarmEnable 0x8000 -#define bCCKFalseAlarmRead 0x4000 -#define bCCKTRSSI 0x7f -#define bCCKRxAGCReport 0xfe -#define bCCKRxReport_AntSel 0x80000000 -#define bCCKRxReport_MFOff 0x40000000 -#define bCCKRxRxReport_SQLoss 0x20000000 -#define bCCKRxReport_Pktloss 0x10000000 -#define bCCKRxReport_Lockedbit 0x08000000 -#define bCCKRxReport_RateError 0x04000000 -#define bCCKRxReport_RxRate 0x03000000 -#define bCCKRxFACounterLower 0xff -#define bCCKRxFACounterUpper 0xff000000 -#define bCCKRxHPAGCStart 0xe000 -#define bCCKRxHPAGCFinal 0x1c00 -#define bCCKRxFalseAlarmEnable 0x8000 -#define bCCKFACounterFreeze 0x4000 -#define bCCKTxPathSel 0x10000000 -#define bCCKDefaultRxPath 0xc000000 -#define bCCKOptionRxPath 0x3000000 - -/* 5. PageC(0xC00) */ -#define bNumOfSTF 0x3 /* Useless */ -#define bShift_L 0xc0 -#define bGI_TH 0xc -#define bRxPathA 0x1 -#define bRxPathB 0x2 -#define bRxPathC 0x4 -#define bRxPathD 0x8 -#define bTxPathA 0x1 -#define bTxPathB 0x2 -#define bTxPathC 0x4 -#define bTxPathD 0x8 -#define bTRSSIFreq 0x200 -#define bADCBackoff 0x3000 -#define bDFIRBackoff 0xc000 -#define bTRSSILatchPhase 0x10000 -#define bRxIDCOffset 0xff -#define bRxQDCOffset 0xff00 -#define bRxDFIRMode 0x1800000 -#define bRxDCNFType 0xe000000 -#define bRXIQImb_A 0x3ff -#define bRXIQImb_B 0xfc00 -#define bRXIQImb_C 0x3f0000 -#define bRXIQImb_D 0xffc00000 -#define bDC_dc_Notch 0x60000 -#define bRxNBINotch 0x1f000000 -#define bPD_TH 0xf -#define bPD_TH_Opt2 0xc000 -#define bPWED_TH 0x700 -#define bIfMF_Win_L 0x800 -#define bPD_Option 0x1000 -#define bMF_Win_L 0xe000 -#define bBW_Search_L 0x30000 -#define bwin_enh_L 0xc0000 -#define bBW_TH 0x700000 -#define bED_TH2 0x3800000 -#define bBW_option 0x4000000 -#define bRatio_TH 0x18000000 -#define bWindow_L 0xe0000000 -#define bSBD_Option 0x1 -#define bFrame_TH 0x1c -#define bFS_Option 0x60 -#define bDC_Slope_check 0x80 -#define bFGuard_Counter_DC_L 0xe00 -#define bFrame_Weight_Short 0x7000 -#define bSub_Tune 0xe00000 -#define bFrame_DC_Length 0xe000000 -#define bSBD_start_offset 0x30000000 -#define bFrame_TH_2 0x7 -#define bFrame_GI2_TH 0x38 -#define bGI2_Sync_en 0x40 -#define bSarch_Short_Early 0x300 -#define bSarch_Short_Late 0xc00 -#define bSarch_GI2_Late 0x70000 -#define bCFOAntSum 0x1 -#define bCFOAcc 0x2 -#define bCFOStartOffset 0xc -#define bCFOLookBack 0x70 -#define bCFOSumWeight 0x80 -#define bDAGCEnable 0x10000 -#define bTXIQImb_A 0x3ff -#define bTXIQImb_B 0xfc00 -#define bTXIQImb_C 0x3f0000 -#define bTXIQImb_D 0xffc00000 -#define bTxIDCOffset 0xff -#define bTxQDCOffset 0xff00 -#define bTxDFIRMode 0x10000 -#define bTxPesudoNoiseOn 0x4000000 -#define bTxPesudoNoise_A 0xff -#define bTxPesudoNoise_B 0xff00 -#define bTxPesudoNoise_C 0xff0000 -#define bTxPesudoNoise_D 0xff000000 -#define bCCADropOption 0x20000 -#define bCCADropThres 0xfff00000 -#define bEDCCA_H 0xf -#define bEDCCA_L 0xf0 -#define bLambda_ED 0x300 -#define bRxInitialGain 0x7f -#define bRxAntDivEn 0x80 -#define bRxAGCAddressForLNA 0x7f00 -#define bRxHighPowerFlow 0x8000 -#define bRxAGCFreezeThres 0xc0000 -#define bRxFreezeStep_AGC1 0x300000 -#define bRxFreezeStep_AGC2 0xc00000 -#define bRxFreezeStep_AGC3 0x3000000 -#define bRxFreezeStep_AGC0 0xc000000 -#define bRxRssi_Cmp_En 0x10000000 -#define bRxQuickAGCEn 0x20000000 -#define bRxAGCFreezeThresMode 0x40000000 -#define bRxOverFlowCheckType 0x80000000 -#define bRxAGCShift 0x7f -#define bTRSW_Tri_Only 0x80 -#define bPowerThres 0x300 -#define bRxAGCEn 0x1 -#define bRxAGCTogetherEn 0x2 -#define bRxAGCMin 0x4 -#define bRxHP_Ini 0x7 -#define bRxHP_TRLNA 0x70 -#define bRxHP_RSSI 0x700 -#define bRxHP_BBP1 0x7000 -#define bRxHP_BBP2 0x70000 -#define bRxHP_BBP3 0x700000 -#define bRSSI_H 0x7f0000 /* the threshold for high power */ -#define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ -#define bRxSettle_TRSW 0x7 -#define bRxSettle_LNA 0x38 -#define bRxSettle_RSSI 0x1c0 -#define bRxSettle_BBP 0xe00 -#define bRxSettle_RxHP 0x7000 -#define bRxSettle_AntSW_RSSI 0x38000 -#define bRxSettle_AntSW 0xc0000 -#define bRxProcessTime_DAGC 0x300000 -#define bRxSettle_HSSI 0x400000 -#define bRxProcessTime_BBPPW 0x800000 -#define bRxAntennaPowerShift 0x3000000 -#define bRSSITableSelect 0xc000000 -#define bRxHP_Final 0x7000000 -#define bRxHTSettle_BBP 0x7 -#define bRxHTSettle_HSSI 0x8 -#define bRxHTSettle_RxHP 0x70 -#define bRxHTSettle_BBPPW 0x80 -#define bRxHTSettle_Idle 0x300 -#define bRxHTSettle_Reserved 0x1c00 -#define bRxHTRxHPEn 0x8000 -#define bRxHTAGCFreezeThres 0x30000 -#define bRxHTAGCTogetherEn 0x40000 -#define bRxHTAGCMin 0x80000 -#define bRxHTAGCEn 0x100000 -#define bRxHTDAGCEn 0x200000 -#define bRxHTRxHP_BBP 0x1c00000 -#define bRxHTRxHP_Final 0xe0000000 -#define bRxPWRatioTH 0x3 -#define bRxPWRatioEn 0x4 -#define bRxMFHold 0x3800 -#define bRxPD_Delay_TH1 0x38 -#define bRxPD_Delay_TH2 0x1c0 -#define bRxPD_DC_COUNT_MAX 0x600 -/* #define bRxMF_Hold 0x3800 */ -#define bRxPD_Delay_TH 0x8000 -#define bRxProcess_Delay 0xf0000 -#define bRxSearchrange_GI2_Early 0x700000 -#define bRxFrame_Guard_Counter_L 0x3800000 -#define bRxSGI_Guard_L 0xc000000 -#define bRxSGI_Search_L 0x30000000 -#define bRxSGI_TH 0xc0000000 -#define bDFSCnt0 0xff -#define bDFSCnt1 0xff00 -#define bDFSFlag 0xf0000 -#define bMFWeightSum 0x300000 -#define bMinIdxTH 0x7f000000 -#define bDAFormat 0x40000 -#define bTxChEmuEnable 0x01000000 -#define bTRSWIsolation_A 0x7f -#define bTRSWIsolation_B 0x7f00 -#define bTRSWIsolation_C 0x7f0000 -#define bTRSWIsolation_D 0x7f000000 -#define bExtLNAGain 0x7c00 - -/* 6. PageE(0xE00) */ -#define bSTBCEn 0x4 /* Useless */ -#define bAntennaMapping 0x10 -#define bNss 0x20 -#define bCFOAntSumD 0x200 -#define bPHYCounterReset 0x8000000 -#define bCFOReportGet 0x4000000 -#define bOFDMContinueTx 0x10000000 -#define bOFDMSingleCarrier 0x20000000 -#define bOFDMSingleTone 0x40000000 -/* #define bRxPath1 0x01 */ -/* #define bRxPath2 0x02 */ -/* #define bRxPath3 0x04 */ -/* #define bRxPath4 0x08 */ -/* #define bTxPath1 0x10 */ -/* #define bTxPath2 0x20 */ -#define bHTDetect 0x100 -#define bCFOEn 0x10000 -#define bCFOValue 0xfff00000 -#define bSigTone_Re 0x3f -#define bSigTone_Im 0x7f00 -#define bCounter_CCA 0xffff -#define bCounter_ParityFail 0xffff0000 -#define bCounter_RateIllegal 0xffff -#define bCounter_CRC8Fail 0xffff0000 -#define bCounter_MCSNoSupport 0xffff -#define bCounter_FastSync 0xffff -#define bShortCFO 0xfff -#define bShortCFOTLength 12 /* total */ -#define bShortCFOFLength 11 /* fraction */ -#define bLongCFO 0x7ff -#define bLongCFOTLength 11 -#define bLongCFOFLength 11 -#define bTailCFO 0x1fff -#define bTailCFOTLength 13 -#define bTailCFOFLength 12 -#define bmax_en_pwdB 0xffff -#define bCC_power_dB 0xffff0000 -#define bnoise_pwdB 0xffff -#define bPowerMeasTLength 10 -#define bPowerMeasFLength 3 -#define bRx_HT_BW 0x1 -#define bRxSC 0x6 -#define bRx_HT 0x8 -#define bNB_intf_det_on 0x1 -#define bIntf_win_len_cfg 0x30 -#define bNB_Intf_TH_cfg 0x1c0 -#define bRFGain 0x3f -#define bTableSel 0x40 -#define bTRSW 0x80 -#define bRxSNR_A 0xff -#define bRxSNR_B 0xff00 -#define bRxSNR_C 0xff0000 -#define bRxSNR_D 0xff000000 -#define bSNREVMTLength 8 -#define bSNREVMFLength 1 -#define bCSI1st 0xff -#define bCSI2nd 0xff00 -#define bRxEVM1st 0xff0000 -#define bRxEVM2nd 0xff000000 -#define bSIGEVM 0xff -#define bPWDB 0xff00 -#define bSGIEN 0x10000 - -#define bSFactorQAM1 0xf /* Useless */ -#define bSFactorQAM2 0xf0 -#define bSFactorQAM3 0xf00 -#define bSFactorQAM4 0xf000 -#define bSFactorQAM5 0xf0000 -#define bSFactorQAM6 0xf0000 -#define bSFactorQAM7 0xf00000 -#define bSFactorQAM8 0xf000000 -#define bSFactorQAM9 0xf0000000 -#define bCSIScheme 0x100000 - -#define bNoiseLvlTopSet 0x3 /* Useless */ -#define bChSmooth 0x4 -#define bChSmoothCfg1 0x38 -#define bChSmoothCfg2 0x1c0 -#define bChSmoothCfg3 0xe00 -#define bChSmoothCfg4 0x7000 -#define bMRCMode 0x800000 -#define bTHEVMCfg 0x7000000 - -#define bLoopFitType 0x1 /* Useless */ -#define bUpdCFO 0x40 -#define bUpdCFOOffData 0x80 -#define bAdvUpdCFO 0x100 -#define bAdvTimeCtrl 0x800 -#define bUpdClko 0x1000 -#define bFC 0x6000 -#define bTrackingMode 0x8000 -#define bPhCmpEnable 0x10000 -#define bUpdClkoLTF 0x20000 -#define bComChCFO 0x40000 -#define bCSIEstiMode 0x80000 -#define bAdvUpdEqz 0x100000 -#define bUChCfg 0x7000000 -#define bUpdEqz 0x8000000 - -/* Rx Pseduo noise */ -#define bRxPesudoNoiseOn 0x20000000 /* Useless */ -#define bRxPesudoNoise_A 0xff -#define bRxPesudoNoise_B 0xff00 -#define bRxPesudoNoise_C 0xff0000 -#define bRxPesudoNoise_D 0xff000000 -#define bPesudoNoiseState_A 0xffff -#define bPesudoNoiseState_B 0xffff0000 -#define bPesudoNoiseState_C 0xffff -#define bPesudoNoiseState_D 0xffff0000 - -/* 7. RF Register - * Zebra1 */ -#define bZebra1_HSSIEnable 0x8 /* Useless */ -#define bZebra1_TRxControl 0xc00 -#define bZebra1_TRxGainSetting 0x07f -#define bZebra1_RxCorner 0xc00 -#define bZebra1_TxChargePump 0x38 -#define bZebra1_RxChargePump 0x7 -#define bZebra1_ChannelNum 0xf80 -#define bZebra1_TxLPFBW 0x400 -#define bZebra1_RxLPFBW 0x600 - -/* Zebra4 */ -#define bRTL8256RegModeCtrl1 0x100 /* Useless */ -#define bRTL8256RegModeCtrl0 0x40 -#define bRTL8256_TxLPFBW 0x18 -#define bRTL8256_RxLPFBW 0x600 - -/* RTL8258 */ -#define bRTL8258_TxLPFBW 0xc /* Useless */ -#define bRTL8258_RxLPFBW 0xc00 -#define bRTL8258_RSSILPFBW 0xc0 - - -/* - * Other Definition - * */ - -/* byte endable for sb_write */ -#define bByte0 0x1 /* Useless */ -#define bByte1 0x2 -#define bByte2 0x4 -#define bByte3 0x8 -#define bWord0 0x3 -#define bWord1 0xc -#define bDWord 0xf - -/* for PutRegsetting & GetRegSetting BitMask */ -#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ -#define bMaskByte1 0xff00 -#define bMaskByte2 0xff0000 -#define bMaskByte3 0xff000000 -#define bMaskHWord 0xffff0000 -#define bMaskLWord 0x0000ffff -#define bMaskDWord 0xffffffff -#define bMaskH3Bytes 0xffffff00 -#define bMask12Bits 0xfff -#define bMaskH4Bits 0xf0000000 -#define bMaskOFDM_D 0xffc00000 -#define bMaskCCK 0x3f3f3f3f - - -#define bEnable 0x1 /* Useless */ -#define bDisable 0x0 - -#define LeftAntenna 0x0 /* Useless */ -#define RightAntenna 0x1 - -#define tCheckTxStatus 500 /* 500ms // Useless */ -#define tUpdateRxCounter 100 /* 100ms */ - -#define rateCCK 0 /* Useless */ -#define rateOFDM 1 -#define rateHT 2 - -/* define Register-End */ -#define bPMAC_End 0x1ff /* Useless */ -#define bFPGAPHY0_End 0x8ff -#define bFPGAPHY1_End 0x9ff -#define bCCKPHY0_End 0xaff -#define bOFDMPHY0_End 0xcff -#define bOFDMPHY1_End 0xdff - -/* define max debug item in each debug page - * #define bMaxItem_FPGA_PHY0 0x9 - * #define bMaxItem_FPGA_PHY1 0x3 - * #define bMaxItem_PHY_11B 0x16 - * #define bMaxItem_OFDM_PHY0 0x29 - * #define bMaxItem_OFDM_PHY1 0x0 */ - -#define bPMACControl 0x0 /* Useless */ -#define bWMACControl 0x1 -#define bWNICControl 0x2 - -#define PathA 0x0 /* Useless */ -#define PathB 0x1 -#define PathC 0x2 -#define PathD 0x3 - -#endif diff --git a/include/Hal8723DPwrSeq.h b/include/Hal8723DPwrSeq.h deleted file mode 100644 index 5032e7c..0000000 --- a/include/Hal8723DPwrSeq.h +++ /dev/null @@ -1,193 +0,0 @@ -#ifndef REALTEK_POWER_SEQUENCE_8723D -#define REALTEK_POWER_SEQUENCE_8723D - -/* #include "PwrSeqCmd.h" */ -#include "HalPwrSeqCmd.h" - -/* - Check document WM-20110607-Paul-RTL8192e_Power_Architecture-R02.vsd - There are 6 HW Power States: - 0: POFF--Power Off - 1: PDN--Power Down - 2: CARDEMU--Card Emulation - 3: ACT--Active Mode - 4: LPS--Low Power State - 5: SUS--Suspend - - The transition from different states are defined below - TRANS_CARDEMU_TO_ACT - TRANS_ACT_TO_CARDEMU - TRANS_CARDEMU_TO_SUS - TRANS_SUS_TO_CARDEMU - TRANS_CARDEMU_TO_PDN - TRANS_ACT_TO_LPS - TRANS_LPS_TO_ACT - - TRANS_END -*/ -#define RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS 27 -#define RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS 8 -#define RTL8723D_TRANS_CARDEMU_TO_SUS_STEPS 7 -#define RTL8723D_TRANS_SUS_TO_CARDEMU_STEPS 5 -#define RTL8723D_TRANS_CARDEMU_TO_CARDDIS_STEPS 8 -#define RTL8723D_TRANS_CARDDIS_TO_CARDEMU_STEPS 7 -#define RTL8723D_TRANS_CARDEMU_TO_PDN_STEPS 4 -#define RTL8723D_TRANS_PDN_TO_CARDEMU_STEPS 1 -#define RTL8723D_TRANS_ACT_TO_LPS_STEPS 13 -#define RTL8723D_TRANS_LPS_TO_ACT_STEPS 11 -#define RTL8723D_TRANS_END_STEPS 1 - - -#define RTL8723D_TRANS_CARDEMU_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \ - {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ - {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \ - {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \ - {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \ - {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)},/* Disable USB suspend */ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},/* wait till 0x04[17] = 1 power ready*/ \ - {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0},/* Enable USB suspend */ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/* release WLON reset 0x04[16]=1*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, (BIT(1) | BIT(0)), 0}, \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},/* disable HWPDN 0x04[15]=0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},/* disable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/* polling until return 0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},/**/ \ - {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},/* Enable WL control XTAL setting*/ \ - {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},/*Enable falling edge triggering interrupt*/\ - {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},/*Enable GPIO9 interrupt mode*/\ - {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*Enable GPIO9 input mode*/\ - {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/*Enable HSISR GPIO[C:0] interrupt*/\ - {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},/*Enable HSISR GPIO9 interrupt*/\ - {0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3), BIT(3)},/*For GPIO9 internal pull high setting by test chip*/\ - {0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},/*For GPIO9 internal pull high setting*/\ - {0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S1*/\ - {0x0077, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S0*/\ - {0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/*enable RF path S1*/\ - {0x0077, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/*enalbe RF path S0*/\ - - -#define RTL8723D_TRANS_ACT_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \ - /*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, */ /*0x1F[7:0] = 0 turn off RF*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, /*0x2[0]=0 Reset BB, RF enter Power Down mode*/ \ - {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*Enable rising edge triggering interrupt*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/* release WLON reset 0x04[16]=1*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ - {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), 0},/* Enable BT control XTAL setting*/\ - {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \ - {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\ - - -#define RTL8723D_TRANS_CARDEMU_TO_SUS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/ - -#define RTL8723D_TRANS_SUS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, /*clear suspend enable and power down enable*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ - - -#define RTL8723D_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)}, /*0x04[10] = 1, enable SW LPS*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend*/ \ - {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/ - -#define RTL8723D_TRANS_CARDDIS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, /*clear suspend enable and power down enable*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\ - {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ - - -#define RTL8723D_TRANS_CARDEMU_TO_PDN \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/ - -#define RTL8723D_TRANS_PDN_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/ - -#define RTL8723D_TRANS_ACT_TO_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ - {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},/*CCK and OFDM are disabled, and clock are gated*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \ - {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \ - {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},/*Respond TxOK to scheduler*/ \ - - -#define RTL8723D_TRANS_LPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ - {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ - {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ - {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ - {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6) | BIT(7), 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, /*. 0x101[1] = 1*/\ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ - -#define RTL8723D_TRANS_END \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \ - {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0}, - - - extern WLAN_PWR_CFG rtl8723D_power_on_flow[RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723D_radio_off_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723D_card_disable_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_CARDDIS_STEPS + RTL8723D_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723D_card_enable_flow[RTL8723D_TRANS_CARDDIS_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723D_suspend_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723D_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723D_resume_flow[RTL8723D_TRANS_SUS_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723D_hwpdn_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723D_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723D_enter_lps_flow[RTL8723D_TRANS_ACT_TO_LPS_STEPS + RTL8723D_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723D_leave_lps_flow[RTL8723D_TRANS_LPS_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS]; - -#endif diff --git a/include/Hal8723PwrSeq.h b/include/Hal8723PwrSeq.h deleted file mode 100644 index 6669641..0000000 --- a/include/Hal8723PwrSeq.h +++ /dev/null @@ -1,169 +0,0 @@ -#ifndef __HAL8723PWRSEQ_H__ -#define __HAL8723PWRSEQ_H__ -/* - Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd - There are 6 HW Power States: - 0: POFF--Power Off - 1: PDN--Power Down - 2: CARDEMU--Card Emulation - 3: ACT--Active Mode - 4: LPS--Low Power State - 5: SUS--Suspend - - The transision from different states are defined below - TRANS_CARDEMU_TO_ACT - TRANS_ACT_TO_CARDEMU - TRANS_CARDEMU_TO_SUS - TRANS_SUS_TO_CARDEMU - TRANS_CARDEMU_TO_PDN - TRANS_ACT_TO_LPS - TRANS_LPS_TO_ACT - - TRANS_END -*/ -#include "HalPwrSeqCmd.h" - -#define RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS 15 -#define RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS 15 -#define RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS 15 -#define RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS 15 -#define RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS 15 -#define RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS 15 -#define RTL8723A_TRANS_ACT_TO_LPS_STEPS 15 -#define RTL8723A_TRANS_LPS_TO_ACT_STEPS 15 -#define RTL8723A_TRANS_END_STEPS 1 - - -#define RTL8723A_TRANS_CARDEMU_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ - {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \ - {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \ - {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \ - {0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 1},/*0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */\ - -#define RTL8723A_TRANS_ACT_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ - {0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ - {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \ - {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \ - - -#define RTL8723A_TRANS_CARDEMU_TO_SUS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ - -#define RTL8723A_TRANS_SUS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ - -#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \ - {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ - -#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ - {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ - - -#define RTL8723A_TRANS_CARDEMU_TO_PDN \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ - -#define RTL8723A_TRANS_PDN_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ - -#define RTL8723A_TRANS_ACT_TO_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ - {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ - {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \ - {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \ - - -#define RTL8723A_TRANS_LPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ - {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ - {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ - {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ - {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ - -#define RTL8723A_TRANS_END \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0}, - - - extern WLAN_PWR_CFG rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723A_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723A_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723A_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723A_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723A_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723A_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723A_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723A_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723A_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723A_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723A_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723A_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STEPS + RTL8723A_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STEPS + RTL8723A_TRANS_END_STEPS]; - -#endif diff --git a/include/Hal8812PhyCfg.h b/include/Hal8812PhyCfg.h deleted file mode 100644 index 05a5fe2..0000000 --- a/include/Hal8812PhyCfg.h +++ /dev/null @@ -1,148 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_HAL8812PHYCFG_H__ -#define __INC_HAL8812PHYCFG_H__ - - -/*--------------------------Define Parameters-------------------------------*/ -#define LOOP_LIMIT 5 -#define MAX_STALL_TIME 50 /* us */ -#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */ -#define MAX_TXPWR_IDX_NMODE_92S 63 -#define Reset_Cnt_Limit 3 - - -#ifdef CONFIG_PCI_HCI - #define MAX_AGGR_NUM 0x0B -#else - #define MAX_AGGR_NUM 0x07 -#endif /* CONFIG_PCI_HCI */ - - -/*--------------------------Define Parameters-------------------------------*/ - -/*------------------------------Define structure----------------------------*/ - - -/* BB/RF related */ - -/*------------------------------Define structure----------------------------*/ - - -/*------------------------Export global variable----------------------------*/ -/*------------------------Export global variable----------------------------*/ - - -/*------------------------Export Marco Definition---------------------------*/ -/*------------------------Export Marco Definition---------------------------*/ - - -/*--------------------------Exported Function prototype---------------------*/ -/* - * BB and RF register read/write - * */ -u32 PHY_QueryBBReg8812(IN PADAPTER Adapter, - IN u32 RegAddr, - IN u32 BitMask); -void PHY_SetBBReg8812(IN PADAPTER Adapter, - IN u32 RegAddr, - IN u32 BitMask, - IN u32 Data); -u32 PHY_QueryRFReg8812(IN PADAPTER Adapter, - IN u8 eRFPath, - IN u32 RegAddr, - IN u32 BitMask); -void PHY_SetRFReg8812(IN PADAPTER Adapter, - IN u8 eRFPath, - IN u32 RegAddr, - IN u32 BitMask, - IN u32 Data); - -/* - * Initialization related function - * - * MAC/BB/RF HAL config */ -int PHY_MACConfig8812(IN PADAPTER Adapter); -int PHY_BBConfig8812(IN PADAPTER Adapter); -void PHY_BB8812_Config_1T(IN PADAPTER Adapter); -int PHY_RFConfig8812(IN PADAPTER Adapter); - -/* RF config */ - -s32 -PHY_SwitchWirelessBand8812( - IN PADAPTER Adapter, - IN u8 Band -); - -/* - * BB TX Power R/W - * */ -void PHY_GetTxPowerLevel8812(IN PADAPTER Adapter, OUT s32 *powerlevel); -void PHY_SetTxPowerLevel8812(IN PADAPTER Adapter, IN u8 Channel); - -BOOLEAN PHY_UpdateTxPowerDbm8812(IN PADAPTER Adapter, IN int powerInDbm); -u8 PHY_GetTxPowerIndex_8812A( - IN PADAPTER pAdapter, - IN u8 RFPath, - IN u8 Rate, - IN u8 BandWidth, - IN u8 Channel, - struct txpwr_idx_comp *tic -); - -u32 phy_get_tx_bb_swing_8812a( - IN PADAPTER Adapter, - IN BAND_TYPE Band, - IN u8 RFPath -); - -VOID -PHY_SetTxPowerIndex_8812A( - IN PADAPTER Adapter, - IN u4Byte PowerIndex, - IN u1Byte RFPath, - IN u1Byte Rate -); - -/* - * channel switch related funciton - * */ -VOID -PHY_SetSwChnlBWMode8812( - IN PADAPTER Adapter, - IN u8 channel, - IN CHANNEL_WIDTH Bandwidth, - IN u8 Offset40, - IN u8 Offset80 -); - -/* - * BB/MAC/RF other monitor API - * */ - -VOID -phy_set_rf_path_switch_8812a( - IN PADAPTER pAdapter, - IN bool bMain -); - -/*--------------------------Exported Function prototype---------------------*/ -#endif /* __INC_HAL8192CPHYCFG_H */ diff --git a/include/Hal8812PhyReg.h b/include/Hal8812PhyReg.h deleted file mode 100644 index 5009750..0000000 --- a/include/Hal8812PhyReg.h +++ /dev/null @@ -1,738 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_HAL8812PHYREG_H__ -#define __INC_HAL8812PHYREG_H__ -/*--------------------------Define Parameters-------------------------------*/ -/* - * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF - * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF - * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 - * 3. RF register 0x00-2E - * 4. Bit Mask for BB/RF register - * 5. Other defintion for BB/RF R/W - * */ - - -/* BB Register Definition */ - -#define rCCAonSec_Jaguar 0x838 -#define rPwed_TH_Jaguar 0x830 - -/* BW and sideband setting */ -#define rBWIndication_Jaguar 0x834 -#define rL1PeakTH_Jaguar 0x848 -#define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/ -#define rRFMOD_Jaguar 0x8ac /* RF mode */ -#define rADC_Buf_Clk_Jaguar 0x8c4 -#define rRFECTRL_Jaguar 0x900 -#define bRFMOD_Jaguar 0xc3 -#define rCCK_System_Jaguar 0xa00 /* for cck sideband */ -#define bCCK_System_Jaguar 0x10 - -/* Block & Path enable */ -#define rOFDMCCKEN_Jaguar 0x808 /* OFDM/CCK block enable */ -#define bOFDMEN_Jaguar 0x20000000 -#define bCCKEN_Jaguar 0x10000000 -#define rRxPath_Jaguar 0x808 /* Rx antenna */ -#define bRxPath_Jaguar 0xff -#define rTxPath_Jaguar 0x80c /* Tx antenna */ -#define bTxPath_Jaguar 0x0fffffff -#define rCCK_RX_Jaguar 0xa04 /* for cck rx path selection */ -#define bCCK_RX_Jaguar 0x0c000000 -#define rVhtlen_Use_Lsig_Jaguar 0x8c3 /* Use LSIG for VHT length */ - -/* RF read/write-related */ -#define rHSSIRead_Jaguar 0x8b0 /* RF read addr */ -#define bHSSIRead_addr_Jaguar 0xff -#define bHSSIRead_trigger_Jaguar 0x100 -#define rA_PIRead_Jaguar 0xd04 /* RF readback with PI */ -#define rB_PIRead_Jaguar 0xd44 /* RF readback with PI */ -#define rA_SIRead_Jaguar 0xd08 /* RF readback with SI */ -#define rB_SIRead_Jaguar 0xd48 /* RF readback with SI */ -#define rRead_data_Jaguar 0xfffff -#define rA_LSSIWrite_Jaguar 0xc90 /* RF write addr */ -#define rB_LSSIWrite_Jaguar 0xe90 /* RF write addr */ -#define bLSSIWrite_data_Jaguar 0x000fffff -#define bLSSIWrite_addr_Jaguar 0x0ff00000 - - - -/* YN: mask the following register definition temporarily */ -#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ -#define rFPGA0_XB_RFInterfaceOE 0x864 - -#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ -#define rFPGA0_XCD_RFInterfaceSW 0x874 - -/* #define rFPGA0_XAB_RFParameter 0x878 */ /* RF Parameter - * #define rFPGA0_XCD_RFParameter 0x87c */ - -/* #define rFPGA0_AnalogParameter1 0x880 */ /* Crystal cap setting RF-R/W protection for parameter4?? - * #define rFPGA0_AnalogParameter2 0x884 - * #define rFPGA0_AnalogParameter3 0x888 - * #define rFPGA0_AdDaClockEn 0x888 */ /* enable ad/da clock1 for dual-phy - * #define rFPGA0_AnalogParameter4 0x88c */ - - -/* CCK TX scaling */ -#define rCCK_TxFilter1_Jaguar 0xa20 -#define bCCK_TxFilter1_C0_Jaguar 0x00ff0000 -#define bCCK_TxFilter1_C1_Jaguar 0xff000000 -#define rCCK_TxFilter2_Jaguar 0xa24 -#define bCCK_TxFilter2_C2_Jaguar 0x000000ff -#define bCCK_TxFilter2_C3_Jaguar 0x0000ff00 -#define bCCK_TxFilter2_C4_Jaguar 0x00ff0000 -#define bCCK_TxFilter2_C5_Jaguar 0xff000000 -#define rCCK_TxFilter3_Jaguar 0xa28 -#define bCCK_TxFilter3_C6_Jaguar 0x000000ff -#define bCCK_TxFilter3_C7_Jaguar 0x0000ff00 - - -/* YN: mask the following register definition temporarily - * #define rPdp_AntA 0xb00 - * #define rPdp_AntA_4 0xb04 - * #define rConfig_Pmpd_AntA 0xb28 - * #define rConfig_AntA 0xb68 - * #define rConfig_AntB 0xb6c - * #define rPdp_AntB 0xb70 - * #define rPdp_AntB_4 0xb74 - * #define rConfig_Pmpd_AntB 0xb98 - * #define rAPK 0xbd8 */ - -/* RXIQC */ -#define rA_RxIQC_AB_Jaguar 0xc10 /* RxIQ imblance matrix coeff. A & B */ -#define rA_RxIQC_CD_Jaguar 0xc14 /* RxIQ imblance matrix coeff. C & D */ -#define rA_TxScale_Jaguar 0xc1c /* Pah_A TX scaling factor */ -#define rB_TxScale_Jaguar 0xe1c /* Path_B TX scaling factor */ -#define rB_RxIQC_AB_Jaguar 0xe10 /* RxIQ imblance matrix coeff. A & B */ -#define rB_RxIQC_CD_Jaguar 0xe14 /* RxIQ imblance matrix coeff. C & D */ -#define b_RxIQC_AC_Jaguar 0x02ff /* bit mask for IQC matrix element A & C */ -#define b_RxIQC_BD_Jaguar 0x02ff0000 /* bit mask for IQC matrix element A & C */ - - -/* DIG-related */ -#define rA_IGI_Jaguar 0xc50 /* Initial Gain for path-A */ -#define rB_IGI_Jaguar 0xe50 /* Initial Gain for path-B */ -#define rOFDM_FalseAlarm1_Jaguar 0xf48 /* counter for break */ -#define rOFDM_FalseAlarm2_Jaguar 0xf4c /* counter for spoofing */ -#define rCCK_FalseAlarm_Jaguar 0xa5c /* counter for cck false alarm */ -#define b_FalseAlarm_Jaguar 0xffff -#define rCCK_CCA_Jaguar 0xa08 /* cca threshold */ -#define bCCK_CCA_Jaguar 0x00ff0000 - -/* Tx Power Ttraining-related */ -#define rA_TxPwrTraing_Jaguar 0xc54 -#define rB_TxPwrTraing_Jaguar 0xe54 - -/* Report-related */ -#define rOFDM_ShortCFOAB_Jaguar 0xf60 -#define rOFDM_LongCFOAB_Jaguar 0xf64 -#define rOFDM_EndCFOAB_Jaguar 0xf70 -#define rOFDM_AGCReport_Jaguar 0xf84 -#define rOFDM_RxSNR_Jaguar 0xf88 -#define rOFDM_RxEVMCSI_Jaguar 0xf8c -#define rOFDM_SIGReport_Jaguar 0xf90 - -/* Misc functions */ -#define rEDCCA_Jaguar 0x8a4 /* EDCCA */ -#define bEDCCA_Jaguar 0xffff -#define rAGC_table_Jaguar 0x82c /* AGC tabel select */ -#define bAGC_table_Jaguar 0x3 -#define b_sel5g_Jaguar 0x1000 /* sel5g */ -#define b_LNA_sw_Jaguar 0x8000 /* HW/WS control for LNA */ -#define rFc_area_Jaguar 0x860 /* fc_area */ -#define bFc_area_Jaguar 0x1ffe000 -#define rSingleTone_ContTx_Jaguar 0x914 - -/* RFE */ -#define rA_RFE_Pinmux_Jaguar 0xcb0 /* Path_A RFE cotrol pinmux */ -#define rB_RFE_Pinmux_Jaguar 0xeb0 /* Path_B RFE control pinmux */ -#define rA_RFE_Inv_Jaguar 0xcb4 /* Path_A RFE cotrol */ -#define rB_RFE_Inv_Jaguar 0xeb4 /* Path_B RFE control */ -#define rA_RFE_Jaguar 0xcb8 /* Path_A RFE cotrol */ -#define rB_RFE_Jaguar 0xeb8 /* Path_B RFE control */ -#define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */ -#define bMask_RFEInv_Jaguar 0x3ff00000 -#define bMask_AntselPathFollow_Jaguar 0x00030000 - -/* TX AGC */ -#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20 -#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24 -#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28 -#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c -#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30 -#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34 -#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38 -#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c -#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40 -#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44 -#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48 -#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c -#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20 -#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24 -#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28 -#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c -#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30 -#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34 -#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38 -#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c -#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40 -#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44 -#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48 -#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c -#define bTxAGC_byte0_Jaguar 0xff -#define bTxAGC_byte1_Jaguar 0xff00 -#define bTxAGC_byte2_Jaguar 0xff0000 -#define bTxAGC_byte3_Jaguar 0xff000000 - -/* IQK YN: temporaily mask this part - * #define rFPGA0_IQK 0xe28 - * #define rTx_IQK_Tone_A 0xe30 - * #define rRx_IQK_Tone_A 0xe34 - * #define rTx_IQK_PI_A 0xe38 - * #define rRx_IQK_PI_A 0xe3c */ - -/* #define rTx_IQK 0xe40 */ -/* #define rRx_IQK 0xe44 */ -/* #define rIQK_AGC_Pts 0xe48 */ -/* #define rIQK_AGC_Rsp 0xe4c */ -/* #define rTx_IQK_Tone_B 0xe50 */ -/* #define rRx_IQK_Tone_B 0xe54 */ -/* #define rTx_IQK_PI_B 0xe58 */ -/* #define rRx_IQK_PI_B 0xe5c */ -/* #define rIQK_AGC_Cont 0xe60 */ - - -/* AFE-related */ -#define rA_AFEPwr1_Jaguar 0xc60 /* dynamic AFE power control */ -#define rA_AFEPwr2_Jaguar 0xc64 /* dynamic AFE power control */ -#define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xc68 -#define rA_Tx_CCKBBON_OFDMRFON_Jaguar 0xc6c -#define rA_Tx_OFDMBBON_Tx2Rx_Jaguar 0xc70 -#define rA_Tx2Tx_RXCCK_Jaguar 0xc74 -#define rA_Rx_OFDM_WaitRIFS_Jaguar 0xc78 -#define rA_Rx2Rx_BT_Jaguar 0xc7c -#define rA_sleep_nav_Jaguar 0xc80 -#define rA_pmpd_Jaguar 0xc84 -#define rB_AFEPwr1_Jaguar 0xe60 /* dynamic AFE power control */ -#define rB_AFEPwr2_Jaguar 0xe64 /* dynamic AFE power control */ -#define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xe68 -#define rB_Tx_CCKBBON_OFDMRFON_Jaguar 0xe6c -#define rB_Tx_OFDMBBON_Tx2Rx_Jaguar 0xe70 -#define rB_Tx2Tx_RXCCK_Jaguar 0xe74 -#define rB_Rx_OFDM_WaitRIFS_Jaguar 0xe78 -#define rB_Rx2Rx_BT_Jaguar 0xe7c -#define rB_sleep_nav_Jaguar 0xe80 -#define rB_pmpd_Jaguar 0xe84 - - -/* YN: mask these registers temporaily - * #define rTx_Power_Before_IQK_A 0xe94 - * #define rTx_Power_After_IQK_A 0xe9c */ - -/* #define rRx_Power_Before_IQK_A 0xea0 */ -/* #define rRx_Power_Before_IQK_A_2 0xea4 */ -/* #define rRx_Power_After_IQK_A 0xea8 */ -/* #define rRx_Power_After_IQK_A_2 0xeac */ - -/* #define rTx_Power_Before_IQK_B 0xeb4 */ -/* #define rTx_Power_After_IQK_B 0xebc */ - -/* #define rRx_Power_Before_IQK_B 0xec0 */ -/* #define rRx_Power_Before_IQK_B_2 0xec4 */ -/* #define rRx_Power_After_IQK_B 0xec8 */ -/* #define rRx_Power_After_IQK_B_2 0xecc */ - - -/* RSSI Dump */ -#define rA_RSSIDump_Jaguar 0xBF0 -#define rB_RSSIDump_Jaguar 0xBF1 -#define rS1_RXevmDump_Jaguar 0xBF4 -#define rS2_RXevmDump_Jaguar 0xBF5 -#define rA_RXsnrDump_Jaguar 0xBF6 -#define rB_RXsnrDump_Jaguar 0xBF7 -#define rA_CfoShortDump_Jaguar 0xBF8 -#define rB_CfoShortDump_Jaguar 0xBFA -#define rA_CfoLongDump_Jaguar 0xBEC -#define rB_CfoLongDump_Jaguar 0xBEE - - -/* RF Register - * */ -#define RF_AC_Jaguar 0x00 /* */ -#define RF_RF_Top_Jaguar 0x07 /* */ -#define RF_TXLOK_Jaguar 0x08 /* */ -#define RF_TXAPK_Jaguar 0x0B -#define RF_CHNLBW_Jaguar 0x18 /* RF channel and BW switch */ -#define RF_RCK1_Jaguar 0x1c /* */ -#define RF_RCK2_Jaguar 0x1d -#define RF_RCK3_Jaguar 0x1e -#define RF_ModeTableAddr 0x30 -#define RF_ModeTableData0 0x31 -#define RF_ModeTableData1 0x32 -#define RF_TxLCTank_Jaguar 0x54 -#define RF_APK_Jaguar 0x63 -#define RF_LCK 0xB4 -#define RF_WeLut_Jaguar 0xEF - -#define bRF_CHNLBW_MOD_AG_Jaguar 0x70300 -#define bRF_CHNLBW_BW 0xc00 - - -/* - * RL6052 Register definition - * */ -#define RF_AC 0x00 /* */ -#define RF_IPA_A 0x0C /* */ -#define RF_TXBIAS_A 0x0D -#define RF_BS_PA_APSET_G9_G11 0x0E -#define RF_MODE1 0x10 /* */ -#define RF_MODE2 0x11 /* */ -#define RF_CHNLBW 0x18 /* RF channel and BW switch */ -#define RF_RCK_OS 0x30 /* RF TX PA control */ -#define RF_TXPA_G1 0x31 /* RF TX PA control */ -#define RF_TXPA_G2 0x32 /* RF TX PA control */ -#define RF_TXPA_G3 0x33 /* RF TX PA control */ -#define RF_0x52 0x52 -#define RF_WE_LUT 0xEF - -#define RF_TX_GAIN_OFFSET_8812A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0)) -#define RF_TX_GAIN_OFFSET_8821A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0)) - -/* - * Bit Mask - * - * 1. Page1(0x100) */ -#define bBBResetB 0x100 /* Useless now? */ -#define bGlobalResetB 0x200 -#define bOFDMTxStart 0x4 -#define bCCKTxStart 0x8 -#define bCRC32Debug 0x100 -#define bPMACLoopback 0x10 -#define bTxLSIG 0xffffff -#define bOFDMTxRate 0xf -#define bOFDMTxReserved 0x10 -#define bOFDMTxLength 0x1ffe0 -#define bOFDMTxParity 0x20000 -#define bTxHTSIG1 0xffffff -#define bTxHTMCSRate 0x7f -#define bTxHTBW 0x80 -#define bTxHTLength 0xffff00 -#define bTxHTSIG2 0xffffff -#define bTxHTSmoothing 0x1 -#define bTxHTSounding 0x2 -#define bTxHTReserved 0x4 -#define bTxHTAggreation 0x8 -#define bTxHTSTBC 0x30 -#define bTxHTAdvanceCoding 0x40 -#define bTxHTShortGI 0x80 -#define bTxHTNumberHT_LTF 0x300 -#define bTxHTCRC8 0x3fc00 -#define bCounterReset 0x10000 -#define bNumOfOFDMTx 0xffff -#define bNumOfCCKTx 0xffff0000 -#define bTxIdleInterval 0xffff -#define bOFDMService 0xffff0000 -#define bTxMACHeader 0xffffffff -#define bTxDataInit 0xff -#define bTxHTMode 0x100 -#define bTxDataType 0x30000 -#define bTxRandomSeed 0xffffffff -#define bCCKTxPreamble 0x1 -#define bCCKTxSFD 0xffff0000 -#define bCCKTxSIG 0xff -#define bCCKTxService 0xff00 -#define bCCKLengthExt 0x8000 -#define bCCKTxLength 0xffff0000 -#define bCCKTxCRC16 0xffff -#define bCCKTxStatus 0x1 -#define bOFDMTxStatus 0x2 - - -/* - * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF - * 1. Page1(0x100) - * */ -#define rPMAC_Reset 0x100 -#define rPMAC_TxStart 0x104 -#define rPMAC_TxLegacySIG 0x108 -#define rPMAC_TxHTSIG1 0x10c -#define rPMAC_TxHTSIG2 0x110 -#define rPMAC_PHYDebug 0x114 -#define rPMAC_TxPacketNum 0x118 -#define rPMAC_TxIdle 0x11c -#define rPMAC_TxMACHeader0 0x120 -#define rPMAC_TxMACHeader1 0x124 -#define rPMAC_TxMACHeader2 0x128 -#define rPMAC_TxMACHeader3 0x12c -#define rPMAC_TxMACHeader4 0x130 -#define rPMAC_TxMACHeader5 0x134 -#define rPMAC_TxDataType 0x138 -#define rPMAC_TxRandomSeed 0x13c -#define rPMAC_CCKPLCPPreamble 0x140 -#define rPMAC_CCKPLCPHeader 0x144 -#define rPMAC_CCKCRC16 0x148 -#define rPMAC_OFDMRxCRC32OK 0x170 -#define rPMAC_OFDMRxCRC32Er 0x174 -#define rPMAC_OFDMRxParityEr 0x178 -#define rPMAC_OFDMRxCRC8Er 0x17c -#define rPMAC_CCKCRxRC16Er 0x180 -#define rPMAC_CCKCRxRC32Er 0x184 -#define rPMAC_CCKCRxRC32OK 0x188 -#define rPMAC_TxStatus 0x18c - -/* - * 3. Page8(0x800) - * */ -#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */ - -#define rFPGA0_TxInfo 0x804 /* Status report?? */ -#define rFPGA0_PSDFunction 0x808 -#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ - -#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ -#define rFPGA0_XA_HSSIParameter2 0x824 -#define rFPGA0_XB_HSSIParameter1 0x828 -#define rFPGA0_XB_HSSIParameter2 0x82c - -#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ -#define rFPGA0_XCD_SwitchControl 0x85c - -#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ -#define rFPGA0_XCD_RFParameter 0x87c - -#define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ -#define rFPGA0_AnalogParameter2 0x884 -#define rFPGA0_AnalogParameter3 0x888 -#define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */ -#define rFPGA0_AnalogParameter4 0x88c -#define rFPGA0_XB_LSSIReadBack 0x8a4 -#define rFPGA0_XCD_RFPara 0x8b4 - -/* - * 4. Page9(0x900) - * */ -#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */ - -#define rFPGA1_TxBlock 0x904 /* Useless now */ -#define rFPGA1_DebugSelect 0x908 /* Useless now */ -#define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */ - -/* - * PageA(0xA00) - * */ -#define rCCK0_System 0xa00 -#define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */ -#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ -#define rCCK0_TxFilter1 0xa20 -#define rCCK0_TxFilter2 0xa24 -#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ -#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ - -/* - * PageB(0xB00) - * */ -#define rPdp_AntA 0xb00 -#define rPdp_AntA_4 0xb04 -#define rConfig_Pmpd_AntA 0xb28 -#define rConfig_AntA 0xb68 -#define rConfig_AntB 0xb6c -#define rPdp_AntB 0xb70 -#define rPdp_AntB_4 0xb74 -#define rConfig_Pmpd_AntB 0xb98 -#define rAPK 0xbd8 - -/* - * 6. PageC(0xC00) - * */ -#define rOFDM0_LSTF 0xc00 - -#define rOFDM0_TRxPathEnable 0xc04 -#define rOFDM0_TRMuxPar 0xc08 -#define rOFDM0_TRSWIsolation 0xc0c - -#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ -#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ -#define rOFDM0_XBRxAFE 0xc18 -#define rOFDM0_XBRxIQImbalance 0xc1c -#define rOFDM0_XCRxAFE 0xc20 -#define rOFDM0_XCRxIQImbalance 0xc24 -#define rOFDM0_XDRxAFE 0xc28 -#define rOFDM0_XDRxIQImbalance 0xc2c - -#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */ -#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ -#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ -#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ - -#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ -#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ -#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ -#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ - -#define rOFDM0_XAAGCCore1 0xc50 /* DIG */ -#define rOFDM0_XAAGCCore2 0xc54 -#define rOFDM0_XBAGCCore1 0xc58 -#define rOFDM0_XBAGCCore2 0xc5c -#define rOFDM0_XCAGCCore1 0xc60 -#define rOFDM0_XCAGCCore2 0xc64 -#define rOFDM0_XDAGCCore1 0xc68 -#define rOFDM0_XDAGCCore2 0xc6c - -#define rOFDM0_AGCParameter1 0xc70 -#define rOFDM0_AGCParameter2 0xc74 -#define rOFDM0_AGCRSSITable 0xc78 -#define rOFDM0_HTSTFAGC 0xc7c - -#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ -#define rOFDM0_XATxAFE 0xc84 -#define rOFDM0_XBTxIQImbalance 0xc88 -#define rOFDM0_XBTxAFE 0xc8c -#define rOFDM0_XCTxIQImbalance 0xc90 -#define rOFDM0_XCTxAFE 0xc94 -#define rOFDM0_XDTxIQImbalance 0xc98 -#define rOFDM0_XDTxAFE 0xc9c - -#define rOFDM0_RxIQExtAnta 0xca0 -#define rOFDM0_TxCoeff1 0xca4 -#define rOFDM0_TxCoeff2 0xca8 -#define rOFDM0_TxCoeff3 0xcac -#define rOFDM0_TxCoeff4 0xcb0 -#define rOFDM0_TxCoeff5 0xcb4 -#define rOFDM0_TxCoeff6 0xcb8 -#define rOFDM0_RxHPParameter 0xce0 -#define rOFDM0_TxPseudoNoiseWgt 0xce4 -#define rOFDM0_FrameSync 0xcf0 -#define rOFDM0_DFSReport 0xcf4 - -/* - * 7. PageD(0xD00) - * */ -#define rOFDM1_LSTF 0xd00 -#define rOFDM1_TRxPathEnable 0xd04 - -/* - * 8. PageE(0xE00) - * */ -#define rTxAGC_A_Rate18_06 0xe00 -#define rTxAGC_A_Rate54_24 0xe04 -#define rTxAGC_A_CCK1_Mcs32 0xe08 -#define rTxAGC_A_Mcs03_Mcs00 0xe10 -#define rTxAGC_A_Mcs07_Mcs04 0xe14 -#define rTxAGC_A_Mcs11_Mcs08 0xe18 -#define rTxAGC_A_Mcs15_Mcs12 0xe1c - -#define rTxAGC_B_Rate18_06 0x830 -#define rTxAGC_B_Rate54_24 0x834 -#define rTxAGC_B_CCK1_55_Mcs32 0x838 -#define rTxAGC_B_Mcs03_Mcs00 0x83c -#define rTxAGC_B_Mcs07_Mcs04 0x848 -#define rTxAGC_B_Mcs11_Mcs08 0x84c -#define rTxAGC_B_Mcs15_Mcs12 0x868 -#define rTxAGC_B_CCK11_A_CCK2_11 0x86c - -#define rFPGA0_IQK 0xe28 -#define rTx_IQK_Tone_A 0xe30 -#define rRx_IQK_Tone_A 0xe34 -#define rTx_IQK_PI_A 0xe38 -#define rRx_IQK_PI_A 0xe3c - -#define rTx_IQK 0xe40 -#define rRx_IQK 0xe44 -#define rIQK_AGC_Pts 0xe48 -#define rIQK_AGC_Rsp 0xe4c -#define rTx_IQK_Tone_B 0xe50 -#define rRx_IQK_Tone_B 0xe54 -#define rTx_IQK_PI_B 0xe58 -#define rRx_IQK_PI_B 0xe5c -#define rIQK_AGC_Cont 0xe60 - -#define rBlue_Tooth 0xe6c -#define rRx_Wait_CCA 0xe70 -#define rTx_CCK_RFON 0xe74 -#define rTx_CCK_BBON 0xe78 -#define rTx_OFDM_RFON 0xe7c -#define rTx_OFDM_BBON 0xe80 -#define rTx_To_Rx 0xe84 -#define rTx_To_Tx 0xe88 -#define rRx_CCK 0xe8c - -#define rTx_Power_Before_IQK_A 0xe94 -#define rTx_Power_After_IQK_A 0xe9c - -#define rRx_Power_Before_IQK_A 0xea0 -#define rRx_Power_Before_IQK_A_2 0xea4 -#define rRx_Power_After_IQK_A 0xea8 -#define rRx_Power_After_IQK_A_2 0xeac - -#define rTx_Power_Before_IQK_B 0xeb4 -#define rTx_Power_After_IQK_B 0xebc - -#define rRx_Power_Before_IQK_B 0xec0 -#define rRx_Power_Before_IQK_B_2 0xec4 -#define rRx_Power_After_IQK_B 0xec8 -#define rRx_Power_After_IQK_B_2 0xecc - -#define rRx_OFDM 0xed0 -#define rRx_Wait_RIFS 0xed4 -#define rRx_TO_Rx 0xed8 -#define rStandby 0xedc -#define rSleep 0xee0 -#define rPMPD_ANAEN 0xeec - - -/* 2. Page8(0x800) */ -#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ -#define bJapanMode 0x2 -#define bCCKTxSC 0x30 -#define bCCKEn 0x1000000 -#define bOFDMEn 0x2000000 -#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ -#define bXCTxAGC 0xf000 -#define bXDTxAGC 0xf0000 - -/* 4. PageA(0xA00) */ -#define bCCKBBMode 0x3 /* Useless */ -#define bCCKTxPowerSaving 0x80 -#define bCCKRxPowerSaving 0x40 - -#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ - -#define bCCKScramble 0x8 /* Useless */ -#define bCCKAntDiversity 0x8000 -#define bCCKCarrierRecovery 0x4000 -#define bCCKTxRate 0x3000 -#define bCCKDCCancel 0x0800 -#define bCCKISICancel 0x0400 -#define bCCKMatchFilter 0x0200 -#define bCCKEqualizer 0x0100 -#define bCCKPreambleDetect 0x800000 -#define bCCKFastFalseCCA 0x400000 -#define bCCKChEstStart 0x300000 -#define bCCKCCACount 0x080000 -#define bCCKcs_lim 0x070000 -#define bCCKBistMode 0x80000000 -#define bCCKCCAMask 0x40000000 -#define bCCKTxDACPhase 0x4 -#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ -#define bCCKr_cp_mode0 0x0100 -#define bCCKTxDCOffset 0xf0 -#define bCCKRxDCOffset 0xf -#define bCCKCCAMode 0xc000 -#define bCCKFalseCS_lim 0x3f00 -#define bCCKCS_ratio 0xc00000 -#define bCCKCorgBit_sel 0x300000 -#define bCCKPD_lim 0x0f0000 -#define bCCKNewCCA 0x80000000 -#define bCCKRxHPofIG 0x8000 -#define bCCKRxIG 0x7f00 -#define bCCKLNAPolarity 0x800000 -#define bCCKRx1stGain 0x7f0000 -#define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ -#define bCCKRxAGCSatLevel 0x1f000000 -#define bCCKRxAGCSatCount 0xe0 -#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ -#define bCCKFixedRxAGC 0x8000 -/* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ -#define bCCKAntennaPolarity 0x2000 -#define bCCKTxFilterType 0x0c00 -#define bCCKRxAGCReportType 0x0300 -#define bCCKRxDAGCEn 0x80000000 -#define bCCKRxDAGCPeriod 0x20000000 -#define bCCKRxDAGCSatLevel 0x1f000000 -#define bCCKTimingRecovery 0x800000 -#define bCCKTxC0 0x3f0000 -#define bCCKTxC1 0x3f000000 -#define bCCKTxC2 0x3f -#define bCCKTxC3 0x3f00 -#define bCCKTxC4 0x3f0000 -#define bCCKTxC5 0x3f000000 -#define bCCKTxC6 0x3f -#define bCCKTxC7 0x3f00 -#define bCCKDebugPort 0xff0000 -#define bCCKDACDebug 0x0f000000 -#define bCCKFalseAlarmEnable 0x8000 -#define bCCKFalseAlarmRead 0x4000 -#define bCCKTRSSI 0x7f -#define bCCKRxAGCReport 0xfe -#define bCCKRxReport_AntSel 0x80000000 -#define bCCKRxReport_MFOff 0x40000000 -#define bCCKRxRxReport_SQLoss 0x20000000 -#define bCCKRxReport_Pktloss 0x10000000 -#define bCCKRxReport_Lockedbit 0x08000000 -#define bCCKRxReport_RateError 0x04000000 -#define bCCKRxReport_RxRate 0x03000000 -#define bCCKRxFACounterLower 0xff -#define bCCKRxFACounterUpper 0xff000000 -#define bCCKRxHPAGCStart 0xe000 -#define bCCKRxHPAGCFinal 0x1c00 -#define bCCKRxFalseAlarmEnable 0x8000 -#define bCCKFACounterFreeze 0x4000 -#define bCCKTxPathSel 0x10000000 -#define bCCKDefaultRxPath 0xc000000 -#define bCCKOptionRxPath 0x3000000 - -/* 6. PageE(0xE00) */ -#define bSTBCEn 0x4 /* Useless */ -#define bAntennaMapping 0x10 -#define bNss 0x20 -#define bCFOAntSumD 0x200 -#define bPHYCounterReset 0x8000000 -#define bCFOReportGet 0x4000000 -#define bOFDMContinueTx 0x10000000 -#define bOFDMSingleCarrier 0x20000000 -#define bOFDMSingleTone 0x40000000 - - -/* - * Other Definition - * */ - -#define bEnable 0x1 /* Useless */ -#define bDisable 0x0 - -/* byte endable for srwrite */ -#define bByte0 0x1 /* Useless */ -#define bByte1 0x2 -#define bByte2 0x4 -#define bByte3 0x8 -#define bWord0 0x3 -#define bWord1 0xc -#define bDWord 0xf - -/* for PutRegsetting & GetRegSetting BitMask */ -#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ -#define bMaskByte1 0xff00 -#define bMaskByte2 0xff0000 -#define bMaskByte3 0xff000000 -#define bMaskHWord 0xffff0000 -#define bMaskLWord 0x0000ffff -#define bMaskDWord 0xffffffff -#define bMaskH3Bytes 0xffffff00 -#define bMask12Bits 0xfff -#define bMaskH4Bits 0xf0000000 -#define bMaskOFDM_D 0xffc00000 -#define bMaskCCK 0x3f3f3f3f - - -/*--------------------------Define Parameters-------------------------------*/ - - -#endif diff --git a/include/Hal8812PwrSeq.h b/include/Hal8812PwrSeq.h deleted file mode 100644 index e089c1a..0000000 --- a/include/Hal8812PwrSeq.h +++ /dev/null @@ -1,209 +0,0 @@ - -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL8812PWRSEQ_H__ -#define __HAL8812PWRSEQ_H__ - -#include "HalPwrSeqCmd.h" - -/* - Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf - There are 6 HW Power States: - 0: POFF--Power Off - 1: PDN--Power Down - 2: CARDEMU--Card Emulation - 3: ACT--Active Mode - 4: LPS--Low Power State - 5: SUS--Suspend - - The transision from different states are defined below - TRANS_CARDEMU_TO_ACT - TRANS_ACT_TO_CARDEMU - TRANS_CARDEMU_TO_SUS - TRANS_SUS_TO_CARDEMU - TRANS_CARDEMU_TO_PDN - TRANS_ACT_TO_LPS - TRANS_LPS_TO_ACT - - TRANS_END -*/ -#define RTL8812_TRANS_CARDEMU_TO_ACT_STEPS 15 -#define RTL8812_TRANS_ACT_TO_CARDEMU_STEPS 15 -#define RTL8812_TRANS_CARDEMU_TO_SUS_STEPS 15 -#define RTL8812_TRANS_SUS_TO_CARDEMU_STEPS 15 -#define RTL8812_TRANS_CARDEMU_TO_PDN_STEPS 15 -#define RTL8812_TRANS_PDN_TO_CARDEMU_STEPS 15 -#define RTL8812_TRANS_ACT_TO_LPS_STEPS 15 -#define RTL8812_TRANS_LPS_TO_ACT_STEPS 15 -#define RTL8812_TRANS_END_STEPS 1 - - -#define RTL8812_TRANS_CARDEMU_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ - /*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, disable HWPDN 0x04[15]=0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ - -#define RTL8812_TRANS_ACT_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \ - {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \ - /*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},//0x1F[7:0] = 0 turn off RF*/ \ - /*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},//0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x2A}, /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/ \ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */ \ - /*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0}, // 0x02[1:0] = 0 reset BB */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ - -#define RTL8812_TRANS_CARDEMU_TO_SUS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},\ - {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},\ - {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \ - {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \ - {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \ - {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */ \ - {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'11 enable WL suspend for PCIe*/ - -#define RTL8812_TRANS_SUS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */ \ - {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */ \ - {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \ - {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */ - -#define RTL8812_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - /**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/ \ - /**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x94}, //0x93 = 0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/ \ - {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 8051*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x05}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/ \ - {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},\ - {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},\ - {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \ - {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \ - {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \ - {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \ - {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */ \ - {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/*0x12[0] = 0 force PFM mode */ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \ - {0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x01f[1]=0 , disable RFC_0 control REG_RF_CTRL_8812 */ \ - {0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x076[1]=0 , disable RFC_1 control REG_OPT_CTRL_8812 +2 */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'01 enable WL suspend*/ - -#define RTL8812_TRANS_CARDDIS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*0x12[0] = 1 force PWM mode */ \ - {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */ \ - {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \ - {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/ \ - {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x03[2] = 1, enable 8051*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ - - -#define RTL8812_TRANS_CARDEMU_TO_PDN \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ - -#define RTL8812_TRANS_PDN_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ - -#define RTL8812_TRANS_ACT_TO_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \ - {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \ - {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ - {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ - - -#define RTL8812_TRANS_LPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \ - {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \ - {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/ \ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/ \ - {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/ \ - {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ - -#define RTL8812_TRANS_END \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0}, - - -extern WLAN_PWR_CFG rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8812_card_disable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8812_card_enable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS + RTL8812_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS]; - -#endif /* __HAL8812PWRSEQ_H__ */ diff --git a/include/Hal8814PhyCfg.h b/include/Hal8814PhyCfg.h deleted file mode 100644 index 9aaaf38..0000000 --- a/include/Hal8814PhyCfg.h +++ /dev/null @@ -1,269 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_HAL8814PHYCFG_H__ -#define __INC_HAL8814PHYCFG_H__ - - -/*--------------------------Define Parameters-------------------------------*/ -#define LOOP_LIMIT 5 -#define MAX_STALL_TIME 50 /* us */ -#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */ -#define MAX_TXPWR_IDX_NMODE_92S 63 -#define Reset_Cnt_Limit 3 - - -#ifdef CONFIG_PCI_HCI - #define MAX_AGGR_NUM 0x0B -#else - #define MAX_AGGR_NUM 0x07 -#endif /* CONFIG_PCI_HCI */ - - -/*--------------------------Define Parameters-------------------------------*/ - -/*------------------------------Define structure----------------------------*/ - - -/* BB/RF related */ - -#define SIC_ENABLE 0 - -/*------------------------------Define structure----------------------------*/ - - -/*------------------------Export global variable----------------------------*/ -/*------------------------Export global variable----------------------------*/ - - -/*------------------------Export Marco Definition---------------------------*/ -/*------------------------Export Marco Definition---------------------------*/ - - -/*--------------------------Exported Function prototype---------------------*/ -/* 1. BB register R/W API */ - -extern u32 -PHY_QueryBBReg8814A(IN PADAPTER Adapter, - IN u32 RegAddr, - IN u32 BitMask); - - -VOID -PHY_SetBBReg8814A(IN PADAPTER Adapter, - IN u32 RegAddr, - IN u32 BitMask, - IN u32 Data); - - -extern u32 -PHY_QueryRFReg8814A(IN PADAPTER Adapter, - IN u8 eRFPath, - IN u32 RegAddr, - IN u32 BitMask); - - -void -PHY_SetRFReg8814A(IN PADAPTER Adapter, - IN u8 eRFPath, - IN u32 RegAddr, - IN u32 BitMask, - IN u32 Data); - -/* 1 3. Initial BB/RF config by reading MAC/BB/RF txt. */ -s32 -phy_BB8814A_Config_ParaFile( - IN PADAPTER Adapter -); - -VOID -PHY_ConfigBB_8814A( - IN PADAPTER Adapter -); - - -VOID -phy_ADC_CLK_8814A( - IN PADAPTER Adapter -); - -s32 -PHY_RFConfig8814A( - IN PADAPTER Adapter -); - -/* - * RF Power setting - * - * BOOLEAN PHY_SetRFPowerState8814A(PADAPTER Adapter, rt_rf_power_state eRFPowerState); */ - -/* 1 5. Tx Power setting API */ - -VOID -PHY_GetTxPowerLevel8814( - IN PADAPTER Adapter, - OUT ps4Byte powerlevel -); - -VOID -PHY_SetTxPowerLevel8814( - IN PADAPTER Adapter, - IN u8 Channel -); - -u8 -phy_get_tx_power_index_8814a( - IN PADAPTER Adapter, - IN u8 RFPath, - IN u8 Rate, - IN CHANNEL_WIDTH BandWidth, - IN u8 Channel -); - -u8 -PHY_GetTxPowerIndex8814A( - IN PADAPTER Adapter, - IN u8 RFPath, - IN u8 Rate, - IN u8 BandWidth, - IN u8 Channel, - struct txpwr_idx_comp *tic -); - -VOID -PHY_SetTxPowerIndex_8814A( - IN PADAPTER Adapter, - IN u32 PowerIndex, - IN u8 RFPath, - IN u8 Rate -); - - -BOOLEAN -PHY_UpdateTxPowerDbm8814A( - IN PADAPTER Adapter, - IN s4Byte powerInDbm -); - - -u32 -PHY_GetTxBBSwing_8814A( - IN PADAPTER Adapter, - IN BAND_TYPE Band, - IN u8 RFPath -); - - - -/* 1 6. Channel setting API */ - -VOID -PHY_SwChnlTimerCallback8814A( - IN struct timer_list *p_timer -); - -VOID -PHY_SwChnlWorkItemCallback8814A( - IN PVOID pContext -); - - -VOID -HAL_HandleSwChnl8814A( - IN PADAPTER pAdapter, - IN u8 channel -); - -VOID -PHY_SwChnlSynchronously8814A(IN PADAPTER pAdapter, - IN u8 channel); - -VOID -PHY_SwChnlAndSetBWModeCallback8814A(IN PVOID pContext); - - -VOID -PHY_HandleSwChnlAndSetBW8814A( - IN PADAPTER Adapter, - IN BOOLEAN bSwitchChannel, - IN BOOLEAN bSetBandWidth, - IN u8 ChannelNum, - IN CHANNEL_WIDTH ChnlWidth, - IN u8 ChnlOffsetOf40MHz, - IN u8 ChnlOffsetOf80MHz, - IN u8 CenterFrequencyIndex1 -); - - -BOOLEAN -PHY_QueryRFPathSwitch_8814A(IN PADAPTER pAdapter); - - - -#if (USE_WORKITEM) -VOID -RtCheckForHangWorkItemCallback8814A( - IN PVOID pContext -); -#endif - -BOOLEAN -SetAntennaConfig8814A( - IN PADAPTER Adapter, - IN u8 DefaultAnt -); - -VOID -PHY_SetRFEReg8814A( - IN PADAPTER Adapter, - IN BOOLEAN bInit, - IN u8 Band -); - - -s32 -PHY_SwitchWirelessBand8814A( - IN PADAPTER Adapter, - IN u8 Band -); - -VOID -PHY_SetIO_8814A( - PADAPTER pAdapter -); - -VOID -PHY_SetSwChnlBWMode8814( - IN PADAPTER Adapter, - IN u8 channel, - IN CHANNEL_WIDTH Bandwidth, - IN u8 Offset40, - IN u8 Offset80 -); - -s32 PHY_MACConfig8814(PADAPTER Adapter); -int PHY_BBConfig8814(PADAPTER Adapter); -VOID PHY_Set_SecCCATH_by_RXANT_8814A(PADAPTER pAdapter, u4Byte ulAntennaRx); - - - -/*--------------------------Exported Function prototype---------------------*/ - -/*--------------------------Exported Function prototype---------------------*/ -#endif /* __INC_HAL8192CPHYCFG_H */ diff --git a/include/Hal8814PhyReg.h b/include/Hal8814PhyReg.h deleted file mode 100644 index 0aec994..0000000 --- a/include/Hal8814PhyReg.h +++ /dev/null @@ -1,866 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __INC_HAL8814PHYREG_H__ -#define __INC_HAL8814PHYREG_H__ -/*--------------------------Define Parameters-------------------------------*/ -/* - * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF - * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF - * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 - * 3. RF register 0x00-2E - * 4. Bit Mask for BB/RF register - * 5. Other defintion for BB/RF R/W - * */ - - -/* BB Register Definition */ - -#define rCCAonSec_Jaguar 0x838 -#define rPwed_TH_Jaguar 0x830 -#define rL1_Weight_Jaguar 0x840 -#define r_L1_SBD_start_time 0x844 - -/* BW and sideband setting */ -#define rBWIndication_Jaguar 0x834 -#define rL1PeakTH_Jaguar 0x848 -#define rRFMOD_Jaguar 0x8ac /* RF mode */ -#define rADC_Buf_Clk_Jaguar 0x8c4 -#define rADC_Buf_40_Clk_Jaguar2 0x8c8 -#define rRFECTRL_Jaguar 0x900 -#define bRFMOD_Jaguar 0xc3 -#define rCCK_System_Jaguar 0xa00 /* for cck sideband */ -#define bCCK_System_Jaguar 0x10 - -/* Block & Path enable */ -#define rOFDMCCKEN_Jaguar 0x808 /* OFDM/CCK block enable */ -#define bOFDMEN_Jaguar 0x20000000 -#define bCCKEN_Jaguar 0x10000000 -#define rRxPath_Jaguar 0x808 /* Rx antenna */ -#define bRxPath_Jaguar 0xff -#define rTxPath_Jaguar 0x80c /* Tx antenna */ -#define bTxPath_Jaguar 0x0fffffff -#define rCCK_RX_Jaguar 0xa04 /* for cck rx path selection */ -#define bCCK_RX_Jaguar 0x0c000000 -#define rVhtlen_Use_Lsig_Jaguar 0x8c3 /* Use LSIG for VHT length */ - -#define rRxPath_Jaguar2 0xa04 /* Rx antenna */ -#define rTxAnt_1Nsts_Jaguar2 0x93c /* Tx antenna for 1Nsts */ -#define rTxAnt_23Nsts_Jaguar2 0x940 /* Tx antenna for 2Nsts and 3Nsts */ - - -/* RF read/write-related */ -#define rHSSIRead_Jaguar 0x8b0 /* RF read addr */ -#define bHSSIRead_addr_Jaguar 0xff -#define bHSSIRead_trigger_Jaguar 0x100 -#define rA_PIRead_Jaguar 0xd04 /* RF readback with PI */ -#define rB_PIRead_Jaguar 0xd44 /* RF readback with PI */ -#define rA_SIRead_Jaguar 0xd08 /* RF readback with SI */ -#define rB_SIRead_Jaguar 0xd48 /* RF readback with SI */ -#define rRead_data_Jaguar 0xfffff -#define rA_LSSIWrite_Jaguar 0xc90 /* RF write addr */ -#define rB_LSSIWrite_Jaguar 0xe90 /* RF write addr */ -#define bLSSIWrite_data_Jaguar 0x000fffff -#define bLSSIWrite_addr_Jaguar 0x0ff00000 - -#define rC_PIRead_Jaguar2 0xd84 /* RF readback with PI */ -#define rD_PIRead_Jaguar2 0xdC4 /* RF readback with PI */ -#define rC_SIRead_Jaguar2 0xd88 /* RF readback with SI */ -#define rD_SIRead_Jaguar2 0xdC8 /* RF readback with SI */ -#define rC_LSSIWrite_Jaguar2 0x1890 /* RF write addr */ -#define rD_LSSIWrite_Jaguar2 0x1A90 /* RF write addr */ - - -/* YN: mask the following register definition temporarily */ -#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ -#define rFPGA0_XB_RFInterfaceOE 0x864 - -#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ -#define rFPGA0_XCD_RFInterfaceSW 0x874 - -/* #define rFPGA0_XAB_RFParameter 0x878 */ /* RF Parameter - * #define rFPGA0_XCD_RFParameter 0x87c */ - -/* #define rFPGA0_AnalogParameter1 0x880 */ /* Crystal cap setting RF-R/W protection for parameter4?? - * #define rFPGA0_AnalogParameter2 0x884 - * #define rFPGA0_AnalogParameter3 0x888 - * #define rFPGA0_AdDaClockEn 0x888 */ /* enable ad/da clock1 for dual-phy - * #define rFPGA0_AnalogParameter4 0x88c */ - - -/* CCK TX scaling */ -#define rCCK_TxFilter1_Jaguar 0xa20 -#define bCCK_TxFilter1_C0_Jaguar 0x00ff0000 -#define bCCK_TxFilter1_C1_Jaguar 0xff000000 -#define rCCK_TxFilter2_Jaguar 0xa24 -#define bCCK_TxFilter2_C2_Jaguar 0x000000ff -#define bCCK_TxFilter2_C3_Jaguar 0x0000ff00 -#define bCCK_TxFilter2_C4_Jaguar 0x00ff0000 -#define bCCK_TxFilter2_C5_Jaguar 0xff000000 -#define rCCK_TxFilter3_Jaguar 0xa28 -#define bCCK_TxFilter3_C6_Jaguar 0x000000ff -#define bCCK_TxFilter3_C7_Jaguar 0x0000ff00 -/* NBI & CSI Mask setting */ -#define rCSI_Mask_Setting1_Jaguar 0x874 -#define rCSI_Fix_Mask0_Jaguar 0x880 -#define rCSI_Fix_Mask1_Jaguar 0x884 -#define rCSI_Fix_Mask2_Jaguar 0x888 -#define rCSI_Fix_Mask3_Jaguar 0x88c -#define rCSI_Fix_Mask4_Jaguar 0x890 -#define rCSI_Fix_Mask5_Jaguar 0x894 -#define rCSI_Fix_Mask6_Jaguar 0x898 -#define rCSI_Fix_Mask7_Jaguar 0x89c -#define rNBI_Setting_Jaguar 0x87c - - -/* YN: mask the following register definition temporarily - * #define rPdp_AntA 0xb00 - * #define rPdp_AntA_4 0xb04 - * #define rConfig_Pmpd_AntA 0xb28 - * #define rConfig_AntA 0xb68 - * #define rConfig_AntB 0xb6c - * #define rPdp_AntB 0xb70 - * #define rPdp_AntB_4 0xb74 - * #define rConfig_Pmpd_AntB 0xb98 - * #define rAPK 0xbd8 */ - -/* RXIQC */ -#define rA_RxIQC_AB_Jaguar 0xc10 /* RxIQ imblance matrix coeff. A & B */ -#define rA_RxIQC_CD_Jaguar 0xc14 /* RxIQ imblance matrix coeff. C & D */ -#define rA_TxScale_Jaguar 0xc1c /* Pah_A TX scaling factor */ -#define rB_TxScale_Jaguar 0xe1c /* Path_B TX scaling factor */ -#define rB_RxIQC_AB_Jaguar 0xe10 /* RxIQ imblance matrix coeff. A & B */ -#define rB_RxIQC_CD_Jaguar 0xe14 /* RxIQ imblance matrix coeff. C & D */ -#define b_RxIQC_AC_Jaguar 0x02ff /* bit mask for IQC matrix element A & C */ -#define b_RxIQC_BD_Jaguar 0x02ff0000 /* bit mask for IQC matrix element A & C */ - -#define rC_TxScale_Jaguar2 0x181c /* Pah_C TX scaling factor */ -#define rD_TxScale_Jaguar2 0x1A1c /* Path_D TX scaling factor */ -#define rRF_TxGainOffset 0x55 - -/* DIG-related */ -#define rA_IGI_Jaguar 0xc50 /* Initial Gain for path-A */ -#define rB_IGI_Jaguar 0xe50 /* Initial Gain for path-B */ -#define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C */ -#define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D */ - -#define rOFDM_FalseAlarm1_Jaguar 0xf48 /* counter for break */ -#define rOFDM_FalseAlarm2_Jaguar 0xf4c /* counter for spoofing */ -#define rCCK_FalseAlarm_Jaguar 0xa5c /* counter for cck false alarm */ -#define b_FalseAlarm_Jaguar 0xffff -#define rCCK_CCA_Jaguar 0xa08 /* cca threshold */ -#define bCCK_CCA_Jaguar 0x00ff0000 - -/* Tx Power Ttraining-related */ -#define rA_TxPwrTraing_Jaguar 0xc54 -#define rB_TxPwrTraing_Jaguar 0xe54 - -/* Report-related */ -#define rOFDM_ShortCFOAB_Jaguar 0xf60 -#define rOFDM_LongCFOAB_Jaguar 0xf64 -#define rOFDM_EndCFOAB_Jaguar 0xf70 -#define rOFDM_AGCReport_Jaguar 0xf84 -#define rOFDM_RxSNR_Jaguar 0xf88 -#define rOFDM_RxEVMCSI_Jaguar 0xf8c -#define rOFDM_SIGReport_Jaguar 0xf90 - -/* Misc functions */ -#define rEDCCA_Jaguar 0x8a4 /* EDCCA */ -#define bEDCCA_Jaguar 0xffff -#define rAGC_table_Jaguar 0x82c /* AGC tabel select */ -#define bAGC_table_Jaguar 0x3 -#define b_sel5g_Jaguar 0x1000 /* sel5g */ -#define b_LNA_sw_Jaguar 0x8000 /* HW/WS control for LNA */ -#define rFc_area_Jaguar 0x860 /* fc_area */ -#define bFc_area_Jaguar 0x1ffe000 -#define rSingleTone_ContTx_Jaguar 0x914 - -#define rAGC_table_Jaguar2 0x958 /* AGC tabel select */ -#define rDMA_trigger_Jaguar2 0x95C /* ADC sample mode */ - - -/* RFE */ -#define rA_RFE_Pinmux_Jaguar 0xcb0 /* Path_A RFE cotrol pinmux */ -#define rB_RFE_Pinmux_Jaguar 0xeb0 /* Path_B RFE control pinmux */ -#define rA_RFE_Inv_Jaguar 0xcb4 /* Path_A RFE cotrol */ -#define rB_RFE_Inv_Jaguar 0xeb4 /* Path_B RFE control */ -#define rA_RFE_Jaguar 0xcb8 /* Path_A RFE cotrol */ -#define rB_RFE_Jaguar 0xeb8 /* Path_B RFE control */ -#define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */ -#define bMask_RFEInv_Jaguar 0x3ff00000 -#define bMask_AntselPathFollow_Jaguar 0x00030000 - -#define rC_RFE_Pinmux_Jaguar 0x18B4 /* Path_C RFE cotrol pinmux */ -#define rD_RFE_Pinmux_Jaguar 0x1AB4 /* Path_D RFE cotrol pinmux */ -#define rA_RFE_Sel_Jaguar2 0x1990 - - - -/* TX AGC */ -#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20 -#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24 -#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28 -#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c -#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30 -#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34 -#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38 -#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c -#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40 -#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44 -#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48 -#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c -#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20 -#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24 -#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28 -#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c -#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30 -#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34 -#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38 -#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c -#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40 -#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44 -#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48 -#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c -#define bTxAGC_byte0_Jaguar 0xff -#define bTxAGC_byte1_Jaguar 0xff00 -#define bTxAGC_byte2_Jaguar 0xff0000 -#define bTxAGC_byte3_Jaguar 0xff000000 - - -/* TX AGC */ -#define rTxAGC_A_CCK11_CCK1_Jaguar2 0xc20 -#define rTxAGC_A_Ofdm18_Ofdm6_Jaguar2 0xc24 -#define rTxAGC_A_Ofdm54_Ofdm24_Jaguar2 0xc28 -#define rTxAGC_A_MCS3_MCS0_Jaguar2 0xc2c -#define rTxAGC_A_MCS7_MCS4_Jaguar2 0xc30 -#define rTxAGC_A_MCS11_MCS8_Jaguar2 0xc34 -#define rTxAGC_A_MCS15_MCS12_Jaguar2 0xc38 -#define rTxAGC_A_MCS19_MCS16_Jaguar2 0xcd8 -#define rTxAGC_A_MCS23_MCS20_Jaguar2 0xcdc -#define rTxAGC_A_Nss1Index3_Nss1Index0_Jaguar2 0xc3c -#define rTxAGC_A_Nss1Index7_Nss1Index4_Jaguar2 0xc40 -#define rTxAGC_A_Nss2Index1_Nss1Index8_Jaguar2 0xc44 -#define rTxAGC_A_Nss2Index5_Nss2Index2_Jaguar2 0xc48 -#define rTxAGC_A_Nss2Index9_Nss2Index6_Jaguar2 0xc4c -#define rTxAGC_A_Nss3Index3_Nss3Index0_Jaguar2 0xce0 -#define rTxAGC_A_Nss3Index7_Nss3Index4_Jaguar2 0xce4 -#define rTxAGC_A_Nss3Index9_Nss3Index8_Jaguar2 0xce8 -#define rTxAGC_B_CCK11_CCK1_Jaguar2 0xe20 -#define rTxAGC_B_Ofdm18_Ofdm6_Jaguar2 0xe24 -#define rTxAGC_B_Ofdm54_Ofdm24_Jaguar2 0xe28 -#define rTxAGC_B_MCS3_MCS0_Jaguar2 0xe2c -#define rTxAGC_B_MCS7_MCS4_Jaguar2 0xe30 -#define rTxAGC_B_MCS11_MCS8_Jaguar2 0xe34 -#define rTxAGC_B_MCS15_MCS12_Jaguar2 0xe38 -#define rTxAGC_B_MCS19_MCS16_Jaguar2 0xed8 -#define rTxAGC_B_MCS23_MCS20_Jaguar2 0xedc -#define rTxAGC_B_Nss1Index3_Nss1Index0_Jaguar2 0xe3c -#define rTxAGC_B_Nss1Index7_Nss1Index4_Jaguar2 0xe40 -#define rTxAGC_B_Nss2Index1_Nss1Index8_Jaguar2 0xe44 -#define rTxAGC_B_Nss2Index5_Nss2Index2_Jaguar2 0xe48 -#define rTxAGC_B_Nss2Index9_Nss2Index6_Jaguar2 0xe4c -#define rTxAGC_B_Nss3Index3_Nss3Index0_Jaguar2 0xee0 -#define rTxAGC_B_Nss3Index7_Nss3Index4_Jaguar2 0xee4 -#define rTxAGC_B_Nss3Index9_Nss3Index8_Jaguar2 0xee8 -#define rTxAGC_C_CCK11_CCK1_Jaguar2 0x1820 -#define rTxAGC_C_Ofdm18_Ofdm6_Jaguar2 0x1824 -#define rTxAGC_C_Ofdm54_Ofdm24_Jaguar2 0x1828 -#define rTxAGC_C_MCS3_MCS0_Jaguar2 0x182c -#define rTxAGC_C_MCS7_MCS4_Jaguar2 0x1830 -#define rTxAGC_C_MCS11_MCS8_Jaguar2 0x1834 -#define rTxAGC_C_MCS15_MCS12_Jaguar2 0x1838 -#define rTxAGC_C_MCS19_MCS16_Jaguar2 0x18d8 -#define rTxAGC_C_MCS23_MCS20_Jaguar2 0x18dc -#define rTxAGC_C_Nss1Index3_Nss1Index0_Jaguar2 0x183c -#define rTxAGC_C_Nss1Index7_Nss1Index4_Jaguar2 0x1840 -#define rTxAGC_C_Nss2Index1_Nss1Index8_Jaguar2 0x1844 -#define rTxAGC_C_Nss2Index5_Nss2Index2_Jaguar2 0x1848 -#define rTxAGC_C_Nss2Index9_Nss2Index6_Jaguar2 0x184c -#define rTxAGC_C_Nss3Index3_Nss3Index0_Jaguar2 0x18e0 -#define rTxAGC_C_Nss3Index7_Nss3Index4_Jaguar2 0x18e4 -#define rTxAGC_C_Nss3Index9_Nss3Index8_Jaguar2 0x18e8 -#define rTxAGC_D_CCK11_CCK1_Jaguar2 0x1a20 -#define rTxAGC_D_Ofdm18_Ofdm6_Jaguar2 0x1a24 -#define rTxAGC_D_Ofdm54_Ofdm24_Jaguar2 0x1a28 -#define rTxAGC_D_MCS3_MCS0_Jaguar2 0x1a2c -#define rTxAGC_D_MCS7_MCS4_Jaguar2 0x1a30 -#define rTxAGC_D_MCS11_MCS8_Jaguar2 0x1a34 -#define rTxAGC_D_MCS15_MCS12_Jaguar2 0x1a38 -#define rTxAGC_D_MCS19_MCS16_Jaguar2 0x1ad8 -#define rTxAGC_D_MCS23_MCS20_Jaguar2 0x1adc -#define rTxAGC_D_Nss1Index3_Nss1Index0_Jaguar2 0x1a3c -#define rTxAGC_D_Nss1Index7_Nss1Index4_Jaguar2 0x1a40 -#define rTxAGC_D_Nss2Index1_Nss1Index8_Jaguar2 0x1a44 -#define rTxAGC_D_Nss2Index5_Nss2Index2_Jaguar2 0x1a48 -#define rTxAGC_D_Nss2Index9_Nss2Index6_Jaguar2 0x1a4c -#define rTxAGC_D_Nss3Index3_Nss3Index0_Jaguar2 0x1ae0 -#define rTxAGC_D_Nss3Index7_Nss3Index4_Jaguar2 0x1ae4 -#define rTxAGC_D_Nss3Index9_Nss3Index8_Jaguar2 0x1ae8 -/* IQK YN: temporaily mask this part - * #define rFPGA0_IQK 0xe28 - * #define rTx_IQK_Tone_A 0xe30 - * #define rRx_IQK_Tone_A 0xe34 - * #define rTx_IQK_PI_A 0xe38 - * #define rRx_IQK_PI_A 0xe3c */ - -/* #define rTx_IQK 0xe40 */ -/* #define rRx_IQK 0xe44 */ -/* #define rIQK_AGC_Pts 0xe48 */ -/* #define rIQK_AGC_Rsp 0xe4c */ -/* #define rTx_IQK_Tone_B 0xe50 */ -/* #define rRx_IQK_Tone_B 0xe54 */ -/* #define rTx_IQK_PI_B 0xe58 */ -/* #define rRx_IQK_PI_B 0xe5c */ -/* #define rIQK_AGC_Cont 0xe60 */ - - -/* AFE-related */ -#define rA_AFEPwr1_Jaguar 0xc60 /* dynamic AFE power control */ -#define rA_AFEPwr2_Jaguar 0xc64 /* dynamic AFE power control */ -#define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xc68 -#define rA_Tx_CCKBBON_OFDMRFON_Jaguar 0xc6c -#define rA_Tx_OFDMBBON_Tx2Rx_Jaguar 0xc70 -#define rA_Tx2Tx_RXCCK_Jaguar 0xc74 -#define rA_Rx_OFDM_WaitRIFS_Jaguar 0xc78 -#define rA_Rx2Rx_BT_Jaguar 0xc7c -#define rA_sleep_nav_Jaguar 0xc80 -#define rA_pmpd_Jaguar 0xc84 -#define rB_AFEPwr1_Jaguar 0xe60 /* dynamic AFE power control */ -#define rB_AFEPwr2_Jaguar 0xe64 /* dynamic AFE power control */ -#define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xe68 -#define rB_Tx_CCKBBON_OFDMRFON_Jaguar 0xe6c -#define rB_Tx_OFDMBBON_Tx2Rx_Jaguar 0xe70 -#define rB_Tx2Tx_RXCCK_Jaguar 0xe74 -#define rB_Rx_OFDM_WaitRIFS_Jaguar 0xe78 -#define rB_Rx2Rx_BT_Jaguar 0xe7c -#define rB_sleep_nav_Jaguar 0xe80 -#define rB_pmpd_Jaguar 0xe84 - - -/* YN: mask these registers temporaily - * #define rTx_Power_Before_IQK_A 0xe94 - * #define rTx_Power_After_IQK_A 0xe9c */ - -/* #define rRx_Power_Before_IQK_A 0xea0 */ -/* #define rRx_Power_Before_IQK_A_2 0xea4 */ -/* #define rRx_Power_After_IQK_A 0xea8 */ -/* #define rRx_Power_After_IQK_A_2 0xeac */ - -/* #define rTx_Power_Before_IQK_B 0xeb4 */ -/* #define rTx_Power_After_IQK_B 0xebc */ - -/* #define rRx_Power_Before_IQK_B 0xec0 */ -/* #define rRx_Power_Before_IQK_B_2 0xec4 */ -/* #define rRx_Power_After_IQK_B 0xec8 */ -/* #define rRx_Power_After_IQK_B_2 0xecc */ - - -/* RSSI Dump */ -#define rA_RSSIDump_Jaguar 0xBF0 -#define rB_RSSIDump_Jaguar 0xBF1 -#define rS1_RXevmDump_Jaguar 0xBF4 -#define rS2_RXevmDump_Jaguar 0xBF5 -#define rA_RXsnrDump_Jaguar 0xBF6 -#define rB_RXsnrDump_Jaguar 0xBF7 -#define rA_CfoShortDump_Jaguar 0xBF8 -#define rB_CfoShortDump_Jaguar 0xBFA -#define rA_CfoLongDump_Jaguar 0xBEC -#define rB_CfoLongDump_Jaguar 0xBEE - - -/* RF Register - * */ -#define RF_AC_Jaguar 0x00 /* */ -#define RF_RF_Top_Jaguar 0x07 /* */ -#define RF_TXLOK_Jaguar 0x08 /* */ -#define RF_TXAPK_Jaguar 0x0B -#define RF_CHNLBW_Jaguar 0x18 /* RF channel and BW switch */ -#define RF_RCK1_Jaguar 0x1c /* */ -#define RF_RCK2_Jaguar 0x1d -#define RF_RCK3_Jaguar 0x1e -#define RF_ModeTableAddr 0x30 -#define RF_ModeTableData0 0x31 -#define RF_ModeTableData1 0x32 -#define RF_TxLCTank_Jaguar 0x54 -#define RF_APK_Jaguar 0x63 -#define RF_LCK 0xB4 -#define RF_WeLut_Jaguar 0xEF - -#define bRF_CHNLBW_MOD_AG_Jaguar 0x70300 -#define bRF_CHNLBW_BW 0xc00 - - -/* - * RL6052 Register definition - * */ -#define RF_AC 0x00 /* */ -#define RF_IPA_A 0x0C /* */ -#define RF_TXBIAS_A 0x0D -#define RF_BS_PA_APSET_G9_G11 0x0E -#define RF_MODE1 0x10 /* */ -#define RF_MODE2 0x11 /* */ -#define RF_CHNLBW 0x18 /* RF channel and BW switch */ -#define RF_RCK_OS 0x30 /* RF TX PA control */ -#define RF_TXPA_G1 0x31 /* RF TX PA control */ -#define RF_TXPA_G2 0x32 /* RF TX PA control */ -#define RF_TXPA_G3 0x33 /* RF TX PA control */ -#define RF_0x52 0x52 -#define RF_WE_LUT 0xEF - -/* - * Bit Mask - * - * 1. Page1(0x100) */ -#define bBBResetB 0x100 /* Useless now? */ -#define bGlobalResetB 0x200 -#define bOFDMTxStart 0x4 -#define bCCKTxStart 0x8 -#define bCRC32Debug 0x100 -#define bPMACLoopback 0x10 -#define bTxLSIG 0xffffff -#define bOFDMTxRate 0xf -#define bOFDMTxReserved 0x10 -#define bOFDMTxLength 0x1ffe0 -#define bOFDMTxParity 0x20000 -#define bTxHTSIG1 0xffffff -#define bTxHTMCSRate 0x7f -#define bTxHTBW 0x80 -#define bTxHTLength 0xffff00 -#define bTxHTSIG2 0xffffff -#define bTxHTSmoothing 0x1 -#define bTxHTSounding 0x2 -#define bTxHTReserved 0x4 -#define bTxHTAggreation 0x8 -#define bTxHTSTBC 0x30 -#define bTxHTAdvanceCoding 0x40 -#define bTxHTShortGI 0x80 -#define bTxHTNumberHT_LTF 0x300 -#define bTxHTCRC8 0x3fc00 -#define bCounterReset 0x10000 -#define bNumOfOFDMTx 0xffff -#define bNumOfCCKTx 0xffff0000 -#define bTxIdleInterval 0xffff -#define bOFDMService 0xffff0000 -#define bTxMACHeader 0xffffffff -#define bTxDataInit 0xff -#define bTxHTMode 0x100 -#define bTxDataType 0x30000 -#define bTxRandomSeed 0xffffffff -#define bCCKTxPreamble 0x1 -#define bCCKTxSFD 0xffff0000 -#define bCCKTxSIG 0xff -#define bCCKTxService 0xff00 -#define bCCKLengthExt 0x8000 -#define bCCKTxLength 0xffff0000 -#define bCCKTxCRC16 0xffff -#define bCCKTxStatus 0x1 -#define bOFDMTxStatus 0x2 - - -/* - * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF - * 1. Page1(0x100) - * */ -#define rPMAC_Reset 0x100 -#define rPMAC_TxStart 0x104 -#define rPMAC_TxLegacySIG 0x108 -#define rPMAC_TxHTSIG1 0x10c -#define rPMAC_TxHTSIG2 0x110 -#define rPMAC_PHYDebug 0x114 -#define rPMAC_TxPacketNum 0x118 -#define rPMAC_TxIdle 0x11c -#define rPMAC_TxMACHeader0 0x120 -#define rPMAC_TxMACHeader1 0x124 -#define rPMAC_TxMACHeader2 0x128 -#define rPMAC_TxMACHeader3 0x12c -#define rPMAC_TxMACHeader4 0x130 -#define rPMAC_TxMACHeader5 0x134 -#define rPMAC_TxDataType 0x138 -#define rPMAC_TxRandomSeed 0x13c -#define rPMAC_CCKPLCPPreamble 0x140 -#define rPMAC_CCKPLCPHeader 0x144 -#define rPMAC_CCKCRC16 0x148 -#define rPMAC_OFDMRxCRC32OK 0x170 -#define rPMAC_OFDMRxCRC32Er 0x174 -#define rPMAC_OFDMRxParityEr 0x178 -#define rPMAC_OFDMRxCRC8Er 0x17c -#define rPMAC_CCKCRxRC16Er 0x180 -#define rPMAC_CCKCRxRC32Er 0x184 -#define rPMAC_CCKCRxRC32OK 0x188 -#define rPMAC_TxStatus 0x18c - -/* - * 3. Page8(0x800) - * */ -#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */ - -#define rFPGA0_TxInfo 0x804 /* Status report?? */ -#define rFPGA0_PSDFunction 0x808 -#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ - -#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ -#define rFPGA0_XA_HSSIParameter2 0x824 -#define rFPGA0_XB_HSSIParameter1 0x828 -#define rFPGA0_XB_HSSIParameter2 0x82c - -#define rFPGA0_XA_LSSIParameter 0x840 -#define rFPGA0_XB_LSSIParameter 0x844 - -#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ -#define rFPGA0_XCD_SwitchControl 0x85c - -#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ -#define rFPGA0_XCD_RFParameter 0x87c - -#define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ -#define rFPGA0_AnalogParameter2 0x884 -#define rFPGA0_AnalogParameter3 0x888 -#define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */ -#define rFPGA0_AnalogParameter4 0x88c - -#define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ -#define rFPGA0_XB_LSSIReadBack 0x8a4 -#define rFPGA0_XC_LSSIReadBack 0x8a8 -#define rFPGA0_XD_LSSIReadBack 0x8ac - -#define rFPGA0_XCD_RFPara 0x8b4 -#define rFPGA0_PSDReport 0x8b4 /* Useless now */ -#define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ -#define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ -#define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ /* RF Interface Readback Value */ -#define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ - -/* - * 4. Page9(0x900) - * */ -#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */ -#define REG_BB_TX_PATH_SEL_1_8814A 0x93c -#define REG_BB_TX_PATH_SEL_2_8814A 0x940 -#define rFPGA1_TxBlock 0x904 /* Useless now */ -#define rFPGA1_DebugSelect 0x908 /* Useless now */ -#define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */ -/*Page 19 for TxBF*/ -#define REG_BB_TXBF_ANT_SET_BF1_8814A 0x19ac -#define REG_BB_TXBF_ANT_SET_BF0_8814A 0x19b4 -/* - * PageA(0xA00) - * */ -#define rCCK0_System 0xa00 -#define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */ -#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ -#define rCCK0_TxFilter1 0xa20 -#define rCCK0_TxFilter2 0xa24 -#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ -#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ - -/* - * PageB(0xB00) - * */ -#define rPdp_AntA 0xb00 -#define rPdp_AntA_4 0xb04 -#define rConfig_Pmpd_AntA 0xb28 -#define rConfig_AntA 0xb68 -#define rConfig_AntB 0xb6c -#define rPdp_AntB 0xb70 -#define rPdp_AntB_4 0xb74 -#define rConfig_Pmpd_AntB 0xb98 -#define rAPK 0xbd8 - -/* - * 6. PageC(0xC00) - * */ -#define rOFDM0_LSTF 0xc00 - -#define rOFDM0_TRxPathEnable 0xc04 -#define rOFDM0_TRMuxPar 0xc08 -#define rOFDM0_TRSWIsolation 0xc0c - -#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ -#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ -#define rOFDM0_XBRxAFE 0xc18 -#define rOFDM0_XBRxIQImbalance 0xc1c -#define rOFDM0_XCRxAFE 0xc20 -#define rOFDM0_XCRxIQImbalance 0xc24 -#define rOFDM0_XDRxAFE 0xc28 -#define rOFDM0_XDRxIQImbalance 0xc2c - -#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */ -#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ -#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ -#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ - -#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ -#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ -#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ -#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ - -#define rOFDM0_XAAGCCore1 0xc50 /* DIG */ -#define rOFDM0_XAAGCCore2 0xc54 -#define rOFDM0_XBAGCCore1 0xc58 -#define rOFDM0_XBAGCCore2 0xc5c -#define rOFDM0_XCAGCCore1 0xc60 -#define rOFDM0_XCAGCCore2 0xc64 -#define rOFDM0_XDAGCCore1 0xc68 -#define rOFDM0_XDAGCCore2 0xc6c - -#define rOFDM0_AGCParameter1 0xc70 -#define rOFDM0_AGCParameter2 0xc74 -#define rOFDM0_AGCRSSITable 0xc78 -#define rOFDM0_HTSTFAGC 0xc7c - -#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ -#define rOFDM0_XATxAFE 0xc84 -#define rOFDM0_XBTxIQImbalance 0xc88 -#define rOFDM0_XBTxAFE 0xc8c -#define rOFDM0_XCTxIQImbalance 0xc90 -#define rOFDM0_XCTxAFE 0xc94 -#define rOFDM0_XDTxIQImbalance 0xc98 -#define rOFDM0_XDTxAFE 0xc9c - -#define rOFDM0_RxIQExtAnta 0xca0 -#define rOFDM0_TxCoeff1 0xca4 -#define rOFDM0_TxCoeff2 0xca8 -#define rOFDM0_TxCoeff3 0xcac -#define rOFDM0_TxCoeff4 0xcb0 -#define rOFDM0_TxCoeff5 0xcb4 -#define rOFDM0_TxCoeff6 0xcb8 -#define rOFDM0_RxHPParameter 0xce0 -#define rOFDM0_TxPseudoNoiseWgt 0xce4 -#define rOFDM0_FrameSync 0xcf0 -#define rOFDM0_DFSReport 0xcf4 - -/* - * 7. PageD(0xD00) - * */ -#define rOFDM1_LSTF 0xd00 -#define rOFDM1_TRxPathEnable 0xd04 - -/* - * 8. PageE(0xE00) - * */ -#define rTxAGC_A_Rate18_06 0xe00 -#define rTxAGC_A_Rate54_24 0xe04 -#define rTxAGC_A_CCK1_Mcs32 0xe08 -#define rTxAGC_A_Mcs03_Mcs00 0xe10 -#define rTxAGC_A_Mcs07_Mcs04 0xe14 -#define rTxAGC_A_Mcs11_Mcs08 0xe18 -#define rTxAGC_A_Mcs15_Mcs12 0xe1c - -#define rTxAGC_B_Rate18_06 0x830 -#define rTxAGC_B_Rate54_24 0x834 -#define rTxAGC_B_CCK1_55_Mcs32 0x838 -#define rTxAGC_B_Mcs03_Mcs00 0x83c -#define rTxAGC_B_Mcs07_Mcs04 0x848 -#define rTxAGC_B_Mcs11_Mcs08 0x84c -#define rTxAGC_B_Mcs15_Mcs12 0x868 -#define rTxAGC_B_CCK11_A_CCK2_11 0x86c - -#define rFPGA0_IQK 0xe28 -#define rTx_IQK_Tone_A 0xe30 -#define rRx_IQK_Tone_A 0xe34 -#define rTx_IQK_PI_A 0xe38 -#define rRx_IQK_PI_A 0xe3c - -#define rTx_IQK 0xe40 -#define rRx_IQK 0xe44 -#define rIQK_AGC_Pts 0xe48 -#define rIQK_AGC_Rsp 0xe4c -#define rTx_IQK_Tone_B 0xe50 -#define rRx_IQK_Tone_B 0xe54 -#define rTx_IQK_PI_B 0xe58 -#define rRx_IQK_PI_B 0xe5c -#define rIQK_AGC_Cont 0xe60 - -#define rBlue_Tooth 0xe6c -#define rRx_Wait_CCA 0xe70 -#define rTx_CCK_RFON 0xe74 -#define rTx_CCK_BBON 0xe78 -#define rTx_OFDM_RFON 0xe7c -#define rTx_OFDM_BBON 0xe80 -#define rTx_To_Rx 0xe84 -#define rTx_To_Tx 0xe88 -#define rRx_CCK 0xe8c - -#define rTx_Power_Before_IQK_A 0xe94 -#define rTx_Power_After_IQK_A 0xe9c - -#define rRx_Power_Before_IQK_A 0xea0 -#define rRx_Power_Before_IQK_A_2 0xea4 -#define rRx_Power_After_IQK_A 0xea8 -#define rRx_Power_After_IQK_A_2 0xeac - -#define rTx_Power_Before_IQK_B 0xeb4 -#define rTx_Power_After_IQK_B 0xebc - -#define rRx_Power_Before_IQK_B 0xec0 -#define rRx_Power_Before_IQK_B_2 0xec4 -#define rRx_Power_After_IQK_B 0xec8 -#define rRx_Power_After_IQK_B_2 0xecc - -#define rRx_OFDM 0xed0 -#define rRx_Wait_RIFS 0xed4 -#define rRx_TO_Rx 0xed8 -#define rStandby 0xedc -#define rSleep 0xee0 -#define rPMPD_ANAEN 0xeec - - -/* 2. Page8(0x800) */ -#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ -#define bJapanMode 0x2 -#define bCCKTxSC 0x30 -#define bCCKEn 0x1000000 -#define bOFDMEn 0x2000000 -#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ -#define bXCTxAGC 0xf000 -#define bXDTxAGC 0xf0000 - -/* 4. PageA(0xA00) */ -#define bCCKBBMode 0x3 /* Useless */ -#define bCCKTxPowerSaving 0x80 -#define bCCKRxPowerSaving 0x40 - -#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ - -#define bCCKScramble 0x8 /* Useless */ -#define bCCKAntDiversity 0x8000 -#define bCCKCarrierRecovery 0x4000 -#define bCCKTxRate 0x3000 -#define bCCKDCCancel 0x0800 -#define bCCKISICancel 0x0400 -#define bCCKMatchFilter 0x0200 -#define bCCKEqualizer 0x0100 -#define bCCKPreambleDetect 0x800000 -#define bCCKFastFalseCCA 0x400000 -#define bCCKChEstStart 0x300000 -#define bCCKCCACount 0x080000 -#define bCCKcs_lim 0x070000 -#define bCCKBistMode 0x80000000 -#define bCCKCCAMask 0x40000000 -#define bCCKTxDACPhase 0x4 -#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ -#define bCCKr_cp_mode0 0x0100 -#define bCCKTxDCOffset 0xf0 -#define bCCKRxDCOffset 0xf -#define bCCKCCAMode 0xc000 -#define bCCKFalseCS_lim 0x3f00 -#define bCCKCS_ratio 0xc00000 -#define bCCKCorgBit_sel 0x300000 -#define bCCKPD_lim 0x0f0000 -#define bCCKNewCCA 0x80000000 -#define bCCKRxHPofIG 0x8000 -#define bCCKRxIG 0x7f00 -#define bCCKLNAPolarity 0x800000 -#define bCCKRx1stGain 0x7f0000 -#define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ -#define bCCKRxAGCSatLevel 0x1f000000 -#define bCCKRxAGCSatCount 0xe0 -#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ -#define bCCKFixedRxAGC 0x8000 -/* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ -#define bCCKAntennaPolarity 0x2000 -#define bCCKTxFilterType 0x0c00 -#define bCCKRxAGCReportType 0x0300 -#define bCCKRxDAGCEn 0x80000000 -#define bCCKRxDAGCPeriod 0x20000000 -#define bCCKRxDAGCSatLevel 0x1f000000 -#define bCCKTimingRecovery 0x800000 -#define bCCKTxC0 0x3f0000 -#define bCCKTxC1 0x3f000000 -#define bCCKTxC2 0x3f -#define bCCKTxC3 0x3f00 -#define bCCKTxC4 0x3f0000 -#define bCCKTxC5 0x3f000000 -#define bCCKTxC6 0x3f -#define bCCKTxC7 0x3f00 -#define bCCKDebugPort 0xff0000 -#define bCCKDACDebug 0x0f000000 -#define bCCKFalseAlarmEnable 0x8000 -#define bCCKFalseAlarmRead 0x4000 -#define bCCKTRSSI 0x7f -#define bCCKRxAGCReport 0xfe -#define bCCKRxReport_AntSel 0x80000000 -#define bCCKRxReport_MFOff 0x40000000 -#define bCCKRxRxReport_SQLoss 0x20000000 -#define bCCKRxReport_Pktloss 0x10000000 -#define bCCKRxReport_Lockedbit 0x08000000 -#define bCCKRxReport_RateError 0x04000000 -#define bCCKRxReport_RxRate 0x03000000 -#define bCCKRxFACounterLower 0xff -#define bCCKRxFACounterUpper 0xff000000 -#define bCCKRxHPAGCStart 0xe000 -#define bCCKRxHPAGCFinal 0x1c00 -#define bCCKRxFalseAlarmEnable 0x8000 -#define bCCKFACounterFreeze 0x4000 -#define bCCKTxPathSel 0x10000000 -#define bCCKDefaultRxPath 0xc000000 -#define bCCKOptionRxPath 0x3000000 - -#define RF_T_METER_88E 0x42 - -/* 6. PageE(0xE00) */ -#define bSTBCEn 0x4 /* Useless */ -#define bAntennaMapping 0x10 -#define bNss 0x20 -#define bCFOAntSumD 0x200 -#define bPHYCounterReset 0x8000000 -#define bCFOReportGet 0x4000000 -#define bOFDMContinueTx 0x10000000 -#define bOFDMSingleCarrier 0x20000000 -#define bOFDMSingleTone 0x40000000 - - -/* - * Other Definition - * */ - -#define bEnable 0x1 /* Useless */ -#define bDisable 0x0 - -/* byte endable for srwrite */ -#define bByte0 0x1 /* Useless */ -#define bByte1 0x2 -#define bByte2 0x4 -#define bByte3 0x8 -#define bWord0 0x3 -#define bWord1 0xc -#define bDWord 0xf - -/* for PutRegsetting & GetRegSetting BitMask */ -#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ -#define bMaskByte1 0xff00 -#define bMaskByte2 0xff0000 -#define bMaskByte3 0xff000000 -#define bMaskHWord 0xffff0000 -#define bMaskLWord 0x0000ffff -#define bMaskDWord 0xffffffff -#define bMaskH3Bytes 0xffffff00 -#define bMask12Bits 0xfff -#define bMaskH4Bits 0xf0000000 -#define bMaskOFDM_D 0xffc00000 -#define bMaskCCK 0x3f3f3f3f -#define bMask7bits 0x7f -#define bMaskByte2HighNibble 0x00f00000 -#define bMaskByte3LowNibble 0x0f000000 -#define bMaskL3Bytes 0x00ffffff - -/*--------------------------Define Parameters-------------------------------*/ - - -#endif diff --git a/include/Hal8814PwrSeq.h b/include/Hal8814PwrSeq.h deleted file mode 100644 index 696959b..0000000 --- a/include/Hal8814PwrSeq.h +++ /dev/null @@ -1,236 +0,0 @@ - -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __HAL8814PWRSEQ_H__ -#define __HAL8814PWRSEQ_H__ - -#include "HalPwrSeqCmd.h" - -/* - Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf - There are 6 HW Power States: - 0: POFF--Power Off - 1: PDN--Power Down - 2: CARDEMU--Card Emulation - 3: ACT--Active Mode - 4: LPS--Low Power State - 5: SUS--Suspend - - The transision from different states are defined below - TRANS_CARDEMU_TO_ACT - TRANS_ACT_TO_CARDEMU - TRANS_CARDEMU_TO_SUS - TRANS_SUS_TO_CARDEMU - TRANS_CARDEMU_TO_PDN - TRANS_ACT_TO_LPS - TRANS_LPS_TO_ACT - - TRANS_END -*/ -#define RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS 16 -#define RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS 20 -#define RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS 17 -#define RTL8814A_TRANS_SUS_TO_CARDEMU_STEPS 15 -#define RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS 17 -#define RTL8814A_TRANS_PDN_TO_CARDEMU_STEPS 16 -#define RTL8814A_TRANS_ACT_TO_LPS_STEPS 20 -#define RTL8814A_TRANS_LPS_TO_ACT_STEPS 15 -#define RTL8814A_TRANS_END_STEPS 1 - - -#define RTL8814A_TRANS_CARDEMU_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ - {0x002B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /* ??0x28[24]=1, enable pll phase select*/ \ - {0x0015, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT3 | BIT2 | BIT1), (BIT3 | BIT2 | BIT1)},/* 0x14[11:9]=3'b111, OCP current threshold = 1.5A */ \ - {0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0E, 0x08},/* 0x2C[11:9]=3'b100, select lpf R3 */ \ - {0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x70, 0x50},/* 0x2C[14:12]=3'b101, select lpf Rs*/ \ - {0x007B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x78[30]=1'b1, SDM order select*/ \ - /*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, */ /* disable HWPDN 0x04[15]=0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/ \ - {0x00F0, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* */ \ - {0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x30, 0x20},/* */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ - -#define RTL8814A_TRANS_ACT_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \ - {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \ - {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \ - {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \ - {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \ - {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \ - {0x0002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \ - {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \ - {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*0x1F[7:0] = 0 turn off RF*/ \ - /*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},*/ /*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x28}, /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/ \ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0}, /*0x8[1] = 0 ANA clk = 500k */ \ - /*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0},*/ /* 0x02[1:0] = 0 reset BB */ \ - {0x0066, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, /*0x66[7]=0, disable ckreq for gpio7 output SUS */ \ - {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x41[4]=0, disable sic for gpio7 output SUS */ \ - {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x42[1]=0, disable ckout for gpio7 output SUS */ \ - {0x004e, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x4E[5]=1, disable LED2 for gpio7 output SUS */ \ - {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x41[0]=0, disable uart for gpio7 output SUS */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ - -#define RTL8814A_TRANS_CARDEMU_TO_SUS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x0c},\ - {0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x0E},\ - {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \ - {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \ - {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \ - {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*0x14[13] = 1 turn on ZCD */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x14[14] =1 trun on ZCD */ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk = 500k */ \ - {0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps, ldo sleep mode */ \ - {0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend */ - -#define RTL8814A_TRANS_SUS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0 enable WL suspend*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* 0x14[14] =0 trun off ZCD */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0},/*0x14[13] = 0 turn off ZCD */ \ - {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \ - {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */ - -#define RTL8814A_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - /**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/ \ - /**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x94}, //0x93 = 0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/ \ - {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 3081*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x01}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/ \ - {0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x30}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/ \ - /*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},*/ \ - /*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},*/ \ - /*{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},*/ /* gpio11 input mode, gpio10~8 output mode */ \ - {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \ - {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \ - {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x15[6] =1 trun on ZCD output */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*0x15[5] = 1 turn on ZCD */ \ - {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/*0x12[6] = 0 force PFM mode */ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk = 500k */ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \ - {0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x01f[1]=0 , disable RFC_0 control REG_RF_CTRL_8814A */ \ - {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x020[1]=0 , disable RFC_1 control REG_RF_CTRL_8814A */ \ - {0x0021, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x021[1]=0 , disable RFC_2 control REG_RF_CTRL_8814A */ \ - {0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x076[1]=0 , disable RFC_3 control REG_OPT_CTRL_8814A +2 */ \ - {0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps, ldo sleep mode */ \ - {0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend*/ - -#define RTL8814A_TRANS_CARDDIS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*0x12[6] = 1 force PWM mode */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0},/*0x15[5] = 0 turn off ZCD */ \ - {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* 0x15[6] =0 trun off ZCD output */ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */ \ - {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \ - {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, /* gpio11 input mode, gpio10~8 input mode */ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0, enable WL suspend*/ \ - /*{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},*/ /*0x03[2] = 1, enable 3081*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ \ - {0x0071, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*0x70[10] = 0, CPHY_MBIAS_EN disable*/ - - -#define RTL8814A_TRANS_CARDEMU_TO_PDN \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ - -#define RTL8814A_TRANS_PDN_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ - -#define RTL8814A_TRANS_ACT_TO_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \ - {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \ - {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \ - {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/ \ - {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \ - {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/ \ - {0x0002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ - {0x05F1, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Respond TxOK to scheduler*/ - - -#define RTL8814A_TRANS_LPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \ - {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \ - {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /* Delay*/ \ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/ \ - {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /* Polling 0x109[7]=0 TSF in 40M*/ \ - /*{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, */ /*. ??0x29[7:6] = 2b'00 enable BB clock*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \ - {0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \ - {0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x1002[1:0] = 2b'11 enable BB macro*/ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ - -#define RTL8814A_TRANS_END \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0}, - - -extern WLAN_PWR_CFG rtl8814A_power_on_flow[RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8814A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8814A_radio_off_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8814A_card_disable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8814A_card_enable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8814A_suspend_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8814A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8814A_resume_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8814A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8814A_hwpdn_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8814A_enter_lps_flow[RTL8814A_TRANS_ACT_TO_LPS_STEPS + RTL8814A_TRANS_END_STEPS]; -extern WLAN_PWR_CFG rtl8814A_leave_lps_flow[RTL8814A_TRANS_LPS_TO_ACT_STEPS + RTL8814A_TRANS_END_STEPS]; - -#endif /* __HAL8814PWRSEQ_H__ */ diff --git a/include/Hal8821APwrSeq.h b/include/Hal8821APwrSeq.h deleted file mode 100644 index 393068b..0000000 --- a/include/Hal8821APwrSeq.h +++ /dev/null @@ -1,186 +0,0 @@ -#ifndef REALTEK_POWER_SEQUENCE_8821 -#define REALTEK_POWER_SEQUENCE_8821 - -#include "HalPwrSeqCmd.h" - -/* - Check document WM-20130516-JackieLau-RTL8821A_Power_Architecture-R10.vsd - There are 6 HW Power States: - 0: POFF--Power Off - 1: PDN--Power Down - 2: CARDEMU--Card Emulation - 3: ACT--Active Mode - 4: LPS--Low Power State - 5: SUS--Suspend - - The transision from different states are defined below - TRANS_CARDEMU_TO_ACT - TRANS_ACT_TO_CARDEMU - TRANS_CARDEMU_TO_SUS - TRANS_SUS_TO_CARDEMU - TRANS_CARDEMU_TO_PDN - TRANS_ACT_TO_LPS - TRANS_LPS_TO_ACT - - TRANS_END -*/ -#define RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS 25 -#define RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS 15 -#define RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS 15 -#define RTL8821A_TRANS_SUS_TO_CARDEMU_STEPS 15 -#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS 15 -#define RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS 15 -#define RTL8821A_TRANS_PDN_TO_CARDEMU_STEPS 15 -#define RTL8821A_TRANS_ACT_TO_LPS_STEPS 15 -#define RTL8821A_TRANS_LPS_TO_ACT_STEPS 15 -#define RTL8821A_TRANS_END_STEPS 1 - - -#define RTL8821A_TRANS_CARDEMU_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ - {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \ - {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \ - {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3 | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/ \ - {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ - {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \ - {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*0x4C[24] = 0x4F[0] = 1, switch DPDT_SEL_P output from WL BB */\ - {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5 | BIT4), (BIT5 | BIT4)},/*0x66[13] = 0x67[5] = 1, switch for PAPE_G/PAPE_A from WL BB ; 0x66[12] = 0x67[4] = 1, switch LNAON from WL BB */\ - {0x0025, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/*anapar_mac<118> , 0x25[6]=0 by wlan single function*/\ - {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\ - {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\ - {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\ - {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\ - {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\ - {0x007A, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3A},/*0x7A = 0x3A start BT*/\ - {0x002E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF , 0x82 },/* 0x2C[23:12]=0x820 ; XTAL trim */ \ - {0x0010, PWR_CUT_A_MSK , PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 },/* 0x10[6]=1 ; MP·s¼W¹ï©ó0x2Cªº±±¨îÅv¡A¶·§â0x10[6]³]¬°1¤~¯àÅýWLAN±±¨î */ \ - - -#define RTL8821A_TRANS_ACT_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ - {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*0x4C[24] = 0x4F[0] = 0, switch DPDT_SEL_P output from register 0x65[2] */\ - {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ - {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \ - {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \ - - -#define RTL8821A_TRANS_CARDEMU_TO_SUS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ - -#define RTL8821A_TRANS_SUS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ - -#define RTL8821A_TRANS_CARDEMU_TO_CARDDIS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \ - {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ - -#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ - {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ - {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ - - -#define RTL8821A_TRANS_CARDEMU_TO_PDN \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ - {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ - {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ - -#define RTL8821A_TRANS_PDN_TO_CARDEMU \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ - -#define RTL8821A_TRANS_ACT_TO_LPS \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ - {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ - {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \ - {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \ - - -#define RTL8821A_TRANS_LPS_TO_ACT \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ - {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ - {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ - {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ - {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ - {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ - {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ - {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ - {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ - {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ - -#define RTL8821A_TRANS_END \ - /* format */ \ - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ - {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0}, - - - extern WLAN_PWR_CFG rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8821A_card_disable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8821A_card_enable_flow[RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS + RTL8821A_TRANS_END_STEPS]; - extern WLAN_PWR_CFG rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS]; - -#endif diff --git a/include/rtl8188f_cmd.h b/include/rtl8188f_cmd.h deleted file mode 100644 index 953d8c4..0000000 --- a/include/rtl8188f_cmd.h +++ /dev/null @@ -1,219 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8188F_CMD_H__ -#define __RTL8188F_CMD_H__ - -/* --------------------------------------------------------------------------------------------------------- - * ---------------------------------- H2C CMD DEFINITION ------------------------------------------------ - * --------------------------------------------------------------------------------------------------------- */ - -enum h2c_cmd_8188F { - /* Common Class: 000 */ - H2C_8188F_RSVD_PAGE = 0x00, - H2C_8188F_MEDIA_STATUS_RPT = 0x01, - H2C_8188F_SCAN_ENABLE = 0x02, - H2C_8188F_KEEP_ALIVE = 0x03, - H2C_8188F_DISCON_DECISION = 0x04, - H2C_8188F_PSD_OFFLOAD = 0x05, - H2C_8188F_AP_OFFLOAD = 0x08, - H2C_8188F_BCN_RSVDPAGE = 0x09, - H2C_8188F_PROBERSP_RSVDPAGE = 0x0A, - H2C_8188F_FCS_RSVDPAGE = 0x10, - H2C_8188F_FCS_INFO = 0x11, - H2C_8188F_AP_WOW_GPIO_CTRL = 0x13, - - /* PoweSave Class: 001 */ - H2C_8188F_SET_PWR_MODE = 0x20, - H2C_8188F_PS_TUNING_PARA = 0x21, - H2C_8188F_PS_TUNING_PARA2 = 0x22, - H2C_8188F_P2P_LPS_PARAM = 0x23, - H2C_8188F_P2P_PS_OFFLOAD = 0x24, - H2C_8188F_PS_SCAN_ENABLE = 0x25, - H2C_8188F_SAP_PS_ = 0x26, - H2C_8188F_INACTIVE_PS_ = 0x27, /* Inactive_PS */ - H2C_8188F_FWLPS_IN_IPS_ = 0x28, - - /* Dynamic Mechanism Class: 010 */ - H2C_8188F_MACID_CFG = 0x40, - H2C_8188F_TXBF = 0x41, - H2C_8188F_RSSI_SETTING = 0x42, - H2C_8188F_AP_REQ_TXRPT = 0x43, - H2C_8188F_INIT_RATE_COLLECT = 0x44, - H2C_8188F_RA_PARA_ADJUST = 0x46, - - /* BT Class: 011 */ - H2C_8188F_B_TYPE_TDMA = 0x60, - H2C_8188F_BT_INFO = 0x61, - H2C_8188F_FORCE_BT_TXPWR = 0x62, - H2C_8188F_BT_IGNORE_WLANACT = 0x63, - H2C_8188F_DAC_SWING_VALUE = 0x64, - H2C_8188F_ANT_SEL_RSV = 0x65, - H2C_8188F_WL_OPMODE = 0x66, - H2C_8188F_BT_MP_OPER = 0x67, - H2C_8188F_BT_CONTROL = 0x68, - H2C_8188F_BT_WIFI_CTRL = 0x69, - H2C_8188F_BT_FW_PATCH = 0x6A, - H2C_8188F_BT_WLAN_CALIBRATION = 0x6D, - - /* WOWLAN Class: 100 */ - H2C_8188F_WOWLAN = 0x80, - H2C_8188F_REMOTE_WAKE_CTRL = 0x81, - H2C_8188F_AOAC_GLOBAL_INFO = 0x82, - H2C_8188F_AOAC_RSVD_PAGE = 0x83, - H2C_8188F_AOAC_RSVD_PAGE2 = 0x84, - H2C_8188F_D0_SCAN_OFFLOAD_CTRL = 0x85, - H2C_8188F_D0_SCAN_OFFLOAD_INFO = 0x86, - H2C_8188F_CHNL_SWITCH_OFFLOAD = 0x87, - H2C_8188F_P2P_OFFLOAD_RSVD_PAGE = 0x8A, - H2C_8188F_P2P_OFFLOAD = 0x8B, - - H2C_8188F_RESET_TSF = 0xC0, - H2C_8188F_MAXID, -}; - -/* --------------------------------------------------------------------------------------------------------- - * ---------------------------------- H2C CMD CONTENT -------------------------------------------------- - * --------------------------------------------------------------------------------------------------------- - * _RSVDPAGE_LOC_CMD_0x00 */ -#define SET_8188F_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8188F_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) -#define SET_8188F_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) -#define SET_8188F_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) -#define SET_8188F_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) - -/* _KEEP_ALIVE_CMD_0x03 */ -#define SET_8188F_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) -#define SET_8188F_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) -#define SET_8188F_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) -#define SET_8188F_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) - -/* _DISCONNECT_DECISION_CMD_0x04 */ -#define SET_8188F_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) -#define SET_8188F_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) -#define SET_8188F_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) -#define SET_8188F_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) - -/* _PWR_MOD_CMD_0x20 */ -#define SET_8188F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8188F_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value) -#define SET_8188F_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value) -#define SET_8188F_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) -#define SET_8188F_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) -#define SET_8188F_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value) -#define SET_8188F_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) -#define SET_8188F_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) - -#define GET_8188F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8) - -/* _PS_TUNE_PARAM_CMD_0x21 */ -#define SET_8188F_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8188F_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) -#define SET_8188F_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value) -#define SET_8188F_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value) -#define SET_8188F_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) - -/* _MACID_CFG_CMD_0x40 */ -#define SET_8188F_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8188F_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value) -#define SET_8188F_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value) -#define SET_8188F_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value) -#define SET_8188F_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value) -#define SET_8188F_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value) -#define SET_8188F_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value) -#define SET_8188F_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value) -#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) -#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value) -#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value) -#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value) - -/* _RSSI_SETTING_CMD_0x42 */ -#define SET_8188F_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8188F_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value) -#define SET_8188F_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) - -/* _AP_REQ_TXRPT_CMD_0x43 */ -#define SET_8188F_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8188F_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) - -/* _FORCE_BT_TXPWR_CMD_0x62 */ -#define SET_8188F_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) - -/* _FORCE_BT_MP_OPER_CMD_0x67 */ -#define SET_8188F_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) -#define SET_8188F_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value) -#define SET_8188F_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) -#define SET_8188F_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) -#define SET_8188F_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) -#define SET_8188F_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value) - -/* _BT_FW_PATCH_0x6A */ -#define SET_8188F_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value) -#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) -#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) -#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) -#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) - - -/* --------------------------------------------------------------------------------------------------------- - * ------------------------------------------- Structure -------------------------------------------------- - * --------------------------------------------------------------------------------------------------------- */ - - -/* --------------------------------------------------------------------------------------------------------- - * ---------------------------------- Function Statement -------------------------------------------------- - * --------------------------------------------------------------------------------------------------------- */ - -/* host message to firmware cmd */ -void rtl8188f_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); -void rtl8188f_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus); -void rtl8188f_set_rssi_cmd(PADAPTER padapter, u8 *param); -void rtl8188f_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack); -/* s32 rtl8188f_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */ -void rtl8188f_set_FwPsTuneParam_cmd(PADAPTER padapter); -void rtl8188f_set_FwMacIdConfig_cmd(_adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask, u8 ignore_bw); -void rtl8188f_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param); -void rtl8188f_download_rsvd_page(PADAPTER padapter, u8 mstatus); -#ifdef CONFIG_BT_COEXIST - void rtl8188f_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter); -#endif /* CONFIG_BT_COEXIST */ -#ifdef CONFIG_P2P -void rtl8188f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); -#endif /* CONFIG_P2P */ - -void CheckFwRsvdPageContent(PADAPTER padapter); - -#ifdef CONFIG_TDLS -#ifdef CONFIG_TDLS_CH_SW -void rtl8188f_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); -#endif -#endif - -#ifdef CONFIG_P2P_WOWLAN -void rtl8188f_set_p2p_wowlan_offload_cmd(PADAPTER padapter); -#endif - -void rtl8188f_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param); - -#ifdef CONFIG_TSF_RESET_OFFLOAD -u8 rtl8188f_reset_tsf(_adapter *padapter, u8 reset_port); -#endif /* CONFIG_TSF_RESET_OFFLOAD */ -s32 FillH2CCmd8188F(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); -u8 GetTxBufferRsvdPageNum8188F(_adapter *padapter, bool wowlan); -#endif diff --git a/include/rtl8188f_dm.h b/include/rtl8188f_dm.h deleted file mode 100644 index 78aeab0..0000000 --- a/include/rtl8188f_dm.h +++ /dev/null @@ -1,47 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8188F_DM_H__ -#define __RTL8188F_DM_H__ -/* ************************************************************ - * Description: - * - * This file is for 8188F dynamic mechanism only - * - * - * ************************************************************ */ - -/* ************************************************************ - * structure and define - * ************************************************************ */ - -/* ************************************************************ - * function prototype - * ************************************************************ */ - -void rtl8188f_init_dm_priv(PADAPTER padapter); -void rtl8188f_deinit_dm_priv(PADAPTER padapter); - -void rtl8188f_InitHalDm(PADAPTER padapter); -void rtl8188f_HalDmWatchDog(PADAPTER padapter); -void rtl8188f_HalDmWatchDog_in_LPS(PADAPTER padapter); -void rtl8188f_hal_dm_in_lps(PADAPTER padapter); - - -#endif diff --git a/include/rtl8188f_hal.h b/include/rtl8188f_hal.h deleted file mode 100644 index 874a3b2..0000000 --- a/include/rtl8188f_hal.h +++ /dev/null @@ -1,271 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8188F_HAL_H__ -#define __RTL8188F_HAL_H__ - -#include "hal_data.h" - -#include "rtl8188f_spec.h" -#include "rtl8188f_rf.h" -#include "rtl8188f_dm.h" -#include "rtl8188f_recv.h" -#include "rtl8188f_xmit.h" -#include "rtl8188f_cmd.h" -#include "rtl8188f_led.h" -#include "Hal8188FPwrSeq.h" -#include "Hal8188FPhyReg.h" -#include "Hal8188FPhyCfg.h" -#ifdef DBG_CONFIG_ERROR_DETECT -#include "rtl8188f_sreset.h" -#endif - -#define FW_8188F_SIZE 0x8000 -#define FW_8188F_START_ADDRESS 0x1000 -#define FW_8188F_END_ADDRESS 0x1FFF /* 0x5FFF */ - -#define IS_FW_HEADER_EXIST_8188F(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x88F0) - -typedef struct _RT_FIRMWARE { - FIRMWARE_SOURCE eFWSource; -#ifdef CONFIG_EMBEDDED_FWIMG - u8 *szFwBuffer; -#else - u8 szFwBuffer[FW_8188F_SIZE]; -#endif - u32 ulFwLength; -} RT_FIRMWARE_8188F, *PRT_FIRMWARE_8188F; - -/* - * This structure must be cared byte-ordering - * - * Added by tynli. 2009.12.04. */ -typedef struct _RT_8188F_FIRMWARE_HDR { - /* 8-byte alinment required */ - - /* --- LONG WORD 0 ---- */ - u16 Signature; /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */ - u8 Category; /* AP/NIC and USB/PCI */ - u8 Function; /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */ - u16 Version; /* FW Version */ - u16 Subversion; /* FW Subversion, default 0x00 */ - - /* --- LONG WORD 1 ---- */ - u8 Month; /* Release time Month field */ - u8 Date; /* Release time Date field */ - u8 Hour; /* Release time Hour field */ - u8 Minute; /* Release time Minute field */ - u16 RamCodeSize; /* The size of RAM code */ - u16 Rsvd2; - - /* --- LONG WORD 2 ---- */ - u32 SvnIdx; /* The SVN entry index */ - u32 Rsvd3; - - /* --- LONG WORD 3 ---- */ - u32 Rsvd4; - u32 Rsvd5; -} RT_8188F_FIRMWARE_HDR, *PRT_8188F_FIRMWARE_HDR; - -#define DRIVER_EARLY_INT_TIME_8188F 0x05 -#define BCN_DMA_ATIME_INT_TIME_8188F 0x02 - -/* for 8188F - * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */ -#define PAGE_SIZE_TX_8188F 128 -#define PAGE_SIZE_RX_8188F 8 - -#define RX_DMA_SIZE_8188F 0x4000 /* 16K */ -#ifdef CONFIG_FW_C2H_DEBUG - #define RX_DMA_RESERVED_SIZE_8188F 0x100 /* 256B, reserved for c2h debug message */ -#else - #define RX_DMA_RESERVED_SIZE_8188F 0x80 /* 128B, reserved for tx report */ -#endif - -#ifdef CONFIG_WOWLAN - #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/ -#else - #define RESV_FMWF 0 -#endif - -#define RX_DMA_BOUNDARY_8188F (RX_DMA_SIZE_8188F - RX_DMA_RESERVED_SIZE_8188F - 1) - -/* Note: We will divide number of page equally for each queue other than public queue! */ - -/* For General Reserved Page Number(Beacon Queue is reserved page) - * Beacon:2, PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1 */ -#define BCNQ_PAGE_NUM_8188F 0x08 -#ifdef CONFIG_CONCURRENT_MODE - #define BCNQ1_PAGE_NUM_8188F 0x08 /* 0x04 */ -#else - #define BCNQ1_PAGE_NUM_8188F 0x00 -#endif - -#ifdef CONFIG_PNO_SUPPORT -#undef BCNQ1_PAGE_NUM_8188F -#define BCNQ1_PAGE_NUM_8188F 0x00 /* 0x04 */ -#endif - -/* For WoWLan , more reserved page - * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt:1 ,PNO: 6 */ -#ifdef CONFIG_WOWLAN - #define WOWLAN_PAGE_NUM_8188F 0x08 -#else - #define WOWLAN_PAGE_NUM_8188F 0x00 -#endif - -#ifdef CONFIG_PNO_SUPPORT -#undef WOWLAN_PAGE_NUM_8188F -#define WOWLAN_PAGE_NUM_8188F 0x15 -#endif - -#ifdef CONFIG_AP_WOWLAN -#define AP_WOWLAN_PAGE_NUM_8188F 0x02 -#endif - -#define TX_TOTAL_PAGE_NUMBER_8188F (0xFF - BCNQ_PAGE_NUM_8188F - BCNQ1_PAGE_NUM_8188F - WOWLAN_PAGE_NUM_8188F) -#define TX_PAGE_BOUNDARY_8188F (TX_TOTAL_PAGE_NUMBER_8188F + 1) - -#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8188F TX_TOTAL_PAGE_NUMBER_8188F -#define WMM_NORMAL_TX_PAGE_BOUNDARY_8188F (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8188F + 1) - -/* For Normal Chip Setting - * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8188F */ -#define NORMAL_PAGE_NUM_HPQ_8188F 0x0C -#define NORMAL_PAGE_NUM_LPQ_8188F 0x02 -#define NORMAL_PAGE_NUM_NPQ_8188F 0x02 - -/* Note: For Normal Chip Setting, modify later */ -#define WMM_NORMAL_PAGE_NUM_HPQ_8188F 0x30 -#define WMM_NORMAL_PAGE_NUM_LPQ_8188F 0x20 -#define WMM_NORMAL_PAGE_NUM_NPQ_8188F 0x20 - - -#include "HalVerDef.h" -#include "hal_com.h" - -#define EFUSE_OOB_PROTECT_BYTES (34 + 1) - -#define HAL_EFUSE_MEMORY - -#define HWSET_MAX_SIZE_8188F 512 -#define EFUSE_REAL_CONTENT_LEN_8188F 256 -#define EFUSE_MAP_LEN_8188F 512 -#define EFUSE_MAX_SECTION_8188F (EFUSE_MAP_LEN_8188F / 8) - -#define EFUSE_IC_ID_OFFSET 506 /* For some inferiority IC purpose. added by Roger, 2009.09.02. */ -#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN_8188F) - -#define EFUSE_ACCESS_ON 0x69 /* For RTL8188 only. */ -#define EFUSE_ACCESS_OFF 0x00 /* For RTL8188 only. */ - -/* ******************************************************** - * EFUSE for BT definition - * ******************************************************** */ -#define EFUSE_BT_REAL_BANK_CONTENT_LEN 512 -#define EFUSE_BT_REAL_CONTENT_LEN 1536 /* 512*3 */ -#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */ -#define EFUSE_BT_MAX_SECTION 128 /* 1024/8 */ - -#define EFUSE_PROTECT_BYTES_BANK 16 - -#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT) -#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) - -/* rtl8188a_hal_init.c */ -s32 rtl8188f_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw); -void rtl8188f_FirmwareSelfReset(PADAPTER padapter); -void rtl8188f_InitializeFirmwareVars(PADAPTER padapter); - -void rtl8188f_InitAntenna_Selection(PADAPTER padapter); -void rtl8188f_DeinitAntenna_Selection(PADAPTER padapter); -void rtl8188f_CheckAntenna_Selection(PADAPTER padapter); -void rtl8188f_init_default_value(PADAPTER padapter); - -s32 rtl8188f_InitLLTTable(PADAPTER padapter); - -s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU); -s32 CardDisableWithoutHWSM(PADAPTER padapter); - -/* EFuse */ -u8 GetEEPROMSize8188F(PADAPTER padapter); -void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent); -void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo); -void Hal_EfuseParseTxPowerInfo_8188F(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail); -/* void Hal_EfuseParseBTCoexistInfo_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); */ -void Hal_EfuseParseEEPROMVer_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParseChnlPlan_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParseCustomerID_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParsePowerSavingMode_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParseAntennaDiversity_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParseXtal_8188F(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail); -void Hal_EfuseParseThermalMeter_8188F(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail); -void Hal_EfuseParseKFreeData_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); - -#if 0 /* Do not need for rtl8188f */ -VOID Hal_EfuseParseVoltage_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -#endif - -void rtl8188f_set_pll_ref_clk_sel(_adapter *adapter, u8 sel); - -void rtl8188f_set_hal_ops(struct hal_ops *pHalFunc); -void init_hal_spec_8188f(_adapter *adapter); -void SetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val); -void GetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val); -u8 SetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); -u8 GetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); - -/* register */ -void rtl8188f_InitBeaconParameters(PADAPTER padapter); -void rtl8188f_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode); -void _InitBurstPktLen_8188FS(PADAPTER Adapter); -void _8051Reset8188(PADAPTER padapter); -#ifdef CONFIG_WOWLAN -void Hal_DetectWoWMode(PADAPTER pAdapter); -#endif /* CONFIG_WOWLAN */ - -void rtl8188f_start_thread(_adapter *padapter); -void rtl8188f_stop_thread(_adapter *padapter); - -#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST) - void rtl8188fs_init_checkbthang_workqueue(_adapter *adapter); - void rtl8188fs_free_checkbthang_workqueue(_adapter *adapter); - void rtl8188fs_cancle_checkbthang_workqueue(_adapter *adapter); - void rtl8188fs_hal_check_bt_hang(_adapter *adapter); -#endif - -#ifdef CONFIG_GPIO_WAKEUP -void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue); -#endif - -#ifdef CONFIG_MP_INCLUDED -int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware); -#endif - -void CCX_FwC2HTxRpt_8188f(PADAPTER padapter, u8 *pdata, u8 len); - -u8 MRateToHwRate8188F(u8 rate); -u8 HwRateToMRate8188F(u8 rate); - -#ifdef CONFIG_PCI_HCI -BOOLEAN InterruptRecognized8188FE(PADAPTER Adapter); -VOID UpdateInterruptMask8188FE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1); -#endif - -#endif diff --git a/include/rtl8188f_led.h b/include/rtl8188f_led.h deleted file mode 100644 index 232ede5..0000000 --- a/include/rtl8188f_led.h +++ /dev/null @@ -1,48 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8188F_LED_H__ -#define __RTL8188F_LED_H__ - -#include -#include -#include - - -/* ******************************************************************************** - * Interface to manipulate LED objects. - * ******************************************************************************** */ -#ifdef CONFIG_USB_HCI -void rtl8188fu_InitSwLeds(PADAPTER padapter); -void rtl8188fu_DeInitSwLeds(PADAPTER padapter); -#endif -#ifdef CONFIG_SDIO_HCI -void rtl8188fs_InitSwLeds(PADAPTER padapter); -void rtl8188fs_DeInitSwLeds(PADAPTER padapter); -#endif -#ifdef CONFIG_GSPI_HCI -void rtl8188fs_InitSwLeds(PADAPTER padapter); -void rtl8188fs_DeInitSwLeds(PADAPTER padapter); -#endif -#ifdef CONFIG_PCI_HCI -void rtl8188fe_InitSwLeds(PADAPTER padapter); -void rtl8188fe_DeInitSwLeds(PADAPTER padapter); -#endif - -#endif diff --git a/include/rtl8188f_recv.h b/include/rtl8188f_recv.h deleted file mode 100644 index 380aa6f..0000000 --- a/include/rtl8188f_recv.h +++ /dev/null @@ -1,69 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8188F_RECV_H__ -#define __RTL8188F_RECV_H__ - -#if defined(CONFIG_USB_HCI) - #ifndef MAX_RECVBUF_SZ - #ifdef CONFIG_MINIMAL_MEMORY_USAGE - #define MAX_RECVBUF_SZ (4000) /* about 4K */ - #else - #ifdef CONFIG_PLATFORM_MSTAR - #define MAX_RECVBUF_SZ (8192) /* 8K */ - #elif defined(CONFIG_PLATFORM_HISILICON) - #define MAX_RECVBUF_SZ (16384) /* 16k */ - #else - #define MAX_RECVBUF_SZ (32768) /* 32k */ - #endif - /* #define MAX_RECVBUF_SZ (20480) */ /* 20K */ - /* #define MAX_RECVBUF_SZ (10240) */ /* 10K */ - /* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */ - /* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */ - #endif - #endif /* !MAX_RECVBUF_SZ */ -#elif defined(CONFIG_PCI_HCI) - #define MAX_RECVBUF_SZ (4000) /* about 4K */ -#elif defined(CONFIG_SDIO_HCI) - #define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8188F + 1) -#endif /* CONFIG_SDIO_HCI */ - -/* Rx smooth factor */ -#define Rx_Smooth_Factor (20) - -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) -s32 rtl8188fs_init_recv_priv(PADAPTER padapter); -void rtl8188fs_free_recv_priv(PADAPTER padapter); -s32 rtl8188fs_recv_hdl(_adapter *padapter); -#endif - -#ifdef CONFIG_USB_HCI -int rtl8188fu_init_recv_priv(_adapter *padapter); -void rtl8188fu_free_recv_priv(_adapter *padapter); -void rtl8188fu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf); -#endif - -#ifdef CONFIG_PCI_HCI -s32 rtl8188fe_init_recv_priv(PADAPTER padapter); -void rtl8188fe_free_recv_priv(PADAPTER padapter); -#endif - -void rtl8188f_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc); - -#endif /* __RTL8188F_RECV_H__ */ diff --git a/include/rtl8188f_rf.h b/include/rtl8188f_rf.h deleted file mode 100644 index 185d2d0..0000000 --- a/include/rtl8188f_rf.h +++ /dev/null @@ -1,30 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8188F_RF_H__ -#define __RTL8188F_RF_H__ - -int PHY_RF6052_Config8188F(IN PADAPTER Adapter); - -VOID -PHY_RF6052SetBandwidth8188F( - IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth); - -#endif diff --git a/include/rtl8188f_spec.h b/include/rtl8188f_spec.h deleted file mode 100644 index 7282cc1..0000000 --- a/include/rtl8188f_spec.h +++ /dev/null @@ -1,291 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ -#ifndef __RTL8188F_SPEC_H__ -#define __RTL8188F_SPEC_H__ - -#include - - -#define HAL_NAV_UPPER_UNIT_8188F 128 /* micro-second */ - -/* ----------------------------------------------------- - * - * 0x0000h ~ 0x00FFh System Configuration - * - * ----------------------------------------------------- */ -#define REG_RSV_CTRL_8188F 0x001C /* 3 Byte */ -#define REG_BT_WIFI_ANTENNA_SWITCH_8188F 0x0038 -#define REG_HSISR_8188F 0x005c -#define REG_PAD_CTRL1_8188F 0x0064 -#define REG_AFE_CTRL_4_8188F 0x0078 -#define REG_HMEBOX_DBG_0_8188F 0x0088 -#define REG_HMEBOX_DBG_1_8188F 0x008A -#define REG_HMEBOX_DBG_2_8188F 0x008C -#define REG_HMEBOX_DBG_3_8188F 0x008E -#define REG_HIMR0_8188F 0x00B0 -#define REG_HISR0_8188F 0x00B4 -#define REG_HIMR1_8188F 0x00B8 -#define REG_HISR1_8188F 0x00BC -#define REG_PMC_DBG_CTRL2_8188F 0x00CC - -/* ----------------------------------------------------- - * - * 0x0100h ~ 0x01FFh MACTOP General Configuration - * - * ----------------------------------------------------- */ -#define REG_C2HEVT_CMD_ID_8188F 0x01A0 -#define REG_C2HEVT_CMD_LEN_8188F 0x01AE -#define REG_WOWLAN_WAKE_REASON 0x01C7 -#define REG_WOWLAN_GTK_DBG1 0x630 -#define REG_WOWLAN_GTK_DBG2 0x634 - -#define REG_HMEBOX_EXT0_8188F 0x01F0 -#define REG_HMEBOX_EXT1_8188F 0x01F4 -#define REG_HMEBOX_EXT2_8188F 0x01F8 -#define REG_HMEBOX_EXT3_8188F 0x01FC - -/* ----------------------------------------------------- - * - * 0x0200h ~ 0x027Fh TXDMA Configuration - * - * ----------------------------------------------------- */ - -/* ----------------------------------------------------- - * - * 0x0280h ~ 0x02FFh RXDMA Configuration - * - * ----------------------------------------------------- */ -#define REG_RXDMA_CONTROL_8188F 0x0286 /* Control the RX DMA. */ -#define REG_RXDMA_MODE_CTRL_8188F 0x0290 - -/* ----------------------------------------------------- - * - * 0x0300h ~ 0x03FFh PCIe - * - * ----------------------------------------------------- */ -#define REG_PCIE_CTRL_REG_8188F 0x0300 -#define REG_INT_MIG_8188F 0x0304 /* Interrupt Migration */ -#define REG_BCNQ_DESA_8188F 0x0308 /* TX Beacon Descriptor Address */ -#define REG_HQ_DESA_8188F 0x0310 /* TX High Queue Descriptor Address */ -#define REG_MGQ_DESA_8188F 0x0318 /* TX Manage Queue Descriptor Address */ -#define REG_VOQ_DESA_8188F 0x0320 /* TX VO Queue Descriptor Address */ -#define REG_VIQ_DESA_8188F 0x0328 /* TX VI Queue Descriptor Address */ -#define REG_BEQ_DESA_8188F 0x0330 /* TX BE Queue Descriptor Address */ -#define REG_BKQ_DESA_8188F 0x0338 /* TX BK Queue Descriptor Address */ -#define REG_RX_DESA_8188F 0x0340 /* RX Queue Descriptor Address */ -#define REG_DBI_WDATA_8188F 0x0348 /* DBI Write Data */ -#define REG_DBI_RDATA_8188F 0x034C /* DBI Read Data */ -#define REG_DBI_ADDR_8188F 0x0350 /* DBI Address */ -#define REG_DBI_FLAG_8188F 0x0352 /* DBI Read/Write Flag */ -#define REG_MDIO_WDATA_8188F 0x0354 /* MDIO for Write PCIE PHY */ -#define REG_MDIO_RDATA_8188F 0x0356 /* MDIO for Reads PCIE PHY */ -#define REG_MDIO_CTL_8188F 0x0358 /* MDIO for Control */ -#define REG_DBG_SEL_8188F 0x0360 /* Debug Selection Register */ -#define REG_PCIE_HRPWM_8188F 0x0361 /* PCIe RPWM */ -#define REG_PCIE_HCPWM_8188F 0x0363 /* PCIe CPWM */ -#define REG_PCIE_MULTIFET_CTRL_8188F 0x036A /* PCIE Multi-Fethc Control */ - -/* ----------------------------------------------------- - * - * 0x0400h ~ 0x047Fh Protocol Configuration - * - * ----------------------------------------------------- */ -#define REG_TXPKTBUF_BCNQ_BDNY_8188F 0x0424 -#define REG_TXPKTBUF_MGQ_BDNY_8188F 0x0425 -#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8188F 0x045D -#ifdef CONFIG_WOWLAN -#define REG_TXPKTBUF_IV_LOW 0x0484 -#define REG_TXPKTBUF_IV_HIGH 0x0488 -#endif -#define REG_AMPDU_BURST_MODE_8188F 0x04BC - -/* ----------------------------------------------------- - * - * 0x0500h ~ 0x05FFh EDCA Configuration - * - * ----------------------------------------------------- */ -#define REG_SECONDARY_CCA_CTRL_8188F 0x0577 - -/* ----------------------------------------------------- - * - * 0x0600h ~ 0x07FFh WMAC Configuration - * - * ----------------------------------------------------- */ - - -/* ************************************************************ - * SDIO Bus Specification - * ************************************************************ */ - -/* ----------------------------------------------------- - * SDIO CMD Address Mapping - * ----------------------------------------------------- */ - -/* ----------------------------------------------------- - * I/O bus domain (Host) - * ----------------------------------------------------- */ - -/* ----------------------------------------------------- - * SDIO register - * ----------------------------------------------------- */ -#define SDIO_REG_HIQ_FREEPG_8188F 0x0020 -#define SDIO_REG_MID_FREEPG_8188F 0x0022 -#define SDIO_REG_LOW_FREEPG_8188F 0x0024 -#define SDIO_REG_PUB_FREEPG_8188F 0x0026 -#define SDIO_REG_EXQ_FREEPG_8188F 0x0028 -#define SDIO_REG_AC_OQT_FREEPG_8188F 0x002A -#define SDIO_REG_NOAC_OQT_FREEPG_8188F 0x002B - -#define SDIO_REG_HCPWM1_8188F 0x0038 - -/* indirect access */ -#define SDIO_REG_INDIRECT_REG_CFG_8188F 0x40 -#define SET_INDIRECT_REG_ADDR(_cmd, _addr) SET_BITS_TO_LE_2BYTE(((u8 *)(_cmd)) + 0, 0, 16, (_addr)) -#define SET_INDIRECT_REG_SIZE_1BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 0) -#define SET_INDIRECT_REG_SIZE_2BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 1) -#define SET_INDIRECT_REG_SIZE_4BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 2) -#define SET_INDIRECT_REG_WRITE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 2, 1, 1) -#define SET_INDIRECT_REG_READ(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 3, 1, 1) -#define GET_INDIRECT_REG_RDY(_cmd) LE_BITS_TO_1BYTE(((u8 *)(_cmd)) + 2, 4, 1) - -#define SDIO_REG_INDIRECT_REG_DATA_8188F 0x44 - -/* **************************************************************************** - * 8188 Regsiter Bit and Content definition - * **************************************************************************** */ - -/* 2 HSISR - * interrupt mask which needs to clear */ -#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\ - HSISR_SPS_OCP_INT |\ - HSISR_RON_INT |\ - HSISR_PDNINT |\ - HSISR_GPIO9_INT) - -/* ----------------------------------------------------- - * - * 0x0100h ~ 0x01FFh MACTOP General Configuration - * - * ----------------------------------------------------- */ - - -/* ----------------------------------------------------- - * - * 0x0200h ~ 0x027Fh TXDMA Configuration - * - * ----------------------------------------------------- */ - -/* ----------------------------------------------------- - * - * 0x0280h ~ 0x02FFh RXDMA Configuration - * - * ----------------------------------------------------- */ -#define BIT_USB_RXDMA_AGG_EN BIT(31) -#define RXDMA_AGG_MODE_EN BIT(1) - -#ifdef CONFIG_WOWLAN -#define RXPKT_RELEASE_POLL BIT(16) -#define RXDMA_IDLE BIT(17) -#define RW_RELEASE_EN BIT(18) -#endif - -/* ----------------------------------------------------- - * - * 0x0400h ~ 0x047Fh Protocol Configuration - * - * ----------------------------------------------------- */ - -/* ---------------------------------------------------------------------------- - * 8188F REG_CCK_CHECK (offset 0x454) - * ---------------------------------------------------------------------------- */ -#define BIT_BCN_PORT_SEL BIT(5) - -/* ----------------------------------------------------- - * - * 0x0500h ~ 0x05FFh EDCA Configuration - * - * ----------------------------------------------------- */ - -/* ----------------------------------------------------- - * - * 0x0600h ~ 0x07FFh WMAC Configuration - * - * ----------------------------------------------------- */ - -/* ---------------------------------------------------------------------------- - * 8195 IMR/ISR bits (offset 0xB0, 8bits) - * ---------------------------------------------------------------------------- */ -#define IMR_DISABLED_8188F 0 -/* IMR DW0(0x00B0-00B3) Bit 0-31 */ -#define IMR_TIMER2_8188F BIT(31) /* Timeout interrupt 2 */ -#define IMR_TIMER1_8188F BIT(30) /* Timeout interrupt 1 */ -#define IMR_PSTIMEOUT_8188F BIT(29) /* Power Save Time Out Interrupt */ -#define IMR_GTINT4_8188F BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ -#define IMR_GTINT3_8188F BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ -#define IMR_TXBCN0ERR_8188F BIT(26) /* Transmit Beacon0 Error */ -#define IMR_TXBCN0OK_8188F BIT(25) /* Transmit Beacon0 OK */ -#define IMR_TSF_BIT32_TOGGLE_8188F BIT(24) /* TSF Timer BIT(32) toggle indication interrupt */ -#define IMR_BCNDMAINT0_8188F BIT(20) /* Beacon DMA Interrupt 0 */ -#define IMR_BCNDERR0_8188F BIT(16) /* Beacon Queue DMA OK0 */ -#define IMR_HSISR_IND_ON_INT_8188F BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ -#define IMR_BCNDMAINT_E_8188F BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ -#define IMR_ATIMEND_8188F BIT(12) /* CTWidnow End or ATIM Window End */ -#define IMR_C2HCMD_8188F BIT(10) /* CPU to Host Command INT Status, Write 1 clear */ -#define IMR_CPWM2_8188F BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_CPWM_8188F BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_HIGHDOK_8188F BIT(7) /* High Queue DMA OK */ -#define IMR_MGNTDOK_8188F BIT(6) /* Management Queue DMA OK */ -#define IMR_BKDOK_8188F BIT(5) /* AC_BK DMA OK */ -#define IMR_BEDOK_8188F BIT(4) /* AC_BE DMA OK */ -#define IMR_VIDOK_8188F BIT(3) /* AC_VI DMA OK */ -#define IMR_VODOK_8188F BIT(2) /* AC_VO DMA OK */ -#define IMR_RDU_8188F BIT(1) /* Rx Descriptor Unavailable */ -#define IMR_ROK_8188F BIT(0) /* Receive DMA OK */ - -/* IMR DW1(0x00B4-00B7) Bit 0-31 */ -#define IMR_BCNDMAINT7_8188F BIT(27) /* Beacon DMA Interrupt 7 */ -#define IMR_BCNDMAINT6_8188F BIT(26) /* Beacon DMA Interrupt 6 */ -#define IMR_BCNDMAINT5_8188F BIT(25) /* Beacon DMA Interrupt 5 */ -#define IMR_BCNDMAINT4_8188F BIT(24) /* Beacon DMA Interrupt 4 */ -#define IMR_BCNDMAINT3_8188F BIT(23) /* Beacon DMA Interrupt 3 */ -#define IMR_BCNDMAINT2_8188F BIT(22) /* Beacon DMA Interrupt 2 */ -#define IMR_BCNDMAINT1_8188F BIT(21) /* Beacon DMA Interrupt 1 */ -#define IMR_BCNDOK7_8188F BIT(20) /* Beacon Queue DMA OK Interrupt 7 */ -#define IMR_BCNDOK6_8188F BIT(19) /* Beacon Queue DMA OK Interrupt 6 */ -#define IMR_BCNDOK5_8188F BIT(18) /* Beacon Queue DMA OK Interrupt 5 */ -#define IMR_BCNDOK4_8188F BIT(17) /* Beacon Queue DMA OK Interrupt 4 */ -#define IMR_BCNDOK3_8188F BIT(16) /* Beacon Queue DMA OK Interrupt 3 */ -#define IMR_BCNDOK2_8188F BIT(15) /* Beacon Queue DMA OK Interrupt 2 */ -#define IMR_BCNDOK1_8188F BIT(14) /* Beacon Queue DMA OK Interrupt 1 */ -#define IMR_ATIMEND_E_8188F BIT(13) /* ATIM Window End Extension for Win7 */ -#define IMR_TXERR_8188F BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */ -#define IMR_RXERR_8188F BIT(10) /* Rx Error Flag INT Status, Write 1 clear */ -#define IMR_TXFOVW_8188F BIT(9) /* Transmit FIFO Overflow */ -#define IMR_RXFOVW_8188F BIT(8) /* Receive FIFO Overflow */ - -#ifdef CONFIG_PCI_HCI -/* #define IMR_RX_MASK (IMR_ROK_8188F|IMR_RDU_8188F|IMR_RXFOVW_8188F) */ -#define IMR_TX_MASK (IMR_VODOK_8188F | IMR_VIDOK_8188F | IMR_BEDOK_8188F | IMR_BKDOK_8188F | IMR_MGNTDOK_8188F | IMR_HIGHDOK_8188F) - -#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8188F | IMR_TXBCN0OK_8188F | IMR_TXBCN0ERR_8188F | IMR_BCNDERR0_8188F) - -#define RT_AC_INT_MASKS (IMR_VIDOK_8188F | IMR_VODOK_8188F | IMR_BEDOK_8188F | IMR_BKDOK_8188F) -#endif - -#endif /* __RTL8188F_SPEC_H__ */ diff --git a/include/rtl8188f_sreset.h b/include/rtl8188f_sreset.h deleted file mode 100644 index ef5b0ff..0000000 --- a/include/rtl8188f_sreset.h +++ /dev/null @@ -1,29 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef _RTL8188F_SRESET_H_ -#define _RTL8188F_SRESET_H_ - -#include - -#ifdef DBG_CONFIG_ERROR_DETECT -extern void rtl8188f_sreset_xmit_status_check(_adapter *padapter); -extern void rtl8188f_sreset_linked_status_check(_adapter *padapter); -#endif -#endif diff --git a/include/rtl8188f_xmit.h b/include/rtl8188f_xmit.h deleted file mode 100644 index be88ca4..0000000 --- a/include/rtl8188f_xmit.h +++ /dev/null @@ -1,338 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8188F_XMIT_H__ -#define __RTL8188F_XMIT_H__ - - -#define MAX_TID (15) - - -#ifndef __INC_HAL8188FDESC_H -#define __INC_HAL8188FDESC_H - -#define RX_STATUS_DESC_SIZE_8188F 24 -#define RX_DRV_INFO_SIZE_UNIT_8188F 8 - - -/* DWORD 0 */ -#define SET_RX_STATUS_DESC_PKT_LEN_8188F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value) -#define SET_RX_STATUS_DESC_EOR_8188F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value) -#define SET_RX_STATUS_DESC_OWN_8188F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value) - -#define GET_RX_STATUS_DESC_PKT_LEN_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14) -#define GET_RX_STATUS_DESC_CRC32_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1) -#define GET_RX_STATUS_DESC_ICV_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1) -#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4) -#define GET_RX_STATUS_DESC_SECURITY_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3) -#define GET_RX_STATUS_DESC_QOS_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1) -#define GET_RX_STATUS_DESC_SHIFT_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2) -#define GET_RX_STATUS_DESC_PHY_STATUS_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1) -#define GET_RX_STATUS_DESC_SWDEC_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1) -#define GET_RX_STATUS_DESC_LAST_SEG_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1) -#define GET_RX_STATUS_DESC_FIRST_SEG_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1) -#define GET_RX_STATUS_DESC_EOR_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1) -#define GET_RX_STATUS_DESC_OWN_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1) - -/* DWORD 1 */ -#define GET_RX_STATUS_DESC_MACID_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7) -#define GET_RX_STATUS_DESC_TID_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4) -#define GET_RX_STATUS_DESC_AMSDU_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1) -#define GET_RX_STATUS_DESC_RXID_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1) -#define GET_RX_STATUS_DESC_PAGGR_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1) -#define GET_RX_STATUS_DESC_A1_FIT_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4) -#define GET_RX_STATUS_DESC_CHKERR_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1) -#define GET_RX_STATUS_DESC_IPVER_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1) -#define GET_RX_STATUS_DESC_IS_TCPUDP__8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1) -#define GET_RX_STATUS_DESC_CHK_VLD_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1) -#define GET_RX_STATUS_DESC_PAM_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1) -#define GET_RX_STATUS_DESC_PWR_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1) -#define GET_RX_STATUS_DESC_MORE_DATA_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1) -#define GET_RX_STATUS_DESC_MORE_FRAG_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1) -#define GET_RX_STATUS_DESC_TYPE_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2) -#define GET_RX_STATUS_DESC_MC_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1) -#define GET_RX_STATUS_DESC_BC_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1) - -/* DWORD 2 */ -#define GET_RX_STATUS_DESC_SEQ_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12) -#define GET_RX_STATUS_DESC_FRAG_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4) -#define GET_RX_STATUS_DESC_RX_IS_QOS_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1) -#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6) -#define GET_RX_STATUS_DESC_RPT_SEL_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1) - -/* DWORD 3 */ -#define GET_RX_STATUS_DESC_RX_RATE_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7) -#define GET_RX_STATUS_DESC_HTC_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1) -#define GET_RX_STATUS_DESC_EOSP_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1) -#define GET_RX_STATUS_DESC_BSSID_FIT_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2) -#ifdef CONFIG_USB_RX_AGGREGATION -#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8) -#endif -#define GET_RX_STATUS_DESC_PATTERN_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1) -#define GET_RX_STATUS_DESC_UNICAST_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1) -#define GET_RX_STATUS_DESC_MAGIC_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1) - -/* DWORD 6 */ -#define GET_RX_STATUS_DESC_SPLCP_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1) -#define GET_RX_STATUS_DESC_LDPC_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1) -#define GET_RX_STATUS_DESC_STBC_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1) -#define GET_RX_STATUS_DESC_BW_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2) - -/* DWORD 5 */ -#define GET_RX_STATUS_DESC_TSFL_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32) - -#define GET_RX_STATUS_DESC_BUFF_ADDR_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32) -#define GET_RX_STATUS_DESC_BUFF_ADDR64_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32) - -#define SET_RX_STATUS_DESC_BUFF_ADDR_8188F(__pRxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value) - - -/* Dword 0 */ -#define GET_TX_DESC_OWN_8188F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1) - -#define SET_TX_DESC_PKT_SIZE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value) -#define SET_TX_DESC_OFFSET_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value) -#define SET_TX_DESC_BMC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value) -#define SET_TX_DESC_HTC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value) -#define SET_TX_DESC_LAST_SEG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value) -#define SET_TX_DESC_FIRST_SEG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value) -#define SET_TX_DESC_LINIP_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value) -#define SET_TX_DESC_NO_ACM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value) -#define SET_TX_DESC_GF_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value) -#define SET_TX_DESC_OWN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) - -/* Dword 1 */ -#define SET_TX_DESC_MACID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value) -#define SET_TX_DESC_QUEUE_SEL_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value) -#define SET_TX_DESC_RDG_NAV_EXT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value) -#define SET_TX_DESC_LSIG_TXOP_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value) -#define SET_TX_DESC_PIFS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value) -#define SET_TX_DESC_RATE_ID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value) -#define SET_TX_DESC_EN_DESC_ID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value) -#define SET_TX_DESC_SEC_TYPE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value) -#define SET_TX_DESC_PKT_OFFSET_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value) - - -/* Dword 2 */ -#define SET_TX_DESC_PAID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value) -#define SET_TX_DESC_CCA_RTS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value) -#define SET_TX_DESC_AGG_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value) -#define SET_TX_DESC_RDG_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value) -#define SET_TX_DESC_AGG_BREAK_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value) -#define SET_TX_DESC_MORE_FRAG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value) -#define SET_TX_DESC_RAW_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value) -#define SET_TX_DESC_SPE_RPT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value) -#define SET_TX_DESC_AMPDU_DENSITY_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value) -#define SET_TX_DESC_BT_INT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value) -#define SET_TX_DESC_GID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value) - - -/* Dword 3 */ -#define SET_TX_DESC_WHEADER_LEN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value) -#define SET_TX_DESC_CHK_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value) -#define SET_TX_DESC_EARLY_MODE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value) -#define SET_TX_DESC_HWSEQ_SEL_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value) -#define SET_TX_DESC_USE_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value) -#define SET_TX_DESC_DISABLE_RTS_FB_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value) -#define SET_TX_DESC_DISABLE_FB_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value) -#define SET_TX_DESC_CTS2SELF_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value) -#define SET_TX_DESC_RTS_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value) -#define SET_TX_DESC_HW_RTS_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value) -#define SET_TX_DESC_NAV_USE_HDR_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value) -#define SET_TX_DESC_USE_MAX_LEN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value) -#define SET_TX_DESC_MAX_AGG_NUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value) -#define SET_TX_DESC_NDPA_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value) -#define SET_TX_DESC_AMPDU_MAX_TIME_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value) - -/* Dword 4 */ -#define SET_TX_DESC_TX_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value) -#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value) -#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value) -#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value) -#define SET_TX_DESC_DATA_RETRY_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value) -#define SET_TX_DESC_RTS_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value) - - -/* Dword 5 */ -#define SET_TX_DESC_DATA_SC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value) -#define SET_TX_DESC_DATA_SHORT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value) -#define SET_TX_DESC_DATA_BW_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value) -#define SET_TX_DESC_DATA_LDPC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value) -#define SET_TX_DESC_DATA_STBC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value) -#define SET_TX_DESC_CTROL_STBC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value) -#define SET_TX_DESC_RTS_SHORT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value) -#define SET_TX_DESC_RTS_SC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value) - - -/* Dword 6 */ -#define SET_TX_DESC_SW_DEFINE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value) -#define SET_TX_DESC_MBSSID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value) -#define SET_TX_DESC_ANTSEL_A_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value) -#define SET_TX_DESC_ANTSEL_B_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value) -#define SET_TX_DESC_ANTSEL_C_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value) -#define SET_TX_DESC_ANTSEL_D_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value) - -/* Dword 7 */ -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) -#define SET_TX_DESC_TX_BUFFER_SIZE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) -#else -#define SET_TX_DESC_TX_DESC_CHECKSUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) -#endif -#define SET_TX_DESC_USB_TXAGG_NUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) -#if (DEV_BUS_TYPE == RT_SDIO_INTERFACE) -#define SET_TX_DESC_SDIO_TXSEQ_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value) -#endif - -/* Dword 8 */ -#define SET_TX_DESC_HWSEQ_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) - -/* Dword 9 */ -#define SET_TX_DESC_SEQ_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value) - -/* Dword 10 */ -#define SET_TX_DESC_TX_BUFFER_ADDRESS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value) -#define GET_TX_DESC_TX_BUFFER_ADDRESS_8188F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32) - -/* Dword 11 */ -#define SET_TX_DESC_NEXT_DESC_ADDRESS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value) - - -#define SET_EARLYMODE_PKTNUM_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value) -#define SET_EARLYMODE_LEN0_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value) -#define SET_EARLYMODE_LEN1_1_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value) -#define SET_EARLYMODE_LEN1_2_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value) -#define SET_EARLYMODE_LEN2_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value) -#define SET_EARLYMODE_LEN3_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value) - -#endif -/* ----------------------------------------------------------- - * - * Rate - * - * ----------------------------------------------------------- - * CCK Rates, TxHT = 0 */ -#define DESC8188F_RATE1M 0x00 -#define DESC8188F_RATE2M 0x01 -#define DESC8188F_RATE5_5M 0x02 -#define DESC8188F_RATE11M 0x03 - -/* OFDM Rates, TxHT = 0 */ -#define DESC8188F_RATE6M 0x04 -#define DESC8188F_RATE9M 0x05 -#define DESC8188F_RATE12M 0x06 -#define DESC8188F_RATE18M 0x07 -#define DESC8188F_RATE24M 0x08 -#define DESC8188F_RATE36M 0x09 -#define DESC8188F_RATE48M 0x0a -#define DESC8188F_RATE54M 0x0b - -/* MCS Rates, TxHT = 1 */ -#define DESC8188F_RATEMCS0 0x0c -#define DESC8188F_RATEMCS1 0x0d -#define DESC8188F_RATEMCS2 0x0e -#define DESC8188F_RATEMCS3 0x0f -#define DESC8188F_RATEMCS4 0x10 -#define DESC8188F_RATEMCS5 0x11 -#define DESC8188F_RATEMCS6 0x12 -#define DESC8188F_RATEMCS7 0x13 -#define DESC8188F_RATEMCS8 0x14 -#define DESC8188F_RATEMCS9 0x15 -#define DESC8188F_RATEMCS10 0x16 -#define DESC8188F_RATEMCS11 0x17 -#define DESC8188F_RATEMCS12 0x18 -#define DESC8188F_RATEMCS13 0x19 -#define DESC8188F_RATEMCS14 0x1a -#define DESC8188F_RATEMCS15 0x1b -#define DESC8188F_RATEVHTSS1MCS0 0x2c -#define DESC8188F_RATEVHTSS1MCS1 0x2d -#define DESC8188F_RATEVHTSS1MCS2 0x2e -#define DESC8188F_RATEVHTSS1MCS3 0x2f -#define DESC8188F_RATEVHTSS1MCS4 0x30 -#define DESC8188F_RATEVHTSS1MCS5 0x31 -#define DESC8188F_RATEVHTSS1MCS6 0x32 -#define DESC8188F_RATEVHTSS1MCS7 0x33 -#define DESC8188F_RATEVHTSS1MCS8 0x34 -#define DESC8188F_RATEVHTSS1MCS9 0x35 -#define DESC8188F_RATEVHTSS2MCS0 0x36 -#define DESC8188F_RATEVHTSS2MCS1 0x37 -#define DESC8188F_RATEVHTSS2MCS2 0x38 -#define DESC8188F_RATEVHTSS2MCS3 0x39 -#define DESC8188F_RATEVHTSS2MCS4 0x3a -#define DESC8188F_RATEVHTSS2MCS5 0x3b -#define DESC8188F_RATEVHTSS2MCS6 0x3c -#define DESC8188F_RATEVHTSS2MCS7 0x3d -#define DESC8188F_RATEVHTSS2MCS8 0x3e -#define DESC8188F_RATEVHTSS2MCS9 0x3f - - -#define RX_HAL_IS_CCK_RATE_8188F(pDesc)\ - (GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE1M || \ - GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE2M || \ - GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE5_5M || \ - GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE11M) - - -void rtl8188f_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem); -void rtl8188f_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); -#if defined(CONFIG_CONCURRENT_MODE) -void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); -#endif - -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) -s32 rtl8188fs_init_xmit_priv(PADAPTER padapter); -void rtl8188fs_free_xmit_priv(PADAPTER padapter); -s32 rtl8188fs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); -s32 rtl8188fs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); -s32 rtl8188fs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); -s32 rtl8188fs_xmit_buf_handler(PADAPTER padapter); -thread_return rtl8188fs_xmit_thread(thread_context context); -#define hal_xmit_handler rtl8188fs_xmit_buf_handler -#endif - -#ifdef CONFIG_USB_HCI -s32 rtl8188fu_xmit_buf_handler(PADAPTER padapter); -#define hal_xmit_handler rtl8188fu_xmit_buf_handler - - -s32 rtl8188fu_init_xmit_priv(PADAPTER padapter); -void rtl8188fu_free_xmit_priv(PADAPTER padapter); -s32 rtl8188fu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); -s32 rtl8188fu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); -s32 rtl8188fu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); -/* s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); */ -void rtl8188fu_xmit_tasklet(void *priv); -s32 rtl8188fu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); -void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, struct tx_desc *ptxdesc); -#endif - -#ifdef CONFIG_PCI_HCI -s32 rtl8188fe_init_xmit_priv(PADAPTER padapter); -void rtl8188fe_free_xmit_priv(PADAPTER padapter); -struct xmit_buf *rtl8188fe_dequeue_xmitbuf(struct rtw_tx_ring *ring); -void rtl8188fe_xmitframe_resume(_adapter *padapter); -s32 rtl8188fe_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); -s32 rtl8188fe_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); -s32 rtl8188fe_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); -void rtl8188fe_xmit_tasklet(void *priv); -#endif - -u8 BWMapping_8188F(PADAPTER Adapter, struct pkt_attrib *pattrib); -u8 SCMapping_8188F(PADAPTER Adapter, struct pkt_attrib *pattrib); - -#endif diff --git a/include/rtl8192e_cmd.h b/include/rtl8192e_cmd.h deleted file mode 100644 index 78d476b..0000000 --- a/include/rtl8192e_cmd.h +++ /dev/null @@ -1,161 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8192E_CMD_H__ -#define __RTL8192E_CMD_H__ - -typedef enum _RTL8192E_H2C_CMD { - H2C_8192E_RSVDPAGE = 0x00, - H2C_8192E_MSRRPT = 0x01, - H2C_8192E_SCAN = 0x02, - H2C_8192E_KEEP_ALIVE_CTRL = 0x03, - H2C_8192E_DISCONNECT_DECISION = 0x04, - H2C_8192E_INIT_OFFLOAD = 0x06, - H2C_8192E_AP_OFFLOAD = 0x08, - H2C_8192E_BCN_RSVDPAGE = 0x09, - H2C_8192E_PROBERSP_RSVDPAGE = 0x0a, - - H2C_8192E_AP_WOW_GPIO_CTRL = 0x13, - - H2C_8192E_SETPWRMODE = 0x20, - H2C_8192E_PS_TUNING_PARA = 0x21, - H2C_8192E_PS_TUNING_PARA2 = 0x22, - H2C_8192E_PS_LPS_PARA = 0x23, - H2C_8192E_P2P_PS_OFFLOAD = 0x24, - H2C_8192E_SAP_PS = 0x26, - H2C_8192E_RA_MASK = 0x40, - H2C_8192E_RSSI_REPORT = 0x42, - H2C_8192E_RA_PARA_ADJUST = 0x46, - - H2C_8192E_WO_WLAN = 0x80, - H2C_8192E_REMOTE_WAKE_CTRL = 0x81, - H2C_8192E_AOAC_GLOBAL_INFO = 0x82, - H2C_8192E_AOAC_RSVDPAGE = 0x83, - - /* Not defined in new 88E H2C CMD Format */ - H2C_8192E_SELECTIVE_SUSPEND_ROF_CMD, - H2C_8192E_P2P_PS_MODE, - H2C_8192E_PSD_RESULT, - MAX_8192E_H2CCMD -} RTL8192E_H2C_CMD; - -struct cmd_msg_parm { - u8 eid; /* element id */ - u8 sz; /* sz */ - u8 buf[6]; -}; - -enum { - PWRS -}; - -typedef struct _SETPWRMODE_PARM { - u8 Mode;/* 0:Active,1:LPS,2:WMMPS */ - /* u8 RLBM:4; */ /* 0:Min,1:Max,2: User define */ - u8 SmartPS_RLBM;/* LPS=0:PS_Poll,1:PS_Poll,2:NullData,WMM=0:PS_Poll,1:NullData */ - u8 AwakeInterval; /* unit: beacon interval */ - u8 bAllQueueUAPSD; - u8 PwrState;/* AllON(0x0c),RFON(0x04),RFOFF(0x00) */ -} SETPWRMODE_PARM, *PSETPWRMODE_PARM; - -struct H2C_SS_RFOFF_PARAM { - u8 ROFOn; /* 1: on, 0:off */ - u16 gpio_period; /* unit: 1024 us */ -} __attribute__((packed)); - - -typedef struct JOINBSSRPT_PARM_92E { - u8 OpMode; /* RT_MEDIA_STATUS */ -#ifdef CONFIG_WOWLAN - u8 MacID; /* MACID */ -#endif /* CONFIG_WOWLAN */ -} JOINBSSRPT_PARM_92E, *PJOINBSSRPT_PARM_92E; - -/* move to hal_com_h2c.h -typedef struct _RSVDPAGE_LOC_92E { - u8 LocProbeRsp; - u8 LocPsPoll; - u8 LocNullData; - u8 LocQosNull; - u8 LocBTQosNull; -} RSVDPAGE_LOC_92E, *PRSVDPAGE_LOC_92E; -*/ - - -/* _SETPWRMODE_PARM */ -#define SET_8192E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8192E_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value) -#define SET_8192E_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value) -#define SET_8192E_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) -#define SET_8192E_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) -#define SET_8192E_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value) -#define SET_8192E_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) -#define SET_8192E_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) -#define GET_8192E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8) - -/* _P2P_PS_OFFLOAD */ -#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) -#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) -#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_CTWINDOW_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) -#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_NOA0_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value) -#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_NOA1_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value) -#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value) - - -/* host message to firmware cmd */ -void rtl8192e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); -void rtl8192e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus); -u8 rtl8192e_set_rssi_cmd(PADAPTER padapter, u8 *param); -void rtl8192e_set_raid_cmd(PADAPTER padapter, u32 bitmap, u8 *arg, u8 bw); -s32 FillH2CCmd_8192E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); -u8 GetTxBufferRsvdPageNum8192E(_adapter *padapter, bool wowlan); -/* u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period); */ -s32 c2h_handler_8192e(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload); -#ifdef CONFIG_BT_COEXIST - void rtl8192e_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter); -#endif /* CONFIG_BT_COEXIST */ -#ifdef CONFIG_P2P_PS - void rtl8192e_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); -#endif /* CONFIG_P2P */ - -void CheckFwRsvdPageContent(PADAPTER padapter); - -#ifdef CONFIG_TDLS - #ifdef CONFIG_TDLS_CH_SW - void rtl8192e_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); - #endif -#endif - -#ifdef CONFIG_TSF_RESET_OFFLOAD - int reset_tsf(PADAPTER Adapter, u8 reset_port); -#endif /* CONFIG_TSF_RESET_OFFLOAD */ - -/* / TX Feedback Content */ -#define USEC_UNIT_FOR_8192E_C2H_TX_RPT_QUEUE_TIME 256 - -#define GET_8192E_C2H_TX_RPT_QUEUE_SELECT(_Header) LE_BITS_TO_1BYTE((_Header + 0), 0, 5) -#define GET_8192E_C2H_TX_RPT_PKT_BROCAST(_Header) LE_BITS_TO_1BYTE((_Header + 0), 5, 1) -#define GET_8192E_C2H_TX_RPT_LIFE_TIME_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 6, 1) -#define GET_8192E_C2H_TX_RPT_RETRY_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 7, 1) -#define GET_8192E_C2H_TX_RPT_MAC_ID(_Header) LE_BITS_TO_1BYTE((_Header + 1), 0, 8) -#define GET_8192E_C2H_TX_RPT_DATA_RETRY_CNT(_Header) LE_BITS_TO_1BYTE((_Header + 2), 0, 6) -#define GET_8192E_C2H_TX_RPT_QUEUE_TIME(_Header) LE_BITS_TO_2BYTE((_Header + 3), 0, 16) /* In unit of 256 microseconds. */ -#define GET_8192E_C2H_TX_RPT_FINAL_DATA_RATE(_Header) LE_BITS_TO_1BYTE((_Header + 5), 0, 8) - -#endif /* __RTL8192E_CMD_H__ */ diff --git a/include/rtl8192e_dm.h b/include/rtl8192e_dm.h deleted file mode 100644 index ff1b341..0000000 --- a/include/rtl8192e_dm.h +++ /dev/null @@ -1,33 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8192E_DM_H__ -#define __RTL8192E_DM_H__ - - -void rtl8192e_init_dm_priv(IN PADAPTER Adapter); -void rtl8192e_deinit_dm_priv(IN PADAPTER Adapter); -void rtl8192e_InitHalDm(IN PADAPTER Adapter); -void rtl8192e_HalDmWatchDog(IN PADAPTER Adapter); - -/* VOID rtl8192c_dm_CheckTXPowerTracking(IN PADAPTER Adapter); */ - -/* void rtl8192c_dm_RF_Saving(IN PADAPTER pAdapter, IN u8 bForceInNormal); */ - -#endif diff --git a/include/rtl8192e_hal.h b/include/rtl8192e_hal.h deleted file mode 100644 index dc64a2b..0000000 --- a/include/rtl8192e_hal.h +++ /dev/null @@ -1,332 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8192E_HAL_H__ -#define __RTL8192E_HAL_H__ - -/* #include "hal_com.h" */ - -#include "hal_data.h" - -/* include HAL Related header after HAL Related compiling flags */ -#include "rtl8192e_spec.h" -#include "rtl8192e_rf.h" -#include "rtl8192e_dm.h" -#include "rtl8192e_recv.h" -#include "rtl8192e_xmit.h" -#include "rtl8192e_cmd.h" -#include "rtl8192e_led.h" -#include "Hal8192EPwrSeq.h" -#include "Hal8192EPhyReg.h" -#include "Hal8192EPhyCfg.h" - - -#ifdef DBG_CONFIG_ERROR_DETECT - #include "rtl8192e_sreset.h" -#endif - -/* --------------------------------------------------------------------- - * RTL8192E Power Configuration CMDs for PCIe interface - * --------------------------------------------------------------------- */ -#define Rtl8192E_NIC_PWR_ON_FLOW rtl8192E_power_on_flow -#define Rtl8192E_NIC_RF_OFF_FLOW rtl8192E_radio_off_flow -#define Rtl8192E_NIC_DISABLE_FLOW rtl8192E_card_disable_flow -#define Rtl8192E_NIC_ENABLE_FLOW rtl8192E_card_enable_flow -#define Rtl8192E_NIC_SUSPEND_FLOW rtl8192E_suspend_flow -#define Rtl8192E_NIC_RESUME_FLOW rtl8192E_resume_flow -#define Rtl8192E_NIC_PDN_FLOW rtl8192E_hwpdn_flow -#define Rtl8192E_NIC_LPS_ENTER_FLOW rtl8192E_enter_lps_flow -#define Rtl8192E_NIC_LPS_LEAVE_FLOW rtl8192E_leave_lps_flow - - -#if 1 /* download firmware related data structure */ -#define FW_SIZE_8192E 0x8000 /* Compatible with RTL8192e Maximal RAM code size 32k */ -#define FW_START_ADDRESS 0x1000 -#define FW_END_ADDRESS 0x5FFF - - -#define IS_FW_HEADER_EXIST_8192E(_pFwHdr) ((GET_FIRMWARE_HDR_SIGNATURE_8192E(_pFwHdr) & 0xFFF0) == 0x92E0) - - - -typedef struct _RT_FIRMWARE_8192E { - FIRMWARE_SOURCE eFWSource; -#ifdef CONFIG_EMBEDDED_FWIMG - u8 *szFwBuffer; -#else - u8 szFwBuffer[FW_SIZE_8192E]; -#endif - u32 ulFwLength; -} RT_FIRMWARE_8192E, *PRT_FIRMWARE_8192E; - -/* - * This structure must be cared byte-ordering - * - * Added by tynli. 2009.12.04. */ - -/* ***************************************************** - * Firmware Header(8-byte alinment required) - * ***************************************************** - * --- LONG WORD 0 ---- */ -#define GET_FIRMWARE_HDR_SIGNATURE_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 0, 16) /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */ -#define GET_FIRMWARE_HDR_CATEGORY_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 16, 8) /* AP/NIC and USB/PCI */ -#define GET_FIRMWARE_HDR_FUNCTION_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 24, 8) /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */ -#define GET_FIRMWARE_HDR_VERSION_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 0, 16)/* FW Version */ -#define GET_FIRMWARE_HDR_SUB_VER_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 16, 8) /* FW Subversion, default 0x00 */ -#define GET_FIRMWARE_HDR_RSVD1_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 24, 8) - -/* --- LONG WORD 1 ---- */ -#define GET_FIRMWARE_HDR_MONTH_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 0, 8) /* Release time Month field */ -#define GET_FIRMWARE_HDR_DATE_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 8, 8) /* Release time Date field */ -#define GET_FIRMWARE_HDR_HOUR_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 16, 8)/* Release time Hour field */ -#define GET_FIRMWARE_HDR_MINUTE_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 24, 8)/* Release time Minute field */ -#define GET_FIRMWARE_HDR_ROMCODE_SIZE_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+12, 0, 16)/* The size of RAM code */ -#define GET_FIRMWARE_HDR_RSVD2_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+12, 16, 16) - -/* --- LONG WORD 2 ---- */ -#define GET_FIRMWARE_HDR_SVN_IDX_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+16, 0, 32)/* The SVN entry index */ -#define GET_FIRMWARE_HDR_RSVD3_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+20, 0, 32) - -/* --- LONG WORD 3 ---- */ -#define GET_FIRMWARE_HDR_RSVD4_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 0, 32) -#define GET_FIRMWARE_HDR_RSVD5_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+28, 0, 32) - -#endif /* download firmware related data structure */ - -#define DRIVER_EARLY_INT_TIME_8192E 0x05 -#define BCN_DMA_ATIME_INT_TIME_8192E 0x02 -#define RX_DMA_SIZE_8192E 0x4000 /* 16K*/ - -#ifdef CONFIG_WOWLAN - #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/ -#else - #define RESV_FMWF 0 -#endif - -#ifdef CONFIG_FW_C2H_DEBUG - #define RX_DMA_RESERVED_SIZE_8192E 0x100 /* 256B, reserved for c2h debug message*/ -#else - #define RX_DMA_RESERVED_SIZE_8192E 0x40 /* 64B, reserved for c2h event(16bytes) or ccx(8 Bytes)*/ -#endif -#define MAX_RX_DMA_BUFFER_SIZE_8192E (RX_DMA_SIZE_8192E-RX_DMA_RESERVED_SIZE_8192E) /*RX 16K*/ - -/* For General Reserved Page Number(Beacon Queue is reserved page) - * if (CONFIG_2BCN_EN) Beacon:4, PS-Poll:1, Null Data:1,Prob Rsp:1,Qos Null Data:1 - * Beacon:2, PS-Poll:1, Null Data:1,Prob Rsp:1,Qos Null Data:1 */ -#define RSVD_PAGE_NUM_8192E 0x08 -/* For WoWLan , more reserved page - * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1,PNO: 6 */ -#ifdef CONFIG_WOWLAN - #define WOWLAN_PAGE_NUM_8192E 0x08 -#else - #define WOWLAN_PAGE_NUM_8192E 0x00 -#endif - -#ifdef CONFIG_PNO_SUPPORT - #undef WOWLAN_PAGE_NUM_8192E - #define WOWLAN_PAGE_NUM_8192E 0x0d -#endif - -/* Note: -Tx FIFO Size : 64KB -Tx page Size : 256B -Total page numbers : 256(0x100) -*/ - -#define TOTAL_RSVD_PAGE_NUMBER_8192E (RSVD_PAGE_NUM_8192E + WOWLAN_PAGE_NUM_8192E) - -#define TOTAL_PAGE_NUMBER_8192E (0x100) -#define TX_TOTAL_PAGE_NUMBER_8192E (TOTAL_PAGE_NUMBER_8192E - TOTAL_RSVD_PAGE_NUMBER_8192E) - -#define TX_PAGE_BOUNDARY_8192E (TX_TOTAL_PAGE_NUMBER_8192E) /* beacon header start address */ - - -#define PAGE_SIZE_TX_92E PAGE_SIZE_256 -#define RSVD_PKT_LEN_92E (TOTAL_RSVD_PAGE_NUMBER_8192E * PAGE_SIZE_TX_92E) - -#define TX_PAGE_LOAD_FW_BOUNDARY_8192E 0x47 /* 0xA5 */ -#define TX_PAGE_BOUNDARY_WOWLAN_8192E 0xE0 - -/* For Normal Chip Setting - * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_92C */ - -#define NORMAL_PAGE_NUM_HPQ_8192E 0x10 -#define NORMAL_PAGE_NUM_LPQ_8192E 0x10 -#define NORMAL_PAGE_NUM_NPQ_8192E 0x10 -#define NORMAL_PAGE_NUM_EPQ_8192E 0x00 - - -/* Note: For WMM Normal Chip Setting ,modify later */ -#define WMM_NORMAL_PAGE_NUM_HPQ_8192E NORMAL_PAGE_NUM_HPQ_8192E -#define WMM_NORMAL_PAGE_NUM_LPQ_8192E NORMAL_PAGE_NUM_LPQ_8192E -#define WMM_NORMAL_PAGE_NUM_NPQ_8192E NORMAL_PAGE_NUM_NPQ_8192E - - -/* ------------------------------------------------------------------------- - * Chip specific - * ------------------------------------------------------------------------- */ - -/* pic buffer descriptor */ -#define RTL8192EE_SEG_NUM TX_BUFFER_SEG_NUM -#define TX_DESC_NUM_92E 128 -#define RX_DESC_NUM_92E 128 - -/* ------------------------------------------------------------------------- - * Channel Plan - * ------------------------------------------------------------------------- */ - -#define HWSET_MAX_SIZE_8192E 512 - -#define EFUSE_REAL_CONTENT_LEN_8192E 512 - -#define EFUSE_MAP_LEN_8192E 512 -#define EFUSE_MAX_SECTION_8192E 64 -#define EFUSE_MAX_WORD_UNIT_8192E 4 -#define EFUSE_IC_ID_OFFSET_8192E 506 /* For some inferiority IC purpose. added by Roger, 2009.09.02. */ -#define AVAILABLE_EFUSE_ADDR_8192E(addr) (addr < EFUSE_REAL_CONTENT_LEN_8192E) -/* - * To prevent out of boundary programming case, leave 1byte and program full section - * 9bytes + 1byt + 5bytes and pre 1byte. - * For worst case: - * | 1byte|----8bytes----|1byte|--5bytes--| - * | | Reserved(14bytes) | - * */ -#define EFUSE_OOB_PROTECT_BYTES_8192E 15 /* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */ - - - -/* ******************************************************** - * EFUSE for BT definition - * ******************************************************** */ -#define EFUSE_BT_REAL_BANK_CONTENT_LEN_8192E 512 -#define EFUSE_BT_REAL_CONTENT_LEN_8192E 1024 /* 512*2 */ -#define EFUSE_BT_MAP_LEN_8192E 1024 /* 1k bytes */ -#define EFUSE_BT_MAX_SECTION_8192E 128 /* 1024/8 */ - -#define EFUSE_PROTECT_BYTES_BANK_8192E 16 -#define EFUSE_MAX_BANK_8192E 3 -/* *********************************************************** */ - -#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT) -#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) - -/* #define IS_MULTI_FUNC_CHIP(_Adapter) (((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) */ - -/* #define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) */ - -/* rtl8812_hal_init.c */ -void _8051Reset8192E(PADAPTER padapter); -s32 FirmwareDownload8192E(PADAPTER Adapter, BOOLEAN bUsedWoWLANFw); -void InitializeFirmwareVars8192E(PADAPTER padapter); - -s32 InitLLTTable8192E(PADAPTER padapter, u8 txpktbuf_bndy); - -/* EFuse */ -u8 GetEEPROMSize8192E(PADAPTER padapter); -void hal_InitPGData_8192E(PADAPTER padapter, u8 *PROMContent); -void Hal_EfuseParseIDCode8192E(PADAPTER padapter, u8 *hwinfo); -void Hal_ReadPROMVersion8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_ReadPowerSavingMode8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_ReadTxPowerInfo8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_ReadBoardType8192E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_ReadThermalMeter_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); -void Hal_ReadChannelPlan8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParseXtal_8192E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_ReadAntennaDiversity8192E(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail); -void Hal_ReadPAType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); -void Hal_ReadAmplifierType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); -void Hal_ReadRFEType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); -void Hal_EfuseParseBTCoexistInfo8192E(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParseKFreeData_8192E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); - -u8 Hal_CrystalAFEAdjust(_adapter *Adapter); - -BOOLEAN HalDetectPwrDownMode8192E(PADAPTER Adapter); - -#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) - void Hal_DetectWoWMode(PADAPTER pAdapter); -#endif /* CONFIG_WOWLAN */ - -/***********************************************************/ -/* RTL8192E-MAC Setting */ -VOID _InitQueueReservedPage_8192E(IN PADAPTER Adapter); -VOID _InitQueuePriority_8192E(IN PADAPTER Adapter); -VOID _InitTxBufferBoundary_8192E(IN PADAPTER Adapter, IN u8 txpktbuf_bndy); -VOID _InitPageBoundary_8192E(IN PADAPTER Adapter); -/* VOID _InitTransferPageSize_8192E(IN PADAPTER Adapter); */ -VOID _InitDriverInfoSize_8192E(IN PADAPTER Adapter, IN u8 drvInfoSize); -VOID _InitRDGSetting_8192E(PADAPTER Adapter); -void _InitID_8192E(IN PADAPTER Adapter); -VOID _InitNetworkType_8192E(IN PADAPTER Adapter); -VOID _InitWMACSetting_8192E(IN PADAPTER Adapter); -VOID _InitAdaptiveCtrl_8192E(IN PADAPTER Adapter); -VOID _InitRateFallback_8192E(IN PADAPTER Adapter); -VOID _InitEDCA_8192E(IN PADAPTER Adapter); -VOID _InitRetryFunction_8192E(IN PADAPTER Adapter); -VOID _BBTurnOnBlock_8192E(IN PADAPTER Adapter); -VOID _InitBeaconParameters_8192E(IN PADAPTER Adapter); -VOID _InitBeaconMaxError_8192E( - IN PADAPTER Adapter, - IN BOOLEAN InfraMode -); -void SetBeaconRelatedRegisters8192E(PADAPTER padapter); -VOID hal_ReadRFType_8192E(PADAPTER Adapter); -/* RTL8192E-MAC Setting - ***********************************************************/ - -void SetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val); -void GetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val); -u8 -SetHalDefVar8192E( - IN PADAPTER Adapter, - IN HAL_DEF_VARIABLE eVariable, - IN PVOID pValue -); -u8 -GetHalDefVar8192E( - IN PADAPTER Adapter, - IN HAL_DEF_VARIABLE eVariable, - IN PVOID pValue -); - -void rtl8192e_set_hal_ops(struct hal_ops *pHalFunc); -void init_hal_spec_8192e(_adapter *adapter); -void rtl8192e_init_default_value(_adapter *padapter); -/* register */ -void SetBcnCtrlReg(PADAPTER padapter, u8 SetBits, u8 ClearBits); - -void rtl8192e_start_thread(_adapter *padapter); -void rtl8192e_stop_thread(_adapter *padapter); - -#ifdef CONFIG_PCI_HCI - BOOLEAN InterruptRecognized8192EE(PADAPTER Adapter); - u16 get_txdesc_buf_addr(u16 ff_hwaddr); -#endif - -#ifdef CONFIG_SDIO_HCI - #ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT - void _init_available_page_threshold(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ); - #endif -#endif - -#ifdef CONFIG_BT_COEXIST - void rtl8192e_combo_card_WifiOnlyHwInit(PADAPTER Adapter); -#endif - -#endif /* __RTL8192E_HAL_H__ */ diff --git a/include/rtl8192e_led.h b/include/rtl8192e_led.h deleted file mode 100644 index d79bd91..0000000 --- a/include/rtl8192e_led.h +++ /dev/null @@ -1,40 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8192E_LED_H__ -#define __RTL8192E_LED_H__ - - -/* ******************************************************************************** - * Interface to manipulate LED objects. - * ******************************************************************************** */ -#ifdef CONFIG_USB_HCI - void rtl8192eu_InitSwLeds(PADAPTER padapter); - void rtl8192eu_DeInitSwLeds(PADAPTER padapter); -#endif -#ifdef CONFIG_PCI_HCI - void rtl8192ee_InitSwLeds(PADAPTER padapter); - void rtl8192ee_DeInitSwLeds(PADAPTER padapter); -#endif -#ifdef CONFIG_SDIO_HCI - void rtl8192es_InitSwLeds(PADAPTER padapter); - void rtl8192es_DeInitSwLeds(PADAPTER padapter); -#endif - -#endif diff --git a/include/rtl8192e_recv.h b/include/rtl8192e_recv.h deleted file mode 100644 index 2d157ab..0000000 --- a/include/rtl8192e_recv.h +++ /dev/null @@ -1,169 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8192E_RECV_H__ -#define __RTL8192E_RECV_H__ - -#if defined(CONFIG_USB_HCI) - - #ifndef MAX_RECVBUF_SZ - #ifdef CONFIG_MINIMAL_MEMORY_USAGE - #define MAX_RECVBUF_SZ (4000) /* about 4K */ - #else - #ifdef CONFIG_PREALLOC_RX_SKB_BUFFER - #define MAX_RECVBUF_SZ (rtw_rtkm_get_buff_size()) /*depend rtkm*/ - #elif defined(CONFIG_PLATFORM_HISILICON) - #define MAX_RECVBUF_SZ (16384) /* 16k */ - #else - #define MAX_RECVBUF_SZ (32768) /* 32k */ - #endif - /* #define MAX_RECVBUF_SZ (20480) */ /* 20K */ - /* #define MAX_RECVBUF_SZ (10240) */ /* 10K */ - /* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */ - /* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */ - #endif - #endif /* !MAX_RECVBUF_SZ */ - -#elif defined(CONFIG_PCI_HCI) - /* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */ - /* #define MAX_RECVBUF_SZ (9100) */ - /* #else */ - #define MAX_RECVBUF_SZ (4000) /* about 4K - * #endif */ - - -#elif defined(CONFIG_SDIO_HCI) - - #define MAX_RECVBUF_SZ (16384) - -#endif - - -/* Rx smooth factor */ -#define Rx_Smooth_Factor (20) - -/* ************* - * [1] Rx Buffer Descriptor (for PCIE) buffer descriptor architecture - * DWORD 0 */ -#define SET_RX_BUFFER_DESC_DATA_LENGTH_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value) -#define SET_RX_BUFFER_DESC_LS_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value) -#define SET_RX_BUFFER_DESC_FS_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value) -#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value) - -#define GET_RX_BUFFER_DESC_OWN_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1) -#define GET_RX_BUFFER_DESC_LS_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1) -#define GET_RX_BUFFER_DESC_FS_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1) -#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15) - - -/* DWORD 1 */ -#define SET_RX_BUFFER_PHYSICAL_LOW_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value) -#define GET_RX_BUFFER_PHYSICAL_LOW_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 0, 32) - -/* DWORD 2 */ -#define SET_RX_BUFFER_PHYSICAL_HIGH_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value) - -/* ************* - * [2] Rx Descriptor - * DWORD 0 */ -#define GET_RX_STATUS_DESC_PKT_LEN_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14) -#define GET_RX_STATUS_DESC_CRC32_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1) -#define GET_RX_STATUS_DESC_ICVERR_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1) -#define GET_RX_STATUS_DESC_DRVINFO_SIZE_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4) -#define GET_RX_STATUS_DESC_SECURITY_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3) -#define GET_RX_STATUS_DESC_QOS_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1) -#define GET_RX_STATUS_DESC_SHIFT_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2) -#define GET_RX_STATUS_DESC_PHY_STATUS_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1) -#define GET_RX_STATUS_DESC_SWDEC_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1) -#define GET_RX_STATUS_DESC_EOR_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1) -#define GET_RX_STATUS_DESC_OWN_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1) - - -#define SET_RX_STATUS_DESC_PKT_LEN_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value) -#define SET_RX_STATUS_DESC_EOR_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value) -#define SET_RX_STATUS_DESC_OWN_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value) - -/* DWORD 1 */ -#define GET_RX_STATUS_DESC_MACID_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7) -#define GET_RX_STATUS_DESC_TID_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4) -#define GET_RX_STATUS_DESC_MACID_VLD_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 12, 1) -#define GET_RX_STATUS_DESC_AMSDU_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1) -#define GET_RX_STATUS_DESC_RXID_MATCH_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1) -#define GET_RX_STATUS_DESC_PAGGR_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 15, 1) -#define GET_RX_STATUS_DESC_A1_FITS_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 16, 4) -#define GET_RX_STATUS_DESC_TCPOFFLOAD_CHKERR_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 20, 1) -#define GET_RX_STATUS_DESC_TCPOFFLOAD_IPVER_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 21, 1) -#define GET_RX_STATUS_DESC_TCPOFFLOAD_IS_TCPUDP_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 22, 1) -#define GET_RX_STATUS_DESC_TCPOFFLOAD_CHK_VLD_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 23, 1) -#define GET_RX_STATUS_DESC_PAM_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 24, 1) -#define GET_RX_STATUS_DESC_PWR_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 25, 1) -#define GET_RX_STATUS_DESC_MORE_DATA_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 26, 1) -#define GET_RX_STATUS_DESC_MORE_FRAG_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 27, 1) -#define GET_RX_STATUS_DESC_TYPE_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 28, 2) -#define GET_RX_STATUS_DESC_MC_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 30, 1) -#define GET_RX_STATUS_DESC_BC_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 31, 1) - -/* DWORD 2 */ -#define GET_RX_STATUS_DESC_SEQ_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12) -#define GET_RX_STATUS_DESC_FRAG_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4) -#define GET_RX_STATUS_DESC_RX_IS_QOS_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1) - -#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6) -#define GET_RX_STATUS_DESC_HWRSVD_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 24, 4) -#define GET_RX_STATUS_DESC_FCS_OK_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1) -#define GET_RX_STATUS_DESC_RPT_SEL_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1) - -/* DWORD 3 */ -#define GET_RX_STATUS_DESC_RX_RATE_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7) -#define GET_RX_STATUS_DESC_HTC_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1) -#define GET_RX_STATUS_DESC_EOSP_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1) -#define GET_RX_STATUS_DESC_BSSID_FIT_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2) -#define GET_RX_STATUS_DESC_DMA_AGG_NUM_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8) - -#define GET_RX_STATUS_DESC_PATTERN_MATCH_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1) -#define GET_RX_STATUS_DESC_UNICAST_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1) -#define GET_RX_STATUS_DESC_MAGIC_WAKE_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1) - - -/* DWORD 5 */ -#define GET_RX_STATUS_DESC_TSFL_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32) - -#define GET_RX_STATUS_DESC_BUFF_ADDR_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32) -#define GET_RX_STATUS_DESC_BUFF_ADDR64_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32) - - -#ifdef CONFIG_SDIO_HCI - s32 rtl8192es_init_recv_priv(PADAPTER padapter); - void rtl8192es_free_recv_priv(PADAPTER padapter); -#endif - -#ifdef CONFIG_USB_HCI - void rtl8192eu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf); - s32 rtl8192eu_init_recv_priv(PADAPTER padapter); - void rtl8192eu_free_recv_priv(PADAPTER padapter); -#endif - -#ifdef CONFIG_PCI_HCI - s32 rtl8192ee_init_recv_priv(PADAPTER padapter); - void rtl8192ee_free_recv_priv(PADAPTER padapter); -#endif - -void rtl8192e_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc); - -#endif /* __RTL8192E_RECV_H__ */ diff --git a/include/rtl8192e_rf.h b/include/rtl8192e_rf.h deleted file mode 100644 index cd344a4..0000000 --- a/include/rtl8192e_rf.h +++ /dev/null @@ -1,33 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8192E_RF_H__ -#define __RTL8192E_RF_H__ - -VOID -PHY_RF6052SetBandwidth8192E( - IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth); - - -int -PHY_RF6052_Config_8192E( - IN PADAPTER Adapter); - -#endif/* __RTL8192E_RF_H__ */ diff --git a/include/rtl8192e_spec.h b/include/rtl8192e_spec.h deleted file mode 100644 index 8a5c5f8..0000000 --- a/include/rtl8192e_spec.h +++ /dev/null @@ -1,317 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ -#ifndef __RTL8192E_SPEC_H__ -#define __RTL8192E_SPEC_H__ - -#include - -#define HAL_NAV_UPPER_UNIT_8192E 128 /* micro-second */ - -/* ************************************************************ - * 8192E Regsiter offset definition - * ************************************************************ */ - -/* ************************************************************ - * - * ************************************************************ */ - -/* ----------------------------------------------------- - * - * 0x0000h ~ 0x00FFh System Configuration - * - * ----------------------------------------------------- */ -#define REG_SYS_SWR_CTRL1_8192E 0x0010 /* 1 Byte */ -#define REG_SYS_SWR_CTRL2_8192E 0x0014 /* 1 Byte */ -#define REG_AFE_CTRL1_8192E 0x0024 -#define REG_AFE_CTRL2_8192E 0x0028 -#define REG_AFE_CTRL3_8192E 0x002c - -#define REG_PAD_CTRL1_8192E 0x0064 -#define REG_SDIO_CTRL_8192E 0x0070 -#define REG_OPT_CTRL_8192E 0x0074 -#define REG_RF_B_CTRL_8192E 0x0076 -#define REG_AFE_CTRL4_8192E 0x0078 -#define REG_LDO_SWR_CTRL 0x007C -#define REG_FW_DRV_MSG_8192E 0x0088 -#define REG_HMEBOX_E2_E3_8192E 0x008C -#define REG_HIMR0_8192E 0x00B0 -#define REG_HISR0_8192E 0x00B4 -#define REG_HIMR1_8192E 0x00B8 -#define REG_HISR1_8192E 0x00BC - -#define REG_SYS_CFG1_8192E 0x00F0 -#define REG_SYS_CFG2_8192E 0x00FC -/* ----------------------------------------------------- - * - * 0x0100h ~ 0x01FFh MACTOP General Configuration - * - * ----------------------------------------------------- */ -#define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL) -#define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2) -#define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3) -#define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN - -#define REG_RSVD3_8192E 0x0168 -#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 -#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 -#define REG_C2HEVT_CMD_LEN_88XX 0x01AE - -#define REG_HMEBOX_EXT0_8192E 0x01F0 -#define REG_HMEBOX_EXT1_8192E 0x01F4 -#define REG_HMEBOX_EXT2_8192E 0x01F8 -#define REG_HMEBOX_EXT3_8192E 0x01FC - -/* ----------------------------------------------------- - * - * 0x0200h ~ 0x027Fh TXDMA Configuration - * - * ----------------------------------------------------- */ -#define REG_DWBCN0_CTRL 0x0208 -#define REG_DWBCN1_CTRL 0x0228 - -/* ----------------------------------------------------- - * - * 0x0280h ~ 0x02FFh RXDMA Configuration - * - * ----------------------------------------------------- */ -#define REG_RXDMA_8192E 0x0290 -#define REG_EARLY_MODE_CONTROL_8192E 0x02BC - -#define REG_RSVD5_8192E 0x02F0 -#define REG_RSVD6_8192E 0x02F4 -#define REG_RSVD7_8192E 0x02F8 -#define REG_RSVD8_8192E 0x02FC - -/* ----------------------------------------------------- - * - * 0x0300h ~ 0x03FFh PCIe - * - * ----------------------------------------------------- */ -#define REG_PCIE_CTRL_REG_8192E 0x0300 -#define REG_INT_MIG_8192E 0x0304 /* Interrupt Migration */ -#define REG_BCNQ_TXBD_DESA_8192E 0x0308 /* TX Beacon Descriptor Address */ -#define REG_MGQ_TXBD_DESA_8192E 0x0310 /* TX Manage Queue Descriptor Address */ -#define REG_VOQ_TXBD_DESA_8192E 0x0318 /* TX VO Queue Descriptor Address */ -#define REG_VIQ_TXBD_DESA_8192E 0x0320 /* TX VI Queue Descriptor Address */ -#define REG_BEQ_TXBD_DESA_8192E 0x0328 /* TX BE Queue Descriptor Address */ -#define REG_BKQ_TXBD_DESA_8192E 0x0330 /* TX BK Queue Descriptor Address */ -#define REG_RXQ_RXBD_DESA_8192E 0x0338 /* RX Queue Descriptor Address */ -#define REG_HI0Q_TXBD_DESA_8192E 0x0340 -#define REG_HI1Q_TXBD_DESA_8192E 0x0348 -#define REG_HI2Q_TXBD_DESA_8192E 0x0350 -#define REG_HI3Q_TXBD_DESA_8192E 0x0358 -#define REG_HI4Q_TXBD_DESA_8192E 0x0360 -#define REG_HI5Q_TXBD_DESA_8192E 0x0368 -#define REG_HI6Q_TXBD_DESA_8192E 0x0370 -#define REG_HI7Q_TXBD_DESA_8192E 0x0378 -#define REG_MGQ_TXBD_NUM_8192E 0x0380 -#define REG_RX_RXBD_NUM_8192E 0x0382 -#define REG_VOQ_TXBD_NUM_8192E 0x0384 -#define REG_VIQ_TXBD_NUM_8192E 0x0386 -#define REG_BEQ_TXBD_NUM_8192E 0x0388 -#define REG_BKQ_TXBD_NUM_8192E 0x038A -#define REG_HI0Q_TXBD_NUM_8192E 0x038C -#define REG_HI1Q_TXBD_NUM_8192E 0x038E -#define REG_HI2Q_TXBD_NUM_8192E 0x0390 -#define REG_HI3Q_TXBD_NUM_8192E 0x0392 -#define REG_HI4Q_TXBD_NUM_8192E 0x0394 -#define REG_HI5Q_TXBD_NUM_8192E 0x0396 -#define REG_HI6Q_TXBD_NUM_8192E 0x0398 -#define REG_HI7Q_TXBD_NUM_8192E 0x039A -#define REG_TSFTIMER_HCI_8192E 0x039C - -/* Read Write Point */ -#define REG_VOQ_TXBD_IDX_8192E 0x03A0 -#define REG_VIQ_TXBD_IDX_8192E 0x03A4 -#define REG_BEQ_TXBD_IDX_8192E 0x03A8 -#define REG_BKQ_TXBD_IDX_8192E 0x03AC -#define REG_MGQ_TXBD_IDX_8192E 0x03B0 -#define REG_RXQ_TXBD_IDX_8192E 0x03B4 -#define REG_HI0Q_TXBD_IDX_8192E 0x03B8 -#define REG_HI1Q_TXBD_IDX_8192E 0x03BC -#define REG_HI2Q_TXBD_IDX_8192E 0x03C0 -#define REG_HI3Q_TXBD_IDX_8192E 0x03C4 -#define REG_HI4Q_TXBD_IDX_8192E 0x03C8 -#define REG_HI5Q_TXBD_IDX_8192E 0x03CC -#define REG_HI6Q_TXBD_IDX_8192E 0x03D0 -#define REG_HI7Q_TXBD_IDX_8192E 0x03D4 - -#define REG_PCIE_HCPWM_8192EE 0x03D8 /* ?????? */ -#define REG_PCIE_HRPWM_8192EE 0x03DC /* PCIe RPWM */ /* ?????? */ -#define REG_DBI_WDATA_V1_8192E 0x03E8 -#define REG_DBI_RDATA_V1_8192E 0x03EC -#define REG_DBI_FLAG_V1_8192E 0x03F0 -#define REG_MDIO_V1_8192E 0x3F4 -#define REG_PCIE_MIX_CFG_8192E 0x3F8 - -/* ----------------------------------------------------- - * - * 0x0400h ~ 0x047Fh Protocol Configuration - * - * ----------------------------------------------------- */ -#define REG_TXBF_CTRL_8192E 0x042C -#define REG_ARFR0_8192E 0x0444 -#define REG_ARFR1_8192E 0x044C -#define REG_CCK_CHECK_8192E 0x0454 -#define REG_AMPDU_MAX_TIME_8192E 0x0456 -#define REG_BCNQ1_BDNY_8192E 0x0457 - -#define REG_AMPDU_MAX_LENGTH_8192E 0x0458 -#define REG_WMAC_LBK_BUF_HD_8192E 0x045D -#define REG_NDPA_OPT_CTRL_8192E 0x045F -#define REG_DATA_SC_8192E 0x0483 -#ifdef CONFIG_WOWLAN - #define REG_TXPKTBUF_IV_LOW 0x0484 - #define REG_TXPKTBUF_IV_HIGH 0x0488 -#endif -#define REG_ARFR2_8192E 0x048C -#define REG_ARFR3_8192E 0x0494 -#define REG_TXRPT_START_OFFSET 0x04AC -#define REG_AMPDU_BURST_MODE_8192E 0x04BC -#define REG_HT_SINGLE_AMPDU_8192E 0x04C7 -#define REG_MACID_PKT_DROP0_8192E 0x04D0 - -/* ----------------------------------------------------- - * - * 0x0500h ~ 0x05FFh EDCA Configuration - * - * ----------------------------------------------------- */ -#define REG_CTWND_8192E 0x0572 -#define REG_SECONDARY_CCA_CTRL_8192E 0x0577 -#define REG_SCH_TXCMD_8192E 0x05F8 - -/* ----------------------------------------------------- - * - * 0x0600h ~ 0x07FFh WMAC Configuration - * - * ----------------------------------------------------- */ -#define REG_MAC_CR_8192E 0x0600 - -#define REG_MAC_TX_SM_STATE_8192E 0x06B4 - -/* Power */ -#define REG_BFMER0_INFO_8192E 0x06E4 -#define REG_BFMER1_INFO_8192E 0x06EC -#define REG_CSI_RPT_PARAM_BW20_8192E 0x06F4 -#define REG_CSI_RPT_PARAM_BW40_8192E 0x06F8 -#define REG_CSI_RPT_PARAM_BW80_8192E 0x06FC - -/* Hardware Port 2 */ -#define REG_BFMEE_SEL_8192E 0x0714 -#define REG_SND_PTCL_CTRL_8192E 0x0718 - - -/* ----------------------------------------------------- - * - * Redifine register definition for compatibility - * - * ----------------------------------------------------- */ - -/* TODO: use these definition when using REG_xxx naming rule. - * NOTE: DO NOT Remove these definition. Use later. */ -#define ISR_8192E REG_HISR0_8192E - -/* ---------------------------------------------------------------------------- - * 8192E IMR/ISR bits (offset 0xB0, 8bits) - * ---------------------------------------------------------------------------- */ -#define IMR_DISABLED_8192E 0 -/* IMR DW0(0x00B0-00B3) Bit 0-31 */ -#define IMR_TIMER2_8192E BIT(31) /* Timeout interrupt 2 */ -#define IMR_TIMER1_8192E BIT(30) /* Timeout interrupt 1 */ -#define IMR_PSTIMEOUT_8192E BIT(29) /* Power Save Time Out Interrupt */ -#define IMR_GTINT4_8192E BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ -#define IMR_GTINT3_8192E BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ -#define IMR_TXBCN0ERR_8192E BIT(26) /* Transmit Beacon0 Error */ -#define IMR_TXBCN0OK_8192E BIT(25) /* Transmit Beacon0 OK */ -#define IMR_TSF_BIT32_TOGGLE_8192E BIT(24) /* TSF Timer BIT(32) toggle indication interrupt */ -#define IMR_BCNDMAINT0_8192E BIT(20) /* Beacon DMA Interrupt 0 */ -#define IMR_BCNDERR0_8192E BIT(16) /* Beacon Queue DMA OK0 */ -#define IMR_HSISR_IND_ON_INT_8192E BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ -#define IMR_BCNDMAINT_E_8192E BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ -#define IMR_ATIMEND_8192E BIT(12) /* CTWidnow End or ATIM Window End */ -#define IMR_C2HCMD_8192E BIT(10) /* CPU to Host Command INT Status, Write 1 clear */ -#define IMR_CPWM2_8192E BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_CPWM_8192E BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_HIGHDOK_8192E BIT(7) /* High Queue DMA OK */ -#define IMR_MGNTDOK_8192E BIT(6) /* Management Queue DMA OK */ -#define IMR_BKDOK_8192E BIT(5) /* AC_BK DMA OK */ -#define IMR_BEDOK_8192E BIT(4) /* AC_BE DMA OK */ -#define IMR_VIDOK_8192E BIT(3) /* AC_VI DMA OK */ -#define IMR_VODOK_8192E BIT(2) /* AC_VO DMA OK */ -#define IMR_RDU_8192E BIT(1) /* Rx Descriptor Unavailable */ -#define IMR_ROK_8192E BIT(0) /* Receive DMA OK */ - -/* IMR DW1(0x00B4-00B7) Bit 0-31 */ -#define IMR_BCNDMAINT7_8192E BIT(27) /* Beacon DMA Interrupt 7 */ -#define IMR_BCNDMAINT6_8192E BIT(26) /* Beacon DMA Interrupt 6 */ -#define IMR_BCNDMAINT5_8192E BIT(25) /* Beacon DMA Interrupt 5 */ -#define IMR_BCNDMAINT4_8192E BIT(24) /* Beacon DMA Interrupt 4 */ -#define IMR_BCNDMAINT3_8192E BIT(23) /* Beacon DMA Interrupt 3 */ -#define IMR_BCNDMAINT2_8192E BIT(22) /* Beacon DMA Interrupt 2 */ -#define IMR_BCNDMAINT1_8192E BIT(21) /* Beacon DMA Interrupt 1 */ -#define IMR_BCNDOK7_8192E BIT(20) /* Beacon Queue DMA OK Interrupt 7 */ -#define IMR_BCNDOK6_8192E BIT(19) /* Beacon Queue DMA OK Interrupt 6 */ -#define IMR_BCNDOK5_8192E BIT(18) /* Beacon Queue DMA OK Interrupt 5 */ -#define IMR_BCNDOK4_8192E BIT(17) /* Beacon Queue DMA OK Interrupt 4 */ -#define IMR_BCNDOK3_8192E BIT(16) /* Beacon Queue DMA OK Interrupt 3 */ -#define IMR_BCNDOK2_8192E BIT(15) /* Beacon Queue DMA OK Interrupt 2 */ -#define IMR_BCNDOK1_8192E BIT(14) /* Beacon Queue DMA OK Interrupt 1 */ -#define IMR_ATIMEND_E_8192E BIT(13) /* ATIM Window End Extension for Win7 */ -#define IMR_TXERR_8192E BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */ -#define IMR_RXERR_8192E BIT(10) /* Rx Error Flag INT Status, Write 1 clear */ -#define IMR_TXFOVW_8192E BIT(9) /* Transmit FIFO Overflow */ -#define IMR_RXFOVW_8192E BIT(8) /* Receive FIFO Overflow */ - -/* ---------------------------------------------------------------------------- - * 8192E Auto LLT bits (offset 0x224, 8bits) - * ---------------------------------------------------------------------------- - * 224 REG_AUTO_LLT - * move to hal_com_reg.h */ - -/* ---------------------------------------------------------------------------- - * 8192E Auto LLT bits (offset 0x290, 32bits) - * ---------------------------------------------------------------------------- */ -#define BIT_DMA_MODE BIT(1) -#define BIT_USB_RXDMA_AGG_EN BIT(31) - -/* ---------------------------------------------------------------------------- - * 8192E REG_SYS_CFG1 (offset 0xF0, 32bits) - * ---------------------------------------------------------------------------- */ -#define BIT_SPSLDO_SEL BIT(24) - - -/* ---------------------------------------------------------------------------- - * 8192E REG_CCK_CHECK (offset 0x454, 8bits) - * ---------------------------------------------------------------------------- */ -#define BIT_BCN_PORT_SEL BIT(5) - -/* **************************************************************************** - * Regsiter Bit and Content definition - * **************************************************************************** */ - -/* 2 ACMHWCTRL 0x05C0 */ -#define AcmHw_HwEn_8192E BIT(0) -#define AcmHw_VoqEn_8192E BIT(1) -#define AcmHw_ViqEn_8192E BIT(2) -#define AcmHw_BeqEn_8192E BIT(3) -#define AcmHw_VoqStatus_8192E BIT(5) -#define AcmHw_ViqStatus_8192E BIT(6) -#define AcmHw_BeqStatus_8192E BIT(7) - -#endif /* __RTL8192E_SPEC_H__ */ diff --git a/include/rtl8192e_sreset.h b/include/rtl8192e_sreset.h deleted file mode 100644 index 7430d9a..0000000 --- a/include/rtl8192e_sreset.h +++ /dev/null @@ -1,29 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef _RTL88812A_SRESET_H_ -#define _RTL8812A_SRESET_H_ - -#include - -#ifdef DBG_CONFIG_ERROR_DETECT - extern void rtl8192e_sreset_xmit_status_check(_adapter *padapter); - extern void rtl8192e_sreset_linked_status_check(_adapter *padapter); -#endif -#endif diff --git a/include/rtl8192e_xmit.h b/include/rtl8192e_xmit.h deleted file mode 100644 index 23deb8d..0000000 --- a/include/rtl8192e_xmit.h +++ /dev/null @@ -1,451 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8192E_XMIT_H__ -#define __RTL8192E_XMIT_H__ - -typedef struct txdescriptor_8192e { - /* Offset 0 */ - u32 pktlen:16; - u32 offset:8; - u32 bmc:1; - u32 htc:1; - u32 ls:1; - u32 fs:1; - u32 linip:1; - u32 noacm:1; - u32 gf:1; - u32 own:1; - - /* Offset 4 */ - u32 macid:6; - u32 rsvd0406:2; - u32 qsel:5; - u32 rd_nav_ext:1; - u32 lsig_txop_en:1; - u32 pifs:1; - u32 rate_id:4; - u32 navusehdr:1; - u32 en_desc_id:1; - u32 sectype:2; - u32 rsvd0424:2; - u32 pkt_offset:5; /* unit: 8 bytes */ - u32 rsvd0431:1; - - /* Offset 8 */ - u32 rts_rc:6; - u32 data_rc:6; - u32 agg_en:1; - u32 rd_en:1; - u32 bar_rty_th:2; - u32 bk:1; - u32 morefrag:1; - u32 raw:1; - u32 ccx:1; - u32 ampdu_density:3; - u32 bt_null:1; - u32 ant_sel_a:1; - u32 ant_sel_b:1; - u32 tx_ant_cck:2; - u32 tx_antl:2; - u32 tx_ant_ht:2; - - /* Offset 12 */ - u32 nextheadpage:8; - u32 tailpage:8; - u32 seq:12; - u32 cpu_handle:1; - u32 tag1:1; - u32 trigger_int:1; - u32 hwseq_en:1; - - /* Offset 16 */ - u32 rtsrate:5; - u32 ap_dcfe:1; - u32 hwseq_sel:2; - u32 userate:1; - u32 disrtsfb:1; - u32 disdatafb:1; - u32 cts2self:1; - u32 rtsen:1; - u32 hw_rts_en:1; - u32 port_id:1; - u32 pwr_status:3; - u32 wait_dcts:1; - u32 cts2ap_en:1; - u32 data_sc:2; - u32 data_stbc:2; - u32 data_short:1; - u32 data_bw:1; - u32 rts_short:1; - u32 rts_bw:1; - u32 rts_sc:2; - u32 vcs_stbc:2; - - /* Offset 20 */ - u32 datarate:6; - u32 sgi:1; - u32 try_rate:1; - u32 data_ratefb_lmt:5; - u32 rts_ratefb_lmt:4; - u32 rty_lmt_en:1; - u32 data_rt_lmt:6; - u32 usb_txagg_num:8; - - /* Offset 24 */ - u32 txagg_a:5; - u32 txagg_b:5; - u32 use_max_len:1; - u32 max_agg_num:5; - u32 mcsg1_max_len:4; - u32 mcsg2_max_len:4; - u32 mcsg3_max_len:4; - u32 mcs7_sgi_max_len:4; - - /* Offset 28 */ - u32 checksum:16; /* TxBuffSize(PCIe)/CheckSum(USB) */ - u32 mcsg4_max_len:4; - u32 mcsg5_max_len:4; - u32 mcsg6_max_len:4; - u32 mcs15_sgi_max_len:4; -} TXDESC_8192E, *PTXDESC_8192E; - - - -/* For 88e early mode */ -#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value) -#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value) -#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value) -#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value) -#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value) -#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value) -#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value) - -/* - * defined for TX DESC Operation - * */ - -#define MAX_TID (15) - -/* OFFSET 0 */ -#define OFFSET_SZ 0 -#define OFFSET_SHT 16 -#define BMC BIT(24) -#define LSG BIT(26) -#define FSG BIT(27) -#define OWN BIT(31) - - -/* OFFSET 4 */ -#define PKT_OFFSET_SZ 0 -#define QSEL_SHT 8 -#define RATE_ID_SHT 16 -#define NAVUSEHDR BIT(20) -#define SEC_TYPE_SHT 22 -#define PKT_OFFSET_SHT 26 - -/* OFFSET 8 */ -#define AGG_EN BIT(12) -#define AGG_BK BIT(16) -#define AMPDU_DENSITY_SHT 20 -#define ANTSEL_A BIT(24) -#define ANTSEL_B BIT(25) -#define TX_ANT_CCK_SHT 26 -#define TX_ANTL_SHT 28 -#define TX_ANT_HT_SHT 30 - -/* OFFSET 12 */ -#define SEQ_SHT 16 -#define EN_HWSEQ BIT(31) - -/* OFFSET 16 */ -#define QOS BIT(6) -#define HW_SSN BIT(7) -#define USERATE BIT(8) -#define DISDATAFB BIT(10) -#define CTS_2_SELF BIT(11) -#define RTS_EN BIT(12) -#define HW_RTS_EN BIT(13) -#define DATA_SHORT BIT(24) -#define PWR_STATUS_SHT 15 -#define DATA_SC_SHT 20 -#define DATA_BW BIT(25) - -/* OFFSET 20 */ -#define RTY_LMT_EN BIT(17) - - -/* OFFSET 20 */ -#define SGI BIT(6) -#define USB_TXAGG_NUM_SHT 24 - - -/* *****Tx Desc Buffer content */ - -/* config element for each tx buffer - * -#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 0, 16, __Valeu) -#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 31, 1, __Valeu) -#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+4, 0, 32, __Valeu) -#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu) -*/ -#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu) -#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu) -#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu) -#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu) - - -/* Dword 0 */ -#define SET_TX_BUFF_DESC_LEN_0_92E(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu) -#define SET_TX_BUFF_DESC_PSB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value) -#define SET_TX_BUFF_DESC_OWN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) -/* Dword 1 */ -#define SET_TX_BUFF_DESC_ADDR_LOW_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value) -#define GET_TX_DESC_TX_BUFFER_ADDRESS_92E(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32) - - -/* Dword 2 */ -#define SET_TX_BUFF_DESC_ADDR_HIGH_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 32, __Value) -/* Dword 3, RESERVED */ - - -/* *****Tx Desc content - * Dword 0 */ -#define SET_TX_DESC_PKT_SIZE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value) -#define SET_TX_DESC_OFFSET_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value) -#define SET_TX_DESC_BMC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value) -#define SET_TX_DESC_HTC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value) -#define SET_TX_DESC_LAST_SEG_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value) -#define SET_TX_DESC_FIRST_SEG_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value) -#define SET_TX_DESC_LINIP_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value) -#define SET_TX_DESC_NO_ACM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value) -#define SET_TX_DESC_GF_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value) -#define SET_TX_DESC_OWN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) -#define GET_TX_DESC_OWN_92E(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1) - -/* Dword 1 */ -#define SET_TX_DESC_MACID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value) -#define SET_TX_DESC_QUEUE_SEL_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value) -#define SET_TX_DESC_RDG_NAV_EXT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value) -#define SET_TX_DESC_LSIG_TXOP_EN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value) -#define SET_TX_DESC_PIFS_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value) -#define SET_TX_DESC_RATE_ID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value) -#define SET_TX_DESC_EN_DESC_ID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value) -#define SET_TX_DESC_SEC_TYPE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value) -#define SET_TX_DESC_PKT_OFFSET_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value) -#define SET_TX_DESC_MORE_DATA_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value) -#define SET_TX_DESC_TXOP_PS_CAP_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 30, 1, __Value) -#define SET_TX_DESC_TXOP_PS_MODE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 31, 1, __Value) - - -/* Dword 2 */ -#define SET_TX_DESC_PAID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value) -#define SET_TX_DESC_CCA_RTS_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value) -#define SET_TX_DESC_AGG_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value) -#define SET_TX_DESC_RDG_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value) -#define SET_TX_DESC_NULL_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value) -#define SET_TX_DESC_NULL_1_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value) -#define SET_TX_DESC_BK_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value) -#define SET_TX_DESC_MORE_FRAG_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value) -#define SET_TX_DESC_RAW_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value) -#define GET_TX_DESC_MORE_FRAG_92E(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 17, 1) -#define SET_TX_DESC_SPE_RPT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value) -#define SET_TX_DESC_AMPDU_DENSITY_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value) -#define SET_TX_DESC_BT_NULL_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value) -#define SET_TX_DESC_GID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value) - - -/* Dword 3 */ -#define SET_TX_DESC_WHEADER_LEN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value) -#define SET_TX_DESC_CHK_EN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value) -#define SET_TX_DESC_EARLY_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value) -#define SET_TX_DESC_HWSEQ_SEL_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value) -#define SET_TX_DESC_USE_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value) -#define SET_TX_DESC_DISABLE_RTS_FB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value) -#define SET_TX_DESC_DISABLE_FB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value) -#define SET_TX_DESC_CTS2SELF_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value) -#define SET_TX_DESC_RTS_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value) -#define SET_TX_DESC_HW_RTS_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value) -#define SET_TX_DESC_HW_PORT_ID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 1, __Value) -#define SET_TX_DESC_NAV_USE_HDR_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value) -#define SET_TX_DESC_USE_MAX_LEN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value) -#define SET_TX_DESC_MAX_AGG_NUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value) -#define SET_TX_DESC_NDPA_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value) -#define SET_TX_DESC_AMPDU_MAX_TIME_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value) - -/* Dword 4 */ -#define SET_TX_DESC_TX_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value) -#define SET_TX_DESC_TRY_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value) -#define SET_TX_DESC_DATA_RATE_FB_LIMIT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value) -#define SET_TX_DESC_RTS_RATE_FB_LIMIT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value) -#define SET_TX_DESC_RETRY_LIMIT_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value) -#define SET_TX_DESC_DATA_RETRY_LIMIT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value) -#define SET_TX_DESC_RTS_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value) -#define SET_TX_DESC_PCTS_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value) -#define SET_TX_DESC_PCTS_MASK_IDX_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value) - - -/* Dword 5 */ -#define SET_TX_DESC_DATA_SC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value) -#define SET_TX_DESC_DATA_SHORT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value) -#define SET_TX_DESC_DATA_BW_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value) -#define SET_TX_DESC_DATA_LDPC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value) -#define SET_TX_DESC_DATA_STBC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value) -#define SET_TX_DESC_VCS_STBC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value) -#define SET_TX_DESC_RTS_SHORT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value) -#define SET_TX_DESC_RTS_SC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value) -#define SET_TX_DESC_TX_ANT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 4, __Value) -#define SET_TX_DESC_TX_POWER_0_PSET_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value) - -/* Dword 6 */ -#define SET_TX_DESC_SW_DEFINE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value) -#define SET_TX_DESC_MBSSID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value) -#define SET_TX_DESC_ANTSEL_A_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value) -#define SET_TX_DESC_ANTSEL_B_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value) -#define SET_TX_DESC_ANTSEL_C_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value) -#define SET_TX_DESC_ANTSEL_D_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value) - -/* Dword 7 */ -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) - #define SET_TX_DESC_TX_BUFFER_SIZE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) -#else - #define SET_TX_DESC_TX_DESC_CHECKSUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) -#endif -#define SET_TX_DESC_USB_TXAGG_NUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) - - -/* #define SET_TX_DESC_HWSEQ_EN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) */ -/* Dword 8 */ - -#define SET_TX_DESC_RTS_RC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value) -#define SET_TX_DESC_BAR_RTY_TH_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value) -#define SET_TX_DESC_DATA_RC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value) -#define SET_TX_DESC_EN_HWSEQ_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) -#define SET_TX_DESC_NEXT_HEAD_PAGE_92E(__pTxDesc, __Value)(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value) -#define SET_TX_DESC_TAIL_PAGE_92E(__pTxDesc, __Value)(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value) - -/* Dword 9 */ -#define SET_TX_DESC_PADDING_LENGTH_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value) -#define SET_TX_DESC_TXBF_PATH_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 11, 1, __Value) -#define SET_TX_DESC_SEQ_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value) -#define SET_TX_DESC_FINAL_DATA_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value) - - -#define SET_EARLYMODE_PKTNUM_92E(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value) -#define SET_EARLYMODE_LEN0_92E(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value) -#define SET_EARLYMODE_LEN1_1_92E(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value) -#define SET_EARLYMODE_LEN1_2_92E(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value) -#define SET_EARLYMODE_LEN2_92E(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value) -#define SET_EARLYMODE_LEN3_92E(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value) - -void rtl8192e_cal_txdesc_chksum(u8 *ptxdesc); - -#ifdef CONFIG_USB_HCI - s32 rtl8192eu_init_xmit_priv(PADAPTER padapter); - void rtl8192eu_free_xmit_priv(PADAPTER padapter); - s32 rtl8192eu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 rtl8192eu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); - s32 rtl8192eu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); - s32 rtl8192eu_xmit_buf_handler(PADAPTER padapter); - #define hal_xmit_handler rtl8192eu_xmit_buf_handler - void rtl8192eu_xmit_tasklet(void *priv); - s32 rtl8192eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); -#endif - -#ifdef CONFIG_PCI_HCI - s32 rtl8192ee_init_xmit_priv(PADAPTER padapter); - void rtl8192ee_free_xmit_priv(PADAPTER padapter); - struct xmit_buf *rtl8192ee_dequeue_xmitbuf(struct rtw_tx_ring *ring); - s32 rtl8192ee_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); - void rtl8192ee_xmitframe_resume(_adapter *padapter); - s32 rtl8192ee_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 rtl8192ee_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); - void rtl8192ee_xmit_tasklet(void *priv); -#endif - -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - s32 rtl8192es_init_xmit_priv(PADAPTER padapter); - void rtl8192es_free_xmit_priv(PADAPTER padapter); - - s32 rtl8192es_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 rtl8192es_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); - s32 rtl8192es_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); - thread_return rtl8192es_xmit_thread(thread_context context); - s32 rtl8192es_xmit_buf_handler(PADAPTER padapter); - - #ifdef CONFIG_SDIO_TX_TASKLET - void rtl8192es_xmit_tasklet(void *priv); - #endif -#endif - -struct txrpt_ccx_92e { - /* offset 0 */ - u8 tag1:1; - u8 pkt_num:3; - u8 txdma_underflow:1; - u8 int_bt:1; - u8 int_tri:1; - u8 int_ccx:1; - - /* offset 1 */ - u8 mac_id:6; - u8 pkt_ok:1; - u8 bmc:1; - - /* offset 2 */ - u8 retry_cnt:6; - u8 lifetime_over:1; - u8 retry_over:1; - - /* offset 3 */ - u8 ccx_qtime0; - u8 ccx_qtime1; - - /* offset 5 */ - u8 final_data_rate; - - /* offset 6 */ - u8 sw1:4; - u8 qsel:4; - - /* offset 7 */ - u8 sw0; -}; - -#ifdef CONFIG_TX_EARLY_MODE - void UpdateEarlyModeInfo8192E(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); -#endif -s32 rtl8192e_init_xmit_priv(_adapter *padapter); -void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, u8 *ptxdesc); - -void rtl8192e_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, - u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); -void rtl8192e_cal_txdesc_chksum(u8 *ptxdesc); - -u8 BWMapping_92E(PADAPTER Adapter, struct pkt_attrib *pattrib); -u8 SCMapping_92E(PADAPTER Adapter, struct pkt_attrib *pattrib); -void fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc); -void fill_txdesc_vcs(struct pkt_attrib *pattrib, u8 *ptxdesc); -#if defined(CONFIG_CONCURRENT_MODE) - void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); -#endif -void fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc); -void rtl8192e_fixed_rate(_adapter *padapter, u8 *ptxdesc); - -#endif /* __RTL8192E_XMIT_H__ */ diff --git a/include/rtl8703b_cmd.h b/include/rtl8703b_cmd.h deleted file mode 100644 index 0e798f0..0000000 --- a/include/rtl8703b_cmd.h +++ /dev/null @@ -1,218 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8703B_CMD_H__ -#define __RTL8703B_CMD_H__ - -/* --------------------------------------------------------------------------------------------------------- - * ---------------------------------- H2C CMD DEFINITION ------------------------------------------------ - * --------------------------------------------------------------------------------------------------------- */ - -enum h2c_cmd_8703B { - /* Common Class: 000 */ - H2C_8703B_RSVD_PAGE = 0x00, - H2C_8703B_MEDIA_STATUS_RPT = 0x01, - H2C_8703B_SCAN_ENABLE = 0x02, - H2C_8703B_KEEP_ALIVE = 0x03, - H2C_8703B_DISCON_DECISION = 0x04, - H2C_8703B_PSD_OFFLOAD = 0x05, - H2C_8703B_AP_OFFLOAD = 0x08, - H2C_8703B_BCN_RSVDPAGE = 0x09, - H2C_8703B_PROBERSP_RSVDPAGE = 0x0A, - H2C_8703B_FCS_RSVDPAGE = 0x10, - H2C_8703B_FCS_INFO = 0x11, - H2C_8703B_AP_WOW_GPIO_CTRL = 0x13, - - /* PoweSave Class: 001 */ - H2C_8703B_SET_PWR_MODE = 0x20, - H2C_8703B_PS_TUNING_PARA = 0x21, - H2C_8703B_PS_TUNING_PARA2 = 0x22, - H2C_8703B_P2P_LPS_PARAM = 0x23, - H2C_8703B_P2P_PS_OFFLOAD = 0x24, - H2C_8703B_PS_SCAN_ENABLE = 0x25, - H2C_8703B_SAP_PS_ = 0x26, - H2C_8703B_INACTIVE_PS_ = 0x27, /* Inactive_PS */ - H2C_8703B_FWLPS_IN_IPS_ = 0x28, - - /* Dynamic Mechanism Class: 010 */ - H2C_8703B_MACID_CFG = 0x40, - H2C_8703B_TXBF = 0x41, - H2C_8703B_RSSI_SETTING = 0x42, - H2C_8703B_AP_REQ_TXRPT = 0x43, - H2C_8703B_INIT_RATE_COLLECT = 0x44, - H2C_8703B_RA_PARA_ADJUST = 0x46, - - /* BT Class: 011 */ - H2C_8703B_B_TYPE_TDMA = 0x60, - H2C_8703B_BT_INFO = 0x61, - H2C_8703B_FORCE_BT_TXPWR = 0x62, - H2C_8703B_BT_IGNORE_WLANACT = 0x63, - H2C_8703B_DAC_SWING_VALUE = 0x64, - H2C_8703B_ANT_SEL_RSV = 0x65, - H2C_8703B_WL_OPMODE = 0x66, - H2C_8703B_BT_MP_OPER = 0x67, - H2C_8703B_BT_CONTROL = 0x68, - H2C_8703B_BT_WIFI_CTRL = 0x69, - H2C_8703B_BT_FW_PATCH = 0x6A, - H2C_8703B_BT_WLAN_CALIBRATION = 0x6D, - - /* WOWLAN Class: 100 */ - H2C_8703B_WOWLAN = 0x80, - H2C_8703B_REMOTE_WAKE_CTRL = 0x81, - H2C_8703B_AOAC_GLOBAL_INFO = 0x82, - H2C_8703B_AOAC_RSVD_PAGE = 0x83, - H2C_8703B_AOAC_RSVD_PAGE2 = 0x84, - H2C_8703B_D0_SCAN_OFFLOAD_CTRL = 0x85, - H2C_8703B_D0_SCAN_OFFLOAD_INFO = 0x86, - H2C_8703B_CHNL_SWITCH_OFFLOAD = 0x87, - H2C_8703B_P2P_OFFLOAD_RSVD_PAGE = 0x8A, - H2C_8703B_P2P_OFFLOAD = 0x8B, - - H2C_8703B_RESET_TSF = 0xC0, - H2C_8703B_MAXID, -}; - -/* --------------------------------------------------------------------------------------------------------- - * ---------------------------------- H2C CMD CONTENT -------------------------------------------------- - * --------------------------------------------------------------------------------------------------------- - * _RSVDPAGE_LOC_CMD_0x00 */ -#define SET_8703B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8703B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) -#define SET_8703B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) -#define SET_8703B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) -#define SET_8703B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) - -/* _KEEP_ALIVE_CMD_0x03 */ -#define SET_8703B_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) -#define SET_8703B_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) -#define SET_8703B_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) -#define SET_8703B_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) - -/* _DISCONNECT_DECISION_CMD_0x04 */ -#define SET_8703B_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) -#define SET_8703B_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) -#define SET_8703B_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) -#define SET_8703B_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) - -/* _PWR_MOD_CMD_0x20 */ -#define SET_8703B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8703B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value) -#define SET_8703B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value) -#define SET_8703B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) -#define SET_8703B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) -#define SET_8703B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value) -#define SET_8703B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) -#define SET_8703B_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) - -#define GET_8703B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8) - -/* _PS_TUNE_PARAM_CMD_0x21 */ -#define SET_8703B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8703B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) -#define SET_8703B_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value) -#define SET_8703B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value) -#define SET_8703B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) - -/* _MACID_CFG_CMD_0x40 */ -#define SET_8703B_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8703B_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value) -#define SET_8703B_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value) -#define SET_8703B_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value) -#define SET_8703B_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value) -#define SET_8703B_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value) -#define SET_8703B_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value) -#define SET_8703B_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value) -#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) -#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value) -#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value) -#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value) - -/* _RSSI_SETTING_CMD_0x42 */ -#define SET_8703B_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8703B_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value) -#define SET_8703B_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) - -/* _AP_REQ_TXRPT_CMD_0x43 */ -#define SET_8703B_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8703B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) - -/* _FORCE_BT_TXPWR_CMD_0x62 */ -#define SET_8703B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) - -/* _FORCE_BT_MP_OPER_CMD_0x67 */ -#define SET_8703B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) -#define SET_8703B_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value) -#define SET_8703B_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) -#define SET_8703B_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) -#define SET_8703B_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) -#define SET_8703B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value) - -/* _BT_FW_PATCH_0x6A */ -#define SET_8703B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value) -#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) -#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) -#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) -#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) - -/* --------------------------------------------------------------------------------------------------------- - * ------------------------------------------- Structure -------------------------------------------------- - * --------------------------------------------------------------------------------------------------------- */ - - -/* --------------------------------------------------------------------------------------------------------- - * ---------------------------------- Function Statement -------------------------------------------------- - * --------------------------------------------------------------------------------------------------------- */ - -/* host message to firmware cmd */ -void rtl8703b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); -void rtl8703b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus); -void rtl8703b_set_rssi_cmd(PADAPTER padapter, u8 *param); -void rtl8703b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack); -/* s32 rtl8703b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */ -void rtl8703b_set_FwPsTuneParam_cmd(PADAPTER padapter); -void rtl8703b_set_FwMacIdConfig_cmd(_adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask, u8 ignore_bw); -void rtl8703b_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param); -void rtl8703b_download_rsvd_page(PADAPTER padapter, u8 mstatus); -#ifdef CONFIG_BT_COEXIST - void rtl8703b_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter); -#endif /* CONFIG_BT_COEXIST */ -#ifdef CONFIG_P2P - void rtl8703b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); -#endif /* CONFIG_P2P */ - -void CheckFwRsvdPageContent(PADAPTER padapter); - -#ifdef CONFIG_TDLS - #ifdef CONFIG_TDLS_CH_SW - void rtl8703b_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); - #endif -#endif - -#ifdef CONFIG_P2P_WOWLAN - void rtl8703b_set_p2p_wowlan_offload_cmd(PADAPTER padapter); -#endif - -void rtl8703b_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param); - -#ifdef CONFIG_TSF_RESET_OFFLOAD - u8 rtl8703b_reset_tsf(_adapter *padapter, u8 reset_port); -#endif /* CONFIG_TSF_RESET_OFFLOAD */ -s32 FillH2CCmd8703B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); -u8 GetTxBufferRsvdPageNum8703B(_adapter *padapter, bool wowlan); -#endif diff --git a/include/rtl8703b_dm.h b/include/rtl8703b_dm.h deleted file mode 100644 index 4ee834d..0000000 --- a/include/rtl8703b_dm.h +++ /dev/null @@ -1,47 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8703B_DM_H__ -#define __RTL8703B_DM_H__ -/* ************************************************************ - * Description: - * - * This file is for 8703B dynamic mechanism only - * - * - * ************************************************************ */ - -/* ************************************************************ - * structure and define - * ************************************************************ */ - -/* ************************************************************ - * function prototype - * ************************************************************ */ - -void rtl8703b_init_dm_priv(PADAPTER padapter); -void rtl8703b_deinit_dm_priv(PADAPTER padapter); - -void rtl8703b_InitHalDm(PADAPTER padapter); -void rtl8703b_HalDmWatchDog(PADAPTER padapter); -void rtl8703b_HalDmWatchDog_in_LPS(PADAPTER padapter); -void rtl8703b_hal_dm_in_lps(PADAPTER padapter); - - -#endif diff --git a/include/rtl8703b_hal.h b/include/rtl8703b_hal.h deleted file mode 100644 index 432ba27..0000000 --- a/include/rtl8703b_hal.h +++ /dev/null @@ -1,277 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8703B_HAL_H__ -#define __RTL8703B_HAL_H__ - -#include "hal_data.h" - -#include "rtl8703b_spec.h" -#include "rtl8703b_rf.h" -#include "rtl8703b_dm.h" -#include "rtl8703b_recv.h" -#include "rtl8703b_xmit.h" -#include "rtl8703b_cmd.h" -#include "rtl8703b_led.h" -#include "Hal8703BPwrSeq.h" -#include "Hal8703BPhyReg.h" -#include "Hal8703BPhyCfg.h" -#ifdef DBG_CONFIG_ERROR_DETECT - #include "rtl8703b_sreset.h" -#endif - -#define FW_8703B_SIZE 0x8000 -#define FW_8703B_START_ADDRESS 0x1000 -#define FW_8703B_END_ADDRESS 0x1FFF /* 0x5FFF */ - -#define IS_FW_HEADER_EXIST_8703B(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x03B0) - -typedef struct _RT_FIRMWARE { - FIRMWARE_SOURCE eFWSource; -#ifdef CONFIG_EMBEDDED_FWIMG - u8 *szFwBuffer; -#else - u8 szFwBuffer[FW_8703B_SIZE]; -#endif - u32 ulFwLength; -} RT_FIRMWARE_8703B, *PRT_FIRMWARE_8703B; - -/* - * This structure must be cared byte-ordering - * - * Added by tynli. 2009.12.04. */ -typedef struct _RT_8703B_FIRMWARE_HDR { - /* 8-byte alinment required */ - - /* --- LONG WORD 0 ---- */ - u16 Signature; /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */ - u8 Category; /* AP/NIC and USB/PCI */ - u8 Function; /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */ - u16 Version; /* FW Version */ - u16 Subversion; /* FW Subversion, default 0x00 */ - - /* --- LONG WORD 1 ---- */ - u8 Month; /* Release time Month field */ - u8 Date; /* Release time Date field */ - u8 Hour; /* Release time Hour field */ - u8 Minute; /* Release time Minute field */ - u16 RamCodeSize; /* The size of RAM code */ - u16 Rsvd2; - - /* --- LONG WORD 2 ---- */ - u32 SvnIdx; /* The SVN entry index */ - u32 Rsvd3; - - /* --- LONG WORD 3 ---- */ - u32 Rsvd4; - u32 Rsvd5; -} RT_8703B_FIRMWARE_HDR, *PRT_8703B_FIRMWARE_HDR; - -#define DRIVER_EARLY_INT_TIME_8703B 0x05 -#define BCN_DMA_ATIME_INT_TIME_8703B 0x02 - -/* for 8703B - * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */ -#define PAGE_SIZE_TX_8703B 128 -#define PAGE_SIZE_RX_8703B 8 - -#define TX_DMA_SIZE_8703B 0x8000 /* 32K(TX) */ -#define RX_DMA_SIZE_8703B 0x4000 /* 16K(RX) */ - -#ifdef CONFIG_WOWLAN - #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/ -#else - #define RESV_FMWF 0 -#endif - -#ifdef CONFIG_FW_C2H_DEBUG - #define RX_DMA_RESERVED_SIZE_8703B 0x100 /* 256B, reserved for c2h debug message */ -#else - #define RX_DMA_RESERVED_SIZE_8703B 0x80 /* 128B, reserved for tx report */ -#endif -#define RX_DMA_BOUNDARY_8703B (RX_DMA_SIZE_8703B - RX_DMA_RESERVED_SIZE_8703B - 1) - - -/* Note: We will divide number of page equally for each queue other than public queue! */ - -/* For General Reserved Page Number(Beacon Queue is reserved page) - * Beacon:2, PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1 */ -#define BCNQ_PAGE_NUM_8703B 0x08 -#ifdef CONFIG_CONCURRENT_MODE - #define BCNQ1_PAGE_NUM_8703B 0x08 /* 0x04 */ -#else - #define BCNQ1_PAGE_NUM_8703B 0x00 -#endif - -#ifdef CONFIG_PNO_SUPPORT - #undef BCNQ1_PAGE_NUM_8703B - #define BCNQ1_PAGE_NUM_8703B 0x00 /* 0x04 */ -#endif - -/* For WoWLan , more reserved page - * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1 PNO: 6 */ -#ifdef CONFIG_WOWLAN - #define WOWLAN_PAGE_NUM_8703B 0x08 -#else - #define WOWLAN_PAGE_NUM_8703B 0x00 -#endif - -#ifdef CONFIG_PNO_SUPPORT - #undef WOWLAN_PAGE_NUM_8703B - #define WOWLAN_PAGE_NUM_8703B 0x15 -#endif - -#ifdef CONFIG_AP_WOWLAN - #define AP_WOWLAN_PAGE_NUM_8703B 0x02 -#endif - -#define TX_TOTAL_PAGE_NUMBER_8703B (0xFF - BCNQ_PAGE_NUM_8703B - BCNQ1_PAGE_NUM_8703B - WOWLAN_PAGE_NUM_8703B) -#define TX_PAGE_BOUNDARY_8703B (TX_TOTAL_PAGE_NUMBER_8703B + 1) - -#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8703B TX_TOTAL_PAGE_NUMBER_8703B -#define WMM_NORMAL_TX_PAGE_BOUNDARY_8703B (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8703B + 1) - -/* For Normal Chip Setting - * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8703B */ -#define NORMAL_PAGE_NUM_HPQ_8703B 0x0C -#define NORMAL_PAGE_NUM_LPQ_8703B 0x02 -#define NORMAL_PAGE_NUM_NPQ_8703B 0x02 - -/* Note: For Normal Chip Setting, modify later */ -#define WMM_NORMAL_PAGE_NUM_HPQ_8703B 0x30 -#define WMM_NORMAL_PAGE_NUM_LPQ_8703B 0x20 -#define WMM_NORMAL_PAGE_NUM_NPQ_8703B 0x20 - - -#include "HalVerDef.h" -#include "hal_com.h" - -#define EFUSE_OOB_PROTECT_BYTES 15 - -#define HAL_EFUSE_MEMORY - -#define HWSET_MAX_SIZE_8703B 256 -#define EFUSE_REAL_CONTENT_LEN_8703B 256 -#define EFUSE_MAP_LEN_8703B 512 -#define EFUSE_MAX_SECTION_8703B 64 - -#define EFUSE_IC_ID_OFFSET 506 /* For some inferiority IC purpose. added by Roger, 2009.09.02. */ -#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN_8703B) - -#define EFUSE_ACCESS_ON 0x69 -#define EFUSE_ACCESS_OFF 0x00 - -/* ******************************************************** - * EFUSE for BT definition - * ******************************************************** */ -#define BANK_NUM 1 -#define EFUSE_BT_REAL_BANK_CONTENT_LEN 128 -#define EFUSE_BT_REAL_CONTENT_LEN (EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM) -#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */ -#define EFUSE_BT_MAX_SECTION (EFUSE_BT_MAP_LEN / 8) -#define EFUSE_PROTECT_BYTES_BANK 16 - -typedef enum tag_Package_Definition { - PACKAGE_DEFAULT, - PACKAGE_QFN68, - PACKAGE_TFBGA90, - PACKAGE_TFBGA80, - PACKAGE_TFBGA79 -} PACKAGE_TYPE_E; - -#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT) -#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) - -/* rtl8703b_hal_init.c */ -s32 rtl8703b_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw); -void rtl8703b_FirmwareSelfReset(PADAPTER padapter); -void rtl8703b_InitializeFirmwareVars(PADAPTER padapter); - -void rtl8703b_InitAntenna_Selection(PADAPTER padapter); -void rtl8703b_DeinitAntenna_Selection(PADAPTER padapter); -void rtl8703b_CheckAntenna_Selection(PADAPTER padapter); -void rtl8703b_init_default_value(PADAPTER padapter); - -s32 rtl8703b_InitLLTTable(PADAPTER padapter); - -s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU); -s32 CardDisableWithoutHWSM(PADAPTER padapter); - -/* EFuse */ -u8 GetEEPROMSize8703B(PADAPTER padapter); -void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent); -void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo); -void Hal_EfuseParseTxPowerInfo_8703B(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail); -void Hal_EfuseParseBTCoexistInfo_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParseEEPROMVer_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParseChnlPlan_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParseCustomerID_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParseAntennaDiversity_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParseXtal_8703B(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail); -void Hal_EfuseParseThermalMeter_8703B(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail); -VOID Hal_EfuseParseVoltage_8703B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -VOID Hal_EfuseParseBoardType_8703B(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); - -void rtl8703b_set_hal_ops(struct hal_ops *pHalFunc); -void init_hal_spec_8703b(_adapter *adapter); -void SetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val); -void GetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val); -u8 SetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); -u8 GetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); - -/* register */ -void rtl8703b_InitBeaconParameters(PADAPTER padapter); -void rtl8703b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode); -void _InitBurstPktLen_8703BS(PADAPTER Adapter); -void _InitLTECoex_8703BS(PADAPTER Adapter); -void _InitMacAPLLSetting_8703B(PADAPTER Adapter); -void _8051Reset8703(PADAPTER padapter); -#ifdef CONFIG_WOWLAN - void Hal_DetectWoWMode(PADAPTER pAdapter); -#endif /* CONFIG_WOWLAN */ - -void rtl8703b_start_thread(_adapter *padapter); -void rtl8703b_stop_thread(_adapter *padapter); - -#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST) - void rtl8703bs_init_checkbthang_workqueue(_adapter *adapter); - void rtl8703bs_free_checkbthang_workqueue(_adapter *adapter); - void rtl8703bs_cancle_checkbthang_workqueue(_adapter *adapter); - void rtl8703bs_hal_check_bt_hang(_adapter *adapter); -#endif - -#ifdef CONFIG_GPIO_WAKEUP - void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue); -#endif -#ifdef CONFIG_MP_INCLUDED -int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware); -#endif -void CCX_FwC2HTxRpt_8703b(PADAPTER padapter, u8 *pdata, u8 len); - -u8 MRateToHwRate8703B(u8 rate); -u8 HwRateToMRate8703B(u8 rate); - -void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); - -#ifdef CONFIG_PCI_HCI - BOOLEAN InterruptRecognized8703BE(PADAPTER Adapter); - VOID UpdateInterruptMask8703BE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1); -#endif - -#endif diff --git a/include/rtl8703b_led.h b/include/rtl8703b_led.h deleted file mode 100644 index fb11fdd..0000000 --- a/include/rtl8703b_led.h +++ /dev/null @@ -1,48 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8703B_LED_H__ -#define __RTL8703B_LED_H__ - -#include -#include -#include - - -/* ******************************************************************************** - * Interface to manipulate LED objects. - * ******************************************************************************** */ -#ifdef CONFIG_USB_HCI - void rtl8703bu_InitSwLeds(PADAPTER padapter); - void rtl8703bu_DeInitSwLeds(PADAPTER padapter); -#endif -#ifdef CONFIG_SDIO_HCI - void rtl8703bs_InitSwLeds(PADAPTER padapter); - void rtl8703bs_DeInitSwLeds(PADAPTER padapter); -#endif -#ifdef CONFIG_GSPI_HCI - void rtl8703bs_InitSwLeds(PADAPTER padapter); - void rtl8703bs_DeInitSwLeds(PADAPTER padapter); -#endif -#ifdef CONFIG_PCI_HCI - void rtl8703be_InitSwLeds(PADAPTER padapter); - void rtl8703be_DeInitSwLeds(PADAPTER padapter); -#endif - -#endif diff --git a/include/rtl8703b_recv.h b/include/rtl8703b_recv.h deleted file mode 100644 index c233fe1..0000000 --- a/include/rtl8703b_recv.h +++ /dev/null @@ -1,87 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8703B_RECV_H__ -#define __RTL8703B_RECV_H__ - -#define RECV_BLK_SZ 512 -#define RECV_BLK_CNT 16 -#define RECV_BLK_TH RECV_BLK_CNT - -#if defined(CONFIG_USB_HCI) - - #ifndef MAX_RECVBUF_SZ - #ifndef CONFIG_MINIMAL_MEMORY_USAGE - /* #define MAX_RECVBUF_SZ (32768) */ /* 32k */ - /* #define MAX_RECVBUF_SZ (16384) */ /* 16K */ - /* #define MAX_RECVBUF_SZ (10240) */ /* 10K */ - #ifdef CONFIG_PLATFORM_MSTAR - #define MAX_RECVBUF_SZ (8192) /* 8K */ - #else - #define MAX_RECVBUF_SZ (15360) /* 15k < 16k */ - #endif - /* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */ - #else - #define MAX_RECVBUF_SZ (4000) /* about 4K */ - #endif - #endif /* !MAX_RECVBUF_SZ */ - -#elif defined(CONFIG_PCI_HCI) - /* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */ - /* #define MAX_RECVBUF_SZ (9100) */ - /* #else */ - #define MAX_RECVBUF_SZ (4000) /* about 4K - * #endif */ - - -#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - - #define MAX_RECVBUF_SZ (RX_DMA_SIZE_8703B - RX_DMA_RESERVED_SIZE_8703B) - -#endif - -/* Rx smooth factor */ -#define Rx_Smooth_Factor (20) - -#ifdef CONFIG_SDIO_HCI - #ifndef CONFIG_SDIO_RX_COPY - #undef MAX_RECVBUF_SZ - #define MAX_RECVBUF_SZ (RX_DMA_SIZE_8703B - RX_DMA_RESERVED_SIZE_8703B) - #endif /* !CONFIG_SDIO_RX_COPY */ -#endif /* CONFIG_SDIO_HCI */ - -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - s32 rtl8703bs_init_recv_priv(PADAPTER padapter); - void rtl8703bs_free_recv_priv(PADAPTER padapter); -#endif - -#ifdef CONFIG_USB_HCI - int rtl8703bu_init_recv_priv(_adapter *padapter); - void rtl8703bu_free_recv_priv(_adapter *padapter); - void rtl8703bu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf); -#endif - -#ifdef CONFIG_PCI_HCI - s32 rtl8703be_init_recv_priv(PADAPTER padapter); - void rtl8703be_free_recv_priv(PADAPTER padapter); -#endif - -void rtl8703b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc); - -#endif /* __RTL8703B_RECV_H__ */ diff --git a/include/rtl8703b_rf.h b/include/rtl8703b_rf.h deleted file mode 100644 index 0d3d0aa..0000000 --- a/include/rtl8703b_rf.h +++ /dev/null @@ -1,30 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8703B_RF_H__ -#define __RTL8703B_RF_H__ - -int PHY_RF6052_Config8703B(IN PADAPTER Adapter); - -VOID -PHY_RF6052SetBandwidth8703B( - IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth); - -#endif diff --git a/include/rtl8703b_spec.h b/include/rtl8703b_spec.h deleted file mode 100644 index e9a13d2..0000000 --- a/include/rtl8703b_spec.h +++ /dev/null @@ -1,468 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ -#ifndef __RTL8703B_SPEC_H__ -#define __RTL8703B_SPEC_H__ - -#include - - -#define HAL_NAV_UPPER_UNIT_8703B 128 /* micro-second */ - -/* ----------------------------------------------------- - * - * 0x0000h ~ 0x00FFh System Configuration - * - * ----------------------------------------------------- */ -#define REG_SYS_ISO_CTRL_8703B 0x0000 /* 2 Byte */ -#define REG_SYS_FUNC_EN_8703B 0x0002 /* 2 Byte */ -#define REG_APS_FSMCO_8703B 0x0004 /* 4 Byte */ -#define REG_SYS_CLKR_8703B 0x0008 /* 2 Byte */ -#define REG_9346CR_8703B 0x000A /* 2 Byte */ -#define REG_EE_VPD_8703B 0x000C /* 2 Byte */ -#define REG_AFE_MISC_8703B 0x0010 /* 1 Byte */ -#define REG_SPS0_CTRL_8703B 0x0011 /* 7 Byte */ -#define REG_SPS_OCP_CFG_8703B 0x0018 /* 4 Byte */ -#define REG_RSV_CTRL_8703B 0x001C /* 3 Byte */ -#define REG_RF_CTRL_8703B 0x001F /* 1 Byte */ -#define REG_LPLDO_CTRL_8703B 0x0023 /* 1 Byte */ -#define REG_AFE_XTAL_CTRL_8703B 0x0024 /* 4 Byte */ -#define REG_AFE_PLL_CTRL_8703B 0x0028 /* 4 Byte */ -#define REG_MAC_PLL_CTRL_EXT_8703B 0x002c /* 4 Byte */ -#define REG_EFUSE_CTRL_8703B 0x0030 -#define REG_EFUSE_TEST_8703B 0x0034 -#define REG_PWR_DATA_8703B 0x0038 -#define REG_CAL_TIMER_8703B 0x003C -#define REG_ACLK_MON_8703B 0x003E -#define REG_GPIO_MUXCFG_8703B 0x0040 -#define REG_GPIO_IO_SEL_8703B 0x0042 -#define REG_MAC_PINMUX_CFG_8703B 0x0043 -#define REG_GPIO_PIN_CTRL_8703B 0x0044 -#define REG_GPIO_INTM_8703B 0x0048 -#define REG_LEDCFG0_8703B 0x004C -#define REG_LEDCFG1_8703B 0x004D -#define REG_LEDCFG2_8703B 0x004E -#define REG_LEDCFG3_8703B 0x004F -#define REG_FSIMR_8703B 0x0050 -#define REG_FSISR_8703B 0x0054 -#define REG_HSIMR_8703B 0x0058 -#define REG_HSISR_8703B 0x005c -#define REG_GPIO_EXT_CTRL 0x0060 -#define REG_PAD_CTRL1_8703B 0x0064 -#define REG_MULTI_FUNC_CTRL_8703B 0x0068 -#define REG_GPIO_STATUS_8703B 0x006C -#define REG_SDIO_CTRL_8703B 0x0070 -#define REG_OPT_CTRL_8703B 0x0074 -#define REG_AFE_CTRL_4_8703B 0x0078 -#define REG_MCUFWDL_8703B 0x0080 -#define REG_HMEBOX_DBG_0_8703B 0x0088 -#define REG_HMEBOX_DBG_1_8703B 0x008A -#define REG_HMEBOX_DBG_2_8703B 0x008C -#define REG_HMEBOX_DBG_3_8703B 0x008E -#define REG_HIMR0_8703B 0x00B0 -#define REG_HISR0_8703B 0x00B4 -#define REG_HIMR1_8703B 0x00B8 -#define REG_HISR1_8703B 0x00BC -#define REG_PMC_DBG_CTRL2_8703B 0x00CC -#define REG_EFUSE_BURN_GNT_8703B 0x00CF -#define REG_HPON_FSM_8703B 0x00EC -#define REG_SYS_CFG_8703B 0x00F0 -#define REG_SYS_CFG1_8703B 0x00FC -#define REG_ROM_VERSION 0x00FD - -/* ----------------------------------------------------- - * - * 0x0100h ~ 0x01FFh MACTOP General Configuration - * - * ----------------------------------------------------- */ -#define REG_C2HEVT_CMD_ID_8703B 0x01A0 -#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 -#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 -#define REG_C2HEVT_CMD_LEN_8703B 0x01AE -#define REG_C2HEVT_CMD_LEN_88XX REG_C2HEVT_CMD_LEN_8703B -#define REG_C2HEVT_CLEAR_8703B 0x01AF -#define REG_MCUTST_1_8703B 0x01C0 -#define REG_WOWLAN_WAKE_REASON 0x01C7 -#define REG_FMETHR_8703B 0x01C8 -#define REG_HMETFR_8703B 0x01CC -#define REG_HMEBOX_0_8703B 0x01D0 -#define REG_HMEBOX_1_8703B 0x01D4 -#define REG_HMEBOX_2_8703B 0x01D8 -#define REG_HMEBOX_3_8703B 0x01DC -#define REG_LLT_INIT_8703B 0x01E0 -#define REG_HMEBOX_EXT0_8703B 0x01F0 -#define REG_HMEBOX_EXT1_8703B 0x01F4 -#define REG_HMEBOX_EXT2_8703B 0x01F8 -#define REG_HMEBOX_EXT3_8703B 0x01FC - -/* ----------------------------------------------------- - * - * 0x0200h ~ 0x027Fh TXDMA Configuration - * - * ----------------------------------------------------- */ -#define REG_RQPN_8703B 0x0200 -#define REG_FIFOPAGE_8703B 0x0204 -#define REG_DWBCN0_CTRL_8703B REG_TDECTRL -#define REG_TXDMA_OFFSET_CHK_8703B 0x020C -#define REG_TXDMA_STATUS_8703B 0x0210 -#define REG_RQPN_NPQ_8703B 0x0214 -#define REG_DWBCN1_CTRL_8703B 0x0228 - - -/* ----------------------------------------------------- - * - * 0x0280h ~ 0x02FFh RXDMA Configuration - * - * ----------------------------------------------------- */ -#define REG_RXDMA_AGG_PG_TH_8703B 0x0280 -#define REG_FW_UPD_RDPTR_8703B 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */ -#define REG_RXDMA_CONTROL_8703B 0x0286 /* Control the RX DMA. */ -#define REG_RXPKT_NUM_8703B 0x0287 /* The number of packets in RXPKTBUF. */ -#define REG_RXDMA_STATUS_8703B 0x0288 -#define REG_RXDMA_MODE_CTRL_8703B 0x0290 -#define REG_EARLY_MODE_CONTROL_8703B 0x02BC -#define REG_RSVD5_8703B 0x02F0 -#define REG_RSVD6_8703B 0x02F4 - -/* ----------------------------------------------------- - * - * 0x0300h ~ 0x03FFh PCIe - * - * ----------------------------------------------------- */ -#define REG_PCIE_CTRL_REG_8703B 0x0300 -#define REG_INT_MIG_8703B 0x0304 /* Interrupt Migration */ -#define REG_BCNQ_DESA_8703B 0x0308 /* TX Beacon Descriptor Address */ -#define REG_HQ_DESA_8703B 0x0310 /* TX High Queue Descriptor Address */ -#define REG_MGQ_DESA_8703B 0x0318 /* TX Manage Queue Descriptor Address */ -#define REG_VOQ_DESA_8703B 0x0320 /* TX VO Queue Descriptor Address */ -#define REG_VIQ_DESA_8703B 0x0328 /* TX VI Queue Descriptor Address */ -#define REG_BEQ_DESA_8703B 0x0330 /* TX BE Queue Descriptor Address */ -#define REG_BKQ_DESA_8703B 0x0338 /* TX BK Queue Descriptor Address */ -#define REG_RX_DESA_8703B 0x0340 /* RX Queue Descriptor Address */ -#define REG_DBI_WDATA_8703B 0x0348 /* DBI Write Data */ -#define REG_DBI_RDATA_8703B 0x034C /* DBI Read Data */ -#define REG_DBI_ADDR_8703B 0x0350 /* DBI Address */ -#define REG_DBI_FLAG_8703B 0x0352 /* DBI Read/Write Flag */ -#define REG_MDIO_WDATA_8703B 0x0354 /* MDIO for Write PCIE PHY */ -#define REG_MDIO_RDATA_8703B 0x0356 /* MDIO for Reads PCIE PHY */ -#define REG_MDIO_CTL_8703B 0x0358 /* MDIO for Control */ -#define REG_DBG_SEL_8703B 0x0360 /* Debug Selection Register */ -#define REG_PCIE_HRPWM_8703B 0x0361 /* PCIe RPWM */ -#define REG_PCIE_HCPWM_8703B 0x0363 /* PCIe CPWM */ -#define REG_PCIE_MULTIFET_CTRL_8703B 0x036A /* PCIE Multi-Fethc Control */ - -/* ----------------------------------------------------- - * - * 0x0400h ~ 0x047Fh Protocol Configuration - * - * ----------------------------------------------------- */ -#define REG_VOQ_INFORMATION_8703B 0x0400 -#define REG_VIQ_INFORMATION_8703B 0x0404 -#define REG_BEQ_INFORMATION_8703B 0x0408 -#define REG_BKQ_INFORMATION_8703B 0x040C -#define REG_MGQ_INFORMATION_8703B 0x0410 -#define REG_HGQ_INFORMATION_8703B 0x0414 -#define REG_BCNQ_INFORMATION_8703B 0x0418 -#define REG_TXPKT_EMPTY_8703B 0x041A - -#define REG_FWHW_TXQ_CTRL_8703B 0x0420 -#define REG_HWSEQ_CTRL_8703B 0x0423 -#define REG_TXPKTBUF_BCNQ_BDNY_8703B 0x0424 -#define REG_TXPKTBUF_MGQ_BDNY_8703B 0x0425 -#define REG_LIFECTRL_CTRL_8703B 0x0426 -#define REG_MULTI_BCNQ_OFFSET_8703B 0x0427 -#define REG_SPEC_SIFS_8703B 0x0428 -#define REG_RL_8703B 0x042A -#define REG_TXBF_CTRL_8703B 0x042C -#define REG_DARFRC_8703B 0x0430 -#define REG_RARFRC_8703B 0x0438 -#define REG_RRSR_8703B 0x0440 -#define REG_ARFR0_8703B 0x0444 -#define REG_ARFR1_8703B 0x044C -#define REG_CCK_CHECK_8703B 0x0454 -#define REG_AMPDU_MAX_TIME_8703B 0x0456 -#define REG_TXPKTBUF_BCNQ_BDNY1_8703B 0x0457 - -#define REG_AMPDU_MAX_LENGTH_8703B 0x0458 -#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8703B 0x045D -#define REG_NDPA_OPT_CTRL_8703B 0x045F -#define REG_FAST_EDCA_CTRL_8703B 0x0460 -#define REG_RD_RESP_PKT_TH_8703B 0x0463 -#define REG_DATA_SC_8703B 0x0483 -#ifdef CONFIG_WOWLAN - #define REG_TXPKTBUF_IV_LOW 0x0484 - #define REG_TXPKTBUF_IV_HIGH 0x0488 -#endif -#define REG_TXRPT_START_OFFSET 0x04AC -#define REG_POWER_STAGE1_8703B 0x04B4 -#define REG_POWER_STAGE2_8703B 0x04B8 -#define REG_AMPDU_BURST_MODE_8703B 0x04BC -#define REG_PKT_VO_VI_LIFE_TIME_8703B 0x04C0 -#define REG_PKT_BE_BK_LIFE_TIME_8703B 0x04C2 -#define REG_STBC_SETTING_8703B 0x04C4 -#define REG_HT_SINGLE_AMPDU_8703B 0x04C7 -#define REG_PROT_MODE_CTRL_8703B 0x04C8 -#define REG_MAX_AGGR_NUM_8703B 0x04CA -#define REG_RTS_MAX_AGGR_NUM_8703B 0x04CB -#define REG_BAR_MODE_CTRL_8703B 0x04CC -#define REG_RA_TRY_RATE_AGG_LMT_8703B 0x04CF -#define REG_MACID_PKT_DROP0_8703B 0x04D0 -#define REG_MACID_PKT_SLEEP_8703B 0x04D4 - -/* ----------------------------------------------------- - * - * 0x0500h ~ 0x05FFh EDCA Configuration - * - * ----------------------------------------------------- */ -#define REG_EDCA_VO_PARAM_8703B 0x0500 -#define REG_EDCA_VI_PARAM_8703B 0x0504 -#define REG_EDCA_BE_PARAM_8703B 0x0508 -#define REG_EDCA_BK_PARAM_8703B 0x050C -#define REG_BCNTCFG_8703B 0x0510 -#define REG_PIFS_8703B 0x0512 -#define REG_RDG_PIFS_8703B 0x0513 -#define REG_SIFS_CTX_8703B 0x0514 -#define REG_SIFS_TRX_8703B 0x0516 -#define REG_AGGR_BREAK_TIME_8703B 0x051A -#define REG_SLOT_8703B 0x051B -#define REG_TX_PTCL_CTRL_8703B 0x0520 -#define REG_TXPAUSE_8703B 0x0522 -#define REG_DIS_TXREQ_CLR_8703B 0x0523 -#define REG_RD_CTRL_8703B 0x0524 -/* - * Format for offset 540h-542h: - * [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. - * [7:4]: Reserved. - * [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. - * [23:20]: Reserved - * Description: - * | - * |<--Setup--|--Hold------------>| - * --------------|---------------------- - * | - * TBTT - * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. - * Described by Designer Tim and Bruce, 2011-01-14. - * */ -#define REG_TBTT_PROHIBIT_8703B 0x0540 -#define REG_RD_NAV_NXT_8703B 0x0544 -#define REG_NAV_PROT_LEN_8703B 0x0546 -#define REG_BCN_CTRL_8703B 0x0550 -#define REG_BCN_CTRL_1_8703B 0x0551 -#define REG_MBID_NUM_8703B 0x0552 -#define REG_DUAL_TSF_RST_8703B 0x0553 -#define REG_BCN_INTERVAL_8703B 0x0554 -#define REG_DRVERLYINT_8703B 0x0558 -#define REG_BCNDMATIM_8703B 0x0559 -#define REG_ATIMWND_8703B 0x055A -#define REG_USTIME_TSF_8703B 0x055C -#define REG_BCN_MAX_ERR_8703B 0x055D -#define REG_RXTSF_OFFSET_CCK_8703B 0x055E -#define REG_RXTSF_OFFSET_OFDM_8703B 0x055F -#define REG_TSFTR_8703B 0x0560 -#define REG_CTWND_8703B 0x0572 -#define REG_SECONDARY_CCA_CTRL_8703B 0x0577 -#define REG_PSTIMER_8703B 0x0580 -#define REG_TIMER0_8703B 0x0584 -#define REG_TIMER1_8703B 0x0588 -#define REG_ACMHWCTRL_8703B 0x05C0 -#define REG_SCH_TXCMD_8703B 0x05F8 - -/* ----------------------------------------------------- - * - * 0x0600h ~ 0x07FFh WMAC Configuration - * - * ----------------------------------------------------- */ -#define REG_MAC_CR_8703B 0x0600 -#define REG_TCR_8703B 0x0604 -#define REG_RCR_8703B 0x0608 -#define REG_RX_PKT_LIMIT_8703B 0x060C -#define REG_RX_DLK_TIME_8703B 0x060D -#define REG_RX_DRVINFO_SZ_8703B 0x060F - -#define REG_MACID_8703B 0x0610 -#define REG_BSSID_8703B 0x0618 -#define REG_MAR_8703B 0x0620 -#define REG_MBIDCAMCFG_8703B 0x0628 -#define REG_WOWLAN_GTK_DBG1 0x630 -#define REG_WOWLAN_GTK_DBG2 0x634 - -#define REG_USTIME_EDCA_8703B 0x0638 -#define REG_MAC_SPEC_SIFS_8703B 0x063A -#define REG_RESP_SIFP_CCK_8703B 0x063C -#define REG_RESP_SIFS_OFDM_8703B 0x063E -#define REG_ACKTO_8703B 0x0640 -#define REG_CTS2TO_8703B 0x0641 -#define REG_EIFS_8703B 0x0642 - -#define REG_NAV_UPPER_8703B 0x0652 /* unit of 128 */ -#define REG_TRXPTCL_CTL_8703B 0x0668 - -/* Security */ -#define REG_CAMCMD_8703B 0x0670 -#define REG_CAMWRITE_8703B 0x0674 -#define REG_CAMREAD_8703B 0x0678 -#define REG_CAMDBG_8703B 0x067C -#define REG_SECCFG_8703B 0x0680 - -/* Power */ -#define REG_WOW_CTRL_8703B 0x0690 -#define REG_PS_RX_INFO_8703B 0x0692 -#define REG_UAPSD_TID_8703B 0x0693 -#define REG_WKFMCAM_CMD_8703B 0x0698 -#define REG_WKFMCAM_NUM_8703B 0x0698 -#define REG_WKFMCAM_RWD_8703B 0x069C -#define REG_RXFLTMAP0_8703B 0x06A0 -#define REG_RXFLTMAP1_8703B 0x06A2 -#define REG_RXFLTMAP2_8703B 0x06A4 -#define REG_BCN_PSR_RPT_8703B 0x06A8 -#define REG_BT_COEX_TABLE_8703B 0x06C0 -#define REG_BFMER0_INFO_8703B 0x06E4 -#define REG_BFMER1_INFO_8703B 0x06EC -#define REG_CSI_RPT_PARAM_BW20_8703B 0x06F4 -#define REG_CSI_RPT_PARAM_BW40_8703B 0x06F8 -#define REG_CSI_RPT_PARAM_BW80_8703B 0x06FC - -/* Hardware Port 2 */ -#define REG_MACID1_8703B 0x0700 -#define REG_BSSID1_8703B 0x0708 -#define REG_BFMEE_SEL_8703B 0x0714 -#define REG_SND_PTCL_CTRL_8703B 0x0718 - -/* LTE_COEX */ -#define REG_LTECOEX_CTRL 0x07C0 -#define REG_LTECOEX_WRITE_DATA 0x07C4 -#define REG_LTECOEX_READ_DATA 0x07C8 -#define REG_LTECOEX_PATH_CONTROL 0x70 - -/* ************************************************************ - * SDIO Bus Specification - * ************************************************************ */ - -/* ----------------------------------------------------- - * SDIO CMD Address Mapping - * ----------------------------------------------------- */ - -/* ----------------------------------------------------- - * I/O bus domain (Host) - * ----------------------------------------------------- */ - -/* ----------------------------------------------------- - * SDIO register - * ----------------------------------------------------- */ -#define SDIO_REG_HCPWM1_8703B 0x025 /* HCI Current Power Mode 1 */ - - -/* **************************************************************************** - * 8703 Regsiter Bit and Content definition - * **************************************************************************** */ - -#define BIT_USB_RXDMA_AGG_EN BIT(31) -#define RXDMA_AGG_MODE_EN BIT(1) - -#ifdef CONFIG_WOWLAN - #define RXPKT_RELEASE_POLL BIT(16) - #define RXDMA_IDLE BIT(17) - #define RW_RELEASE_EN BIT(18) -#endif - -/* 2 HSISR - * interrupt mask which needs to clear */ -#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\ - HSISR_SPS_OCP_INT |\ - HSISR_RON_INT |\ - HSISR_PDNINT |\ - HSISR_GPIO9_INT) - - -/* ---------------------------------------------------------------------------- - * 8703B REG_CCK_CHECK (offset 0x454) - * ---------------------------------------------------------------------------- */ -#define BIT_BCN_PORT_SEL BIT(5) - -#ifdef CONFIG_RF_POWER_TRIM - - #ifdef CONFIG_RTL8703B - #define EEPROM_RF_GAIN_OFFSET 0xC1 - #endif - - #define EEPROM_RF_GAIN_VAL 0x1F6 -#endif /*CONFIG_RF_POWER_TRIM*/ - - -/* ---------------------------------------------------------------------------- - * 8195 IMR/ISR bits (offset 0xB0, 8bits) - * ---------------------------------------------------------------------------- */ -#define IMR_DISABLED_8703B 0 -/* IMR DW0(0x00B0-00B3) Bit 0-31 */ -#define IMR_TIMER2_8703B BIT(31) /* Timeout interrupt 2 */ -#define IMR_TIMER1_8703B BIT(30) /* Timeout interrupt 1 */ -#define IMR_PSTIMEOUT_8703B BIT(29) /* Power Save Time Out Interrupt */ -#define IMR_GTINT4_8703B BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ -#define IMR_GTINT3_8703B BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ -#define IMR_TXBCN0ERR_8703B BIT(26) /* Transmit Beacon0 Error */ -#define IMR_TXBCN0OK_8703B BIT(25) /* Transmit Beacon0 OK */ -#define IMR_TSF_BIT32_TOGGLE_8703B BIT(24) /* TSF Timer BIT32 toggle indication interrupt */ -#define IMR_BCNDMAINT0_8703B BIT(20) /* Beacon DMA Interrupt 0 */ -#define IMR_BCNDERR0_8703B BIT(16) /* Beacon Queue DMA OK0 */ -#define IMR_HSISR_IND_ON_INT_8703B BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ -#define IMR_BCNDMAINT_E_8703B BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ -#define IMR_ATIMEND_8703B BIT(12) /* CTWidnow End or ATIM Window End */ -#define IMR_C2HCMD_8703B BIT(10) /* CPU to Host Command INT Status, Write 1 clear */ -#define IMR_CPWM2_8703B BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_CPWM_8703B BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_HIGHDOK_8703B BIT(7) /* High Queue DMA OK */ -#define IMR_MGNTDOK_8703B BIT(6) /* Management Queue DMA OK */ -#define IMR_BKDOK_8703B BIT(5) /* AC_BK DMA OK */ -#define IMR_BEDOK_8703B BIT(4) /* AC_BE DMA OK */ -#define IMR_VIDOK_8703B BIT(3) /* AC_VI DMA OK */ -#define IMR_VODOK_8703B BIT(2) /* AC_VO DMA OK */ -#define IMR_RDU_8703B BIT(1) /* Rx Descriptor Unavailable */ -#define IMR_ROK_8703B BIT(0) /* Receive DMA OK */ - -/* IMR DW1(0x00B4-00B7) Bit 0-31 */ -#define IMR_BCNDMAINT7_8703B BIT(27) /* Beacon DMA Interrupt 7 */ -#define IMR_BCNDMAINT6_8703B BIT(26) /* Beacon DMA Interrupt 6 */ -#define IMR_BCNDMAINT5_8703B BIT(25) /* Beacon DMA Interrupt 5 */ -#define IMR_BCNDMAINT4_8703B BIT(24) /* Beacon DMA Interrupt 4 */ -#define IMR_BCNDMAINT3_8703B BIT(23) /* Beacon DMA Interrupt 3 */ -#define IMR_BCNDMAINT2_8703B BIT(22) /* Beacon DMA Interrupt 2 */ -#define IMR_BCNDMAINT1_8703B BIT(21) /* Beacon DMA Interrupt 1 */ -#define IMR_BCNDOK7_8703B BIT(20) /* Beacon Queue DMA OK Interrupt 7 */ -#define IMR_BCNDOK6_8703B BIT(19) /* Beacon Queue DMA OK Interrupt 6 */ -#define IMR_BCNDOK5_8703B BIT(18) /* Beacon Queue DMA OK Interrupt 5 */ -#define IMR_BCNDOK4_8703B BIT(17) /* Beacon Queue DMA OK Interrupt 4 */ -#define IMR_BCNDOK3_8703B BIT(16) /* Beacon Queue DMA OK Interrupt 3 */ -#define IMR_BCNDOK2_8703B BIT(15) /* Beacon Queue DMA OK Interrupt 2 */ -#define IMR_BCNDOK1_8703B BIT(14) /* Beacon Queue DMA OK Interrupt 1 */ -#define IMR_ATIMEND_E_8703B BIT(13) /* ATIM Window End Extension for Win7 */ -#define IMR_TXERR_8703B BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */ -#define IMR_RXERR_8703B BIT(10) /* Rx Error Flag INT Status, Write 1 clear */ -#define IMR_TXFOVW_8703B BIT(9) /* Transmit FIFO Overflow */ -#define IMR_RXFOVW_8703B BIT(8) /* Receive FIFO Overflow */ - -#ifdef CONFIG_PCI_HCI - /* #define IMR_RX_MASK (IMR_ROK_8703B|IMR_RDU_8703B|IMR_RXFOVW_8703B) */ - #define IMR_TX_MASK (IMR_VODOK_8703B | IMR_VIDOK_8703B | IMR_BEDOK_8703B | IMR_BKDOK_8703B | IMR_MGNTDOK_8703B | IMR_HIGHDOK_8703B) - - #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8703B | IMR_TXBCN0OK_8703B | IMR_TXBCN0ERR_8703B | IMR_BCNDERR0_8703B) - - #define RT_AC_INT_MASKS (IMR_VIDOK_8703B | IMR_VODOK_8703B | IMR_BEDOK_8703B | IMR_BKDOK_8703B) -#endif - -#endif /* __RTL8703B_SPEC_H__ */ diff --git a/include/rtl8703b_sreset.h b/include/rtl8703b_sreset.h deleted file mode 100644 index fbed1fb..0000000 --- a/include/rtl8703b_sreset.h +++ /dev/null @@ -1,29 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef _RTL8703B_SRESET_H_ -#define _RTL8703B_SRESET_H_ - -#include - -#ifdef DBG_CONFIG_ERROR_DETECT - extern void rtl8703b_sreset_xmit_status_check(_adapter *padapter); - extern void rtl8703b_sreset_linked_status_check(_adapter *padapter); -#endif -#endif diff --git a/include/rtl8703b_xmit.h b/include/rtl8703b_xmit.h deleted file mode 100644 index c44609c..0000000 --- a/include/rtl8703b_xmit.h +++ /dev/null @@ -1,338 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8703B_XMIT_H__ -#define __RTL8703B_XMIT_H__ - - -#define MAX_TID (15) - - -#ifndef __INC_HAL8703BDESC_H - #define __INC_HAL8703BDESC_H - - #define RX_STATUS_DESC_SIZE_8703B 24 - #define RX_DRV_INFO_SIZE_UNIT_8703B 8 - - - /* DWORD 0 */ - #define SET_RX_STATUS_DESC_PKT_LEN_8703B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value) - #define SET_RX_STATUS_DESC_EOR_8703B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value) - #define SET_RX_STATUS_DESC_OWN_8703B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value) - - #define GET_RX_STATUS_DESC_PKT_LEN_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14) - #define GET_RX_STATUS_DESC_CRC32_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1) - #define GET_RX_STATUS_DESC_ICV_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1) - #define GET_RX_STATUS_DESC_DRVINFO_SIZE_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4) - #define GET_RX_STATUS_DESC_SECURITY_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3) - #define GET_RX_STATUS_DESC_QOS_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1) - #define GET_RX_STATUS_DESC_SHIFT_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2) - #define GET_RX_STATUS_DESC_PHY_STATUS_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1) - #define GET_RX_STATUS_DESC_SWDEC_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1) - #define GET_RX_STATUS_DESC_LAST_SEG_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1) - #define GET_RX_STATUS_DESC_FIRST_SEG_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1) - #define GET_RX_STATUS_DESC_EOR_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1) - #define GET_RX_STATUS_DESC_OWN_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1) - - /* DWORD 1 */ - #define GET_RX_STATUS_DESC_MACID_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7) - #define GET_RX_STATUS_DESC_TID_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4) - #define GET_RX_STATUS_DESC_AMSDU_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1) - #define GET_RX_STATUS_DESC_RXID_MATCH_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1) - #define GET_RX_STATUS_DESC_PAGGR_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1) - #define GET_RX_STATUS_DESC_A1_FIT_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4) - #define GET_RX_STATUS_DESC_CHKERR_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1) - #define GET_RX_STATUS_DESC_IPVER_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1) - #define GET_RX_STATUS_DESC_IS_TCPUDP__8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1) - #define GET_RX_STATUS_DESC_CHK_VLD_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1) - #define GET_RX_STATUS_DESC_PAM_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1) - #define GET_RX_STATUS_DESC_PWR_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1) - #define GET_RX_STATUS_DESC_MORE_DATA_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1) - #define GET_RX_STATUS_DESC_MORE_FRAG_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1) - #define GET_RX_STATUS_DESC_TYPE_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2) - #define GET_RX_STATUS_DESC_MC_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1) - #define GET_RX_STATUS_DESC_BC_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1) - - /* DWORD 2 */ - #define GET_RX_STATUS_DESC_SEQ_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12) - #define GET_RX_STATUS_DESC_FRAG_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4) - #define GET_RX_STATUS_DESC_RX_IS_QOS_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1) - #define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6) - #define GET_RX_STATUS_DESC_RPT_SEL_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1) - - /* DWORD 3 */ - #define GET_RX_STATUS_DESC_RX_RATE_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7) - #define GET_RX_STATUS_DESC_HTC_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1) - #define GET_RX_STATUS_DESC_EOSP_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1) - #define GET_RX_STATUS_DESC_BSSID_FIT_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2) - #ifdef CONFIG_USB_RX_AGGREGATION - #define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8) - #endif - #define GET_RX_STATUS_DESC_PATTERN_MATCH_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1) - #define GET_RX_STATUS_DESC_UNICAST_MATCH_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1) - #define GET_RX_STATUS_DESC_MAGIC_MATCH_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1) - - /* DWORD 6 */ - #define GET_RX_STATUS_DESC_SPLCP_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1) - #define GET_RX_STATUS_DESC_LDPC_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1) - #define GET_RX_STATUS_DESC_STBC_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1) - #define GET_RX_STATUS_DESC_BW_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2) - - /* DWORD 5 */ - #define GET_RX_STATUS_DESC_TSFL_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32) - - #define GET_RX_STATUS_DESC_BUFF_ADDR_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32) - #define GET_RX_STATUS_DESC_BUFF_ADDR64_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32) - - #define SET_RX_STATUS_DESC_BUFF_ADDR_8703B(__pRxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value) - - - /* Dword 0 */ - #define GET_TX_DESC_OWN_8703B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1) - - #define SET_TX_DESC_PKT_SIZE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value) - #define SET_TX_DESC_OFFSET_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value) - #define SET_TX_DESC_BMC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value) - #define SET_TX_DESC_HTC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value) - #define SET_TX_DESC_LAST_SEG_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value) - #define SET_TX_DESC_FIRST_SEG_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value) - #define SET_TX_DESC_LINIP_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value) - #define SET_TX_DESC_NO_ACM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value) - #define SET_TX_DESC_GF_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value) - #define SET_TX_DESC_OWN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) - - /* Dword 1 */ - #define SET_TX_DESC_MACID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value) - #define SET_TX_DESC_QUEUE_SEL_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value) - #define SET_TX_DESC_RDG_NAV_EXT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value) - #define SET_TX_DESC_LSIG_TXOP_EN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value) - #define SET_TX_DESC_PIFS_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value) - #define SET_TX_DESC_RATE_ID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value) - #define SET_TX_DESC_EN_DESC_ID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value) - #define SET_TX_DESC_SEC_TYPE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value) - #define SET_TX_DESC_PKT_OFFSET_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value) - - - /* Dword 2 */ - #define SET_TX_DESC_PAID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value) - #define SET_TX_DESC_CCA_RTS_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value) - #define SET_TX_DESC_AGG_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value) - #define SET_TX_DESC_RDG_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value) - #define SET_TX_DESC_AGG_BREAK_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value) - #define SET_TX_DESC_MORE_FRAG_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value) - #define SET_TX_DESC_RAW_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value) - #define SET_TX_DESC_SPE_RPT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value) - #define SET_TX_DESC_AMPDU_DENSITY_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value) - #define SET_TX_DESC_BT_INT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value) - #define SET_TX_DESC_GID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value) - - - /* Dword 3 */ - #define SET_TX_DESC_WHEADER_LEN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value) - #define SET_TX_DESC_CHK_EN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value) - #define SET_TX_DESC_EARLY_MODE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value) - #define SET_TX_DESC_HWSEQ_SEL_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value) - #define SET_TX_DESC_USE_RATE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value) - #define SET_TX_DESC_DISABLE_RTS_FB_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value) - #define SET_TX_DESC_DISABLE_FB_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value) - #define SET_TX_DESC_CTS2SELF_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value) - #define SET_TX_DESC_RTS_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value) - #define SET_TX_DESC_HW_RTS_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value) - #define SET_TX_DESC_NAV_USE_HDR_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value) - #define SET_TX_DESC_USE_MAX_LEN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value) - #define SET_TX_DESC_MAX_AGG_NUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value) - #define SET_TX_DESC_NDPA_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value) - #define SET_TX_DESC_AMPDU_MAX_TIME_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value) - - /* Dword 4 */ - #define SET_TX_DESC_TX_RATE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value) - #define SET_TX_DESC_DATA_RATE_FB_LIMIT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value) - #define SET_TX_DESC_RTS_RATE_FB_LIMIT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value) - #define SET_TX_DESC_RETRY_LIMIT_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value) - #define SET_TX_DESC_DATA_RETRY_LIMIT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value) - #define SET_TX_DESC_RTS_RATE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value) - - - /* Dword 5 */ - #define SET_TX_DESC_DATA_SC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value) - #define SET_TX_DESC_DATA_SHORT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value) - #define SET_TX_DESC_DATA_BW_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value) - #define SET_TX_DESC_DATA_LDPC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value) - #define SET_TX_DESC_DATA_STBC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value) - #define SET_TX_DESC_CTROL_STBC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value) - #define SET_TX_DESC_RTS_SHORT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value) - #define SET_TX_DESC_RTS_SC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value) - - - /* Dword 6 */ - #define SET_TX_DESC_SW_DEFINE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value) - #define SET_TX_DESC_MBSSID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value) - #define SET_TX_DESC_ANTSEL_A_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value) - #define SET_TX_DESC_ANTSEL_B_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value) - #define SET_TX_DESC_ANTSEL_C_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value) - #define SET_TX_DESC_ANTSEL_D_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value) - - /* Dword 7 */ - #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) - #define SET_TX_DESC_TX_BUFFER_SIZE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) - #else - #define SET_TX_DESC_TX_DESC_CHECKSUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) - #endif - #define SET_TX_DESC_USB_TXAGG_NUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) - #if (DEV_BUS_TYPE == RT_SDIO_INTERFACE) - #define SET_TX_DESC_SDIO_TXSEQ_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value) - #endif - - /* Dword 8 */ - #define SET_TX_DESC_HWSEQ_EN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) - - /* Dword 9 */ - #define SET_TX_DESC_SEQ_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value) - - /* Dword 10 */ - #define SET_TX_DESC_TX_BUFFER_ADDRESS_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value) - #define GET_TX_DESC_TX_BUFFER_ADDRESS_8703B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32) - - /* Dword 11 */ - #define SET_TX_DESC_NEXT_DESC_ADDRESS_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value) - - - #define SET_EARLYMODE_PKTNUM_8703B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value) - #define SET_EARLYMODE_LEN0_8703B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value) - #define SET_EARLYMODE_LEN1_1_8703B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value) - #define SET_EARLYMODE_LEN1_2_8703B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value) - #define SET_EARLYMODE_LEN2_8703B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value) - #define SET_EARLYMODE_LEN3_8703B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value) - -#endif -/* ----------------------------------------------------------- - * - * Rate - * - * ----------------------------------------------------------- - * CCK Rates, TxHT = 0 */ -#define DESC8703B_RATE1M 0x00 -#define DESC8703B_RATE2M 0x01 -#define DESC8703B_RATE5_5M 0x02 -#define DESC8703B_RATE11M 0x03 - -/* OFDM Rates, TxHT = 0 */ -#define DESC8703B_RATE6M 0x04 -#define DESC8703B_RATE9M 0x05 -#define DESC8703B_RATE12M 0x06 -#define DESC8703B_RATE18M 0x07 -#define DESC8703B_RATE24M 0x08 -#define DESC8703B_RATE36M 0x09 -#define DESC8703B_RATE48M 0x0a -#define DESC8703B_RATE54M 0x0b - -/* MCS Rates, TxHT = 1 */ -#define DESC8703B_RATEMCS0 0x0c -#define DESC8703B_RATEMCS1 0x0d -#define DESC8703B_RATEMCS2 0x0e -#define DESC8703B_RATEMCS3 0x0f -#define DESC8703B_RATEMCS4 0x10 -#define DESC8703B_RATEMCS5 0x11 -#define DESC8703B_RATEMCS6 0x12 -#define DESC8703B_RATEMCS7 0x13 -#define DESC8703B_RATEMCS8 0x14 -#define DESC8703B_RATEMCS9 0x15 -#define DESC8703B_RATEMCS10 0x16 -#define DESC8703B_RATEMCS11 0x17 -#define DESC8703B_RATEMCS12 0x18 -#define DESC8703B_RATEMCS13 0x19 -#define DESC8703B_RATEMCS14 0x1a -#define DESC8703B_RATEMCS15 0x1b -#define DESC8703B_RATEVHTSS1MCS0 0x2c -#define DESC8703B_RATEVHTSS1MCS1 0x2d -#define DESC8703B_RATEVHTSS1MCS2 0x2e -#define DESC8703B_RATEVHTSS1MCS3 0x2f -#define DESC8703B_RATEVHTSS1MCS4 0x30 -#define DESC8703B_RATEVHTSS1MCS5 0x31 -#define DESC8703B_RATEVHTSS1MCS6 0x32 -#define DESC8703B_RATEVHTSS1MCS7 0x33 -#define DESC8703B_RATEVHTSS1MCS8 0x34 -#define DESC8703B_RATEVHTSS1MCS9 0x35 -#define DESC8703B_RATEVHTSS2MCS0 0x36 -#define DESC8703B_RATEVHTSS2MCS1 0x37 -#define DESC8703B_RATEVHTSS2MCS2 0x38 -#define DESC8703B_RATEVHTSS2MCS3 0x39 -#define DESC8703B_RATEVHTSS2MCS4 0x3a -#define DESC8703B_RATEVHTSS2MCS5 0x3b -#define DESC8703B_RATEVHTSS2MCS6 0x3c -#define DESC8703B_RATEVHTSS2MCS7 0x3d -#define DESC8703B_RATEVHTSS2MCS8 0x3e -#define DESC8703B_RATEVHTSS2MCS9 0x3f - - -#define RX_HAL_IS_CCK_RATE_8703B(pDesc)\ - (GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE1M || \ - GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE2M || \ - GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE5_5M || \ - GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE11M) - - -void rtl8703b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem); -void rtl8703b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); -#if defined(CONFIG_CONCURRENT_MODE) - void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); -#endif - -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - s32 rtl8703bs_init_xmit_priv(PADAPTER padapter); - void rtl8703bs_free_xmit_priv(PADAPTER padapter); - s32 rtl8703bs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 rtl8703bs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); - s32 rtl8703bs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); - s32 rtl8703bs_xmit_buf_handler(PADAPTER padapter); - thread_return rtl8703bs_xmit_thread(thread_context context); - #define hal_xmit_handler rtl8703bs_xmit_buf_handler -#endif - -#ifdef CONFIG_USB_HCI - s32 rtl8703bu_xmit_buf_handler(PADAPTER padapter); - #define hal_xmit_handler rtl8703bu_xmit_buf_handler - - - s32 rtl8703bu_init_xmit_priv(PADAPTER padapter); - void rtl8703bu_free_xmit_priv(PADAPTER padapter); - s32 rtl8703bu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 rtl8703bu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); - s32 rtl8703bu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); - /* s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); */ - void rtl8703bu_xmit_tasklet(void *priv); - s32 rtl8703bu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); - void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, struct tx_desc *ptxdesc); -#endif - -#ifdef CONFIG_PCI_HCI - s32 rtl8703be_init_xmit_priv(PADAPTER padapter); - void rtl8703be_free_xmit_priv(PADAPTER padapter); - struct xmit_buf *rtl8703be_dequeue_xmitbuf(struct rtw_tx_ring *ring); - void rtl8703be_xmitframe_resume(_adapter *padapter); - s32 rtl8703be_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 rtl8703be_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); - s32 rtl8703be_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); - void rtl8703be_xmit_tasklet(void *priv); -#endif - -u8 BWMapping_8703B(PADAPTER Adapter, struct pkt_attrib *pattrib); -u8 SCMapping_8703B(PADAPTER Adapter, struct pkt_attrib *pattrib); - -#endif diff --git a/include/rtl8723b_cmd.h b/include/rtl8723b_cmd.h deleted file mode 100644 index 1000d20..0000000 --- a/include/rtl8723b_cmd.h +++ /dev/null @@ -1,218 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8723B_CMD_H__ -#define __RTL8723B_CMD_H__ - -/* --------------------------------------------------------------------------------------------------------- - * ---------------------------------- H2C CMD DEFINITION ------------------------------------------------ - * --------------------------------------------------------------------------------------------------------- */ - -enum h2c_cmd_8723B { - /* Common Class: 000 */ - H2C_8723B_RSVD_PAGE = 0x00, - H2C_8723B_MEDIA_STATUS_RPT = 0x01, - H2C_8723B_SCAN_ENABLE = 0x02, - H2C_8723B_KEEP_ALIVE = 0x03, - H2C_8723B_DISCON_DECISION = 0x04, - H2C_8723B_PSD_OFFLOAD = 0x05, - H2C_8723B_AP_OFFLOAD = 0x08, - H2C_8723B_BCN_RSVDPAGE = 0x09, - H2C_8723B_PROBERSP_RSVDPAGE = 0x0A, - H2C_8723B_FCS_RSVDPAGE = 0x10, - H2C_8723B_FCS_INFO = 0x11, - H2C_8723B_AP_WOW_GPIO_CTRL = 0x13, - - /* PoweSave Class: 001 */ - H2C_8723B_SET_PWR_MODE = 0x20, - H2C_8723B_PS_TUNING_PARA = 0x21, - H2C_8723B_PS_TUNING_PARA2 = 0x22, - H2C_8723B_P2P_LPS_PARAM = 0x23, - H2C_8723B_P2P_PS_OFFLOAD = 0x24, - H2C_8723B_PS_SCAN_ENABLE = 0x25, - H2C_8723B_SAP_PS_ = 0x26, - H2C_8723B_INACTIVE_PS_ = 0x27, /* Inactive_PS */ - H2C_8723B_FWLPS_IN_IPS_ = 0x28, - - /* Dynamic Mechanism Class: 010 */ - H2C_8723B_MACID_CFG = 0x40, - H2C_8723B_TXBF = 0x41, - H2C_8723B_RSSI_SETTING = 0x42, - H2C_8723B_AP_REQ_TXRPT = 0x43, - H2C_8723B_INIT_RATE_COLLECT = 0x44, - H2C_8723B_RA_PARA_ADJUST = 0x46, - - /* BT Class: 011 */ - H2C_8723B_B_TYPE_TDMA = 0x60, - H2C_8723B_BT_INFO = 0x61, - H2C_8723B_FORCE_BT_TXPWR = 0x62, - H2C_8723B_BT_IGNORE_WLANACT = 0x63, - H2C_8723B_DAC_SWING_VALUE = 0x64, - H2C_8723B_ANT_SEL_RSV = 0x65, - H2C_8723B_WL_OPMODE = 0x66, - H2C_8723B_BT_MP_OPER = 0x67, - H2C_8723B_BT_CONTROL = 0x68, - H2C_8723B_BT_WIFI_CTRL = 0x69, - H2C_8723B_BT_FW_PATCH = 0x6A, - H2C_8723B_BT_WLAN_CALIBRATION = 0x6D, - - /* WOWLAN Class: 100 */ - H2C_8723B_WOWLAN = 0x80, - H2C_8723B_REMOTE_WAKE_CTRL = 0x81, - H2C_8723B_AOAC_GLOBAL_INFO = 0x82, - H2C_8723B_AOAC_RSVD_PAGE = 0x83, - H2C_8723B_AOAC_RSVD_PAGE2 = 0x84, - H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85, - H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86, - H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87, - H2C_8723B_P2P_OFFLOAD_RSVD_PAGE = 0x8A, - H2C_8723B_P2P_OFFLOAD = 0x8B, - - H2C_8723B_RESET_TSF = 0xC0, - H2C_8723B_MAXID, -}; - -/* --------------------------------------------------------------------------------------------------------- - * ---------------------------------- H2C CMD CONTENT -------------------------------------------------- - * --------------------------------------------------------------------------------------------------------- - * _RSVDPAGE_LOC_CMD_0x00 */ -#define SET_8723B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8723B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) -#define SET_8723B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) -#define SET_8723B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) -#define SET_8723B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) - -/* _KEEP_ALIVE_CMD_0x03 */ -#define SET_8723B_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) -#define SET_8723B_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) -#define SET_8723B_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) -#define SET_8723B_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) - -/* _DISCONNECT_DECISION_CMD_0x04 */ -#define SET_8723B_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) -#define SET_8723B_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) -#define SET_8723B_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) -#define SET_8723B_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) - -/* _PWR_MOD_CMD_0x20 */ -#define SET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8723B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value) -#define SET_8723B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value) -#define SET_8723B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) -#define SET_8723B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) -#define SET_8723B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value) -#define SET_8723B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) -#define SET_8723B_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) - -#define GET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8) - -/* _PS_TUNE_PARAM_CMD_0x21 */ -#define SET_8723B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8723B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) -#define SET_8723B_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value) -#define SET_8723B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value) -#define SET_8723B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) - -/* _MACID_CFG_CMD_0x40 */ -#define SET_8723B_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8723B_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value) -#define SET_8723B_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value) -#define SET_8723B_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value) -#define SET_8723B_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value) -#define SET_8723B_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value) -#define SET_8723B_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value) -#define SET_8723B_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value) -#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) -#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value) -#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value) -#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value) - -/* _RSSI_SETTING_CMD_0x42 */ -#define SET_8723B_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8723B_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value) -#define SET_8723B_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) - -/* _AP_REQ_TXRPT_CMD_0x43 */ -#define SET_8723B_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8723B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) - -/* _FORCE_BT_TXPWR_CMD_0x62 */ -#define SET_8723B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) - -/* _FORCE_BT_MP_OPER_CMD_0x67 */ -#define SET_8723B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) -#define SET_8723B_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value) -#define SET_8723B_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) -#define SET_8723B_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) -#define SET_8723B_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) -#define SET_8723B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value) - -/* _BT_FW_PATCH_0x6A */ -#define SET_8723B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value) -#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) -#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) -#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) -#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) - -/* --------------------------------------------------------------------------------------------------------- - * ------------------------------------------- Structure -------------------------------------------------- - * --------------------------------------------------------------------------------------------------------- */ - - -/* --------------------------------------------------------------------------------------------------------- - * ---------------------------------- Function Statement -------------------------------------------------- - * --------------------------------------------------------------------------------------------------------- */ - -/* host message to firmware cmd */ -void rtl8723b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); -void rtl8723b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus); -void rtl8723b_set_rssi_cmd(PADAPTER padapter, u8 *param); -void rtl8723b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack); -/* s32 rtl8723b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */ -void rtl8723b_set_FwPsTuneParam_cmd(PADAPTER padapter); -void rtl8723b_set_FwMacIdConfig_cmd(_adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask, u8 ignore_bw); -void rtl8723b_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param); -void rtl8723b_download_rsvd_page(PADAPTER padapter, u8 mstatus); -#ifdef CONFIG_BT_COEXIST - void rtl8723b_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter); -#endif /* CONFIG_BT_COEXIST */ -#ifdef CONFIG_P2P - void rtl8723b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); -#endif /* CONFIG_P2P */ - -void CheckFwRsvdPageContent(PADAPTER padapter); - -#ifdef CONFIG_TDLS - #ifdef CONFIG_TDLS_CH_SW - void rtl8723b_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); - #endif -#endif - -#ifdef CONFIG_P2P_WOWLAN - void rtl8723b_set_p2p_wowlan_offload_cmd(PADAPTER padapter); -#endif - -void rtl8723b_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param); - -#ifdef CONFIG_TSF_RESET_OFFLOAD - u8 rtl8723b_reset_tsf(_adapter *padapter, u8 reset_port); -#endif /* CONFIG_TSF_RESET_OFFLOAD */ -s32 FillH2CCmd8723B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); -u8 GetTxBufferRsvdPageNum8723B(_adapter *padapter, bool wowlan); -#endif diff --git a/include/rtl8723b_dm.h b/include/rtl8723b_dm.h deleted file mode 100644 index a3bb7df..0000000 --- a/include/rtl8723b_dm.h +++ /dev/null @@ -1,47 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8723B_DM_H__ -#define __RTL8723B_DM_H__ -/* ************************************************************ - * Description: - * - * This file is for 8723B dynamic mechanism only - * - * - * ************************************************************ */ - -/* ************************************************************ - * structure and define - * ************************************************************ */ - -/* ************************************************************ - * function prototype - * ************************************************************ */ - -void rtl8723b_init_dm_priv(PADAPTER padapter); -void rtl8723b_deinit_dm_priv(PADAPTER padapter); - -void rtl8723b_InitHalDm(PADAPTER padapter); -void rtl8723b_HalDmWatchDog(PADAPTER padapter); -void rtl8723b_HalDmWatchDog_in_LPS(PADAPTER padapter); -void rtl8723b_hal_dm_in_lps(PADAPTER padapter); - - -#endif diff --git a/include/rtl8723b_hal.h b/include/rtl8723b_hal.h deleted file mode 100755 index b7c8bc5..0000000 --- a/include/rtl8723b_hal.h +++ /dev/null @@ -1,283 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8723B_HAL_H__ -#define __RTL8723B_HAL_H__ - -#include "hal_data.h" - -#include "rtl8723b_spec.h" -#include "rtl8723b_rf.h" -#include "rtl8723b_dm.h" -#include "rtl8723b_recv.h" -#include "rtl8723b_xmit.h" -#include "rtl8723b_cmd.h" -#include "rtl8723b_led.h" -#include "Hal8723BPwrSeq.h" -#include "Hal8723BPhyReg.h" -#include "Hal8723BPhyCfg.h" -#ifdef DBG_CONFIG_ERROR_DETECT - #include "rtl8723b_sreset.h" -#endif - -#define FW_8723B_SIZE 0x8000 -#define FW_8723B_START_ADDRESS 0x1000 -#define FW_8723B_END_ADDRESS 0x1FFF /* 0x5FFF */ - -#define IS_FW_HEADER_EXIST_8723B(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x5300) - -typedef struct _RT_FIRMWARE { - FIRMWARE_SOURCE eFWSource; -#ifdef CONFIG_EMBEDDED_FWIMG - u8 *szFwBuffer; -#else - u8 szFwBuffer[FW_8723B_SIZE]; -#endif - u32 ulFwLength; -} RT_FIRMWARE_8723B, *PRT_FIRMWARE_8723B; - -/* - * This structure must be cared byte-ordering - * - * Added by tynli. 2009.12.04. */ -typedef struct _RT_8723B_FIRMWARE_HDR { - /* 8-byte alinment required */ - - /* --- LONG WORD 0 ---- */ - u16 Signature; /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */ - u8 Category; /* AP/NIC and USB/PCI */ - u8 Function; /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */ - u16 Version; /* FW Version */ - u16 Subversion; /* FW Subversion, default 0x00 */ - - /* --- LONG WORD 1 ---- */ - u8 Month; /* Release time Month field */ - u8 Date; /* Release time Date field */ - u8 Hour; /* Release time Hour field */ - u8 Minute; /* Release time Minute field */ - u16 RamCodeSize; /* The size of RAM code */ - u16 Rsvd2; - - /* --- LONG WORD 2 ---- */ - u32 SvnIdx; /* The SVN entry index */ - u32 Rsvd3; - - /* --- LONG WORD 3 ---- */ - u32 Rsvd4; - u32 Rsvd5; -} RT_8723B_FIRMWARE_HDR, *PRT_8723B_FIRMWARE_HDR; - -#define DRIVER_EARLY_INT_TIME_8723B 0x05 -#define BCN_DMA_ATIME_INT_TIME_8723B 0x02 - -/* for 8723B - * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */ -#define PAGE_SIZE_TX_8723B 128 -#define PAGE_SIZE_RX_8723B 8 - -#define TX_DMA_SIZE_8723B 0x8000 /* 32K(TX) */ -#define RX_DMA_SIZE_8723B 0x4000 /* 16K(RX) */ - -#ifdef CONFIG_WOWLAN - #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/ -#else - #define RESV_FMWF 0 -#endif - -#ifdef CONFIG_FW_C2H_DEBUG - #define RX_DMA_RESERVED_SIZE_8723B 0x100 /* 256B, reserved for c2h debug message */ -#else - #define RX_DMA_RESERVED_SIZE_8723B 0x80 /* 128B, reserved for tx report */ -#endif -#define RX_DMA_BOUNDARY_8723B (RX_DMA_SIZE_8723B - RX_DMA_RESERVED_SIZE_8723B - 1) - - -/* Note: We will divide number of page equally for each queue other than public queue! */ - -/* For General Reserved Page Number(Beacon Queue is reserved page) - * Beacon:2, PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1 */ -#define BCNQ_PAGE_NUM_8723B 0x08 -#ifdef CONFIG_CONCURRENT_MODE - #define BCNQ1_PAGE_NUM_8723B 0x08 /* 0x04 */ -#else - #define BCNQ1_PAGE_NUM_8723B 0x00 -#endif - -#ifdef CONFIG_PNO_SUPPORT - #undef BCNQ1_PAGE_NUM_8723B - #define BCNQ1_PAGE_NUM_8723B 0x00 /* 0x04 */ -#endif - -/* For WoWLan , more reserved page - * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1,PNO: 6 */ -#ifdef CONFIG_WOWLAN - #define WOWLAN_PAGE_NUM_8723B 0x08 -#else - #define WOWLAN_PAGE_NUM_8723B 0x00 -#endif - -#ifdef CONFIG_PNO_SUPPORT - #undef WOWLAN_PAGE_NUM_8723B - #define WOWLAN_PAGE_NUM_8723B 0x15 -#endif - -#ifdef CONFIG_AP_WOWLAN - #define AP_WOWLAN_PAGE_NUM_8723B 0x02 -#endif - -#define TX_TOTAL_PAGE_NUMBER_8723B (0xFF - BCNQ_PAGE_NUM_8723B - BCNQ1_PAGE_NUM_8723B - WOWLAN_PAGE_NUM_8723B) -#define TX_PAGE_BOUNDARY_8723B (TX_TOTAL_PAGE_NUMBER_8723B + 1) - -#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723B TX_TOTAL_PAGE_NUMBER_8723B -#define WMM_NORMAL_TX_PAGE_BOUNDARY_8723B (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723B + 1) - -/* For Normal Chip Setting - * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8723B */ -#define NORMAL_PAGE_NUM_HPQ_8723B 0x0C -#define NORMAL_PAGE_NUM_LPQ_8723B 0x02 -#define NORMAL_PAGE_NUM_NPQ_8723B 0x02 - -/* Note: For Normal Chip Setting, modify later */ -#define WMM_NORMAL_PAGE_NUM_HPQ_8723B 0x30 -#define WMM_NORMAL_PAGE_NUM_LPQ_8723B 0x20 -#define WMM_NORMAL_PAGE_NUM_NPQ_8723B 0x20 - - -#include "HalVerDef.h" -#include "hal_com.h" - -#define EFUSE_OOB_PROTECT_BYTES 15 - -#define HAL_EFUSE_MEMORY - -#define HWSET_MAX_SIZE_8723B 512 -#define EFUSE_REAL_CONTENT_LEN_8723B 512 -#define EFUSE_MAP_LEN_8723B 512 -#define EFUSE_MAX_SECTION_8723B 64 - -#define EFUSE_IC_ID_OFFSET 506 /* For some inferiority IC purpose. added by Roger, 2009.09.02. */ -#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN_8723B) - -#define EFUSE_ACCESS_ON 0x69 /* For RTL8723 only. */ -#define EFUSE_ACCESS_OFF 0x00 /* For RTL8723 only. */ - -/* ******************************************************** - * EFUSE for BT definition - * ******************************************************** */ -#define EFUSE_BT_REAL_BANK_CONTENT_LEN 512 -#define EFUSE_BT_REAL_CONTENT_LEN 1536 /* 512*3 */ -#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */ -#define EFUSE_BT_MAX_SECTION 128 /* 1024/8 */ - -#define EFUSE_PROTECT_BYTES_BANK 16 - -typedef enum tag_Package_Definition { - PACKAGE_DEFAULT, - PACKAGE_QFN68, - PACKAGE_TFBGA90, - PACKAGE_TFBGA80, - PACKAGE_TFBGA79 -} PACKAGE_TYPE_E; - -#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT) -#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) - -/* rtl8723a_hal_init.c */ -s32 rtl8723b_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw); -void rtl8723b_FirmwareSelfReset(PADAPTER padapter); -void rtl8723b_InitializeFirmwareVars(PADAPTER padapter); - -void rtl8723b_InitAntenna_Selection(PADAPTER padapter); -void rtl8723b_DeinitAntenna_Selection(PADAPTER padapter); -void rtl8723b_CheckAntenna_Selection(PADAPTER padapter); -void rtl8723b_init_default_value(PADAPTER padapter); - -s32 rtl8723b_InitLLTTable(PADAPTER padapter); - -s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU); -s32 CardDisableWithoutHWSM(PADAPTER padapter); - -/* EFuse */ -u8 GetEEPROMSize8723B(PADAPTER padapter); -void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent); -void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo); -void Hal_EfuseParseTxPowerInfo_8723B(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail); -void Hal_EfuseParseBTCoexistInfo_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParseEEPROMVer_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParseChnlPlan_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParseCustomerID_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParseAntennaDiversity_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParseXtal_8723B(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail); -void Hal_EfuseParseThermalMeter_8723B(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail); -VOID Hal_EfuseParsePackageType_8723B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -VOID Hal_EfuseParseVoltage_8723B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -VOID Hal_EfuseParseBoardType_8723B(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); - -void rtl8723b_set_hal_ops(struct hal_ops *pHalFunc); -void init_hal_spec_8723b(_adapter *adapter); -void SetHwReg8723B(PADAPTER padapter, u8 variable, u8 *val); -void GetHwReg8723B(PADAPTER padapter, u8 variable, u8 *val); -u8 SetHalDefVar8723B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); -u8 GetHalDefVar8723B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); - -/* register */ -void rtl8723b_InitBeaconParameters(PADAPTER padapter); -void rtl8723b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode); -void _InitBurstPktLen_8723BS(PADAPTER Adapter); -void _8051Reset8723(PADAPTER padapter); -#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) - void Hal_DetectWoWMode(PADAPTER pAdapter); -#endif /* CONFIG_WOWLAN */ - -void rtl8723b_start_thread(_adapter *padapter); -void rtl8723b_stop_thread(_adapter *padapter); - -#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST) - void rtl8723bs_init_checkbthang_workqueue(_adapter *adapter); - void rtl8723bs_free_checkbthang_workqueue(_adapter *adapter); - void rtl8723bs_cancle_checkbthang_workqueue(_adapter *adapter); - void rtl8723bs_hal_check_bt_hang(_adapter *adapter); -#endif - -#ifdef CONFIG_GPIO_WAKEUP - void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue); -#endif -#ifdef CONFIG_MP_INCLUDED -int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware); -#endif -void CCX_FwC2HTxRpt_8723b(PADAPTER padapter, u8 *pdata, u8 len); - -u8 MRateToHwRate8723B(u8 rate); -u8 HwRateToMRate8723B(u8 rate); - -#ifdef CONFIG_RF_POWER_TRIM - void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -#endif /*CONFIG_RF_POWER_TRIM*/ - -#ifdef CONFIG_PCI_HCI - BOOLEAN InterruptRecognized8723BE(PADAPTER Adapter); - VOID UpdateInterruptMask8723BE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1); -#endif - -#ifdef CONFIG_GPIO_API -int rtl8723b_GpioFuncCheck(PADAPTER adapter, u8 gpio_num); -VOID rtl8723b_GpioMultiFuncReset(PADAPTER adapter, u8 gpio_num); -#endif - -#endif diff --git a/include/rtl8723b_led.h b/include/rtl8723b_led.h deleted file mode 100755 index 0a7b2c9..0000000 --- a/include/rtl8723b_led.h +++ /dev/null @@ -1,48 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8723B_LED_H__ -#define __RTL8723B_LED_H__ - -#include -#include -#include - - -/* ******************************************************************************** - * Interface to manipulate LED objects. - * ******************************************************************************** */ -#ifdef CONFIG_USB_HCI - void rtl8723bu_InitSwLeds(PADAPTER padapter); - void rtl8723bu_DeInitSwLeds(PADAPTER padapter); -#endif -#ifdef CONFIG_SDIO_HCI - void rtl8723bs_InitSwLeds(PADAPTER padapter); - void rtl8723bs_DeInitSwLeds(PADAPTER padapter); -#endif -#ifdef CONFIG_GSPI_HCI - void rtl8723bs_InitSwLeds(PADAPTER padapter); - void rtl8723bs_DeInitSwLeds(PADAPTER padapter); -#endif -#ifdef CONFIG_PCI_HCI - void rtl8723be_InitSwLeds(PADAPTER padapter); - void rtl8723be_DeInitSwLeds(PADAPTER padapter); -#endif - -#endif diff --git a/include/rtl8723b_recv.h b/include/rtl8723b_recv.h deleted file mode 100755 index bd93368..0000000 --- a/include/rtl8723b_recv.h +++ /dev/null @@ -1,87 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8723B_RECV_H__ -#define __RTL8723B_RECV_H__ - -#define RECV_BLK_SZ 512 -#define RECV_BLK_CNT 16 -#define RECV_BLK_TH RECV_BLK_CNT - -#if defined(CONFIG_USB_HCI) - - #ifndef MAX_RECVBUF_SZ - #ifndef CONFIG_MINIMAL_MEMORY_USAGE - /* #define MAX_RECVBUF_SZ (32768) */ /* 32k */ - /* #define MAX_RECVBUF_SZ (16384) */ /* 16K */ - /* #define MAX_RECVBUF_SZ (10240) */ /* 10K */ - #ifdef CONFIG_PLATFORM_MSTAR - #define MAX_RECVBUF_SZ (8192) /* 8K */ - #else - #define MAX_RECVBUF_SZ (15360) /* 15k < 16k */ - #endif - /* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */ - #else - #define MAX_RECVBUF_SZ (4000) /* about 4K */ - #endif - #endif /* !MAX_RECVBUF_SZ */ - -#elif defined(CONFIG_PCI_HCI) - /* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */ - /* #define MAX_RECVBUF_SZ (9100) */ - /* #else */ - #define MAX_RECVBUF_SZ (4000) /* about 4K - * #endif */ - - -#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - - #define MAX_RECVBUF_SZ (RX_DMA_SIZE_8723B - RX_DMA_RESERVED_SIZE_8723B) - -#endif - -/* Rx smooth factor */ -#define Rx_Smooth_Factor (20) - -#ifdef CONFIG_SDIO_HCI - #ifndef CONFIG_SDIO_RX_COPY - #undef MAX_RECVBUF_SZ - #define MAX_RECVBUF_SZ (RX_DMA_SIZE_8723B - RX_DMA_RESERVED_SIZE_8723B) - #endif /* !CONFIG_SDIO_RX_COPY */ -#endif /* CONFIG_SDIO_HCI */ - -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - s32 rtl8723bs_init_recv_priv(PADAPTER padapter); - void rtl8723bs_free_recv_priv(PADAPTER padapter); -#endif - -#ifdef CONFIG_USB_HCI - int rtl8723bu_init_recv_priv(_adapter *padapter); - void rtl8723bu_free_recv_priv(_adapter *padapter); - void rtl8723bu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf); -#endif - -#ifdef CONFIG_PCI_HCI - s32 rtl8723be_init_recv_priv(PADAPTER padapter); - void rtl8723be_free_recv_priv(PADAPTER padapter); -#endif - -void rtl8723b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc); - -#endif /* __RTL8723B_RECV_H__ */ diff --git a/include/rtl8723b_rf.h b/include/rtl8723b_rf.h deleted file mode 100644 index bf56dde..0000000 --- a/include/rtl8723b_rf.h +++ /dev/null @@ -1,30 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8723B_RF_H__ -#define __RTL8723B_RF_H__ - -int PHY_RF6052_Config8723B(IN PADAPTER Adapter); - -VOID -PHY_RF6052SetBandwidth8723B( - IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth); - -#endif diff --git a/include/rtl8723b_spec.h b/include/rtl8723b_spec.h deleted file mode 100755 index f8e8a65..0000000 --- a/include/rtl8723b_spec.h +++ /dev/null @@ -1,284 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ -#ifndef __RTL8723B_SPEC_H__ -#define __RTL8723B_SPEC_H__ - -#include - - -#define HAL_NAV_UPPER_UNIT_8723B 128 /* micro-second */ - -/* ----------------------------------------------------- - * - * 0x0000h ~ 0x00FFh System Configuration - * - * ----------------------------------------------------- */ -#define REG_RSV_CTRL_8723B 0x001C /* 3 Byte */ -#define REG_BT_WIFI_ANTENNA_SWITCH_8723B 0x0038 -#define REG_HSISR_8723B 0x005c -#define REG_PAD_CTRL1_8723B 0x0064 -#define REG_AFE_CTRL_4_8723B 0x0078 -#define REG_HMEBOX_DBG_0_8723B 0x0088 -#define REG_HMEBOX_DBG_1_8723B 0x008A -#define REG_HMEBOX_DBG_2_8723B 0x008C -#define REG_HMEBOX_DBG_3_8723B 0x008E -#define REG_HIMR0_8723B 0x00B0 -#define REG_HISR0_8723B 0x00B4 -#define REG_HIMR1_8723B 0x00B8 -#define REG_HISR1_8723B 0x00BC -#define REG_PMC_DBG_CTRL2_8723B 0x00CC - -/* ----------------------------------------------------- - * - * 0x0100h ~ 0x01FFh MACTOP General Configuration - * - * ----------------------------------------------------- */ -#define REG_C2HEVT_CMD_ID_8723B 0x01A0 -#define REG_C2HEVT_CMD_LEN_8723B 0x01AE -#define REG_WOWLAN_WAKE_REASON 0x01C7 -#define REG_WOWLAN_GTK_DBG1 0x630 -#define REG_WOWLAN_GTK_DBG2 0x634 - -#define REG_HMEBOX_EXT0_8723B 0x01F0 -#define REG_HMEBOX_EXT1_8723B 0x01F4 -#define REG_HMEBOX_EXT2_8723B 0x01F8 -#define REG_HMEBOX_EXT3_8723B 0x01FC - -/* ----------------------------------------------------- - * - * 0x0200h ~ 0x027Fh TXDMA Configuration - * - * ----------------------------------------------------- */ - -/* ----------------------------------------------------- - * - * 0x0280h ~ 0x02FFh RXDMA Configuration - * - * ----------------------------------------------------- */ -#define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */ -#define REG_RXDMA_MODE_CTRL_8723B 0x0290 - -/* ----------------------------------------------------- - * - * 0x0300h ~ 0x03FFh PCIe - * - * ----------------------------------------------------- */ -#define REG_PCIE_CTRL_REG_8723B 0x0300 -#define REG_INT_MIG_8723B 0x0304 /* Interrupt Migration */ -#define REG_BCNQ_DESA_8723B 0x0308 /* TX Beacon Descriptor Address */ -#define REG_HQ_DESA_8723B 0x0310 /* TX High Queue Descriptor Address */ -#define REG_MGQ_DESA_8723B 0x0318 /* TX Manage Queue Descriptor Address */ -#define REG_VOQ_DESA_8723B 0x0320 /* TX VO Queue Descriptor Address */ -#define REG_VIQ_DESA_8723B 0x0328 /* TX VI Queue Descriptor Address */ -#define REG_BEQ_DESA_8723B 0x0330 /* TX BE Queue Descriptor Address */ -#define REG_BKQ_DESA_8723B 0x0338 /* TX BK Queue Descriptor Address */ -#define REG_RX_DESA_8723B 0x0340 /* RX Queue Descriptor Address */ -#define REG_DBI_WDATA_8723B 0x0348 /* DBI Write Data */ -#define REG_DBI_RDATA_8723B 0x034C /* DBI Read Data */ -#define REG_DBI_ADDR_8723B 0x0350 /* DBI Address */ -#define REG_DBI_FLAG_8723B 0x0352 /* DBI Read/Write Flag */ -#define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */ -#define REG_MDIO_RDATA_8723B 0x0356 /* MDIO for Reads PCIE PHY */ -#define REG_MDIO_CTL_8723B 0x0358 /* MDIO for Control */ -#define REG_DBG_SEL_8723B 0x0360 /* Debug Selection Register */ -#define REG_PCIE_HRPWM_8723B 0x0361 /* PCIe RPWM */ -#define REG_PCIE_HCPWM_8723B 0x0363 /* PCIe CPWM */ -#define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */ - -/* ----------------------------------------------------- - * - * 0x0400h ~ 0x047Fh Protocol Configuration - * - * ----------------------------------------------------- */ -#define REG_TXPKTBUF_BCNQ_BDNY_8723B 0x0424 -#define REG_TXPKTBUF_MGQ_BDNY_8723B 0x0425 -#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B 0x045D -#ifdef CONFIG_WOWLAN - #define REG_TXPKTBUF_IV_LOW 0x0484 - #define REG_TXPKTBUF_IV_HIGH 0x0488 -#endif -#define REG_AMPDU_BURST_MODE_8723B 0x04BC - -/* ----------------------------------------------------- - * - * 0x0500h ~ 0x05FFh EDCA Configuration - * - * ----------------------------------------------------- */ -#define REG_SECONDARY_CCA_CTRL_8723B 0x0577 - -/* ----------------------------------------------------- - * - * 0x0600h ~ 0x07FFh WMAC Configuration - * - * ----------------------------------------------------- */ - - -/* ************************************************************ - * SDIO Bus Specification - * ************************************************************ */ - -/* ----------------------------------------------------- - * SDIO CMD Address Mapping - * ----------------------------------------------------- */ - -/* ----------------------------------------------------- - * I/O bus domain (Host) - * ----------------------------------------------------- */ - -/* ----------------------------------------------------- - * SDIO register - * ----------------------------------------------------- */ -#define SDIO_REG_HCPWM1_8723B 0x025 /* HCI Current Power Mode 1 */ - - -/* **************************************************************************** - * 8723 Regsiter Bit and Content definition - * **************************************************************************** */ - -/* 2 HSISR - * interrupt mask which needs to clear */ -#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\ - HSISR_SPS_OCP_INT |\ - HSISR_RON_INT |\ - HSISR_PDNINT |\ - HSISR_GPIO9_INT) - -/* ----------------------------------------------------- - * - * 0x0100h ~ 0x01FFh MACTOP General Configuration - * - * ----------------------------------------------------- */ -#undef IS_E_CUT -#define IS_E_CUT(version) FALSE -#undef IS_F_CUT -#define IS_F_CUT(version) ((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE) - -/* ----------------------------------------------------- - * - * 0x0200h ~ 0x027Fh TXDMA Configuration - * - * ----------------------------------------------------- */ - -/* ----------------------------------------------------- - * - * 0x0280h ~ 0x02FFh RXDMA Configuration - * - * ----------------------------------------------------- */ -#define BIT_USB_RXDMA_AGG_EN BIT(31) -#define RXDMA_AGG_MODE_EN BIT(1) - -#ifdef CONFIG_WOWLAN - #define RXPKT_RELEASE_POLL BIT(16) - #define RXDMA_IDLE BIT(17) - #define RW_RELEASE_EN BIT(18) -#endif - -/* ----------------------------------------------------- - * - * 0x0400h ~ 0x047Fh Protocol Configuration - * - * ----------------------------------------------------- */ - -/* ---------------------------------------------------------------------------- - * 8723B REG_CCK_CHECK (offset 0x454) - * ---------------------------------------------------------------------------- */ -#define BIT_BCN_PORT_SEL BIT(5) - -/* ----------------------------------------------------- - * - * 0x0500h ~ 0x05FFh EDCA Configuration - * - * ----------------------------------------------------- */ - -/* ----------------------------------------------------- - * - * 0x0600h ~ 0x07FFh WMAC Configuration - * - * ----------------------------------------------------- */ -#ifdef CONFIG_RF_POWER_TRIM - - #ifdef CONFIG_RTL8723B - #define EEPROM_RF_GAIN_OFFSET 0xC1 - #endif - - #define EEPROM_RF_GAIN_VAL 0x1F6 -#endif /*CONFIG_RF_POWER_TRIM*/ - - -/* ---------------------------------------------------------------------------- - * 8195 IMR/ISR bits (offset 0xB0, 8bits) - * ---------------------------------------------------------------------------- */ -#define IMR_DISABLED_8723B 0 -/* IMR DW0(0x00B0-00B3) Bit 0-31 */ -#define IMR_TIMER2_8723B BIT(31) /* Timeout interrupt 2 */ -#define IMR_TIMER1_8723B BIT(30) /* Timeout interrupt 1 */ -#define IMR_PSTIMEOUT_8723B BIT(29) /* Power Save Time Out Interrupt */ -#define IMR_GTINT4_8723B BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ -#define IMR_GTINT3_8723B BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ -#define IMR_TXBCN0ERR_8723B BIT(26) /* Transmit Beacon0 Error */ -#define IMR_TXBCN0OK_8723B BIT(25) /* Transmit Beacon0 OK */ -#define IMR_TSF_BIT32_TOGGLE_8723B BIT(24) /* TSF Timer BIT(32) toggle indication interrupt */ -#define IMR_BCNDMAINT0_8723B BIT(20) /* Beacon DMA Interrupt 0 */ -#define IMR_BCNDERR0_8723B BIT(16) /* Beacon Queue DMA OK0 */ -#define IMR_HSISR_IND_ON_INT_8723B BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ -#define IMR_BCNDMAINT_E_8723B BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ -#define IMR_ATIMEND_8723B BIT(12) /* CTWidnow End or ATIM Window End */ -#define IMR_C2HCMD_8723B BIT(10) /* CPU to Host Command INT Status, Write 1 clear */ -#define IMR_CPWM2_8723B BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_CPWM_8723B BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_HIGHDOK_8723B BIT(7) /* High Queue DMA OK */ -#define IMR_MGNTDOK_8723B BIT(6) /* Management Queue DMA OK */ -#define IMR_BKDOK_8723B BIT(5) /* AC_BK DMA OK */ -#define IMR_BEDOK_8723B BIT(4) /* AC_BE DMA OK */ -#define IMR_VIDOK_8723B BIT(3) /* AC_VI DMA OK */ -#define IMR_VODOK_8723B BIT(2) /* AC_VO DMA OK */ -#define IMR_RDU_8723B BIT(1) /* Rx Descriptor Unavailable */ -#define IMR_ROK_8723B BIT(0) /* Receive DMA OK */ - -/* IMR DW1(0x00B4-00B7) Bit 0-31 */ -#define IMR_BCNDMAINT7_8723B BIT(27) /* Beacon DMA Interrupt 7 */ -#define IMR_BCNDMAINT6_8723B BIT(26) /* Beacon DMA Interrupt 6 */ -#define IMR_BCNDMAINT5_8723B BIT(25) /* Beacon DMA Interrupt 5 */ -#define IMR_BCNDMAINT4_8723B BIT(24) /* Beacon DMA Interrupt 4 */ -#define IMR_BCNDMAINT3_8723B BIT(23) /* Beacon DMA Interrupt 3 */ -#define IMR_BCNDMAINT2_8723B BIT(22) /* Beacon DMA Interrupt 2 */ -#define IMR_BCNDMAINT1_8723B BIT(21) /* Beacon DMA Interrupt 1 */ -#define IMR_BCNDOK7_8723B BIT(20) /* Beacon Queue DMA OK Interrupt 7 */ -#define IMR_BCNDOK6_8723B BIT(19) /* Beacon Queue DMA OK Interrupt 6 */ -#define IMR_BCNDOK5_8723B BIT(18) /* Beacon Queue DMA OK Interrupt 5 */ -#define IMR_BCNDOK4_8723B BIT(17) /* Beacon Queue DMA OK Interrupt 4 */ -#define IMR_BCNDOK3_8723B BIT(16) /* Beacon Queue DMA OK Interrupt 3 */ -#define IMR_BCNDOK2_8723B BIT(15) /* Beacon Queue DMA OK Interrupt 2 */ -#define IMR_BCNDOK1_8723B BIT(14) /* Beacon Queue DMA OK Interrupt 1 */ -#define IMR_ATIMEND_E_8723B BIT(13) /* ATIM Window End Extension for Win7 */ -#define IMR_TXERR_8723B BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */ -#define IMR_RXERR_8723B BIT(10) /* Rx Error Flag INT Status, Write 1 clear */ -#define IMR_TXFOVW_8723B BIT(9) /* Transmit FIFO Overflow */ -#define IMR_RXFOVW_8723B BIT(8) /* Receive FIFO Overflow */ - -#ifdef CONFIG_PCI_HCI - /* #define IMR_RX_MASK (IMR_ROK_8723B|IMR_RDU_8723B|IMR_RXFOVW_8723B) */ - #define IMR_TX_MASK (IMR_VODOK_8723B | IMR_VIDOK_8723B | IMR_BEDOK_8723B | IMR_BKDOK_8723B | IMR_MGNTDOK_8723B | IMR_HIGHDOK_8723B) - - #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8723B | IMR_TXBCN0OK_8723B | IMR_TXBCN0ERR_8723B | IMR_BCNDERR0_8723B) - - #define RT_AC_INT_MASKS (IMR_VIDOK_8723B | IMR_VODOK_8723B | IMR_BEDOK_8723B | IMR_BKDOK_8723B) -#endif - -#endif /* __RTL8723B_SPEC_H__ */ diff --git a/include/rtl8723b_sreset.h b/include/rtl8723b_sreset.h deleted file mode 100644 index 8067359..0000000 --- a/include/rtl8723b_sreset.h +++ /dev/null @@ -1,29 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef _RTL8723B_SRESET_H_ -#define _RTL8723B_SRESET_H_ - -#include - -#ifdef DBG_CONFIG_ERROR_DETECT - extern void rtl8723b_sreset_xmit_status_check(_adapter *padapter); - extern void rtl8723b_sreset_linked_status_check(_adapter *padapter); -#endif -#endif diff --git a/include/rtl8723b_xmit.h b/include/rtl8723b_xmit.h deleted file mode 100755 index 7cc33e1..0000000 --- a/include/rtl8723b_xmit.h +++ /dev/null @@ -1,338 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8723B_XMIT_H__ -#define __RTL8723B_XMIT_H__ - - -#define MAX_TID (15) - - -#ifndef __INC_HAL8723BDESC_H - #define __INC_HAL8723BDESC_H - - #define RX_STATUS_DESC_SIZE_8723B 24 - #define RX_DRV_INFO_SIZE_UNIT_8723B 8 - - - /* DWORD 0 */ - #define SET_RX_STATUS_DESC_PKT_LEN_8723B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value) - #define SET_RX_STATUS_DESC_EOR_8723B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value) - #define SET_RX_STATUS_DESC_OWN_8723B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value) - - #define GET_RX_STATUS_DESC_PKT_LEN_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14) - #define GET_RX_STATUS_DESC_CRC32_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1) - #define GET_RX_STATUS_DESC_ICV_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1) - #define GET_RX_STATUS_DESC_DRVINFO_SIZE_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4) - #define GET_RX_STATUS_DESC_SECURITY_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3) - #define GET_RX_STATUS_DESC_QOS_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1) - #define GET_RX_STATUS_DESC_SHIFT_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2) - #define GET_RX_STATUS_DESC_PHY_STATUS_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1) - #define GET_RX_STATUS_DESC_SWDEC_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1) - #define GET_RX_STATUS_DESC_LAST_SEG_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1) - #define GET_RX_STATUS_DESC_FIRST_SEG_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1) - #define GET_RX_STATUS_DESC_EOR_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1) - #define GET_RX_STATUS_DESC_OWN_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1) - - /* DWORD 1 */ - #define GET_RX_STATUS_DESC_MACID_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7) - #define GET_RX_STATUS_DESC_TID_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4) - #define GET_RX_STATUS_DESC_AMSDU_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1) - #define GET_RX_STATUS_DESC_RXID_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1) - #define GET_RX_STATUS_DESC_PAGGR_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1) - #define GET_RX_STATUS_DESC_A1_FIT_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4) - #define GET_RX_STATUS_DESC_CHKERR_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1) - #define GET_RX_STATUS_DESC_IPVER_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1) - #define GET_RX_STATUS_DESC_IS_TCPUDP__8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1) - #define GET_RX_STATUS_DESC_CHK_VLD_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1) - #define GET_RX_STATUS_DESC_PAM_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1) - #define GET_RX_STATUS_DESC_PWR_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1) - #define GET_RX_STATUS_DESC_MORE_DATA_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1) - #define GET_RX_STATUS_DESC_MORE_FRAG_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1) - #define GET_RX_STATUS_DESC_TYPE_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2) - #define GET_RX_STATUS_DESC_MC_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1) - #define GET_RX_STATUS_DESC_BC_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1) - - /* DWORD 2 */ - #define GET_RX_STATUS_DESC_SEQ_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12) - #define GET_RX_STATUS_DESC_FRAG_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4) - #define GET_RX_STATUS_DESC_RX_IS_QOS_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1) - #define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6) - #define GET_RX_STATUS_DESC_RPT_SEL_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1) - - /* DWORD 3 */ - #define GET_RX_STATUS_DESC_RX_RATE_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7) - #define GET_RX_STATUS_DESC_HTC_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1) - #define GET_RX_STATUS_DESC_EOSP_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1) - #define GET_RX_STATUS_DESC_BSSID_FIT_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2) - #ifdef CONFIG_USB_RX_AGGREGATION - #define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8) - #endif - #define GET_RX_STATUS_DESC_PATTERN_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1) - #define GET_RX_STATUS_DESC_UNICAST_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1) - #define GET_RX_STATUS_DESC_MAGIC_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1) - - /* DWORD 6 */ - #define GET_RX_STATUS_DESC_SPLCP_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1) - #define GET_RX_STATUS_DESC_LDPC_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1) - #define GET_RX_STATUS_DESC_STBC_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1) - #define GET_RX_STATUS_DESC_BW_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2) - - /* DWORD 5 */ - #define GET_RX_STATUS_DESC_TSFL_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32) - - #define GET_RX_STATUS_DESC_BUFF_ADDR_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32) - #define GET_RX_STATUS_DESC_BUFF_ADDR64_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32) - - #define SET_RX_STATUS_DESC_BUFF_ADDR_8723B(__pRxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value) - - - /* Dword 0 */ - #define GET_TX_DESC_OWN_8723B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1) - - #define SET_TX_DESC_PKT_SIZE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value) - #define SET_TX_DESC_OFFSET_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value) - #define SET_TX_DESC_BMC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value) - #define SET_TX_DESC_HTC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value) - #define SET_TX_DESC_LAST_SEG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value) - #define SET_TX_DESC_FIRST_SEG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value) - #define SET_TX_DESC_LINIP_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value) - #define SET_TX_DESC_NO_ACM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value) - #define SET_TX_DESC_GF_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value) - #define SET_TX_DESC_OWN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) - - /* Dword 1 */ - #define SET_TX_DESC_MACID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value) - #define SET_TX_DESC_QUEUE_SEL_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value) - #define SET_TX_DESC_RDG_NAV_EXT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value) - #define SET_TX_DESC_LSIG_TXOP_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value) - #define SET_TX_DESC_PIFS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value) - #define SET_TX_DESC_RATE_ID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value) - #define SET_TX_DESC_EN_DESC_ID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value) - #define SET_TX_DESC_SEC_TYPE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value) - #define SET_TX_DESC_PKT_OFFSET_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value) - - - /* Dword 2 */ - #define SET_TX_DESC_PAID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value) - #define SET_TX_DESC_CCA_RTS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value) - #define SET_TX_DESC_AGG_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value) - #define SET_TX_DESC_RDG_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value) - #define SET_TX_DESC_AGG_BREAK_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value) - #define SET_TX_DESC_MORE_FRAG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value) - #define SET_TX_DESC_RAW_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value) - #define SET_TX_DESC_SPE_RPT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value) - #define SET_TX_DESC_AMPDU_DENSITY_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value) - #define SET_TX_DESC_BT_INT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value) - #define SET_TX_DESC_GID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value) - - - /* Dword 3 */ - #define SET_TX_DESC_WHEADER_LEN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value) - #define SET_TX_DESC_CHK_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value) - #define SET_TX_DESC_EARLY_MODE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value) - #define SET_TX_DESC_HWSEQ_SEL_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value) - #define SET_TX_DESC_USE_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value) - #define SET_TX_DESC_DISABLE_RTS_FB_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value) - #define SET_TX_DESC_DISABLE_FB_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value) - #define SET_TX_DESC_CTS2SELF_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value) - #define SET_TX_DESC_RTS_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value) - #define SET_TX_DESC_HW_RTS_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value) - #define SET_TX_DESC_NAV_USE_HDR_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value) - #define SET_TX_DESC_USE_MAX_LEN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value) - #define SET_TX_DESC_MAX_AGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value) - #define SET_TX_DESC_NDPA_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value) - #define SET_TX_DESC_AMPDU_MAX_TIME_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value) - - /* Dword 4 */ - #define SET_TX_DESC_TX_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value) - #define SET_TX_DESC_DATA_RATE_FB_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value) - #define SET_TX_DESC_RTS_RATE_FB_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value) - #define SET_TX_DESC_RETRY_LIMIT_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value) - #define SET_TX_DESC_DATA_RETRY_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value) - #define SET_TX_DESC_RTS_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value) - - - /* Dword 5 */ - #define SET_TX_DESC_DATA_SC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value) - #define SET_TX_DESC_DATA_SHORT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value) - #define SET_TX_DESC_DATA_BW_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value) - #define SET_TX_DESC_DATA_LDPC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value) - #define SET_TX_DESC_DATA_STBC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value) - #define SET_TX_DESC_CTROL_STBC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value) - #define SET_TX_DESC_RTS_SHORT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value) - #define SET_TX_DESC_RTS_SC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value) - - - /* Dword 6 */ - #define SET_TX_DESC_SW_DEFINE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value) - #define SET_TX_DESC_MBSSID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value) - #define SET_TX_DESC_ANTSEL_A_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value) - #define SET_TX_DESC_ANTSEL_B_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value) - #define SET_TX_DESC_ANTSEL_C_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value) - #define SET_TX_DESC_ANTSEL_D_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value) - - /* Dword 7 */ - #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) - #define SET_TX_DESC_TX_BUFFER_SIZE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) - #else - #define SET_TX_DESC_TX_DESC_CHECKSUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) - #endif - #define SET_TX_DESC_USB_TXAGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) - #if (DEV_BUS_TYPE == RT_SDIO_INTERFACE) - #define SET_TX_DESC_SDIO_TXSEQ_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value) - #endif - - /* Dword 8 */ - #define SET_TX_DESC_HWSEQ_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) - - /* Dword 9 */ - #define SET_TX_DESC_SEQ_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value) - - /* Dword 10 */ - #define SET_TX_DESC_TX_BUFFER_ADDRESS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value) - #define GET_TX_DESC_TX_BUFFER_ADDRESS_8723B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32) - - /* Dword 11 */ - #define SET_TX_DESC_NEXT_DESC_ADDRESS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value) - - - #define SET_EARLYMODE_PKTNUM_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value) - #define SET_EARLYMODE_LEN0_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value) - #define SET_EARLYMODE_LEN1_1_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value) - #define SET_EARLYMODE_LEN1_2_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value) - #define SET_EARLYMODE_LEN2_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value) - #define SET_EARLYMODE_LEN3_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value) - -#endif -/* ----------------------------------------------------------- - * - * Rate - * - * ----------------------------------------------------------- - * CCK Rates, TxHT = 0 */ -#define DESC8723B_RATE1M 0x00 -#define DESC8723B_RATE2M 0x01 -#define DESC8723B_RATE5_5M 0x02 -#define DESC8723B_RATE11M 0x03 - -/* OFDM Rates, TxHT = 0 */ -#define DESC8723B_RATE6M 0x04 -#define DESC8723B_RATE9M 0x05 -#define DESC8723B_RATE12M 0x06 -#define DESC8723B_RATE18M 0x07 -#define DESC8723B_RATE24M 0x08 -#define DESC8723B_RATE36M 0x09 -#define DESC8723B_RATE48M 0x0a -#define DESC8723B_RATE54M 0x0b - -/* MCS Rates, TxHT = 1 */ -#define DESC8723B_RATEMCS0 0x0c -#define DESC8723B_RATEMCS1 0x0d -#define DESC8723B_RATEMCS2 0x0e -#define DESC8723B_RATEMCS3 0x0f -#define DESC8723B_RATEMCS4 0x10 -#define DESC8723B_RATEMCS5 0x11 -#define DESC8723B_RATEMCS6 0x12 -#define DESC8723B_RATEMCS7 0x13 -#define DESC8723B_RATEMCS8 0x14 -#define DESC8723B_RATEMCS9 0x15 -#define DESC8723B_RATEMCS10 0x16 -#define DESC8723B_RATEMCS11 0x17 -#define DESC8723B_RATEMCS12 0x18 -#define DESC8723B_RATEMCS13 0x19 -#define DESC8723B_RATEMCS14 0x1a -#define DESC8723B_RATEMCS15 0x1b -#define DESC8723B_RATEVHTSS1MCS0 0x2c -#define DESC8723B_RATEVHTSS1MCS1 0x2d -#define DESC8723B_RATEVHTSS1MCS2 0x2e -#define DESC8723B_RATEVHTSS1MCS3 0x2f -#define DESC8723B_RATEVHTSS1MCS4 0x30 -#define DESC8723B_RATEVHTSS1MCS5 0x31 -#define DESC8723B_RATEVHTSS1MCS6 0x32 -#define DESC8723B_RATEVHTSS1MCS7 0x33 -#define DESC8723B_RATEVHTSS1MCS8 0x34 -#define DESC8723B_RATEVHTSS1MCS9 0x35 -#define DESC8723B_RATEVHTSS2MCS0 0x36 -#define DESC8723B_RATEVHTSS2MCS1 0x37 -#define DESC8723B_RATEVHTSS2MCS2 0x38 -#define DESC8723B_RATEVHTSS2MCS3 0x39 -#define DESC8723B_RATEVHTSS2MCS4 0x3a -#define DESC8723B_RATEVHTSS2MCS5 0x3b -#define DESC8723B_RATEVHTSS2MCS6 0x3c -#define DESC8723B_RATEVHTSS2MCS7 0x3d -#define DESC8723B_RATEVHTSS2MCS8 0x3e -#define DESC8723B_RATEVHTSS2MCS9 0x3f - - -#define RX_HAL_IS_CCK_RATE_8723B(pDesc)\ - (GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE1M || \ - GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE2M || \ - GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE5_5M || \ - GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE11M) - - -void rtl8723b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem); -void rtl8723b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); -#if defined(CONFIG_CONCURRENT_MODE) - void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); -#endif - -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - s32 rtl8723bs_init_xmit_priv(PADAPTER padapter); - void rtl8723bs_free_xmit_priv(PADAPTER padapter); - s32 rtl8723bs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 rtl8723bs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); - s32 rtl8723bs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); - s32 rtl8723bs_xmit_buf_handler(PADAPTER padapter); - thread_return rtl8723bs_xmit_thread(thread_context context); - #define hal_xmit_handler rtl8723bs_xmit_buf_handler -#endif - -#ifdef CONFIG_USB_HCI - s32 rtl8723bu_xmit_buf_handler(PADAPTER padapter); - #define hal_xmit_handler rtl8723bu_xmit_buf_handler - - - s32 rtl8723bu_init_xmit_priv(PADAPTER padapter); - void rtl8723bu_free_xmit_priv(PADAPTER padapter); - s32 rtl8723bu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 rtl8723bu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); - s32 rtl8723bu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); - /* s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); */ - void rtl8723bu_xmit_tasklet(void *priv); - s32 rtl8723bu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); - void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, struct tx_desc *ptxdesc); -#endif - -#ifdef CONFIG_PCI_HCI - s32 rtl8723be_init_xmit_priv(PADAPTER padapter); - void rtl8723be_free_xmit_priv(PADAPTER padapter); - struct xmit_buf *rtl8723be_dequeue_xmitbuf(struct rtw_tx_ring *ring); - void rtl8723be_xmitframe_resume(_adapter *padapter); - s32 rtl8723be_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 rtl8723be_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); - s32 rtl8723be_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); - void rtl8723be_xmit_tasklet(void *priv); -#endif - -u8 BWMapping_8723B(PADAPTER Adapter, struct pkt_attrib *pattrib); -u8 SCMapping_8723B(PADAPTER Adapter, struct pkt_attrib *pattrib); - -#endif diff --git a/include/rtl8723d_cmd.h b/include/rtl8723d_cmd.h deleted file mode 100644 index e00b7ed..0000000 --- a/include/rtl8723d_cmd.h +++ /dev/null @@ -1,211 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8723D_CMD_H__ -#define __RTL8723D_CMD_H__ - -/* --------------------------------------------------------------------------------------------------------- - * ---------------------------------- H2C CMD DEFINITION ------------------------------------------------ - * --------------------------------------------------------------------------------------------------------- */ - -enum h2c_cmd_8723D { - /* Common Class: 000 */ - H2C_8723D_RSVD_PAGE = 0x00, - H2C_8723D_MEDIA_STATUS_RPT = 0x01, - H2C_8723D_SCAN_ENABLE = 0x02, - H2C_8723D_KEEP_ALIVE = 0x03, - H2C_8723D_DISCON_DECISION = 0x04, - H2C_8723D_PSD_OFFLOAD = 0x05, - H2C_8723D_AP_OFFLOAD = 0x08, - H2C_8723D_BCN_RSVDPAGE = 0x09, - H2C_8723D_PROBERSP_RSVDPAGE = 0x0A, - H2C_8723D_FCS_RSVDPAGE = 0x10, - H2C_8723D_FCS_INFO = 0x11, - H2C_8723D_AP_WOW_GPIO_CTRL = 0x13, - - /* PoweSave Class: 001 */ - H2C_8723D_SET_PWR_MODE = 0x20, - H2C_8723D_PS_TUNING_PARA = 0x21, - H2C_8723D_PS_TUNING_PARA2 = 0x22, - H2C_8723D_P2P_LPS_PARAM = 0x23, - H2C_8723D_P2P_PS_OFFLOAD = 0x24, - H2C_8723D_PS_SCAN_ENABLE = 0x25, - H2C_8723D_SAP_PS_ = 0x26, - H2C_8723D_INACTIVE_PS_ = 0x27, /* Inactive_PS */ - H2C_8723D_FWLPS_IN_IPS_ = 0x28, - - /* Dynamic Mechanism Class: 010 */ - H2C_8723D_MACID_CFG = 0x40, - H2C_8723D_TXBF = 0x41, - H2C_8723D_RSSI_SETTING = 0x42, - H2C_8723D_AP_REQ_TXRPT = 0x43, - H2C_8723D_INIT_RATE_COLLECT = 0x44, - H2C_8723D_RA_PARA_ADJUST = 0x46, - - /* BT Class: 011 */ - H2C_8723D_B_TYPE_TDMA = 0x60, - H2C_8723D_BT_INFO = 0x61, - H2C_8723D_FORCE_BT_TXPWR = 0x62, - H2C_8723D_BT_IGNORE_WLANACT = 0x63, - H2C_8723D_DAC_SWING_VALUE = 0x64, - H2C_8723D_ANT_SEL_RSV = 0x65, - H2C_8723D_WL_OPMODE = 0x66, - H2C_8723D_BT_MP_OPER = 0x67, - H2C_8723D_BT_CONTROL = 0x68, - H2C_8723D_BT_WIFI_CTRL = 0x69, - H2C_8723D_BT_FW_PATCH = 0x6A, - H2C_8723D_BT_WLAN_CALIBRATION = 0x6D, - - /* WOWLAN Class: 100 */ - H2C_8723D_WOWLAN = 0x80, - H2C_8723D_REMOTE_WAKE_CTRL = 0x81, - H2C_8723D_AOAC_GLOBAL_INFO = 0x82, - H2C_8723D_AOAC_RSVD_PAGE = 0x83, - H2C_8723D_AOAC_RSVD_PAGE2 = 0x84, - H2C_8723D_D0_SCAN_OFFLOAD_CTRL = 0x85, - H2C_8723D_D0_SCAN_OFFLOAD_INFO = 0x86, - H2C_8723D_CHNL_SWITCH_OFFLOAD = 0x87, - H2C_8723D_P2P_OFFLOAD_RSVD_PAGE = 0x8A, - H2C_8723D_P2P_OFFLOAD = 0x8B, - - H2C_8723D_RESET_TSF = 0xC0, - H2C_8723D_MAXID, -}; - -/* --------------------------------------------------------------------------------------------------------- - * ---------------------------------- H2C CMD CONTENT -------------------------------------------------- - * --------------------------------------------------------------------------------------------------------- - * _RSVDPAGE_LOC_CMD_0x00 */ -#define SET_8723D_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8723D_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) -#define SET_8723D_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) -#define SET_8723D_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) -#define SET_8723D_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) - -/* _KEEP_ALIVE_CMD_0x03 */ -#define SET_8723D_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) -#define SET_8723D_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) -#define SET_8723D_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) -#define SET_8723D_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) - -/* _DISCONNECT_DECISION_CMD_0x04 */ -#define SET_8723D_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) -#define SET_8723D_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) -#define SET_8723D_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) -#define SET_8723D_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) - -/* _PWR_MOD_CMD_0x20 */ -#define SET_8723D_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8723D_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value) -#define SET_8723D_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value) -#define SET_8723D_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) -#define SET_8723D_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) -#define SET_8723D_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) -#define SET_8723D_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) - -#define GET_8723D_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8) - -/* _PS_TUNE_PARAM_CMD_0x21 */ -#define SET_8723D_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8723D_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) -#define SET_8723D_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value) -#define SET_8723D_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value) -#define SET_8723D_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) - -/* _MACID_CFG_CMD_0x40 */ -#define SET_8723D_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8723D_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value) -#define SET_8723D_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value) -#define SET_8723D_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value) -#define SET_8723D_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value) -#define SET_8723D_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value) -#define SET_8723D_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value) -#define SET_8723D_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value) -#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) -#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value) -#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value) -#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value) - -/* _RSSI_SETTING_CMD_0x42 */ -#define SET_8723D_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8723D_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value) -#define SET_8723D_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) - -/* _AP_REQ_TXRPT_CMD_0x43 */ -#define SET_8723D_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8723D_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) - -/* _FORCE_BT_TXPWR_CMD_0x62 */ -#define SET_8723D_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) - -/* _FORCE_BT_MP_OPER_CMD_0x67 */ -#define SET_8723D_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) -#define SET_8723D_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value) -#define SET_8723D_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) -#define SET_8723D_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) -#define SET_8723D_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) -#define SET_8723D_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value) - -/* _BT_FW_PATCH_0x6A */ -#define SET_8723D_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value) -#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) -#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) -#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) -#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) - -/* --------------------------------------------------------------------------------------------------------- - * ------------------------------------------- Structure -------------------------------------------------- - * --------------------------------------------------------------------------------------------------------- */ - - -/* --------------------------------------------------------------------------------------------------------- - * ---------------------------------- Function Statement -------------------------------------------------- - * --------------------------------------------------------------------------------------------------------- */ - -/* host message to firmware cmd */ -void rtl8723d_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); -void rtl8723d_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus); -void rtl8723d_set_rssi_cmd(PADAPTER padapter, u8 *param); -void rtl8723d_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack); -/* s32 rtl8723d_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */ -void rtl8723d_set_FwPsTuneParam_cmd(PADAPTER padapter); -void rtl8723d_set_FwMacIdConfig_cmd(_adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask, u8 ignore_bw); -void rtl8723d_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param); -void rtl8723d_download_rsvd_page(PADAPTER padapter, u8 mstatus); -#ifdef CONFIG_BT_COEXIST - void rtl8723d_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter); -#endif /* CONFIG_BT_COEXIST */ -#ifdef CONFIG_P2P - void rtl8723d_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); -#endif /* CONFIG_P2P */ - -void CheckFwRsvdPageContent(PADAPTER padapter); - -#ifdef CONFIG_P2P_WOWLAN - void rtl8723d_set_p2p_wowlan_offload_cmd(PADAPTER padapter); -#endif - -void rtl8723d_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param); - -#ifdef CONFIG_TSF_RESET_OFFLOAD - u8 rtl8723d_reset_tsf(_adapter *padapter, u8 reset_port); -#endif /* CONFIG_TSF_RESET_OFFLOAD */ -s32 FillH2CCmd8723D(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); -u8 GetTxBufferRsvdPageNum8723D(_adapter *padapter, bool wowlan); -#endif diff --git a/include/rtl8723d_dm.h b/include/rtl8723d_dm.h deleted file mode 100644 index bae086d..0000000 --- a/include/rtl8723d_dm.h +++ /dev/null @@ -1,47 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8723D_DM_H__ -#define __RTL8723D_DM_H__ -/* ************************************************************ - * Description: - * - * This file is for 8723D dynamic mechanism only - * - * - * ************************************************************ */ - -/* ************************************************************ - * structure and define - * ************************************************************ */ - -/* ************************************************************ - * function prototype - * ************************************************************ */ - -void rtl8723d_init_dm_priv(PADAPTER padapter); -void rtl8723d_deinit_dm_priv(PADAPTER padapter); - -void rtl8723d_InitHalDm(PADAPTER padapter); -void rtl8723d_HalDmWatchDog(PADAPTER padapter); -void rtl8723d_HalDmWatchDog_in_LPS(PADAPTER padapter); -void rtl8723d_hal_dm_in_lps(PADAPTER padapter); - - -#endif diff --git a/include/rtl8723d_hal.h b/include/rtl8723d_hal.h deleted file mode 100644 index 494dad3..0000000 --- a/include/rtl8723d_hal.h +++ /dev/null @@ -1,316 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8723D_HAL_H__ -#define __RTL8723D_HAL_H__ - -#include "hal_data.h" - -#include "rtl8723d_spec.h" -#include "rtl8723d_rf.h" -#include "rtl8723d_dm.h" -#include "rtl8723d_recv.h" -#include "rtl8723d_xmit.h" -#include "rtl8723d_cmd.h" -#include "rtl8723d_led.h" -#include "Hal8723DPwrSeq.h" -#include "Hal8723DPhyReg.h" -#include "Hal8723DPhyCfg.h" -#ifdef DBG_CONFIG_ERROR_DETECT - #include "rtl8723d_sreset.h" -#endif -#ifdef CONFIG_LPS_POFF - #include "rtl8723d_lps_poff.h" -#endif - -#define FW_8723D_SIZE 0x8000 -#define FW_8723D_START_ADDRESS 0x1000 -#define FW_8723D_END_ADDRESS 0x1FFF /* 0x5FFF */ - -#define IS_FW_HEADER_EXIST_8723D(_pFwHdr)\ - ((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x23D0) - -typedef struct _RT_FIRMWARE { - FIRMWARE_SOURCE eFWSource; -#ifdef CONFIG_EMBEDDED_FWIMG - u8 *szFwBuffer; -#else - u8 szFwBuffer[FW_8723D_SIZE]; -#endif - u32 ulFwLength; -} RT_FIRMWARE_8723D, *PRT_FIRMWARE_8723D; - -/* - * This structure must be cared byte-ordering - * - * Added by tynli. 2009.12.04. */ -typedef struct _RT_8723D_FIRMWARE_HDR { - /* 8-byte alinment required */ - - /* --- LONG WORD 0 ---- */ - u16 Signature; /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */ - u8 Category; /* AP/NIC and USB/PCI */ - u8 Function; /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */ - u16 Version; /* FW Version */ - u16 Subversion; /* FW Subversion, default 0x00 */ - - /* --- LONG WORD 1 ---- */ - u8 Month; /* Release time Month field */ - u8 Date; /* Release time Date field */ - u8 Hour; /* Release time Hour field */ - u8 Minute; /* Release time Minute field */ - u16 RamCodeSize; /* The size of RAM code */ - u16 Rsvd2; - - /* --- LONG WORD 2 ---- */ - u32 SvnIdx; /* The SVN entry index */ - u32 Rsvd3; - - /* --- LONG WORD 3 ---- */ - u32 Rsvd4; - u32 Rsvd5; -} RT_8723D_FIRMWARE_HDR, *PRT_8723D_FIRMWARE_HDR; - -#define DRIVER_EARLY_INT_TIME_8723D 0x05 -#define BCN_DMA_ATIME_INT_TIME_8723D 0x02 - -/* for 8723D - * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */ -#define PAGE_SIZE_TX_8723D 128 -#define PAGE_SIZE_RX_8723D 8 - -#define TX_DMA_SIZE_8723D 0x8000 /* 32K(TX) */ -#define RX_DMA_SIZE_8723D 0x4000 /* 16K(RX) */ - -#ifdef CONFIG_WOWLAN - #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/ -#else - #define RESV_FMWF 0 -#endif - -#ifdef CONFIG_FW_C2H_DEBUG - #define RX_DMA_RESERVED_SIZE_8723D 0x100 /* 256B, reserved for c2h debug message */ -#else - #define RX_DMA_RESERVED_SIZE_8723D 0x80 /* 128B, reserved for tx report */ -#endif -#define RX_DMA_BOUNDARY_8723D\ - (RX_DMA_SIZE_8723D - RX_DMA_RESERVED_SIZE_8723D - 1) - - -/* Note: We will divide number of page equally for each queue other than public queue! */ - -/* For General Reserved Page Number(Beacon Queue is reserved page) - * Beacon:2, PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1 */ -#define BCNQ_PAGE_NUM_8723D 0x08 -#ifdef CONFIG_CONCURRENT_MODE - #define BCNQ1_PAGE_NUM_8723D 0x08 /* 0x04 */ -#else - #define BCNQ1_PAGE_NUM_8723D 0x00 -#endif - -#ifdef CONFIG_PNO_SUPPORT - #undef BCNQ1_PAGE_NUM_8723D - #define BCNQ1_PAGE_NUM_8723D 0x00 /* 0x04 */ -#endif - -/* For WoWLan , more reserved page - * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6 */ -#ifdef CONFIG_WOWLAN - #define WOWLAN_PAGE_NUM_8723D 0x08 -#else - #define WOWLAN_PAGE_NUM_8723D 0x00 -#endif - -#ifdef CONFIG_PNO_SUPPORT - #undef WOWLAN_PAGE_NUM_8723D - #define WOWLAN_PAGE_NUM_8723D 0x15 -#endif - -#ifdef CONFIG_AP_WOWLAN - #define AP_WOWLAN_PAGE_NUM_8723D 0x02 -#endif - -#define TX_TOTAL_PAGE_NUMBER_8723D\ - (0xFF - BCNQ_PAGE_NUM_8723D - BCNQ1_PAGE_NUM_8723D - WOWLAN_PAGE_NUM_8723D) -#define TX_PAGE_BOUNDARY_8723D (TX_TOTAL_PAGE_NUMBER_8723D + 1) - -#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723D TX_TOTAL_PAGE_NUMBER_8723D -#define WMM_NORMAL_TX_PAGE_BOUNDARY_8723D\ - (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723D + 1) - -/* For Normal Chip Setting - * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8723D */ -#define NORMAL_PAGE_NUM_HPQ_8723D 0x0C -#define NORMAL_PAGE_NUM_LPQ_8723D 0x02 -#define NORMAL_PAGE_NUM_NPQ_8723D 0x02 - -/* Note: For Normal Chip Setting, modify later */ -#define WMM_NORMAL_PAGE_NUM_HPQ_8723D 0x30 -#define WMM_NORMAL_PAGE_NUM_LPQ_8723D 0x20 -#define WMM_NORMAL_PAGE_NUM_NPQ_8723D 0x20 - - -#include "HalVerDef.h" -#include "hal_com.h" - -#define EFUSE_OOB_PROTECT_BYTES (96 + 1) - -#define HAL_EFUSE_MEMORY -#define HWSET_MAX_SIZE_8723D 512 -#define EFUSE_REAL_CONTENT_LEN_8723D 512 -#define EFUSE_MAP_LEN_8723D 512 -#define EFUSE_MAX_SECTION_8723D 64 - -/* For some inferiority IC purpose. added by Roger, 2009.09.02.*/ -#define EFUSE_IC_ID_OFFSET 506 -#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN_8723D) - -#define EFUSE_ACCESS_ON 0x69 -#define EFUSE_ACCESS_OFF 0x00 - -/* ******************************************************** - * EFUSE for BT definition - * ******************************************************** */ -#define BANK_NUM 1 -#define EFUSE_BT_REAL_BANK_CONTENT_LEN 128 -#define EFUSE_BT_REAL_CONTENT_LEN \ - (EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM) -#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */ -#define EFUSE_BT_MAX_SECTION (EFUSE_BT_MAP_LEN / 8) -#define EFUSE_PROTECT_BYTES_BANK 16 - -typedef enum tag_Package_Definition { - PACKAGE_DEFAULT, - PACKAGE_QFN68, - PACKAGE_TFBGA90, - PACKAGE_TFBGA80, - PACKAGE_TFBGA79 -} PACKAGE_TYPE_E; - -#define INCLUDE_MULTI_FUNC_BT(_Adapter) \ - (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT) -#define INCLUDE_MULTI_FUNC_GPS(_Adapter) \ - (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) - -#ifdef CONFIG_FILE_FWIMG - extern char *rtw_fw_file_path; - extern char *rtw_fw_wow_file_path; - #ifdef CONFIG_MP_INCLUDED - extern char *rtw_fw_mp_bt_file_path; - #endif /* CONFIG_MP_INCLUDED */ -#endif /* CONFIG_FILE_FWIMG */ - -/* rtl8723d_hal_init.c */ -s32 rtl8723d_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw); -void rtl8723d_FirmwareSelfReset(PADAPTER padapter); -void rtl8723d_InitializeFirmwareVars(PADAPTER padapter); - -void rtl8723d_InitAntenna_Selection(PADAPTER padapter); -void rtl8723d_DeinitAntenna_Selection(PADAPTER padapter); -void rtl8723d_CheckAntenna_Selection(PADAPTER padapter); -void rtl8723d_init_default_value(PADAPTER padapter); - -s32 rtl8723d_InitLLTTable(PADAPTER padapter); - -s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU); -s32 CardDisableWithoutHWSM(PADAPTER padapter); - -/* EFuse */ -u8 GetEEPROMSize8723D(PADAPTER padapter); -void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent); -void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo); -void Hal_EfuseParseTxPowerInfo_8723D(PADAPTER padapter, - u8 *PROMContent, BOOLEAN AutoLoadFail); -void Hal_EfuseParseBTCoexistInfo_8723D(PADAPTER padapter, - u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParseEEPROMVer_8723D(PADAPTER padapter, - u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParsePackageType_8723D(PADAPTER pAdapter, - u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParseChnlPlan_8723D(PADAPTER padapter, - u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParseCustomerID_8723D(PADAPTER padapter, - u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParseAntennaDiversity_8723D(PADAPTER padapter, - u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParseXtal_8723D(PADAPTER pAdapter, - u8 *hwinfo, u8 AutoLoadFail); -void Hal_EfuseParseThermalMeter_8723D(PADAPTER padapter, - u8 *hwinfo, u8 AutoLoadFail); -VOID Hal_EfuseParseVoltage_8723D(PADAPTER pAdapter, - u8 *hwinfo, BOOLEAN AutoLoadFail); -VOID Hal_EfuseParseBoardType_8723D(PADAPTER Adapter, - u8 *PROMContent, BOOLEAN AutoloadFail); - -void rtl8723d_set_hal_ops(struct hal_ops *pHalFunc); -void init_hal_spec_8723d(_adapter *adapter); -void SetHwReg8723D(PADAPTER padapter, u8 variable, u8 *val); -void GetHwReg8723D(PADAPTER padapter, u8 variable, u8 *val); -u8 SetHalDefVar8723D(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); -u8 GetHalDefVar8723D(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); - -/* register */ -void rtl8723d_InitBeaconParameters(PADAPTER padapter); -void rtl8723d_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode); -void _InitBurstPktLen_8723DS(PADAPTER Adapter); -void _InitLTECoex_8723DS(PADAPTER Adapter); -void _InitMacAPLLSetting_8723D(PADAPTER Adapter); -void _8051Reset8723(PADAPTER padapter); -#ifdef CONFIG_WOWLAN - void Hal_DetectWoWMode(PADAPTER pAdapter); -#endif /* CONFIG_WOWLAN */ - -void rtl8723d_start_thread(_adapter *padapter); -void rtl8723d_stop_thread(_adapter *padapter); - -#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST) - void rtl8723ds_init_checkbthang_workqueue(_adapter *adapter); - void rtl8723ds_free_checkbthang_workqueue(_adapter *adapter); - void rtl8723ds_cancle_checkbthang_workqueue(_adapter *adapter); - void rtl8723ds_hal_check_bt_hang(_adapter *adapter); -#endif - -#ifdef CONFIG_GPIO_WAKEUP - void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue); -#endif -#ifdef CONFIG_MP_INCLUDED -int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware); -#endif -void CCX_FwC2HTxRpt_8723d(PADAPTER padapter, u8 *pdata, u8 len); - -u8 MRateToHwRate8723D(u8 rate); -u8 HwRateToMRate8723D(u8 rate); - -void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); - -#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST) - void check_bt_status_work(void *data); -#endif - -#ifdef CONFIG_USB_HCI - void rtl8723d_cal_txdesc_chksum(struct tx_desc *ptxdesc); -#endif - -#ifdef CONFIG_PCI_HCI - BOOLEAN InterruptRecognized8723DE(PADAPTER Adapter); - VOID UpdateInterruptMask8723DE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1); - u16 get_txbufdesc_idx_hwaddr(u16 ff_hwaddr); -#endif - -#endif diff --git a/include/rtl8723d_led.h b/include/rtl8723d_led.h deleted file mode 100644 index 439ee82..0000000 --- a/include/rtl8723d_led.h +++ /dev/null @@ -1,48 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8723D_LED_H__ -#define __RTL8723D_LED_H__ - -#include -#include -#include - - -/* ******************************************************************************** - * Interface to manipulate LED objects. - * ******************************************************************************** */ -#ifdef CONFIG_USB_HCI - void rtl8723du_InitSwLeds(PADAPTER padapter); - void rtl8723du_DeInitSwLeds(PADAPTER padapter); -#endif -#ifdef CONFIG_SDIO_HCI - void rtl8723ds_InitSwLeds(PADAPTER padapter); - void rtl8723ds_DeInitSwLeds(PADAPTER padapter); -#endif -#ifdef CONFIG_GSPI_HCI - void rtl8723ds_InitSwLeds(PADAPTER padapter); - void rtl8723ds_DeInitSwLeds(PADAPTER padapter); -#endif -#ifdef CONFIG_PCI_HCI - void rtl8723de_InitSwLeds(PADAPTER padapter); - void rtl8723de_DeInitSwLeds(PADAPTER padapter); -#endif - -#endif diff --git a/include/rtl8723d_lps_poff.h b/include/rtl8723d_lps_poff.h deleted file mode 100644 index c466d40..0000000 --- a/include/rtl8723d_lps_poff.h +++ /dev/null @@ -1,61 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -/******************************************** CONST ************************/ -#define NUM_OF_REGISTER_BANK 13 -#define NUM_OF_TOTAL_DWORD (NUM_OF_REGISTER_BANK * 64) -#define TOTAL_LEN_FOR_HIOE ((NUM_OF_TOTAL_DWORD + 1) * 8) -#define LPS_POFF_STATIC_FILE_LEN (TOTAL_LEN_FOR_HIOE + TXDESC_SIZE) -#define LPS_POFF_DYNAMIC_FILE_LEN (512 + TXDESC_SIZE) -/******************************************** CONST ************************/ - -/******************************************** MACRO ************************/ -/* HOIE Entry Definition */ -#define SET_HOIE_ENTRY_LOW_DATA(__pHOIE, __Value) \ - SET_BITS_TO_LE_4BYTE((__pHOIE), 0, 16, __Value) -#define SET_HOIE_ENTRY_HIGH_DATA(__pHOIE, __Value) \ - SET_BITS_TO_LE_4BYTE((__pHOIE), 16, 16, __Value) -#define SET_HOIE_ENTRY_MODE_SELECT(__pHOIE, __Value) \ - SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 0, 1, __Value) -#define SET_HOIE_ENTRY_ADDRESS(__pHOIE, __Value) \ - SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 1, 14, __Value) -#define SET_HOIE_ENTRY_BYTE_MASK(__pHOIE, __Value) \ - SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 15, 4, __Value) -#define SET_HOIE_ENTRY_IO_LOCK(__pHOIE, __Value) \ - SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 19, 1, __Value) -#define SET_HOIE_ENTRY_RD_EN(__pHOIE, __Value) \ - SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 20, 1, __Value) -#define SET_HOIE_ENTRY_WR_EN(__pHOIE, __Value) \ - SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 21, 1, __Value) -#define SET_HOIE_ENTRY_RAW_RW(__pHOIE, __Value) \ - SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 22, 1, __Value) -#define SET_HOIE_ENTRY_RAW(__pHOIE, __Value) \ - SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 23, 1, __Value) -#define SET_HOIE_ENTRY_IO_DELAY(__pHOIE, __Value) \ - SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 24, 8, __Value) - -/*********************Function Definition*******************************************/ -void rtl8723d_lps_poff_init(PADAPTER padapter); -void rtl8723d_lps_poff_deinit(PADAPTER padapter); -bool rtl8723d_lps_poff_get_txbndy_status(PADAPTER padapter); -void rtl8723d_lps_poff_h2c_ctrl(PADAPTER padapter, u8 enable); -void rtl8723d_lps_poff_set_ps_mode(PADAPTER padapter, bool bEnterLPS); -bool rtl8723d_lps_poff_get_status(PADAPTER padapter); -void rtl8723d_lps_poff_wow(PADAPTER padapter); diff --git a/include/rtl8723d_recv.h b/include/rtl8723d_recv.h deleted file mode 100644 index 713b89a..0000000 --- a/include/rtl8723d_recv.h +++ /dev/null @@ -1,116 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8723D_RECV_H__ -#define __RTL8723D_RECV_H__ - -#define RECV_BLK_SZ 512 -#define RECV_BLK_CNT 16 -#define RECV_BLK_TH RECV_BLK_CNT - -#if defined(CONFIG_USB_HCI) - - #ifndef MAX_RECVBUF_SZ - #ifndef CONFIG_MINIMAL_MEMORY_USAGE - /* #define MAX_RECVBUF_SZ (32768) */ /* 32k */ - /* #define MAX_RECVBUF_SZ (16384) */ /* 16K */ - /* #define MAX_RECVBUF_SZ (10240) */ /* 10K */ - #ifdef CONFIG_PLATFORM_MSTAR - #define MAX_RECVBUF_SZ (8192) /* 8K */ - #else - #define MAX_RECVBUF_SZ (15360) /* 15k < 16k */ - #endif - /* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */ - #else - #define MAX_RECVBUF_SZ (4000) /* about 4K */ - #endif - #endif /* !MAX_RECVBUF_SZ */ - -#elif defined(CONFIG_PCI_HCI) - /* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */ - /* #define MAX_RECVBUF_SZ (9100) */ - /* #else */ - #define MAX_RECVBUF_SZ (4000) /* about 4K - * #endif */ - - -#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - - #define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8723D + 1) - -#endif - -/* Rx smooth factor */ -#define Rx_Smooth_Factor (20) - -#ifdef CONFIG_SDIO_HCI - #ifndef CONFIG_SDIO_RX_COPY - #undef MAX_RECVBUF_SZ - #define MAX_RECVBUF_SZ (RX_DMA_SIZE_8723D - RX_DMA_RESERVED_SIZE_8723D) - #endif /* !CONFIG_SDIO_RX_COPY */ -#endif /* CONFIG_SDIO_HCI */ - -/*-----------------------------------------------------------------*/ -/* RTL8723D RX BUFFER DESC */ -/*-----------------------------------------------------------------*/ -/*DWORD 0*/ -#define SET_RX_BUFFER_DESC_DATA_LENGTH_8723D(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value) -#define SET_RX_BUFFER_DESC_LS_8723D(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value) -#define SET_RX_BUFFER_DESC_FS_8723D(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value) -#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8723D(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value) - -#define GET_RX_BUFFER_DESC_OWN_8723D(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1) -#define GET_RX_BUFFER_DESC_LS_8723D(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1) -#define GET_RX_BUFFER_DESC_FS_8723D(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1) -#ifdef USING_RX_TAG - #define GET_RX_BUFFER_DESC_RX_TAG_8723D(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 13) -#else - #define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8723D(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15) -#endif - -/*DWORD 1*/ -#define SET_RX_BUFFER_PHYSICAL_LOW_8723D(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value) - -/*DWORD 2*/ -#ifdef CONFIG_64BIT_DMA - #define SET_RX_BUFFER_PHYSICAL_HIGH_8723D(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value) -#else - #define SET_RX_BUFFER_PHYSICAL_HIGH_8723D(__pRxStatusDesc, __Value) -#endif - - -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - s32 rtl8723ds_init_recv_priv(PADAPTER padapter); - void rtl8723ds_free_recv_priv(PADAPTER padapter); -#endif - -#ifdef CONFIG_USB_HCI - int rtl8723du_init_recv_priv(_adapter *padapter); - void rtl8723du_free_recv_priv(_adapter *padapter); - void rtl8723du_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf); -#endif - -#ifdef CONFIG_PCI_HCI - s32 rtl8723de_init_recv_priv(PADAPTER padapter); - void rtl8723de_free_recv_priv(PADAPTER padapter); -#endif - -void rtl8723d_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc); - -#endif /* __RTL8723D_RECV_H__ */ diff --git a/include/rtl8723d_rf.h b/include/rtl8723d_rf.h deleted file mode 100644 index 0aa5813..0000000 --- a/include/rtl8723d_rf.h +++ /dev/null @@ -1,26 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8723D_RF_H__ -#define __RTL8723D_RF_H__ - -int PHY_RF6052_Config8723D(IN PADAPTER pdapter); - -void PHY_RF6052SetBandwidth8723D(IN PADAPTER Adapter, IN CHANNEL_WIDTH Bandwidth); -#endif diff --git a/include/rtl8723d_spec.h b/include/rtl8723d_spec.h deleted file mode 100644 index 21653f2..0000000 --- a/include/rtl8723d_spec.h +++ /dev/null @@ -1,445 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ -#ifndef __RTL8723D_SPEC_H__ -#define __RTL8723D_SPEC_H__ - -#include - - -#define HAL_NAV_UPPER_UNIT_8723D 128 /* micro-second */ - -/* ----------------------------------------------------- - * - * 0x0000h ~ 0x00FFh System Configuration - * - * ----------------------------------------------------- */ -#define REG_SYS_ISO_CTRL_8723D 0x0000 /* 2 Byte */ -#define REG_SYS_FUNC_EN_8723D 0x0002 /* 2 Byte */ -#define REG_APS_FSMCO_8723D 0x0004 /* 4 Byte */ -#define REG_SYS_CLKR_8723D 0x0008 /* 2 Byte */ -#define REG_9346CR_8723D 0x000A /* 2 Byte */ -#define REG_EE_VPD_8723D 0x000C /* 2 Byte */ -#define REG_AFE_MISC_8723D 0x0010 /* 1 Byte */ -#define REG_SPS0_CTRL_8723D 0x0011 /* 7 Byte */ -#define REG_SPS_OCP_CFG_8723D 0x0018 /* 4 Byte */ -#define REG_RSV_CTRL_8723D 0x001C /* 3 Byte */ -#define REG_RF_CTRL_8723D 0x001F /* 1 Byte */ -#define REG_LPLDO_CTRL_8723D 0x0023 /* 1 Byte */ -#define REG_AFE_XTAL_CTRL_8723D 0x0024 /* 4 Byte */ -#define REG_AFE_PLL_CTRL_8723D 0x0028 /* 4 Byte */ -#define REG_MAC_PLL_CTRL_EXT_8723D 0x002c /* 4 Byte */ -#define REG_EFUSE_CTRL_8723D 0x0030 -#define REG_EFUSE_TEST_8723D 0x0034 -#define REG_PWR_DATA_8723D 0x0038 -#define REG_CAL_TIMER_8723D 0x003C -#define REG_ACLK_MON_8723D 0x003E -#define REG_GPIO_MUXCFG_8723D 0x0040 -#define REG_GPIO_IO_SEL_8723D 0x0042 -#define REG_MAC_PINMUX_CFG_8723D 0x0043 -#define REG_GPIO_PIN_CTRL_8723D 0x0044 -#define REG_GPIO_INTM_8723D 0x0048 -#define REG_LEDCFG0_8723D 0x004C -#define REG_LEDCFG1_8723D 0x004D -#define REG_LEDCFG2_8723D 0x004E -#define REG_LEDCFG3_8723D 0x004F -#define REG_FSIMR_8723D 0x0050 -#define REG_FSISR_8723D 0x0054 -#define REG_HSIMR_8723D 0x0058 -#define REG_HSISR_8723D 0x005c -#define REG_GPIO_EXT_CTRL 0x0060 -#define REG_PAD_CTRL1_8723D 0x0064 -#define REG_MULTI_FUNC_CTRL_8723D 0x0068 -#define REG_GPIO_STATUS_8723D 0x006C -#define REG_SDIO_CTRL_8723D 0x0070 -#define REG_OPT_CTRL_8723D 0x0074 -#define REG_AFE_CTRL_4_8723D 0x0078 -#define REG_MCUFWDL_8723D 0x0080 -#define REG_8051FW_CTRL_8723D 0x0080 -#define REG_HMEBOX_DBG_0_8723D 0x0088 -#define REG_HMEBOX_DBG_1_8723D 0x008A -#define REG_HMEBOX_DBG_2_8723D 0x008C -#define REG_HMEBOX_DBG_3_8723D 0x008E -#define REG_WLLPS_CTRL 0x0090 -#define REG_HIMR0_8723D 0x00B0 -#define REG_HISR0_8723D 0x00B4 -#define REG_HIMR1_8723D 0x00B8 -#define REG_HISR1_8723D 0x00BC -#define REG_PMC_DBG_CTRL2_8723D 0x00CC -#define REG_EFUSE_BURN_GNT_8723D 0x00CF -#define REG_HPON_FSM_8723D 0x00EC -#define REG_SYS_CFG_8723D 0x00FC -#define REG_ROM_VERSION 0x00FD - -/* ----------------------------------------------------- - * - * 0x0100h ~ 0x01FFh MACTOP General Configuration - * - * ----------------------------------------------------- */ -#define REG_C2HEVT_CMD_ID_8723D 0x01A0 -#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 -#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 -#define REG_C2HEVT_CMD_LEN_8723D 0x01AE -#define REG_C2HEVT_CLEAR_8723D 0x01AF -#define REG_MCUTST_1_8723D 0x01C0 -#define REG_WOWLAN_WAKE_REASON 0x01C7 -#define REG_FMETHR_8723D 0x01C8 -#define REG_HMETFR_8723D 0x01CC -#define REG_HMEBOX_0_8723D 0x01D0 -#define REG_HMEBOX_1_8723D 0x01D4 -#define REG_HMEBOX_2_8723D 0x01D8 -#define REG_HMEBOX_3_8723D 0x01DC -#define REG_LLT_INIT_8723D 0x01E0 -#define REG_HMEBOX_EXT0_8723D 0x01F0 -#define REG_HMEBOX_EXT1_8723D 0x01F4 -#define REG_HMEBOX_EXT2_8723D 0x01F8 -#define REG_HMEBOX_EXT3_8723D 0x01FC - -/* ----------------------------------------------------- - * - * 0x0200h ~ 0x027Fh TXDMA Configuration - * - * ----------------------------------------------------- */ -#define REG_RQPN_8723D 0x0200 -#define REG_FIFOPAGE_8723D 0x0204 -#define REG_DWBCN0_CTRL_8723D REG_TDECTRL -#define REG_TXDMA_OFFSET_CHK_8723D 0x020C -#define REG_TXDMA_STATUS_8723D 0x0210 -#define REG_RQPN_NPQ_8723D 0x0214 -#define REG_DWBCN1_CTRL_8723D 0x0228 - - -/* ----------------------------------------------------- - * - * 0x0280h ~ 0x02FFh RXDMA Configuration - * - * ----------------------------------------------------- */ -#define REG_RXDMA_AGG_PG_TH_8723D 0x0280 -#define REG_FW_UPD_RDPTR_8723D 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */ -#define REG_RXDMA_CONTROL_8723D 0x0286 /* Control the RX DMA. */ -#define REG_RXDMA_STATUS_8723D 0x0288 -#define REG_RXDMA_MODE_CTRL_8723D 0x0290 -#define REG_EARLY_MODE_CONTROL_8723D 0x02BC -#define REG_RSVD5_8723D 0x02F0 -#define REG_RSVD6_8723D 0x02F4 - -/* ----------------------------------------------------- - * - * 0x0300h ~ 0x03FFh PCIe - * - * ----------------------------------------------------- */ -#define REG_PCIE_CTRL_REG_8723D 0x0300 -#define REG_INT_MIG_8723D 0x0304 /* Interrupt Migration */ -#define REG_BCNQ_TXBD_DESA_8723D 0x0308 /* TX Beacon Descriptor Address */ -#define REG_MGQ_TXBD_DESA_8723D 0x0310 /* TX Manage Queue Descriptor Address */ -#define REG_VOQ_TXBD_DESA_8723D 0x0318 /* TX VO Queue Descriptor Address */ -#define REG_VIQ_TXBD_DESA_8723D 0x0320 /* TX VI Queue Descriptor Address */ -#define REG_BEQ_TXBD_DESA_8723D 0x0328 /* TX BE Queue Descriptor Address */ -#define REG_BKQ_TXBD_DESA_8723D 0x0330 /* TX BK Queue Descriptor Address */ -#define REG_RXQ_RXBD_DESA_8723D 0x0338 /* RX Queue Descriptor Address */ -#define REG_HI0Q_TXBD_DESA_8723D 0x0340 -#define REG_HI1Q_TXBD_DESA_8723D 0x0348 -#define REG_HI2Q_TXBD_DESA_8723D 0x0350 -#define REG_HI3Q_TXBD_DESA_8723D 0x0358 -#define REG_HI4Q_TXBD_DESA_8723D 0x0360 -#define REG_HI5Q_TXBD_DESA_8723D 0x0368 -#define REG_HI6Q_TXBD_DESA_8723D 0x0370 -#define REG_HI7Q_TXBD_DESA_8723D 0x0378 -#define REG_MGQ_TXBD_NUM_8723D 0x0380 -#define REG_RX_RXBD_NUM_8723D 0x0382 -#define REG_VOQ_TXBD_NUM_8723D 0x0384 -#define REG_VIQ_TXBD_NUM_8723D 0x0386 -#define REG_BEQ_TXBD_NUM_8723D 0x0388 -#define REG_BKQ_TXBD_NUM_8723D 0x038A -#define REG_HI0Q_TXBD_NUM_8723D 0x038C -#define REG_HI1Q_TXBD_NUM_8723D 0x038E -#define REG_HI2Q_TXBD_NUM_8723D 0x0390 -#define REG_HI3Q_TXBD_NUM_8723D 0x0392 -#define REG_HI4Q_TXBD_NUM_8723D 0x0394 -#define REG_HI5Q_TXBD_NUM_8723D 0x0396 -#define REG_HI6Q_TXBD_NUM_8723D 0x0398 -#define REG_HI7Q_TXBD_NUM_8723D 0x039A -#define REG_TSFTIMER_HCI_8723D 0x039C -#define REG_BD_RW_PTR_CLR_8723D 0x039C - -/* Read Write Point */ -#define REG_VOQ_TXBD_IDX_8723D 0x03A0 -#define REG_VIQ_TXBD_IDX_8723D 0x03A4 -#define REG_BEQ_TXBD_IDX_8723D 0x03A8 -#define REG_BKQ_TXBD_IDX_8723D 0x03AC -#define REG_MGQ_TXBD_IDX_8723D 0x03B0 -#define REG_RXQ_TXBD_IDX_8723D 0x03B4 -#define REG_HI0Q_TXBD_IDX_8723D 0x03B8 -#define REG_HI1Q_TXBD_IDX_8723D 0x03BC -#define REG_HI2Q_TXBD_IDX_8723D 0x03C0 -#define REG_HI3Q_TXBD_IDX_8723D 0x03C4 -#define REG_HI4Q_TXBD_IDX_8723D 0x03C8 -#define REG_HI5Q_TXBD_IDX_8723D 0x03CC -#define REG_HI6Q_TXBD_IDX_8723D 0x03D0 -#define REG_HI7Q_TXBD_IDX_8723D 0x03D4 - -#define REG_PCIE_HCPWM_8723DE 0x03D8 /* ?????? */ -#define REG_PCIE_HRPWM_8723DE 0x03DC /* PCIe RPWM ?????? */ -#define REG_DBI_WDATA_V1_8723D 0x03E8 -#define REG_DBI_RDATA_V1_8723D 0x03EC -#define REG_DBI_FLAG_V1_8723D 0x03F0 -#define REG_MDIO_V1_8723D 0x03F4 -#define REG_PCIE_MIX_CFG_8723D 0x03F8 -#define REG_HCI_MIX_CFG_8723D 0x03FC - -/* ----------------------------------------------------- - * - * 0x0400h ~ 0x047Fh Protocol Configuration - * - * ----------------------------------------------------- */ -#define REG_VOQ_INFORMATION_8723D 0x0400 -#define REG_VIQ_INFORMATION_8723D 0x0404 -#define REG_BEQ_INFORMATION_8723D 0x0408 -#define REG_BKQ_INFORMATION_8723D 0x040C -#define REG_MGQ_INFORMATION_8723D 0x0410 -#define REG_HGQ_INFORMATION_8723D 0x0414 -#define REG_BCNQ_INFORMATION_8723D 0x0418 -#define REG_TXPKT_EMPTY_8723D 0x041A - -#define REG_FWHW_TXQ_CTRL_8723D 0x0420 -#define REG_HWSEQ_CTRL_8723D 0x0423 -#define REG_TXPKTBUF_BCNQ_BDNY_8723D 0x0424 -#define REG_TXPKTBUF_MGQ_BDNY_8723D 0x0425 -#define REG_LIFECTRL_CTRL_8723D 0x0426 -#define REG_MULTI_BCNQ_OFFSET_8723D 0x0427 -#define REG_SPEC_SIFS_8723D 0x0428 -#define REG_RL_8723D 0x042A -#define REG_TXBF_CTRL_8723D 0x042C -#define REG_DARFRC_8723D 0x0430 -#define REG_RARFRC_8723D 0x0438 -#define REG_RRSR_8723D 0x0440 -#define REG_ARFR0_8723D 0x0444 -#define REG_ARFR1_8723D 0x044C -#define REG_CCK_CHECK_8723D 0x0454 -#define REG_AMPDU_MAX_TIME_8723D 0x0456 -#define REG_TXPKTBUF_BCNQ_BDNY1_8723D 0x0457 - -#define REG_AMPDU_MAX_LENGTH_8723D 0x0458 -#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723D 0x045D -#define REG_NDPA_OPT_CTRL_8723D 0x045F -#define REG_FAST_EDCA_CTRL_8723D 0x0460 -#define REG_RD_RESP_PKT_TH_8723D 0x0463 -#define REG_DATA_SC_8723D 0x0483 -#ifdef CONFIG_WOWLAN - #define REG_TXPKTBUF_IV_LOW 0x0484 - #define REG_TXPKTBUF_IV_HIGH 0x0488 -#endif -#define REG_TXRPT_START_OFFSET 0x04AC -#define REG_POWER_STAGE1_8723D 0x04B4 -#define REG_POWER_STAGE2_8723D 0x04B8 -#define REG_AMPDU_BURST_MODE_8723D 0x04BC -#define REG_PKT_VO_VI_LIFE_TIME_8723D 0x04C0 -#define REG_PKT_BE_BK_LIFE_TIME_8723D 0x04C2 -#define REG_STBC_SETTING_8723D 0x04C4 -#define REG_HT_SINGLE_AMPDU_8723D 0x04C7 -#define REG_PROT_MODE_CTRL_8723D 0x04C8 -#define REG_MAX_AGGR_NUM_8723D 0x04CA -#define REG_RTS_MAX_AGGR_NUM_8723D 0x04CB -#define REG_BAR_MODE_CTRL_8723D 0x04CC -#define REG_RA_TRY_RATE_AGG_LMT_8723D 0x04CF -#define REG_MACID_PKT_DROP0_8723D 0x04D0 -#define REG_MACID_PKT_SLEEP_8723D 0x04D4 - -/* ----------------------------------------------------- - * - * 0x0500h ~ 0x05FFh EDCA Configuration - * - * ----------------------------------------------------- */ -#define REG_EDCA_VO_PARAM_8723D 0x0500 -#define REG_EDCA_VI_PARAM_8723D 0x0504 -#define REG_EDCA_BE_PARAM_8723D 0x0508 -#define REG_EDCA_BK_PARAM_8723D 0x050C -#define REG_BCNTCFG_8723D 0x0510 -#define REG_PIFS_8723D 0x0512 -#define REG_RDG_PIFS_8723D 0x0513 -#define REG_SIFS_CTX_8723D 0x0514 -#define REG_SIFS_TRX_8723D 0x0516 -#define REG_AGGR_BREAK_TIME_8723D 0x051A -#define REG_SLOT_8723D 0x051B -#define REG_TX_PTCL_CTRL_8723D 0x0520 -#define REG_TXPAUSE_8723D 0x0522 -#define REG_DIS_TXREQ_CLR_8723D 0x0523 -#define REG_RD_CTRL_8723D 0x0524 -/* - * Format for offset 540h-542h: - * [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. - * [7:4]: Reserved. - * [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. - * [23:20]: Reserved - * Description: - * | - * |<--Setup--|--Hold------------>| - * --------------|---------------------- - * | - * TBTT - * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. - * Described by Designer Tim and Bruce, 2011-01-14. - * */ -#define REG_TBTT_PROHIBIT_8723D 0x0540 -#define REG_RD_NAV_NXT_8723D 0x0544 -#define REG_NAV_PROT_LEN_8723D 0x0546 -#define REG_BCN_CTRL_8723D 0x0550 -#define REG_BCN_CTRL_1_8723D 0x0551 -#define REG_MBID_NUM_8723D 0x0552 -#define REG_DUAL_TSF_RST_8723D 0x0553 -#define REG_BCN_INTERVAL_8723D 0x0554 -#define REG_DRVERLYINT_8723D 0x0558 -#define REG_BCNDMATIM_8723D 0x0559 -#define REG_ATIMWND_8723D 0x055A -#define REG_USTIME_TSF_8723D 0x055C -#define REG_BCN_MAX_ERR_8723D 0x055D -#define REG_RXTSF_OFFSET_CCK_8723D 0x055E -#define REG_RXTSF_OFFSET_OFDM_8723D 0x055F -#define REG_TSFTR_8723D 0x0560 -#define REG_CTWND_8723D 0x0572 -#define REG_SECONDARY_CCA_CTRL_8723D 0x0577 -#define REG_PSTIMER_8723D 0x0580 -#define REG_TIMER0_8723D 0x0584 -#define REG_TIMER1_8723D 0x0588 -#define REG_ACMHWCTRL_8723D 0x05C0 -#define REG_SCH_TXCMD_8723D 0x05F8 - -/* ----------------------------------------------------- - * - * 0x0600h ~ 0x07FFh WMAC Configuration - * - * ----------------------------------------------------- */ -#define REG_MAC_CR_8723D 0x0600 -#define REG_TCR_8723D 0x0604 -#define REG_RCR_8723D 0x0608 -#define REG_RX_PKT_LIMIT_8723D 0x060C -#define REG_RX_DLK_TIME_8723D 0x060D -#define REG_RX_DRVINFO_SZ_8723D 0x060F - -#define REG_MACID_8723D 0x0610 -#define REG_BSSID_8723D 0x0618 -#define REG_MAR_8723D 0x0620 -#define REG_MBIDCAMCFG_8723D 0x0628 -#define REG_WOWLAN_GTK_DBG1 0x630 -#define REG_WOWLAN_GTK_DBG2 0x634 - -#define REG_USTIME_EDCA_8723D 0x0638 -#define REG_MAC_SPEC_SIFS_8723D 0x063A -#define REG_RESP_SIFP_CCK_8723D 0x063C -#define REG_RESP_SIFS_OFDM_8723D 0x063E -#define REG_ACKTO_8723D 0x0640 -#define REG_CTS2TO_8723D 0x0641 -#define REG_EIFS_8723D 0x0642 - -#define REG_NAV_UPPER_8723D 0x0652 /* unit of 128 */ -#define REG_TRXPTCL_CTL_8723D 0x0668 - -/* Security */ -#define REG_CAMCMD_8723D 0x0670 -#define REG_CAMWRITE_8723D 0x0674 -#define REG_CAMREAD_8723D 0x0678 -#define REG_CAMDBG_8723D 0x067C -#define REG_SECCFG_8723D 0x0680 - -/* Power */ -#define REG_WOW_CTRL_8723D 0x0690 -#define REG_PS_RX_INFO_8723D 0x0692 -#define REG_UAPSD_TID_8723D 0x0693 -#define REG_WKFMCAM_CMD_8723D 0x0698 -#define REG_WKFMCAM_NUM_8723D 0x0698 -#define REG_WKFMCAM_RWD_8723D 0x069C -#define REG_RXFLTMAP0_8723D 0x06A0 -#define REG_RXFLTMAP1_8723D 0x06A2 -#define REG_RXFLTMAP2_8723D 0x06A4 -#define REG_BCN_PSR_RPT_8723D 0x06A8 -#define REG_BT_COEX_TABLE_8723D 0x06C0 -#define REG_BFMER0_INFO_8723D 0x06E4 -#define REG_BFMER1_INFO_8723D 0x06EC -#define REG_CSI_RPT_PARAM_BW20_8723D 0x06F4 -#define REG_CSI_RPT_PARAM_BW40_8723D 0x06F8 -#define REG_CSI_RPT_PARAM_BW80_8723D 0x06FC - -/* Hardware Port 2 */ -#define REG_MACID1_8723D 0x0700 -#define REG_BSSID1_8723D 0x0708 -#define REG_BFMEE_SEL_8723D 0x0714 -#define REG_SND_PTCL_CTRL_8723D 0x0718 - -/* LTE_COEX */ -#define REG_LTECOEX_CTRL 0x07C0 -#define REG_LTECOEX_WRITE_DATA 0x07C4 -#define REG_LTECOEX_READ_DATA 0x07C8 -#define REG_LTECOEX_PATH_CONTROL 0x70 - -/* ************************************************************ - * SDIO Bus Specification - * ************************************************************ */ - -/* ----------------------------------------------------- - * SDIO CMD Address Mapping - * ----------------------------------------------------- */ - -/* ----------------------------------------------------- - * I/O bus domain (Host) - * ----------------------------------------------------- */ - -/* ----------------------------------------------------- - * SDIO register - * ----------------------------------------------------- */ -#define SDIO_REG_HCPWM1_8723D 0x025 /* HCI Current Power Mode 1 */ - - -/* **************************************************************************** - * 8723 Regsiter Bit and Content definition - * **************************************************************************** */ - -#define BIT_USB_RXDMA_AGG_EN BIT(31) -#define RXDMA_AGG_MODE_EN BIT(1) - -#ifdef CONFIG_WOWLAN - #define RXPKT_RELEASE_POLL BIT(16) - #define RXDMA_IDLE BIT(17) - #define RW_RELEASE_EN BIT(18) -#endif - -/* 2 HSISR - * interrupt mask which needs to clear */ -#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\ - HSISR_SPS_OCP_INT |\ - HSISR_RON_INT |\ - HSISR_PDNINT |\ - HSISR_GPIO9_INT) - -#ifdef CONFIG_RF_POWER_TRIM - #ifdef CONFIG_RTL8723D - #define EEPROM_RF_GAIN_OFFSET 0xC1 - #endif - - #define EEPROM_RF_GAIN_VAL 0x1F6 -#endif /*CONFIG_RF_POWER_TRIM*/ - -#ifdef CONFIG_PCI_HCI - /* #define IMR_RX_MASK (IMR_ROK_8723D|IMR_RDU_8723D|IMR_RXFOVW_8723D) */ - #define IMR_TX_MASK (IMR_VODOK_8723D | IMR_VIDOK_8723D | IMR_BEDOK_8723D | IMR_BKDOK_8723D | IMR_MGNTDOK_8723D | IMR_HIGHDOK_8723D) - - #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8723D | IMR_TXBCN0OK_8723D | IMR_TXBCN0ERR_8723D | IMR_BCNDERR0_8723D) - - #define RT_AC_INT_MASKS (IMR_VIDOK_8723D | IMR_VODOK_8723D | IMR_BEDOK_8723D | IMR_BKDOK_8723D) -#endif - -#endif /* __RTL8723D_SPEC_H__ */ diff --git a/include/rtl8723d_sreset.h b/include/rtl8723d_sreset.h deleted file mode 100644 index aafe7c8..0000000 --- a/include/rtl8723d_sreset.h +++ /dev/null @@ -1,29 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef _RTL8723D_SRESET_H_ -#define _RTL8723D_SRESET_H_ - -#include - -#ifdef DBG_CONFIG_ERROR_DETECT - extern void rtl8723d_sreset_xmit_status_check(_adapter *padapter); - extern void rtl8723d_sreset_linked_status_check(_adapter *padapter); -#endif -#endif diff --git a/include/rtl8723d_xmit.h b/include/rtl8723d_xmit.h deleted file mode 100644 index 20f98b0..0000000 --- a/include/rtl8723d_xmit.h +++ /dev/null @@ -1,522 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8723D_XMIT_H__ -#define __RTL8723D_XMIT_H__ - - -#define MAX_TID (15) - - -#ifndef __INC_HAL8723DDESC_H -#define __INC_HAL8723DDESC_H - -#define RX_STATUS_DESC_SIZE_8723D 24 -#define RX_DRV_INFO_SIZE_UNIT_8723D 8 - - -/* DWORD 0 */ -#define SET_RX_STATUS_DESC_PKT_LEN_8723D(__pRxStatusDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value) -#define SET_RX_STATUS_DESC_EOR_8723D(__pRxStatusDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value) -#define SET_RX_STATUS_DESC_OWN_8723D(__pRxStatusDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value) - -#define GET_RX_STATUS_DESC_PKT_LEN_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14) -#define GET_RX_STATUS_DESC_CRC32_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1) -#define GET_RX_STATUS_DESC_ICV_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1) -#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4) -#define GET_RX_STATUS_DESC_SECURITY_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3) -#define GET_RX_STATUS_DESC_QOS_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1) -#define GET_RX_STATUS_DESC_SHIFT_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2) -#define GET_RX_STATUS_DESC_PHY_STATUS_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1) -#define GET_RX_STATUS_DESC_SWDEC_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1) -#define GET_RX_STATUS_DESC_EOR_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1) -#define GET_RX_STATUS_DESC_OWN_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1) - -/* DWORD 1 */ -#define GET_RX_STATUS_DESC_MACID_8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7) -#define GET_RX_STATUS_DESC_TID_8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4) -#define GET_RX_STATUS_DESC_AMSDU_8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1) -#define GET_RX_STATUS_DESC_RXID_MATCH_8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1) -#define GET_RX_STATUS_DESC_PAGGR_8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1) -#define GET_RX_STATUS_DESC_A1_FIT_8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4) -#define GET_RX_STATUS_DESC_CHKERR_8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1) -#define GET_RX_STATUS_DESC_IPVER_8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1) -#define GET_RX_STATUS_DESC_IS_TCPUDP__8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1) -#define GET_RX_STATUS_DESC_CHK_VLD_8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1) -#define GET_RX_STATUS_DESC_PAM_8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1) -#define GET_RX_STATUS_DESC_PWR_8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1) -#define GET_RX_STATUS_DESC_MORE_DATA_8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1) -#define GET_RX_STATUS_DESC_MORE_FRAG_8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1) -#define GET_RX_STATUS_DESC_TYPE_8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2) -#define GET_RX_STATUS_DESC_MC_8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1) -#define GET_RX_STATUS_DESC_BC_8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1) - -/* DWORD 2 */ -#define GET_RX_STATUS_DESC_SEQ_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12) -#define GET_RX_STATUS_DESC_FRAG_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4) -#define GET_RX_STATUS_DESC_RX_IS_QOS_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1) -#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6) -#define GET_RX_STATUS_DESC_RPT_SEL_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1) -#define GET_RX_STATUS_DESC_FCS_OK_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1) - -/* DWORD 3 */ -#define GET_RX_STATUS_DESC_RX_RATE_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7) -#define GET_RX_STATUS_DESC_HTC_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1) -#define GET_RX_STATUS_DESC_EOSP_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1) -#define GET_RX_STATUS_DESC_BSSID_FIT_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2) -#ifdef CONFIG_USB_RX_AGGREGATION -#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8) -#endif -#define GET_RX_STATUS_DESC_PATTERN_MATCH_8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1) -#define GET_RX_STATUS_DESC_UNICAST_MATCH_8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1) -#define GET_RX_STATUS_DESC_MAGIC_MATCH_8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1) - -/* DWORD 6 */ -#define GET_RX_STATUS_DESC_MATCH_ID_8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 7) - -/* DWORD 5 */ -#define GET_RX_STATUS_DESC_TSFL_8723D(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32) - -#define GET_RX_STATUS_DESC_BUFF_ADDR_8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32) -#define GET_RX_STATUS_DESC_BUFF_ADDR64_8723D(__pRxDesc) \ - LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32) - -#define SET_RX_STATUS_DESC_BUFF_ADDR_8723D(__pRxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value) - - -/* Dword 0, rsvd: bit26, bit28 */ -#define GET_TX_DESC_OWN_8723D(__pTxDesc)\ - LE_BITS_TO_4BYTE(__pTxDesc, 31, 1) - -#define SET_TX_DESC_PKT_SIZE_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value) -#define SET_TX_DESC_OFFSET_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value) -#define SET_TX_DESC_BMC_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value) -#define SET_TX_DESC_HTC_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value) -#define SET_TX_DESC_AMSDU_PAD_EN_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value) -#define SET_TX_DESC_NO_ACM_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value) -#define SET_TX_DESC_GF_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value) - -/* Dword 1 */ -#define SET_TX_DESC_MACID_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value) -#define SET_TX_DESC_QUEUE_SEL_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value) -#define SET_TX_DESC_RDG_NAV_EXT_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value) -#define SET_TX_DESC_LSIG_TXOP_EN_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value) -#define SET_TX_DESC_PIFS_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value) -#define SET_TX_DESC_RATE_ID_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value) -#define SET_TX_DESC_EN_DESC_ID_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value) -#define SET_TX_DESC_SEC_TYPE_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value) -#define SET_TX_DESC_PKT_OFFSET_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value) -#define SET_TX_DESC_MORE_DATA_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value) - -/* Dword 2 remove P_AID, G_ID field*/ -#define SET_TX_DESC_CCA_RTS_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value) -#define SET_TX_DESC_AGG_ENABLE_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value) -#define SET_TX_DESC_RDG_ENABLE_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value) -#define SET_TX_DESC_NULL0_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value) -#define SET_TX_DESC_NULL1_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value) -#define SET_TX_DESC_BK_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value) -#define SET_TX_DESC_MORE_FRAG_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value) -#define SET_TX_DESC_RAW_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value) -#define SET_TX_DESC_CCX_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value) -#define SET_TX_DESC_AMPDU_DENSITY_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value) -#define SET_TX_DESC_BT_INT_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value) -#define SET_TX_DESC_FTM_EN_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 30, 1, __Value) - -/* Dword 3 */ -#define SET_TX_DESC_NAV_USE_HDR_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value) -#define SET_TX_DESC_HWSEQ_SEL_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value) -#define SET_TX_DESC_USE_RATE_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value) -#define SET_TX_DESC_DISABLE_RTS_FB_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value) -#define SET_TX_DESC_DISABLE_FB_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value) -#define SET_TX_DESC_CTS2SELF_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value) -#define SET_TX_DESC_RTS_ENABLE_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value) -#define SET_TX_DESC_HW_RTS_ENABLE_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value) -#define SET_TX_DESC_PORT_ID_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 2, __Value) -#define SET_TX_DESC_USE_MAX_LEN_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value) -#define SET_TX_DESC_MAX_AGG_NUM_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value) -#define SET_TX_DESC_AMPDU_MAX_TIME_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value) - -/* Dword 4 */ -#define SET_TX_DESC_TX_RATE_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value) -#define SET_TX_DESC_TX_TRY_RATE_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value) -#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value) -#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value) -#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value) -#define SET_TX_DESC_DATA_RETRY_LIMIT_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value) -#define SET_TX_DESC_RTS_RATE_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value) -#define SET_TX_DESC_PCTS_EN_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value) -#define SET_TX_DESC_PCTS_MASK_IDX_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value) - -/* Dword 5 */ -#define SET_TX_DESC_DATA_SC_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value) -#define SET_TX_DESC_DATA_SHORT_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value) -#define SET_TX_DESC_DATA_BW_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value) -#define SET_TX_DESC_DATA_STBC_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value) -#define SET_TX_DESC_RTS_STBC_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value) -#define SET_TX_DESC_RTS_SHORT_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value) -#define SET_TX_DESC_RTS_SC_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value) -#define SET_TX_DESC_PATH_A_EN_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 1, __Value) -#define SET_TX_DESC_TXPWR_OF_SET_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value) - -/* Dword 6 */ -#define SET_TX_DESC_SW_DEFINE_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value) -#define SET_TX_DESC_MBSSID_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value) -#define SET_TX_DESC_RF_SEL_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value) - -/* Dword 7 */ -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) -#define SET_TX_DESC_TX_BUFFER_SIZE_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) -#elif(DEV_BUS_TYPE == RT_USB_INTERFACE) -#define SET_TX_DESC_TX_DESC_CHECKSUM_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) -#else -#define SET_TX_DESC_TX_TIMESTAMP_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value) -#endif - -#define SET_TX_DESC_USB_TXAGG_NUM_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) - -/* Dword 8 */ -#define SET_TX_DESC_RTS_RC_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value) -#define SET_TX_DESC_BAR_RC_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value) -#define SET_TX_DESC_DATA_RC_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value) -#define SET_TX_DESC_HWSEQ_EN_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) -#define SET_TX_DESC_NEXTHEADPAGE_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value) -#define SET_TX_DESC_TAILPAGE_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value) - -/* Dword 9 */ -#define SET_TX_DESC_PADDING_LEN_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value) -#define SET_TX_DESC_SEQ_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value) -#define SET_TX_DESC_FINAL_DATA_RATE_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value) - - -#define SET_EARLYMODE_PKTNUM_8723D(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value) -#define SET_EARLYMODE_LEN0_8723D(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value) -#define SET_EARLYMODE_LEN1_1_8723D(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value) -#define SET_EARLYMODE_LEN1_2_8723D(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value) -#define SET_EARLYMODE_LEN2_8723D(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value) -#define SET_EARLYMODE_LEN3_8723D(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value) - - -/*-----------------------------------------------------------------*/ -/* RTL8723D TX BUFFER DESC */ -/*-----------------------------------------------------------------*/ -#ifdef CONFIG_64BIT_DMA - #define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu) - #define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu) - #define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu) - #define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu) -#else - #define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu) - #define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu) - #define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu) - #define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) /* 64 BIT mode only */ -#endif -/* ********************************************************* */ - -/* 64 bits -- 32 bits */ -/* ======= ======= */ -/* Dword 0 0 */ -#define SET_TX_BUFF_DESC_LEN_0_8723D(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu) -#define SET_TX_BUFF_DESC_PSB_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value) -#define SET_TX_BUFF_DESC_OWN_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) - -/* Dword 1 1 */ -#define SET_TX_BUFF_DESC_ADDR_LOW_0_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value) -#define GET_TX_BUFF_DESC_ADDR_LOW_0_8723D(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32) -/* Dword 2 NA */ -#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 0, __Value) -#ifdef CONFIG_64BIT_DMA - #define GET_TX_BUFF_DESC_ADDR_HIGH_0_8723D(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32) -#else - #define GET_TX_BUFF_DESC_ADDR_HIGH_0_8723D(__pTxDesc) 0 -#endif -/* Dword 3 NA */ -/* RESERVED 0 */ -/* Dword 4 2 */ -#define SET_TX_BUFF_DESC_LEN_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 1, __Value) -#define SET_TX_BUFF_DESC_AMSDU_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 1, __Value) -/* Dword 5 3 */ -#define SET_TX_BUFF_DESC_ADDR_LOW_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 1, __Value) -/* Dword 6 NA */ -#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 1, __Value) -/* Dword 7 NA */ -/*RESERVED 0 */ -/* Dword 8 4 */ -#define SET_TX_BUFF_DESC_LEN_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 2, __Value) -#define SET_TX_BUFF_DESC_AMSDU_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 2, __Value) -/* Dword 9 5 */ -#define SET_TX_BUFF_DESC_ADDR_LOW_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 2, __Value) -/* Dword 10 NA */ -#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 2, __Value) -/* Dword 11 NA */ -/*RESERVED 0 */ -/* Dword 12 6 */ -#define SET_TX_BUFF_DESC_LEN_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 3, __Value) -#define SET_TX_BUFF_DESC_AMSDU_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 3, __Value) -/* Dword 13 7 */ -#define SET_TX_BUFF_DESC_ADDR_LOW_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 3, __Value) -/* Dword 14 NA */ -#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 3, __Value) -/* Dword 15 NA */ -/*RESERVED 0 */ - - -#endif -/* ----------------------------------------------------------- - * - * Rate - * - * ----------------------------------------------------------- - * CCK Rates, TxHT = 0 */ -#define DESC8723D_RATE1M 0x00 -#define DESC8723D_RATE2M 0x01 -#define DESC8723D_RATE5_5M 0x02 -#define DESC8723D_RATE11M 0x03 - -/* OFDM Rates, TxHT = 0 */ -#define DESC8723D_RATE6M 0x04 -#define DESC8723D_RATE9M 0x05 -#define DESC8723D_RATE12M 0x06 -#define DESC8723D_RATE18M 0x07 -#define DESC8723D_RATE24M 0x08 -#define DESC8723D_RATE36M 0x09 -#define DESC8723D_RATE48M 0x0a -#define DESC8723D_RATE54M 0x0b - -/* MCS Rates, TxHT = 1 */ -#define DESC8723D_RATEMCS0 0x0c -#define DESC8723D_RATEMCS1 0x0d -#define DESC8723D_RATEMCS2 0x0e -#define DESC8723D_RATEMCS3 0x0f -#define DESC8723D_RATEMCS4 0x10 -#define DESC8723D_RATEMCS5 0x11 -#define DESC8723D_RATEMCS6 0x12 -#define DESC8723D_RATEMCS7 0x13 -#define DESC8723D_RATEMCS8 0x14 -#define DESC8723D_RATEMCS9 0x15 -#define DESC8723D_RATEMCS10 0x16 -#define DESC8723D_RATEMCS11 0x17 -#define DESC8723D_RATEMCS12 0x18 -#define DESC8723D_RATEMCS13 0x19 -#define DESC8723D_RATEMCS14 0x1a -#define DESC8723D_RATEMCS15 0x1b -#define DESC8723D_RATEVHTSS1MCS0 0x2c -#define DESC8723D_RATEVHTSS1MCS1 0x2d -#define DESC8723D_RATEVHTSS1MCS2 0x2e -#define DESC8723D_RATEVHTSS1MCS3 0x2f -#define DESC8723D_RATEVHTSS1MCS4 0x30 -#define DESC8723D_RATEVHTSS1MCS5 0x31 -#define DESC8723D_RATEVHTSS1MCS6 0x32 -#define DESC8723D_RATEVHTSS1MCS7 0x33 -#define DESC8723D_RATEVHTSS1MCS8 0x34 -#define DESC8723D_RATEVHTSS1MCS9 0x35 -#define DESC8723D_RATEVHTSS2MCS0 0x36 -#define DESC8723D_RATEVHTSS2MCS1 0x37 -#define DESC8723D_RATEVHTSS2MCS2 0x38 -#define DESC8723D_RATEVHTSS2MCS3 0x39 -#define DESC8723D_RATEVHTSS2MCS4 0x3a -#define DESC8723D_RATEVHTSS2MCS5 0x3b -#define DESC8723D_RATEVHTSS2MCS6 0x3c -#define DESC8723D_RATEVHTSS2MCS7 0x3d -#define DESC8723D_RATEVHTSS2MCS8 0x3e -#define DESC8723D_RATEVHTSS2MCS9 0x3f - - -#define RX_HAL_IS_CCK_RATE_8723D(pDesc)\ - (GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE1M || \ - GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE2M || \ - GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE5_5M || \ - GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE11M) - -#ifdef CONFIG_TRX_BD_ARCH - struct tx_desc; -#endif - -void rtl8723d_cal_txdesc_chksum(struct tx_desc *ptxdesc); -void rtl8723d_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem); -void rtl8723d_fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc); -void rtl8723d_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc); -void rtl8723d_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc); -void rtl8723d_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); - -#if defined(CONFIG_CONCURRENT_MODE) - void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); -#endif - -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - s32 rtl8723ds_init_xmit_priv(PADAPTER padapter); - void rtl8723ds_free_xmit_priv(PADAPTER padapter); - s32 rtl8723ds_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 rtl8723ds_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); - s32 rtl8723ds_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); - s32 rtl8723ds_xmit_buf_handler(PADAPTER padapter); - thread_return rtl8723ds_xmit_thread(thread_context context); - #define hal_xmit_handler rtl8723ds_xmit_buf_handler -#endif - -#ifdef CONFIG_USB_HCI - s32 rtl8723du_xmit_buf_handler(PADAPTER padapter); - #define hal_xmit_handler rtl8723du_xmit_buf_handler - s32 rtl8723du_init_xmit_priv(PADAPTER padapter); - void rtl8723du_free_xmit_priv(PADAPTER padapter); - s32 rtl8723du_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 rtl8723du_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); - s32 rtl8723du_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); - void rtl8723du_xmit_tasklet(void *priv); - s32 rtl8723du_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); - void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, struct tx_desc *ptxdesc); -#endif - -#ifdef CONFIG_PCI_HCI - s32 rtl8723de_init_xmit_priv(PADAPTER padapter); - void rtl8723de_free_xmit_priv(PADAPTER padapter); - struct xmit_buf *rtl8723de_dequeue_xmitbuf(struct rtw_tx_ring *ring); - void rtl8723de_xmitframe_resume(_adapter *padapter); - s32 rtl8723de_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 rtl8723de_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); - s32 rtl8723de_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); - void rtl8723de_xmit_tasklet(void *priv); -#endif - -u8 BWMapping_8723D(PADAPTER Adapter, struct pkt_attrib *pattrib); -u8 SCMapping_8723D(PADAPTER Adapter, struct pkt_attrib *pattrib); - -#endif diff --git a/include/rtl8812a_cmd.h b/include/rtl8812a_cmd.h deleted file mode 100644 index 3891bd0..0000000 --- a/include/rtl8812a_cmd.h +++ /dev/null @@ -1,171 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8812A_CMD_H__ -#define __RTL8812A_CMD_H__ - -typedef enum _RTL8812_H2C_CMD { - H2C_8812_RSVDPAGE = 0, - H2C_8812_MSRRPT = 1, - H2C_8812_SCAN = 2, - H2C_8812_KEEP_ALIVE_CTRL = 3, - H2C_8812_DISCONNECT_DECISION = 4, - - H2C_8812_INIT_OFFLOAD = 6, - H2C_8812_AP_OFFLOAD = 8, - H2C_8812_BCN_RSVDPAGE = 9, - H2C_8812_PROBERSP_RSVDPAGE = 10, - - H2C_8812_SETPWRMODE = 0x20, - H2C_8812_PS_TUNING_PARA = 0x21, - H2C_8812_PS_TUNING_PARA2 = 0x22, - H2C_8812_PS_LPS_PARA = 0x23, - H2C_8812_P2P_PS_OFFLOAD = 0x24, - H2C_8812_INACTIVE_PS = 0x27, - H2C_8812_RA_MASK = 0x40, - H2C_8812_TxBF = 0x41, - H2C_8812_RSSI_REPORT = 0x42, - H2C_8812_IQ_CALIBRATION = 0x45, - H2C_8812_RA_PARA_ADJUST = 0x46, - - H2C_8812_BT_FW_PATCH = 0x6a, - - H2C_8812_WO_WLAN = 0x80, - H2C_8812_REMOTE_WAKE_CTRL = 0x81, - H2C_8812_AOAC_GLOBAL_INFO = 0x82, - H2C_8812_AOAC_RSVDPAGE = 0x83, - H2C_8812_FW_SWCHANNL = 0x87, - - H2C_8812_TSF_RESET = 0xC0, - - MAX_8812_H2CCMD -} RTL8812_H2C_CMD; - -struct cmd_msg_parm { - u8 eid; /* element id */ - u8 sz; /* sz */ - u8 buf[6]; -}; - -enum { - PWRS -}; - -struct H2C_SS_RFOFF_PARAM { - u8 ROFOn; /* 1: on, 0:off */ - u16 gpio_period; /* unit: 1024 us */ -} __attribute__((packed)); - - - -/* _RSVDPAGE_LOC_CMD0 */ -#define SET_8812_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8812_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) -#define SET_8812_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) -#define SET_8812_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) -#define SET_8812_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) - -/* _SETPWRMODE_PARM */ -#define SET_8812_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8812_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value) -#define SET_8812_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value) -#define SET_8812_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) -#define SET_8812_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) -#define SET_8812_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value) -#define SET_8812_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) -#define SET_8812_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) - -#define GET_8812_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8) - -/* _P2P_PS_OFFLOAD */ -#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) -#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) -#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_CTWINDOW_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) -#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_NOA0_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value) -#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_NOA1_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value) -#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value) -#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value) - - -void set_ra_ldpc_8812(struct sta_info *psta, BOOLEAN bLDPC); - -/* host message to firmware cmd */ -s32 fill_h2c_cmd_8812(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); -void rtl8812_set_FwPwrMode_cmd(PADAPTER padapter, u8 PSMode); -void rtl8812_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus); -u8 rtl8812_set_rssi_cmd(PADAPTER padapter, u8 *param); -void rtl8812_set_raid_cmd(PADAPTER padapter, u32 bitmap, u8 *arg, u8 bw); -void rtl8812_set_wowlan_cmd(_adapter *padapter, u8 enable); -u8 GetTxBufferRsvdPageNum8812(_adapter *padapter, bool wowlan); - -#ifdef CONFIG_BT_COEXIST -void rtl8812a_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter); -#endif /* CONFIG_BT_COEXIST */ -#ifdef CONFIG_P2P_PS -void rtl8812_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); -#endif /* CONFIG_P2P */ - -#ifdef CONFIG_FWLPS_IN_IPS -void rtl8812_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param); -#endif - -void CheckFwRsvdPageContent(PADAPTER padapter); - -#ifdef CONFIG_TDLS -#ifdef CONFIG_TDLS_CH_SW -void rtl8812_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); -#endif -#endif - -#ifdef CONFIG_TSF_RESET_OFFLOAD -int reset_tsf(PADAPTER Adapter, u8 reset_port); -#endif /* CONFIG_TSF_RESET_OFFLOAD */ - -/* ------------------------------------ - * C2H format - * ------------------------------------ */ - -/* TX Beamforming */ -#define GET_8812_C2H_TXBF_ORIGINATE(_Header) LE_BITS_TO_1BYTE(_Header, 0, 8) -#define GET_8812_C2H_TXBF_MACID(_Header) LE_BITS_TO_1BYTE((_Header + 1), 0, 8) - - - -/* / TX Feedback Content */ -#define USEC_UNIT_FOR_8812_C2H_TX_RPT_QUEUE_TIME 256 - -#define GET_8812_C2H_TX_RPT_QUEUE_SELECT(_Header) LE_BITS_TO_1BYTE((_Header + 0), 0, 5) -#define GET_8812_C2H_TX_RPT_PKT_BROCAST(_Header) LE_BITS_TO_1BYTE((_Header + 0), 5, 1) -#define GET_8812_C2H_TX_RPT_LIFE_TIME_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 6, 1) -#define GET_8812_C2H_TX_RPT_RETRY_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 7, 1) -#define GET_8812_C2H_TX_RPT_MAC_ID(_Header) LE_BITS_TO_1BYTE((_Header + 1), 0, 8) -#define GET_8812_C2H_TX_RPT_DATA_RETRY_CNT(_Header) LE_BITS_TO_1BYTE((_Header + 2), 0, 6) -#define GET_8812_C2H_TX_RPT_QUEUE_TIME(_Header) LE_BITS_TO_2BYTE((_Header + 3), 0, 16) /* In unit of 256 microseconds. */ -#define GET_8812_C2H_TX_RPT_FINAL_DATA_RATE(_Header) LE_BITS_TO_1BYTE((_Header + 5), 0, 8) - -/* BT_FW_PATCH */ -#define SET_8812_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value) -#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((pu1Byte)(__pH2CCmd)+2, 0, 8, __Value) -#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((pu1Byte)(__pH2CCmd)+3, 0, 8, __Value) -#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((pu1Byte)(__pH2CCmd)+4, 0, 8, __Value) -#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((pu1Byte)(__pH2CCmd)+5, 0, 8, __Value) - -s32 c2h_handler_8812a(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload); - -#endif/* __RTL8812A_CMD_H__ */ diff --git a/include/rtl8812a_dm.h b/include/rtl8812a_dm.h deleted file mode 100644 index fef5824..0000000 --- a/include/rtl8812a_dm.h +++ /dev/null @@ -1,32 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8812A_DM_H__ -#define __RTL8812A_DM_H__ - -void rtl8812_init_dm_priv(IN PADAPTER Adapter); -void rtl8812_deinit_dm_priv(IN PADAPTER Adapter); -void rtl8812_InitHalDm(IN PADAPTER Adapter); -void rtl8812_HalDmWatchDog(IN PADAPTER Adapter); - -/* VOID rtl8192c_dm_CheckTXPowerTracking(IN PADAPTER Adapter); */ - -/* void rtl8192c_dm_RF_Saving(IN PADAPTER pAdapter, IN u8 bForceInNormal); */ - -#endif diff --git a/include/rtl8812a_hal.h b/include/rtl8812a_hal.h deleted file mode 100644 index 2ea4c83..0000000 --- a/include/rtl8812a_hal.h +++ /dev/null @@ -1,361 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8812A_HAL_H__ -#define __RTL8812A_HAL_H__ - -/* #include "hal_com.h" */ -#include "hal_data.h" - -/* include HAL Related header after HAL Related compiling flags */ -#include "rtl8812a_spec.h" -#include "rtl8812a_rf.h" -#include "rtl8812a_dm.h" -#include "rtl8812a_recv.h" -#include "rtl8812a_xmit.h" -#include "rtl8812a_cmd.h" -#include "rtl8812a_led.h" -#include "Hal8812PwrSeq.h" -#include "Hal8821APwrSeq.h" /* for 8821A/8811A */ -#include "Hal8812PhyReg.h" -#include "Hal8812PhyCfg.h" -#ifdef DBG_CONFIG_ERROR_DETECT -#include "rtl8812a_sreset.h" -#endif - -/* --------------------------------------------------------------------- - * RTL8812 Power Configuration CMDs for PCIe interface - * --------------------------------------------------------------------- */ -#define Rtl8812_NIC_PWR_ON_FLOW rtl8812_power_on_flow -#define Rtl8812_NIC_RF_OFF_FLOW rtl8812_radio_off_flow -#define Rtl8812_NIC_DISABLE_FLOW rtl8812_card_disable_flow -#define Rtl8812_NIC_ENABLE_FLOW rtl8812_card_enable_flow -#define Rtl8812_NIC_SUSPEND_FLOW rtl8812_suspend_flow -#define Rtl8812_NIC_RESUME_FLOW rtl8812_resume_flow -#define Rtl8812_NIC_PDN_FLOW rtl8812_hwpdn_flow -#define Rtl8812_NIC_LPS_ENTER_FLOW rtl8812_enter_lps_flow -#define Rtl8812_NIC_LPS_LEAVE_FLOW rtl8812_leave_lps_flow - -/* --------------------------------------------------------------------- - * RTL8821 Power Configuration CMDs for PCIe interface - * --------------------------------------------------------------------- */ -#define Rtl8821A_NIC_PWR_ON_FLOW rtl8821A_power_on_flow -#define Rtl8821A_NIC_RF_OFF_FLOW rtl8821A_radio_off_flow -#define Rtl8821A_NIC_DISABLE_FLOW rtl8821A_card_disable_flow -#define Rtl8821A_NIC_ENABLE_FLOW rtl8821A_card_enable_flow -#define Rtl8821A_NIC_SUSPEND_FLOW rtl8821A_suspend_flow -#define Rtl8821A_NIC_RESUME_FLOW rtl8821A_resume_flow -#define Rtl8821A_NIC_PDN_FLOW rtl8821A_hwpdn_flow -#define Rtl8821A_NIC_LPS_ENTER_FLOW rtl8821A_enter_lps_flow -#define Rtl8821A_NIC_LPS_LEAVE_FLOW rtl8821A_leave_lps_flow - - -#if 1 /* download firmware related data structure */ -#define FW_SIZE_8812 0x8000 /* Compatible with RTL8723 Maximal RAM code size 24K. modified to 32k, TO compatible with 92d maximal fw size 32k */ -#define FW_START_ADDRESS 0x1000 -#define FW_END_ADDRESS 0x5FFF - - - -typedef struct _RT_FIRMWARE_8812 { - FIRMWARE_SOURCE eFWSource; -#ifdef CONFIG_EMBEDDED_FWIMG - u8 *szFwBuffer; -#else - u8 szFwBuffer[FW_SIZE_8812]; -#endif - u32 ulFwLength; -} RT_FIRMWARE_8812, *PRT_FIRMWARE_8812; - -/* - * This structure must be cared byte-ordering - * - * Added by tynli. 2009.12.04. */ -#define IS_FW_HEADER_EXIST_8812(_pFwHdr) ((GET_FIRMWARE_HDR_SIGNATURE_8812(_pFwHdr) & 0xFFF0) == 0x9500) - -#define IS_FW_HEADER_EXIST_8821(_pFwHdr) ((GET_FIRMWARE_HDR_SIGNATURE_8812(_pFwHdr) & 0xFFF0) == 0x2100) -/* ***************************************************** - * Firmware Header(8-byte alinment required) - * ***************************************************** - * --- LONG WORD 0 ---- */ -#define GET_FIRMWARE_HDR_SIGNATURE_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 0, 16) /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */ -#define GET_FIRMWARE_HDR_CATEGORY_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 16, 8) /* AP/NIC and USB/PCI */ -#define GET_FIRMWARE_HDR_FUNCTION_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 24, 8) /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */ -#define GET_FIRMWARE_HDR_VERSION_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 0, 16)/* FW Version */ -#define GET_FIRMWARE_HDR_SUB_VER_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 16, 8) /* FW Subversion, default 0x00 */ -#define GET_FIRMWARE_HDR_RSVD1_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 24, 8) - -/* --- LONG WORD 1 ---- */ -#define GET_FIRMWARE_HDR_MONTH_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 0, 8) /* Release time Month field */ -#define GET_FIRMWARE_HDR_DATE_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 8, 8) /* Release time Date field */ -#define GET_FIRMWARE_HDR_HOUR_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 16, 8)/* Release time Hour field */ -#define GET_FIRMWARE_HDR_MINUTE_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 24, 8)/* Release time Minute field */ -#define GET_FIRMWARE_HDR_ROMCODE_SIZE_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+12, 0, 16)/* The size of RAM code */ -#define GET_FIRMWARE_HDR_RSVD2_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+12, 16, 16) - -/* --- LONG WORD 2 ---- */ -#define GET_FIRMWARE_HDR_SVN_IDX_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+16, 0, 32)/* The SVN entry index */ -#define GET_FIRMWARE_HDR_RSVD3_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+20, 0, 32) - -/* --- LONG WORD 3 ---- */ -#define GET_FIRMWARE_HDR_RSVD4_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 0, 32) -#define GET_FIRMWARE_HDR_RSVD5_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+28, 0, 32) - -#endif /* download firmware related data structure */ - - -#define DRIVER_EARLY_INT_TIME_8812 0x05 -#define BCN_DMA_ATIME_INT_TIME_8812 0x02 - -/* for 8812 - * TX 128K, RX 16K, Page size 512B for TX, 128B for RX */ -#define MAX_RX_DMA_BUFFER_SIZE_8812 0x3E80 /* RX 16K */ - -#ifdef CONFIG_WOWLAN - #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/ -#else - #define RESV_FMWF 0 -#endif - -#ifdef CONFIG_FW_C2H_DEBUG - #define RX_DMA_RESERVED_SIZE_8812 0x100 /* 256B, reserved for c2h debug message */ -#else - #define RX_DMA_RESERVED_SIZE_8812 0x0 /* 0B */ -#endif -#define RX_DMA_BOUNDARY_8812 (MAX_RX_DMA_BUFFER_SIZE_8812 - RX_DMA_RESERVED_SIZE_8812 - 1) - -#define BCNQ_PAGE_NUM_8812 0x07 - -/* For WoWLan , more reserved page - * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:1,GTK EXT MEM:1, AOAC rpt: 1,PNO: 6 */ -#ifdef CONFIG_WOWLAN - #define WOWLAN_PAGE_NUM_8812 0x06 -#else - #define WOWLAN_PAGE_NUM_8812 0x00 -#endif - - -#ifdef CONFIG_BEAMFORMER_FW_NDPA - #define FW_NDPA_PAGE_NUM 0x02 -#else - #define FW_NDPA_PAGE_NUM 0x00 -#endif - -#define TX_TOTAL_PAGE_NUMBER_8812 (0xFF - BCNQ_PAGE_NUM_8812 - WOWLAN_PAGE_NUM_8812-FW_NDPA_PAGE_NUM) -#define TX_PAGE_BOUNDARY_8812 (TX_TOTAL_PAGE_NUMBER_8812 + 1) - -#define TX_PAGE_BOUNDARY_WOWLAN_8812 (0xFF - BCNQ_PAGE_NUM_8812 - WOWLAN_PAGE_NUM_8812 + 1) - -#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8812 TX_TOTAL_PAGE_NUMBER_8812 -#define WMM_NORMAL_TX_PAGE_BOUNDARY_8812 (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8812 + 1) - -/* For Normal Chip Setting - * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8812 */ -#define NORMAL_PAGE_NUM_LPQ_8812 0x10 -#define NORMAL_PAGE_NUM_HPQ_8812 0x10 -#define NORMAL_PAGE_NUM_NPQ_8812 0x00 - -#define WMM_NORMAL_PAGE_NUM_HPQ_8812 0x30 -#define WMM_NORMAL_PAGE_NUM_LPQ_8812 0x20 -#define WMM_NORMAL_PAGE_NUM_NPQ_8812 0x20 - - -/* for 8821A - * TX 64K, RX 16K, Page size 256B for TX, 128B for RX */ -#define PAGE_SIZE_TX_8821A 256 -#define PAGE_SIZE_RX_8821A 128 - -#define MAX_RX_DMA_BUFFER_SIZE_8821 0x3E80 /* RX 16K */ - -#ifdef CONFIG_FW_C2H_DEBUG - #define RX_DMA_RESERVED_SIZE_8821 0x100 /* 256B, reserved for c2h debug message */ -#else - #define RX_DMA_RESERVED_SIZE_8821 0x0 /* 0B */ -#endif -#define RX_DMA_BOUNDARY_8821 (MAX_RX_DMA_BUFFER_SIZE_8821 - RX_DMA_RESERVED_SIZE_8821 - 1) - -#define BCNQ_PAGE_NUM_8821 0x08 -#ifdef CONFIG_CONCURRENT_MODE - #define BCNQ1_PAGE_NUM_8821 0x04 -#else - #define BCNQ1_PAGE_NUM_8821 0x00 -#endif - -/* For WoWLan , more reserved page - * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:1,GTK EXT MEM:1, PNO: 6 */ -#ifdef CONFIG_WOWLAN - #define WOWLAN_PAGE_NUM_8821 0x06 -#else - #define WOWLAN_PAGE_NUM_8821 0x00 -#endif - -#define TX_TOTAL_PAGE_NUMBER_8821 (0xFF - BCNQ_PAGE_NUM_8821 - BCNQ1_PAGE_NUM_8821 - WOWLAN_PAGE_NUM_8821) -#define TX_PAGE_BOUNDARY_8821 (TX_TOTAL_PAGE_NUMBER_8821 + 1) -/* #define TX_PAGE_BOUNDARY_WOWLAN_8821 0xE0 */ - -#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8821 TX_TOTAL_PAGE_NUMBER_8821 -#define WMM_NORMAL_TX_PAGE_BOUNDARY_8821 (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8821 + 1) - - -/* (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER */ -#define NORMAL_PAGE_NUM_LPQ_8821 0x08/* 0x10 */ -#define NORMAL_PAGE_NUM_HPQ_8821 0x08/* 0x10 */ -#define NORMAL_PAGE_NUM_NPQ_8821 0x00 - -#define WMM_NORMAL_PAGE_NUM_HPQ_8821 0x30 -#define WMM_NORMAL_PAGE_NUM_LPQ_8821 0x20 -#define WMM_NORMAL_PAGE_NUM_NPQ_8821 0x20 - -#define MCC_NORMAL_PAGE_NUM_HPQ_8821 0x10 -#define MCC_NORMAL_PAGE_NUM_LPQ_8821 0x10 -#define MCC_NORMAL_PAGE_NUM_NPQ_8821 0x10 - -#define EFUSE_HIDDEN_812AU 0 -#define EFUSE_HIDDEN_812AU_VS 1 -#define EFUSE_HIDDEN_812AU_VL 2 -#define EFUSE_HIDDEN_812AU_VN 3 - -#if 0 -#define EFUSE_REAL_CONTENT_LEN_JAGUAR 1024 -#define HWSET_MAX_SIZE_JAGUAR 1024 -#else -#define EFUSE_REAL_CONTENT_LEN_JAGUAR 512 -#define HWSET_MAX_SIZE_JAGUAR 512 -#endif - -#define EFUSE_MAX_BANK_8812A 2 -#define EFUSE_MAP_LEN_JAGUAR 512 -#define EFUSE_MAX_SECTION_JAGUAR 64 -#define EFUSE_MAX_WORD_UNIT_JAGUAR 4 -#define EFUSE_IC_ID_OFFSET_JAGUAR 506 /* For some inferiority IC purpose. added by Roger, 2009.09.02. */ -#define AVAILABLE_EFUSE_ADDR_8812(addr) (addr < EFUSE_REAL_CONTENT_LEN_JAGUAR) -/* To prevent out of boundary programming case, leave 1byte and program full section - * 9bytes + 1byt + 5bytes and pre 1byte. - * For worst case: - * | 2byte|----8bytes----|1byte|--7bytes--| */ /* 92D */ -#define EFUSE_OOB_PROTECT_BYTES_JAGUAR 18 /* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */ -#define EFUSE_PROTECT_BYTES_BANK_JAGUAR 16 - -#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT) -#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) - -/* #define IS_MULTI_FUNC_CHIP(_Adapter) (((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) */ - -/* #define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) */ -#define HAL_EFUSE_MEMORY - -/* ******************************************************** - * EFUSE for BT definition - * ******************************************************** */ -#define BANK_NUM 2 -#define EFUSE_BT_REAL_BANK_CONTENT_LEN 512 -#define EFUSE_BT_REAL_CONTENT_LEN \ - (EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM) -#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */ -#define EFUSE_BT_MAX_SECTION (EFUSE_BT_MAP_LEN / 8) -#define EFUSE_PROTECT_BYTES_BANK 16 - -#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_BT_REAL_CONTENT_LEN) - -#ifdef CONFIG_FILE_FWIMG -extern char *rtw_fw_file_path; -#ifdef CONFIG_WOWLAN -extern char *rtw_fw_wow_file_path; -#endif -#ifdef CONFIG_MP_INCLUDED -extern char *rtw_fw_mp_bt_file_path; -#endif -#endif - - -/* rtl8812_hal_init.c */ -void _8051Reset8812(PADAPTER padapter); -s32 FirmwareDownload8812(PADAPTER Adapter, BOOLEAN bUsedWoWLANFw); -void InitializeFirmwareVars8812(PADAPTER padapter); - -s32 _LLTWrite_8812A(PADAPTER Adapter, u32 address, u32 data); -s32 InitLLTTable8812A(PADAPTER padapter, u8 txpktbuf_bndy); -void InitRDGSetting8812A(PADAPTER padapter); - -void CheckAutoloadState8812A(PADAPTER padapter); - -/* EFuse */ -u8 GetEEPROMSize8812A(PADAPTER padapter); -void InitPGData8812A(PADAPTER padapter); -void Hal_EfuseParseIDCode8812A(PADAPTER padapter, u8 *hwinfo); -void Hal_ReadPROMVersion8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_ReadTxPowerInfo8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_ReadBoardType8812A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_ReadThermalMeter_8812A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); -void Hal_ReadChannelPlan8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParseXtal_8812A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_ReadAntennaDiversity8812A(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail); -void Hal_ReadAmplifierType_8812A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); -void Hal_ReadPAType_8821A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); -void Hal_ReadRFEType_8812A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); -void Hal_EfuseParseBTCoexistInfo8812A(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void hal_ReadUsbType_8812AU(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); -#ifdef CONFIG_MP_INCLUDED -int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware); -#endif -void Hal_ReadRemoteWakeup_8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); - -BOOLEAN HalDetectPwrDownMode8812(PADAPTER Adapter); -void Hal_EfuseParseKFreeData_8821A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); - -#ifdef CONFIG_WOWLAN -void Hal_DetectWoWMode(PADAPTER pAdapter); -#endif /* CONFIG_WOWLAN */ - -void _InitBeaconParameters_8812A(PADAPTER padapter); -void SetBeaconRelatedRegisters8812A(PADAPTER padapter); - -void ReadRFType8812A(PADAPTER padapter); -void InitDefaultValue8821A(PADAPTER padapter); - -void SetHwReg8812A(PADAPTER padapter, u8 variable, u8 *pval); -void GetHwReg8812A(PADAPTER padapter, u8 variable, u8 *pval); -u8 SetHalDefVar8812A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); -u8 GetHalDefVar8812A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); -void rtl8812_set_hal_ops(struct hal_ops *pHalFunc); -void init_hal_spec_8812a(_adapter *adapter); -void init_hal_spec_8821a(_adapter *adapter); - -/* register */ -void SetBcnCtrlReg(PADAPTER padapter, u8 SetBits, u8 ClearBits); - -void rtl8812_start_thread(PADAPTER padapter); -void rtl8812_stop_thread(PADAPTER padapter); - -#ifdef CONFIG_PCI_HCI -BOOLEAN InterruptRecognized8812AE(PADAPTER Adapter); -VOID UpdateInterruptMask8812AE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1); -#endif - -#ifdef CONFIG_BT_COEXIST -void rtl8812a_combo_card_WifiOnlyHwInit(PADAPTER Adapter); -#endif - -VOID -Hal_PatchwithJaguar_8812( - IN PADAPTER Adapter, - IN RT_MEDIA_STATUS MediaStatus -); - -#endif /* __RTL8188E_HAL_H__ */ diff --git a/include/rtl8812a_led.h b/include/rtl8812a_led.h deleted file mode 100644 index 28840be..0000000 --- a/include/rtl8812a_led.h +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8812A_LED_H__ -#define __RTL8812A_LED_H__ - - -/* ******************************************************************************** - * Interface to manipulate LED objects. - * ******************************************************************************** */ -#ifdef CONFIG_USB_HCI -void rtl8812au_InitSwLeds(PADAPTER padapter); -void rtl8812au_DeInitSwLeds(PADAPTER padapter); -#endif -#ifdef CONFIG_PCI_HCI -void rtl8812ae_InitSwLeds(PADAPTER padapter); -void rtl8812ae_DeInitSwLeds(PADAPTER padapter); -#endif -#ifdef CONFIG_SDIO_HCI -void rtl8821as_hw_led_config(PADAPTER adapter); -void rtl8821as_InitSwLeds(PADAPTER padapter); -void rtl8821as_DeInitSwLeds(PADAPTER padapter); -#endif - -#endif diff --git a/include/rtl8812a_recv.h b/include/rtl8812a_recv.h deleted file mode 100644 index 0c5ca00..0000000 --- a/include/rtl8812a_recv.h +++ /dev/null @@ -1,154 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8812A_RECV_H__ -#define __RTL8812A_RECV_H__ - -#if defined(CONFIG_USB_HCI) - - #ifndef MAX_RECVBUF_SZ - #ifndef CONFIG_MINIMAL_MEMORY_USAGE - #ifdef CONFIG_PREALLOC_RX_SKB_BUFFER - #define MAX_RECVBUF_SZ (rtw_rtkm_get_buff_size()) /*depend rtkm*/ - #else - #define MAX_RECVBUF_SZ (32768) /*32k*/ - #endif - /* #define MAX_RECVBUF_SZ (24576) */ /* 24k */ - /* #define MAX_RECVBUF_SZ (20480) */ /* 20K */ - /* #define MAX_RECVBUF_SZ (10240) */ /* 10K */ - /* #define MAX_RECVBUF_SZ (15360) */ /* 15k < 16k */ - /* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */ - #ifdef CONFIG_PLATFORM_NOVATEK_NT72668 - #undef MAX_RECVBUF_SZ - #define MAX_RECVBUF_SZ (15360) /* 15k < 16k */ - #endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */ - #else - #define MAX_RECVBUF_SZ (4000) /* about 4K */ - #endif - #endif /* !MAX_RECVBUF_SZ */ - -#elif defined(CONFIG_PCI_HCI) - /* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */ - /* #define MAX_RECVBUF_SZ (9100) */ - /* #else */ - #define MAX_RECVBUF_SZ (4000) /* about 4K - * #endif */ - - -#elif defined(CONFIG_SDIO_HCI) - - #define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8821 + 1) - -#endif - - -/* Rx smooth factor */ -#define Rx_Smooth_Factor (20) - -/* DWORD 0 */ -#define SET_RX_STATUS_DESC_PKT_LEN_8812(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value) -#define SET_RX_STATUS_DESC_EOR_8812(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value) -#define SET_RX_STATUS_DESC_OWN_8812(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value) - -#define GET_RX_STATUS_DESC_PKT_LEN_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14) -#define GET_RX_STATUS_DESC_CRC32_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1) -#define GET_RX_STATUS_DESC_ICV_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1) -#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4) -#define GET_RX_STATUS_DESC_SECURITY_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3) -#define GET_RX_STATUS_DESC_QOS_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1) -#define GET_RX_STATUS_DESC_SHIFT_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2) -#define GET_RX_STATUS_DESC_PHY_STATUS_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1) -#define GET_RX_STATUS_DESC_SWDEC_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1) -#define GET_RX_STATUS_DESC_LAST_SEG_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1) -#define GET_RX_STATUS_DESC_FIRST_SEG_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1) -#define GET_RX_STATUS_DESC_EOR_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1) -#define GET_RX_STATUS_DESC_OWN_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1) - -/* DWORD 1 */ -#define GET_RX_STATUS_DESC_MACID_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7) -#define GET_RX_STATUS_DESC_TID_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4) -#define GET_RX_STATUS_DESC_AMSDU_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1) -#define GET_RX_STATUS_DESC_RXID_MATCH_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1) -#define GET_RX_STATUS_DESC_PAGGR_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1) -#define GET_RX_STATUS_DESC_A1_FIT_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4) -#define GET_RX_STATUS_DESC_CHKERR_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1) -#define GET_RX_STATUS_DESC_IPVER_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1) -#define GET_RX_STATUS_DESC_IS_TCPUDP__8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1) -#define GET_RX_STATUS_DESC_CHK_VLD_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1) -#define GET_RX_STATUS_DESC_PAM_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1) -#define GET_RX_STATUS_DESC_PWR_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1) -#define GET_RX_STATUS_DESC_MORE_DATA_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1) -#define GET_RX_STATUS_DESC_MORE_FRAG_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1) -#define GET_RX_STATUS_DESC_TYPE_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2) -#define GET_RX_STATUS_DESC_MC_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1) -#define GET_RX_STATUS_DESC_BC_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1) - -/* DWORD 2 */ -#define GET_RX_STATUS_DESC_SEQ_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12) -#define GET_RX_STATUS_DESC_FRAG_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4) -#define GET_RX_STATUS_DESC_RX_IS_QOS_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1) -#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6) -#define GET_RX_STATUS_DESC_RPT_SEL_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1) - -/* DWORD 3 */ -#define GET_RX_STATUS_DESC_RX_RATE_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7) -#define GET_RX_STATUS_DESC_HTC_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1) -#define GET_RX_STATUS_DESC_EOSP_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1) -#define GET_RX_STATUS_DESC_BSSID_FIT_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2) -#ifdef CONFIG_USB_RX_AGGREGATION -#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8) -#endif -#define GET_RX_STATUS_DESC_PATTERN_MATCH_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1) -#define GET_RX_STATUS_DESC_UNICAST_MATCH_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1) -#define GET_RX_STATUS_DESC_MAGIC_MATCH_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1) - -/* DWORD 6 */ -#define GET_RX_STATUS_DESC_SPLCP_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1) -#define GET_RX_STATUS_DESC_LDPC_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1) -#define GET_RX_STATUS_DESC_STBC_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1) -#define GET_RX_STATUS_DESC_BW_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2) - -/* DWORD 5 */ -#define GET_RX_STATUS_DESC_TSFL_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32) - -#define GET_RX_STATUS_DESC_BUFF_ADDR_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32) -#define GET_RX_STATUS_DESC_BUFF_ADDR64_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32) - -#define SET_RX_STATUS_DESC_BUFF_ADDR_8812(__pRxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value) - - -#ifdef CONFIG_SDIO_HCI -s32 InitRecvPriv8821AS(PADAPTER padapter); -void FreeRecvPriv8821AS(PADAPTER padapter); -#endif /* CONFIG_SDIO_HCI */ - -#ifdef CONFIG_USB_HCI -void rtl8812au_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf); -s32 rtl8812au_init_recv_priv(PADAPTER padapter); -void rtl8812au_free_recv_priv(PADAPTER padapter); -#endif - -#ifdef CONFIG_PCI_HCI -s32 rtl8812ae_init_recv_priv(PADAPTER padapter); -void rtl8812ae_free_recv_priv(PADAPTER padapter); -#endif - -void rtl8812_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc); - -#endif /* __RTL8812A_RECV_H__ */ diff --git a/include/rtl8812a_rf.h b/include/rtl8812a_rf.h deleted file mode 100644 index 9a7175d..0000000 --- a/include/rtl8812a_rf.h +++ /dev/null @@ -1,33 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8812A_RF_H__ -#define __RTL8812A_RF_H__ - -VOID -PHY_RF6052SetBandwidth8812( - IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth); - - -int -PHY_RF6052_Config_8812( - IN PADAPTER Adapter); - -#endif/* __RTL8188E_RF_H__ */ diff --git a/include/rtl8812a_spec.h b/include/rtl8812a_spec.h deleted file mode 100644 index d92e803..0000000 --- a/include/rtl8812a_spec.h +++ /dev/null @@ -1,264 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ -#ifndef __RTL8812A_SPEC_H__ -#define __RTL8812A_SPEC_H__ - -#include - - -/* ************************************************************ -* 8812 Regsiter offset definition -* ************************************************************ */ - -/* ************************************************************ -* -* ************************************************************ */ - -/* ----------------------------------------------------- -* -* 0x0000h ~ 0x00FFh System Configuration -* -* ----------------------------------------------------- */ -#define REG_SYS_CLKR_8812A 0x0008 -#define REG_AFE_PLL_CTRL_8812A 0x0028 -#define REG_HSIMR_8812 0x0058 -#define REG_HSISR_8812 0x005c -#define REG_GPIO_EXT_CTRL 0x0060 -#define REG_GPIO_STATUS_8812 0x006C -#define REG_SDIO_CTRL_8812 0x0070 -#define REG_OPT_CTRL_8812 0x0074 -#define REG_RF_B_CTRL_8812 0x0076 -#define REG_FW_DRV_MSG_8812 0x0088 -#define REG_HMEBOX_E2_E3_8812 0x008C -#define REG_HIMR0_8812 0x00B0 -#define REG_HISR0_8812 0x00B4 -#define REG_HIMR1_8812 0x00B8 -#define REG_HISR1_8812 0x00BC -#define REG_EFUSE_BURN_GNT_8812 0x00CF -#define REG_SYS_CFG1_8812 0x00FC - -/* ----------------------------------------------------- -* -* 0x0100h ~ 0x01FFh MACTOP General Configuration -* -* ----------------------------------------------------- */ -#define REG_CR_8812A 0x100 -#define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL) -#define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2) -#define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3) -#define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN - -#define REG_RSVD3_8812 0x0168 -#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 -#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 -#define REG_C2HEVT_CMD_LEN_88XX 0x01AE - -#define REG_HMEBOX_EXT0_8812 0x01F0 -#define REG_HMEBOX_EXT1_8812 0x01F4 -#define REG_HMEBOX_EXT2_8812 0x01F8 -#define REG_HMEBOX_EXT3_8812 0x01FC - -/* ----------------------------------------------------- -* -* 0x0200h ~ 0x027Fh TXDMA Configuration -* -* ----------------------------------------------------- */ -#define REG_DWBCN0_CTRL_8812 REG_TDECTRL -#define REG_DWBCN1_CTRL_8812 0x0228 - -/* ----------------------------------------------------- -* -* 0x0280h ~ 0x02FFh RXDMA Configuration -* -* ----------------------------------------------------- */ -#define REG_TDECTRL_8812A 0x0208 -#define REG_RXDMA_CONTROL_8812A 0x0286 /*Control the RX DMA.*/ -#define REG_RXDMA_PRO_8812 0x0290 -#define REG_EARLY_MODE_CONTROL_8812 0x02BC -#define REG_RSVD5_8812 0x02F0 -#define REG_RSVD6_8812 0x02F4 -#define REG_RSVD7_8812 0x02F8 -#define REG_RSVD8_8812 0x02FC - - -/* ----------------------------------------------------- -* -* 0x0300h ~ 0x03FFh PCIe -* -* ----------------------------------------------------- */ -#define REG_PCIE_CTRL_REG_8812A 0x0300 -#define REG_DBI_WDATA_8812 0x0348 /* DBI Write Data */ -#define REG_DBI_RDATA_8812 0x034C /* DBI Read Data */ -#define REG_DBI_ADDR_8812 0x0350 /* DBI Address */ -#define REG_DBI_FLAG_8812 0x0352 /* DBI Read/Write Flag */ -#define REG_MDIO_WDATA_8812 0x0354 /* MDIO for Write PCIE PHY */ -#define REG_MDIO_RDATA_8812 0x0356 /* MDIO for Reads PCIE PHY */ -#define REG_MDIO_CTL_8812 0x0358 /* MDIO for Control */ -#define REG_PCIE_MULTIFET_CTRL_8812 0x036A /* PCIE Multi-Fethc Control */ - -/* ----------------------------------------------------- -* -* 0x0400h ~ 0x047Fh Protocol Configuration -* -* ----------------------------------------------------- */ -#define REG_TXPKT_EMPTY_8812A 0x041A -#define REG_FWHW_TXQ_CTRL_8812A 0x0420 -#define REG_TXBF_CTRL_8812A 0x042C -#define REG_ARFR0_8812 0x0444 -#define REG_ARFR1_8812 0x044C -#define REG_CCK_CHECK_8812 0x0454 -#define REG_AMPDU_MAX_TIME_8812 0x0456 -#define REG_TXPKTBUF_BCNQ_BDNY1_8812 0x0457 - -#define REG_AMPDU_MAX_LENGTH_8812 0x0458 -#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8812 0x045D -#define REG_NDPA_OPT_CTRL_8812A 0x045F -#define REG_DATA_SC_8812 0x0483 -#ifdef CONFIG_WOWLAN -#define REG_TXPKTBUF_IV_LOW 0x0484 -#define REG_TXPKTBUF_IV_HIGH 0x0488 -#endif -#define REG_ARFR2_8812 0x048C -#define REG_ARFR3_8812 0x0494 -#define REG_TXRPT_START_OFFSET 0x04AC -#define REG_AMPDU_BURST_MODE_8812 0x04BC -#define REG_HT_SINGLE_AMPDU_8812 0x04C7 -#define REG_MACID_PKT_DROP0_8812 0x04D0 - -/* ----------------------------------------------------- -* -* 0x0500h ~ 0x05FFh EDCA Configuration -* -* ----------------------------------------------------- */ -#define REG_TXPAUSE_8812A 0x0522 -#define REG_CTWND_8812 0x0572 -#define REG_SECONDARY_CCA_CTRL_8812 0x0577 -#define REG_SCH_TXCMD_8812A 0x05F8 - -/* ----------------------------------------------------- -* -* 0x0600h ~ 0x07FFh WMAC Configuration -* -* ----------------------------------------------------- */ -#define REG_MAC_CR_8812 0x0600 - -#define REG_MAC_TX_SM_STATE_8812 0x06B4 - -/* Power */ -#define REG_BFMER0_INFO_8812A 0x06E4 -#define REG_BFMER1_INFO_8812A 0x06EC -#define REG_CSI_RPT_PARAM_BW20_8812A 0x06F4 -#define REG_CSI_RPT_PARAM_BW40_8812A 0x06F8 -#define REG_CSI_RPT_PARAM_BW80_8812A 0x06FC - -/* Hardware Port 2 */ -#define REG_BFMEE_SEL_8812A 0x0714 -#define REG_SND_PTCL_CTRL_8812A 0x0718 - - -/* ----------------------------------------------------- -* -* Redifine register definition for compatibility -* -* ----------------------------------------------------- */ - -/* TODO: use these definition when using REG_xxx naming rule. -* NOTE: DO NOT Remove these definition. Use later. */ -#define ISR_8812 REG_HISR0_8812 - -/* ---------------------------------------------------------------------------- -* 8195 IMR/ISR bits (offset 0xB0, 8bits) -* ---------------------------------------------------------------------------- */ -#define IMR_DISABLED_8812 0 -/* IMR DW0(0x00B0-00B3) Bit 0-31 */ -#define IMR_TIMER2_8812 BIT31 /* Timeout interrupt 2 */ -#define IMR_TIMER1_8812 BIT30 /* Timeout interrupt 1 */ -#define IMR_PSTIMEOUT_8812 BIT29 /* Power Save Time Out Interrupt */ -#define IMR_GTINT4_8812 BIT28 /* When GTIMER4 expires, this bit is set to 1 */ -#define IMR_GTINT3_8812 BIT27 /* When GTIMER3 expires, this bit is set to 1 */ -#define IMR_TXBCN0ERR_8812 BIT26 /* Transmit Beacon0 Error */ -#define IMR_TXBCN0OK_8812 BIT25 /* Transmit Beacon0 OK */ -#define IMR_TSF_BIT32_TOGGLE_8812 BIT24 /* TSF Timer BIT32 toggle indication interrupt */ -#define IMR_BCNDMAINT0_8812 BIT20 /* Beacon DMA Interrupt 0 */ -#define IMR_BCNDERR0_8812 BIT16 /* Beacon Queue DMA OK0 */ -#define IMR_HSISR_IND_ON_INT_8812 BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ -#define IMR_BCNDMAINT_E_8812 BIT14 /* Beacon DMA Interrupt Extension for Win7 */ -#define IMR_ATIMEND_8812 BIT12 /* CTWidnow End or ATIM Window End */ -#define IMR_C2HCMD_8812 BIT10 /* CPU to Host Command INT Status, Write 1 clear */ -#define IMR_CPWM2_8812 BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_CPWM_8812 BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_HIGHDOK_8812 BIT7 /* High Queue DMA OK */ -#define IMR_MGNTDOK_8812 BIT6 /* Management Queue DMA OK */ -#define IMR_BKDOK_8812 BIT5 /* AC_BK DMA OK */ -#define IMR_BEDOK_8812 BIT4 /* AC_BE DMA OK */ -#define IMR_VIDOK_8812 BIT3 /* AC_VI DMA OK */ -#define IMR_VODOK_8812 BIT2 /* AC_VO DMA OK */ -#define IMR_RDU_8812 BIT1 /* Rx Descriptor Unavailable */ -#define IMR_ROK_8812 BIT0 /* Receive DMA OK */ - -/* IMR DW1(0x00B4-00B7) Bit 0-31 */ -#define IMR_BCNDMAINT7_8812 BIT27 /* Beacon DMA Interrupt 7 */ -#define IMR_BCNDMAINT6_8812 BIT26 /* Beacon DMA Interrupt 6 */ -#define IMR_BCNDMAINT5_8812 BIT25 /* Beacon DMA Interrupt 5 */ -#define IMR_BCNDMAINT4_8812 BIT24 /* Beacon DMA Interrupt 4 */ -#define IMR_BCNDMAINT3_8812 BIT23 /* Beacon DMA Interrupt 3 */ -#define IMR_BCNDMAINT2_8812 BIT22 /* Beacon DMA Interrupt 2 */ -#define IMR_BCNDMAINT1_8812 BIT21 /* Beacon DMA Interrupt 1 */ -#define IMR_BCNDOK7_8812 BIT20 /* Beacon Queue DMA OK Interrup 7 */ -#define IMR_BCNDOK6_8812 BIT19 /* Beacon Queue DMA OK Interrup 6 */ -#define IMR_BCNDOK5_8812 BIT18 /* Beacon Queue DMA OK Interrup 5 */ -#define IMR_BCNDOK4_8812 BIT17 /* Beacon Queue DMA OK Interrup 4 */ -#define IMR_BCNDOK3_8812 BIT16 /* Beacon Queue DMA OK Interrup 3 */ -#define IMR_BCNDOK2_8812 BIT15 /* Beacon Queue DMA OK Interrup 2 */ -#define IMR_BCNDOK1_8812 BIT14 /* Beacon Queue DMA OK Interrup 1 */ -#define IMR_ATIMEND_E_8812 BIT13 /* ATIM Window End Extension for Win7 */ -#define IMR_TXERR_8812 BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ -#define IMR_RXERR_8812 BIT10 /* Rx Error Flag INT Status, Write 1 clear */ -#define IMR_TXFOVW_8812 BIT9 /* Transmit FIFO Overflow */ -#define IMR_RXFOVW_8812 BIT8 /* Receive FIFO Overflow */ - - -#ifdef CONFIG_PCI_HCI -/* #define IMR_RX_MASK (IMR_ROK_8812|IMR_RDU_8812|IMR_RXFOVW_8812) */ -#define IMR_TX_MASK (IMR_VODOK_8812 | IMR_VIDOK_8812 | IMR_BEDOK_8812 | IMR_BKDOK_8812 | IMR_MGNTDOK_8812 | IMR_HIGHDOK_8812) - -#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8812 | IMR_TXBCN0OK_8812 | IMR_TXBCN0ERR_8812 | IMR_BCNDERR0_8812) - -#define RT_AC_INT_MASKS (IMR_VIDOK_8812 | IMR_VODOK_8812 | IMR_BEDOK_8812 | IMR_BKDOK_8812) -#endif - - -/* **************************************************************************** -* Regsiter Bit and Content definition -* **************************************************************************** */ - -/* 2 ACMHWCTRL 0x05C0 */ -#define AcmHw_HwEn_8812 BIT(0) -#define AcmHw_VoqEn_8812 BIT(1) -#define AcmHw_ViqEn_8812 BIT(2) -#define AcmHw_BeqEn_8812 BIT(3) -#define AcmHw_VoqStatus_8812 BIT(5) -#define AcmHw_ViqStatus_8812 BIT(6) -#define AcmHw_BeqStatus_8812 BIT(7) - -#endif /* __RTL8812A_SPEC_H__ */ - -#ifdef CONFIG_RTL8821A -#include "rtl8821a_spec.h" -#endif /* CONFIG_RTL8821A */ diff --git a/include/rtl8812a_sreset.h b/include/rtl8812a_sreset.h deleted file mode 100644 index 1d166dc..0000000 --- a/include/rtl8812a_sreset.h +++ /dev/null @@ -1,29 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef _RTL88812A_SRESET_H_ -#define _RTL8812A_SRESET_H_ - -#include - -#ifdef DBG_CONFIG_ERROR_DETECT -extern void rtl8812_sreset_xmit_status_check(_adapter *padapter); -extern void rtl8812_sreset_linked_status_check(_adapter *padapter); -#endif -#endif diff --git a/include/rtl8812a_xmit.h b/include/rtl8812a_xmit.h deleted file mode 100644 index 9fe4dfb..0000000 --- a/include/rtl8812a_xmit.h +++ /dev/null @@ -1,371 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8812A_XMIT_H__ -#define __RTL8812A_XMIT_H__ - - -/* For 88e early mode */ -#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value) -#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value) -#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value) -#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value) -#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value) -#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value) -#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value) - -/* - * defined for TX DESC Operation - * */ - -#define MAX_TID (15) - -/* OFFSET 0 */ -#define OFFSET_SZ 0 -#define OFFSET_SHT 16 -#define BMC BIT(24) -#define LSG BIT(26) -#define FSG BIT(27) -#define OWN BIT(31) - - -/* OFFSET 4 */ -#define PKT_OFFSET_SZ 0 -#define QSEL_SHT 8 -#define RATE_ID_SHT 16 -#define NAVUSEHDR BIT(20) -#define SEC_TYPE_SHT 22 -#define PKT_OFFSET_SHT 26 - -/* OFFSET 8 */ -#define AGG_EN BIT(12) -#define AGG_BK BIT(16) -#define AMPDU_DENSITY_SHT 20 -#define ANTSEL_A BIT(24) -#define ANTSEL_B BIT(25) -#define TX_ANT_CCK_SHT 26 -#define TX_ANTL_SHT 28 -#define TX_ANT_HT_SHT 30 - -/* OFFSET 12 */ -#define SEQ_SHT 16 -#define EN_HWSEQ BIT(31) - -/* OFFSET 16 */ -#define QOS BIT(6) -#define HW_SSN BIT(7) -#define USERATE BIT(8) -#define DISDATAFB BIT(10) -#define CTS_2_SELF BIT(11) -#define RTS_EN BIT(12) -#define HW_RTS_EN BIT(13) -#define DATA_SHORT BIT(24) -#define PWR_STATUS_SHT 15 -#define DATA_SC_SHT 20 -#define DATA_BW BIT(25) - -/* OFFSET 20 */ -#define RTY_LMT_EN BIT(17) - -/* OFFSET 20 */ -#define SGI BIT(6) -#define USB_TXAGG_NUM_SHT 24 - -typedef struct txdescriptor_8812 { - /* Offset 0 */ - u32 pktlen:16; - u32 offset:8; - u32 bmc:1; - u32 htc:1; - u32 ls:1; - u32 fs:1; - u32 linip:1; - u32 noacm:1; - u32 gf:1; - u32 own:1; - - /* Offset 4 */ - u32 macid:6; - u32 rsvd0406:2; - u32 qsel:5; - u32 rd_nav_ext:1; - u32 lsig_txop_en:1; - u32 pifs:1; - u32 rate_id:4; - u32 navusehdr:1; - u32 en_desc_id:1; - u32 sectype:2; - u32 rsvd0424:2; - u32 pkt_offset:5; /* unit: 8 bytes */ - u32 rsvd0431:1; - - /* Offset 8 */ - u32 rts_rc:6; - u32 data_rc:6; - u32 agg_en:1; - u32 rd_en:1; - u32 bar_rty_th:2; - u32 bk:1; - u32 morefrag:1; - u32 raw:1; - u32 ccx:1; - u32 ampdu_density:3; - u32 bt_null:1; - u32 ant_sel_a:1; - u32 ant_sel_b:1; - u32 tx_ant_cck:2; - u32 tx_antl:2; - u32 tx_ant_ht:2; - - /* Offset 12 */ - u32 nextheadpage:8; - u32 tailpage:8; - u32 seq:12; - u32 cpu_handle:1; - u32 tag1:1; - u32 trigger_int:1; - u32 hwseq_en:1; - - /* Offset 16 */ - u32 rtsrate:5; - u32 ap_dcfe:1; - u32 hwseq_sel:2; - u32 userate:1; - u32 disrtsfb:1; - u32 disdatafb:1; - u32 cts2self:1; - u32 rtsen:1; - u32 hw_rts_en:1; - u32 port_id:1; - u32 pwr_status:3; - u32 wait_dcts:1; - u32 cts2ap_en:1; - u32 data_sc:2; - u32 data_stbc:2; - u32 data_short:1; - u32 data_bw:1; - u32 rts_short:1; - u32 rts_bw:1; - u32 rts_sc:2; - u32 vcs_stbc:2; - - /* Offset 20 */ - u32 datarate:6; - u32 sgi:1; - u32 try_rate:1; - u32 data_ratefb_lmt:5; - u32 rts_ratefb_lmt:4; - u32 rty_lmt_en:1; - u32 data_rt_lmt:6; - u32 usb_txagg_num:8; - - /* Offset 24 */ - u32 txagg_a:5; - u32 txagg_b:5; - u32 use_max_len:1; - u32 max_agg_num:5; - u32 mcsg1_max_len:4; - u32 mcsg2_max_len:4; - u32 mcsg3_max_len:4; - u32 mcs7_sgi_max_len:4; - - /* Offset 28 */ - u32 checksum:16; /* TxBuffSize(PCIe)/CheckSum(USB) */ - u32 mcsg4_max_len:4; - u32 mcsg5_max_len:4; - u32 mcsg6_max_len:4; - u32 mcs15_sgi_max_len:4; - - /* Offset 32 */ - u32 rsvd32; - - /* Offset 36 */ - u32 rsvd36; -} TXDESC_8812, *PTXDESC_8812; - - -/* Dword 0 */ -#define GET_TX_DESC_OWN_8812(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1) -#define SET_TX_DESC_PKT_SIZE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value) -#define SET_TX_DESC_OFFSET_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value) -#define SET_TX_DESC_BMC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value) -#define SET_TX_DESC_HTC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value) -#define SET_TX_DESC_LAST_SEG_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value) -#define SET_TX_DESC_FIRST_SEG_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value) -#define SET_TX_DESC_LINIP_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value) -#define SET_TX_DESC_NO_ACM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value) -#define SET_TX_DESC_GF_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value) -#define SET_TX_DESC_OWN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) - -/* Dword 1 */ -#define SET_TX_DESC_MACID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value) -#define SET_TX_DESC_QUEUE_SEL_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value) -#define SET_TX_DESC_RDG_NAV_EXT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value) -#define SET_TX_DESC_LSIG_TXOP_EN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value) -#define SET_TX_DESC_PIFS_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value) -#define SET_TX_DESC_RATE_ID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value) -#define SET_TX_DESC_EN_DESC_ID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value) -#define SET_TX_DESC_SEC_TYPE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value) -#define SET_TX_DESC_PKT_OFFSET_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value) - -/* Dword 2 */ -#define SET_TX_DESC_PAID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value) -#define SET_TX_DESC_CCA_RTS_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value) -#define SET_TX_DESC_AGG_ENABLE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value) -#define SET_TX_DESC_RDG_ENABLE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value) -#define SET_TX_DESC_AGG_BREAK_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value) -#define SET_TX_DESC_MORE_FRAG_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value) -#define SET_TX_DESC_RAW_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value) -#define SET_TX_DESC_SPE_RPT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value) -#define SET_TX_DESC_AMPDU_DENSITY_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value) -#define SET_TX_DESC_BT_INT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value) -#define SET_TX_DESC_GID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value) - -/* Dword 3 */ -#define SET_TX_DESC_WHEADER_LEN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value) -#define SET_TX_DESC_CHK_EN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value) -#define SET_TX_DESC_EARLY_MODE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value) -#define SET_TX_DESC_HWSEQ_SEL_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value) -#define SET_TX_DESC_USE_RATE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value) -#define SET_TX_DESC_DISABLE_RTS_FB_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value) -#define SET_TX_DESC_DISABLE_FB_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value) -#define SET_TX_DESC_CTS2SELF_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value) -#define SET_TX_DESC_RTS_ENABLE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value) -#define SET_TX_DESC_HW_RTS_ENABLE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value) -#define SET_TX_DESC_NAV_USE_HDR_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value) -#define SET_TX_DESC_USE_MAX_LEN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value) -#define SET_TX_DESC_MAX_AGG_NUM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value) -#define SET_TX_DESC_NDPA_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value) -#define SET_TX_DESC_AMPDU_MAX_TIME_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value) - -/* Dword 4 */ -#define SET_TX_DESC_TX_RATE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value) -#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value) -#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value) -#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value) -#define SET_TX_DESC_DATA_RETRY_LIMIT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value) -#define SET_TX_DESC_RTS_RATE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value) - -/* Dword 5 */ -#define SET_TX_DESC_DATA_SC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value) -#define SET_TX_DESC_DATA_SHORT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value) -#define SET_TX_DESC_DATA_BW_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value) -#define SET_TX_DESC_DATA_LDPC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value) -#define SET_TX_DESC_DATA_STBC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value) -#define SET_TX_DESC_CTROL_STBC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value) -#define SET_TX_DESC_RTS_SHORT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value) -#define SET_TX_DESC_RTS_SC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value) -#define SET_TX_DESC_TX_ANT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 4, __Value) - -/* Dword 6 */ -#define SET_TX_DESC_SW_DEFINE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value) -#define SET_TX_DESC_ANTSEL_A_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value) -#define SET_TX_DESC_ANTSEL_B_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value) -#define SET_TX_DESC_ANTSEL_C_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value) -#define SET_TX_DESC_ANTSEL_D_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value) -#define SET_TX_DESC_MBSSID_8821(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value) - -/* Dword 7 */ -#define SET_TX_DESC_TX_BUFFER_SIZE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) -#define SET_TX_DESC_TX_DESC_CHECKSUM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) -#define SET_TX_DESC_USB_TXAGG_NUM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) -#ifdef CONFIG_SDIO_HCI -#define SET_TX_DESC_SDIO_TXSEQ_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value) -#endif - -/* Dword 8 */ -#define SET_TX_DESC_HWSEQ_EN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) - -/* Dword 9 */ -#define SET_TX_DESC_SEQ_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value) - -/* Dword 10 */ -#define SET_TX_DESC_TX_BUFFER_ADDRESS_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value) -#define GET_TX_DESC_TX_BUFFER_ADDRESS_8812(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32) - -/* Dword 11 */ -#define SET_TX_DESC_NEXT_DESC_ADDRESS_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value) - - -#define SET_EARLYMODE_PKTNUM_8812(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value) -#define SET_EARLYMODE_LEN0_8812(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value) -#define SET_EARLYMODE_LEN1_1_8812(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value) -#define SET_EARLYMODE_LEN1_2_8812(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value) -#define SET_EARLYMODE_LEN2_8812(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value) -#define SET_EARLYMODE_LEN3_8812(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value) - -#ifdef CONFIG_TX_EARLY_MODE - #define USB_DUMMY_OFFSET 2 -#else - #define USB_DUMMY_OFFSET 1 -#endif -#define USB_DUMMY_LENGTH (USB_DUMMY_OFFSET * PACKET_OFFSET_SZ) - - -void rtl8812a_cal_txdesc_chksum(u8 *ptxdesc); -void rtl8812a_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); -void rtl8812a_fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc); -void rtl8812a_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc); -void rtl8812a_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc); -#if defined(CONFIG_CONCURRENT_MODE) -void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); -#endif - -#ifdef CONFIG_USB_HCI -s32 rtl8812au_init_xmit_priv(PADAPTER padapter); -void rtl8812au_free_xmit_priv(PADAPTER padapter); -s32 rtl8812au_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); -s32 rtl8812au_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); -s32 rtl8812au_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); -s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); -void rtl8812au_xmit_tasklet(void *priv); -s32 rtl8812au_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); -#endif - -#ifdef CONFIG_PCI_HCI -s32 rtl8812ae_init_xmit_priv(PADAPTER padapter); -void rtl8812ae_free_xmit_priv(PADAPTER padapter); -struct xmit_buf *rtl8812ae_dequeue_xmitbuf(struct rtw_tx_ring *ring); -void rtl8812ae_xmitframe_resume(_adapter *padapter); -s32 rtl8812ae_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); -s32 rtl8812ae_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); -s32 rtl8812ae_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); -void rtl8812ae_xmit_tasklet(void *priv); - -#ifdef CONFIG_XMIT_THREAD_MODE -s32 rtl8812ae_xmit_buf_handler(_adapter *padapter); -#endif - -#endif - -#ifdef CONFIG_TX_EARLY_MODE -void UpdateEarlyModeInfo8812(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); -#endif - -void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, u8 *ptxdesc); - -u8 BWMapping_8812(PADAPTER Adapter, struct pkt_attrib *pattrib); - -u8 SCMapping_8812(PADAPTER Adapter, struct pkt_attrib *pattrib); - -#endif /* __RTL8812_XMIT_H__ */ - -#ifdef CONFIG_RTL8821A -#include "rtl8821a_xmit.h" -#endif /* CONFIG_RTL8821A */ diff --git a/include/rtl8814a_cmd.h b/include/rtl8814a_cmd.h deleted file mode 100755 index ddd7fa6..0000000 --- a/include/rtl8814a_cmd.h +++ /dev/null @@ -1,170 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8814A_CMD_H__ -#define __RTL8814A_CMD_H__ -#include "hal_com_h2c.h" - -/* _RSVDPAGE_LOC_CMD0 */ -#define SET_8814A_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8814A_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) -#define SET_8814A_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) -#define SET_8814A_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) -#define SET_8814A_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) - -/* _SETPWRMODE_PARM */ -#define SET_8814A_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8814A_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value) -#define SET_8814A_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value) -#define SET_8814A_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) -#define SET_8814A_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) -#define SET_8814A_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value) -#define SET_8814A_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) -#define SET_8814A_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) - -#define GET_8814A_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8) - - -/* _WoWLAN PARAM_CMD5 */ -#define SET_8814A_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) -#define SET_8814A_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) -#define SET_8814A_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) -#define SET_8814A_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value) -#define SET_8814A_H2CCMD_WOWLAN_ALL_PKT_DROP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value) -#define SET_8814A_H2CCMD_WOWLAN_GPIO_ACTIVE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value) -#define SET_8814A_H2CCMD_WOWLAN_REKEY_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value) -#define SET_8814A_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value) -#define SET_8814A_H2CCMD_WOWLAN_GPIONUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) -#define SET_8814A_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) - - -/* WLANINFO_PARM */ -#define SET_8814A_H2CCMD_WLANINFO_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8814A_H2CCMD_WLANINFO_PARM_CHANNEL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) -#define SET_8814A_H2CCMD_WLANINFO_PARM_BW40MHZ(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) - -/* _REMOTE_WAKEUP_CMD7 */ -#define SET_8814A_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) -#define SET_8814A_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) -#define SET_8814A_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) -#define SET_8814A_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value) - - -/* _AP_OFFLOAD_CMD8 */ -#define SET_8814A_H2CCMD_AP_OFFLOAD_ON(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8814A_H2CCMD_AP_OFFLOAD_HIDDEN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) -#define SET_8814A_H2CCMD_AP_OFFLOAD_DENYANY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) -#define SET_8814A_H2CCMD_AP_OFFLOAD_WAKEUP_EVT_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) - -/* _PWR_MOD_CMD20 */ -#define SET_88E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_88E_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value) -#define SET_88E_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value) -#define SET_88E_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) -#define SET_88E_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) -#define SET_88E_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) - -/* AP_REQ_TXREP_CMD 0x43 */ -#define SET_8814A_H2CCMD_TXREP_PARM_STA1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_8814A_H2CCMD_TXREP_PARM_STA2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) -#define SET_8814A_H2CCMD_TXREP_PARM_RTY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value) - -/* C2H_AP_REQ_TXRPT */ -#define GET_8814A_C2H_TC2H_APREQ_TXRPT_MACID1(_Header) LE_BITS_TO_1BYTE((_Header + 0), 0, 8) -#define GET_8814A_C2H_TC2H_APREQ_TXRPT_TXOK1(_Header) LE_BITS_TO_2BYTE((_Header + 1), 0, 16) -#define GET_8814A_C2H_TC2H_APREQ_TXRPT_TXFAIL1(_Header) LE_BITS_TO_2BYTE((_Header + 3), 0, 16) -#define GET_8814A_C2H_TC2H_APREQ_TXRPT_INIRATE1(_Header) LE_BITS_TO_1BYTE((_Header + 5), 0, 8) -#define GET_8814A_C2H_TC2H_APREQ_TXRPT_MACID2(_Header) LE_BITS_TO_1BYTE((_Header + 6), 0, 8) -#define GET_8814A_C2H_TC2H_APREQ_TXRPT_TXOK2(_Header) LE_BITS_TO_2BYTE((_Header + 7), 0, 16) -#define GET_8814A_C2H_TC2H_APREQ_TXRPT_TXFAIL2(_Header) LE_BITS_TO_2BYTE((_Header + 9), 0, 16) -#define GET_8814A_C2H_TC2H_APREQ_TXRPT_INIRATE2(_Header) LE_BITS_TO_1BYTE((_Header + 11), 0, 8) - -/* C2H_SPC_STAT */ -#define GET_8814A_C2H_SPC_STAT_IDX(_Header) LE_BITS_TO_1BYTE((_Header + 0), 0, 8) - /* Tip :TYPE_A data3 is msb and data0 is lsb */ -#define GET_8814A_C2H_SPC_STAT_TYPEA_RETRY(_Header) LE_BITS_TO_4BYTE((_Header + 1), 0, 32) -#define GET_8814A_C2H_SPC_STAT_TYPEB_PKT1(_Header) LE_BITS_TO_2BYTE((_Header + 1), 0, 16) -#define GET_8814A_C2H_SPC_STAT_TYPEB_RETRY1(_Header) LE_BITS_TO_2BYTE((_Header + 3), 0, 16) -#define GET_8814A_C2H_SPC_STAT_TYPEB_PKT2(_Header) LE_BITS_TO_2BYTE((_Header + 5), 0, 16) -#define GET_8814A_C2H_SPC_STAT_TYPEB_RETRY2(_Header) LE_BITS_TO_2BYTE((_Header + 7), 0, 16) - -/*BCNHWSEQ*/ -#define SET_8814A_H2CCMD_BCNHWSEQ_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 1, __Value) -#define SET_8814A_H2CCMD_BCNHWSEQ_BCN_NUMBER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 1, 3, __Value) -#define SET_8814A_H2CCMD_BCNHWSEQ_HWSEQ(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 6, 1, __Value) -#define SET_8814A_H2CCMD_BCNHWSEQ_EXHWSEQ(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 7, 1, __Value) -#define SET_8814A_H2CCMD_BCNHWSEQ_PAGE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) -void rtl8814_fw_update_beacon_cmd(_adapter *padapter); - -/* TX Beamforming */ -#define GET_8814A_C2H_TXBF_ORIGINATE(_Header) LE_BITS_TO_1BYTE(_Header, 0, 8) -#define GET_8814A_C2H_TXBF_MACID(_Header) LE_BITS_TO_1BYTE((_Header + 1), 0, 8) - - - -/* / TX Feedback Content */ -#define USEC_UNIT_FOR_8814A_C2H_TX_RPT_QUEUE_TIME 256 - -#define GET_8814A_C2H_TX_RPT_QUEUE_SELECT(_Header) LE_BITS_TO_1BYTE((_Header + 0), 0, 5) -#define GET_8814A_C2H_TX_RPT_PKT_BROCAST(_Header) LE_BITS_TO_1BYTE((_Header + 0), 5, 1) -#define GET_8814A_C2H_TX_RPT_LIFE_TIME_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 6, 1) -#define GET_8814A_C2H_TX_RPT_RETRY_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 7, 1) -#define GET_8814A_C2H_TX_RPT_MAC_ID(_Header) LE_BITS_TO_1BYTE((_Header + 1), 0, 8) -#define GET_8814A_C2H_TX_RPT_DATA_RETRY_CNT(_Header) LE_BITS_TO_1BYTE((_Header + 2), 0, 6) -#define GET_8814A_C2H_TX_RPT_QUEUE_TIME(_Header) LE_BITS_TO_2BYTE((_Header + 3), 0, 16) /* In unit of 256 microseconds. */ -#define GET_8814A_C2H_TX_RPT_FINAL_DATA_RATE(_Header) LE_BITS_TO_1BYTE((_Header + 5), 0, 8) - - -/* _P2P_PS_OFFLOAD */ -#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) -#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) -#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_CTWINDOW_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) -#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_NOA0_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value) -#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_NOA1_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value) -#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value) -#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value) - -s32 FillH2CCmd_8814(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); -void rtl8814_set_raid_cmd(PADAPTER padapter, u64 bitmap, u8 *arg, u8 bw); -void rtl8814_set_wowlan_cmd(_adapter *padapter, u8 enable); -void rtl8814_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus); -void rtl8814_set_FwPwrMode_cmd(PADAPTER padapter, u8 PSMode); -u8 GetTxBufferRsvdPageNum8814(_adapter *padapter, bool wowlan); -u8 rtl8814_set_rssi_cmd(_adapter *padapter, u8 *param); -void rtl8814_req_txrpt_cmd(PADAPTER padapter, u8 macid); - -#ifdef CONFIG_TDLS - #ifdef CONFIG_TDLS_CH_SW - void rtl8814_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); - #endif -#endif - -void -Set_RA_LDPC_8814( - struct sta_info *psta, - BOOLEAN bLDPC -); - -s32 c2h_handler_8814a(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload); - -#ifdef CONFIG_P2P_PS - void rtl8814_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); -#endif /* CONFIG_P2P */ - -#endif/* __RTL8814A_CMD_H__ */ diff --git a/include/rtl8814a_dm.h b/include/rtl8814a_dm.h deleted file mode 100644 index bb925e4..0000000 --- a/include/rtl8814a_dm.h +++ /dev/null @@ -1,28 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8814A_DM_H__ -#define __RTL8814A_DM_H__ - -void rtl8814_init_dm_priv(IN PADAPTER Adapter); -void rtl8814_deinit_dm_priv(IN PADAPTER Adapter); -void rtl8814_InitHalDm(IN PADAPTER Adapter); -void rtl8814_HalDmWatchDog(IN PADAPTER Adapter); - -#endif diff --git a/include/rtl8814a_hal.h b/include/rtl8814a_hal.h deleted file mode 100755 index c5a3f88..0000000 --- a/include/rtl8814a_hal.h +++ /dev/null @@ -1,324 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8814A_HAL_H__ -#define __RTL8814A_HAL_H__ - -/* #include "hal_com.h" */ -#include "hal_data.h" - -/* include HAL Related header after HAL Related compiling flags */ -#include "rtl8814a_spec.h" -#include "rtl8814a_rf.h" -#include "rtl8814a_dm.h" -#include "rtl8814a_recv.h" -#include "rtl8814a_xmit.h" -#include "rtl8814a_cmd.h" -#include "rtl8814a_led.h" -#include "Hal8814PwrSeq.h" -#include "Hal8814PhyReg.h" -#include "Hal8814PhyCfg.h" -#ifdef DBG_CONFIG_ERROR_DETECT - #include "rtl8814a_sreset.h" -#endif /* DBG_CONFIG_ERROR_DETECT */ - -enum { - VOLTAGE_V25 = 0x03, - LDOE25_SHIFT = 28 , -}; -/* max. iram is 64k , max dmen is 32k. Total = 96k = 0x18000*/ -#define FW_SIZE 0x18000 -#define FW_START_ADDRESS 0x1000 -typedef struct _RT_FIRMWARE_8814 { - FIRMWARE_SOURCE eFWSource; -#ifdef CONFIG_EMBEDDED_FWIMG - u8 *szFwBuffer; -#else - u8 szFwBuffer[FW_SIZE]; -#endif - u32 ulFwLength; -} RT_FIRMWARE_8814, *PRT_FIRMWARE_8814; - -#define PAGE_SIZE_TX_8814 PAGE_SIZE_128 -#define BCNQ_PAGE_NUM_8814 0x08 - -#define Rtl8814A_NIC_PWR_ON_FLOW rtl8814A_power_on_flow -#define Rtl8814A_NIC_RF_OFF_FLOW rtl8814A_radio_off_flow -#define Rtl8814A_NIC_DISABLE_FLOW rtl8814A_card_disable_flow -#define Rtl8814A_NIC_ENABLE_FLOW rtl8814A_card_enable_flow -#define Rtl8814A_NIC_SUSPEND_FLOW rtl8814A_suspend_flow -#define Rtl8814A_NIC_RESUME_FLOW rtl8814A_resume_flow -#define Rtl8814A_NIC_PDN_FLOW rtl8814A_hwpdn_flow -#define Rtl8814A_NIC_LPS_ENTER_FLOW rtl8814A_enter_lps_flow -#define Rtl8814A_NIC_LPS_LEAVE_FLOW rtl8814A_leave_lps_flow - -/* ***************************************************** - * New Firmware Header(8-byte alinment required) - * ***************************************************** - * --- LONG WORD 0 ---- */ -#define GET_FIRMWARE_HDR_SIGNATURE_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 0, 16) -#define GET_FIRMWARE_HDR_CATEGORY_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 16, 8) /* AP/NIC and USB/PCI */ -#define GET_FIRMWARE_HDR_FUNCTION_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 24, 8) /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */ -#define GET_FIRMWARE_HDR_VERSION_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 0, 16)/* FW Version */ -#define GET_FIRMWARE_HDR_SUB_VER_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 16, 8) /* FW Subversion, default 0x00 */ -#define GET_FIRMWARE_HDR_SUB_IDX_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 24, 8) /* FW Subversion Index */ - -/* --- LONG WORD 1 ---- */ -#define GET_FIRMWARE_HDR_SVN_IDX_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 0, 32)/* The SVN entry index */ -#define GET_FIRMWARE_HDR_RSVD1_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+12, 0, 32) - -/* --- LONG WORD 2 ---- */ -#define GET_FIRMWARE_HDR_MONTH_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+16, 0, 8) /* Release time Month field */ -#define GET_FIRMWARE_HDR_DATE_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+16, 8, 8) /* Release time Date field */ -#define GET_FIRMWARE_HDR_HOUR_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+16, 16, 8)/* Release time Hour field */ -#define GET_FIRMWARE_HDR_MINUTE_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+16, 24, 8)/* Release time Minute field */ -#define GET_FIRMWARE_HDR_YEAR_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+20, 0, 16)/* Release time Year field */ -#define GET_FIRMWARE_HDR_FOUNDRY_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+20, 16, 8)/* Release time Foundry field */ -#define GET_FIRMWARE_HDR_RSVD2_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+20, 24, 8) - -/* --- LONG WORD 3 ---- */ -#define GET_FIRMWARE_HDR_MEM_UASGE_DL_FROM_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 0, 1) -#define GET_FIRMWARE_HDR_MEM_UASGE_BOOT_FROM_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 1, 1) -#define GET_FIRMWARE_HDR_MEM_UASGE_BOOT_LOADER_3081(__FwHdr)LE_BITS_TO_4BYTE(__FwHdr+24, 2, 1) -#define GET_FIRMWARE_HDR_MEM_UASGE_IRAM_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 3, 1) -#define GET_FIRMWARE_HDR_MEM_UASGE_ERAM_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 4, 1) -#define GET_FIRMWARE_HDR_MEM_UASGE_RSVD4_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 5, 3) -#define GET_FIRMWARE_HDR_RSVD3_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 8, 8) -#define GET_FIRMWARE_HDR_BOOT_LOADER_SZ_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 16, 16) -#define GET_FIRMWARE_HDR_RSVD5_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+28, 0, 32) - -/* --- LONG WORD 4 ---- */ -#define GET_FIRMWARE_HDR_TOTAL_DMEM_SZ_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+36, 0, 32) -#define GET_FIRMWARE_HDR_FW_CFG_SZ_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+36, 0, 16) -#define GET_FIRMWARE_HDR_FW_ATTR_SZ_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+36, 16, 16) - -/* --- LONG WORD 5 ---- */ -#define GET_FIRMWARE_HDR_IROM_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+40, 0, 32) -#define GET_FIRMWARE_HDR_EROM_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+44, 0, 32) - -/* --- LONG WORD 6 ---- */ -#define GET_FIRMWARE_HDR_IRAM_SZ_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+48, 0, 32) -#define GET_FIRMWARE_HDR_ERAM_SZ_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+52, 0, 32) - -/* --- LONG WORD 7 ---- */ -#define GET_FIRMWARE_HDR_RSVD6_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+56, 0, 32) -#define GET_FIRMWARE_HDR_RSVD7_3081(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+60, 0, 32) - - - -/* - * 2013/08/16 MH MOve from SDIO.h for common use. - * */ -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI) - #define TRX_SHARE_MODE_8814A 0 /* TRX Buffer Share Index */ - #define BASIC_RXFF_SIZE_8814A 24576/* Basic RXFF Size is 24K = 24*1024 Unit: Byte */ - #define TRX_SHARE_BUFF_UNIT_8814A 65536/* TRX Share Buffer unit Size 64K = 64*1024 Unit: Byte */ - #define TRX_SHARE_BUFF_UNIT_PAGE_8814A (TRX_SHARE_BUFF_UNIT_8814A/PAGE_SIZE_8814A)/* 512 Pages */ - - /* Origin: */ - #define HPQ_PGNUM_8814A 0x20 /* High Queue */ - #define LPQ_PGNUM_8814A 0x20 /* Low Queue */ - #define NPQ_PGNUM_8814A 0x20 /* Normal Queue */ - #define EPQ_PGNUM_8814A 0x20 /* Extra Queue */ - -#else /* #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI) */ - - #define HPQ_PGNUM_8814A 20 - #define NPQ_PGNUM_8814A 20 - #define LPQ_PGNUM_8814A 20 /* 1972 */ - #define EPQ_PGNUM_8814A 20 - #define BCQ_PGNUM_8814A 32 - -#endif /* #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI) */ - -#ifdef CONFIG_WOWLAN - #define WOWLAN_PAGE_NUM_8814 0x00 -#else - #define WOWLAN_PAGE_NUM_8814 0x00 -#endif - -#define PAGE_SIZE_8814A 128/* TXFF Page Size, Unit: Byte */ -#define MAX_RX_DMA_BUFFER_SIZE_8814A 0x5C00 /* BASIC_RXFF_SIZE_8814A + TRX_SHARE_MODE_8814A * TRX_SHARE_BUFF_UNIT_8814A */ /* Basic RXFF Size + ShareBuffer Size */ -#define TX_PAGE_BOUNDARY_8814A TXPKT_PGNUM_8814A /* Need to enlarge boundary, by KaiYuan */ -#define TX_PAGE_BOUNDARY_WOWLAN_8814A TXPKT_PGNUM_8814A /* TODO: 20130415 KaiYuan Check this value later */ - -#ifdef CONFIG_FW_C2H_DEBUG - #define RX_DMA_RESERVED_SIZE_8814A 0x100 /* 256B, reserved for c2h debug message */ -#else - #define RX_DMA_RESERVED_SIZE_8814A 0x0 /* 0B */ -#endif -#define RX_DMA_BOUNDARY_8814A (MAX_RX_DMA_BUFFER_SIZE_8814A - RX_DMA_RESERVED_SIZE_8814A - 1) - -#define TOTAL_PGNUM_8814A 2048 -#define TXPKT_PGNUM_8814A (2048 - BCNQ_PAGE_NUM_8814-WOWLAN_PAGE_NUM_8814) -#define PUB_PGNUM_8814A (TXPKT_PGNUM_8814A-HPQ_PGNUM_8814A-NPQ_PGNUM_8814A-LPQ_PGNUM_8814A-EPQ_PGNUM_8814A) - -/* Note: For WMM Normal Chip Setting ,modify later */ -#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8814A TX_PAGE_BOUNDARY_8814A -#define WMM_NORMAL_TX_PAGE_BOUNDARY_8814A (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8814A + 1) - -#define DRIVER_EARLY_INT_TIME_8814 0x05 -#define BCN_DMA_ATIME_INT_TIME_8814 0x02 - - -#define MAX_PAGE_SIZE 4096 /* @ page : 4k bytes */ - -#define EFUSE_MAX_SECTION_JAGUAR 64 - -#define HWSET_MAX_SIZE_8814A 512 - -#define EFUSE_REAL_CONTENT_LEN_8814A 1024 -#define EFUSE_MAX_BANK_8814A 2 - -#define EFUSE_MAP_LEN_8814A 512 -#define EFUSE_MAX_SECTION_8814A 64 -#define EFUSE_MAX_WORD_UNIT_8814A 4 -#define EFUSE_PROTECT_BYTES_BANK_8814A 16 - -#define EFUSE_IC_ID_OFFSET_8814A 506 /* For some inferiority IC purpose. added by Roger, 2009.09.02. */ -#define AVAILABLE_EFUSE_ADDR_8814A(addr) (addr < EFUSE_REAL_CONTENT_LEN_8814A) - -/*------------------------------------------------------------------------- -Chip specific --------------------------------------------------------------------------*/ - -/* pic buffer descriptor */ -#if 1 /* according to the define in the rtw_xmit.h, rtw_recv.h */ - #define RTL8814AE_SEG_NUM TX_BUFFER_SEG_NUM /* 0:2 seg, 1: 4 seg, 2: 8 seg */ - #define TX_DESC_NUM_8814A TXDESC_NUM /* 128 */ - #define RX_DESC_NUM_8814A PCI_MAX_RX_COUNT /* 128 */ - #ifdef CONFIG_CONCURRENT_MODE - #define BE_QUEUE_TX_DESC_NUM_8814A (TXDESC_NUM<<1) /* 256 */ - #else - #define BE_QUEUE_TX_DESC_NUM_8814A (TXDESC_NUM+(TXDESC_NUM>>1)) /* 192 */ - #endif -#else - #define RTL8814AE_SEG_NUM TX_BUFFER_SEG_NUM /* 0:2 seg, 1: 4 seg, 2: 8 seg */ - #define TX_DESC_NUM_8814A 128 /* 1024//2048 change by ylb 20130624 */ - #define RX_DESC_NUM_8814A 128 /* 1024 //512 change by ylb 20130624 */ -#endif - -/* To prevent out of boundary programming case, leave 1byte and program full section - * 9bytes + 1byt + 5bytes and pre 1byte. - * For worst case: - * | 1byte|----8bytes----|1byte|--5bytes--| - * | | Reserved(14bytes) | - * */ -#define EFUSE_OOB_PROTECT_BYTES 15 /* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */ - -/* rtl8814_hal_init.c */ -s32 FirmwareDownload8814A(PADAPTER Adapter, BOOLEAN bUsedWoWLANFw); -void InitializeFirmwareVars8814(PADAPTER padapter); - -VOID -Hal_InitEfuseVars_8814A( - IN PADAPTER Adapter -); - -s32 InitLLTTable8814A( - IN PADAPTER Adapter -); - - -void InitRDGSetting8814A(PADAPTER padapter); - -/* void CheckAutoloadState8812A(PADAPTER padapter); */ - -/* EFuse */ -u8 GetEEPROMSize8814A(PADAPTER padapter); -VOID hal_InitPGData_8814A( - IN PADAPTER padapter, - IN OUT u8 *PROMContent -); - -void hal_ReadPROMVersion8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void hal_ReadTxPowerInfo8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void hal_ReadBoardType8814A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void hal_ReadThermalMeter_8814A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); -void hal_ReadChannelPlan8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void hal_EfuseParseXtal_8814A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void hal_ReadAntennaDiversity8814A(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail); -void hal_Read_TRX_antenna_8814A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); -VOID hal_ReadAmplifierType_8814A( - IN PADAPTER Adapter -); -VOID hal_ReadPAType_8814A( - IN PADAPTER Adapter, - IN u8 *PROMContent, - IN BOOLEAN AutoloadFail, - OUT u8 *pPAType, - OUT u8 *pLNAType -); - -void hal_ReadPowerTrackingType_8814A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); - -void hal_GetRxGainOffset_8814A( - PADAPTER Adapter, - pu1Byte PROMContent, - BOOLEAN AutoloadFail -); -void Hal_EfuseParseKFreeData_8814A( - IN PADAPTER Adapter, - IN u8 *PROMContent, - IN BOOLEAN AutoloadFail); -void hal_ReadRFEType_8814A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); -void hal_EfuseParseBTCoexistInfo8814A(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail); - -/* void hal_ReadUsbType_8812AU(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); - * int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware); */ -void hal_ReadRemoteWakeup_8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -u8 MgntQuery_NssTxRate(u16 Rate); - -/* BOOLEAN HalDetectPwrDownMode8812(PADAPTER Adapter); */ - -#ifdef CONFIG_WOWLAN - void Hal_DetectWoWMode(PADAPTER pAdapter); -#endif /* CONFIG_WOWLAN */ - -void _InitBeaconParameters_8814A(PADAPTER padapter); -void SetBeaconRelatedRegisters8814A(PADAPTER padapter); - -void ReadRFType8814A(PADAPTER padapter); -void InitDefaultValue8814A(PADAPTER padapter); - -void SetHwReg8814A(PADAPTER padapter, u8 variable, u8 *pval); -void GetHwReg8814A(PADAPTER padapter, u8 variable, u8 *pval); -u8 SetHalDefVar8814A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); -u8 GetHalDefVar8814A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); -void rtl8814_set_hal_ops(struct hal_ops *pHalFunc); -void init_hal_spec_8814a(_adapter *adapter); - -/* register */ -void SetBcnCtrlReg(PADAPTER padapter, u8 SetBits, u8 ClearBits); -void SetBcnCtrlReg(PADAPTER Adapter, u8 SetBits, u8 ClearBits); -void rtl8814_start_thread(PADAPTER padapter); -void rtl8814_stop_thread(PADAPTER padapter); - - -#ifdef CONFIG_PCI_HCI - BOOLEAN InterruptRecognized8814AE(PADAPTER Adapter); - VOID UpdateInterruptMask8814AE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1); - u16 get_txbd_idx_addr(u16 ff_hwaddr); -#endif - -#ifdef CONFIG_BT_COEXIST - void rtl8812a_combo_card_WifiOnlyHwInit(PADAPTER Adapter); -#endif - -#endif /* __RTL8188E_HAL_H__ */ diff --git a/include/rtl8814a_led.h b/include/rtl8814a_led.h deleted file mode 100644 index 1137a9b..0000000 --- a/include/rtl8814a_led.h +++ /dev/null @@ -1,40 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8814A_LED_H__ -#define __RTL8814A_LED_H__ - - -/* ******************************************************************************** - * Interface to manipulate LED objects. - * ******************************************************************************** */ -#ifdef CONFIG_USB_HCI - void rtl8814au_InitSwLeds(PADAPTER padapter); - void rtl8814au_DeInitSwLeds(PADAPTER padapter); -#endif /* CONFIG_USB_HCI */ -#ifdef CONFIG_PCI_HCI - void rtl8814ae_InitSwLeds(PADAPTER padapter); - void rtl8814ae_DeInitSwLeds(PADAPTER padapter); -#endif /* CONFIG_PCI_HCI */ -#ifdef CONFIG_SDIO_HCI - void rtl8814s_InitSwLeds(PADAPTER padapter); - void rtl8814s_DeInitSwLeds(PADAPTER padapter); -#endif /* CONFIG_SDIO_HCI */ - -#endif /* __RTL8814A_LED_H__ */ diff --git a/include/rtl8814a_recv.h b/include/rtl8814a_recv.h deleted file mode 100755 index 710b1b2..0000000 --- a/include/rtl8814a_recv.h +++ /dev/null @@ -1,187 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8814A_RECV_H__ -#define __RTL8814A_RECV_H__ - -#if defined(CONFIG_USB_HCI) - - #ifndef MAX_RECVBUF_SZ - #ifndef CONFIG_MINIMAL_MEMORY_USAGE - #ifdef CONFIG_PLATFORM_MSTAR - #define MAX_RECVBUF_SZ (8192) /* 8K */ - #else - #define MAX_RECVBUF_SZ (32768) /* 32k */ - #endif - /* #define MAX_RECVBUF_SZ (24576) */ /* 24k */ - /* #define MAX_RECVBUF_SZ (20480) */ /* 20K */ - /* #define MAX_RECVBUF_SZ (10240) */ /* 10K */ - /* #define MAX_RECVBUF_SZ (15360) */ /* 15k < 16k */ - /* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */ - #else - #define MAX_RECVBUF_SZ (4000) /* about 4K */ - #endif - #endif /* !MAX_RECVBUF_SZ */ - -#elif defined(CONFIG_PCI_HCI) - /* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */ - /* #define MAX_RECVBUF_SZ (9100) */ - /* #else */ - #define MAX_RECVBUF_SZ (4000) /* about 4K - * #endif */ - - -#elif defined(CONFIG_SDIO_HCI) - #if 0 - /* temp solution */ - #ifdef CONFIG_SDIO_RX_COPY - #define MAX_RECVBUF_SZ (10240) - #else /* !CONFIG_SDIO_RX_COPY */ - #define MAX_RECVBUF_SZ MAX_RX_DMA_BUFFER_SIZE_8821 - #endif /* !CONFIG_SDIO_RX_COPY */ - #endif -#endif - - -/* RX buffer descriptor */ -/* DWORD 0 */ -#define SET_RX_BUFFER_DESC_DATA_LENGTH_8814A(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value) -#define SET_RX_BUFFER_DESC_LS_8814A(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 14, 1, __Value) -#define SET_RX_BUFFER_DESC_FS_8814A(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value) -#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8814A(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 16, __Value) - -#define GET_RX_BUFFER_DESC_OWN_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1) -#define GET_RX_BUFFER_DESC_LS_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1) -#define GET_RX_BUFFER_DESC_FS_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1) -#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15) - -/* DWORD 1 */ -#define SET_RX_BUFFER_PHYSICAL_LOW_8814A(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value) -#define GET_RX_BUFFER_PHYSICAL_LOW_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 0, 32) - -/* DWORD 2 */ -#define SET_RX_BUFFER_PHYSICAL_HIGH_8814A(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value) - -/* DWORD 3*/ /* RESERVED */ - - -#if 0 - /* ============= - * RX Info - * ============== */ -#endif -/* DWORD 0 */ -#define SET_RX_STATUS_DESC_PKT_LEN_8814A(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value) -#define SET_RX_STATUS_DESC_EOR_8814A(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value) -#define SET_RX_STATUS_DESC_OWN_8814AE(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value) - -#define GET_RX_STATUS_DESC_PKT_LEN_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14) -#define GET_RX_STATUS_DESC_CRC32_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1) -#define GET_RX_STATUS_DESC_ICV_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1) -#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4) -#define GET_RX_STATUS_DESC_SECURITY_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3) -#define GET_RX_STATUS_DESC_QOS_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1) -#define GET_RX_STATUS_DESC_SHIFT_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2) -#define GET_RX_STATUS_DESC_PHY_STATUS_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1) -#define GET_RX_STATUS_DESC_SWDEC_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1) -#define GET_RX_STATUS_DESC_LAST_SEG_8814AE(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1) -#define GET_RX_STATUS_DESC_EOR_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1) - -/* DWORD 1 */ -#define GET_RX_STATUS_DESC_MACID_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 0, 7) -#define GET_RX_STATUS_DESC_EXT_SECTYPE_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 7, 1)/* 20130415 KaiYuan add for 8814 */ -#define GET_RX_STATUS_DESC_TID_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 8, 4) -#define GET_RX_STATUS_DESC_MACID_VLD_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 12, 1) -#define GET_RX_STATUS_DESC_AMSDU_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 13, 1) -#define GET_RX_STATUS_DESC_RXID_MATCH_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 14, 1) -#define GET_RX_STATUS_DESC_PAGGR_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 15, 1) -#define GET_RX_STATUS_DESC_TCPOFFLOAD_CHKERR_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 20, 1) -#define GET_RX_STATUS_DESC_TCPOFFLOAD_IPVER_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 21, 1) -#define GET_RX_STATUS_DESC_TCPOFFLOAD_IS_TCPUDP_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 22, 1) -#define GET_RX_STATUS_DESC_TCPOFFLOAD_CHK_VLD_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 23, 1) -#define GET_RX_STATUS_DESC_PAM_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 24, 1) -#define GET_RX_STATUS_DESC_PWR_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 25, 1) -#define GET_RX_STATUS_DESC_MORE_DATA_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 26, 1) -#define GET_RX_STATUS_DESC_MORE_FRAG_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 27, 1) -#define GET_RX_STATUS_DESC_TYPE_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 28, 2) -#define GET_RX_STATUS_DESC_FIRST_SEG_8814AE(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1) -#define GET_RX_STATUS_DESC_EOR_8814AE(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1) -#define GET_RX_STATUS_DESC_MC_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 30, 1) -#define GET_RX_STATUS_DESC_BC_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 31, 1) - -/* DWORD 2 */ -#define GET_RX_STATUS_DESC_SEQ_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12) -#define GET_RX_STATUS_DESC_FRAG_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4) -#ifdef CONFIG_USB_RX_AGGREGATION - #define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 8) -#else - #define GET_RX_STATUS_DESC_RX_IS_QOS_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1) -#endif -#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6) -#define GET_RX_STATUS_DESC_HWRSVD_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 24, 4) -#define GET_RX_STATUS_C2H_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1) -#define GET_RX_STATUS_DESC_FCS_OK_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1) - -/* DWORD 3 */ -#define GET_RX_STATUS_DESC_RX_RATE_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7) -#define GET_RX_STATUS_DESC_BSSID_FIT_H_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 7, 3)/* 20130415 KaiYuan add for 8814 */ -#define GET_RX_STATUS_DESC_HTC_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1) -#define GET_RX_STATUS_DESC_EOSP_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1) -#define GET_RX_STATUS_DESC_BSSID_FIT_L_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2) -#define GET_RX_STATUS_DESC_DMA_AGG_NUM_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)/* 20130415 KaiYuan Check if it exist anymore */ -#define GET_RX_STATUS_DESC_PATTERN_MATCH_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 29, 1) -#define GET_RX_STATUS_DESC_UNICAST_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 30, 1) -#define GET_RX_STATUS_DESC_MAGIC_WAKE_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 31, 1) - -/* DWORD 4 */ -#define GET_RX_STATUS_DESC_PATTERN_IDX_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 0, 8) -#define GET_RX_STATUS_DESC_RX_EOF_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 8, 1) -#define GET_RX_STATUS_DESC_RX_SCRAMBLER_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 9, 7) -#define GET_RX_STATUS_DESC_RX_PRE_NDP_VLD_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 16, 1) -#define GET_RX_STATUS_DESC_A1_FIT_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 24, 5) - - -/* DWORD 5 */ -#define GET_RX_STATUS_DESC_TSFL_8814A(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32) - - -/* Rx smooth factor */ -#define Rx_Smooth_Factor (20) - -#ifdef CONFIG_USB_HCI - s32 rtl8814au_init_recv_priv(PADAPTER padapter); - void rtl8814au_free_recv_priv(PADAPTER padapter); -#endif - -#ifdef CONFIG_PCI_HCI - s32 rtl8814ae_init_recv_priv(PADAPTER padapter); - void rtl8814ae_free_recv_priv(PADAPTER padapter); -#endif - -#if 0 - /* temp solution */ - #ifdef CONFIG_SDIO_HCI - s32 InitRecvPriv8821AS(PADAPTER padapter); - void FreeRecvPriv8821AS(PADAPTER padapter); - #endif /* CONFIG_SDIO_HCI */ -#endif - -void rtl8814_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc); - -#endif /* __RTL8814A_RECV_H__ */ diff --git a/include/rtl8814a_rf.h b/include/rtl8814a_rf.h deleted file mode 100644 index 7b11d99..0000000 --- a/include/rtl8814a_rf.h +++ /dev/null @@ -1,33 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8814A_RF_H__ -#define __RTL8814A_RF_H__ - -VOID -PHY_RF6052SetBandwidth8814A( - IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth); - - -int -PHY_RF6052_Config_8814A( - IN PADAPTER Adapter); - -#endif/* __RTL8188E_RF_H__ */ diff --git a/include/rtl8814a_spec.h b/include/rtl8814a_spec.h deleted file mode 100755 index a3c7e64..0000000 --- a/include/rtl8814a_spec.h +++ /dev/null @@ -1,643 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ -#ifndef __RTL8814A_SPEC_H__ -#define __RTL8814A_SPEC_H__ - -#include - - -/* ************************************************************ - * - * ************************************************************ */ - -/* ----------------------------------------------------- - * - * 0x0000h ~ 0x00FFh System Configuration - * - * ----------------------------------------------------- */ -#define REG_SYS_ISO_CTRL_8814A 0x0000 /* 2 Byte */ -#define REG_SYS_FUNC_EN_8814A 0x0002 /* 2 Byte */ -#define REG_SYS_PW_CTRL_8814A 0x0004 /* 4 Byte */ -#define REG_SYS_CLKR_8814A 0x0008 /* 2 Byte */ -#define REG_SYS_EEPROM_CTRL_8814A 0x000A /* 2 Byte */ -#define REG_EE_VPD_8814A 0x000C /* 2 Byte */ -#define REG_SYS_SWR_CTRL1_8814A 0x0010 /* 1 Byte */ -#define REG_SPS0_CTRL_8814A 0x0011 /* 7 Byte */ -#define REG_SYS_SWR_CTRL3_8814A 0x0018 /* 4 Byte */ -#define REG_RSV_CTRL_8814A 0x001C /* 3 Byte */ -#define REG_RF_CTRL0_8814A 0x001F /* 1 Byte */ -#define REG_RF_CTRL1_8814A 0x0020 /* 1 Byte */ -#define REG_RF_CTRL2_8814A 0x0021 /* 1 Byte */ -#define REG_LPLDO_CTRL_8814A 0x0023 /* 1 Byte */ -#define REG_AFE_CTRL1_8814A 0x0024 /* 4 Byte */ -#define REG_AFE_CTRL2_8814A 0x0028 /* 4 Byte */ -#define REG_AFE_CTRL3_8814A 0x002c /* 4 Byte */ -#define REG_EFUSE_CTRL_8814A 0x0030 -#define REG_LDO_EFUSE_CTRL_8814A 0x0034 -#define REG_PWR_DATA_8814A 0x0038 -#define REG_CAL_TIMER_8814A 0x003C -#define REG_ACLK_MON_8814A 0x003E -#define REG_GPIO_MUXCFG_8814A 0x0040 -#define REG_GPIO_IO_SEL_8814A 0x0042 -#define REG_MAC_PINMUX_CFG_8814A 0x0043 -#define REG_GPIO_PIN_CTRL_8814A 0x0044 -#define REG_GPIO_INTM_8814A 0x0048 -#define REG_LEDCFG0_8814A 0x004C -#define REG_LEDCFG1_8814A 0x004D -#define REG_LEDCFG2_8814A 0x004E -#define REG_LEDCFG3_8814A 0x004F -#define REG_FSIMR_8814A 0x0050 -#define REG_FSISR_8814A 0x0054 -#define REG_HSIMR_8814A 0x0058 -#define REG_HSISR_8814A 0x005c -#define REG_GPIO_EXT_CTRL_8814A 0x0060 -#define REG_GPIO_STATUS_8814A 0x006C -#define REG_SDIO_CTRL_8814A 0x0070 -#define REG_HCI_OPT_CTRL_8814A 0x0074 -#define REG_RF_CTRL3_8814A 0x0076 /* 1 Byte */ -#define REG_AFE_CTRL4_8814A 0x0078 -#define REG_8051FW_CTRL_8814A 0x0080 -#define REG_HIMR0_8814A 0x00B0 -#define REG_HISR0_8814A 0x00B4 -#define REG_HIMR1_8814A 0x00B8 -#define REG_HISR1_8814A 0x00BC -#define REG_SYS_CFG1_8814A 0x00F0 -#define REG_SYS_CFG2_8814A 0x00FC -#define REG_SYS_CFG3_8814A 0x1000 - -/* ----------------------------------------------------- - * - * 0x0100h ~ 0x01FFh MACTOP General Configuration - * - * ----------------------------------------------------- */ -#define REG_CR_8814A 0x0100 -#define REG_PBP_8814A 0x0104 -#define REG_PKT_BUFF_ACCESS_CTRL_8814A 0x0106 -#define REG_TRXDMA_CTRL_8814A 0x010C -#define REG_TRXFF_BNDY_8814A 0x0114 -#define REG_TRXFF_STATUS_8814A 0x0118 -#define REG_RXFF_PTR_8814A 0x011C -#define REG_CPWM_8814A 0x012F -#define REG_FWIMR_8814A 0x0130 -#define REG_FWISR_8814A 0x0134 -#define REG_FTIMR_8814A 0x0138 -#define REG_PKTBUF_DBG_CTRL_8814A 0x0140 -#define REG_RXPKTBUF_CTRL_8814A 0x0142 -#define REG_PKTBUF_DBG_DATA_L_8814A 0x0144 -#define REG_PKTBUF_DBG_DATA_H_8814A 0x0148 - -#define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN - -#define REG_TC0_CTRL_8814A 0x0150 -#define REG_TC1_CTRL_8814A 0x0154 -#define REG_TC2_CTRL_8814A 0x0158 -#define REG_TC3_CTRL_8814A 0x015C -#define REG_TC4_CTRL_8814A 0x0160 -#define REG_TCUNIT_BASE_8814A 0x0164 -#define REG_RSVD3_8814A 0x0168 -#define REG_C2HEVT_MSG_NORMAL_8814A 0x01A0 -#define REG_C2HEVT_CLEAR_8814A 0x01AF -#define REG_MCUTST_1_8814A 0x01C0 -#define REG_MCUTST_WOWLAN_8814A 0x01C7 -#define REG_FMETHR_8814A 0x01C8 -#define REG_HMETFR_8814A 0x01CC -#define REG_HMEBOX_0_8814A 0x01D0 -#define REG_HMEBOX_1_8814A 0x01D4 -#define REG_HMEBOX_2_8814A 0x01D8 -#define REG_HMEBOX_3_8814A 0x01DC -#define REG_LLT_INIT_8814A 0x01E0 -#define REG_LLT_ADDR_8814A 0x01E4 /* 20130415 KaiYuan add for 8814 */ -#define REG_HMEBOX_EXT0_8814A 0x01F0 -#define REG_HMEBOX_EXT1_8814A 0x01F4 -#define REG_HMEBOX_EXT2_8814A 0x01F8 -#define REG_HMEBOX_EXT3_8814A 0x01FC - -/* ----------------------------------------------------- - * - * 0x0200h ~ 0x027Fh TXDMA Configuration - * - * ----------------------------------------------------- */ -#define REG_FIFOPAGE_CTRL_1_8814A 0x0200 -#define REG_FIFOPAGE_CTRL_2_8814A 0x0204 -#define REG_AUTO_LLT_8814A 0x0208 -#define REG_TXDMA_OFFSET_CHK_8814A 0x020C -#define REG_TXDMA_STATUS_8814A 0x0210 -#define REG_RQPN_NPQ_8814A 0x0214 -#define REG_TQPNT1_8814A 0x0218 -#define REG_TQPNT2_8814A 0x021C -#define REG_TQPNT3_8814A 0x0220 -#define REG_TQPNT4_8814A 0x0224 -#define REG_RQPN_CTRL_1_8814A 0x0228 -#define REG_RQPN_CTRL_2_8814A 0x022C -#define REG_FIFOPAGE_INFO_1_8814A 0x0230 -#define REG_FIFOPAGE_INFO_2_8814A 0x0234 -#define REG_FIFOPAGE_INFO_3_8814A 0x0238 -#define REG_FIFOPAGE_INFO_4_8814A 0x023C -#define REG_FIFOPAGE_INFO_5_8814A 0x0240 - - -/* ----------------------------------------------------- - * - * 0x0280h ~ 0x02FFh RXDMA Configuration - * - * ----------------------------------------------------- */ -#define REG_RXDMA_AGG_PG_TH_8814A 0x0280 -#define REG_RXPKT_NUM_8814A 0x0284 /* The number of packets in RXPKTBUF. */ -#define REG_RXDMA_CONTROL_8814A 0x0286 /* ?????? Control the RX DMA. */ -#define REG_RXDMA_STATUS_8814A 0x0288 -#define REG_RXDMA_MODE_8814A 0x0290 /* ?????? */ -#define REG_EARLY_MODE_CONTROL_8814A 0x02BC /* ?????? */ -#define REG_RSVD5_8814A 0x02F0 /* ?????? */ - - -/* ----------------------------------------------------- - * - * 0x0300h ~ 0x03FFh PCIe - * - * ----------------------------------------------------- */ -#define REG_PCIE_CTRL_REG_8814A 0x0300 -#define REG_INT_MIG_8814A 0x0304 /* Interrupt Migration */ -#define REG_BCNQ_TXBD_DESA_8814A 0x0308 /* TX Beacon Descriptor Address */ -#define REG_MGQ_TXBD_DESA_8814A 0x0310 /* TX Manage Queue Descriptor Address */ -#define REG_VOQ_TXBD_DESA_8814A 0x0318 /* TX VO Queue Descriptor Address */ -#define REG_VIQ_TXBD_DESA_8814A 0x0320 /* TX VI Queue Descriptor Address */ -#define REG_BEQ_TXBD_DESA_8814A 0x0328 /* TX BE Queue Descriptor Address */ -#define REG_BKQ_TXBD_DESA_8814A 0x0330 /* TX BK Queue Descriptor Address */ -#define REG_RXQ_RXBD_DESA_8814A 0x0338 /* RX Queue Descriptor Address */ -#define REG_HI0Q_TXBD_DESA_8814A 0x0340 -#define REG_HI1Q_TXBD_DESA_8814A 0x0348 -#define REG_HI2Q_TXBD_DESA_8814A 0x0350 -#define REG_HI3Q_TXBD_DESA_8814A 0x0358 -#define REG_HI4Q_TXBD_DESA_8814A 0x0360 -#define REG_HI5Q_TXBD_DESA_8814A 0x0368 -#define REG_HI6Q_TXBD_DESA_8814A 0x0370 -#define REG_HI7Q_TXBD_DESA_8814A 0x0378 -#define REG_MGQ_TXBD_NUM_8814A 0x0380 -#define REG_RX_RXBD_NUM_8814A 0x0382 -#define REG_VOQ_TXBD_NUM_8814A 0x0384 -#define REG_VIQ_TXBD_NUM_8814A 0x0386 -#define REG_BEQ_TXBD_NUM_8814A 0x0388 -#define REG_BKQ_TXBD_NUM_8814A 0x038A -#define REG_HI0Q_TXBD_NUM_8814A 0x038C -#define REG_HI1Q_TXBD_NUM_8814A 0x038E -#define REG_HI2Q_TXBD_NUM_8814A 0x0390 -#define REG_HI3Q_TXBD_NUM_8814A 0x0392 -#define REG_HI4Q_TXBD_NUM_8814A 0x0394 -#define REG_HI5Q_TXBD_NUM_8814A 0x0396 -#define REG_HI6Q_TXBD_NUM_8814A 0x0398 -#define REG_HI7Q_TXBD_NUM_8814A 0x039A -#define REG_TSFTIMER_HCI_8814A 0x039C - -/* Read Write Point */ -#define REG_VOQ_TXBD_IDX_8814A 0x03A0 -#define REG_VIQ_TXBD_IDX_8814A 0x03A4 -#define REG_BEQ_TXBD_IDX_8814A 0x03A8 -#define REG_BKQ_TXBD_IDX_8814A 0x03AC -#define REG_MGQ_TXBD_IDX_8814A 0x03B0 -#define REG_RXQ_TXBD_IDX_8814A 0x03B4 -#define REG_HI0Q_TXBD_IDX_8814A 0x03B8 -#define REG_HI1Q_TXBD_IDX_8814A 0x03BC -#define REG_HI2Q_TXBD_IDX_8814A 0x03C0 -#define REG_HI3Q_TXBD_IDX_8814A 0x03C4 -#define REG_HI4Q_TXBD_IDX_8814A 0x03C8 -#define REG_HI5Q_TXBD_IDX_8814A 0x03CC -#define REG_HI6Q_TXBD_IDX_8814A 0x03D0 -#define REG_HI7Q_TXBD_IDX_8814A 0x03D4 -#define REG_DBG_SEL_V1_8814A 0x03D8 -#define REG_PCIE_HRPWM1_V1_8814A 0x03D9 -#define REG_PCIE_HCPWM1_V1_8814A 0x03DA -#define REG_PCIE_CTRL2_8814A 0x03DB -#define REG_PCIE_HRPWM2_V1_8814A 0x03DC -#define REG_PCIE_HCPWM2_V1_8814A 0x03DE -#define REG_PCIE_H2C_MSG_V1_8814A 0x03E0 -#define REG_PCIE_C2H_MSG_V1_8814A 0x03E4 -#define REG_DBI_WDATA_V1_8814A 0x03E8 -#define REG_DBI_RDATA_V1_8814A 0x03EC -#define REG_DBI_FLAG_V1_8814A 0x03F0 -#define REG_MDIO_V1_8814A 0x03F4 -#define REG_PCIE_MIX_CFG_8814A 0x03F8 -#define REG_DBG_8814A 0x03FC -/* ----------------------------------------------------- - * - * 0x0400h ~ 0x047Fh Protocol Configuration - * - * ----------------------------------------------------- */ -#define REG_VOQ_INFORMATION_8814A 0x0400 -#define REG_VIQ_INFORMATION_8814A 0x0404 -#define REG_BEQ_INFORMATION_8814A 0x0408 -#define REG_BKQ_INFORMATION_8814A 0x040C -#define REG_MGQ_INFORMATION_8814A 0x0410 -#define REG_HGQ_INFORMATION_8814A 0x0414 -#define REG_BCNQ_INFORMATION_8814A 0x0418 -#define REG_TXPKT_EMPTY_8814A 0x041A -#define REG_CPU_MGQ_INFORMATION_8814A 0x041C -#define REG_FWHW_TXQ_CTRL_8814A 0x0420 -#define REG_HWSEQ_CTRL_8814A 0x0423 -#define REG_TXPKTBUF_BCNQ_BDNY_8814A 0x0424 -/* #define REG_MGQ_BDNY_8814A 0x0425 */ -#define REG_LIFETIME_EN_8814A 0x0426 -/* #define REG_FW_FREE_TAIL_8814A 0x0427 */ -#define REG_SPEC_SIFS_8814A 0x0428 -#define REG_RETRY_LIMIT_8814A 0x042A -#define REG_TXBF_CTRL_8814A 0x042C -#define REG_DARFRC_8814A 0x0430 -#define REG_RARFRC_8814A 0x0438 -#define REG_RRSR_8814A 0x0440 -#define REG_ARFR0_8814A 0x0444 -#define REG_ARFR1_8814A 0x044C -#define REG_CCK_CHECK_8814A 0x0454 -#define REG_AMPDU_MAX_TIME_8814A 0x0455 -#define REG_TXPKTBUF_BCNQ1_BDNY_8814A 0x0456 -#define REG_AMPDU_MAX_LENGTH_8814A 0x0458 -#define REG_ACQ_STOP_8814A 0x045C -#define REG_NDPA_RATE_8814A 0x045D -#define REG_TX_HANG_CTRL_8814A 0x045E -#define REG_NDPA_OPT_CTRL_8814A 0x045F -#define REG_FAST_EDCA_CTRL_8814A 0x0460 -#define REG_RD_RESP_PKT_TH_8814A 0x0463 -#define REG_CMDQ_INFO_8814A 0x0464 -#define REG_Q4_INFO_8814A 0x0468 -#define REG_Q5_INFO_8814A 0x046C -#define REG_Q6_INFO_8814A 0x0470 -#define REG_Q7_INFO_8814A 0x0474 -#define REG_WMAC_LBK_BUF_HD_8814A 0x0478 -#define REG_MGQ_PGBNDY_8814A 0x047A -#define REG_INIRTS_RATE_SEL_8814A 0x0480 -#define REG_BASIC_CFEND_RATE_8814A 0x0481 -#define REG_STBC_CFEND_RATE_8814A 0x0482 -#define REG_DATA_SC_8814A 0x0483 -#define REG_MACID_SLEEP3_8814A 0x0484 -#define REG_MACID_SLEEP1_8814A 0x0488 -#ifdef CONFIG_WOWLAN - #define REG_TXPKTBUF_IV_LOW 0x0484 - #define REG_TXPKTBUF_IV_HIGH 0x0488 -#endif /* CONFIG_WOWLAN */ -#define REG_ARFR2_8814A 0x048C -#define REG_ARFR3_8814A 0x0494 -#define REG_ARFR4_8814A 0x049C -#define REG_ARFR5_8814A 0x04A4 -#define REG_TXRPT_START_OFFSET_8814A 0x04AC -#define REG_TRYING_CNT_TH_8814A 0x04B0 -#define REG_POWER_STAGE1_8814A 0x04B4 -#define REG_POWER_STAGE2_8814A 0x04B8 -#define REG_SW_AMPDU_BURST_MODE_CTRL_8814A 0x04BC -#define REG_PKT_LIFE_TIME_8814A 0x04C0 -#define REG_PKT_BE_BK_LIFE_TIME_8814A 0x04C2 /* ?????? */ -#define REG_STBC_SETTING_8814A 0x04C4 -#define REG_STBC_8814A 0x04C5 -#define REG_QUEUE_CTRL_8814A 0x04C6 -#define REG_SINGLE_AMPDU_CTRL_8814A 0x04C7 -#define REG_PROT_MODE_CTRL_8814A 0x04C8 -#define REG_MAX_AGGR_NUM_8814A 0x04CA -#define REG_RTS_MAX_AGGR_NUM_8814A 0x04CB -#define REG_BAR_MODE_CTRL_8814A 0x04CC -#define REG_RA_TRY_RATE_AGG_LMT_8814A 0x04CF -#define REG_MACID_SLEEP2_8814A 0x04D0 -#define REG_MACID_SLEEP0_8814A 0x04D4 -#define REG_HW_SEQ0_8814A 0x04D8 -#define REG_HW_SEQ1_8814A 0x04DA -#define REG_HW_SEQ2_8814A 0x04DC -#define REG_HW_SEQ3_8814A 0x04DE -#define REG_NULL_PKT_STATUS_8814A 0x04E0 -#define REG_PTCL_ERR_STATUS_8814A 0x04E2 -#define REG_DROP_PKT_NUM_8814A 0x04EC -#define REG_PTCL_TX_RPT_8814A 0x04F0 -#define REG_Dummy_8814A 0x04FC - - -/* ----------------------------------------------------- - * - * 0x0500h ~ 0x05FFh EDCA Configuration - * - * ----------------------------------------------------- */ -#define REG_EDCA_VO_PARAM_8814A 0x0500 -#define REG_EDCA_VI_PARAM_8814A 0x0504 -#define REG_EDCA_BE_PARAM_8814A 0x0508 -#define REG_EDCA_BK_PARAM_8814A 0x050C -#define REG_BCNTCFG_8814A 0x0510 -#define REG_PIFS_8814A 0x0512 -#define REG_RDG_PIFS_8814A 0x0513 -#define REG_SIFS_CTX_8814A 0x0514 -#define REG_SIFS_TRX_8814A 0x0516 -#define REG_AGGR_BREAK_TIME_8814A 0x051A -#define REG_SLOT_8814A 0x051B -#define REG_TX_PTCL_CTRL_8814A 0x0520 -#define REG_TXPAUSE_8814A 0x0522 -#define REG_DIS_TXREQ_CLR_8814A 0x0523 -#define REG_RD_CTRL_8814A 0x0524 -/* - * Format for offset 540h-542h: - * [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. - * [7:4]: Reserved. - * [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. - * [23:20]: Reserved - * Description: - * | - * |<--Setup--|--Hold------------>| - * --------------|---------------------- - * | - * TBTT - * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. - * Described by Designer Tim and Bruce, 2011-01-14. - * */ -#define REG_TBTT_PROHIBIT_8814A 0x0540 -#define REG_RD_NAV_NXT_8814A 0x0544 -#define REG_NAV_PROT_LEN_8814A 0x0546 -#define REG_BCN_CTRL_8814A 0x0550 -#define REG_BCN_CTRL_1_8814A 0x0551 -#define REG_MBID_NUM_8814A 0x0552 -#define REG_DUAL_TSF_RST_8814A 0x0553 -#define REG_MBSSID_BCN_SPACE_8814A 0x0554 -#define REG_DRVERLYINT_8814A 0x0558 -#define REG_BCNDMATIM_8814A 0x0559 -#define REG_ATIMWND_8814A 0x055A -#define REG_USTIME_TSF_8814A 0x055C -#define REG_BCN_MAX_ERR_8814A 0x055D -#define REG_RXTSF_OFFSET_CCK_8814A 0x055E -#define REG_RXTSF_OFFSET_OFDM_8814A 0x055F -#define REG_TSFTR_8814A 0x0560 -#define REG_CTWND_8814A 0x0572 -#define REG_SECONDARY_CCA_CTRL_8814A 0x0577 /* ?????? */ -#define REG_PSTIMER_8814A 0x0580 -#define REG_TIMER0_8814A 0x0584 -#define REG_TIMER1_8814A 0x0588 -#define REG_BCN_PREDL_ITV_8814A 0x058F /* Pre download beacon interval */ -#define REG_ACMHWCTRL_8814A 0x05C0 -#define REG_P2P_RST_8814A 0x05F0 - -/* ----------------------------------------------------- - * - * 0x0600h ~ 0x07FFh WMAC Configuration - * - * ----------------------------------------------------- */ -#define REG_MAC_CR_8814A 0x0600 -#define REG_TCR_8814A 0x0604 -#define REG_RCR_8814A 0x0608 -#define REG_RX_PKT_LIMIT_8814A 0x060C -#define REG_RX_DLK_TIME_8814A 0x060D -#define REG_RX_DRVINFO_SZ_8814A 0x060F - -#define REG_MACID_8814A 0x0610 -#define REG_BSSID_8814A 0x0618 -#define REG_MAR_8814A 0x0620 -#define REG_MBIDCAMCFG_8814A 0x0628 - -#define REG_USTIME_EDCA_8814A 0x0638 -#define REG_MAC_SPEC_SIFS_8814A 0x063A -#define REG_RESP_SIFP_CCK_8814A 0x063C -#define REG_RESP_SIFS_OFDM_8814A 0x063E -#define REG_ACKTO_8814A 0x0640 -#define REG_CTS2TO_8814A 0x0641 -#define REG_EIFS_8814A 0x0642 - -#define REG_NAV_UPPER_8814A 0x0652 /* unit of 128 */ -#define REG_TRXPTCL_CTL_8814A 0x0668 - -/* Security */ -#define REG_CAMCMD_8814A 0x0670 -#define REG_CAMWRITE_8814A 0x0674 -#define REG_CAMREAD_8814A 0x0678 -#define REG_CAMDBG_8814A 0x067C -#define REG_SECCFG_8814A 0x0680 - -/* Power */ -#define REG_WOW_CTRL_8814A 0x0690 -#define REG_PS_RX_INFO_8814A 0x0692 -#define REG_UAPSD_TID_8814A 0x0693 -#define REG_WKFMCAM_NUM_8814A 0x0698 -#define REG_RXFLTMAP0_8814A 0x06A0 -#define REG_RXFLTMAP1_8814A 0x06A2 -#define REG_RXFLTMAP2_8814A 0x06A4 -#define REG_BCN_PSR_RPT_8814A 0x06A8 -#define REG_BT_COEX_TABLE_8814A 0x06C0 -#define REG_TX_DATA_RSP_RATE_8814A 0x06DE -#define REG_ASSOCIATED_BFMER0_INFO_8814A 0x06E4 -#define REG_ASSOCIATED_BFMER1_INFO_8814A 0x06EC -#define REG_CSI_RPT_PARAM_BW20_8814A 0x06F4 -#define REG_CSI_RPT_PARAM_BW40_8814A 0x06F8 -#define REG_CSI_RPT_PARAM_BW80_8814A 0x06FC - -/* Hardware Port 2 */ -#define REG_MACID1_8814A 0x0700 -#define REG_BSSID1_8814A 0x0708 -/* Hardware Port 3 */ -#define REG_MACID2_8814A 0x1620 -#define REG_BSSID2_8814A 0x1628 -/* Hardware Port 4 */ -#define REG_MACID3_8814A 0x1630 -#define REG_BSSID3_8814A 0x1638 -/* Hardware Port 5 */ -#define REG_MACID4_8814A 0x1640 -#define REG_BSSID4_8814A 0x1648 - -#define REG_ASSOCIATED_BFMEE_SEL_8814A 0x0714 -#define REG_SND_PTCL_CTRL_8814A 0x0718 -#define REG_IQ_DUMP_8814A 0x07C0 - -/**** page 19 ****/ -/* TX BeamForming */ -#define REG_BB_TXBF_ANT_SET_BF1 0x19ac -#define REG_BB_TXBF_ANT_SET_BF0 0x19b4 - -/* 0x1200h ~ 0x12FFh DDMA CTRL - * - * ----------------------------------------------------- */ -#define REG_DDMA_CH0SA 0x1200 -#define REG_DDMA_CH0DA 0x1204 -#define REG_DDMA_CH0CTRL 0x1208 -#define REG_DDMA_CH1SA 0x1210 -#define REG_DDMA_CH1DA 0x1214 -#define REG_DDMA_CH1CTRL 0x1218 -#define REG_DDMA_CH2SA 0x1220 -#define REG_DDMA_CH2DA 0x1224 -#define REG_DDMA_CH2CTRL 0x1228 -#define REG_DDMA_CH3SA 0x1230 -#define REG_DDMA_CH3DA 0x1234 -#define REG_DDMA_CH3CTRL 0x1238 -#define REG_DDMA_CH4SA 0x1240 -#define REG_DDMA_CH4DA 0x1244 -#define REG_DDMA_CH4CTRL 0x1248 -#define REG_DDMA_CH5SA 0x1250 -#define REG_DDMA_CH5DA 0x1254 -#define REG_DDMA_CH5CTRL 0x1258 -#define REG_DDMA_INT_MSK 0x12E0 -#define REG_DDMA_CHSTATUS 0x12E8 -#define REG_DDMA_CHKSUM 0x12F0 -#define REG_DDMA_MONITER 0x12FC - -#define DDMA_LEN_MASK 0x0001FFFF -#define FW_CHKSUM_DUMMY_SZ 8 -#define DDMA_CH_CHKSUM_CNT BIT(24) -#define DDMA_RST_CHKSUM_STS BIT(25) -#define DDMA_MODE_BLOCK_CPU BIT(26) -#define DDMA_CHKSUM_FAIL BIT(27) -#define DDMA_DA_W_DISABLE BIT(28) -#define DDMA_CHKSUM_EN BIT(29) -#define DDMA_CH_OWN BIT(31) - - -/* 3081 FWDL */ -#define FWDL_EN BIT0 -#define IMEM_BOOT_DL_RDY BIT1 -#define IMEM_BOOT_CHKSUM_FAIL BIT2 -#define IMEM_DL_RDY BIT3 -#define IMEM_CHKSUM_OK BIT4 -#define DMEM_DL_RDY BIT5 -#define DMEM_CHKSUM_OK BIT6 -#define EMEM_DL_RDY BIT7 -#define EMEM_CHKSUM_FAIL BIT8 -#define EMEM_TXBUF_DL_RDY BIT9 -#define EMEM_TXBUF_CHKSUM_FAIL BIT10 -#define CPU_CLK_SWITCH_BUSY BIT11 -#define CPU_CLK_SEL (BIT12 | BIT13) -#define FWDL_OK BIT14 -#define FW_INIT_RDY BIT15 -#define R_EN_BOOT_FLASH BIT20 - -#define OCPBASE_IMEM_3081 0x00000000 -#define OCPBASE_DMEM_3081 0x00200000 -#define OCPBASE_RPTBUF_3081 0x18660000 -#define OCPBASE_RXBUF2_3081 0x18680000 -#define OCPBASE_RXBUF_3081 0x18700000 -#define OCPBASE_TXBUF_3081 0x18780000 - - -#define REG_FAST_EDCA_VOVI_SETTING_8814A 0x1448 -#define REG_FAST_EDCA_BEBK_SETTING_8814A 0x144C - - -/* ----------------------------------------------------- - * */ - - -/* ----------------------------------------------------- - * - * Redifine 8192C register definition for compatibility - * - * ----------------------------------------------------- */ - -/* TODO: use these definition when using REG_xxx naming rule. - * NOTE: DO NOT Remove these definition. Use later. */ -#define EFUSE_CTRL_8814A REG_EFUSE_CTRL_8814A /* E-Fuse Control. */ -#define EFUSE_TEST_8814A REG_LDO_EFUSE_CTRL_8814A /* E-Fuse Test. */ -#define MSR_8814A (REG_CR_8814A + 2) /* Media Status register */ -#define ISR_8814A REG_HISR0_8814A -#define TSFR_8814A REG_TSFTR_8814A /* Timing Sync Function Timer Register. */ - -#define PBP_8814A REG_PBP_8814A - -/* Redifine MACID register, to compatible prior ICs. */ -#define IDR0_8814A REG_MACID_8814A /* MAC ID Register, Offset 0x0050-0x0053 */ -#define IDR4_8814A (REG_MACID_8814A + 4) /* MAC ID Register, Offset 0x0054-0x0055 */ - - -/* - * 9. Security Control Registers (Offset: ) - * */ -#define RWCAM_8814A REG_CAMCMD_8814A /* IN 8190 Data Sheet is called CAMcmd */ -#define WCAMI_8814A REG_CAMWRITE_8814A /* Software write CAM input content */ -#define RCAMO_8814A REG_CAMREAD_8814A /* Software read/write CAM config */ -#define CAMDBG_8814A REG_CAMDBG_8814A -#define SECR_8814A REG_SECCFG_8814A /* Security Configuration Register */ - - -/* ---------------------------------------------------------------------------- - * 8195 IMR/ISR bits (offset 0xB0, 8bits) - * ---------------------------------------------------------------------------- */ -#define IMR_DISABLED_8814A 0 -/* IMR DW0(0x00B0-00B3) Bit 0-31 */ -#define IMR_TIMER2_8814A BIT31 /* Timeout interrupt 2 */ -#define IMR_TIMER1_8814A BIT30 /* Timeout interrupt 1 */ -#define IMR_PSTIMEOUT_8814A BIT29 /* Power Save Time Out Interrupt */ -#define IMR_GTINT4_8814A BIT28 /* When GTIMER4 expires, this bit is set to 1 */ -#define IMR_GTINT3_8814A BIT27 /* When GTIMER3 expires, this bit is set to 1 */ -#define IMR_TXBCN0ERR_8814A BIT26 /* Transmit Beacon0 Error */ -#define IMR_TXBCN0OK_8814A BIT25 /* Transmit Beacon0 OK */ -#define IMR_TSF_BIT32_TOGGLE_8814A BIT24 /* TSF Timer BIT32 toggle indication interrupt */ -#define IMR_BCNDMAINT0_8814A BIT20 /* Beacon DMA Interrupt 0 */ -#define IMR_BCNDERR0_8814A BIT16 /* Beacon Queue DMA OK0 */ -#define IMR_HSISR_IND_ON_INT_8814A BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ -#define IMR_BCNDMAINT_E_8814A BIT14 /* Beacon DMA Interrupt Extension for Win7 */ -#define IMR_ATIMEND_8814A BIT12 /* CTWidnow End or ATIM Window End */ -#define IMR_C2HCMD_8814A BIT10 /* CPU to Host Command INT Status, Write 1 clear */ -#define IMR_CPWM2_8814A BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_CPWM_8814A BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_HIGHDOK_8814A BIT7 /* High Queue DMA OK */ -#define IMR_MGNTDOK_8814A BIT6 /* Management Queue DMA OK */ -#define IMR_BKDOK_8814A BIT5 /* AC_BK DMA OK */ -#define IMR_BEDOK_8814A BIT4 /* AC_BE DMA OK */ -#define IMR_VIDOK_8814A BIT3 /* AC_VI DMA OK */ -#define IMR_VODOK_8814A BIT2 /* AC_VO DMA OK */ -#define IMR_RDU_8814A BIT1 /* Rx Descriptor Unavailable */ -#define IMR_ROK_8814A BIT0 /* Receive DMA OK */ - -/* IMR DW1(0x00B4-00B7) Bit 0-31 */ -#define IMR_MCUERR_8814A BIT28 /* Beacon DMA Interrupt 7 */ -#define IMR_BCNDMAINT7_8814A BIT27 /* Beacon DMA Interrupt 7 */ -#define IMR_BCNDMAINT6_8814A BIT26 /* Beacon DMA Interrupt 6 */ -#define IMR_BCNDMAINT5_8814A BIT25 /* Beacon DMA Interrupt 5 */ -#define IMR_BCNDMAINT4_8814A BIT24 /* Beacon DMA Interrupt 4 */ -#define IMR_BCNDMAINT3_8814A BIT23 /* Beacon DMA Interrupt 3 */ -#define IMR_BCNDMAINT2_8814A BIT22 /* Beacon DMA Interrupt 2 */ -#define IMR_BCNDMAINT1_8814A BIT21 /* Beacon DMA Interrupt 1 */ -#define IMR_BCNDOK7_8814A BIT20 /* Beacon Queue DMA OK Interrup 7 */ -#define IMR_BCNDOK6_8814A BIT19 /* Beacon Queue DMA OK Interrup 6 */ -#define IMR_BCNDOK5_8814A BIT18 /* Beacon Queue DMA OK Interrup 5 */ -#define IMR_BCNDOK4_8814A BIT17 /* Beacon Queue DMA OK Interrup 4 */ -#define IMR_BCNDOK3_8814A BIT16 /* Beacon Queue DMA OK Interrup 3 */ -#define IMR_BCNDOK2_8814A BIT15 /* Beacon Queue DMA OK Interrup 2 */ -#define IMR_BCNDOK1_8814A BIT14 /* Beacon Queue DMA OK Interrup 1 */ -#define IMR_ATIMEND_E_8814A BIT13 /* ATIM Window End Extension for Win7 */ -#define IMR_TXERR_8814A BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ -#define IMR_RXERR_8814A BIT10 /* Rx Error Flag INT Status, Write 1 clear */ -#define IMR_TXFOVW_8814A BIT9 /* Transmit FIFO Overflow */ -#define IMR_RXFOVW_8814A BIT8 /* Receive FIFO Overflow */ - - -#ifdef CONFIG_PCI_HCI - #define IMR_TX_MASK (IMR_VODOK_8814A | IMR_VIDOK_8814A | IMR_BEDOK_8814A | IMR_BKDOK_8814A | IMR_MGNTDOK_8814A | IMR_HIGHDOK_8814A) - - #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8814A | IMR_TXBCN0OK_8814A | IMR_TXBCN0ERR_8814A | IMR_BCNDERR0_8814A) - - #define RT_AC_INT_MASKS (IMR_VIDOK_8814A | IMR_VODOK_8814A | IMR_BEDOK_8814A | IMR_BKDOK_8814A) -#endif - - -/*=================================================================== -===================================================================== -Here the register defines are for 92C. When the define is as same with 92C, -we will use the 92C's define for the consistency -So the following defines for 92C is not entire!!!!!! -===================================================================== -=====================================================================*/ - - -/* ----------------------------------------------------- - * - * 0xFE00h ~ 0xFE55h USB Configuration - * - * ----------------------------------------------------- */ - -/* 2 Special Option */ -#define USB_AGG_EN_8814A BIT(7) -#define REG_USB_HRPWM_U3 0xF052 - -#define LAST_ENTRY_OF_TX_PKT_BUFFER_8814A (2048-1) /* 20130415 KaiYuan add for 8814 */ - -#endif /* __RTL8814A_SPEC_H__ */ diff --git a/include/rtl8814a_sreset.h b/include/rtl8814a_sreset.h deleted file mode 100644 index 5d95e1f..0000000 --- a/include/rtl8814a_sreset.h +++ /dev/null @@ -1,29 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef _RTL88814A_SRESET_H_ -#define _RTL8814A_SRESET_H_ - -#include - -#ifdef DBG_CONFIG_ERROR_DETECT - extern void rtl8814_sreset_xmit_status_check(_adapter *padapter); - extern void rtl8814_sreset_linked_status_check(_adapter *padapter); -#endif -#endif diff --git a/include/rtl8814a_xmit.h b/include/rtl8814a_xmit.h deleted file mode 100755 index 099760d..0000000 --- a/include/rtl8814a_xmit.h +++ /dev/null @@ -1,310 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8814A_XMIT_H__ -#define __RTL8814A_XMIT_H__ - -typedef struct txdescriptor_8814 { - /* Offset 0 */ - u32 pktlen:16; - u32 offset:8; - u32 bmc:1; - u32 htc:1; - u32 ls:1; -} TXDESC_8814, *PTXDESC_8814; - - -#define OFFSET_SZ 0 -#define OFFSET_SHT 16 - - - -#ifdef CONFIG_SDIO_HCI - #define SET_TX_DESC_SDIO_TXSEQ_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value) -#endif /* CONFIG_SDIO_HCI */ - -/* ----------------------------------------------------------------- - * RTL8814A TX BUFFER DESC - * ----------------------------------------------------------------- - * -- Each TXBD has 4 segment. - -- For 32 bit, each segment is 8 bytes. - -- For 64 bit, each segment is 16 bytes. -*/ -#if 0 - #if 1 /* 32 bit */ - #define SET_TX_EXTBUFF_DESC_LEN_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*8), 0, 16, __Value) - #define SET_TX_EXTBUFF_DESC_ADDR_LOW_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*8)+4, 0, 32, __Value) - #else /* 64 bit */ - #define SET_TX_EXTBUFF_DESC_LEN_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*16), 0, 16, __Value) - #define SET_TX_EXTBUFF_DESC_ADDR_LOW_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*16)+4, 0, 32, __Value) - #endif - #define SET_TX_EXTBUFF_DESC_ADDR_HIGH_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*16)+8, 0, 32, __Value) -#endif -/*c2h-DWORD 2*/ -#define GET_RX_STATUS_DESC_RPT_SEL_8814A(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+8, 28, 1) - -/* ********************************************************* - * for Txfilldescroptor8814Ae, fill the desc content. */ -#if 1 /* 32 bit */ - #define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*8), 0, 16, __Valeu) - #define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*8), 31, 1, __Valeu) - #define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*8)+4, 0, 32, __Valeu) -#else /* 64 bit */ - #define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu) - #define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu) - #define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu) -#endif -#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu) - -/* ********************************************************* */ - -/* TX buffer - * ************* - * Dword 0 */ -#define SET_TX_BUFF_DESC_LEN_0_8814A(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Valeu) -#define SET_TX_BUFF_DESC_PSB_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value) -#define SET_TX_BUFF_DESC_OWN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) -#define GET_TX_BUFF_DESC_OWN_8814A(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1) - -/* Dword 1 */ -#define SET_TX_BUFF_DESC_ADDR_LOW_0_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value) -#define GET_TX_BUFF_DESC_ADDR_LOW_0_8814A(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32) -/* Dword 2 */ -#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 32, __Value) -#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8814A(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32) -/* Dword 3 */ /* RESERVED 0 */ - -#if 0 /* 64 bit */ - /* Dword 4 */ - #define SET_TX_BUFF_DESC_LEN_1_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 16, __Value) - #define SET_TX_BUFF_DESC_AMSDU_1_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 31, 1, __Value) - /* Dword 5 */ - #define SET_TX_BUFF_DESC_ADDR_LOW_1_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 32, __Value) - /* Dword 6 */ - #define SET_TX_BUFF_DESC_ADDR_HIGH_1_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 32, __Value) - /* Dword 7 */ /* RESERVED 0 */ - /* Dword 8 */ - #define SET_TX_BUFF_DESC_LEN_2_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 16, __Value) - #define SET_TX_BUFF_DESC_AMSDU_2_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 31, 1, __Value) - /* Dword 9 */ - #define SET_TX_BUFF_DESC_ADDR_LOW_2_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 32, __Value) - /* Dword 10 */ - #define SET_TX_BUFF_DESC_ADDR_HIGH_2_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value) - /* Dword 11 */ /* RESERVED 0 */ - /* Dword 12 */ - #define SET_TX_BUFF_DESC_LEN_3_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 16, __Value) - #define SET_TX_BUFF_DESC_AMSDU_3_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 31, 1, __Value) - /* Dword 13 */ - #define SET_TX_BUFF_DESC_ADDR_LOW_3_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+52, 0, 32, __Value) - /* Dword 14 */ - #define SET_TX_BUFF_DESC_ADDR_HIGH_3_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+56, 0, 32, __Value) - /* Dword 15 */ /* RESERVED 0 */ -#endif - -/* *****Desc content - * TX Info - * ************* - * Dword 0 */ -#define SET_TX_DESC_PKT_SIZE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value) -#define GET_TX_DESC_PKT_SIZE_8814A(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 0, 16) -#define SET_TX_DESC_OFFSET_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value) -#define GET_TX_DESC_OFFSET_8814A(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 16, 8) -#define SET_TX_DESC_BMC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value) -#define SET_TX_DESC_HTC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value) -#define SET_TX_DESC_LAST_SEG_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value) -#define SET_TX_DESC_LINIP_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value) -#define SET_TX_DESC_AMSDU_PAD_EN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value) -#define SET_TX_DESC_NO_ACM_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value) -#define SET_TX_DESC_GF_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value) -#define SET_TX_DESC_DISQSELSEQ_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) - -/* Dword 1 */ -#define SET_TX_DESC_MACID_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value) -#define SET_TX_DESC_QUEUE_SEL_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value) -#define SET_TX_DESC_RDG_NAV_EXT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value) -#define SET_TX_DESC_LSIG_TXOP_EN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value) -#define SET_TX_DESC_PIFS_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value) -#define SET_TX_DESC_RATE_ID_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value) -#define SET_TX_DESC_EN_DESC_ID_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value) -#define SET_TX_DESC_SEC_TYPE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value) -#define SET_TX_DESC_PKT_OFFSET_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value) -#define SET_TX_DESC_MORE_DATA_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value) -#define SET_TX_DESC_TXOP_PS_CAP_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 30, 1, __Value) -#define SET_TX_DESC_TXOP_PS_MODE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 31, 1, __Value) - - -/* Dword 2 */ -#define SET_TX_DESC_PAID_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value) -#define SET_TX_DESC_CCA_RTS_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value) -#define SET_TX_DESC_AGG_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value) -#define SET_TX_DESC_RDG_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value) -#define SET_TX_DESC_NULL_0_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value) -#define SET_TX_DESC_NULL_1_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value) -#define SET_TX_DESC_BK_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value) -#define SET_TX_DESC_MORE_FRAG_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value) -#define GET_TX_DESC_MORE_FRAG_8814A(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 17, 1) -#define SET_TX_DESC_RAW_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value) -#define SET_TX_DESC_SPE_RPT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value) -#define SET_TX_DESC_AMPDU_DENSITY_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value) -#define SET_TX_DESC_BT_NULL_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value) -#define SET_TX_DESC_GID_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value) -#define SET_TX_DESC_HW_AES_IV_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 31, 1, __Value) - - -/* Dword 3 */ -#define SET_TX_DESC_WHEADER_LEN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 5, __Value) -#define SET_TX_DESC_EARLY_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value) -#define SET_TX_DESC_HW_SSN_SEL_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value) -#define SET_TX_DESC_USE_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value) -#define SET_TX_DESC_DISABLE_RTS_FB_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value) -#define SET_TX_DESC_DISABLE_FB_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value) -#define SET_TX_DESC_CTS2SELF_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value) -#define SET_TX_DESC_RTS_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value) -#define SET_TX_DESC_HW_RTS_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value) -#define SET_TX_DESC_CHECK_EN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 1, __Value) -#define SET_TX_DESC_NAV_USE_HDR_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value) -#define SET_TX_DESC_USE_MAX_LEN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value) -#define SET_TX_DESC_MAX_AGG_NUM_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value) -#define SET_TX_DESC_NDPA_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value) -#define SET_TX_DESC_AMPDU_MAX_TIME_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value) - -/* Dword 4 */ -#define SET_TX_DESC_TX_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value) -#define SET_TX_DESC_TRY_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value) -#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value) -#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value) -#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value) -#define SET_TX_DESC_DATA_RETRY_LIMIT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value) -#define SET_TX_DESC_RTS_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value) -#define SET_TX_DESC_PCTS_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value) -#define SET_TX_DESC_PCTS_MASK_IDX_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value) - - -/* Dword 5 */ -#define SET_TX_DESC_DATA_SC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value) -#define SET_TX_DESC_DATA_SHORT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value) -#define SET_TX_DESC_DATA_BW_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value) -#define SET_TX_DESC_DATA_LDPC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value) -#define SET_TX_DESC_DATA_STBC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value) -#define SET_TX_DESC_CTROL_STBC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value) -#define SET_TX_DESC_RTS_SHORT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value) -#define SET_TX_DESC_RTS_SC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value) -#define SET_TX_DESC_SIGNALING_TA_PKT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 17, 1, __Value) -#define SET_TX_DESC_PORT_ID_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 21, 3, __Value)/* 20130415 KaiYuan add for 8814 */ -#define SET_TX_DESC_TX_ANT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 4, __Value) -#define SET_TX_DESC_TX_POWER_OFFSET_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value) - -/* Dword 6 */ -#define SET_TX_DESC_SW_DEFINE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value) -#define SET_TX_DESC_MBSSID_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value) -#define SET_TX_DESC_ANTSEL_A_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value) -#define SET_TX_DESC_ANTSEL_B_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value) -#define SET_TX_DESC_ANT_MAPA_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 2, __Value) -#define SET_TX_DESC_ANT_MAPB_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 24, 2, __Value) -#define SET_TX_DESC_ANT_MAPC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 26, 2, __Value) -#define SET_TX_DESC_ANT_MAPD_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 28, 2, __Value) - - -/* Dword 7 */ -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) - #define SET_TX_DESC_TX_BUFFER_SIZE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) -#else - #define SET_TX_DESC_TX_DESC_CHECKSUM_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) -#endif -#define SET_TX_DESC_NTX_MAP_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 20, 4, __Value) -#define SET_TX_DESC_USB_TXAGG_NUM_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) - - -/* Dword 8 */ -#define SET_TX_DESC_RTS_RC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value) -#define SET_TX_DESC_BAR_RTY_TH_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value) -#define SET_TX_DESC_DATA_RC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value) -#define SET_TX_DESC_EN_HWEXSEQ_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 14, 1, __Value) -#define SET_TX_DESC_HWSEQ_EN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) -#if (DEV_BUS_TYPE != RT_SDIO_INTERFACE) - #define SET_TX_DESC_NEXT_HEAD_PAGE_L_8814A(__pTxDesc, __Value)(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value) -#else - #define SET_TX_DESC_SDIO_SEQ_8814A(__pTxDesc, __Value)(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value) /* 20130415 KaiYuan add for 8814AS */ -#endif -#define SET_TX_DESC_TAIL_PAGE_L_8814A(__pTxDesc, __Value)(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value) - -/* Dword 9 */ -#define SET_TX_DESC_PADDING_LENGTH_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value) -#define SET_TX_DESC_TXBF_PATH_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 11, 1, __Value) -#define SET_TX_DESC_SEQ_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value) -#define SET_TX_DESC_NEXT_HEAD_PAGE_H_8814A(__pTxDesc, __Value)(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 4, __Value) -#define SET_TX_DESC_TAIL_PAGE_H_8814A(__pTxDesc, __Value)(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 28, 4, __Value) - - - -#define SET_EARLYMODE_PKTNUM_8814A(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value) -#define SET_EARLYMODE_LEN0_8814A(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value) -#define SET_EARLYMODE_LEN1_1_8814A(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value) -#define SET_EARLYMODE_LEN1_2_8814A(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value) -#define SET_EARLYMODE_LEN2_8814A(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value) -#define SET_EARLYMODE_LEN3_8814A(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value) - - -void rtl8814a_cal_txdesc_chksum(u8 *ptxdesc); -void rtl8814a_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); -void rtl8814a_fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc); -void rtl8814a_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc); -void rtl8814a_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc); -#if defined(CONFIG_CONCURRENT_MODE) - void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); -#endif - -#ifdef CONFIG_USB_HCI - s32 rtl8814au_init_xmit_priv(PADAPTER padapter); - void rtl8814au_free_xmit_priv(PADAPTER padapter); - s32 rtl8814au_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 rtl8814au_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); - s32 rtl8814au_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); - s32 rtl8814au_xmit_buf_handler(PADAPTER padapter); - void rtl8814au_xmit_tasklet(void *priv); - s32 rtl8814au_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); -#endif /* CONFIG_USB_HCI */ - -#ifdef CONFIG_PCI_HCI - s32 rtl8814ae_init_xmit_priv(PADAPTER padapter); - void rtl8814ae_free_xmit_priv(PADAPTER padapter); - struct xmit_buf *rtl8814ae_dequeue_xmitbuf(struct rtw_tx_ring *ring); - void rtl8814ae_xmitframe_resume(_adapter *padapter); - s32 rtl8814ae_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); - s32 rtl8814ae_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); - s32 rtl8814ae_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); - void rtl8814ae_xmit_tasklet(void *priv); -#endif - -void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, u8 *ptxdesc); -u8 -SCMapping_8814( - IN PADAPTER Adapter, - IN struct pkt_attrib *pattrib -); - -u8 -BWMapping_8814( - IN PADAPTER Adapter, - IN struct pkt_attrib *pattrib -); - - -#endif /* __RTL8814_XMIT_H__ */ diff --git a/include/rtl8821a_spec.h b/include/rtl8821a_spec.h deleted file mode 100644 index fc4c7ed..0000000 --- a/include/rtl8821a_spec.h +++ /dev/null @@ -1,96 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ -#ifndef __RTL8821A_SPEC_H__ -#define __RTL8821A_SPEC_H__ - -#include -/* This file should based on "hal_com_reg.h" */ -#include -/* Because 8812a and 8821a is the same serial, - * most of 8821a register definitions are the same as 8812a. */ -#include - - -/* ************************************************************ - * 8821A Regsiter offset definition - * ************************************************************ */ - -/* ************************************************************ - * MAC register - * ************************************************************ */ - -/* ----------------------------------------------------- - * 0x0000h ~ 0x00FFh System Configuration - * ----------------------------------------------------- */ - -/* ----------------------------------------------------- - * 0x0100h ~ 0x01FFh MACTOP General Configuration - * ----------------------------------------------------- */ -#define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN - -/* ----------------------------------------------------- - * 0x0200h ~ 0x027Fh TXDMA Configuration - * ----------------------------------------------------- */ - -/* ----------------------------------------------------- - * 0x0280h ~ 0x02FFh RXDMA Configuration - * ----------------------------------------------------- */ - -/* ----------------------------------------------------- - * 0x0300h ~ 0x03FFh PCIe - * ----------------------------------------------------- */ - -/* ----------------------------------------------------- - * 0x0400h ~ 0x047Fh Protocol Configuration - * ----------------------------------------------------- */ - -/* ----------------------------------------------------- - * 0x0500h ~ 0x05FFh EDCA Configuration - * ----------------------------------------------------- */ - -/* ----------------------------------------------------- - * 0x0600h ~ 0x07FFh WMAC Configuration - * ----------------------------------------------------- */ - - -/* ************************************************************ - * SDIO Bus Specification - * ************************************************************ */ - -/* ----------------------------------------------------- - * SDIO CMD Address Mapping - * ----------------------------------------------------- */ - -/* ----------------------------------------------------- - * I/O bus domain (Host) - * ----------------------------------------------------- */ - -/* ----------------------------------------------------- - * SDIO register - * ----------------------------------------------------- */ -#undef SDIO_REG_HCPWM1 -#define SDIO_REG_FREE_TXPG2 0x024 -#define SDIO_REG_HCPWM1 0x025 - - -/* ************************************************************ - * Regsiter Bit and Content definition - * ************************************************************ */ - -#endif /* __RTL8821A_SPEC_H__ */ diff --git a/include/rtl8821a_xmit.h b/include/rtl8821a_xmit.h deleted file mode 100644 index d7a97e3..0000000 --- a/include/rtl8821a_xmit.h +++ /dev/null @@ -1,178 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8821A_XMIT_H__ -#define __RTL8821A_XMIT_H__ - -#include - -typedef struct txdescriptor_8821a { - /* Offset 0 */ - u32 pktlen:16; - u32 offset:8; - u32 bmc:1; - u32 htc:1; - u32 rsvd0026:1; - u32 rsvd0027:1; - u32 linip:1; - u32 noacm:1; - u32 gf:1; - u32 rsvd0031:1; - - /* Offset 4 */ - u32 macid:7; - u32 rsvd0407:1; - u32 qsel:5; - u32 rdg_nav_ext:1; - u32 lsig_txop_en:1; - u32 pifs:1; - u32 rate_id:5; - u32 en_desc_id:1; - u32 sectype:2; - u32 pkt_offset:5; /* unit: 8 bytes */ - u32 moredata:1; - u32 txop_ps_cap:1; - u32 txop_ps_mode:1; - - /* Offset 8 */ - u32 p_aid:9; - u32 rsvd0809:1; - u32 cca_rts:2; - u32 agg_en:1; - u32 rdg_en:1; - u32 null_0:1; - u32 null_1:1; - u32 bk:1; - u32 morefrag:1; - u32 raw:1; - u32 spe_rpt:1; - u32 ampdu_density:3; - u32 bt_null:1; - u32 g_id:6; - u32 rsvd0830:2; - - /* Offset 12 */ - u32 wheader_len:4; - u32 chk_en:1; - u32 early_rate:1; - u32 hw_ssn_sel:2; - u32 userate:1; - u32 disrtsfb:1; - u32 disdatafb:1; - u32 cts2self:1; - u32 rtsen:1; - u32 hw_rts_en:1; - u32 port_id:1; - u32 navusehdr:1; - u32 use_max_len:1; - u32 max_agg_num:5; - u32 ndpa:2; - u32 ampdu_max_time:8; - - /* Offset 16 */ - u32 datarate:7; - u32 try_rate:1; - u32 data_ratefb_lmt:5; - u32 rts_ratefb_lmt:4; - u32 rty_lmt_en:1; - u32 data_rt_lmt:6; - u32 rtsrate:5; - u32 pcts_en:1; - u32 pcts_mask_idx:2; - - /* Offset 20 */ - u32 data_sc:4; - u32 data_short:1; - u32 data_bw:2; - u32 data_ldpc:1; - u32 data_stbc:2; - u32 vcs_stbc:2; - u32 rts_short:1; - u32 rts_sc:4; - u32 rsvd2016:7; - u32 tx_ant:4; - u32 txpwr_offset:3; - u32 rsvd2031:1; - - /* Offset 24 */ - u32 sw_define:12; - u32 mbssid:4; - u32 antsel_A:3; - u32 antsel_B:3; - u32 antsel_C:3; - u32 antsel_D:3; - u32 rsvd2428:4; - - /* Offset 28 */ - u32 checksum:16; - u32 rsvd2816:8; - u32 usb_txagg_num:8; - - /* Offset 32 */ - u32 rts_rc:6; - u32 bar_rty_th:2; - u32 data_rc:6; - u32 rsvd3214:1; - u32 en_hwseq:1; - u32 nextneadpage:8; - u32 tailpage:8; - - /* Offset 36 */ - u32 padding_len:11; - u32 txbf_path:1; - u32 seq:12; - u32 final_data_rate:8; -} TXDESC_8821A, *PTXDESC_8821A; - -#ifdef CONFIG_SDIO_HCI -s32 InitXmitPriv8821AS(PADAPTER padapter); -void FreeXmitPriv8821AS(PADAPTER padapter); -s32 XmitBufHandler8821AS(PADAPTER padapter); -s32 MgntXmit8821AS(PADAPTER padapter, struct xmit_frame *pmgntframe); -s32 HalXmitNoLock8821AS(PADAPTER padapter, struct xmit_frame *pxmitframe); -s32 HalXmit8821AS(PADAPTER padapter, struct xmit_frame *pxmitframe); -#ifndef CONFIG_SDIO_TX_TASKLET -thread_return XmitThread8821AS(thread_context context); -#endif /* !CONFIG_SDIO_TX_TASKLET */ -#endif /* CONFIG_SDIO_HCI */ - -#if 0 -#ifdef CONFIG_USB_HCI -s32 rtl8821au_init_xmit_priv(PADAPTER padapter); -void rtl8821au_free_xmit_priv(PADAPTER padapter); -s32 rtl8821au_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); -s32 rtl8821au_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); -s32 rtl8821au_hal_xmitframe_enqueue(PADAPTER padapter, struct xmit_frame *pxmitframe); -s32 rtl8821au_xmit_buf_handler(PADAPTER padapter); -void rtl8821au_xmit_tasklet(void *priv); -s32 rtl8821au_xmitframe_complete(PADAPTER padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); -#endif /* CONFIG_USB_HCI */ - -#ifdef CONFIG_PCI_HCI -s32 rtl8821e_init_xmit_priv(PADAPTER padapter); -void rtl8821e_free_xmit_priv(PADAPTER padapter); -struct xmit_buf *rtl8821e_dequeue_xmitbuf(struct rtw_tx_ring *ring); -void rtl8821e_xmitframe_resume(PADAPTER padapter); -s32 rtl8821e_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); -s32 rtl8821e_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); -void rtl8821e_xmit_tasklet(void *priv); -#endif /* CONFIG_PCI_HCI */ -#endif - -#endif /* __RTL8821_XMIT_H__ */ diff --git a/include/rtl8821c_dm.h b/include/rtl8821c_dm.h deleted file mode 100644 index 6cdcb0a..0000000 --- a/include/rtl8821c_dm.h +++ /dev/null @@ -1,30 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8812C_DM_H__ -#define __RTL8812C_DM_H__ - -void rtl8821c_phy_init_dm_priv(PADAPTER); -void rtl8821c_phy_deinit_dm_priv(PADAPTER); -void rtl8821c_phy_init_haldm(PADAPTER); -void rtl8821c_phy_haldm_watchdog(PADAPTER); -void rtl8821c_phy_haldm_in_lps(PADAPTER); -void rtl8821c_phy_haldm_watchdog_in_lps(PADAPTER); - -#endif diff --git a/include/rtl8821c_hal.h b/include/rtl8821c_hal.h deleted file mode 100644 index fd6586e..0000000 --- a/include/rtl8821c_hal.h +++ /dev/null @@ -1,86 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef _RTL8821C_HAL_H_ -#define _RTL8821C_HAL_H_ - -#include /* BIT(x) */ -#include "../hal/halmac/halmac_api.h" /* MAC REG definition */ -#include "hal_data.h" -#include "rtl8821c_spec.h" -#include "../hal/rtl8821c/hal8821c_fw.h" - -#ifdef CONFIG_USB_HCI -#include -#endif -#ifdef CONFIG_SDIO_HCI -#include -#endif -#ifdef CONFIG_PCI_HCI -#include -#endif - -#ifdef CONFIG_SUPPORT_TRX_SHARED -#define FIFO_BLOCK_SIZE 32768 /*@Block size = 32K*/ -#define RX_FIFO_EXPANDING (1 * FIFO_BLOCK_SIZE) -#else -#define RX_FIFO_EXPANDING 0 -#endif - - -#if defined(CONFIG_USB_HCI) - - #ifndef MAX_RECVBUF_SZ - #ifndef CONFIG_MINIMAL_MEMORY_USAGE - #ifdef CONFIG_PLATFORM_MSTAR - #define MAX_RECVBUF_SZ (8192 + RX_FIFO_EXPANDING) /* 8K */ - #else - /* 8821C - RX FIFO :16K ,for RX agg DMA mode = 16K, Rx agg USB mode could large than 16k*/ - #define MAX_RECVBUF_SZ (HALMAC_RX_FIFO_SIZE_8821C + RX_FIFO_EXPANDING) - #endif - /*#define MAX_RECVBUF_SZ_8821C (24576)*/ /* 24k*/ - /*#define MAX_RECVBUF_SZ_8821C (20480)*/ /*20K*/ - /*#define MAX_RECVBUF_SZ_8821C (10240) */ /*10K*/ - /*#define MAX_RECVBUF_SZ_8821C (15360)*/ /*15k < 16k*/ - /*#define MAX_RECVBUF_SZ_8821C (8192+1024)*/ /* 8K+1k*/ - #else - #define MAX_RECVBUF_SZ (4096 + RX_FIFO_EXPANDING) /* about 4K */ - #endif - #endif/* !MAX_RECVBUF_SZ*/ - -#elif defined(CONFIG_PCI_HCI) - /*#ifndef CONFIG_MINIMAL_MEMORY_USAGE - #define MAX_RECVBUF_SZ (9100) - #else*/ - #define MAX_RECVBUF_SZ (4096 + RX_FIFO_EXPANDING) /* about 4K */ - /*#endif*/ - -#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - #define MAX_RECVBUF_SZ (HALMAC_RX_FIFO_SIZE_8821C + RX_FIFO_EXPANDING) -#endif - -void init_hal_spec_rtl8821c(PADAPTER); -/* MP Functions */ -#ifdef CONFIG_MP_INCLUDED -void rtl8821c_phy_init_haldm(PADAPTER); /* rtw_mp.c */ -void rtl8821c_prepare_mp_txdesc(PADAPTER, struct mp_priv *); /* rtw_mp.c */ -void rtl8821c_mp_config_rfpath(PADAPTER); /* hal_mp.c */ -#endif - -#endif /* _RTL8821C_HAL_H_ */ diff --git a/include/rtl8821c_spec.h b/include/rtl8821c_spec.h deleted file mode 100644 index 005b033..0000000 --- a/include/rtl8821c_spec.h +++ /dev/null @@ -1,195 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ -#ifndef __RTL8821C_SPEC_H__ -#define __RTL8821C_SPEC_H__ - -#define EFUSE_MAP_SIZE HALMAC_EFUSE_SIZE_8821C - -/* - * MAC Register definition - */ -#define REG_AFE_XTAL_CTRL REG_AFE_CTRL1_8821C /* hal_com.c & phydm */ -#define REG_AFE_PLL_CTRL REG_AFE_CTRL2_8821C /* hal_com.c & phydm */ -#define REG_MAC_PHY_CTRL REG_AFE_CTRL3_8821C /* phydm only */ -#define REG_LEDCFG0 REG_LED_CFG_8821C /* rtw_mp.c */ -#define MSR (REG_CR_8821C + 2) /* rtw_mp.c */ -#define MSR1 REG_CR_EXT_8821C /* rtw_mp.c & hal_com.c */ -#define REG_C2HEVT_MSG_NORMAL 0x1A0 /* hal_com.c */ -#define REG_C2HEVT_CLEAR 0x1AF /* hal_com.c */ -#define REG_BCN_CTRL_1 REG_BCN_CTRL_CLINT0_8821C/* hal_com.c */ -#define REG_TSFTR1 REG_FREERUN_CNT_8821C /* hal_com.c */ -#define REG_RXFLTMAP2 REG_RXFLTMAP_8821C /* rtw_mp.c */ -#define REG_WOWLAN_WAKE_REASON 0x01C7 - -/* RXERR_RPT, for rtw_mp.c */ -#define RXERR_TYPE_OFDM_PPDU 0 -#define RXERR_TYPE_OFDM_FALSE_ALARM 2 -#define RXERR_TYPE_OFDM_MPDU_OK 0 -#define RXERR_TYPE_OFDM_MPDU_FAIL 1 -#define RXERR_TYPE_CCK_PPDU 3 -#define RXERR_TYPE_CCK_FALSE_ALARM 5 -#define RXERR_TYPE_CCK_MPDU_OK 3 -#define RXERR_TYPE_CCK_MPDU_FAIL 4 -#define RXERR_TYPE_HT_PPDU 8 -#define RXERR_TYPE_HT_FALSE_ALARM 9 -#define RXERR_TYPE_HT_MPDU_TOTAL 6 -#define RXERR_TYPE_HT_MPDU_OK 6 -#define RXERR_TYPE_HT_MPDU_FAIL 7 -#define RXERR_TYPE_RX_FULL_DROP 10 - -#define RXERR_COUNTER_MASK BIT_MASK_RPT_COUNTER_8821C -#define RXERR_RPT_RST BIT_RXERR_RPT_RST_8821C -#define _RXERR_RPT_SEL(type) (BIT_RXERR_RPT_SEL_V1_3_0_8821C(type) \ - | ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8821C : 0)) - -/* - * BB Register definition - */ -#define rPMAC_Reset 0x100 /* hal_mp.c */ - -#define rFPGA0_RFMOD 0x800 -#define rFPGA0_TxInfo 0x804 -#define rOFDMCCKEN_Jaguar 0x808 /* hal_mp.c */ -#define rFPGA0_TxGainStage 0x80C /* phydm only */ -#define rFPGA0_XA_HSSIParameter1 0x820 /* hal_mp.c */ -#define rFPGA0_XA_HSSIParameter2 0x824 /* hal_mp.c */ -#define rFPGA0_XB_HSSIParameter1 0x828 /* hal_mp.c */ -#define rFPGA0_XB_HSSIParameter2 0x82C /* hal_mp.c */ -#define rTxAGC_B_Rate18_06 0x830 -#define rTxAGC_B_Rate54_24 0x834 -#define rTxAGC_B_CCK1_55_Mcs32 0x838 -#define rCCAonSec_Jaguar 0x838 /* hal_mp.c */ -#define rTxAGC_B_Mcs03_Mcs00 0x83C -#define rTxAGC_B_Mcs07_Mcs04 0x848 -#define rTxAGC_B_Mcs11_Mcs08 0x84C -#define rFPGA0_XA_RFInterfaceOE 0x860 -#define rFPGA0_XB_RFInterfaceOE 0x864 -#define rTxAGC_B_Mcs15_Mcs12 0x868 -#define rTxAGC_B_CCK11_A_CCK2_11 0x86C -#define rFPGA0_XAB_RFInterfaceSW 0x870 -#define rFPGA0_XAB_RFParameter 0x878 -#define rFPGA0_AnalogParameter4 0x88C /* hal_mp.c & phydm */ -#define rFPGA0_XB_LSSIReadBack 0x8A4 /* phydm */ -#define rHSSIRead_Jaguar 0x8B0 /* RF read addr (rtl8821c_phy.c) */ - -#define rC_TxScale_Jaguar2 0x181C /* Pah_C TX scaling factor (hal_mp.c) */ -#define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C (hal_mp.c) */ - -#define rFPGA1_TxInfo 0x90C /* hal_mp.c */ -#define rSingleTone_ContTx_Jaguar 0x914 /* hal_mp.c */ - -#define rCCK0_System 0xA00 -#define rCCK0_AFESetting 0xA04 - -#define rCCK0_DSPParameter2 0xA1C -#define rCCK0_TxFilter1 0xA20 -#define rCCK0_TxFilter2 0xA24 -#define rCCK0_DebugPort 0xA28 -#define rCCK0_FalseAlarmReport 0xA2C - -#define rD_TxScale_Jaguar2 0x1A1C /* Path_D TX scaling factor (hal_mp.c) */ -#define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D (hal_mp.c) */ - -#define rOFDM0_TRxPathEnable 0xC04 -#define rOFDM0_TRMuxPar 0xC08 -#define rA_TxScale_Jaguar 0xC1C /* Pah_A TX scaling factor (hal_mp.c) */ -#define rOFDM0_RxDetector1 0xC30 /* rtw_mp.c */ -#define rOFDM0_ECCAThreshold 0xC4C /* phydm only */ -#define rOFDM0_XAAGCCore1 0xC50 /* phydm only */ -#define rA_IGI_Jaguar 0xC50 /* Initial Gain for path-A (hal_mp.c) */ -#define rOFDM0_XBAGCCore1 0xC58 /* phydm only */ -#define rOFDM0_XATxIQImbalance 0xC80 /* phydm only */ -#define rA_LSSIWrite_Jaguar 0xC90 /* RF write addr, LSSI Parameter (rtl8821c_phy.c) */ -#define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */ - -#define rOFDM1_LSTF 0xD00 -#define rOFDM1_TRxPathEnable 0xD04 /* hal_mp.c */ -#define rA_PIRead_Jaguar 0xD04 /* RF readback with PI (rtl8821c_phy.c) */ -#define rA_SIRead_Jaguar 0xD08 /* RF readback with SI (rtl8821c_phy.c) */ -#define rB_PIRead_Jaguar 0xD44 /* RF readback with PI (rtl8821c_phy.c) */ -#define rB_SIRead_Jaguar 0xD48 /* RF readback with SI (rtl8821c_phy.c) */ - -#define rTxAGC_A_Rate18_06 0xE00 -#define rTxAGC_A_Rate54_24 0xE04 -#define rTxAGC_A_CCK1_Mcs32 0xE08 -#define rTxAGC_A_Mcs03_Mcs00 0xE10 -#define rTxAGC_A_Mcs07_Mcs04 0xE14 -#define rTxAGC_A_Mcs11_Mcs08 0xE18 -#define rTxAGC_A_Mcs15_Mcs12 0xE1C -#define rB_TxScale_Jaguar 0xE1C /* Path_B TX scaling factor (hal_mp.c) */ -#define rB_IGI_Jaguar 0xE50 /* Initial Gain for path-B (hal_mp.c) */ -#define rB_LSSIWrite_Jaguar 0xE90 /* RF write addr, LSSI Parameter (rtl8821c_phy.c) */ -#define rB_RFE_Pinmux_Jaguar 0xEB0 /* hal_mp.c */ - -/* Page1(0x100) */ -#define bBBResetB 0x100 - -/* Page8(0x800) */ -#define bCCKEn 0x1000000 -#define bOFDMEn 0x2000000 -/* Reg 0x80C rFPGA0_TxGainStage */ -#define bXBTxAGC 0xF00 -#define bXCTxAGC 0xF000 -#define bXDTxAGC 0xF0000 - -/* PageA(0xA00) */ -#define bCCKBBMode 0x3 - -#define bCCKScramble 0x8 -#define bCCKTxRate 0x3000 - -/* General */ -#define bMaskByte0 0xFF /* mp, rtw_odm.c & phydm */ -#define bMaskByte1 0xFF00 /* hal_mp.c & phydm */ -#define bMaskByte2 0xFF0000 /* hal_mp.c & phydm */ -#define bMaskByte3 0xFF000000 /* hal_mp.c & phydm */ -#define bMaskHWord 0xFFFF0000 /* hal_com.c, rtw_mp.c */ -#define bMaskLWord 0x0000FFFF /* mp, hal_com.c & phydm */ -#define bMaskDWord 0xFFFFFFFF /* mp, hal, rtw_odm.c & phydm */ - -#define bEnable 0x1 /* hal_mp.c, rtw_mp.c */ -#define bDisable 0x0 /* rtw_mp.c */ - -#define MAX_STALL_TIME 50 /* unit: us, hal_com_phycfg.c */ - -#define Rx_Smooth_Factor 20 /* phydm only */ - -/* - * RF Register definition - */ -#define RF_AC 0x00 -#define RF_AC_Jaguar 0x00 /* hal_mp.c */ -#define RF_CHNLBW 0x18 /* rtl8821c_phy.c */ -#define RF_0x52 0x52 - -struct hw_port_reg { - u32 net_type; /*reg_offset*/ - u8 net_type_shift; - u32 macaddr; /*reg_offset*/ - u32 bssid; /*reg_offset*/ - u32 bcn_ctl; /*reg_offset*/ - u32 tsf_rst; /*reg_offset*/ - u8 tsf_rst_bit; - u32 bcn_space; /*reg_offset*/ - u8 bcn_space_shift; - u16 bcn_space_mask; - u32 ps_aid; /*reg_offset*/ -}; - -#endif /* __RTL8192E_SPEC_H__ */ diff --git a/include/rtl8821ce_hal.h b/include/rtl8821ce_hal.h deleted file mode 100755 index c6334bd..0000000 --- a/include/rtl8821ce_hal.h +++ /dev/null @@ -1,28 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef _RTL8821CE_HAL_H_ -#define _RTL8821CE_HAL_H_ - -#include /* PADAPTER */ - -/* rtl8821ce_ops.c */ -void rtl8821ce_set_hal_ops(PADAPTER); - -#endif /* _RTL8821CE_HAL_H_ */ diff --git a/include/rtl8821cs_hal.h b/include/rtl8821cs_hal.h deleted file mode 100644 index 97df6e9..0000000 --- a/include/rtl8821cs_hal.h +++ /dev/null @@ -1,28 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef _RTL8821CS_HAL_H_ -#define _RTL8821CS_HAL_H_ - -#include /* PADAPTER */ - -/* rtl8821cs_ops.c */ -u8 rtl8821cs_set_hal_ops(PADAPTER); - -#endif /* _RTL8821CS_HAL_H_ */ diff --git a/include/rtl8821cu_hal.h b/include/rtl8821cu_hal.h deleted file mode 100644 index 63c25a8..0000000 --- a/include/rtl8821cu_hal.h +++ /dev/null @@ -1,29 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2016 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef _RTL8821CU_HAL_H_ -#define _RTL8821CU_HAL_H_ - -#include /* PADAPTER */ - -/* rtl8821cu_ops.c */ -u8 rtl8821cu_set_hal_ops(PADAPTER); -void rtl8821cu_set_hw_type(struct dvobj_priv *pdvobj); - -#endif /* _RTL8821CU_HAL_H_ */ diff --git a/include/rtl8822b_hal.h b/include/rtl8822b_hal.h deleted file mode 100644 index 191dd6f..0000000 --- a/include/rtl8822b_hal.h +++ /dev/null @@ -1,218 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef _RTL8822B_HAL_H_ -#define _RTL8822B_HAL_H_ - -#include /* BIT(x) */ -#include /* PADAPTER */ -#include "../hal/halmac/halmac_api.h" /* MAC REG definition */ - - -#define MAX_RECVBUF_SZ HALMAC_RX_FIFO_SIZE_8822B - -/* - * MAC Register definition - */ -#define REG_AFE_XTAL_CTRL REG_AFE_CTRL1_8822B /* hal_com.c & phydm */ -#define REG_AFE_PLL_CTRL REG_AFE_CTRL2_8822B /* hal_com.c & phydm */ -#define REG_MAC_PHY_CTRL REG_AFE_CTRL3_8822B /* phydm only */ -#define REG_LEDCFG0 REG_LED_CFG_8822B /* rtw_mp.c */ -#define MSR (REG_CR_8822B + 2) /* rtw_mp.c & hal_com.c */ -#define MSR1 REG_CR_EXT_8822B /* rtw_mp.c & hal_com.c */ -#define REG_C2HEVT_MSG_NORMAL 0x1A0 /* hal_com.c */ -#define REG_C2HEVT_CLEAR 0x1AF /* hal_com.c */ -#define REG_BCN_CTRL_1 REG_BCN_CTRL_CLINT0_8822B /* hal_com.c */ -#define REG_TSFTR1 REG_FREERUN_CNT_8822B /* hal_com.c */ -#define REG_RXFLTMAP2 REG_RXFLTMAP_8822B /* rtw_mp.c */ -#define REG_WOWLAN_WAKE_REASON 0x01C7 /* hal_com.c */ -#define REG_GPIO_PIN_CTRL_2 REG_GPIO_EXT_CTRL_8822B /* hal_com.c */ - -/* RXERR_RPT, for rtw_mp.c */ -#define RXERR_TYPE_OFDM_PPDU 0 -#define RXERR_TYPE_OFDM_FALSE_ALARM 2 -#define RXERR_TYPE_OFDM_MPDU_OK 0 -#define RXERR_TYPE_OFDM_MPDU_FAIL 1 -#define RXERR_TYPE_CCK_PPDU 3 -#define RXERR_TYPE_CCK_FALSE_ALARM 5 -#define RXERR_TYPE_CCK_MPDU_OK 3 -#define RXERR_TYPE_CCK_MPDU_FAIL 4 -#define RXERR_TYPE_HT_PPDU 8 -#define RXERR_TYPE_HT_FALSE_ALARM 9 -#define RXERR_TYPE_HT_MPDU_TOTAL 6 -#define RXERR_TYPE_HT_MPDU_OK 6 -#define RXERR_TYPE_HT_MPDU_FAIL 7 -#define RXERR_TYPE_RX_FULL_DROP 10 - -#define RXERR_COUNTER_MASK BIT_MASK_RPT_COUNTER_8822B -#define RXERR_RPT_RST BIT_RXERR_RPT_RST_8822B -#define _RXERR_RPT_SEL(type) (BIT_RXERR_RPT_SEL_V1_3_0_8822B(type) \ - | ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8822B : 0)) - -/* - * BB Register definition - */ -#define rPMAC_Reset 0x100 /* hal_mp.c */ - -#define rFPGA0_RFMOD 0x800 -#define rFPGA0_TxInfo 0x804 -#define rOFDMCCKEN_Jaguar 0x808 /* hal_mp.c */ -#define rFPGA0_TxGainStage 0x80C /* phydm only */ -#define rFPGA0_XA_HSSIParameter1 0x820 /* hal_mp.c */ -#define rFPGA0_XA_HSSIParameter2 0x824 /* hal_mp.c */ -#define rFPGA0_XB_HSSIParameter1 0x828 /* hal_mp.c */ -#define rFPGA0_XB_HSSIParameter2 0x82C /* hal_mp.c */ -#define rTxAGC_B_Rate18_06 0x830 -#define rTxAGC_B_Rate54_24 0x834 -#define rTxAGC_B_CCK1_55_Mcs32 0x838 -#define rCCAonSec_Jaguar 0x838 /* hal_mp.c */ -#define rTxAGC_B_Mcs03_Mcs00 0x83C -#define rTxAGC_B_Mcs07_Mcs04 0x848 -#define rTxAGC_B_Mcs11_Mcs08 0x84C -#define rFPGA0_XA_RFInterfaceOE 0x860 -#define rFPGA0_XB_RFInterfaceOE 0x864 -#define rTxAGC_B_Mcs15_Mcs12 0x868 -#define rTxAGC_B_CCK11_A_CCK2_11 0x86C -#define rFPGA0_XAB_RFInterfaceSW 0x870 -#define rFPGA0_XAB_RFParameter 0x878 -#define rFPGA0_AnalogParameter4 0x88C /* hal_mp.c & phydm */ -#define rFPGA0_XB_LSSIReadBack 0x8A4 /* phydm */ -#define rHSSIRead_Jaguar 0x8B0 /* RF read addr (rtl8822b_phy.c) */ - -#define rC_TxScale_Jaguar2 0x181C /* Pah_C TX scaling factor (hal_mp.c) */ -#define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C (hal_mp.c) */ - -#define rFPGA1_TxInfo 0x90C /* hal_mp.c */ -#define rSingleTone_ContTx_Jaguar 0x914 /* hal_mp.c */ -/* TX BeamForming */ -#define REG_BB_TX_PATH_SEL_1_8822B 0x93C /* rtl8822b_phy.c */ -#define REG_BB_TX_PATH_SEL_2_8822B 0x940 /* rtl8822b_phy.c */ - -/* TX BeamForming */ -#define REG_BB_TXBF_ANT_SET_BF1_8822B 0x19AC /* rtl8822b_phy.c */ -#define REG_BB_TXBF_ANT_SET_BF0_8822B 0x19B4 /* rtl8822b_phy.c */ - -#define rCCK0_System 0xA00 -#define rCCK0_AFESetting 0xA04 - -#define rCCK0_DSPParameter2 0xA1C -#define rCCK0_TxFilter1 0xA20 -#define rCCK0_TxFilter2 0xA24 -#define rCCK0_DebugPort 0xA28 -#define rCCK0_FalseAlarmReport 0xA2C - -#define rD_TxScale_Jaguar2 0x1A1C /* Path_D TX scaling factor (hal_mp.c) */ -#define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D (hal_mp.c) */ - -#define rOFDM0_TRxPathEnable 0xC04 -#define rOFDM0_TRMuxPar 0xC08 -#define rA_TxScale_Jaguar 0xC1C /* Pah_A TX scaling factor (hal_mp.c) */ -#define rOFDM0_RxDetector1 0xC30 /* rtw_mp.c */ -#define rOFDM0_ECCAThreshold 0xC4C /* phydm only */ -#define rOFDM0_XAAGCCore1 0xC50 /* phydm only */ -#define rA_IGI_Jaguar 0xC50 /* Initial Gain for path-A (hal_mp.c) */ -#define rOFDM0_XBAGCCore1 0xC58 /* phydm only */ -#define rOFDM0_XATxIQImbalance 0xC80 /* phydm only */ -#define rA_LSSIWrite_Jaguar 0xC90 /* RF write addr, LSSI Parameter (rtl8822b_phy.c) */ -#define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */ - -#define rOFDM1_LSTF 0xD00 -#define rOFDM1_TRxPathEnable 0xD04 /* hal_mp.c */ -#define rA_PIRead_Jaguar 0xD04 /* RF readback with PI (rtl8822b_phy.c) */ -#define rA_SIRead_Jaguar 0xD08 /* RF readback with SI (rtl8822b_phy.c) */ -#define rB_PIRead_Jaguar 0xD44 /* RF readback with PI (rtl8822b_phy.c) */ -#define rB_SIRead_Jaguar 0xD48 /* RF readback with SI (rtl8822b_phy.c) */ - -#define rTxAGC_A_Rate18_06 0xE00 -#define rTxAGC_A_Rate54_24 0xE04 -#define rTxAGC_A_CCK1_Mcs32 0xE08 -#define rTxAGC_A_Mcs03_Mcs00 0xE10 -#define rTxAGC_A_Mcs07_Mcs04 0xE14 -#define rTxAGC_A_Mcs11_Mcs08 0xE18 -#define rTxAGC_A_Mcs15_Mcs12 0xE1C -#define rB_TxScale_Jaguar 0xE1C /* Path_B TX scaling factor (hal_mp.c) */ -#define rB_IGI_Jaguar 0xE50 /* Initial Gain for path-B (hal_mp.c) */ -#define rB_LSSIWrite_Jaguar 0xE90 /* RF write addr, LSSI Parameter (rtl8822b_phy.c) */ -#define rB_RFE_Pinmux_Jaguar 0xEB0 /* hal_mp.c */ - -/* Page1(0x100) */ -#define bBBResetB 0x100 - -/* Page8(0x800) */ -#define bCCKEn 0x1000000 -#define bOFDMEn 0x2000000 -/* Reg 0x80C rFPGA0_TxGainStage */ -#define bXBTxAGC 0xF00 -#define bXCTxAGC 0xF000 -#define bXDTxAGC 0xF0000 - -/* PageA(0xA00) */ -#define bCCKBBMode 0x3 - -#define bCCKScramble 0x8 -#define bCCKTxRate 0x3000 - -/* General */ -#define bMaskByte0 0xFF /* mp, rtw_odm.c & phydm */ -#define bMaskByte1 0xFF00 /* hal_mp.c & phydm */ -#define bMaskByte2 0xFF0000 /* hal_mp.c & phydm */ -#define bMaskByte3 0xFF000000 /* hal_mp.c & phydm */ -#define bMaskHWord 0xFFFF0000 /* hal_com.c, rtw_mp.c */ -#define bMaskLWord 0x0000FFFF /* mp, hal_com.c & phydm */ -#define bMaskDWord 0xFFFFFFFF /* mp, hal, rtw_odm.c & phydm */ - -#define bEnable 0x1 /* hal_mp.c, rtw_mp.c */ -#define bDisable 0x0 /* rtw_mp.c */ - -#define MAX_STALL_TIME 50 /* unit: us, hal_com_phycfg.c */ - -#define Rx_Smooth_Factor 20 /* phydm only */ - -/* - * RF Register definition - */ -#define RF_AC 0x00 -#define RF_AC_Jaguar 0x00 /* hal_mp.c */ -#define RF_CHNLBW 0x18 /* rtl8822b_phy.c */ -#define RF_ModeTableAddr 0x30 /* rtl8822b_phy.c */ -#define RF_ModeTableData0 0x31 /* rtl8822b_phy.c */ -#define RF_ModeTableData1 0x32 /* rtl8822b_phy.c */ -#define RF_0x52 0x52 -#define RF_WeLut_Jaguar 0xEF /* rtl8822b_phy.c */ - -/* General Functions */ -void rtl8822b_init_hal_spec(PADAPTER); /* hal/hal_com.c */ - -#ifdef CONFIG_MP_INCLUDED -/* MP Functions */ -#include /* struct mp_priv */ -void rtl8822b_phy_init_haldm(PADAPTER); /* rtw_mp.c */ -void rtl8822b_prepare_mp_txdesc(PADAPTER, struct mp_priv *); /* rtw_mp.c */ -void rtl8822b_mp_config_rfpath(PADAPTER); /* hal_mp.c */ -#endif - -#ifdef CONFIG_USB_HCI -#include -#elif defined(CONFIG_SDIO_HCI) -#include -#elif defined(CONFIG_PCI_HCI) -#include -#endif - -#endif /* _RTL8822B_HAL_H_ */ diff --git a/include/rtl8822be_hal.h b/include/rtl8822be_hal.h deleted file mode 100755 index 8379fab..0000000 --- a/include/rtl8822be_hal.h +++ /dev/null @@ -1,30 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef _RTL8822BE_HAL_H_ -#define _RTL8822BE_HAL_H_ - -#include /* PADAPTER */ - -#define RT_BCN_INT_MASKS (BIT20 | BIT25 | BIT26 | BIT16) - -/* rtl8822be_ops.c */ -void UpdateInterruptMask8822BE(PADAPTER, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1); - -#endif /* _RTL8822BE_HAL_H_ */ diff --git a/include/rtl8822bs_hal.h b/include/rtl8822bs_hal.h deleted file mode 100644 index 313036d..0000000 --- a/include/rtl8822bs_hal.h +++ /dev/null @@ -1,32 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef _RTL8822BS_HAL_H_ -#define _RTL8822BS_HAL_H_ - -#include /* PADAPTER */ - -/* rtl8822bs_ops.c */ -void rtl8822bs_set_hal_ops(PADAPTER); - -/* rtl8822bs_xmit.c */ -s32 rtl8822bs_dequeue_writeport(PADAPTER); -#define _dequeue_writeport(a) rtl8822bs_dequeue_writeport(a) - -#endif /* _RTL8822BS_HAL_H_ */ diff --git a/include/rtl8822bu_hal.h b/include/rtl8822bu_hal.h deleted file mode 100644 index 4f1af49..0000000 --- a/include/rtl8822bu_hal.h +++ /dev/null @@ -1,59 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef _RTL8822BU_HAL_H_ -#define _RTL8822BU_HAL_H_ - -#ifdef CONFIG_USB_HCI - #include /* PADAPTER */ - - #ifdef CONFIG_USB_HCI - #ifdef USB_PACKET_OFFSET_SZ - #define PACKET_OFFSET_SZ (USB_PACKET_OFFSET_SZ) - #else - #define PACKET_OFFSET_SZ (8) - #endif - #define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ) - #endif - - /* undefine MAX_RECVBUF_SZ from rtl8822b_hal.h */ - #ifdef MAX_RECVBUF_SZ - #undef MAX_RECVBUF_SZ - #endif - - /* recv_buffer must be large than usb agg size */ - #ifndef MAX_RECVBUF_SZ - #ifndef CONFIG_MINIMAL_MEMORY_USAGE - #define MAX_RECVBUF_SZ (32768) - #else - #define MAX_RECVBUF_SZ (4000) - #endif - #endif /* !MAX_RECVBUF_SZ */ - - /* rtl8822bu_ops.c */ - void rtl8822bu_set_hal_ops(PADAPTER padapter); - void rtl8822bu_set_hw_type(struct dvobj_priv *pdvobj); - - /* rtl8822bu_io.c */ - void rtl8822bu_set_intf_ops(struct _io_ops *pops); - -#endif /* CONFIG_USB_HCI */ - - -#endif /* _RTL8822BU_HAL_H_ */