mirror of
https://github.com/lwfinger/rtl8188eu.git
synced 2025-06-23 08:34:20 +00:00
rtl8188eu: Backport kernel version
This driver was added to the kernel with version 3.12. The changes in that version are now brought back to the GitHub repo. Essentually all of the code is updated. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
parent
868a407435
commit
19db43ecbd
89 changed files with 2026 additions and 5957 deletions
298
hal/odm.c
298
hal/odm.c
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@ -540,51 +540,6 @@ void odm_CmnInfoUpdate_Debug(struct odm_dm_struct *pDM_Odm)
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min=%d\n", pDM_Odm->RSSI_Min));
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}
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/* 3============================================================ */
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/* 3 DIG */
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/* 3============================================================ */
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/*-----------------------------------------------------------------------------
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* Function: odm_DIGInit()
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*
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* Overview: Set DIG scheme init value.
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*
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* Input: NONE
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*
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* Output: NONE
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*
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* Return: NONE
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*
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* Revised History:
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* When Who Remark
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*
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*---------------------------------------------------------------------------*/
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static void ODM_ChangeDynamicInitGainThresh(struct odm_dm_struct *pDM_Odm, u32 DM_Type, u32 DM_Value)
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{
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struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
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if (DM_Type == DM_DIG_THRESH_HIGH) {
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pDM_DigTable->RssiHighThresh = DM_Value;
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} else if (DM_Type == DM_DIG_THRESH_LOW) {
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pDM_DigTable->RssiLowThresh = DM_Value;
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} else if (DM_Type == RT_TYPE_ENABLE) {
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pDM_DigTable->Dig_Enable_Flag = true;
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} else if (DM_Type == RT_TYPE_DISABLE) {
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pDM_DigTable->Dig_Enable_Flag = false;
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} else if (DM_Type == RT_TYPE_BACKOFF) {
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if (DM_Value > 30)
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DM_Value = 30;
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pDM_DigTable->BackoffVal = (u8)DM_Value;
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} else if (DM_Type == RT_TYPE_RX_GAIN_MIN) {
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if (DM_Value == 0)
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DM_Value = 0x1;
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pDM_DigTable->rx_gain_range_min = (u8)DM_Value;
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} else if (DM_Type == RT_TYPE_RX_GAIN_MAX) {
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if (DM_Value > 0x50)
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DM_Value = 0x50;
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pDM_DigTable->rx_gain_range_max = (u8)DM_Value;
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}
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} /* DM_ChangeDynamicInitGainThresh */
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static int getIGIForDiff(int value_IGI)
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{
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#define ONERCCA_LOW_TH 0x30
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@ -1470,39 +1425,6 @@ void odm_DynamicTxPowerInit(struct odm_dm_struct *pDM_Odm)
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pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
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}
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static void odm_DynamicTxPowerSavePowerIndex(struct odm_dm_struct *pDM_Odm)
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{
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u8 index;
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u32 Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
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struct adapter *Adapter = pDM_Odm->Adapter;
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struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
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struct dm_priv *pdmpriv = &pHalData->dmpriv;
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for (index = 0; index < 6; index++)
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pdmpriv->PowerIndex_backup[index] = rtw_read8(Adapter, Power_Index_REG[index]);
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}
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static void odm_DynamicTxPowerRestorePowerIndex(struct odm_dm_struct *pDM_Odm)
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{
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u8 index;
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struct adapter *Adapter = pDM_Odm->Adapter;
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struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
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u32 Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
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struct dm_priv *pdmpriv = &pHalData->dmpriv;
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for (index = 0; index < 6; index++)
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rtw_write8(Adapter, Power_Index_REG[index], pdmpriv->PowerIndex_backup[index]);
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}
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static void odm_DynamicTxPowerWritePowerIndex(struct odm_dm_struct *pDM_Odm, u8 Value)
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{
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u8 index;
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u32 Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
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for (index = 0; index < 6; index++)
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ODM_Write1Byte(pDM_Odm, Power_Index_REG[index], Value);
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}
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void odm_DynamicTxPower(struct odm_dm_struct *pDM_Odm)
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{
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/* For AP/ADSL use struct rtl8192cd_priv * */
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@ -1546,18 +1468,10 @@ void odm_DynamicTxPowerAP(struct odm_dm_struct *pDM_Odm)
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{
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}
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static void odm_DynamicTxPower_92C(struct odm_dm_struct *pDM_Odm)
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{
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}
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/* 3============================================================ */
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/* 3 RSSI Monitor */
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/* 3============================================================ */
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static void odm_RSSIMonitorInit(struct odm_dm_struct *pDM_Odm)
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{
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}
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void odm_RSSIMonitorCheck(struct odm_dm_struct *pDM_Odm)
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{
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if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR))
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@ -1589,13 +1503,6 @@ void odm_RSSIMonitorCheckMP(struct odm_dm_struct *pDM_Odm)
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{
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}
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/* */
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/* sherry move from DUSC to here 20110517 */
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/* */
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static void FindMinimumRSSI_Dmsp(struct adapter *pAdapter)
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{
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}
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static void FindMinimumRSSI(struct adapter *pAdapter)
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{
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struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
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@ -1780,10 +1687,6 @@ void odm_SwAntDivChkAntSwitch(struct odm_dm_struct *pDM_Odm, u8 Step)
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{
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}
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static void ODM_SwAntDivResetBeforeLink(struct odm_dm_struct *pDM_Odm)
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{
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}
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void ODM_SwAntDivRestAfterLink(struct odm_dm_struct *pDM_Odm)
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{
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}
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@ -1796,67 +1699,6 @@ void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext)
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/* 3 SW Antenna Diversity */
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/* 3============================================================ */
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static void odm_InitHybridAntDiv_88C_92D(struct odm_dm_struct *pDM_Odm)
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{
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struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
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u8 bTxPathSel = 0; /* 0:Path-A 1:Path-B */
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u8 i;
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_InitHybridAntDiv==============>\n"));
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/* whether to do antenna diversity or not */
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if ((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8192D))
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return;
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bTxPathSel = (pDM_Odm->RFType == ODM_1T1R) ? false : true;
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ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV1_11N, BIT23, 0); /* No update ANTSEL during GNT_BT=1 */
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ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N, BIT21, 1); /* TX atenna selection from tx_info */
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ODM_SetBBReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, BIT23, 1); /* enable LED[1:0] pin as ANTSEL */
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ODM_SetBBReg(pDM_Odm, ODM_REG_ANTSEL_CTRL_11N, BIT8|BIT9, 0x01); /* 0x01: left antenna, 0x02: right antenna */
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/* check HW setting: ANTSEL pin connection */
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/* only AP support different path selection temperarly */
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if (!bTxPathSel) { /* PATH-A */
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ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N, BIT8|BIT9, 0); /* ANTSEL as HW control */
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ODM_SetBBReg(pDM_Odm, ODM_REG_ANTSEL_PATH_11N, BIT13, 1); /* select TX ANTESEL from path A */
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} else {
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ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N, BIT24|BIT25, 0); /* ANTSEL as HW control */
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ODM_SetBBReg(pDM_Odm, ODM_REG_ANTSEL_PATH_11N, BIT13, 0); /* select ANTESEL from path B */
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}
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/* Set OFDM HW RX Antenna Diversity */
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ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N, 0x7FF, 0x0c0); /* Pwdb threshold=8dB */
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ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N, BIT11, 0); /* Switch to another antenna by checking pwdb threshold */
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ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA3_11N, BIT23, 1); /* Decide final antenna by comparing 2 antennas' pwdb */
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/* Set CCK HW RX Antenna Diversity */
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ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 0); /* Antenna diversity decision period = 32 sample */
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ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N, 0xf, 0xf); /* Threshold for antenna diversity. Check another antenna power if input power < ANT_lim*4 */
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ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA3_11N, BIT13, 1); /* polarity ana_A=1 and ana_B=0 */
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ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA4_11N, 0x1f, 0x8); /* default antenna power = inpwr*(0.5 + r_ant_step/16) */
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/* Enable HW Antenna Diversity */
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if (!bTxPathSel) /* PATH-A */
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ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N, BIT7, 1); /* Enable Hardware antenna switch */
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else
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ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_B_11N, BIT7, 1); /* Enable Hardware antenna switch */
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ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 1);/* Enable antenna diversity */
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pDM_SWAT_Table->CurAntenna = 0; /* choose left antenna as default antenna */
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pDM_SWAT_Table->PreAntenna = 0;
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for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) {
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pDM_SWAT_Table->CCK_Ant1_Cnt[i] = 0;
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pDM_SWAT_Table->CCK_Ant2_Cnt[i] = 0;
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pDM_SWAT_Table->OFDM_Ant1_Cnt[i] = 0;
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pDM_SWAT_Table->OFDM_Ant2_Cnt[i] = 0;
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pDM_SWAT_Table->RSSI_Ant1_Sum[i] = 0;
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pDM_SWAT_Table->RSSI_Ant2_Sum[i] = 0;
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}
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("<==============odm_InitHybridAntDiv\n"));
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}
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void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm)
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{
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if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) {
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@ -1870,69 +1712,6 @@ void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm)
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ODM_AntennaDiversityInit_88E(pDM_Odm);
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}
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static bool odm_StaDefAntSel(struct odm_dm_struct *pDM_Odm, u32 OFDM_Ant1_Cnt,
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u32 OFDM_Ant2_Cnt, u32 CCK_Ant1_Cnt, u32 CCK_Ant2_Cnt, u8 *pDefAnt)
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{
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_StaDefAntSelect==============>\n"));
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("OFDM_Ant1_Cnt:%d, OFDM_Ant2_Cnt:%d\n", OFDM_Ant1_Cnt, OFDM_Ant2_Cnt));
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CCK_Ant1_Cnt:%d, CCK_Ant2_Cnt:%d\n", CCK_Ant1_Cnt, CCK_Ant2_Cnt));
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if (((OFDM_Ant1_Cnt+OFDM_Ant2_Cnt) == 0) && ((CCK_Ant1_Cnt + CCK_Ant2_Cnt) < 10)) {
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_StaDefAntSelect Fail: No enough packet info!\n"));
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return false;
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}
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if (OFDM_Ant1_Cnt || OFDM_Ant2_Cnt) {
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/* if RX OFDM packet number larger than 0 */
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if (OFDM_Ant1_Cnt > OFDM_Ant2_Cnt)
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(*pDefAnt) = 1;
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else
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(*pDefAnt) = 0;
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} else if ((CCK_Ant1_Cnt + CCK_Ant2_Cnt) >= 10) {
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/* else if RX CCK packet number larger than 10 */
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if (CCK_Ant1_Cnt > (5*CCK_Ant2_Cnt))
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(*pDefAnt) = 1;
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else if (CCK_Ant2_Cnt > (5*CCK_Ant1_Cnt))
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(*pDefAnt) = 0;
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else if (CCK_Ant1_Cnt > CCK_Ant2_Cnt)
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(*pDefAnt) = 0;
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else
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(*pDefAnt) = 1;
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}
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TxAnt = %s\n", ((*pDefAnt) == 1) ? "Ant1" : "Ant2"));
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("<==============odm_StaDefAntSelect\n"));
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return true;
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}
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static void odm_SetRxIdleAnt(struct odm_dm_struct *pDM_Odm, u8 Ant, bool bDualPath)
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{
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struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
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if (Ant != pDM_SWAT_Table->RxIdleAnt) {
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/* for path-A */
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if (Ant == 1)
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N, 0xFFFF, 0x65a9); /* right-side antenna */
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else
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N, 0xFFFF, 0x569a); /* left-side antenna */
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/* for path-B */
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if (bDualPath) {
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if (Ant == 0)
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N, 0xFFFF0000, 0x65a9); /* right-side antenna */
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else
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ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N, 0xFFFF0000, 0x569a); /* left-side antenna */
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}
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}
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pDM_SWAT_Table->RxIdleAnt = Ant;
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RxIdleAnt: %s Reg858=0x%x\n", (Ant == 1) ? "Ant1" : "Ant2", (Ant == 1) ? 0x65a9 : 0x569a));
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}
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void ODM_AntselStatistics_88C(struct odm_dm_struct *pDM_Odm, u8 MacId, u32 PWDBAll, bool isCCKrate)
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{
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struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
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@ -1954,78 +1733,6 @@ void ODM_AntselStatistics_88C(struct odm_dm_struct *pDM_Odm, u8 MacId, u32 PWDBA
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}
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}
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static void ODM_SetTxAntByTxInfo_88C_92D(struct odm_dm_struct *pDM_Odm)
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{
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}
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static void odm_HwAntDiv_92C_92D(struct odm_dm_struct *pDM_Odm)
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{
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struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
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u32 RSSI_Min = 0xFF, RSSI, RSSI_Ant1, RSSI_Ant2;
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u8 RxIdleAnt, i;
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bool bRet = false;
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struct sta_info *pEntry;
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_HwAntDiv==============>\n"));
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if (!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV)) {
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/* if don't support antenna diveristy */
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_HwAntDiv: Not supported!\n"));
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return;
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}
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if ((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8192D)) {
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: IC Type is not 92C or 92D\n"));
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return;
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}
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if (!pDM_Odm->bLinked) {
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: bLinked is false\n"));
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return;
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}
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for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
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pEntry = pDM_Odm->pODM_StaInfo[i];
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if (IS_STA_VALID(pEntry)) {
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RSSI_Ant1 = (pDM_SWAT_Table->OFDM_Ant1_Cnt[i] == 0) ? 0 : (pDM_SWAT_Table->RSSI_Ant1_Sum[i]/pDM_SWAT_Table->OFDM_Ant1_Cnt[i]);
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RSSI_Ant2 = (pDM_SWAT_Table->OFDM_Ant2_Cnt[i] == 0) ? 0 : (pDM_SWAT_Table->RSSI_Ant2_Sum[i]/pDM_SWAT_Table->OFDM_Ant2_Cnt[i]);
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ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RSSI_Ant1=%d, RSSI_Ant2=%d\n", RSSI_Ant1, RSSI_Ant2));
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if (RSSI_Ant1 || RSSI_Ant2) {
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RSSI = (RSSI_Ant1 < RSSI_Ant2) ? RSSI_Ant1 : RSSI_Ant2;
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if ((!RSSI) || (RSSI < RSSI_Min)) {
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pDM_SWAT_Table->TargetSTA = i;
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RSSI_Min = RSSI;
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}
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}
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/* STA: found out default antenna */
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bRet = odm_StaDefAntSel(pDM_Odm,
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pDM_SWAT_Table->OFDM_Ant1_Cnt[i],
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pDM_SWAT_Table->OFDM_Ant2_Cnt[i],
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pDM_SWAT_Table->CCK_Ant1_Cnt[i],
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pDM_SWAT_Table->CCK_Ant2_Cnt[i],
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&pDM_SWAT_Table->TxAnt[i]);
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/* if Tx antenna selection: successful */
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if (bRet) {
|
||||
pDM_SWAT_Table->RSSI_Ant1_Sum[i] = 0;
|
||||
pDM_SWAT_Table->RSSI_Ant2_Sum[i] = 0;
|
||||
pDM_SWAT_Table->OFDM_Ant1_Cnt[i] = 0;
|
||||
pDM_SWAT_Table->OFDM_Ant2_Cnt[i] = 0;
|
||||
pDM_SWAT_Table->CCK_Ant1_Cnt[i] = 0;
|
||||
pDM_SWAT_Table->CCK_Ant2_Cnt[i] = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* set RX Idle Ant */
|
||||
RxIdleAnt = pDM_SWAT_Table->TxAnt[pDM_SWAT_Table->TargetSTA];
|
||||
odm_SetRxIdleAnt(pDM_Odm, RxIdleAnt, false);
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("<==============odm_HwAntDiv\n"));
|
||||
}
|
||||
|
||||
void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm)
|
||||
{
|
||||
if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) {
|
||||
|
|
@ -2095,11 +1802,6 @@ void odm_EdcaTurboCheckCE(struct odm_dm_struct *pDM_Odm)
|
|||
if (pmlmeinfo->assoc_AP_vendor >= HT_IOT_PEER_MAX)
|
||||
goto dm_CheckEdcaTurbo_EXIT;
|
||||
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
if (BT_DisableEDCATurbo(Adapter))
|
||||
goto dm_CheckEdcaTurbo_EXIT;
|
||||
#endif
|
||||
|
||||
/* Check if the status needs to be changed. */
|
||||
if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) {
|
||||
cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue