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rtl8188eu: Remove MP_DRIVER conditionals - selected

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2013-07-26 22:26:30 -05:00
parent caeea00c03
commit 1e96c9a1d4
8 changed files with 53 additions and 141 deletions
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13
core/rtw_efuse.c
View file

@ -1136,13 +1136,9 @@ EFUSE_ShadowWrite(
u16 Offset, u16 Offset,
u32 Value) u32 Value)
{ {
#if (MP_DRIVER == 0)
return;
#endif
if ( pAdapter->registrypriv.mp_mode == 0) if ( pAdapter->registrypriv.mp_mode == 0)
return; return;
if (Type == 1) if (Type == 1)
efuse_ShadowWrite1Byte(pAdapter, Offset, (u8)Value); efuse_ShadowWrite1Byte(pAdapter, Offset, (u8)Value);
else if (Type == 2) else if (Type == 2)
@ -1152,14 +1148,7 @@ EFUSE_ShadowWrite(
} /* EFUSE_ShadowWrite */ } /* EFUSE_ShadowWrite */
void void Efuse_InitSomeVar(struct adapter *pAdapter)
Efuse_InitSomeVar(
struct adapter * pAdapter
);
void
Efuse_InitSomeVar(
struct adapter * pAdapter
)
{ {
u8 i; u8 i;

2
core/rtw_pwrctrl.c
View file

@ -34,10 +34,8 @@ void ips_enter(struct adapter * padapter)
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct xmit_priv *pxmit_priv = &padapter->xmitpriv; struct xmit_priv *pxmit_priv = &padapter->xmitpriv;
#if (MP_DRIVER == 1)
if (padapter->registrypriv.mp_mode == 1) if (padapter->registrypriv.mp_mode == 1)
return; return;
#endif
if (pxmit_priv->free_xmitbuf_cnt != NR_XMITBUFF || if (pxmit_priv->free_xmitbuf_cnt != NR_XMITBUFF ||
pxmit_priv->free_xmit_extbuf_cnt != NR_XMIT_EXTBUFF) { pxmit_priv->free_xmit_extbuf_cnt != NR_XMIT_EXTBUFF) {

71
hal/HalPhyRf_8188e.c
View file

@ -189,10 +189,8 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
pDM_Odm->RFCalibrateInfo.TXPowerTrackingCallbackCnt++; /* cosa add for debug */ pDM_Odm->RFCalibrateInfo.TXPowerTrackingCallbackCnt++; /* cosa add for debug */
pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = true; pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = true;
#if (MP_DRIVER == 1) /* <Kordan> RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. */
/* <Kordan> RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. */ pDM_Odm->RFCalibrateInfo.RegA24 = 0x090e1317;
pDM_Odm->RFCalibrateInfo.RegA24 = 0x090e1317;
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("===>dm_TXPowerTrackingCallback_ThermalMeter_8188E txpowercontrol %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl)); ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("===>dm_TXPowerTrackingCallback_ThermalMeter_8188E txpowercontrol %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl));
@ -1223,17 +1221,13 @@ static void phy_IQCalibrate_8188E(
rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD
}; };
#if MP_DRIVER
u4Byte retryCount = 9; u4Byte retryCount = 9;
#else
u4Byte retryCount = 2;
#endif
if ( *(pDM_Odm->mp_mode) == 1) if ( *(pDM_Odm->mp_mode) == 1)
retryCount = 9; retryCount = 9;
else else
retryCount = 2; retryCount = 2;
/* Note: IQ calibration must be performed after loading */ /* Note: IQ calibration must be performed after loading */
/* PHY_REG.txt , and radio_a, radio_b.txt */ /* PHY_REG.txt , and radio_a, radio_b.txt */
if (t==0) { if (t==0) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));
@ -1544,18 +1538,13 @@ static void phy_APCalibrate_8188E(
}; };
u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; /* val_1_1a, val_1_2a, val_2a, val_3a, val_4a */ u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; /* val_1_1a, val_1_2a, val_2a, val_3a, val_4a */
/* u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; */
s4Byte BB_offset, delta_V, delta_offset; s4Byte BB_offset, delta_V, delta_offset;
#if MP_DRIVER == 1 if ( *(pDM_Odm->mp_mode) == 1) {
if ( *(pDM_Odm->mp_mode) == 1) struct mpt_context * pMptCtx = &(pAdapter->mppriv.MptCtx);
{ pMptCtx->APK_bound[0] = 45;
struct mpt_context * pMptCtx = &(pAdapter->mppriv.MptCtx); pMptCtx->APK_bound[1] = 52;
pMptCtx->APK_bound[0] = 45; }
pMptCtx->APK_bound[1] = 52;
}
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta)); ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R")));
@ -1568,10 +1557,8 @@ if ( *(pDM_Odm->mp_mode) == 1)
/* and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal */ /* and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal */
/* will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the */ /* will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the */
/* root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. */ /* root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. */
/* if MP_DRIVER != 1 */ if (*(pDM_Odm->mp_mode) != 1)
if (*(pDM_Odm->mp_mode) != 1) return;
return;
/* endif */
/* settings adjust for normal chip */ /* settings adjust for normal chip */
for (index = 0; index < PATH_NUM; index ++) for (index = 0; index < PATH_NUM; index ++)
{ {
@ -1884,13 +1871,8 @@ PHY_IQCalibrate_8188E(
) )
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv; struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
struct mpt_context * pMptCtx = &(pAdapter->mppriv.MptCtx);
#if (MP_DRIVER == 1)
struct mpt_context * pMptCtx = &(pAdapter->mppriv.MptCtx);
#endif/* MP_DRIVER == 1) */
s4Byte result[4][8]; /* last is final result */ s4Byte result[4][8]; /* last is final result */
u1Byte i, final_candidate, Indexforchannel; u1Byte i, final_candidate, Indexforchannel;
u1Byte channelToIQK = 7; u1Byte channelToIQK = 7;
@ -1913,13 +1895,10 @@ PHY_IQCalibrate_8188E(
if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
return; return;
#if MP_DRIVER == 1 if (*(pDM_Odm->mp_mode) == 1) {
if (*(pDM_Odm->mp_mode) == 1) bSingleTone = pMptCtx->bSingleTone;
{ bCarrierSuppression = pMptCtx->bCarrierSuppression;
bSingleTone = pMptCtx->bSingleTone; }
bCarrierSuppression = pMptCtx->bCarrierSuppression;
}
#endif
/* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */ /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */
if (bSingleTone || bCarrierSuppression) if (bSingleTone || bCarrierSuppression)
@ -2069,22 +2048,14 @@ PHY_LCCalibrate_8188E(
{ {
bool bSingleTone = false, bCarrierSuppression = false; bool bSingleTone = false, bCarrierSuppression = false;
u4Byte timeout = 2000, timecount = 0; u4Byte timeout = 2000, timecount = 0;
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv; struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
#if (MP_DRIVER == 1)
struct mpt_context *pMptCtx = &(pAdapter->mppriv.MptCtx); struct mpt_context *pMptCtx = &(pAdapter->mppriv.MptCtx);
#endif/* MP_DRIVER == 1) */
#if MP_DRIVER == 1 if (*(pDM_Odm->mp_mode) == 1) {
if (*(pDM_Odm->mp_mode) == 1) bSingleTone = pMptCtx->bSingleTone;
{ bCarrierSuppression = pMptCtx->bCarrierSuppression;
bSingleTone = pMptCtx->bSingleTone; }
bCarrierSuppression = pMptCtx->bCarrierSuppression;
}
#endif
if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
{ {
return; return;

18
hal/odm_RTL8188E.c
View file

@ -50,16 +50,15 @@ odm_RX_HWAntDivInit(
) )
{ {
u4Byte value32; u4Byte value32;
struct adapter * Adapter = pDM_Odm->Adapter; struct adapter *Adapter = pDM_Odm->Adapter;
#if (MP_DRIVER == 1)
if (*(pDM_Odm->mp_mode) == 1) if (*(pDM_Odm->mp_mode) == 1)
{ {
pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV; pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); /* disable HW AntDiv */ ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); /* disable HW AntDiv */
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); /* 1:CG, 0:CS */ ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); /* 1:CG, 0:CS */
return; return;
} }
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_RX_HWAntDivInit()\n")); ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_RX_HWAntDivInit()\n"));
/* MAC Setting */ /* MAC Setting */
@ -87,17 +86,13 @@ odm_TRX_HWAntDivInit(
u4Byte value32; u4Byte value32;
struct adapter * Adapter = pDM_Odm->Adapter; struct adapter * Adapter = pDM_Odm->Adapter;
#if (MP_DRIVER == 1)
if (*(pDM_Odm->mp_mode) == 1) if (*(pDM_Odm->mp_mode) == 1)
{ {
pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV; pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); /* disable HW AntDiv */ ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); /* disable HW AntDiv */
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); /* Default RX (0/1) */ ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); /* Default RX (0/1) */
return; return;
} }
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_TRX_HWAntDivInit()\n")); ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_TRX_HWAntDivInit()\n"));
/* MAC Setting */ /* MAC Setting */
@ -138,16 +133,13 @@ odm_FastAntTrainingInit(
struct adapter * Adapter = pDM_Odm->Adapter; struct adapter * Adapter = pDM_Odm->Adapter;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_FastAntTrainingInit()\n")); ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_FastAntTrainingInit()\n"));
#if (MP_DRIVER == 1)
if (*(pDM_Odm->mp_mode) == 1) if (*(pDM_Odm->mp_mode) == 1)
{ {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("pDM_Odm->AntDivType: %d\n", pDM_Odm->AntDivType)); ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("pDM_Odm->AntDivType: %d\n", pDM_Odm->AntDivType));
return; return;
} }
#endif
for (i=0; i<6; i++) for (i=0; i<6; i++) {
{
pDM_FatTable->Bssid[i] = 0; pDM_FatTable->Bssid[i] = 0;
pDM_FatTable->antSumRSSI[i] = 0; pDM_FatTable->antSumRSSI[i] = 0;
pDM_FatTable->antRSSIcnt[i] = 0; pDM_FatTable->antRSSIcnt[i] = 0;

9
hal/rtl8188e_dm.c
View file

@ -204,13 +204,10 @@ static void Update_ODM_ComInfo_88E(struct adapter * Adapter)
if (pHalData->AntDivCfg) if (pHalData->AntDivCfg)
pdmpriv->InitODMFlag |= ODM_BB_ANT_DIV; pdmpriv->InitODMFlag |= ODM_BB_ANT_DIV;
#if (MP_DRIVER==1) if (Adapter->registrypriv.mp_mode == 1) {
if (Adapter->registrypriv.mp_mode == 1)
{
pdmpriv->InitODMFlag = ODM_RF_CALIBRATION | pdmpriv->InitODMFlag = ODM_RF_CALIBRATION |
ODM_RF_TX_PWR_TRACK; ODM_RF_TX_PWR_TRACK;
} }
#endif/* MP_DRIVER==1) */
ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_ABILITY,pdmpriv->InitODMFlag); ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_ABILITY,pdmpriv->InitODMFlag);

58
hal/usb_halinit.c
View file

@ -209,7 +209,6 @@ static void _InitBTCoexist(struct adapter *padapter)
if (pbtpriv->BT_Coexist && pbtpriv->BT_CoexistType == BT_CSR_BC4) if (pbtpriv->BT_Coexist && pbtpriv->BT_CoexistType == BT_CSR_BC4)
{ {
/* if MP_DRIVER != 1 */
if (padapter->registrypriv.mp_mode == 0) if (padapter->registrypriv.mp_mode == 0)
{ {
if (pbtpriv->BT_Ant_isolation) if (pbtpriv->BT_Ant_isolation)
@ -218,47 +217,40 @@ static void _InitBTCoexist(struct adapter *padapter)
DBG_88E("BT write 0x%x = 0x%x\n", REG_GPIO_MUXCFG, 0xa0); DBG_88E("BT write 0x%x = 0x%x\n", REG_GPIO_MUXCFG, 0xa0);
} }
} }
/* endif */
u1Tmp = rtw_read8(padapter, 0x4fd) & BIT0; u1Tmp = rtw_read8(padapter, 0x4fd) & BIT0;
u1Tmp = u1Tmp | u1Tmp = u1Tmp |
((pbtpriv->BT_Ant_isolation==1)?0:BIT1) | ((pbtpriv->BT_Ant_isolation==1)?0:BIT1) |
((pbtpriv->BT_Service==BT_SCO)?0:BIT2); ((pbtpriv->BT_Service==BT_SCO)?0:BIT2);
rtw_write8( padapter, 0x4fd, u1Tmp); rtw_write8( padapter, 0x4fd, u1Tmp);
DBG_88E("BT write 0x%x = 0x%x for non-isolation\n", 0x4fd, u1Tmp); DBG_88E("BT write 0x%x = 0x%x for non-isolation\n", 0x4fd, u1Tmp);
rtw_write32(padapter, REG_BT_COEX_TABLE+4, 0xaaaa9aaa); rtw_write32(padapter, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
DBG_88E("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+4, 0xaaaa9aaa); DBG_88E("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
rtw_write32(padapter, REG_BT_COEX_TABLE+8, 0xffbd0040); rtw_write32(padapter, REG_BT_COEX_TABLE+8, 0xffbd0040);
DBG_88E("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+8, 0xffbd0040); DBG_88E("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+8, 0xffbd0040);
rtw_write32(padapter, REG_BT_COEX_TABLE+0xc, 0x40000010); rtw_write32(padapter, REG_BT_COEX_TABLE+0xc, 0x40000010);
DBG_88E("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+0xc, 0x40000010); DBG_88E("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+0xc, 0x40000010);
/* Config to 1T1R */ /* Config to 1T1R */
u1Tmp = rtw_read8(padapter,rOFDM0_TRxPathEnable); u1Tmp = rtw_read8(padapter,rOFDM0_TRxPathEnable);
u1Tmp &= ~(BIT1); u1Tmp &= ~(BIT1);
rtw_write8( padapter, rOFDM0_TRxPathEnable, u1Tmp); rtw_write8( padapter, rOFDM0_TRxPathEnable, u1Tmp);
DBG_88E("BT write 0xC04 = 0x%x\n", u1Tmp); DBG_88E("BT write 0xC04 = 0x%x\n", u1Tmp);
u1Tmp = rtw_read8(padapter, rOFDM1_TRxPathEnable); u1Tmp = rtw_read8(padapter, rOFDM1_TRxPathEnable);
u1Tmp &= ~(BIT1); u1Tmp &= ~(BIT1);
rtw_write8( padapter, rOFDM1_TRxPathEnable, u1Tmp); rtw_write8( padapter, rOFDM1_TRxPathEnable, u1Tmp);
DBG_88E("BT write 0xD04 = 0x%x\n", u1Tmp); DBG_88E("BT write 0xD04 = 0x%x\n", u1Tmp);
} }
} }
#endif #endif
/* */
/* */
/* MAC init functions */ /* MAC init functions */
/* */
/* */
static void static void
_SetMacID( _SetMacID(
struct adapter * Adapter, u8* MacID struct adapter * Adapter, u8* MacID
@ -611,10 +603,6 @@ _InitWMACSetting(
pHalData->ReceiveConfig = pHalData->ReceiveConfig =
RCR_AAP | RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYSTS; RCR_AAP | RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYSTS;
#if (1 == RTL8188E_RX_PACKET_INCLUDE_CRC)
pHalData->ReceiveConfig |= ACRC32;
#endif
/* some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile() */ /* some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile() */
rtw_write32(Adapter, REG_RCR, pHalData->ReceiveConfig); rtw_write32(Adapter, REG_RCR, pHalData->ReceiveConfig);
@ -1193,7 +1181,6 @@ _func_enter_;
_InitTxBufferBoundary(Adapter, 0); _InitTxBufferBoundary(Adapter, 0);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW); HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
#if (MP_DRIVER == 1)
if (Adapter->registrypriv.mp_mode == 1) if (Adapter->registrypriv.mp_mode == 1)
{ {
_InitRxSetting(Adapter); _InitRxSetting(Adapter);
@ -1201,7 +1188,6 @@ _func_enter_;
pHalData->fw_ractrl = false; pHalData->fw_ractrl = false;
} }
else else
#endif /* MP_DRIVER == 1 */
{ {
#ifdef CONFIG_WOWLAN #ifdef CONFIG_WOWLAN
status = rtl8188e_FirmwareDownload(Adapter, false); status = rtl8188e_FirmwareDownload(Adapter, false);
@ -1355,14 +1341,12 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM); HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
rtl8188e_InitHalDm(Adapter); rtl8188e_InitHalDm(Adapter);
#if (MP_DRIVER == 1)
if (Adapter->registrypriv.mp_mode == 1) if (Adapter->registrypriv.mp_mode == 1)
{ {
Adapter->mppriv.channel = pHalData->CurrentChannel; Adapter->mppriv.channel = pHalData->CurrentChannel;
MPT_InitializeAdapter(Adapter, Adapter->mppriv.channel); MPT_InitializeAdapter(Adapter, Adapter->mppriv.channel);
} }
else else
#endif /* if (MP_DRIVER == 1) */
{ {
/* */ /* */
/* 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status */ /* 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status */

17
include/autoconf.h
View file

@ -22,12 +22,9 @@
/* /*
* Public General Config * Public General Config
*/ */
#define AUTOCONF_INCLUDED
#define RTL871X_MODULE_NAME "88EU" #define RTL871X_MODULE_NAME "88EU"
#define DRV_NAME "rtl8188eu" #define DRV_NAME "rtl8188eu"
#define CONFIG_RTL8188E
/* /*
* Internal General Config * Internal General Config
*/ */
@ -42,20 +39,6 @@
#define CONFIG_BR_EXT_BRNAME "br0" #define CONFIG_BR_EXT_BRNAME "br0"
/*
* Interface Related Config
*/
#define CONFIG_VENDOR_REQ_RETRY
/*
* HAL Related Config
*/
#define RTL8188E_RX_PACKET_INCLUDE_CRC 0
#define MP_DRIVER 1
/* /*
* Outsource Related Config * Outsource Related Config
*/ */

6
os_dep/mlme_linux.c
View file

@ -43,10 +43,8 @@ static void _dynamic_check_timer_handlder (void *FunctionContext)
{ {
struct adapter *adapter = (struct adapter *)FunctionContext; struct adapter *adapter = (struct adapter *)FunctionContext;
#if (MP_DRIVER == 1) if (adapter->registrypriv.mp_mode == 1)
if (adapter->registrypriv.mp_mode == 1) return;
return;
#endif
rtw_dynamic_check_timer_handlder(adapter); rtw_dynamic_check_timer_handlder(adapter);
_set_timer(&adapter->mlmepriv.dynamic_chk_timer, 2000); _set_timer(&adapter->mlmepriv.dynamic_chk_timer, 2000);