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rtl8188eu: Remove typedef statements from include/rtw_rf.h and delete unused header files

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2015-03-15 12:43:37 -05:00
parent 851dc8fff5
commit 26b163f24f
12 changed files with 84 additions and 660 deletions
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2
core/rtw_wlan_util.c
View file

@ -455,7 +455,7 @@ void SetBWMode(struct adapter *padapter, unsigned short bwmode, unsigned char ch
rtw_set_oper_bw(padapter, bwmode);
rtw_set_oper_choffset(padapter, channel_offset);
rtw_hal_set_bwmode(padapter, (HT_CHANNEL_WIDTH)bwmode, channel_offset);
rtw_hal_set_bwmode(padapter, (enum HT_CHANNEL_WIDTH)bwmode, channel_offset);
_exit_critical_mutex(&(adapter_to_dvobj(padapter)->setbw_mutex), NULL);
}

2
hal/hal_intf.c
View file

@ -405,7 +405,7 @@ s32 rtw_hal_interrupt_handler(struct adapter *padapter)
return _FAIL;
}
void rtw_hal_set_bwmode(struct adapter *padapter, HT_CHANNEL_WIDTH Bandwidth, u8 Offset)
void rtw_hal_set_bwmode(struct adapter *padapter, enum HT_CHANNEL_WIDTH Bandwidth, u8 Offset)
{
if(padapter->HalFunc.set_bwmode_handler)
padapter->HalFunc.set_bwmode_handler(padapter, Bandwidth, Offset);

6
hal/rtl8188e_phycfg.c
View file

@ -1834,7 +1834,7 @@ _PHY_SetBWMode92C(
* Overview: This function is export to "HalCommon" moudule
*
* Input: struct adapter * Adapter
* HT_CHANNEL_WIDTH Bandwidth 20M or 40M
* enum HT_CHANNEL_WIDTH Bandwidth 20M or 40M
*
* Output: NONE
*
@ -1845,12 +1845,12 @@ _PHY_SetBWMode92C(
void
PHY_SetBWMode8188E(
struct adapter * Adapter,
HT_CHANNEL_WIDTH Bandwidth, /* 20M or 40M */
enum HT_CHANNEL_WIDTH Bandwidth, /* 20M or 40M */
unsigned char Offset /* Upper, Lower, or Don't care */
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
HT_CHANNEL_WIDTH tmpBW= pHalData->CurrentChannelBW;
enum HT_CHANNEL_WIDTH tmpBW= pHalData->CurrentChannelBW;
pHalData->CurrentChannelBW = Bandwidth;

42
hal/rtl8188e_rf6052.c
View file

@ -116,7 +116,7 @@ void rtl8188e_RF_ChangeTxPath( struct adapter *Adapter,
void
rtl8188e_PHY_RF6052SetBandwidth(
struct adapter * Adapter,
HT_CHANNEL_WIDTH Bandwidth) /* 20M or 40M */
enum HT_CHANNEL_WIDTH Bandwidth) /* 20M or 40M */
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
@ -371,66 +371,28 @@ static void getTxPowerWriteValByRegulatory88E(
chnlGroup++;
else
chnlGroup+=6;
/*
if(Channel <= 3)
chnlGroup = 0;
else if(Channel >= 4 && Channel <= 9)
chnlGroup = 1;
else if(Channel > 9)
chnlGroup = 2;
if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
chnlGroup++;
else
chnlGroup+=4;
*/
}
/* RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", */
/* chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); */
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
/* RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); */
}
break;
case 2: /* Better regulatory */
/* don't increase any power diff */
writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]);
/* RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); */
break;
case 3: /* Customer defined power diff. */
/* increase power diff defined by customer. */
chnlGroup = 0;
/* RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", */
/* chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); */
/*
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
{
RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 40MHz rf(%c) = 0x%x\n",
((rf==0)?'A':'B'), pHalData->PwrGroupHT40[rf][Channel-1]));
}
else
{
RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 20MHz rf(%c) = 0x%x\n",
((rf==0)?'A':'B'), pHalData->PwrGroupHT20[rf][Channel-1]));
}*/
if(index < 2)
pwr_diff = pHalData->TxPwrLegacyHtDiff[rf][Channel-1];
else if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
pwr_diff = pHalData->TxPwrHt20Diff[rf][Channel-1];
/* RTPRINT(FPHY, PHY_TXPWR, ("power diff rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), pwr_diff)); */
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
customer_pwr_limit = pHalData->PwrGroupHT40[rf][Channel-1];
else
customer_pwr_limit = pHalData->PwrGroupHT20[rf][Channel-1];
/* RTPRINT(FPHY, PHY_TXPWR, ("customer pwr limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_pwr_limit)); */
if(pwr_diff >= customer_pwr_limit)
pwr_diff = 0;
else
@ -617,7 +579,7 @@ phy_RF6052_Config_HardCode(
{
/* Set Default Bandwidth to 20M */
/* Adapter->HalFunc .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20); */
/* Adapter->HalFunc .SetBWModeHandler(Adapter, enum HT_CHANNEL_WIDTH_20); */
/* TODO: Set Default Channel to channel one for RTL8225 */

2
include/Hal8188EPhyCfg.h
View file

@ -258,7 +258,7 @@ PHY_ScanOperationBackup8188E(struct adapter *Adapter, u8 Operation);
//
// Switch bandwidth for 8192S
//
void PHY_SetBWMode8188E(struct adapter *pAdapter, HT_CHANNEL_WIDTH ChnlWidth, unsigned char Offset);
void PHY_SetBWMode8188E(struct adapter *pAdapter, enum HT_CHANNEL_WIDTH ChnlWidth, unsigned char Offset);
//
// Set A2 entry to fw for 8192S

30
include/custom_gpio.h
View file

@ -1,30 +0,0 @@
#ifndef __CUSTOM_GPIO_H__
#define __CUSTOM_GPIO_H___
#include <drv_conf.h>
#include <osdep_service.h>
#ifdef PLATFORM_OS_XP
#include <drv_types_xp.h>
#endif
#ifdef PLATFORM_OS_CE
#include <drv_types_ce.h>
#endif
#include <drv_types_linux.h>
typedef enum cust_gpio_modes {
WLAN_PWDN_ON,
WLAN_PWDN_OFF,
WLAN_POWER_ON,
WLAN_POWER_OFF,
WLAN_BT_PWDN_ON,
WLAN_BT_PWDN_OFF
} cust_gpio_modes_t;
extern int rtw_wifi_gpio_init(void);
extern int rtw_wifi_gpio_deinit(void);
extern void rtw_wifi_gpio_wlan_ctrl(int onoff);
#endif

4
include/hal_intf.h
View file

@ -186,7 +186,7 @@ struct hal_ops {
void (*enable_interrupt)(struct adapter *padapter);
void (*disable_interrupt)(struct adapter *padapter);
s32 (*interrupt_handler)(struct adapter *padapter);
void (*set_bwmode_handler)(struct adapter *padapter, HT_CHANNEL_WIDTH Bandwidth, u8 Offset);
void (*set_bwmode_handler)(struct adapter *padapter, enum HT_CHANNEL_WIDTH Bandwidth, u8 Offset);
void (*set_channel_handler)(struct adapter *padapter, u8 channel);
void (*hal_dm_watchdog)(struct adapter *padapter);
@ -391,7 +391,7 @@ void rtw_hal_write_rfreg(struct adapter *padapter, u32 eRFPath, u32 RegAddr, u32
s32 rtw_hal_interrupt_handler(struct adapter *padapter);
void rtw_hal_set_bwmode(struct adapter *padapter, HT_CHANNEL_WIDTH Bandwidth, u8 Offset);
void rtw_hal_set_bwmode(struct adapter *padapter, enum HT_CHANNEL_WIDTH Bandwidth, u8 Offset);
void rtw_hal_set_chan(struct adapter *padapter, u8 channel);
void rtw_hal_dm_watchdog(struct adapter *padapter);

164
include/pci_hal.h
View file

@ -1,164 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PCI_HAL_H__
#define __PCI_HAL_H__
#define INTEL_VENDOR_ID 0x8086
#define SIS_VENDOR_ID 0x1039
#define ATI_VENDOR_ID 0x1002
#define ATI_DEVICE_ID 0x7914
#define AMD_VENDOR_ID 0x1022
#define PCI_MAX_BRIDGE_NUMBER 255
#define PCI_MAX_DEVICES 32
#define PCI_MAX_FUNCTION 8
#define PCI_CONF_ADDRESS 0x0CF8 // PCI Configuration Space Address
#define PCI_CONF_DATA 0x0CFC // PCI Configuration Space Data
#define PCI_CLASS_BRIDGE_DEV 0x06
#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04
#define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10
#define U1DONTCARE 0xFF
#define U2DONTCARE 0xFFFF
#define U4DONTCARE 0xFFFFFFFF
#define PCI_VENDER_ID_REALTEK 0x10ec
#define HAL_HW_PCI_8180_DEVICE_ID 0x8180
#define HAL_HW_PCI_8185_DEVICE_ID 0x8185 //8185 or 8185b
#define HAL_HW_PCI_8188_DEVICE_ID 0x8188 //8185b
#define HAL_HW_PCI_8198_DEVICE_ID 0x8198 //8185b
#define HAL_HW_PCI_8190_DEVICE_ID 0x8190 //8190
#define HAL_HW_PCI_8723E_DEVICE_ID 0x8723 //8723E
#define HAL_HW_PCI_8192_DEVICE_ID 0x8192 //8192 PCI-E
#define HAL_HW_PCI_8192SE_DEVICE_ID 0x8192 //8192 SE
#define HAL_HW_PCI_8174_DEVICE_ID 0x8174 //8192 SE
#define HAL_HW_PCI_8173_DEVICE_ID 0x8173 //8191 SE Crab
#define HAL_HW_PCI_8172_DEVICE_ID 0x8172 //8191 SE RE
#define HAL_HW_PCI_8171_DEVICE_ID 0x8171 //8191 SE Unicron
#define HAL_HW_PCI_0045_DEVICE_ID 0x0045 //8190 PCI for Ceraga
#define HAL_HW_PCI_0046_DEVICE_ID 0x0046 //8190 Cardbus for Ceraga
#define HAL_HW_PCI_0044_DEVICE_ID 0x0044 //8192e PCIE for Ceraga
#define HAL_HW_PCI_0047_DEVICE_ID 0x0047 //8192e Express Card for Ceraga
#define HAL_HW_PCI_700F_DEVICE_ID 0x700F
#define HAL_HW_PCI_701F_DEVICE_ID 0x701F
#define HAL_HW_PCI_DLINK_DEVICE_ID 0x3304
#define HAL_HW_PCI_8192CET_DEVICE_ID 0x8191 //8192ce
#define HAL_HW_PCI_8192CE_DEVICE_ID 0x8178 //8192ce
#define HAL_HW_PCI_8191CE_DEVICE_ID 0x8177 //8192ce
#define HAL_HW_PCI_8188CE_DEVICE_ID 0x8176 //8192ce
#define HAL_HW_PCI_8192CU_DEVICE_ID 0x8191 //8192ce
#define HAL_HW_PCI_8192DE_DEVICE_ID 0x8193 //8192de
#define HAL_HW_PCI_002B_DEVICE_ID 0x002B //8192de, provided by HW SD
#define HAL_HW_PCI_8188EE_DEVICE_ID 0x8179
#define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI 0x1000 //8190 support 16 pages of IO registers
#define HAL_HW_PCI_REVISION_ID_8190PCI 0x00
#define HAL_MEMORY_MAPPED_IO_RANGE_8192PCIE 0x4000 //8192 support 16 pages of IO registers
#define HAL_HW_PCI_REVISION_ID_8192PCIE 0x01
#define HAL_MEMORY_MAPPED_IO_RANGE_8192SE 0x4000 //8192 support 16 pages of IO registers
#define HAL_HW_PCI_REVISION_ID_8192SE 0x10
#define HAL_HW_PCI_REVISION_ID_8192CE 0x1
#define HAL_MEMORY_MAPPED_IO_RANGE_8192CE 0x4000 //8192 support 16 pages of IO registers
#define HAL_HW_PCI_REVISION_ID_8192DE 0x0
#define HAL_MEMORY_MAPPED_IO_RANGE_8192DE 0x4000 //8192 support 16 pages of IO registers
enum pci_bridge_vendor {
PCI_BRIDGE_VENDOR_INTEL = 0x0,//0b'0000,0001
PCI_BRIDGE_VENDOR_ATI, //= 0x02,//0b'0000,0010
PCI_BRIDGE_VENDOR_AMD, //= 0x04,//0b'0000,0100
PCI_BRIDGE_VENDOR_SIS ,//= 0x08,//0b'0000,1000
PCI_BRIDGE_VENDOR_UNKNOWN, //= 0x40,//0b'0100,0000
PCI_BRIDGE_VENDOR_MAX ,//= 0x80
} ;
struct rt_pci_capabilities_header {
u8 capability_id;
u8 next;
};
struct pci_priv{
u8 linkctrl_reg;
u8 busnumber;
u8 devnumber;
u8 funcnumber;
u8 pcibridge_busnum;
u8 pcibridge_devnum;
u8 pcibridge_funcnum;
u8 pcibridge_vendor;
u16 pcibridge_vendorid;
u16 pcibridge_deviceid;
u8 pcibridge_pciehdr_offset;
u8 pcibridge_linkctrlreg;
u8 amd_l1_patch;
};
typedef struct _RT_ISR_CONTENT
{
union{
u32 IntArray[2];
u32 IntReg4Byte;
u16 IntReg2Byte;
};
}RT_ISR_CONTENT, *PRT_ISR_CONTENT;
//#define RegAddr(addr) (addr + 0xB2000000UL)
//some platform macros will def here
static inline void NdisRawWritePortUlong(u32 port, u32 val)
{
outl(val, port);
//writel(val, (u8 *)RegAddr(port));
}
static inline void NdisRawWritePortUchar(u32 port, u8 val)
{
outb(val, port);
//writeb(val, (u8 *)RegAddr(port));
}
static inline void NdisRawReadPortUchar(u32 port, u8 *pval)
{
*pval = inb(port);
//*pval = readb((u8 *)RegAddr(port));
}
static inline void NdisRawReadPortUshort(u32 port, u16 *pval)
{
*pval = inw(port);
//*pval = readw((u8 *)RegAddr(port));
}
static inline void NdisRawReadPortUlong(u32 port, u32 *pval)
{
*pval = inl(port);
//*pval = readl((u8 *)RegAddr(port));
}
void rtl8188ee_set_hal_ops(struct adapter * padapter);
#define hal_set_hal_ops rtl8188ee_set_hal_ops
#endif //__PCIE_HAL_H__

2
include/rtl8188e_hal.h
View file

@ -289,7 +289,7 @@ typedef struct hal_data_8188e
//current WIFI_PHY values
u32 ReceiveConfig;
WIRELESS_MODE CurrentWirelessMode;
HT_CHANNEL_WIDTH CurrentChannelBW;
enum HT_CHANNEL_WIDTH CurrentChannelBW;
u8 CurrentChannel;
u8 nCur40MhzPrimeSC;// Control channel sub-carrier

17
include/rtl8188e_rf.h
View file

@ -28,17 +28,10 @@
int PHY_RF6052_Config8188E( struct adapter * Adapter );
void rtl8188e_RF_ChangeTxPath( struct adapter *Adapter,
u16 DataRate);
void rtl8188e_PHY_RF6052SetBandwidth(
struct adapter * Adapter,
HT_CHANNEL_WIDTH Bandwidth);
void rtl8188e_PHY_RF6052SetCckTxPower(
struct adapter *Adapter,
u8* pPowerlevel);
void rtl8188e_PHY_RF6052SetOFDMTxPower(
struct adapter *Adapter,
u8* pPowerLevelOFDM,
u8* pPowerLevelBW20,
u8* pPowerLevelBW40,
u8 Channel);
void rtl8188e_PHY_RF6052SetBandwidth(struct adapter *Adapter, enum HT_CHANNEL_WIDTH Bandwidth);
void rtl8188e_PHY_RF6052SetCckTxPower(struct adapter *Adapter, u8 *pPowerlevel);
void rtl8188e_PHY_RF6052SetOFDMTxPower(struct adapter *Adapter, u8 *pPowerLevelOFDM,
u8 *pPowerLevelBW20, u8 *pPowerLevelBW40,
u8 Channel);
#endif//__RTL8188E_RF_H__

317
include/rtw_bt_mp.h
View file

@ -1,317 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTW_BT_MP_H
#define __RTW_BT_MP_H
#include <osdep_service.h>
#include <drv_types.h>
#include <rtw_mp.h>
#if(MP_DRIVER == 1)
#pragma pack(1)
// definition for BT_UP_OP_BT_READY
#define MP_BT_NOT_READY 0
#define MP_BT_READY 1
// definition for BT_UP_OP_BT_SET_MODE
typedef enum _MP_BT_MODE{
MP_BT_MODE_RF_TXRX_TEST_MODE = 0,
MP_BT_MODE_BT20_DUT_TEST_MODE = 1,
MP_BT_MODE_BT40_DIRECT_TEST_MODE = 2,
MP_BT_MODE_CONNECT_TEST_MODE = 3,
MP_BT_MODE_MAX
}MP_BT_MODE,*PMP_BT_MODE;
// definition for BT_UP_OP_BT_SET_TX_RX_PARAMETER
typedef struct _BT_TXRX_PARAMETERS{
u8 txrxChannel;
u32 txrxTxPktCnt;
u8 txrxTxPktInterval;
u8 txrxPayloadType;
u8 txrxPktType;
u16 txrxPayloadLen;
u32 txrxPktHeader;
u8 txrxWhitenCoeff;
u8 txrxBdaddr[6];
u8 txrxTxGainIndex;
} BT_TXRX_PARAMETERS, *PBT_TXRX_PARAMETERS;
// txrxPktType
typedef enum _MP_BT_PKT_TYPE{
MP_BT_PKT_DH1 = 0,
MP_BT_PKT_DH3 = 1,
MP_BT_PKT_DH5 = 2,
MP_BT_PKT_2DH1 = 3,
MP_BT_PKT_2DH3 = 4,
MP_BT_PKT_2DH5 = 5,
MP_BT_PKT_3DH1 = 6,
MP_BT_PKT_3DH3 = 7,
MP_BT_PKT_3DH5 = 8,
MP_BT_PKT_LE = 9,
MP_BT_PKT_MAX
}MP_BT_PKT_TYPE,*PMP_BT_PKT_TYPE;
// txrxPayloadType
typedef enum _MP_BT_PAYLOAD_TYPE{
MP_BT_PAYLOAD_01010101 = 0,
MP_BT_PAYLOAD_ALL_1 = 1,
MP_BT_PAYLOAD_ALL_0 = 2,
MP_BT_PAYLOAD_11110000 = 3,
MP_BT_PAYLOAD_PRBS9 = 4,
MP_BT_PAYLOAD_MAX
}MP_BT_PAYLOAD_TYPE,*PMP_BT_PAYLOAD_TYPE;
// definition for BT_UP_OP_BT_TEST_CTRL
typedef enum _MP_BT_TEST_CTRL{
MP_BT_TEST_STOP_ALL_TESTS = 0,
MP_BT_TEST_START_RX_TEST = 1,
MP_BT_TEST_START_PACKET_TX_TEST = 2,
MP_BT_TEST_START_CONTINUOUS_TX_TEST = 3,
MP_BT_TEST_START_INQUIRY_SCAN_TEST = 4,
MP_BT_TEST_START_PAGE_SCAN_TEST = 5,
MP_BT_TEST_START_INQUIRY_PAGE_SCAN_TEST = 6,
MP_BT_TEST_START_LEGACY_CONNECT_TEST = 7,
MP_BT_TEST_START_LE_CONNECT_TEST_INITIATOR = 8,
MP_BT_TEST_START_LE_CONNECT_TEST_ADVERTISER = 9,
MP_BT_TEST_MAX
}MP_BT_TEST_CTRL,*PMP_BT_TEST_CTRL;
typedef enum _RTL_EXT_C2H_EVT
{
EXT_C2H_WIFI_FW_ACTIVE_RSP = 0,
EXT_C2H_TRIG_BY_BT_FW = 1,
MAX_EXT_C2HEVENT
}RTL_EXT_C2H_EVT;
// return status definition to the user layer
typedef enum _BT_CTRL_STATUS{
BT_STATUS_SUCCESS = 0x00, // Success
BT_STATUS_BT_OP_SUCCESS = 0x01, // bt fw op execution success
BT_STATUS_H2C_SUCCESS = 0x02, // H2c success
BT_STATUS_H2C_TIMTOUT = 0x03, // H2c timeout
BT_STATUS_H2C_BT_NO_RSP = 0x04, // H2c sent, bt no rsp
BT_STATUS_C2H_SUCCESS = 0x05, // C2h success
BT_STATUS_C2H_REQNUM_MISMATCH = 0x06, // bt fw wrong rsp
BT_STATUS_OPCODE_U_VERSION_MISMATCH = 0x07, // Upper layer OP code version mismatch.
BT_STATUS_OPCODE_L_VERSION_MISMATCH = 0x08, // Lower layer OP code version mismatch.
BT_STATUS_UNKNOWN_OPCODE_U = 0x09, // Unknown Upper layer OP code
BT_STATUS_UNKNOWN_OPCODE_L = 0x0a, // Unknown Lower layer OP code
BT_STATUS_PARAMETER_FORMAT_ERROR_U = 0x0b, // Wrong parameters sent by upper layer.
BT_STATUS_PARAMETER_FORMAT_ERROR_L = 0x0c, // bt fw parameter format is not consistency
BT_STATUS_PARAMETER_OUT_OF_RANGE_U = 0x0d, // uppery layer parameter value is out of range
BT_STATUS_PARAMETER_OUT_OF_RANGE_L = 0x0e, // bt fw parameter value is out of range
BT_STATUS_UNKNOWN_STATUS_L = 0x0f, // bt returned an defined status code
BT_STATUS_UNKNOWN_STATUS_H = 0x10, // driver need to do error handle or not handle-well.
BT_STATUS_WRONG_LEVEL = 0x11, // should be under passive level
BT_STATUS_MAX
}BT_CTRL_STATUS,*PBT_CTRL_STATUS;
// OP codes definition between the user layer and driver
typedef enum _BT_CTRL_OPCODE_UPPER{
BT_UP_OP_BT_READY = 0x00,
BT_UP_OP_BT_SET_MODE = 0x01,
BT_UP_OP_BT_SET_TX_RX_PARAMETER = 0x02,
BT_UP_OP_BT_SET_GENERAL = 0x03,
BT_UP_OP_BT_GET_GENERAL = 0x04,
BT_UP_OP_BT_TEST_CTRL = 0x05,
BT_UP_OP_TEST_BT = 0x06,
BT_UP_OP_MAX
}BT_CTRL_OPCODE_UPPER,*PBT_CTRL_OPCODE_UPPER;
typedef enum _BT_SET_GENERAL{
BT_GSET_REG = 0x00,
BT_GSET_RESET = 0x01,
BT_GSET_TARGET_BD_ADDR = 0x02,
BT_GSET_TX_PWR_FINETUNE = 0x03,
BT_SET_TRACKING_INTERVAL = 0x04,
BT_SET_THERMAL_METER = 0x05,
BT_ENABLE_CFO_TRACKING = 0x06,
BT_GSET_UPDATE_BT_PATCH = 0x07,
BT_GSET_MAX
}BT_SET_GENERAL,*PBT_SET_GENERAL;
typedef enum _BT_GET_GENERAL{
BT_GGET_REG = 0x00,
BT_GGET_STATUS = 0x01,
BT_GGET_REPORT = 0x02,
BT_GGET_AFH_MAP = 0x03,
BT_GGET_AFH_STATUS = 0x04,
BT_GGET_MAX
}BT_GET_GENERAL,*PBT_GET_GENERAL;
// definition for BT_UP_OP_BT_SET_GENERAL
typedef enum _BT_REG_TYPE{
BT_REG_RF = 0,
BT_REG_MODEM = 1,
BT_REG_BLUEWIZE = 2,
BT_REG_VENDOR = 3,
BT_REG_LE = 4,
BT_REG_MAX
}BT_REG_TYPE,*PBT_REG_TYPE;
// definition for BT_LO_OP_GET_AFH_MAP
typedef enum _BT_AFH_MAP_TYPE{
BT_AFH_MAP_RESULT = 0,
BT_AFH_MAP_WIFI_PSD_ONLY = 1,
BT_AFH_MAP_WIFI_CH_BW_ONLY = 2,
BT_AFH_MAP_BT_PSD_ONLY = 3,
BT_AFH_MAP_HOST_CLASSIFICATION_ONLY = 4,
BT_AFH_MAP_MAX
}BT_AFH_MAP_TYPE,*PBT_AFH_MAP_TYPE;
// definition for BT_UP_OP_BT_GET_GENERAL
typedef enum _BT_REPORT_TYPE{
BT_REPORT_RX_PACKET_CNT = 0,
BT_REPORT_RX_ERROR_BITS = 1,
BT_REPORT_RSSI = 2,
BT_REPORT_CFO_HDR_QUALITY = 3,
BT_REPORT_CONNECT_TARGET_BD_ADDR = 4,
BT_REPORT_MAX
}BT_REPORT_TYPE,*PBT_REPORT_TYPE;
void
MPTBT_Test(
IN struct adapter *Adapter,
IN u8 opCode,
IN u8 byte1,
IN u8 byte2,
IN u8 byte3
);
NDIS_STATUS
MPTBT_SendOidBT(
IN struct adapter * pAdapter,
IN void * InformationBuffer,
IN ULONG InformationBufferLength,
OUT PULONG BytesRead,
OUT PULONG BytesNeeded
);
void
MPTBT_FwC2hBtMpCtrl(
struct adapter *Adapter,
u8 * tmpBuf,
u8 length
);
void MPh2c_timeout_handle(void *FunctionContext);
void mptbt_BtControlProcess(
struct adapter *Adapter,
void * pInBuf
);
#define BT_H2C_MAX_RETRY 1
#define BT_MAX_C2H_LEN 20
typedef struct _BT_REQ_CMD{
u8 opCodeVer;
u8 OpCode;
u16 paraLength;
u8 pParamStart[100];
} BT_REQ_CMD, *PBT_REQ_CMD;
typedef struct _BT_RSP_CMD{
u16 status;
u16 paraLength;
u8 pParamStart[100];
} BT_RSP_CMD, *PBT_RSP_CMD;
typedef struct _BT_H2C{
u8 opCodeVer:4;
u8 reqNum:4;
u8 opCode;
u8 buf[100];
}BT_H2C, *PBT_H2C;
typedef struct _BT_EXT_C2H{
u8 extendId;
u8 statusCode:4;
u8 retLen:4;
u8 opCodeVer:4;
u8 reqNum:4;
u8 buf[100];
}BT_EXT_C2H, *PBT_EXT_C2H;
typedef enum _BT_OPCODE_STATUS{
BT_OP_STATUS_SUCCESS = 0x00, // Success
BT_OP_STATUS_VERSION_MISMATCH = 0x01,
BT_OP_STATUS_UNKNOWN_OPCODE = 0x02,
BT_OP_STATUS_ERROR_PARAMETER = 0x03,
BT_OP_STATUS_MAX
}BT_OPCODE_STATUS,*PBT_OPCODE_STATUS;
//OP codes definition between driver and bt fw
typedef enum _BT_CTRL_OPCODE_LOWER{
BT_LO_OP_GET_BT_VERSION = 0x00,
BT_LO_OP_RESET = 0x01,
BT_LO_OP_TEST_CTRL = 0x02,
BT_LO_OP_SET_BT_MODE = 0x03,
BT_LO_OP_SET_CHNL_TX_GAIN = 0x04,
BT_LO_OP_SET_PKT_TYPE_LEN = 0x05,
BT_LO_OP_SET_PKT_CNT_L_PL_TYPE = 0x06,
BT_LO_OP_SET_PKT_CNT_H_PKT_INTV = 0x07,
BT_LO_OP_SET_PKT_HEADER = 0x08,
BT_LO_OP_SET_WHITENCOEFF = 0x09,
BT_LO_OP_SET_BD_ADDR_L = 0x0a,
BT_LO_OP_SET_BD_ADDR_H = 0x0b,
BT_LO_OP_WRITE_REG_ADDR = 0x0c,
BT_LO_OP_WRITE_REG_VALUE = 0x0d,
BT_LO_OP_GET_BT_STATUS = 0x0e,
BT_LO_OP_GET_BD_ADDR_L = 0x0f,
BT_LO_OP_GET_BD_ADDR_H = 0x10,
BT_LO_OP_READ_REG = 0x11,
BT_LO_OP_SET_TARGET_BD_ADDR_L = 0x12,
BT_LO_OP_SET_TARGET_BD_ADDR_H = 0x13,
BT_LO_OP_SET_TX_POWER_CALIBRATION = 0x14,
BT_LO_OP_GET_RX_PKT_CNT_L = 0x15,
BT_LO_OP_GET_RX_PKT_CNT_H = 0x16,
BT_LO_OP_GET_RX_ERROR_BITS_L = 0x17,
BT_LO_OP_GET_RX_ERROR_BITS_H = 0x18,
BT_LO_OP_GET_RSSI = 0x19,
BT_LO_OP_GET_CFO_HDR_QUALITY_L = 0x1a,
BT_LO_OP_GET_CFO_HDR_QUALITY_H = 0x1b,
BT_LO_OP_GET_TARGET_BD_ADDR_L = 0x1c,
BT_LO_OP_GET_TARGET_BD_ADDR_H = 0x1d,
BT_LO_OP_GET_AFH_MAP_L = 0x1e,
BT_LO_OP_GET_AFH_MAP_M = 0x1f,
BT_LO_OP_GET_AFH_MAP_H = 0x20,
BT_LO_OP_GET_AFH_STATUS = 0x21,
BT_LO_OP_SET_TRACKING_INTERVAL = 0x22,
BT_LO_OP_SET_THERMAL_METER = 0x23,
BT_LO_OP_ENABLE_CFO_TRACKING = 0x24,
BT_LO_OP_MAX
}BT_CTRL_OPCODE_LOWER,*PBT_CTRL_OPCODE_LOWER;
#endif /* #if(MP_DRIVER == 1) */
#endif // #ifndef __INC_MPT_BT_H

156
include/rtw_rf.h
View file

@ -1,22 +1,22 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTW_RF_H_
#define __RTW_RF_H_
@ -29,59 +29,59 @@
#define NumRates (13)
// slot time for 11g
#define SHORT_SLOT_TIME 9
#define NON_SHORT_SLOT_TIME 20
/* slot time for 11g */
#define SHORT_SLOT_TIME 9
#define NON_SHORT_SLOT_TIME 20
#define RTL8711_RF_MAX_SENS 6
#define RTL8711_RF_DEF_SENS 4
//
// We now define the following channels as the max channels in each channel plan.
// 2G, total 14 chnls
// {1,2,3,4,5,6,7,8,9,10,11,12,13,14}
// 5G, total 24 chnls
// {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}
#define MAX_CHANNEL_NUM_2G 14
#define MAX_CHANNEL_NUM_5G 24
#define MAX_CHANNEL_NUM 38//14+24
/* */
/* We now define the following channels as the max channels in each channel plan. */
/* 2G, total 14 chnls */
/* {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14} */
/* 5G, total 24 chnls */
/* {36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165} */
#define MAX_CHANNEL_NUM_2G 14
#define MAX_CHANNEL_NUM_5G 24
#define MAX_CHANNEL_NUM 38/* 14+24 */
//#define NUM_REGULATORYS 21
/* define NUM_REGULATORYS 21 */
#define NUM_REGULATORYS 1
//Country codes
#define USA 0x555320
#define EUROPE 0x1 //temp, should be provided later
#define JAPAN 0x2 //temp, should be provided later
/* Country codes */
#define USA 0x555320
#define EUROPE 0x1 /* temp, should be provided later */
#define JAPAN 0x2 /* temp, should be provided later */
struct regulatory_class {
u32 starting_freq; //MHz,
u32 starting_freq; /* MHz, */
u8 channel_set[MAX_CHANNEL_NUM];
u8 channel_cck_power[MAX_CHANNEL_NUM];//dbm
u8 channel_ofdm_power[MAX_CHANNEL_NUM];//dbm
u8 txpower_limit; //dbm
u8 channel_spacing; //MHz
u8 channel_cck_power[MAX_CHANNEL_NUM];/* dbm */
u8 channel_ofdm_power[MAX_CHANNEL_NUM];/* dbm */
u8 txpower_limit; /* dbm */
u8 channel_spacing; /* MHz */
u8 modem;
};
typedef enum _CAPABILITY{
cESS = 0x0001,
cIBSS = 0x0002,
cPollable = 0x0004,
cPollReq = 0x0008,
cPrivacy = 0x0010,
enum CAPABILITY {
cESS = 0x0001,
cIBSS = 0x0002,
cPollable = 0x0004,
cPollReq = 0x0008,
cPrivacy = 0x0010,
cShortPreamble = 0x0020,
cPBCC = 0x0040,
cPBCC = 0x0040,
cChannelAgility = 0x0080,
cSpectrumMgnt = 0x0100,
cQos = 0x0200, // For HCCA, use with CF-Pollable and CF-PollReq
cQos = 0x0200, /* For HCCA, use with CF-Pollable and CF-PollReq */
cShortSlotTime = 0x0400,
cAPSD = 0x0800,
cRM = 0x1000, // RRM (Radio Request Measurement)
cAPSD = 0x0800,
cRM = 0x1000, /* RRM (Radio Request Measurement) */
cDSSS_OFDM = 0x2000,
cDelayedBA = 0x4000,
cDelayedBA = 0x4000,
cImmediateBA = 0x8000,
}CAPABILITY, *PCAPABILITY;
};
enum _REG_PREAMBLE_MODE{
PREAMBLE_LONG = 1,
@ -89,69 +89,49 @@ enum _REG_PREAMBLE_MODE{
PREAMBLE_SHORT = 3,
};
enum _RTL8712_RF_MIMO_CONFIG_{
RTL8712_RFCONFIG_1T=0x10,
RTL8712_RFCONFIG_2T=0x20,
RTL8712_RFCONFIG_1R=0x01,
RTL8712_RFCONFIG_2R=0x02,
RTL8712_RFCONFIG_1T1R=0x11,
RTL8712_RFCONFIG_1T2R=0x12,
RTL8712_RFCONFIG_TURBO=0x92,
RTL8712_RFCONFIG_2T2R=0x22
enum RF90_RADIO_PATH {
RF90_PATH_A = 0, /* Radio Path A */
RF90_PATH_B = 1, /* Radio Path B */
RF90_PATH_C = 2, /* Radio Path C */
RF90_PATH_D = 3 /* Radio Path D */
};
typedef enum _RF90_RADIO_PATH{
RF90_PATH_A = 0, //Radio Path A
RF90_PATH_B = 1, //Radio Path B
RF90_PATH_C = 2, //Radio Path C
RF90_PATH_D = 3 //Radio Path D
//RF90_PATH_MAX //Max RF number 90 support
}RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E;
// Bandwidth Offset
/* Bandwidth Offset */
#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
#define HAL_PRIME_CHNL_OFFSET_LOWER 1
#define HAL_PRIME_CHNL_OFFSET_UPPER 2
// Represent Channel Width in HT Capabilities
//
typedef enum _HT_CHANNEL_WIDTH {
/* Represent Channel Width in HT Capabilities */
enum HT_CHANNEL_WIDTH {
HT_CHANNEL_WIDTH_20 = 0,
HT_CHANNEL_WIDTH_40 = 1,
HT_CHANNEL_WIDTH_80 = 2,
HT_CHANNEL_WIDTH_160 = 3,
HT_CHANNEL_WIDTH_10 = 4,
};
}HT_CHANNEL_WIDTH, *PHT_CHANNEL_WIDTH;
//
// Represent Extention Channel Offset in HT Capabilities
// This is available only in 40Mhz mode.
//
typedef enum _HT_EXTCHNL_OFFSET{
/* Represent Extention Channel Offset in HT Capabilities */
/* This is available only in 40Mhz mode. */
enum HT_EXTCHNL_OFFSET {
HT_EXTCHNL_OFFSET_NO_EXT = 0,
HT_EXTCHNL_OFFSET_UPPER = 1,
HT_EXTCHNL_OFFSET_NO_DEF = 2,
HT_EXTCHNL_OFFSET_LOWER = 3,
}HT_EXTCHNL_OFFSET, *PHT_EXTCHNL_OFFSET;
};
/* 2007/11/15 MH Define different RF type. */
typedef enum _RT_RF_TYPE_DEFINITION
{
enum RT_RF_TYPE_DEFINITION {
RF_1T2R = 0,
RF_2T4R = 1,
RF_2T2R = 2,
RF_1T1R = 3,
RF_2T2R_GREEN = 4,
RF_819X_MAX_TYPE = 5,
}RT_RF_TYPE_DEF_E;
};
u32 rtw_ch2freq(u32 ch);
u32 rtw_freq2ch(u32 freq);
#endif //_RTL8711_RF_H_
#endif /* _RTL8711_RF_H_ */