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rtl8188eu: FRemove dead code for other than USB

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2014-12-28 11:13:03 -06:00
parent 5a2939fa9e
commit 2d60bad9ad
66 changed files with 229 additions and 4045 deletions
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32
Makefile
View file

@ -17,9 +17,6 @@ ccflags-y += -D__CHECK_ENDIAN__
CONFIG_RTL8188E = y
CONFIG_USB_HCI = y
CONFIG_PCI_HCI = n
CONFIG_SDIO_HCI = n
CONFIG_GSPI_HCI = n
CONFIG_POWER_SAVING = y
CONFIG_USB_AUTOSUSPEND = n
@ -106,8 +103,6 @@ PWRSEQ_FILES := hal/HalPwrSeqCmd.o \
CHIP_FILES += $(HAL_COMM_FILES) $(OUTSRC_FILES) $(PWRSEQ_FILES)
HCI_NAME = usb
_OS_INTFS_FILES := os_dep/osdep_service.o \
os_dep/os_intfs.o \
os_dep/usb_intf.o \
@ -119,16 +114,6 @@ _OS_INTFS_FILES := os_dep/osdep_service.o \
os_dep/ioctl_cfg80211.o \
os_dep/rtw_android.o
ifeq ($(CONFIG_SDIO_HCI), y)
_OS_INTFS_FILES += os_dep/custom_gpio_linux.o
_OS_INTFS_FILES += os_dep/usb_ops_linux.o
endif
ifeq ($(CONFIG_GSPI_HCI), y)
_OS_INTFS_FILES += os_dep/custom_gpio_linux.o
_OS_INTFS_FILES += os_dep/usb_ops_linux.o
endif
_HAL_INTFS_FILES := hal/hal_intf.o \
hal/hal_com.o \
hal/rtl8188e_hal_init.o \
@ -445,9 +430,6 @@ endif
ifeq ($(CONFIG_PLATFORM_ARM_RK2818), y)
EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ROCKCHIPS -DCONFIG_MINIMAL_MEMORY_USAGE
ifeq ($(CONFIG_SDIO_HCI), y)
EXTRA_CFLAGS += -DCONFIG_DETECT_CPWM_BY_POLLING -DCONFIG_DETECT_C2H_BY_POLLING
endif
ARCH := arm
CROSS_COMPILE := /usr/src/release_fae_version/toolchain/arm-eabi-4.4.0/bin/arm-eabi-
KSRC := /usr/src/release_fae_version/kernel25_A7_281x
@ -499,17 +481,12 @@ endif
ifeq ($(CONFIG_PLATFORM_ARM_SUNxI), y)
EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ARM_SUNxI
ifeq ($(CONFIG_USB_HCI), y)
EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
endif
# default setting for Android 4.1, 4.2
EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
EXTRA_CFLAGS += -DDCONFIG_P2P_IPS
# default setting for A10-EVB mmc0
ifeq ($(CONFIG_SDIO_HCI), y)
#EXTRA_CFLAGS += -DCONFIG_WITS_EVB_V13
endif
ARCH := arm
#CROSS_COMPILE := arm-none-linux-gnueabi-
CROSS_COMPILE=/home/android_sdk/Allwinner/a10/android-jb42/lichee-jb42/buildroot/output/external-toolchain/bin/arm-none-linux-gnueabi-
@ -521,13 +498,8 @@ endif
ifeq ($(CONFIG_PLATFORM_ARM_SUN6I), y)
EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN6I
ifeq ($(CONFIG_USB_HCI), y)
EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
endif
# default setting for A31-EVB mmc0
ifeq ($(CONFIG_SDIO_HCI), y)
EXTRA_CFLAGS += -DCONFIG_A31_EVB
endif
EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
# default setting for Android 4.1, 4.2
@ -539,17 +511,13 @@ CROSS_COMPILE := /home/android_sdk/Allwinner/a31/android-jb42/lichee/buildroot/o
KVER := 3.3.0
#KSRC:= ../lichee/linux-3.3/
KSRC :=/home/android_sdk/Allwinner/a31/android-jb42/lichee/linux-3.3
ifeq ($(CONFIG_USB_HCI), y)
MODULE_NAME := 8188eu_sw
endif
endif
ifeq ($(CONFIG_PLATFORM_ARM_SUN7I), y)
EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN7I
ifeq ($(CONFIG_USB_HCI), y)
EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
endif
EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
# default setting for Android 4.1, 4.2
EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE

17
core/rtw_ap.c
View file

@ -195,12 +195,8 @@ static void update_BCNTIM(struct adapter *padapter)
}
#ifndef CONFIG_INTERRUPT_BASED_TXBCN
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
set_tx_beacon_cmd(padapter);
#endif
#endif //!CONFIG_INTERRUPT_BASED_TXBCN
}
void rtw_add_bcn_ie(struct adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len)
@ -1355,13 +1351,9 @@ static void start_bss_network(struct adapter *padapter, u8 *pbuf)
update_beacon(padapter, _TIM_IE_, NULL, _FALSE);
#ifndef CONFIG_INTERRUPT_BASED_TXBCN //other case will tx beacon when bcn interrupt coming in.
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
//issue beacon frame
if(send_beacon(padapter)==_FAIL)
{
DBG_871X("issue_beacon, fail!\n");
}
#endif
#endif //!CONFIG_INTERRUPT_BASED_TXBCN
}
@ -2146,17 +2138,10 @@ void update_beacon(struct adapter *padapter, u8 ie_id, u8 *oui, u8 tx)
_exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
#ifndef CONFIG_INTERRUPT_BASED_TXBCN
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
if(tx)
{
if(tx) {
//send_beacon(padapter);//send_beacon must execute on TSR level
set_tx_beacon_cmd(padapter);
}
#else
{
//PCI will issue beacon when BCN interrupt occurs.
}
#endif
#endif //!CONFIG_INTERRUPT_BASED_TXBCN
}

22
core/rtw_cmd.c
View file

@ -116,28 +116,6 @@ _func_enter_;
}
pevtpriv->evt_buf = pevtpriv->evt_allocated_buf + 4 - ((unsigned int)(pevtpriv->evt_allocated_buf) & 3);
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
pevtpriv->allocated_c2h_mem = rtw_zmalloc(C2H_MEM_SZ +4);
if (pevtpriv->allocated_c2h_mem == NULL){
res= _FAIL;
goto exit;
}
pevtpriv->c2h_mem = pevtpriv->allocated_c2h_mem + 4\
- ( (u32)(pevtpriv->allocated_c2h_mem) & 3);
#ifdef PLATFORM_OS_XP
pevtpriv->pc2h_mdl= IoAllocateMdl((u8 *)pevtpriv->c2h_mem, C2H_MEM_SZ , FALSE, FALSE, NULL);
if(pevtpriv->pc2h_mdl == NULL){
res= _FAIL;
goto exit;
}
MmBuildMdlForNonPagedPool(pevtpriv->pc2h_mdl);
#endif
#endif //end of CONFIG_SDIO_HCI
_rtw_init_queue(&(pevtpriv->evt_queue));
exit:

3
core/rtw_debug.c
View file

@ -406,10 +406,7 @@ int proc_get_trx_info(char *page, char **start,
len += snprintf(page + len, count - len, "%d, hwq.accnt=%d\n", i, phwxmit->accnt);
}
#ifdef CONFIG_USB_HCI
len += snprintf(page + len, count - len, "rx_urb_pending_cn=%d\n", precvpriv->rx_pending_cnt);
#endif
*eof = 1;
return len;

31
core/rtw_io.c
View file

@ -30,17 +30,8 @@ c. provides the software interface between caller and the hardware interface
Compiler Flag Option:
1. CONFIG_SDIO_HCI:
a. USE_SYNC_IRP: Only sync operations are provided.
b. USE_ASYNC_IRP:Both sync/async operations are provided.
2. CONFIG_USB_HCI:
a. USE_ASYNC_IRP: Both sync/async operations are provided.
3. CONFIG_CFIO_HCI:
b. USE_SYNC_IRP: Only sync operations are provided.
Only sync read/rtw_write_mem operations are provided.
jackson@realtek.com.tw
@ -53,34 +44,12 @@ jackson@realtek.com.tw
#include <drv_types.h>
#include <rtw_io.h>
#include <osdep_intf.h>
#ifdef CONFIG_SDIO_HCI
#include <sdio_ops.h>
#endif
#ifdef CONFIG_GSPI_HCI
#include <gspi_ops.h>
#endif
#ifdef CONFIG_USB_HCI
#include <usb_ops.h>
#endif
#ifdef CONFIG_PCI_HCI
#include <pci_ops.h>
#endif
#ifdef CONFIG_SDIO_HCI
#define rtw_le16_to_cpu(val) val
#define rtw_le32_to_cpu(val) val
#define rtw_cpu_to_le16(val) val
#define rtw_cpu_to_le32(val) val
#else
#define rtw_le16_to_cpu(val) le16_to_cpu(val)
#define rtw_le32_to_cpu(val) le32_to_cpu(val)
#define rtw_cpu_to_le16(val) cpu_to_le16(val)
#define rtw_cpu_to_le32(val) cpu_to_le32(val)
#endif
u8 _rtw_read8(struct adapter *adapter, u32 addr)

12
core/rtw_ioctl_set.c
View file

@ -25,20 +25,10 @@
#include <drv_types.h>
#include <rtw_ioctl_set.h>
#include <hal_intf.h>
#ifdef CONFIG_USB_HCI
#include <usb_osintf.h>
#include <usb_ops.h>
#endif
#ifdef CONFIG_SDIO_HCI
#include <sdio_osintf.h>
#endif
#ifdef CONFIG_GSPI_HCI
#include <gspi_osintf.h>
#endif
extern void indicate_wx_scan_complete_event(struct adapter *padapter);
void indicate_wx_scan_complete_event(struct adapter *padapter);
#define IS_MAC_ADDRESS_BROADCAST(addr) \
( \

17
core/rtw_iol.c
View file

@ -101,27 +101,10 @@ bool rtw_IOL_applied(struct adapter *adapter)
if(1 == adapter->registrypriv.fw_iol)
return _TRUE;
#ifdef CONFIG_USB_HCI
if((2 == adapter->registrypriv.fw_iol) && (!adapter_to_dvobj(adapter)->ishighspeed))
return _TRUE;
#endif
return _FALSE;
}
/*
bool rtw_IOL_applied(struct adapter *adapter)
{
if(adapter->registrypriv.fw_iol)
return _TRUE;
#ifdef CONFIG_USB_HCI
if(!adapter_to_dvobj(adapter)->ishighspeed)
return _TRUE;
#endif
return _FALSE;
}
*/
int rtw_IOL_exec_cmds_sync(struct adapter *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt)
{

16
core/rtw_led.c
View file

@ -38,19 +38,13 @@ void BlinkTimerCallback(void *data)
return;
}
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
#ifdef CONFIG_LED_HANDLED_BY_CMD_THREAD
rtw_led_blink_cmd(padapter, pLed);
#else
_set_workitem(&(pLed->BlinkWorkItem));
#endif
#elif defined(CONFIG_PCI_HCI)
BlinkHandler(pLed);
#endif
}
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
//
// Description:
// Callback function of LED BlinkWorkItem.
@ -61,7 +55,6 @@ void BlinkWorkItemCallback(struct work_struct *work)
PLED_871x pLed = container_of(work, LED_871x, BlinkWorkItem);
BlinkHandler(pLed);
}
#endif
//
// Description:
@ -78,12 +71,10 @@ void ResetLedStatus(PLED_871x pLed) {
pLed->BlinkTimes = 0; // Number of times to toggle led state for blinking.
pLed->BlinkingLedState = LED_UNKNOWN; // Next state for blinking, either RTW_LED_ON or RTW_LED_OFF are.
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
pLed->bLedNoLinkBlinkInProgress = _FALSE;
pLed->bLedLinkBlinkInProgress = _FALSE;
pLed->bLedStartToLinkBlinkInProgress = _FALSE;
pLed->bLedScanBlinkInProgress = _FALSE;
#endif
}
//
@ -104,9 +95,7 @@ InitLed871x(
_init_timer(&(pLed->BlinkTimer), padapter->pnetdev, BlinkTimerCallback, pLed);
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
_init_workitem(&(pLed->BlinkWorkItem), BlinkWorkItemCallback, pLed);
#endif
}
@ -119,9 +108,7 @@ DeInitLed871x(
PLED_871x pLed
)
{
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
_cancel_workitem_sync(&(pLed->BlinkWorkItem));
#endif
_cancel_timer_ex(&(pLed->BlinkTimer));
ResetLedStatus(pLed);
}
@ -132,7 +119,6 @@ DeInitLed871x(
// Implementation of LED blinking behavior.
// It toggle off LED and schedule corresponding timer if necessary.
//
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
void SwLedOn(struct adapter *padapter, PLED_871x pLed);
void SwLedOff(struct adapter *padapter, PLED_871x pLed);
@ -2417,5 +2403,3 @@ LedControl871x(
RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("LedStrategy:%d, LedAction %d\n", ledpriv->LedStrategy,LedAction));
}
#endif

4
core/rtw_mlme.c
View file

@ -3317,7 +3317,6 @@ void rtw_joinbss_reset(struct adapter *padapter)
phtpriv->ampdu_enable = _FALSE;//reset to disabled
#ifdef CONFIG_USB_HCI
// TH=1 => means that invalidate usb rx aggregation
// TH=0 => means that validate usb rx aggregation, use init value.
if(phtpriv->ht_option)
@ -3334,9 +3333,6 @@ void rtw_joinbss_reset(struct adapter *padapter)
rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
}
#endif
#endif
}

42
core/rtw_mlme_ext.c
View file

@ -8748,24 +8748,6 @@ unsigned int send_beacon(struct adapter *padapter)
u8 bxmitok = _FALSE;
int issue=0;
int poll = 0;
//#ifdef CONFIG_CONCURRENT_MODE
//struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
//struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
//struct adapter *pbuddy_adapter = padapter->pbuddy_adapter;
//struct mlme_priv *pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv);
//#endif
#ifdef CONFIG_PCI_HCI
//DBG_871X("%s\n", __FUNCTION__);
issue_beacon(padapter, 0);
return _SUCCESS;
#endif
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
u32 start = rtw_get_current_time();
rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
@ -8802,9 +8784,6 @@ unsigned int send_beacon(struct adapter *padapter)
return _SUCCESS;
}
#endif
}
/****************************************************************************
@ -11958,10 +11937,7 @@ u8 tx_beacon_hdl(struct adapter *padapter, unsigned char *pbuf)
if((pstapriv->tim_bitmap&BIT(0)) && (psta_bmc->sleepq_len>0))
{
#ifndef CONFIG_PCI_HCI
rtw_msleep_os(10);// 10ms, ATIM(HIQ) Windows
#endif
//_enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
_enter_critical_bh(&pxmitpriv->lock, &irqL);
xmitframe_phead = get_list_head(&psta_bmc->sleep_q);
@ -11985,29 +11961,11 @@ u8 tx_beacon_hdl(struct adapter *padapter, unsigned char *pbuf)
pxmitframe->attrib.qsel = 0x11;//HIQ
#if 0
_exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE)
{
rtw_os_xmit_complete(padapter, pxmitframe);
}
_enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
#endif
rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
//pstapriv->tim_bitmap &= ~BIT(0);
}
//_exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
_exit_critical_bh(&pxmitpriv->lock, &irqL);
//#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
rtw_chk_hi_queue_cmd(padapter);
#endif
}
}

1433
core/rtw_mp_ioctl.c
View file

File diff suppressed because it is too large Load diff

17
core/rtw_pwrctrl.c
View file

@ -910,9 +910,7 @@ _func_enter_;
if ((padapter->bSurpriseRemoved == _TRUE)
|| (padapter->hw_init_completed == _FALSE)
#ifdef CONFIG_USB_HCI
|| (padapter->bDriverStopped== _TRUE)
#endif
|| (pwrpriv->pwr_mode == PS_MODE_ACTIVE)
)
{
@ -1522,9 +1520,7 @@ _func_exit_;
}
#ifdef CONFIG_RESUME_IN_WORKQUEUE
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
extern int rtw_resume_process(struct adapter *padapter);
#endif
static void resume_workitem_callback(struct work_struct *work)
{
struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, resume_work);
@ -1533,10 +1529,7 @@ static void resume_workitem_callback(struct work_struct *work)
DBG_871X("%s\n",__FUNCTION__);
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
rtw_resume_process(adapter);
#endif
}
void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv)
@ -1570,9 +1563,7 @@ inline void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable)
#endif
#ifdef CONFIG_HAS_EARLYSUSPEND
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
extern int rtw_resume_process(struct adapter *padapter);
#endif
static void rtw_early_suspend(struct early_suspend *h)
{
struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);
@ -1589,10 +1580,8 @@ static void rtw_late_resume(struct early_suspend *h)
DBG_871X("%s\n",__FUNCTION__);
if(pwrpriv->do_late_resume) {
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
rtw_set_do_late_resume(pwrpriv, _FALSE);
rtw_resume_process(adapter);
#endif
}
}
@ -1622,9 +1611,7 @@ void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv)
#endif //CONFIG_HAS_EARLYSUSPEND
#ifdef CONFIG_ANDROID_POWER
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
extern int rtw_resume_process(struct adapter *padapter);
#endif
static void rtw_early_suspend(android_early_suspend_t *h)
{
struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);
@ -1641,10 +1628,8 @@ static void rtw_late_resume(android_early_suspend_t *h)
DBG_871X("%s\n",__FUNCTION__);
if(pwrpriv->do_late_resume) {
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
rtw_set_do_late_resume(pwrpriv, _FALSE);
rtw_resume_process(adapter);
#endif
}
}
@ -1792,7 +1777,6 @@ int _rtw_pwr_wakeup(struct adapter *padapter, u32 ips_deffer_ms, const char *cal
if(rf_off == pwrpriv->rf_pwrstate )
{
#ifdef CONFIG_USB_HCI
#ifdef CONFIG_AUTOSUSPEND
if(pwrpriv->brfoffbyhw==_TRUE)
{
@ -1811,7 +1795,6 @@ int _rtw_pwr_wakeup(struct adapter *padapter, u32 ips_deffer_ms, const char *cal
}
}
else
#endif
#endif
{
#ifdef CONFIG_IPS

83
core/rtw_recv.c
View file

@ -26,10 +26,7 @@
#include <ip.h>
#include <if_ether.h>
#include <ethernet.h>
#ifdef CONFIG_USB_HCI
#include <usb_ops.h>
#endif
#ifdef CONFIG_BT_COEXIST
#include <rtl8723a_hal.h>
@ -116,15 +113,9 @@ _func_enter_;
precvframe++;
}
#ifdef CONFIG_USB_HCI
precvpriv->rx_pending_cnt=1;
_rtw_init_sema(&precvpriv->allrxreturnevt, 0);
#endif
res = rtw_hal_init_recv_priv(padapter);
#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
@ -413,20 +404,12 @@ sint rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue)
sint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue)
{
_irqL irqL;
#ifdef CONFIG_SDIO_HCI
_enter_critical_bh(&queue->lock, &irqL);
#else
_enter_critical_ex(&queue->lock, &irqL);
#endif/*#ifdef CONFIG_SDIO_HCI*/
rtw_list_delete(&precvbuf->list);
rtw_list_insert_tail(&precvbuf->list, get_list_head(queue));
#ifdef CONFIG_SDIO_HCI
_exit_critical_bh(&queue->lock, &irqL);
#else
_exit_critical_ex(&queue->lock, &irqL);
#endif/*#ifdef CONFIG_SDIO_HCI*/
return _SUCCESS;
}
@ -437,11 +420,7 @@ struct recv_buf *rtw_dequeue_recvbuf (_queue *queue)
struct recv_buf *precvbuf;
_list *plist, *phead;
#ifdef CONFIG_SDIO_HCI
_enter_critical_bh(&queue->lock, &irqL);
#else
_enter_critical_ex(&queue->lock, &irqL);
#endif/*#ifdef CONFIG_SDIO_HCI*/
if(_rtw_queue_empty(queue) == _TRUE)
{
@ -459,11 +438,7 @@ struct recv_buf *rtw_dequeue_recvbuf (_queue *queue)
}
#ifdef CONFIG_SDIO_HCI
_exit_critical_bh(&queue->lock, &irqL);
#else
_exit_critical_ex(&queue->lock, &irqL);
#endif/*#ifdef CONFIG_SDIO_HCI*/
return precvbuf;
@ -2539,59 +2514,7 @@ _func_exit_;
#endif
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
static void recvframe_expand_pkt(
struct adapter *padapter,
union recv_frame *prframe)
{
struct recv_frame_hdr *pfhdr;
_pkt *ppkt;
u8 shift_sz;
u32 alloc_sz;
pfhdr = &prframe->u.hdr;
// 6 is for IP header 8 bytes alignment in QoS packet case.
if (pfhdr->attrib.qos)
shift_sz = 6;
else
shift_sz = 0;
// for first fragment packet, need to allocate
// (1536 + RXDESC_SIZE + drvinfo_sz) to reassemble packet
// 8 is for skb->data 8 bytes alignment.
// alloc_sz = _RND(1536 + RXDESC_SIZE + pfhdr->attrib.drvinfosize + shift_sz + 8, 128);
alloc_sz = 1664; // round (1536 + 24 + 32 + shift_sz + 8) to 128 bytes alignment
//3 1. alloc new skb
// prepare extra space for 4 bytes alignment
ppkt = rtw_skb_alloc(alloc_sz);
if (!ppkt) return; // no way to expand
//3 2. Prepare new skb to replace & release old skb
// force ppkt->data at 8-byte alignment address
skb_reserve(ppkt, 8 - ((SIZE_PTR)ppkt->data & 7));
// force ip_hdr at 8-byte alignment address according to shift_sz
skb_reserve(ppkt, shift_sz);
// copy data to new pkt
_rtw_memcpy(skb_put(ppkt, pfhdr->len), pfhdr->rx_data, pfhdr->len);
rtw_skb_free(pfhdr->pkt);
// attach new pkt to recvframe
pfhdr->pkt = ppkt;
pfhdr->rx_head = ppkt->head;
pfhdr->rx_data = ppkt->data;
pfhdr->rx_tail = skb_tail_pointer(ppkt);
pfhdr->rx_end = skb_end_pointer(ppkt);
}
#endif
//perform defrag
union recv_frame * recvframe_defrag(struct adapter *adapter,_queue *defrag_q);
union recv_frame * recvframe_defrag(struct adapter *adapter,_queue *defrag_q)
{
_list *plist, *phead;
@ -2622,12 +2545,6 @@ _func_enter_;
return NULL;
}
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#ifndef CONFIG_SDIO_RX_COPY
recvframe_expand_pkt(adapter, prframe);
#endif
#endif
curfragnum++;
plist= get_list_head(defrag_q);

6
core/rtw_sreset.c
View file

@ -197,7 +197,6 @@ void sreset_restore_network_station(struct adapter *padapter)
{
u8 threshold;
#ifdef CONFIG_USB_HCI
// TH=1 => means that invalidate usb rx aggregation
// TH=0 => means that validate usb rx aggregation, use init value.
if(mlmepriv->htpriv.ht_option) {
@ -210,7 +209,6 @@ void sreset_restore_network_station(struct adapter *padapter)
threshold = 1;
rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
}
#endif
}
set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
@ -270,9 +268,7 @@ void sreset_stop_adapter(struct adapter *padapter)
rtw_cancel_all_timer(padapter);
/* TODO: OS and HCI independent */
#if defined(CONFIG_USB_HCI)
tasklet_kill(&pxmitpriv->xmit_tasklet);
#endif
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY))
rtw_scan_abort(padapter);
@ -300,9 +296,7 @@ void sreset_start_adapter(struct adapter *padapter)
}
/* TODO: OS and HCI independent */
#if defined(CONFIG_USB_HCI)
tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
#endif
_set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000);

82
core/rtw_xmit.c
View file

@ -27,11 +27,7 @@
#include <osdep_intf.h>
#include <circ_buf.h>
#include <ip.h>
#ifdef CONFIG_USB_HCI
#include <usb_ops.h>
#endif
static u8 P802_1H_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0xf8 };
static u8 RFC1042_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0x00 };
@ -196,13 +192,6 @@ _func_enter_;
}
}
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
pxmitbuf->phead = pxmitbuf->pbuf;
pxmitbuf->pend = pxmitbuf->pbuf + MAX_XMITBUF_SZ;
pxmitbuf->len = 0;
pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
#endif
pxmitbuf->flags = XMIT_VO_QUEUE;
rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmitbuf_queue.queue));
@ -288,13 +277,6 @@ _func_enter_;
goto exit;
}
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
pxmitbuf->phead = pxmitbuf->pbuf;
pxmitbuf->pend = pxmitbuf->pbuf + max_xmit_extbuf_size;
pxmitbuf->len = 0;
pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
#endif
rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue));
#ifdef DBG_XMIT_BUF_EXT
pxmitbuf->no=i;
@ -313,7 +295,6 @@ _func_enter_;
pxmitpriv->wmm_para_seq[i] = i;
}
#ifdef CONFIG_USB_HCI
pxmitpriv->txirp_cnt=1;
_rtw_init_sema(&(pxmitpriv->tx_retevt), 0);
@ -323,8 +304,6 @@ _func_enter_;
pxmitpriv->bkq_cnt = 0;
pxmitpriv->viq_cnt = 0;
pxmitpriv->voq_cnt = 0;
#endif
#ifdef CONFIG_XMIT_ACK
pxmitpriv->ack_tx = _FALSE;
@ -2270,7 +2249,7 @@ void rtw_count_tx_stats(struct adapter *padapter, struct xmit_frame *pxmitframe,
if ((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG)
{
pxmitpriv->tx_bytes += sz;
#if defined(CONFIG_USB_TX_AGGREGATION) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#if defined(CONFIG_USB_TX_AGGREGATION)
pmlmepriv->LinkDetectInfo.NumTxOkInPeriod += pxmitframe->agg_num;
#else
pmlmepriv->LinkDetectInfo.NumTxOkInPeriod++;
@ -2280,7 +2259,7 @@ void rtw_count_tx_stats(struct adapter *padapter, struct xmit_frame *pxmitframe,
if (psta)
{
pstats = &psta->sta_stats;
#if defined(CONFIG_USB_TX_AGGREGATION) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#if defined(CONFIG_USB_TX_AGGREGATION)
pstats->tx_pkts += pxmitframe->agg_num;
#else
pstats->tx_pkts++;
@ -2325,14 +2304,6 @@ _func_enter_;
pxmitbuf->priv_data = NULL;
//pxmitbuf->ext_tag = _TRUE;
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
pxmitbuf->len = 0;
pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
#endif
#ifdef CONFIG_PCI_HCI
pxmitbuf->len = 0;
#endif
if (pxmitbuf->sctx) {
DBG_871X("%s pxmitbuf->sctx is not NULL\n", __func__);
rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC);
@ -2412,16 +2383,6 @@ _func_enter_;
pxmitbuf->priv_data = NULL;
//pxmitbuf->ext_tag = _FALSE;
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
pxmitbuf->len = 0;
pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
pxmitbuf->agg_num = 0;
pxmitbuf->pg_num = 0;
#endif
#ifdef CONFIG_PCI_HCI
pxmitbuf->len = 0;
#endif
if (pxmitbuf->sctx) {
DBG_871X("%s pxmitbuf->sctx is not NULL\n", __func__);
rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC);
@ -2497,7 +2458,6 @@ void rtw_init_xmitframe(struct xmit_frame *pxframe)
pxframe->frame_tag = DATA_FRAMETAG;
#ifdef CONFIG_USB_HCI
pxframe->pkt = NULL;
pxframe->pkt_offset = 1;//default use pkt_offset to fill tx desc
@ -2505,13 +2465,6 @@ void rtw_init_xmitframe(struct xmit_frame *pxframe)
pxframe->agg_num = 1;
#endif
#endif //#ifdef CONFIG_USB_HCI
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
pxframe->pg_num = 1;
pxframe->agg_num = 1;
#endif
#ifdef CONFIG_XMIT_ACK
pxframe->ack_report = 0;
#endif
@ -2788,9 +2741,6 @@ struct xmit_frame* rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmi
struct adapter *padapter = pxmitpriv->adapter;
struct registry_priv *pregpriv = &padapter->registrypriv;
int i, inx[4];
#ifdef CONFIG_USB_HCI
// int j, tmp, acirp_cnt[4];
#endif
_func_enter_;
@ -2799,19 +2749,8 @@ _func_enter_;
if(pregpriv->wifi_spec==1)
{
int j, tmp, acirp_cnt[4];
#if 0
if(flags<XMIT_QUEUE_ENTRY)
{
//priority exchange according to the completed xmitbuf flags.
inx[flags] = 0;
inx[0] = flags;
}
#endif
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
for(j=0; j<4; j++)
inx[j] = pxmitpriv->wmm_para_seq[j];
#endif
}
_enter_critical_bh(&pxmitpriv->lock, &irqL0);
@ -4041,14 +3980,7 @@ void enqueue_pending_xmitbuf(
rtw_list_insert_tail(&pxmitbuf->list, get_list_head(pqueue));
_exit_critical_bh(&pqueue->lock, &irql);
#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_CONCURRENT_MODE)
if (pri_adapter->adapter_type > PRIMARY_ADAPTER)
pri_adapter = pri_adapter->pbuddy_adapter;
#endif //SDIO_HCI + CONCURRENT
_rtw_up_sema(&(pri_adapter->xmitpriv.xmit_sema));
}
struct xmit_buf* dequeue_pending_xmitbuf(
@ -4084,9 +4016,7 @@ struct xmit_buf* dequeue_pending_xmitbuf_under_survey(
{
_irqL irql;
struct xmit_buf *pxmitbuf;
#ifdef CONFIG_USB_HCI
struct xmit_frame *pxmitframe;
#endif
_queue *pqueue;
@ -4108,19 +4038,11 @@ struct xmit_buf* dequeue_pending_xmitbuf_under_survey(
pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);
#ifdef CONFIG_USB_HCI
pxmitframe = (struct xmit_frame*)pxmitbuf->priv_data;
if(pxmitframe)
{
type = GetFrameSubType(pxmitbuf->pbuf + TXDESC_SIZE + pxmitframe->pkt_offset * PACKET_OFFSET_SZ);
}
else
{
DBG_871X("%s, !!!ERROR!!! For USB, TODO ITEM \n", __FUNCTION__);
}
#else
type = GetFrameSubType(pxmitbuf->pbuf + TXDESC_OFFSET);
#endif
if ((type == WIFI_PROBEREQ) ||
(type == WIFI_DATA_NULL) ||

53
hal/HalPwrSeqCmd.c
View file

@ -34,11 +34,6 @@ Major Change History:
--*/
#include <HalPwrSeqCmd.h>
#ifdef CONFIG_SDIO_HCI
#include <sdio_ops.h>
#elif defined(CONFIG_GSPI_HCI)
#include <gspi_ops.h>
#endif
//
// Description:
@ -93,56 +88,22 @@ u8 HalPwrSeqCmdParsing(
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n"));
offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
#ifdef CONFIG_SDIO_HCI
//
// <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface
// 2011.07.07.
//
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
{
// Read Back SDIO Local value
value = SdioLocalCmd52Read1Byte(padapter, offset);
// Read the value from system register
value = rtw_read8(padapter, offset);
value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
// Write Back SDIO Local value
SdioLocalCmd52Write1Byte(padapter, offset, value);
}
else
#endif
{
#ifdef CONFIG_GSPI_HCI
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
offset = SPI_LOCAL_OFFSET | offset;
#endif
// Read the value from system register
value = rtw_read8(padapter, offset);
value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
// Write the value back to sytem register
rtw_write8(padapter, offset, value);
}
// Write the value back to sytem register
rtw_write8(padapter, offset, value);
break;
case PWR_CMD_POLLING:
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n"));
bPollingBit = _FALSE;
offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
#ifdef CONFIG_GSPI_HCI
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
offset = SPI_LOCAL_OFFSET | offset;
#endif
do {
#ifdef CONFIG_SDIO_HCI
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
value = SdioLocalCmd52Read1Byte(padapter, offset);
else
#endif
value = rtw_read8(padapter, offset);
value = rtw_read8(padapter, offset);
value &= GET_PWR_CFG_MASK(PwrCfgCmd);
if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))

10
hal/hal_intf.c
View file

@ -23,16 +23,8 @@
#include <osdep_service.h>
#include <drv_types.h>
#include <rtw_byteorder.h>
#include <hal_intf.h>
#ifdef CONFIG_SDIO_HCI
#include <sdio_hal.h>
#elif defined(CONFIG_USB_HCI)
#include <usb_hal.h>
#elif defined(CONFIG_GSPI_HCI)
#include <gspi_hal.h>
#endif
#include <usb_hal.h>
void rtw_hal_chip_configure(struct adapter *padapter)
{

14
hal/odm.c
View file

@ -4160,7 +4160,6 @@ odm_DynamicTxPowerInit(
pdmpriv->bDynamicTxPowerEnable = _FALSE;
#if (RTL8192C_SUPPORT==1)
#ifdef CONFIG_USB_HCI
#ifdef CONFIG_INTEL_PROXIM
if((pHalData->BoardType == BOARD_USB_High_PA)||(Adapter->proximity.proxim_support==_TRUE))
@ -4174,9 +4173,6 @@ odm_DynamicTxPowerInit(
pdmpriv->bDynamicTxPowerEnable = _TRUE;
}
else
#else
pdmpriv->bDynamicTxPowerEnable = _FALSE;
#endif
#endif
pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal;
@ -7528,25 +7524,17 @@ odm_EdcaTurboCheckCE(
}
#endif
#ifdef CONFIG_PCI_HCI
if(IS_92C_SERIAL(pHalData->VersionID))
{
edca_param = 0x60a42b;
}
else
{
edca_param = 0x6ea42b;
}
#endif
rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param);
pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
}
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _TRUE;
}
else
{
} else {
//
// Turn Off EDCA turbo here.
// Restore original EDCA according to the declaration of AP.

11
hal/odm_types.h
View file

@ -208,16 +208,7 @@ typedef enum _RT_SPINLOCK_TYPE{
#define ps8Byte s64*
#endif
#ifdef CONFIG_USB_HCI
#define DEV_BUS_TYPE RT_USB_INTERFACE
#elif defined(CONFIG_PCI_HCI)
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#elif defined(CONFIG_SDIO_HCI)
#define DEV_BUS_TYPE RT_SDIO_INTERFACE
#elif defined(CONFIG_GSPI_HCI)
#define DEV_BUS_TYPE RT_SDIO_INTERFACE
#endif
#define DEV_BUS_TYPE RT_USB_INTERFACE
#if defined(CONFIG_LITTLE_ENDIAN)
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE

7
hal/rtl8188e_cmd.c
View file

@ -1423,14 +1423,7 @@ _func_enter_;
pwowlan_parm.mode |=FW_WOWLAN_DEAUTH_WAKEUP;
//DataPinWakeUp
#ifdef CONFIG_USB_HCI
pwowlan_parm.gpio_index=0x0;
#endif //CONFIG_USB_HCI
#ifdef CONFIG_SDIO_HCI
pwowlan_parm.gpio_index = 0x80;
#endif //CONFIG_SDIO_HCI
#ifdef CONFIG_GPIO_WAKEUP
pwowlan_parm.gpio_index = gpio_wake_pin;

132
hal/rtl8188e_dm.c
View file

@ -97,7 +97,6 @@ static void dm_CheckPbcGPIO(struct adapter *padapter)
if(!padapter->registrypriv.hw_wps_pbc)
return;
#ifdef CONFIG_USB_HCI
tmp1byte = rtw_read8(padapter, GPIO_IO_SEL);
tmp1byte |= (HAL_8188E_HW_GPIO_WPS_BIT);
rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); //enable GPIO[2] as output mode
@ -118,19 +117,6 @@ static void dm_CheckPbcGPIO(struct adapter *padapter)
{
bPbcPressed = _TRUE;
}
#else
tmp1byte = rtw_read8(padapter, GPIO_IN);
//RT_TRACE(COMP_IO, DBG_TRACE, ("dm_CheckPbcGPIO - %x\n", tmp1byte));
if (tmp1byte == 0xff || padapter->init_adpt_in_progress)
return ;
if((tmp1byte&HAL_8188E_HW_GPIO_WPS_BIT)==0)
{
bPbcPressed = _TRUE;
}
#endif
if( _TRUE == bPbcPressed)
{
// Here we only set bPbcPressed to true
@ -154,91 +140,6 @@ static void dm_CheckPbcGPIO(struct adapter *padapter)
}
}
#ifdef CONFIG_PCI_HCI
//
// Description:
// Perform interrupt migration dynamically to reduce CPU utilization.
//
// Assumption:
// 1. Do not enable migration under WIFI test.
//
// Created by Roger, 2010.03.05.
//
VOID
dm_InterruptMigration(
IN struct adapter *Adapter
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
BOOLEAN bCurrentIntMt, bCurrentACIntDisable;
BOOLEAN IntMtToSet = _FALSE;
BOOLEAN ACIntToSet = _FALSE;
// Retrieve current interrupt migration and Tx four ACs IMR settings first.
bCurrentIntMt = pHalData->bInterruptMigration;
bCurrentACIntDisable = pHalData->bDisableTxInt;
//
// <Roger_Notes> Currently we use busy traffic for reference instead of RxIntOK counts to prevent non-linear Rx statistics
// when interrupt migration is set before. 2010.03.05.
//
if(!Adapter->registrypriv.wifi_spec &&
(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) &&
pmlmepriv->LinkDetectInfo.bHigherBusyTraffic)
{
IntMtToSet = _TRUE;
// To check whether we should disable Tx interrupt or not.
if(pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic )
ACIntToSet = _TRUE;
}
//Update current settings.
if( bCurrentIntMt != IntMtToSet ){
DBG_8192C("%s(): Update interrrupt migration(%d)\n",__FUNCTION__,IntMtToSet);
if(IntMtToSet)
{
//
// <Roger_Notes> Set interrrupt migration timer and corresponging Tx/Rx counter.
// timer 25ns*0xfa0=100us for 0xf packets.
// 2010.03.05.
//
rtw_write32(Adapter, REG_INT_MIG, 0xff000fa0);// 0x306:Rx, 0x307:Tx
pHalData->bInterruptMigration = IntMtToSet;
}
else
{
// Reset all interrupt migration settings.
rtw_write32(Adapter, REG_INT_MIG, 0);
pHalData->bInterruptMigration = IntMtToSet;
}
}
/*if( bCurrentACIntDisable != ACIntToSet ){
DBG_8192C("%s(): Update AC interrrupt(%d)\n",__FUNCTION__,ACIntToSet);
if(ACIntToSet) // Disable four ACs interrupts.
{
//
// <Roger_Notes> Disable VO, VI, BE and BK four AC interrupts to gain more efficient CPU utilization.
// When extremely highly Rx OK occurs, we will disable Tx interrupts.
// 2010.03.05.
//
UpdateInterruptMask8192CE( Adapter, 0, RT_AC_INT_MASKS );
pHalData->bDisableTxInt = ACIntToSet;
}
else// Enable four ACs interrupts.
{
UpdateInterruptMask8192CE( Adapter, RT_AC_INT_MASKS, 0 );
pHalData->bDisableTxInt = ACIntToSet;
}
}*/
}
#endif
//
// Initialize GPIO setting registers
//
@ -301,15 +202,6 @@ static void Init_ODM_ComInfo_88E(struct adapter *Adapter)
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP,IS_NORMAL_CHIP(pHalData->VersionID));
#if 0
//#ifdef CONFIG_USB_HCI
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_BOARD_TYPE,pHalData->BoardType);
if(pHalData->BoardType == BOARD_USB_High_PA){
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_EXT_LNA,_TRUE);
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_EXT_PA,_TRUE);
}
#endif
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_PATCH_ID,pHalData->CustomerID);
// ODM_CMNINFO_BINHCT_TEST only for MP Team
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_BWIFI_TEST,Adapter->registrypriv.wifi_spec);
@ -434,9 +326,7 @@ rtl8188e_InitHalDm(
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
u8 i;
#ifdef CONFIG_USB_HCI
dm_InitGPIOSetting(Adapter);
#endif
pdmpriv->DM_Type = DM_Type_ByDriver;
pdmpriv->DMFlag = DYNAMIC_FUNC_DISABLE;
@ -490,21 +380,6 @@ rtl8188e_HalDmWatchDog(
// Calculate Tx/Rx statistics.
//
dm_CheckStatistics(Adapter);
//
// Dynamically switch RTS/CTS protection.
//
//dm_CheckProtection(Adapter);
#ifdef CONFIG_PCI_HCI
// 20100630 Joseph: Disable Interrupt Migration mechanism temporarily because it degrades Rx throughput.
// Tx Migration settings.
//dm_InterruptMigration(Adapter);
//if(Adapter->HalFunc.TxCheckStuckHandler(Adapter))
// PlatformScheduleWorkItem(&(GET_HAL_DATA(Adapter)->HalResetWorkItem));
#endif
}
@ -544,13 +419,6 @@ skip_dm:
// Check GPIO to determine current RF on/off and Pbc status.
// Check Hardware Radio ON/OFF or not
#ifdef CONFIG_PCI_HCI
if(pHalData->bGpioHwWpsPbc)
#endif
{
//temp removed
//dm_CheckPbcGPIO(Adapter);
}
return;
}

87
hal/rtl8188e_hal_init.c
View file

@ -28,9 +28,8 @@
#include <rtw_iol.h>
#if defined(CONFIG_IOL)
#ifdef CONFIG_USB_HCI
#include <usb_ops.h>
#endif
static void iol_mode_enable(struct adapter *padapter, u8 enable)
{
u8 reg_0xf0 = 0;
@ -487,7 +486,6 @@ int rtl8188e_IOL_exec_cmds_sync(struct adapter *adapter, struct xmit_frame *xmit
//printk("===> %s ,bndy_cnt = %d \n",__FUNCTION__,bndy_cnt);
if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS)
goto exit;
#ifdef CONFIG_USB_HCI
{
struct pkt_attrib *pattrib = &xmit_frame->attrib;
if(rtw_usb_bulk_size_boundary(adapter,TXDESC_SIZE+pattrib->last_txcmdsz))
@ -496,11 +494,6 @@ int rtl8188e_IOL_exec_cmds_sync(struct adapter *adapter, struct xmit_frame *xmit
goto exit;
}
}
#endif //CONFIG_USB_HCI
//rtw_IOL_cmd_buf_dump(adapter,xmit_frame->attrib.pktlen+TXDESC_OFFSET,xmit_frame->buf_addr);
//rtw_hal_mgnt_xmit(adapter, xmit_frame);
//rtw_dump_xframe_sync(adapter, xmit_frame);
dump_mgntframe_and_wait(adapter, xmit_frame, max_wating_ms);
@ -612,14 +605,7 @@ _BlockWrite(
u32 remainSize_p1 = 0, remainSize_p2 = 0;
u8 *bufferPtr = (u8*)buffer;
u32 i=0, offset=0;
#ifdef CONFIG_PCI_HCI
u8 remainFW[4] = {0, 0, 0, 0};
u8 *p = NULL;
#endif
#ifdef CONFIG_USB_HCI
blockSize_p1 = MAX_REG_BOLCK_SIZE;
#endif
//3 Phase #1
blockCount_p1 = buffSize / blockSize_p1;
@ -633,35 +619,11 @@ _BlockWrite(
for (i = 0; i < blockCount_p1; i++)
{
#ifdef CONFIG_USB_HCI
ret = rtw_writeN(padapter, (FW_8188E_START_ADDRESS + i * blockSize_p1), blockSize_p1, (bufferPtr + i * blockSize_p1));
#else
ret = rtw_write32(padapter, (FW_8188E_START_ADDRESS + i * blockSize_p1), le32_to_cpu(*((u32*)(bufferPtr + i * blockSize_p1))));
#endif
if(ret == _FAIL)
goto exit;
}
#ifdef CONFIG_PCI_HCI
p = (u8*)((u32*)(bufferPtr + blockCount_p1 * blockSize_p1));
if (remainSize_p1) {
switch (remainSize_p1) {
case 0:
break;
case 3:
remainFW[2]=*(p+2);
case 2:
remainFW[1]=*(p+1);
case 1:
remainFW[0]=*(p);
ret = rtw_write32(padapter, (FW_8188E_START_ADDRESS + blockCount_p1 * blockSize_p1),
le32_to_cpu(*(u32*)remainFW));
}
return ret;
}
#endif
//3 Phase #2
if (remainSize_p1)
{
@ -676,14 +638,12 @@ _BlockWrite(
(buffSize-offset), blockSize_p2 ,blockCount_p2, remainSize_p2));
}
#ifdef CONFIG_USB_HCI
for (i = 0; i < blockCount_p2; i++) {
ret = rtw_writeN(padapter, (FW_8188E_START_ADDRESS + offset + i*blockSize_p2), blockSize_p2, (bufferPtr + offset + i*blockSize_p2));
if(ret == _FAIL)
goto exit;
}
#endif
}
//3 Phase #3
@ -760,14 +720,7 @@ _WriteFW(
u32 page, offset;
u8 *bufferPtr = (u8*)buffer;
#ifdef CONFIG_PCI_HCI
// 20100120 Joseph: Add for 88CE normal chip.
// Fill in zero to make firmware image to dword alignment.
// _FillDummy(bufferPtr, &size);
#endif
pageNums = size / MAX_PAGE_SIZE ;
//RT_ASSERT((pageNums <= 4), ("Page numbers should not greater then 4 \n"));
remainSize = size % MAX_PAGE_SIZE;
for (page = 0; page < pageNums; page++) {
@ -2814,34 +2767,12 @@ void rtl8188e_SetHalODMVar(
void rtl8188e_start_thread(struct adapter *padapter)
{
#ifdef CONFIG_SDIO_HCI
#ifndef CONFIG_SDIO_TX_TASKLET
struct xmit_priv *xmitpriv = &padapter->xmitpriv;
xmitpriv->SdioXmitThread = kthread_run(rtl8188es_xmit_thread, padapter, "RTWHALXT");
if (IS_ERR(xmitpriv->SdioXmitThread))
{
RT_TRACE(_module_hal_xmit_c_, _drv_err_, ("%s: start rtl8188es_xmit_thread FAIL!!\n", __FUNCTION__));
}
#endif
#endif
}
void rtl8188e_stop_thread(struct adapter *padapter)
{
#ifdef CONFIG_SDIO_HCI
#ifndef CONFIG_SDIO_TX_TASKLET
struct xmit_priv *xmitpriv = &padapter->xmitpriv;
// stop xmit_buf_thread
if (xmitpriv->SdioXmitThread ) {
_rtw_up_sema(&xmitpriv->SdioXmitSema);
_rtw_down_sema(&xmitpriv->SdioXmitTerminateSema);
xmitpriv->SdioXmitThread = 0;
}
#endif
#endif
}
void hal_notch_filter_8188e(struct adapter *adapter, bool enable)
{
if (enable) {
@ -2930,7 +2861,6 @@ u8 GetEEPROMSize8188E(struct adapter *padapter)
return size;
}
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_PCI_HCI)
//-------------------------------------------------------------------------
//
// LLT R/W/Init function
@ -3049,8 +2979,6 @@ s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy)
return status;
}
#endif
void
Hal_InitPGData88E(struct adapter *padapter)
@ -3396,12 +3324,7 @@ void Hal_ReadPowerSavingMode88E(
// decide hw if support remote wakeup function
// if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume
#ifdef CONFIG_USB_HCI
pwrctl->bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0] & BIT1)?_TRUE :_FALSE;
#endif //CONFIG_USB_HCI
//if(SUPPORT_HW_RADIO_DETECT(Adapter))
//Adapter->registrypriv.usbss_enable = pwrctl->bSupportRemoteWakeup ;
DBG_8192C("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) ,bSupportRemoteWakeup(%x)\n",__FUNCTION__,
pwrctl->bHWPwrPindetect, pwrctl->bHWPowerdown, pwrctl->bSupportRemoteWakeup);
@ -3789,11 +3712,5 @@ void SetBcnCtrlReg(
pHalData->RegBcnCtrlVal |= SetBits;
pHalData->RegBcnCtrlVal &= ~ClearBits;
#if 0
//#ifdef CONFIG_SDIO_HCI
if (pHalData->sdio_himr & (SDIO_HIMR_TXBCNOK_MSK | SDIO_HIMR_TXBCNERR_MSK))
pHalData->RegBcnCtrlVal |= EN_TXBCN_RPT;
#endif
rtw_write8(padapter, REG_BCN_CTRL, (u8)pHalData->RegBcnCtrlVal);
}

145
hal/rtl8188e_phycfg.c
View file

@ -692,31 +692,11 @@ rtl8188e_PHY_QueryRFReg(
return 0;
#endif
//RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryRFReg(): RegAddr(%#lx), eRFPath(%#x), BitMask(%#lx)\n", RegAddr, eRFPath,BitMask));
#ifdef CONFIG_USB_HCI
//PlatformAcquireMutex(&pHalData->mxRFOperate);
#else
//_enter_critical(&pHalData->rf_lock, &irqL);
#endif
Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);
BitShift = phy_CalculateBitShift(BitMask);
Readback_Value = (Original_Value & BitMask) >> BitShift;
#ifdef CONFIG_USB_HCI
//PlatformReleaseMutex(&pHalData->mxRFOperate);
#else
//_exit_critical(&pHalData->rf_lock, &irqL);
#endif
//RTPRINT(FPHY, PHY_RFR, ("RFR-%d MASK=0x%lx Addr[0x%lx]=0x%lx\n", eRFPath, BitMask, RegAddr, Original_Value));//BitMask(%#lx),BitMask,
//RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_QueryRFReg(): RegAddr(%#lx), eRFPath(%#x), Original_Value(%#lx)\n",
// RegAddr, eRFPath, Original_Value));
return (Readback_Value);
}
@ -757,19 +737,6 @@ rtl8188e_PHY_SetRFReg(
return;
#endif
//RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",
// RegAddr, BitMask, Data, eRFPath));
//RTPRINT(FINIT, INIT_RF, ("PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",
// RegAddr, BitMask, Data, eRFPath));
#ifdef CONFIG_USB_HCI
//PlatformAcquireMutex(&pHalData->mxRFOperate);
#else
//_enter_critical(&pHalData->rf_lock, &irqL);
#endif
// RF data is 12 bits only
if (BitMask != bRFRegOffsetMask)
{
@ -779,18 +746,6 @@ rtl8188e_PHY_SetRFReg(
}
phy_RFSerialWrite(Adapter, eRFPath, RegAddr, Data);
#ifdef CONFIG_USB_HCI
//PlatformReleaseMutex(&pHalData->mxRFOperate);
#else
//_exit_critical(&pHalData->rf_lock, &irqL);
#endif
//PHY_QueryRFReg(Adapter,eRFPath,RegAddr,BitMask);
//RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",
// RegAddr, BitMask, Data, eRFPath));
}
@ -1093,29 +1048,6 @@ phy_ConfigBBExternalPA(
IN struct adapter * Adapter
)
{
#ifdef CONFIG_USB_HCI
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u16 i=0;
u32 temp=0;
if(!pHalData->ExternalPA)
{
return;
}
// 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the
// same code as SU. It is already updated in PHY_REG_1T_HP.txt.
#if 0
PHY_SetBBReg(Adapter, 0xee8, BIT28, 1);
temp = PHY_QueryBBReg(Adapter, 0x860, bMaskDWord);
temp |= (BIT26|BIT21|BIT10|BIT5);
PHY_SetBBReg(Adapter, 0x860, bMaskDWord, temp);
PHY_SetBBReg(Adapter, 0x870, BIT10, 0);
PHY_SetBBReg(Adapter, 0xc80, bMaskDWord, 0x20000080);
PHY_SetBBReg(Adapter, 0xc88, bMaskDWord, 0x40000100);
#endif
#endif
}
/*-----------------------------------------------------------------------------
@ -1662,36 +1594,7 @@ PHY_BBConfig8188E(
rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);
#ifdef CONFIG_USB_HCI
rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
#else
rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB);
#endif
#if 0
#ifdef CONFIG_USB_HCI
//To Fix MAC loopback mode fail. Suggested by SD4 Johnny. 2010.03.23.
rtw_write8(Adapter, REG_LDOHCI12_CTRL, 0x0f);
rtw_write8(Adapter, 0x15, 0xe9);
#endif
rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80);
#endif
#ifdef CONFIG_USB_HCI
//rtw_write8(Adapter, 0x15, 0xe9);
#endif
#ifdef CONFIG_PCI_HCI
// Force use left antenna by default for 88C.
// if(!IS_92C_SERIAL(pHalData->VersionID) || IS_92C_1T2R(pHalData->VersionID))
if(Adapter->ledpriv.LedStrategy != SW_LED_MODE10)
{
RegVal = rtw_read32(Adapter, REG_LEDCFG0);
rtw_write32(Adapter, REG_LEDCFG0, RegVal|BIT23);
}
#endif
//
// Config BB and AGC
@ -1801,27 +1704,11 @@ PHY_ConfigRFExternalPA(
)
{
int rtStatus = _SUCCESS;
#ifdef CONFIG_USB_HCI
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u16 i=0;
if(!pHalData->ExternalPA)
{
return rtStatus;
}
// 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the
// same code as SU. It is already updated in radio_a_1T_HP.txt.
#if 0
//add for SU High Power PA
for(i = 0;i<HighPowerRadioAArrayLen; i=i+2)
{
RT_TRACE(COMP_INIT, DBG_LOUD, ("External PA, write RF 0x%lx=0x%lx\n", Rtl8192S_HighPower_RadioA_Array[i], Rtl8192S_HighPower_RadioA_Array[i+1]));
PHY_SetRFReg(Adapter, eRFPath, Rtl8192S_HighPower_RadioA_Array[i], bRFRegOffsetMask, Rtl8192S_HighPower_RadioA_Array[i+1]);
}
#endif
#endif
return rtStatus;
}
//****************************************
@ -1973,19 +1860,11 @@ rtl8188e_PHY_ConfigRFWithHeaderFile(
{
if(Rtl819XRadioB_Array_Table[i] == 0xfe)
{ // Deay specific ms. Only RF configuration require delay.
#if 0//#ifdef CONFIG_USB_HCI
#ifdef CONFIG_LONG_DELAY_ISSUE
rtw_msleep_os(1000);
#else
rtw_mdelay_os(1000);
#endif
#else
#ifdef CONFIG_LONG_DELAY_ISSUE
rtw_msleep_os(50);
#else
rtw_mdelay_os(50);
#endif
#endif
}
else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
rtw_mdelay_os(5);
@ -3505,7 +3384,6 @@ _PHY_DumpRFReg(IN struct adapter *pAdapter)
// Move from phycfg.c to gen.c to be code independent later
//
//-------------------------Move to other DIR later----------------------------*/
#ifdef CONFIG_USB_HCI
//
// Description:
@ -3517,35 +3395,12 @@ DumpBBDbgPort_92CU(
IN struct adapter * Adapter
)
{
//RT_TRACE(COMP_SEND, DBG_WARNING, ("\n>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"));
//RT_TRACE(COMP_SEND, DBG_WARNING, ("BaseBand Debug Ports:\n"));
PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0000);
//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0803);
//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0a06);
//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0007);
//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0100);
PHY_SetBBReg(Adapter, 0x0a28, 0x00ff0000, 0x000f0000);
//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0100);
PHY_SetBBReg(Adapter, 0x0a28, 0x00ff0000, 0x00150000);
//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0x800, PHY_QueryBBReg(Adapter, 0x0800, bMaskDWord)));
//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0x900, PHY_QueryBBReg(Adapter, 0x0900, bMaskDWord)));
//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa00, PHY_QueryBBReg(Adapter, 0x0a00, bMaskDWord)));
//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa54, PHY_QueryBBReg(Adapter, 0x0a54, bMaskDWord)));
//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa58, PHY_QueryBBReg(Adapter, 0x0a58, bMaskDWord)));
}
#endif

2
hal/rtl8188e_rf6052.c
View file

@ -235,11 +235,9 @@ rtl8188e_PHY_RF6052SetCckTxPower(
TxAGC[idx1] =
pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
#ifdef CONFIG_USB_HCI
// 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20.
if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA)
TxAGC[idx1] = 0x20;
#endif
}
}
}

3
hal/rtl8188e_sreset.c
View file

@ -38,7 +38,6 @@ void rtl8188e_sreset_xmit_status_check(struct adapter *padapter)
DBG_871X("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status);
rtw_hal_sreset_reset(padapter);
}
#ifdef CONFIG_USB_HCI
//total xmit irp = 4
//DBG_8192C("==>%s free_xmitbuf_cnt(%d),txirp_cnt(%d)\n",__FUNCTION__,pxmitpriv->free_xmitbuf_cnt,pxmitpriv->txirp_cnt);
//if(pxmitpriv->txirp_cnt == NR_XMITBUFF+1)
@ -69,8 +68,6 @@ void rtl8188e_sreset_xmit_status_check(struct adapter *padapter)
}
}
}
#endif //CONFIG_USB_HCI
if (psrtpriv->dbg_trigger_point == SRESET_TGP_XMIT_STATUS) {
psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
rtw_hal_sreset_reset(padapter);

2
hal/rtl8188eu_xmit.c
View file

@ -121,11 +121,9 @@ void rtl8188e_fill_fake_txdesc(
//offset 16
ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
// USB interface drop packet if the checksum of descriptor isn't correct.
// Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.).
rtl8188eu_cal_txdesc_chksum(ptxdesc);
#endif
}
void fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc)

26
hal/usb_halinit.c
View file

@ -31,12 +31,6 @@
#include <rtw_iol.h>
#endif
#ifndef CONFIG_USB_HCI
#error "CONFIG_USB_HCI shall be on!\n"
#endif
#include <usb_ops.h>
#include <usb_hal.h>
#include <usb_osintf.h>
@ -2902,7 +2896,6 @@ readAdapterInfo_8188EU(
IN struct adapter *padapter
)
{
#if 1
EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
/* parse the eeprom/efuse content */
@ -2928,28 +2921,9 @@ readAdapterInfo_8188EU(
// The following part initialize some vars by PG info.
//
Hal_InitChannelPlan(padapter);
#if defined(CONFIG_WOWLAN) && defined(CONFIG_SDIO_HCI)
Hal_DetectWoWMode(padapter);
#endif //CONFIG_WOWLAN && CONFIG_SDIO_HCI
Hal_CustomizeByCustomerID_8188EU(padapter);
_ReadLEDSetting(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
#else
#ifdef CONFIG_INTEL_PROXIM
/* for intel proximity */
if (pHalData->rf_type== RF_1T1R) {
Adapter->proximity.proxim_support = _TRUE;
} else if (pHalData->rf_type== RF_2T2R) {
if ((pHalData->EEPROMPID == 0x8186) &&
(pHalData->EEPROMVID== 0x0bda))
Adapter->proximity.proxim_support = _TRUE;
} else {
Adapter->proximity.proxim_support = _FALSE;
}
#endif //CONFIG_INTEL_PROXIM
#endif
}
static void _ReadPROMContent(

4
include/Hal8188EPhyCfg.h
View file

@ -33,11 +33,7 @@
#define IQK_BB_REG_NUM 9
#define HP_THERMAL_NUM 8
#ifdef CONFIG_PCI_HCI
#define MAX_AGGR_NUM 0x0B
#else
#define MAX_AGGR_NUM 0x07
#endif // CONFIG_PCI_HCI
/*--------------------------Define Parameters-------------------------------*/

27
include/Hal8192CPhyCfg.h
View file

@ -47,34 +47,7 @@
#define Reset_Cnt_Limit 3
#ifdef CONFIG_PCI_HCI
#define MAX_AGGR_NUM 0x0A0A
#else
#define MAX_AGGR_NUM 0x0909
#endif
#ifdef CONFIG_PCI_HCI
#define SET_RTL8192SE_RF_SLEEP(_pAdapter) \
{ \
u1Byte u1bTmp; \
u1bTmp = PlatformEFIORead1Byte(_pAdapter, REG_LDOV12D_CTRL); \
u1bTmp |= BIT0; \
PlatformEFIOWrite1Byte(_pAdapter, REG_LDOV12D_CTRL, u1bTmp); \
PlatformEFIOWrite1Byte(_pAdapter, REG_SPS_OCP_CFG, 0x0); \
PlatformEFIOWrite1Byte(_pAdapter, TXPAUSE, 0xFF); \
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \
delay_us(100); \
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \
PlatformEFIOWrite1Byte(_pAdapter, PHY_CCA, 0x0); \
delay_us(10); \
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x37FC); \
delay_us(10); \
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \
delay_us(10); \
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \
}
#endif
/*--------------------------Define Parameters-------------------------------*/

23
include/Hal8192DPhyCfg.h
View file

@ -48,29 +48,6 @@
#define Reset_Cnt_Limit 3
#ifdef CONFIG_PCI_HCI
#define SET_RTL8192SE_RF_SLEEP(_pAdapter) \
{ \
u1Byte u1bTmp; \
u1bTmp = PlatformEFIORead1Byte(_pAdapter, REG_LDOV12D_CTRL); \
u1bTmp |= BIT0; \
PlatformEFIOWrite1Byte(_pAdapter, REG_LDOV12D_CTRL, u1bTmp); \
PlatformEFIOWrite1Byte(_pAdapter, REG_SPS_OCP_CFG, 0x0); \
PlatformEFIOWrite1Byte(_pAdapter, TXPAUSE, 0xFF); \
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \
delay_us(100); \
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \
PlatformEFIOWrite1Byte(_pAdapter, PHY_CCA, 0x0); \
delay_us(10); \
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x37FC); \
delay_us(10); \
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \
delay_us(10); \
PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \
}
#endif
/*--------------------------Define Parameters-------------------------------*/

62
include/drv_types.h
View file

@ -218,16 +218,6 @@ struct registry_priv
#define BSSID_OFT(field) ((ULONG)FIELD_OFFSET(WLAN_BSSID_EX,field))
#define BSSID_SZ(field) sizeof(((PWLAN_BSSID_EX) 0)->field)
#ifdef CONFIG_SDIO_HCI
#include <drv_types_sdio.h>
#define INTF_DATA SDIO_DATA
#elif defined(CONFIG_GSPI_HCI)
#include <drv_types_gspi.h>
#define INTF_DATA GSPI_DATA
#endif
#ifdef CONFIG_CONCURRENT_MODE
#define is_primary_adapter(adapter) (adapter->adapter_type == PRIMARY_ADAPTER)
#else
@ -289,8 +279,6 @@ struct dvobj_priv
/*-------- below is for USB INTERFACE --------*/
#ifdef CONFIG_USB_HCI
u8 nr_endpoint;
u8 ishighspeed;
u8 RtNumInPipes;
@ -312,45 +300,6 @@ struct dvobj_priv
struct usb_interface *pusbintf;
struct usb_device *pusbdev;
#endif//CONFIG_USB_HCI
/*-------- below is for PCIE INTERFACE --------*/
#ifdef CONFIG_PCI_HCI
struct pci_dev *ppcidev;
//PCI MEM map
unsigned long pci_mem_end; /* shared mem end */
unsigned long pci_mem_start; /* shared mem start */
//PCI IO map
unsigned long pci_base_addr; /* device I/O address */
//PciBridge
struct pci_priv pcipriv;
u16 irqline;
u8 irq_enabled;
RT_ISR_CONTENT isr_content;
_lock irq_th_lock;
//ASPM
u8 const_pci_aspm;
u8 const_amdpci_aspm;
u8 const_hwsw_rfoff_d3;
u8 const_support_pciaspm;
// pci-e bridge */
u8 const_hostpci_aspm_setting;
// pci-e device */
u8 const_devicepci_aspm_setting;
u8 b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00.
u8 b_support_backdoor;
u8 bdma64;
#endif//CONFIG_PCI_HCI
};
#define dvobj_to_pwrctl(dvobj) (&(dvobj->pwrctl_priv))
@ -360,18 +309,7 @@ static struct device *dvobj_to_dev(struct dvobj_priv *dvobj)
{
/* todo: get interface type from dvobj and the return the dev accordingly */
#ifdef CONFIG_USB_HCI
return &dvobj->pusbintf->dev;
#endif
#ifdef CONFIG_SDIO_HCI
return &dvobj->intf_data.func->dev;
#endif
#ifdef CONFIG_GSPI_HCI
return &dvobj->intf_data.func->dev;
#endif
#ifdef CONFIG_PCI_HCI
return &dvobj->ppcidev->dev;
#endif
}
enum _IFACE_TYPE {

18
include/drv_types_ce.h
View file

@ -60,33 +60,15 @@ typedef struct _MP_REG_ENTRY
u32 Max; // maximum value allowed
} MP_REG_ENTRY, *PMP_REG_ENTRY;
#ifdef CONFIG_USB_HCI
typedef struct _USB_EXTENSION {
LPCUSB_FUNCS _lpUsbFuncs;
USB_HANDLE _hDevice;
PVOID pAdapter;
#if 0
USB_ENDPOINT_DESCRIPTOR _endpACLIn;
USB_ENDPOINT_DESCRIPTOR _endpACLOutHigh;
USB_ENDPOINT_DESCRIPTOR _endpACLOutNormal;
USB_PIPE pPipeIn;
USB_PIPE pPipeOutNormal;
USB_PIPE pPipeOutHigh;
#endif
} USB_EXTENSION, *PUSB_EXTENSION;
#endif
typedef struct _OCTET_STRING{
u8 *Octet;
u16 Length;
} OCTET_STRING, *POCTET_STRING;
#endif

6
include/hal_intf.h
View file

@ -24,11 +24,6 @@
#include <osdep_service.h>
#include <drv_types.h>
#ifdef CONFIG_PCI_HCI
#include <pci_hal.h>
#endif
enum RTL871X_HCI_TYPE {
RTW_PCIE = BIT0,
RTW_USB = BIT1,
@ -37,7 +32,6 @@ enum RTL871X_HCI_TYPE {
};
enum _CHIP_TYPE {
NULL_CHIP_TYPE,
RTL8712_8188S_8191S_8192S,
RTL8188C_8192C,

7
include/osdep_ce_service.h
View file

@ -24,14 +24,7 @@
#include <ndis.h>
#include <ntddndis.h>
#ifdef CONFIG_SDIO_HCI
#include "SDCardDDK.h"
#endif
#ifdef CONFIG_USB_HCI
#include <usbdi.h>
#endif
typedef HANDLE _sema;
typedef LIST_ENTRY _list;

2
include/osdep_intf.h
View file

@ -51,7 +51,6 @@ The protection mechanism is through the pending queue.
_mutex ioctl_mutex;
#ifdef CONFIG_USB_HCI
// when in USB, IO is through interrupt in/out endpoints
struct usb_device *udev;
PURB piorw_urb;
@ -61,7 +60,6 @@ The protection mechanism is through the pending queue.
_timer io_timer;
u8 bio_irp_timeout;
u8 bio_timer_cancel;
#endif
};
#ifdef CONFIG_R871X_TEST

18
include/osdep_service.h
View file

@ -88,18 +88,12 @@
#include <linux/udp.h>
#endif
#ifdef CONFIG_USB_HCI
#include <linux/usb.h>
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21))
#include <linux/usb_ch9.h>
#else
#include <linux/usb/ch9.h>
#endif
#endif
#ifdef CONFIG_PCI_HCI
#include <linux/pci.h>
#endif
#ifdef CONFIG_TX_MCAST2UNI
extern int rtw_mc2u_disable;
@ -130,13 +124,11 @@ struct dvobj_priv;
extern void rtw_unregister_netdevs(struct dvobj_priv *dvobj);
extern int pm_netdev_open(struct net_device *pnetdev,u8 bnormal);
#ifdef CONFIG_USB_HCI
typedef struct urb * PURB;
typedef struct urb * PURB;
#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22))
#ifdef CONFIG_USB_SUSPEND
#define CONFIG_AUTOSUSPEND 1
#endif
#endif
#endif
typedef struct semaphore _sema;
@ -470,10 +462,8 @@ struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f flags,
int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line);
void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line);
#ifdef CONFIG_USB_HCI
void *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, const int line);
void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma, const enum mstat_f flags, const char *func, const int line);
#endif /* CONFIG_USB_HCI */
#ifdef CONFIG_USE_VMALLOC
#define rtw_vmalloc(sz) dbg_rtw_vmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
@ -507,12 +497,10 @@ void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dm
#define rtw_skb_clone_f(skb, mstat_f) dbg_rtw_skb_clone((skb), ((mstat_f)&0xff00)|MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
#define rtw_netif_rx(ndev, skb) dbg_rtw_netif_rx(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
#define rtw_skb_queue_purge(sk_buff_head) dbg_rtw_skb_queue_purge(sk_buff_head, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
#ifdef CONFIG_USB_HCI
#define rtw_usb_buffer_alloc(dev, size, dma) dbg_rtw_usb_buffer_alloc((dev), (size), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
#define rtw_usb_buffer_free(dev, size, addr, dma) dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
#define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f) dbg_rtw_usb_buffer_alloc((dev), (size), (dma), ((mstat_f)&0xff00)|MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
#define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f) dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), ((mstat_f)&0xff00)|MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
#endif /* CONFIG_USB_HCI */
#else /* DBG_MEM_ALLOC */
#define rtw_mstat_update(flag, status, sz) do {} while(0)
@ -531,10 +519,8 @@ struct sk_buff *_rtw_skb_clone(struct sk_buff *skb);
int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb);
void _rtw_skb_queue_purge(struct sk_buff_head *list);
#ifdef CONFIG_USB_HCI
void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma);
void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma);
#endif /* CONFIG_USB_HCI */
#ifdef CONFIG_USE_VMALLOC
#define rtw_vmalloc(sz) _rtw_vmalloc((sz))
@ -568,12 +554,10 @@ void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_a
#define rtw_skb_clone_f(skb, mstat_f) _rtw_skb_clone((skb))
#define rtw_netif_rx(ndev, skb) _rtw_netif_rx(ndev, skb)
#define rtw_skb_queue_purge(sk_buff_head) _rtw_skb_queue_purge(sk_buff_head)
#ifdef CONFIG_USB_HCI
#define rtw_usb_buffer_alloc(dev, size, dma) _rtw_usb_buffer_alloc((dev), (size), (dma))
#define rtw_usb_buffer_free(dev, size, addr, dma) _rtw_usb_buffer_free((dev), (size), (addr), (dma))
#define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f) _rtw_usb_buffer_alloc((dev), (size), (dma))
#define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f) _rtw_usb_buffer_free((dev), (size), (addr), (dma))
#endif /* CONFIG_USB_HCI */
#endif /* DBG_MEM_ALLOC */
extern void* rtw_malloc2d(int h, int w, int size);

180
include/rtl8188e_hal.h
View file

@ -46,105 +46,27 @@
#define Rtl8188E_FwWoWImgArrayLength ArrayLength_8188E_FW_WoWLAN
#endif //CONFIG_WOWLAN
#ifdef CONFIG_SDIO_HCI
//TODO: We should define 8188ES firmware related macro settings here!!
//TODO: The following need to check!!
#define RTL8188E_FW_UMC_IMG "rtl8188E\\rtl8188efw.bin"
#define RTL8188E_PHY_REG "rtl8188E\\PHY_REG_1T.txt"
#define RTL8188E_PHY_RADIO_A "rtl8188E\\radio_a_1T.txt"
#define RTL8188E_PHY_RADIO_B "rtl8188E\\radio_b_1T.txt"
#define RTL8188E_AGC_TAB "rtl8188E\\AGC_TAB_1T.txt"
#define RTL8188E_PHY_MACREG "rtl8188E\\MAC_REG.txt"
#define RTL8188E_PHY_REG_PG "rtl8188E\\PHY_REG_PG.txt"
#define RTL8188E_PHY_REG_MP "rtl8188E\\PHY_REG_MP.txt"
#define RTL8188E_FW_UMC_IMG "rtl8188E\\rtl8188efw.bin"
#define RTL8188E_PHY_REG "rtl8188E\\PHY_REG_1T.txt"
#define RTL8188E_PHY_RADIO_A "rtl8188E\\radio_a_1T.txt"
#define RTL8188E_PHY_RADIO_B "rtl8188E\\radio_b_1T.txt"
#define RTL8188E_AGC_TAB "rtl8188E\\AGC_TAB_1T.txt"
#define RTL8188E_PHY_MACREG "rtl8188E\\MAC_REG.txt"
#define RTL8188E_PHY_REG_PG "rtl8188E\\PHY_REG_PG.txt"
#define RTL8188E_PHY_REG_MP "rtl8188E\\PHY_REG_MP.txt"
//---------------------------------------------------------------------
// RTL8188E From header
// RTL8188E Power Configuration CMDs for USB/SDIO interfaces
//---------------------------------------------------------------------
#if 0
#define Rtl8188E_PHY_REG_Array_PG Rtl8188ESPHY_REG_Array_PG
#define Rtl8188E_PHY_REG_Array_PGLength Rtl8188ESPHY_REG_Array_PGLength
#endif
//---------------------------------------------------------------------
// RTL8188E Power Configuration CMDs for USB/SDIO interfaces
//---------------------------------------------------------------------
#define Rtl8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow
#define Rtl8188E_NIC_RF_OFF_FLOW rtl8188E_radio_off_flow
#define Rtl8188E_NIC_DISABLE_FLOW rtl8188E_card_disable_flow
#define Rtl8188E_NIC_ENABLE_FLOW rtl8188E_card_enable_flow
#define Rtl8188E_NIC_SUSPEND_FLOW rtl8188E_suspend_flow
#define Rtl8188E_NIC_RESUME_FLOW rtl8188E_resume_flow
#define Rtl8188E_NIC_PDN_FLOW rtl8188E_hwpdn_flow
#define Rtl8188E_NIC_LPS_ENTER_FLOW rtl8188E_enter_lps_flow
#define Rtl8188E_NIC_LPS_LEAVE_FLOW rtl8188E_leave_lps_flow
#elif defined(CONFIG_USB_HCI)
#define RTL8188E_FW_UMC_IMG "rtl8188E\\rtl8188efw.bin"
#define RTL8188E_PHY_REG "rtl8188E\\PHY_REG_1T.txt"
#define RTL8188E_PHY_RADIO_A "rtl8188E\\radio_a_1T.txt"
#define RTL8188E_PHY_RADIO_B "rtl8188E\\radio_b_1T.txt"
#define RTL8188E_AGC_TAB "rtl8188E\\AGC_TAB_1T.txt"
#define RTL8188E_PHY_MACREG "rtl8188E\\MAC_REG.txt"
#define RTL8188E_PHY_REG_PG "rtl8188E\\PHY_REG_PG.txt"
#define RTL8188E_PHY_REG_MP "rtl8188E\\PHY_REG_MP.txt"
#if 0
#define Rtl8188E_PHY_REG_Array_PG Rtl8188EUPHY_REG_Array_PG
#define Rtl8188E_PHY_REG_Array_PGLength Rtl8188EUPHY_REG_Array_PGLength
#endif
//---------------------------------------------------------------------
// RTL8188E Power Configuration CMDs for USB/SDIO interfaces
//---------------------------------------------------------------------
#define Rtl8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow
#define Rtl8188E_NIC_RF_OFF_FLOW rtl8188E_radio_off_flow
#define Rtl8188E_NIC_DISABLE_FLOW rtl8188E_card_disable_flow
#define Rtl8188E_NIC_ENABLE_FLOW rtl8188E_card_enable_flow
#define Rtl8188E_NIC_SUSPEND_FLOW rtl8188E_suspend_flow
#define Rtl8188E_NIC_RESUME_FLOW rtl8188E_resume_flow
#define Rtl8188E_NIC_PDN_FLOW rtl8188E_hwpdn_flow
#define Rtl8188E_NIC_LPS_ENTER_FLOW rtl8188E_enter_lps_flow
#define Rtl8188E_NIC_LPS_LEAVE_FLOW rtl8188E_leave_lps_flow
#elif defined(CONFIG_PCI_HCI)
#define RTL8188E_FW_UMC_IMG "rtl8188E\\rtl8188efw.bin"
#define RTL8188E_PHY_REG "rtl8188E\\PHY_REG_1T.txt"
#define RTL8188E_PHY_RADIO_A "rtl8188E\\radio_a_1T.txt"
#define RTL8188E_PHY_RADIO_B "rtl8188E\\radio_b_1T.txt"
#define RTL8188E_AGC_TAB "rtl8188E\\AGC_TAB_1T.txt"
#define RTL8188E_PHY_MACREG "rtl8188E\\MAC_REG.txt"
#define RTL8188E_PHY_REG_PG "rtl8188E\\PHY_REG_PG.txt"
#define RTL8188E_PHY_REG_MP "rtl8188E\\PHY_REG_MP.txt"
#define Rtl8188E_PHY_REG_Array_PG Rtl8188EEPHY_REG_Array_PG
#define Rtl8188E_PHY_REG_Array_PGLength Rtl8188EEPHY_REG_Array_PGLength
#ifndef CONFIG_PHY_SETTING_WITH_ODM
#if MP_DRIVER == 1
#define Rtl8188ES_PHY_REG_Array_MP Rtl8188ESPHY_REG_Array_MP
#endif
#endif
//---------------------------------------------------------------------
// RTL8188E Power Configuration CMDs for USB/SDIO/PCIE interfaces
//---------------------------------------------------------------------
#define Rtl8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow
#define Rtl8188E_NIC_RF_OFF_FLOW rtl8188E_radio_off_flow
#define Rtl8188E_NIC_DISABLE_FLOW rtl8188E_card_disable_flow
#define Rtl8188E_NIC_ENABLE_FLOW rtl8188E_card_enable_flow
#define Rtl8188E_NIC_SUSPEND_FLOW rtl8188E_suspend_flow
#define Rtl8188E_NIC_RESUME_FLOW rtl8188E_resume_flow
#define Rtl8188E_NIC_PDN_FLOW rtl8188E_hwpdn_flow
#define Rtl8188E_NIC_LPS_ENTER_FLOW rtl8188E_enter_lps_flow
#define Rtl8188E_NIC_LPS_LEAVE_FLOW rtl8188E_leave_lps_flow
#endif //CONFIG_***_HCI
#define Rtl8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow
#define Rtl8188E_NIC_RF_OFF_FLOW rtl8188E_radio_off_flow
#define Rtl8188E_NIC_DISABLE_FLOW rtl8188E_card_disable_flow
#define Rtl8188E_NIC_ENABLE_FLOW rtl8188E_card_enable_flow
#define Rtl8188E_NIC_SUSPEND_FLOW rtl8188E_suspend_flow
#define Rtl8188E_NIC_RESUME_FLOW rtl8188E_resume_flow
#define Rtl8188E_NIC_PDN_FLOW rtl8188E_hwpdn_flow
#define Rtl8188E_NIC_LPS_ENTER_FLOW rtl8188E_enter_lps_flow
#define Rtl8188E_NIC_LPS_LEAVE_FLOW rtl8188E_leave_lps_flow
#define DRVINFO_SZ 4 // unit is 8bytes
#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
@ -553,35 +475,6 @@ typedef struct hal_data_8188e
// Auto FSM to Turn On, include clock, isolation, power control for MAC only
u8 bMacPwrCtrlOn;
#ifdef CONFIG_SDIO_HCI
//
// For SDIO Interface HAL related
//
//
// SDIO ISR Related
//
// u32 IntrMask[1];
// u32 IntrMaskToSet[1];
// LOG_INTERRUPT InterruptLog;
u32 sdio_himr;
u32 sdio_hisr;
//
// SDIO Tx FIFO related.
//
// HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg
u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
_lock SdioTxFIFOFreePageLock;
//
// SDIO Rx FIFO related.
//
u8 SdioRxFIFOCnt;
u16 SdioRxFIFOSize;
#endif //CONFIG_SDIO_HCI
#ifdef CONFIG_USB_HCI
u32 UsbBulkOutSize;
// Interrupt relatd register information.
@ -602,34 +495,6 @@ typedef struct hal_data_8188e
u8 UsbRxAggPageCount; // 8192C DMA page count
u8 UsbRxAggPageTimeout;
#endif
#endif //CONFIG_USB_HCI
#ifdef CONFIG_PCI_HCI
//
// EEPROM setting.
//
u16 EEPROMDID;
u16 EEPROMSMID;
u16 EEPROMChannelPlan;
u8 EEPROMTSSI[2];
u8 EEPROMBoardType;
u32 TransmitConfig;
u32 IntrMask[2];
u32 IntrMaskToSet[2];
u8 bDefaultAntenna;
u8 bIQKInitialized;
u8 bInterruptMigration;
u8 bDisableTxInt;
u8 bGpioHwWpsPbc;
#endif //CONFIG_PCI_HCI
#ifdef CONFIG_TX_EARLY_MODE
u8 bEarlyModeEnable;
@ -645,15 +510,6 @@ typedef struct hal_data_8188e HAL_DATA_TYPE, *PHAL_DATA_TYPE;
#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
//#define IS_MULTI_FUNC_CHIP(_Adapter) (((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE)
//#define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) )
#ifdef CONFIG_PCI_HCI
void InterruptRecognized8188EE(struct adapter *Adapter, PRT_ISR_CONTENT pIsrContent);
void UpdateInterruptMask8188EE(struct adapter *Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
#endif //CONFIG_PCI_HCI
// rtl8188e_hal_init.c
#ifdef CONFIG_WOWLAN
s32 rtl8188e_FirmwareDownload(struct adapter *padapter, BOOLEAN bUsedWoWLANFw);

11
include/rtl8188e_led.h
View file

@ -28,18 +28,7 @@
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
#ifdef CONFIG_USB_HCI
void rtl8188eu_InitSwLeds(struct adapter *padapter);
void rtl8188eu_DeInitSwLeds(struct adapter *padapter);
#endif
#ifdef CONFIG_PCI_HCI
void rtl8188ee_gen_RefreshLedState(struct adapter *Adapter);
void rtl8188ee_InitSwLeds(struct adapter *padapter);
void rtl8188ee_DeInitSwLeds(struct adapter *padapter);
#endif
#ifdef CONFIG_SDIO_HCI
void rtl8188es_InitSwLeds(struct adapter *padapter);
void rtl8188es_DeInitSwLeds(struct adapter *padapter);
#endif
#endif

15
include/rtl8188e_recv.h
View file

@ -115,14 +115,6 @@ typedef struct rxreport_8188e
u32 rsvd2413:19;
} RXREPORT, *PRXREPORT;
#ifdef CONFIG_SDIO_HCI
s32 rtl8188es_init_recv_priv(struct adapter *padapter);
void rtl8188es_free_recv_priv(struct adapter *padapter);
void rtl8188es_recv_hdl(struct adapter *padapter, struct recv_buf *precvbuf);
#endif
#ifdef CONFIG_USB_HCI
#define INTERRUPT_MSG_FORMAT_LEN 60
void rtl8188eu_init_recvbuf(struct adapter *padapter, struct recv_buf *precvbuf);
s32 rtl8188eu_init_recv_priv(struct adapter *padapter);
@ -130,13 +122,6 @@ void rtl8188eu_free_recv_priv(struct adapter *padapter);
void rtl8188eu_recv_hdl(struct adapter *padapter, struct recv_buf *precvbuf);
void rtl8188eu_recv_tasklet(void *priv);
#endif
#ifdef CONFIG_PCI_HCI
s32 rtl8188ee_init_recv_priv(struct adapter *padapter);
void rtl8188ee_free_recv_priv(struct adapter *padapter);
#endif
void rtl8188e_query_rx_phy_status(union recv_frame *prframe, struct phy_stat *pphy_stat);
void rtl8188e_process_phy_info(struct adapter *padapter, void *prframe);
void update_recvframe_phyinfo_88e(union recv_frame *precvframe,struct phy_stat *pphy_status);

29
include/rtl8188e_xmit.h
View file

@ -255,22 +255,6 @@ struct txrpt_ccx_88e {
#define txrpt_ccx_qtime_88e(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
void rtl8188e_fill_fake_txdesc(struct adapter *padapter,u8*pDesc,u32 BufferLen,u8 IsPsPoll,u8 IsBTQosNull);
#ifdef CONFIG_SDIO_HCI
s32 rtl8188es_init_xmit_priv(struct adapter *padapter);
void rtl8188es_free_xmit_priv(struct adapter *padapter);
s32 rtl8188es_hal_xmit(struct adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8188es_mgnt_xmit(struct adapter *padapter, struct xmit_frame *pmgntframe);
s32 rtl8188es_hal_xmitframe_enqueue(struct adapter *padapter, struct xmit_frame *pxmitframe);
thread_return rtl8188es_xmit_thread(thread_context context);
s32 rtl8188es_xmit_buf_handler(struct adapter *padapter);
#define hal_xmit_handler rtl8188es_xmit_buf_handler
#ifdef CONFIG_SDIO_TX_TASKLET
void rtl8188es_xmit_tasklet(void *priv);
#endif
#endif
#ifdef CONFIG_USB_HCI
s32 rtl8188eu_init_xmit_priv(struct adapter *padapter);
void rtl8188eu_free_xmit_priv(struct adapter *padapter);
s32 rtl8188eu_hal_xmit(struct adapter *padapter, struct xmit_frame *pxmitframe);
@ -280,19 +264,6 @@ s32 rtl8188eu_xmit_buf_handler(struct adapter *padapter);
#define hal_xmit_handler rtl8188eu_xmit_buf_handler
void rtl8188eu_xmit_tasklet(void *priv);
s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
#endif
#ifdef CONFIG_PCI_HCI
s32 rtl8188ee_init_xmit_priv(struct adapter *padapter);
void rtl8188ee_free_xmit_priv(struct adapter *padapter);
struct xmit_buf *rtl8188ee_dequeue_xmitbuf(struct rtw_tx_ring *ring);
void rtl8188ee_xmitframe_resume(struct adapter *padapter);
s32 rtl8188ee_hal_xmit(struct adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8188ee_mgnt_xmit(struct adapter *padapter, struct xmit_frame *pmgntframe);
void rtl8188ee_xmit_tasklet(void *priv);
#endif
#ifdef CONFIG_TX_EARLY_MODE
void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmitbuf );

456
include/rtl8192c_hal.h
View file

@ -36,190 +36,89 @@
#include "../hal/OUTSRC/odm_precomp.h"
//2TODO: We should define 8192S firmware related macro settings here!!
#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
#define RTL819X_TOTAL_RF_PATH 2
#ifdef CONFIG_PCI_HCI
//TODO: The following need to check!!
#define RTL8192C_FW_TSMC_IMG "rtl8192CU\\rtl8192cfwT.bin"
#define RTL8192C_FW_UMC_IMG "rtl8192CU\\rtl8192cfwU.bin"
#define RTL8192C_FW_UMC_B_IMG "rtl8192CU\\rtl8192cfwU_B.bin"
#define RTL819X_DEFAULT_RF_TYPE RF_2T2R
//#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
#define RTL819X_TOTAL_RF_PATH 2
#define RTL8188C_PHY_REG "rtl8188CU\\PHY_REG.txt"
#define RTL8188C_PHY_RADIO_A "rtl8188CU\\radio_a.txt"
#define RTL8188C_PHY_RADIO_B "rtl8188CU\\radio_b.txt"
#define RTL8188C_PHY_RADIO_A_mCard "rtl8192CU\\radio_a_1T_mCard.txt"
#define RTL8188C_PHY_RADIO_B_mCard "rtl8192CU\\radio_b_1T_mCard.txt"
#define RTL8188C_PHY_RADIO_A_HP "rtl8192CU\\radio_a_1T_HP.txt"
#define RTL8188C_AGC_TAB "rtl8188CU\\AGC_TAB.txt"
#define RTL8188C_PHY_MACREG "rtl8188CU\\MACREG.txt"
//2TODO: The following need to check!!
#define RTL8192C_FW_TSMC_IMG "rtl8192CE\\rtl8192cfwT.bin"
#define RTL8192C_FW_UMC_IMG "rtl8192CE\\rtl8192cfwU.bin"
#define RTL8192C_FW_UMC_B_IMG "rtl8192CE\\rtl8192cfwU_B.bin"
#define RTL8192C_PHY_REG "rtl8192CU\\PHY_REG.txt"
#define RTL8192C_PHY_RADIO_A "rtl8192CU\\radio_a.txt"
#define RTL8192C_PHY_RADIO_B "rtl8192CU\\radio_b.txt"
#define RTL8192C_AGC_TAB "rtl8192CU\\AGC_TAB.txt"
#define RTL8192C_PHY_MACREG "rtl8192CU\\MACREG.txt"
#define RTL8188C_PHY_REG "rtl8192CE\\PHY_REG_1T.txt"
#define RTL8188C_PHY_RADIO_A "rtl8192CE\\radio_a_1T.txt"
#define RTL8188C_PHY_RADIO_B "rtl8192CE\\radio_b_1T.txt"
#define RTL8188C_AGC_TAB "rtl8192CE\\AGC_TAB_1T.txt"
#define RTL8188C_PHY_MACREG "rtl8192CE\\MACREG_1T.txt"
#define RTL8192C_PHY_REG "rtl8192CE\\PHY_REG_2T.txt"
#define RTL8192C_PHY_RADIO_A "rtl8192CE\\radio_a_2T.txt"
#define RTL8192C_PHY_RADIO_B "rtl8192CE\\radio_b_2T.txt"
#define RTL8192C_AGC_TAB "rtl8192CE\\AGC_TAB_2T.txt"
#define RTL8192C_PHY_MACREG "rtl8192CE\\MACREG_2T.txt"
#define RTL819X_PHY_MACPHY_REG "rtl8192CE\\MACPHY_reg.txt"
#define RTL819X_PHY_MACPHY_REG_PG "rtl8192CE\\MACPHY_reg_PG.txt"
#define RTL819X_PHY_MACREG "rtl8192CE\\MAC_REG.txt"
#define RTL819X_PHY_REG "rtl8192CE\\PHY_REG.txt"
#define RTL819X_PHY_REG_1T2R "rtl8192CE\\PHY_REG_1T2R.txt"
#define RTL819X_PHY_REG_to1T1R "rtl8192CE\\phy_to1T1R_a.txt"
#define RTL819X_PHY_REG_to1T2R "rtl8192CE\\phy_to1T2R.txt"
#define RTL819X_PHY_REG_to2T2R "rtl8192CE\\phy_to2T2R.txt"
#define RTL819X_PHY_REG_PG "rtl8192CE\\PHY_REG_PG.txt"
#define RTL819X_AGC_TAB "rtl8192CE\\AGC_TAB.txt"
#define RTL819X_PHY_RADIO_A "rtl8192CE\\radio_a.txt"
#define RTL819X_PHY_RADIO_A_1T "rtl8192CE\\radio_a_1t.txt"
#define RTL819X_PHY_RADIO_A_2T "rtl8192CE\\radio_a_2t.txt"
#define RTL819X_PHY_RADIO_B "rtl8192CE\\radio_b.txt"
#define RTL819X_PHY_RADIO_B_GM "rtl8192CE\\radio_b_gm.txt"
#define RTL819X_PHY_RADIO_C "rtl8192CE\\radio_c.txt"
#define RTL819X_PHY_RADIO_D "rtl8192CE\\radio_d.txt"
#define RTL819X_EEPROM_MAP "rtl8192CE\\8192ce.map"
#define RTL819X_EFUSE_MAP "rtl8192CE\\8192ce.map"
//---------------------------------------------------------------------
// RTL8723E From file
//---------------------------------------------------------------------
// The file name "_2T" is for 92CE, "_1T" is for 88CE. Modified by tynli. 2009.11.24.
#define Rtl819XFwTSMCImageArray Rtl8192CEFwTSMCImgArray
#define Rtl819XFwUMCACutImageArray Rtl8192CEFwUMCACutImgArray
#define Rtl819XFwUMCBCutImageArray Rtl8192CEFwUMCBCutImgArray
// #define Rtl8723FwUMCImageArray Rtl8192CEFwUMC8723ImgArray
#define Rtl819XMAC_Array Rtl8192CEMAC_2T_Array
#define Rtl819XAGCTAB_2TArray Rtl8192CEAGCTAB_2TArray
#define Rtl819XAGCTAB_1TArray Rtl8192CEAGCTAB_1TArray
#define Rtl819XPHY_REG_2TArray Rtl8192CEPHY_REG_2TArray
#define Rtl819XPHY_REG_1TArray Rtl8192CEPHY_REG_1TArray
#define Rtl819XRadioA_2TArray Rtl8192CERadioA_2TArray
#define Rtl819XRadioA_1TArray Rtl8192CERadioA_1TArray
#define Rtl819XRadioB_2TArray Rtl8192CERadioB_2TArray
#define Rtl819XRadioB_1TArray Rtl8192CERadioB_1TArray
#define Rtl819XPHY_REG_Array_PG Rtl8192CEPHY_REG_Array_PG
#define Rtl819XPHY_REG_Array_MP Rtl8192CEPHY_REG_Array_MP
#define PHY_REG_2TArrayLength Rtl8192CEPHY_REG_2TArrayLength
#define PHY_REG_1TArrayLength Rtl8192CEPHY_REG_1TArrayLength
#define PHY_ChangeTo_1T1RArrayLength Rtl8192CEPHY_ChangeTo_1T1RArrayLength
#define PHY_ChangeTo_1T2RArrayLength Rtl8192CEPHY_ChangeTo_1T2RArrayLength
#define PHY_ChangeTo_2T2RArrayLength Rtl8192CEPHY_ChangeTo_2T2RArrayLength
#define PHY_REG_Array_PGLength Rtl8192CEPHY_REG_Array_PGLength
//#define PHY_REG_Array_PG_mCardLength Rtl8192CEPHY_REG_Array_PG_mCardLength
#define PHY_REG_Array_MPLength Rtl8192CEPHY_REG_Array_MPLength
#define PHY_REG_Array_MPLength Rtl8192CEPHY_REG_Array_MPLength
//#define PHY_REG_1T_mCardArrayLength Rtl8192CEPHY_REG_1T_mCardArrayLength
//#define PHY_REG_2T_mCardArrayLength Rtl8192CEPHY_REG_2T_mCardArrayLength
//#define PHY_REG_Array_PG_HPLength Rtl8192CEPHY_REG_Array_PG_HPLength
#define RadioA_2TArrayLength Rtl8192CERadioA_2TArrayLength
#define RadioB_2TArrayLength Rtl8192CERadioB_2TArrayLength
#define RadioA_1TArrayLength Rtl8192CERadioA_1TArrayLength
#define RadioB_1TArrayLength Rtl8192CERadioB_1TArrayLength
//#define RadioA_1T_mCardArrayLength Rtl8192CERadioA_1T_mCardArrayLength
//#define RadioB_1T_mCardArrayLength Rtl8192CERadioB_1T_mCardArrayLength
//#define RadioA_1T_HPArrayLength Rtl8192CERadioA_1T_HPArrayLength
#define RadioB_GM_ArrayLength Rtl8192CERadioB_GM_ArrayLength
#define MAC_2T_ArrayLength Rtl8192CEMAC_2T_ArrayLength
#define MACPHY_Array_PGLength Rtl8192CEMACPHY_Array_PGLength
#define AGCTAB_2TArrayLength Rtl8192CEAGCTAB_2TArrayLength
#define AGCTAB_1TArrayLength Rtl8192CEAGCTAB_1TArrayLength
//#define AGCTAB_1T_HPArrayLength Rtl8192CEAGCTAB_1T_HPArrayLength
#elif defined(CONFIG_USB_HCI)
//2TODO: We should define 8192S firmware related macro settings here!!
#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
#define RTL819X_TOTAL_RF_PATH 2
//TODO: The following need to check!!
#define RTL8192C_FW_TSMC_IMG "rtl8192CU\\rtl8192cfwT.bin"
#define RTL8192C_FW_UMC_IMG "rtl8192CU\\rtl8192cfwU.bin"
#define RTL8192C_FW_UMC_B_IMG "rtl8192CU\\rtl8192cfwU_B.bin"
//#define RTL819X_FW_BOOT_IMG "rtl8192CU\\boot.img"
//#define RTL819X_FW_MAIN_IMG "rtl8192CU\\main.img"
//#define RTL819X_FW_DATA_IMG "rtl8192CU\\data.img"
#define RTL8188C_PHY_REG "rtl8188CU\\PHY_REG.txt"
#define RTL8188C_PHY_RADIO_A "rtl8188CU\\radio_a.txt"
#define RTL8188C_PHY_RADIO_B "rtl8188CU\\radio_b.txt"
#define RTL8188C_PHY_RADIO_A_mCard "rtl8192CU\\radio_a_1T_mCard.txt"
#define RTL8188C_PHY_RADIO_B_mCard "rtl8192CU\\radio_b_1T_mCard.txt"
#define RTL8188C_PHY_RADIO_A_HP "rtl8192CU\\radio_a_1T_HP.txt"
#define RTL8188C_AGC_TAB "rtl8188CU\\AGC_TAB.txt"
#define RTL8188C_PHY_MACREG "rtl8188CU\\MACREG.txt"
#define RTL8192C_PHY_REG "rtl8192CU\\PHY_REG.txt"
#define RTL8192C_PHY_RADIO_A "rtl8192CU\\radio_a.txt"
#define RTL8192C_PHY_RADIO_B "rtl8192CU\\radio_b.txt"
#define RTL8192C_AGC_TAB "rtl8192CU\\AGC_TAB.txt"
#define RTL8192C_PHY_MACREG "rtl8192CU\\MACREG.txt"
#define RTL819X_PHY_REG_PG "rtl8192CU\\PHY_REG_PG.txt"
#define RTL819X_PHY_REG_PG "rtl8192CU\\PHY_REG_PG.txt"
//---------------------------------------------------------------------
// RTL8723U From file
//---------------------------------------------------------------------
// The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24.
#define Rtl819XFwImageArray Rtl8192CUFwTSMCImgArray
#define Rtl819XFwTSMCImageArray Rtl8192CUFwTSMCImgArray
#define Rtl819XFwUMCACutImageArray Rtl8192CUFwUMCACutImgArray
#define Rtl819XFwUMCBCutImageArray Rtl8192CUFwUMCBCutImgArray
// The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24.
#define Rtl819XFwImageArray Rtl8192CUFwTSMCImgArray
#define Rtl819XFwTSMCImageArray Rtl8192CUFwTSMCImgArray
#define Rtl819XFwUMCACutImageArray Rtl8192CUFwUMCACutImgArray
#define Rtl819XFwUMCBCutImageArray Rtl8192CUFwUMCBCutImgArray
#define Rtl819XMAC_Array Rtl8192CUMAC_2T_Array
#define Rtl819XAGCTAB_2TArray Rtl8192CUAGCTAB_2TArray
#define Rtl819XAGCTAB_1TArray Rtl8192CUAGCTAB_1TArray
#define Rtl819XAGCTAB_1T_HPArray Rtl8192CUAGCTAB_1T_HPArray
#define Rtl819XPHY_REG_2TArray Rtl8192CUPHY_REG_2TArray
#define Rtl819XPHY_REG_1TArray Rtl8192CUPHY_REG_1TArray
#define Rtl819XPHY_REG_1T_mCardArray Rtl8192CUPHY_REG_1T_mCardArray
#define Rtl819XPHY_REG_2T_mCardArray Rtl8192CUPHY_REG_2T_mCardArray
#define Rtl819XPHY_REG_1T_HPArray Rtl8192CUPHY_REG_1T_HPArray
#define Rtl819XRadioA_2TArray Rtl8192CURadioA_2TArray
#define Rtl819XRadioA_1TArray Rtl8192CURadioA_1TArray
#define Rtl819XRadioA_1T_mCardArray Rtl8192CURadioA_1T_mCardArray
#define Rtl819XRadioB_2TArray Rtl8192CURadioB_2TArray
#define Rtl819XRadioB_1TArray Rtl8192CURadioB_1TArray
#define Rtl819XRadioB_1T_mCardArray Rtl8192CURadioB_1T_mCardArray
#define Rtl819XRadioA_1T_HPArray Rtl8192CURadioA_1T_HPArray
#define Rtl819XPHY_REG_Array_PG Rtl8192CUPHY_REG_Array_PG
#define Rtl819XPHY_REG_Array_PG_mCard Rtl8192CUPHY_REG_Array_PG_mCard
#define Rtl819XPHY_REG_Array_PG_HP Rtl8192CUPHY_REG_Array_PG_HP
#define Rtl819XPHY_REG_Array_MP Rtl8192CUPHY_REG_Array_MP
#define Rtl819XMAC_Array Rtl8192CUMAC_2T_Array
#define Rtl819XAGCTAB_2TArray Rtl8192CUAGCTAB_2TArray
#define Rtl819XAGCTAB_1TArray Rtl8192CUAGCTAB_1TArray
#define Rtl819XAGCTAB_1T_HPArray Rtl8192CUAGCTAB_1T_HPArray
#define Rtl819XPHY_REG_2TArray Rtl8192CUPHY_REG_2TArray
#define Rtl819XPHY_REG_1TArray Rtl8192CUPHY_REG_1TArray
#define Rtl819XPHY_REG_1T_mCardArray Rtl8192CUPHY_REG_1T_mCardArray
#define Rtl819XPHY_REG_2T_mCardArray Rtl8192CUPHY_REG_2T_mCardArray
#define Rtl819XPHY_REG_1T_HPArray Rtl8192CUPHY_REG_1T_HPArray
#define Rtl819XRadioA_2TArray Rtl8192CURadioA_2TArray
#define Rtl819XRadioA_1TArray Rtl8192CURadioA_1TArray
#define Rtl819XRadioA_1T_mCardArray Rtl8192CURadioA_1T_mCardArray
#define Rtl819XRadioB_2TArray Rtl8192CURadioB_2TArray
#define Rtl819XRadioB_1TArray Rtl8192CURadioB_1TArray
#define Rtl819XRadioB_1T_mCardArray Rtl8192CURadioB_1T_mCardArray
#define Rtl819XRadioA_1T_HPArray Rtl8192CURadioA_1T_HPArray
#define Rtl819XPHY_REG_Array_PG Rtl8192CUPHY_REG_Array_PG
#define Rtl819XPHY_REG_Array_PG_mCard Rtl8192CUPHY_REG_Array_PG_mCard
#define Rtl819XPHY_REG_Array_PG_HP Rtl8192CUPHY_REG_Array_PG_HP
#define Rtl819XPHY_REG_Array_MP Rtl8192CUPHY_REG_Array_MP
#define PHY_REG_2TArrayLength Rtl8192CUPHY_REG_2TArrayLength
#define PHY_REG_1TArrayLength Rtl8192CUPHY_REG_1TArrayLength
#define PHY_ChangeTo_1T1RArrayLength Rtl8192CUPHY_ChangeTo_1T1RArrayLength
#define PHY_ChangeTo_1T2RArrayLength Rtl8192CUPHY_ChangeTo_1T2RArrayLength
#define PHY_ChangeTo_2T2RArrayLength Rtl8192CUPHY_ChangeTo_2T2RArrayLength
#define PHY_REG_Array_PGLength Rtl8192CUPHY_REG_Array_PGLength
#define PHY_REG_Array_PG_mCardLength Rtl8192CUPHY_REG_Array_PG_mCardLength
#define PHY_REG_Array_MPLength Rtl8192CUPHY_REG_Array_MPLength
#define PHY_REG_Array_MPLength Rtl8192CUPHY_REG_Array_MPLength
#define PHY_REG_1T_mCardArrayLength Rtl8192CUPHY_REG_1T_mCardArrayLength
#define PHY_REG_2T_mCardArrayLength Rtl8192CUPHY_REG_2T_mCardArrayLength
#define PHY_REG_Array_PG_HPLength Rtl8192CUPHY_REG_Array_PG_HPLength
#define RadioA_2TArrayLength Rtl8192CURadioA_2TArrayLength
#define RadioB_2TArrayLength Rtl8192CURadioB_2TArrayLength
#define RadioA_1TArrayLength Rtl8192CURadioA_1TArrayLength
#define RadioB_1TArrayLength Rtl8192CURadioB_1TArrayLength
#define RadioA_1T_mCardArrayLength Rtl8192CURadioA_1T_mCardArrayLength
#define RadioB_1T_mCardArrayLength Rtl8192CURadioB_1T_mCardArrayLength
#define RadioA_1T_HPArrayLength Rtl8192CURadioA_1T_HPArrayLength
#define RadioB_GM_ArrayLength Rtl8192CURadioB_GM_ArrayLength
#define MAC_2T_ArrayLength Rtl8192CUMAC_2T_ArrayLength
#define MACPHY_Array_PGLength Rtl8192CUMACPHY_Array_PGLength
#define AGCTAB_2TArrayLength Rtl8192CUAGCTAB_2TArrayLength
#define AGCTAB_1TArrayLength Rtl8192CUAGCTAB_1TArrayLength
#define AGCTAB_1T_HPArrayLength Rtl8192CUAGCTAB_1T_HPArrayLength
#define PHY_REG_1T_HPArrayLength Rtl8192CUPHY_REG_1T_HPArrayLength
#endif
#define PHY_REG_2TArrayLength Rtl8192CUPHY_REG_2TArrayLength
#define PHY_REG_1TArrayLength Rtl8192CUPHY_REG_1TArrayLength
#define PHY_ChangeTo_1T1RArrayLength Rtl8192CUPHY_ChangeTo_1T1RArrayLength
#define PHY_ChangeTo_1T2RArrayLength Rtl8192CUPHY_ChangeTo_1T2RArrayLength
#define PHY_ChangeTo_2T2RArrayLength Rtl8192CUPHY_ChangeTo_2T2RArrayLength
#define PHY_REG_Array_PGLength Rtl8192CUPHY_REG_Array_PGLength
#define PHY_REG_Array_PG_mCardLength Rtl8192CUPHY_REG_Array_PG_mCardLength
#define PHY_REG_Array_MPLength Rtl8192CUPHY_REG_Array_MPLength
#define PHY_REG_Array_MPLength Rtl8192CUPHY_REG_Array_MPLength
#define PHY_REG_1T_mCardArrayLength Rtl8192CUPHY_REG_1T_mCardArrayLength
#define PHY_REG_2T_mCardArrayLength Rtl8192CUPHY_REG_2T_mCardArrayLength
#define PHY_REG_Array_PG_HPLength Rtl8192CUPHY_REG_Array_PG_HPLength
#define RadioA_2TArrayLength Rtl8192CURadioA_2TArrayLength
#define RadioB_2TArrayLength Rtl8192CURadioB_2TArrayLength
#define RadioA_1TArrayLength Rtl8192CURadioA_1TArrayLength
#define RadioB_1TArrayLength Rtl8192CURadioB_1TArrayLength
#define RadioA_1T_mCardArrayLength Rtl8192CURadioA_1T_mCardArrayLength
#define RadioB_1T_mCardArrayLength Rtl8192CURadioB_1T_mCardArrayLength
#define RadioA_1T_HPArrayLength Rtl8192CURadioA_1T_HPArrayLength
#define RadioB_GM_ArrayLength Rtl8192CURadioB_GM_ArrayLength
#define MAC_2T_ArrayLength Rtl8192CUMAC_2T_ArrayLength
#define MACPHY_Array_PGLength Rtl8192CUMACPHY_Array_PGLength
#define AGCTAB_2TArrayLength Rtl8192CUAGCTAB_2TArrayLength
#define AGCTAB_1TArrayLength Rtl8192CUAGCTAB_1TArrayLength
#define AGCTAB_1T_HPArrayLength Rtl8192CUAGCTAB_1T_HPArrayLength
#define PHY_REG_1T_HPArrayLength Rtl8192CUPHY_REG_1T_HPArrayLength
#define DRVINFO_SZ 4 // unit is 8bytes
#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
@ -443,197 +342,6 @@ enum c2h_id_8192c {
MAX_C2HEVENT
};
#ifdef CONFIG_PCI_HCI
struct hal_data_8192ce
{
HAL_VERSION VersionID;
RT_MULTI_FUNC MultiFunc; // For multi-function consideration.
RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control.
RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO
u16 CustomerID;
u16 FirmwareVersion;
u16 FirmwareVersionRev;
u16 FirmwareSubVersion;
u32 IntrMask[2];
u32 IntrMaskToSet[2];
u32 DisabledFunctions;
//current WIFI_PHY values
u32 ReceiveConfig;
u32 TransmitConfig;
WIRELESS_MODE CurrentWirelessMode;
HT_CHANNEL_WIDTH CurrentChannelBW;
u8 CurrentChannel;
u8 nCur40MhzPrimeSC;// Control channel sub-carrier
u16 BasicRateSet;
//rf_ctrl
_lock rf_lock;
u8 rf_chip;
u8 rf_type;
u8 NumTotalRFPath;
INTERFACE_SELECT_8192CPCIe InterfaceSel;
//
// EEPROM setting.
//
u16 EEPROMVID;
u16 EEPROMDID;
u16 EEPROMSVID;
u16 EEPROMSMID;
u16 EEPROMChannelPlan;
u16 EEPROMVersion;
u8 EEPROMChnlAreaTxPwrCCK[2][3];
u8 EEPROMChnlAreaTxPwrHT40_1S[2][3];
u8 EEPROMChnlAreaTxPwrHT40_2SDiff[2][3];
u8 EEPROMPwrLimitHT20[3];
u8 EEPROMPwrLimitHT40[3];
u8 bTXPowerDataReadFromEEPORM;
u8 EEPROMThermalMeter;
u8 EEPROMTSSI[2];
u8 EEPROMCustomerID;
u8 EEPROMBoardType;
u8 EEPROMRegulatory;
u8 bDefaultAntenna;
u8 bIQKInitialized;
u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
// For power group
u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff
BOOLEAN EepromOrEfuse;
u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes)
u8 EfuseUsedPercentage;
EFUSE_HAL EfuseHal;
#ifdef CONFIG_BT_COEXIST
struct btcoexist_priv bt_coexist;
#endif
// Read/write are allow for following hardware information variables
u8 framesync;
u32 framesyncC34;
u8 framesyncMonitor;
u8 DefaultInitialGain[4];
u8 pwrGroupCnt;
u32 MCSTxPowerLevelOriginalOffset[7][16];
u32 CCKTxPowerLevelOriginalOffset;
u32 AntennaTxPath; // Antenna path Tx
u32 AntennaRxPath; // Antenna path Rx
u8 BluetoothCoexist;
u8 ExternalPA;
//u32 LedControlNum;
//u32 LedControlMode;
u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
//u32 TxPowerTrackControl;
u8 b1x1RecvCombine; // for 1T1R receive combining
u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo.
//vivi, for tx power tracking, 20080407
//u16 TSSI_13dBm;
//u32 Pwr_Track;
// The current Tx Power Level
u8 CurrentCckTxPwrIdx;
u8 CurrentOfdm24GTxPwrIdx;
BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
u32 RfRegChnlVal[2];
//RDG enable
BOOLEAN bRDGEnable;
//for host message to fw
u8 LastHMEBoxNum;
u8 fw_ractrl;
u8 RegTxPause;
// Beacon function related global variable.
u32 RegBcnCtrlVal;
u8 RegFwHwTxQCtrl;
u8 RegReg542;
u8 CurAntenna;
//### ODM-DUPLICATE CODE ###
u8 AntDivCfg;
/*
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
//SW Antenna Switch
s32 RSSI_sum_A;
s32 RSSI_sum_B;
s32 RSSI_cnt_A;
s32 RSSI_cnt_B;
BOOLEAN RSSI_test;
#endif
#ifdef CONFIG_HW_ANTENNA_DIVERSITY
//Hybrid Antenna Diversity
u32 CCK_Ant1_Cnt;
u32 CCK_Ant2_Cnt;
u32 OFDM_Ant1_Cnt;
u32 OFDM_Ant2_Cnt;
#endif
*/
//### ODM-DUPLICATE CODE ###
struct dm_priv dmpriv;
DM_ODM_T odmpriv;
//_lock odm_stainfo_lock;
u8 bDumpRxPkt;//for debug
#ifdef DBG_CONFIG_ERROR_DETECT
struct sreset_priv srestpriv;
#endif
u8 bInterruptMigration;
u8 bDisableTxInt;
u8 bGpioHwWpsPbc;
u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
u16 EfuseUsedBytes;
#ifdef CONFIG_P2P
struct P2P_PS_Offload_t p2p_ps_offload;
#endif //CONFIG_P2P
};
typedef struct hal_data_8192ce HAL_DATA_TYPE, *PHAL_DATA_TYPE;
//
// Function disabled.
//
#define DF_TX_BIT BIT0
#define DF_RX_BIT BIT1
#define DF_IO_BIT BIT2
#define DF_IO_D3_BIT BIT3
#define RT_DF_TYPE u32
#define RT_DISABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions |= ((RT_DF_TYPE)(__FuncBits)))
#define RT_ENABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions &= (~((RT_DF_TYPE)(__FuncBits))))
#define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) )
#define IS_MULTI_FUNC_CHIP(_Adapter) (((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE)
void InterruptRecognized8192CE(struct adapter *Adapter, PRT_ISR_CONTENT pIsrContent);
VOID UpdateInterruptMask8192CE(struct adapter *Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
#endif
#ifdef CONFIG_USB_HCI
struct hal_data_8192cu
{
HAL_VERSION VersionID;
@ -752,25 +460,6 @@ struct hal_data_8192cu
/*****ODM duplicate data********/
u8 AntDivCfg;
/*
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
//SW Antenna Switch
s32 RSSI_sum_A;
s32 RSSI_sum_B;
s32 RSSI_cnt_A;
s32 RSSI_cnt_B;
BOOLEAN RSSI_test;
#endif
#ifdef CONFIG_HW_ANTENNA_DIVERSITY
//Hybrid Antenna Diversity
u32 CCK_Ant1_Cnt;
u32 CCK_Ant2_Cnt;
u32 OFDM_Ant1_Cnt;
u32 OFDM_Ant2_Cnt;
#endif
*/
u8 bDumpRxPkt;//for debug
u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
@ -824,7 +513,6 @@ struct hal_data_8192cu
};
typedef struct hal_data_8192cu HAL_DATA_TYPE, *PHAL_DATA_TYPE;
#endif
#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData))
#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type)

7
include/rtl8192c_led.h
View file

@ -28,14 +28,7 @@
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
#ifdef CONFIG_USB_HCI
void rtl8192cu_InitSwLeds(struct adapter *padapter);
void rtl8192cu_DeInitSwLeds(struct adapter *padapter);
#endif
#ifdef CONFIG_PCI_HCI
void rtl8192ce_gen_RefreshLedState(struct adapter *Adapter);
void rtl8192ce_InitSwLeds(struct adapter *padapter);
void rtl8192ce_DeInitSwLeds(struct adapter *padapter);
#endif
#endif

41
include/rtl8192c_recv.h
View file

@ -31,17 +31,11 @@
#define NR_RECVBUFF (4)
#else
#if defined(CONFIG_GSPI_HCI)
#define NR_RECVBUFF (32)
#elif defined(CONFIG_SDIO_HCI)
#define NR_RECVBUFF (8)
#else
#ifdef CONFIG_SINGLE_RECV_BUF
#define NR_RECVBUFF (1)
#else
#define NR_RECVBUFF (4)
#endif //CONFIG_SINGLE_RECV_BUF
#endif
#define NR_PREALLOC_RECV_SKB (8)
#endif
@ -51,15 +45,7 @@
#define RECV_BLK_CNT 16
#define RECV_BLK_TH RECV_BLK_CNT
#if defined(CONFIG_USB_HCI)
#ifdef PLATFORM_OS_CE
#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k
#else
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
//#define MAX_RECVBUF_SZ (32768) // 32k
//#define MAX_RECVBUF_SZ (16384) //16K
//#define MAX_RECVBUF_SZ (10240) //10K
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) // 8K
#else
@ -69,25 +55,6 @@
#else
#define MAX_RECVBUF_SZ (4000) // about 4K
#endif
#endif
#elif defined(CONFIG_PCI_HCI)
//#ifndef CONFIG_MINIMAL_MEMORY_USAGE
// #define MAX_RECVBUF_SZ (9100)
//#else
#define MAX_RECVBUF_SZ (4000) // about 4K
//#endif
#define RX_MPDU_QUEUE 0
#define RX_CMD_QUEUE 1
#define RX_MAX_QUEUE 2
#elif defined(CONFIG_SDIO_HCI)
#define MAX_RECVBUF_SZ (10240)
#endif
#define RECV_BULK_IN_ADDR 0x80
#define RECV_INT_IN_ADDR 0x81
@ -118,8 +85,6 @@ struct phy_stat
// Rx smooth factor
#define Rx_Smooth_Factor (20)
#ifdef CONFIG_USB_HCI
typedef struct _INTERRUPT_MSG_FORMAT_EX{
unsigned int C2H_MSG0;
unsigned int C2H_MSG1;
@ -133,12 +98,6 @@ typedef struct _INTERRUPT_MSG_FORMAT_EX{
void rtl8192cu_init_recvbuf(struct adapter *padapter, struct recv_buf *precvbuf);
int rtl8192cu_init_recv_priv(struct adapter * padapter);
void rtl8192cu_free_recv_priv(struct adapter * padapter);
#endif
#ifdef CONFIG_PCI_HCI
int rtl8192ce_init_recv_priv(struct adapter * padapter);
void rtl8192ce_free_recv_priv(struct adapter * padapter);
#endif
void rtl8192c_translate_rx_signal_stuff(union recv_frame *precvframe, struct phy_stat *pphy_status);
void rtl8192c_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *pdesc);

78
include/rtl8192c_spec.h
View file

@ -689,59 +689,6 @@ Default: 00b.
#define RTL_EEPROM_ID 0x8129
#ifdef CONFIG_PCI_HCI
#define RT_IBSS_INT_MASKS (IMR_BcnInt | IMR_TBDOK | IMR_TBDER)
#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
#define RT_BSS_INT_MASKS (RT_IBSS_INT_MASKS)
//
// Interface type.
//
typedef enum _INTERFACE_SELECT_8192CPCIe{
INTF_SEL0_SOLO_MINICARD = 0, // WiFi solo-mCard
INTF_SEL1_BT_COMBO_MINICARD = 1, // WiFi+BT combo-mCard
INTF_SEL2_PCIe = 2, // PCIe Card
} INTERFACE_SELECT_8192CPCIe, *PINTERFACE_SELECT_8192CPCIe;
#define RTL8190_EEPROM_ID 0x8129 // 0-1
#define EEPROM_HPON 0x02 // LDO settings.2-5
#define EEPROM_CLK 0x06 // Clock settings.6-7
#define EEPROM_TESTR 0x08 // SE Test mode.8
#define EEPROM_VID 0x0A // SE Vendor ID.A-B
#define EEPROM_DID 0x0C // SE Device ID. C-D
#define EEPROM_SVID 0x0E // SE Vendor ID.E-F
#define EEPROM_SMID 0x10 // SE PCI Subsystem ID. 10-11
#define EEPROM_MAC_ADDR 0x16 // SEMAC Address. 12-17
//----------------------------------------------------------------
// Ziv - Let PCIe and USB use the same define. Modify address mapping later.
#define EEPROM_CCK_TX_PWR_INX 0x5A
#define EEPROM_HT40_1S_TX_PWR_INX 0x60
#define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66
#define EEPROM_HT20_TX_PWR_INX_DIFF 0x69
#define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C
#define EEPROM_HT40_MAX_PWR_OFFSET 0x6F
#define EEPROM_HT20_MAX_PWR_OFFSET 0x72
#define EEPROM_CHANNEL_PLAN 0x75
#define EEPROM_TSSI_A 0x76
#define EEPROM_TSSI_B 0x77
#define EEPROM_THERMAL_METER 0x78
#define EEPROM_RF_OPT1 0x79
#define EEPROM_RF_OPT2 0x7A
#define EEPROM_RF_OPT3 0x7B
#define EEPROM_RF_OPT4 0x7C
#define EEPROM_VERSION 0x7E
#define EEPROM_CUSTOMER_ID 0x7F
#define EEPROM_NORMAL_BoardType EEPROM_RF_OPT1 //[7:5]
#endif
#ifdef CONFIG_USB_HCI
//should be renamed and moved to another file
typedef enum _BOARD_TYPE_8192CUSB{
BOARD_USB_DONGLE = 0, // USB dongle
@ -892,31 +839,6 @@ typedef enum _BOARD_TYPE_8192CUSB{
#define EEPROM_USB_DEVICE_PWR BIT(2)
#define EEPROM_EP_NUMBER (BIT(3)|BIT(4))
#if 0
#define EEPROM_CHANNEL_PLAN_FCC 0x0
#define EEPROM_CHANNEL_PLAN_IC 0x1
#define EEPROM_CHANNEL_PLAN_ETSI 0x2
#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
#define EEPROM_CHANNEL_PLAN_MKK 0x5
#define EEPROM_CHANNEL_PLAN_MKK1 0x6
#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
#define EEPROM_CHANNEL_PLAN_TELEC 0x8
#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
#define EEPROM_CID_DEFAULT 0x0
#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25.
#endif
#endif
/*===================================================================
=====================================================================
Here the register defines are for 92C. When the define is as same with 92C,

23
include/rtl8192c_xmit.h
View file

@ -118,8 +118,6 @@ void handle_txrpt_ccx_8192c(struct adapter *adapter, void *buf);
#define handle_txrpt_ccx_8192c(adapter, buf) do {} while(0)
#endif
#ifdef CONFIG_USB_HCI
#ifdef CONFIG_USB_TX_AGGREGATION
#define MAX_TX_AGG_PACKET_NUMBER 0xFF
#endif
@ -141,24 +139,3 @@ s32 rtl8192cu_hostap_mgnt_xmit_entry(struct adapter *padapter, _pkt *pkt);
#endif
#endif
#ifdef CONFIG_PCI_HCI
s32 rtl8192ce_init_xmit_priv(struct adapter * padapter);
void rtl8192ce_free_xmit_priv(struct adapter * padapter);
s32 rtl8192ce_enqueue_xmitbuf(struct rtw_tx_ring *ring, struct xmit_buf *pxmitbuf);
struct xmit_buf *rtl8192ce_dequeue_xmitbuf(struct rtw_tx_ring *ring);
void rtl8192ce_xmitframe_resume(struct adapter *padapter);
s32 rtl8192ce_mgnt_xmit(struct adapter *padapter, struct xmit_frame *pmgntframe);
s32 rtl8192ce_hal_xmit(struct adapter *padapter, struct xmit_frame *pxmitframe);
#ifdef CONFIG_HOSTAPD_MLME
s32 rtl8192ce_hostap_mgnt_xmit_entry(struct adapter *padapter, _pkt *pkt);
#endif
#endif
#endif

266
include/rtl8192d_hal.h
View file

@ -32,157 +32,69 @@
#include "../hal/OUTSRC/odm_precomp.h"
#ifdef CONFIG_PCI_HCI
#include <pci_ops.h>
#define RTL819X_DEFAULT_RF_TYPE RF_2T2R
//---------------------------------------------------------------------
// RTL8192DE From file
//---------------------------------------------------------------------
#define RTL8192D_FW_IMG "rtl8192DE\\rtl8192dfw.bin"
#define RTL8192D_PHY_REG "rtl8192DE\\PHY_REG.txt"
#define RTL8192D_PHY_REG_PG "rtl8192DE\\PHY_REG_PG.txt"
#define RTL8192D_PHY_REG_MP "rtl8192DE\\PHY_REG_MP.txt"
#define RTL8192D_AGC_TAB "rtl8192DE\\AGC_TAB.txt"
#define RTL8192D_AGC_TAB_2G "rtl8192DE\\AGC_TAB_2G.txt"
#define RTL8192D_AGC_TAB_5G "rtl8192DE\\AGC_TAB_5G.txt"
#define RTL8192D_PHY_RADIO_A "rtl8192DE\\radio_a.txt"
#define RTL8192D_PHY_RADIO_B "rtl8192DE\\radio_b.txt"
#define RTL8192D_PHY_RADIO_A_intPA "rtl8192DE\\radio_a_intPA.txt"
#define RTL8192D_PHY_RADIO_B_intPA "rtl8192DE\\radio_b_intPA.txt"
#define RTL8192D_PHY_MACREG "rtl8192DE\\MAC_REG.txt"
//---------------------------------------------------------------------
// RTL8192DE From header
//---------------------------------------------------------------------
// Fw Array
#define Rtl8192D_FwImageArray Rtl8192DEFwImgArray
// MAC/BB/PHY Array
#define Rtl8192D_MAC_Array Rtl8192DEMAC_2T_Array
#define Rtl8192D_AGCTAB_Array Rtl8192DEAGCTAB_Array
#define Rtl8192D_AGCTAB_5GArray Rtl8192DEAGCTAB_5GArray
#define Rtl8192D_AGCTAB_2GArray Rtl8192DEAGCTAB_2GArray
#define Rtl8192D_AGCTAB_2TArray Rtl8192DEAGCTAB_2TArray
#define Rtl8192D_AGCTAB_1TArray Rtl8192DEAGCTAB_1TArray
#define Rtl8192D_PHY_REG_2TArray Rtl8192DEPHY_REG_2TArray
#define Rtl8192D_PHY_REG_1TArray Rtl8192DEPHY_REG_1TArray
#define Rtl8192D_PHY_REG_Array_PG Rtl8192DEPHY_REG_Array_PG
#define Rtl8192D_PHY_REG_Array_MP Rtl8192DEPHY_REG_Array_MP
#define Rtl8192D_RadioA_2TArray Rtl8192DERadioA_2TArray
#define Rtl8192D_RadioA_1TArray Rtl8192DERadioA_1TArray
#define Rtl8192D_RadioB_2TArray Rtl8192DERadioB_2TArray
#define Rtl8192D_RadioB_1TArray Rtl8192DERadioB_1TArray
#define Rtl8192D_RadioA_2T_intPAArray Rtl8192DERadioA_2T_intPAArray
#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DERadioB_2T_intPAArray
// Array length
#define Rtl8192D_FwImageArrayLength Rtl8192DEImgArrayLength
#define Rtl8192D_MAC_ArrayLength Rtl8192DEMAC_2T_ArrayLength
#define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DEAGCTAB_5GArrayLength
#define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DEAGCTAB_2GArrayLength
#define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DEAGCTAB_2TArrayLength
#define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DEAGCTAB_1TArrayLength
#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DEAGCTAB_ArrayLength
#define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DEPHY_REG_2TArrayLength
#define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DEPHY_REG_1TArrayLength
#define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DEPHY_REG_Array_PGLength
#define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DEPHY_REG_Array_MPLength
#define Rtl8192D_RadioA_2TArrayLength Rtl8192DERadioA_2TArrayLength
#define Rtl8192D_RadioB_2TArrayLength Rtl8192DERadioB_2TArrayLength
#define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DERadioA_2T_intPAArrayLength
#define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DERadioB_2T_intPAArrayLength
#elif defined(CONFIG_USB_HCI)
#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
//---------------------------------------------------------------------
// RTL8192DU From file
//---------------------------------------------------------------------
#define RTL8192D_FW_IMG "rtl8192DU\\rtl8192dfw.bin"
#define RTL8192D_FW_IMG "rtl8192DU\\rtl8192dfw.bin"
#define RTL8192D_PHY_REG "rtl8192DU\\PHY_REG.txt"
#define RTL8192D_PHY_REG_PG "rtl8192DU\\PHY_REG_PG.txt"
#define RTL8192D_PHY_REG_MP "rtl8192DU\\PHY_REG_MP.txt"
#define RTL8192D_PHY_REG "rtl8192DU\\PHY_REG.txt"
#define RTL8192D_PHY_REG_PG "rtl8192DU\\PHY_REG_PG.txt"
#define RTL8192D_PHY_REG_MP "rtl8192DU\\PHY_REG_MP.txt"
#define RTL8192D_AGC_TAB "rtl8192DU\\AGC_TAB.txt"
#define RTL8192D_AGC_TAB_2G "rtl8192DU\\AGC_TAB_2G.txt"
#define RTL8192D_AGC_TAB_5G "rtl8192DU\\AGC_TAB_5G.txt"
#define RTL8192D_PHY_RADIO_A "rtl8192DU\\radio_a.txt"
#define RTL8192D_PHY_RADIO_B "rtl8192DU\\radio_b.txt"
#define RTL8192D_PHY_RADIO_A_intPA "rtl8192DU\\radio_a_intPA.txt"
#define RTL8192D_PHY_RADIO_B_intPA "rtl8192DU\\radio_b_intPA.txt"
#define RTL8192D_PHY_MACREG "rtl8192DU\\MAC_REG.txt"
#define RTL8192D_AGC_TAB "rtl8192DU\\AGC_TAB.txt"
#define RTL8192D_AGC_TAB_2G "rtl8192DU\\AGC_TAB_2G.txt"
#define RTL8192D_AGC_TAB_5G "rtl8192DU\\AGC_TAB_5G.txt"
#define RTL8192D_PHY_RADIO_A "rtl8192DU\\radio_a.txt"
#define RTL8192D_PHY_RADIO_B "rtl8192DU\\radio_b.txt"
#define RTL8192D_PHY_RADIO_A_intPA "rtl8192DU\\radio_a_intPA.txt"
#define RTL8192D_PHY_RADIO_B_intPA "rtl8192DU\\radio_b_intPA.txt"
#define RTL8192D_PHY_MACREG "rtl8192DU\\MAC_REG.txt"
//---------------------------------------------------------------------
// RTL8192DU From header
//---------------------------------------------------------------------
// Fw Array
#define Rtl8192D_FwImageArray Rtl8192DUFwImgArray
// Fw Array
#define Rtl8192D_FwImageArray Rtl8192DUFwImgArray
// MAC/BB/PHY Array
#define Rtl8192D_MAC_Array Rtl8192DUMAC_2T_Array
#define Rtl8192D_AGCTAB_Array Rtl8192DUAGCTAB_Array
#define Rtl8192D_AGCTAB_5GArray Rtl8192DUAGCTAB_5GArray
#define Rtl8192D_AGCTAB_2GArray Rtl8192DUAGCTAB_2GArray
#define Rtl8192D_AGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
#define Rtl8192D_AGCTAB_1TArray Rtl8192DUAGCTAB_1TArray
#define Rtl8192D_PHY_REG_2TArray Rtl8192DUPHY_REG_2TArray
#define Rtl8192D_PHY_REG_1TArray Rtl8192DUPHY_REG_1TArray
#define Rtl8192D_PHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
#define Rtl8192D_PHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
#define Rtl8192D_RadioA_2TArray Rtl8192DURadioA_2TArray
#define Rtl8192D_RadioA_1TArray Rtl8192DURadioA_1TArray
#define Rtl8192D_RadioB_2TArray Rtl8192DURadioB_2TArray
#define Rtl8192D_RadioB_1TArray Rtl8192DURadioB_1TArray
#define Rtl8192D_RadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
// MAC/BB/PHY Array
#define Rtl8192D_MAC_Array Rtl8192DUMAC_2T_Array
#define Rtl8192D_AGCTAB_Array Rtl8192DUAGCTAB_Array
#define Rtl8192D_AGCTAB_5GArray Rtl8192DUAGCTAB_5GArray
#define Rtl8192D_AGCTAB_2GArray Rtl8192DUAGCTAB_2GArray
#define Rtl8192D_AGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
#define Rtl8192D_AGCTAB_1TArray Rtl8192DUAGCTAB_1TArray
#define Rtl8192D_PHY_REG_2TArray Rtl8192DUPHY_REG_2TArray
#define Rtl8192D_PHY_REG_1TArray Rtl8192DUPHY_REG_1TArray
#define Rtl8192D_PHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
#define Rtl8192D_PHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
#define Rtl8192D_RadioA_2TArray Rtl8192DURadioA_2TArray
#define Rtl8192D_RadioA_1TArray Rtl8192DURadioA_1TArray
#define Rtl8192D_RadioB_2TArray Rtl8192DURadioB_2TArray
#define Rtl8192D_RadioB_1TArray Rtl8192DURadioB_1TArray
#define Rtl8192D_RadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
// Array length
#define Rtl8192D_FwImageArrayLength Rtl8192DUImgArrayLength
#define Rtl8192D_MAC_ArrayLength Rtl8192DUMAC_2T_ArrayLength
#define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DUAGCTAB_5GArrayLength
#define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DUAGCTAB_2GArrayLength
#define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DUAGCTAB_2TArrayLength
#define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DUAGCTAB_1TArrayLength
#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DUAGCTAB_ArrayLength
#define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DUPHY_REG_2TArrayLength
#define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DUPHY_REG_1TArrayLength
#define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DUPHY_REG_Array_PGLength
#define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DUPHY_REG_Array_MPLength
#define Rtl8192D_RadioA_2TArrayLength Rtl8192DURadioA_2TArrayLength
#define Rtl8192D_RadioB_2TArrayLength Rtl8192DURadioB_2TArrayLength
#define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DURadioA_2T_intPAArrayLength
#define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DURadioB_2T_intPAArrayLength
// The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24.
/* #define Rtl819XFwImageArray Rtl8192DUFwImgArray
#define Rtl819XMAC_Array Rtl8192DUMAC_2TArray
#define Rtl819XAGCTAB_Array Rtl8192DUAGCTAB_Array
#define Rtl819XAGCTAB_5GArray Rtl8192DUAGCTAB_5GArray
#define Rtl819XAGCTAB_2GArray Rtl8192DUAGCTAB_2GArray
#define Rtl819XPHY_REG_2TArray Rtl8192DUPHY_REG_2TArray
#define Rtl819XPHY_REG_1TArray Rtl8192DUPHY_REG_1TArray
#define Rtl819XRadioA_2TArray Rtl8192DURadioA_2TArray
#define Rtl819XRadioA_1TArray Rtl8192DURadioA_1TArray
#define Rtl819XRadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
#define Rtl819XRadioB_2TArray Rtl8192DURadioB_2TArray
#define Rtl819XRadioB_1TArray Rtl8192DURadioB_1TArray
#define Rtl819XRadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
#define Rtl819XPHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
#define Rtl819XPHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
#define Rtl819XAGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
#define Rtl819XAGCTAB_1TArray Rtl8192DUAGCTAB_1TArray*/
#endif
// Array length
#define Rtl8192D_FwImageArrayLength Rtl8192DUImgArrayLength
#define Rtl8192D_MAC_ArrayLength Rtl8192DUMAC_2T_ArrayLength
#define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DUAGCTAB_5GArrayLength
#define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DUAGCTAB_2GArrayLength
#define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DUAGCTAB_2TArrayLength
#define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DUAGCTAB_1TArrayLength
#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DUAGCTAB_ArrayLength
#define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DUPHY_REG_2TArrayLength
#define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DUPHY_REG_1TArrayLength
#define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DUPHY_REG_Array_PGLength
#define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DUPHY_REG_Array_MPLength
#define Rtl8192D_RadioA_2TArrayLength Rtl8192DURadioA_2TArrayLength
#define Rtl8192D_RadioB_2TArrayLength Rtl8192DURadioB_2TArrayLength
#define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DURadioA_2T_intPAArrayLength
#define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DURadioB_2T_intPAArrayLength
// The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24.
#define DRVINFO_SZ 4 // unit is 8bytes
#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
@ -191,15 +103,15 @@
// By tynli. 2009.12.04.
//
#define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D0 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D1 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D2 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D3 )
(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D0 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D1 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D2 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D3 )
#define FW_8192D_SIZE 0x8020 // Max FW len = 32k + 32(FW header length).
#define FW_8192D_START_ADDRESS 0x1000
#define FW_8192D_END_ADDRESS 0x1FFF
#define FW_8192D_START_ADDRESS 0x1000
#define FW_8192D_END_ADDRESS 0x1FFF
#define MAX_PAGE_SIZE 4096 // @ page : 4k bytes
@ -251,11 +163,11 @@ typedef struct _RT_8192D_FIRMWARE_HDR {//8-byte alinment required
#define BCN_DMA_ATIME_INT_TIME 0x02
typedef enum _BT_CoType{
BT_2Wire = 0,
BT_ISSC_3Wire = 1,
BT_Accel = 2,
BT_2Wire = 0,
BT_ISSC_3Wire = 1,
BT_Accel = 2,
BT_CSR = 3,
BT_CSR_ENHAN = 4,
BT_CSR_ENHAN = 4,
BT_RTL8756 = 5,
} BT_CoType, *PBT_CoType;
@ -271,7 +183,7 @@ typedef enum _BT_ServiceType{
BT_HID_Idle = 3,
BT_Scan = 4,
BT_Idle = 5,
BT_OtherAction = 6,
BT_OtherAction = 6,
BT_Busy = 7,
BT_OtherBusy = 8,
} BT_ServiceType, *PBT_ServiceType;
@ -282,17 +194,17 @@ typedef enum _BT_RadioShared{
} BT_RadioShared, *PBT_RadioShared;
typedef struct _BT_COEXIST_STR{
u8 BluetoothCoexist;
u8 BT_Ant_Num;
u8 BT_CoexistType;
u8 BT_State;
u8 BT_CUR_State; //0:on, 1:off
u8 BT_Ant_isolation; //0:good, 1:bad
u8 BT_PapeCtrl; //0:SW, 1:SW/HW dynamic
u8 BT_Service;
u8 BT_RadioSharedType;
u8 Ratio_Tx;
u8 Ratio_PRI;
u8 BluetoothCoexist;
u8 BT_Ant_Num;
u8 BT_CoexistType;
u8 BT_State;
u8 BT_CUR_State; //0:on, 1:off
u8 BT_Ant_isolation; //0:good, 1:bad
u8 BT_PapeCtrl; //0:SW, 1:SW/HW dynamic
u8 BT_Service;
u8 BT_RadioSharedType;
u8 Ratio_Tx;
u8 Ratio_PRI;
}BT_COEXIST_STR, *PBT_COEXIST_STR;
@ -318,7 +230,7 @@ typedef enum _USB_RX_AGG_MODE{
// Note: We will divide number of page equally for each queue other than public queue!
#define TX_TOTAL_PAGE_NUMBER 0xF8
#define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER + 1)
#define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER + 1)
// For Normal Chip Setting
// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER
@ -328,13 +240,13 @@ typedef enum _USB_RX_AGG_MODE{
// For Test Chip Setting
// (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER
#define TEST_PAGE_NUM_PUBQ 0x89
#define TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC 0x7A
#define NORMAL_PAGE_NUM_PUBQ_92D_DUAL_MAC 0x5A
#define NORMAL_PAGE_NUM_HPQ_92D_DUAL_MAC 0x10
#define NORMAL_PAGE_NUM_LPQ_92D_DUAL_MAC 0x10
#define NORMAL_PAGE_NUM_NORMALQ_92D_DUAL_MAC 0
#define TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC 0x7A
#define NORMAL_PAGE_NUM_PUBQ_92D_DUAL_MAC 0x5A
#define NORMAL_PAGE_NUM_HPQ_92D_DUAL_MAC 0x10
#define NORMAL_PAGE_NUM_LPQ_92D_DUAL_MAC 0x10
#define NORMAL_PAGE_NUM_NORMALQ_92D_DUAL_MAC 0
#define TX_PAGE_BOUNDARY_DUAL_MAC (TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC + 1)
#define TX_PAGE_BOUNDARY_DUAL_MAC (TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC + 1)
// For Test Chip Setting
#define WMM_TEST_TX_TOTAL_PAGE_NUMBER 0xF5
@ -349,15 +261,15 @@ typedef enum _USB_RX_AGG_MODE{
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5
#define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
#define WMM_NORMAL_PAGE_NUM_PUBQ 0xB0
#define WMM_NORMAL_PAGE_NUM_PUBQ 0xB0
#define WMM_NORMAL_PAGE_NUM_HPQ 0x29
#define WMM_NORMAL_PAGE_NUM_LPQ 0x1C
#define WMM_NORMAL_PAGE_NUM_LPQ 0x1C
#define WMM_NORMAL_PAGE_NUM_NPQ 0x1C
#define WMM_NORMAL_PAGE_NUM_PUBQ_92D 0X65//0x82
#define WMM_NORMAL_PAGE_NUM_HPQ_92D 0X30//0x29
#define WMM_NORMAL_PAGE_NUM_LPQ_92D 0X30
#define WMM_NORMAL_PAGE_NUM_NPQ_92D 0X30
#define WMM_NORMAL_PAGE_NUM_PUBQ_92D 0X65//0x82
#define WMM_NORMAL_PAGE_NUM_HPQ_92D 0X30//0x29
#define WMM_NORMAL_PAGE_NUM_LPQ_92D 0X30
#define WMM_NORMAL_PAGE_NUM_NPQ_92D 0X30
//-------------------------------------------------------------------------
// Chip specific
@ -434,9 +346,7 @@ enum c2h_id_8192d {
MAX_C2HEVENT
};
#ifdef CONFIG_PCI_HCI
struct hal_data_8192de
{
struct hal_data_8192de {
HAL_VERSION VersionID;
// add for 92D Phy mode/mac/Band mode
MACPHY_MODE_8192D MacPhyMode92D;
@ -624,9 +534,6 @@ typedef struct hal_data_8192de HAL_DATA_TYPE, *PHAL_DATA_TYPE;
void InterruptRecognized8192DE(struct adapter *Adapter, PRT_ISR_CONTENT pIsrContent);
VOID UpdateInterruptMask8192DE(struct adapter *Adapter, u32 AddMSR, u32 RemoveMSR);
#endif
#ifdef CONFIG_USB_HCI
//should be renamed and moved to another file
typedef enum _INTERFACE_SELECT_8192DUSB{
@ -833,7 +740,6 @@ struct hal_data_8192du
};
typedef struct hal_data_8192du HAL_DATA_TYPE, *PHAL_DATA_TYPE;
#endif
#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData))
#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type)

8
include/rtl8192d_led.h
View file

@ -28,15 +28,7 @@
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
#ifdef CONFIG_USB_HCI
void rtl8192du_InitSwLeds(struct adapter *padapter);
void rtl8192du_DeInitSwLeds(struct adapter *padapter);
#endif
#ifdef CONFIG_PCI_HCI
void rtl8192de_gen_RefreshLedState(struct adapter *Adapter);
void rtl8192de_InitSwLeds(struct adapter *padapter);
void rtl8192de_DeInitSwLeds(struct adapter *padapter);
#endif
#endif

59
include/rtl8192d_recv.h
View file

@ -25,62 +25,25 @@
#include <drv_types.h>
#ifdef PLATFORM_OS_XP
#ifdef CONFIG_SDIO_HCI
#define NR_RECVBUFF 1024//512//128
#else
#define NR_RECVBUFF (16)
#endif
#elif defined(PLATFORM_OS_CE)
#ifdef CONFIG_SDIO_HCI
#define NR_RECVBUFF (128)
#else
#define NR_RECVBUFF (4)
#endif
#else
#ifdef CONFIG_SINGLE_RECV_BUF
#define NR_RECVBUFF (1)
#else
#define NR_RECVBUFF (4)
#endif //CONFIG_SINGLE_RECV_BUF
#define NR_PREALLOC_RECV_SKB (8)
#endif
#define NR_PREALLOC_RECV_SKB (8)
#define RECV_BLK_SZ 512
#define RECV_BLK_CNT 16
#define RECV_BLK_TH RECV_BLK_CNT
#if defined(CONFIG_USB_HCI)
#ifdef PLATFORM_OS_CE
#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k
#else
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
//#define MAX_RECVBUF_SZ (32768) // 32k
//#define MAX_RECVBUF_SZ (16384) //16K
//#define MAX_RECVBUF_SZ (10240) //10K
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) // 8K
#else
#define MAX_RECVBUF_SZ (15360) // 15k < 16k
#endif
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
#ifdef CONFIG_PLATFORM_MSTAR
#define MAX_RECVBUF_SZ (8192) // 8K
#else
#define MAX_RECVBUF_SZ (4000) // about 4K
#define MAX_RECVBUF_SZ (15360) // 15k < 16k
#endif
#endif
#elif defined(CONFIG_PCI_HCI)
//#ifndef CONFIG_MINIMAL_MEMORY_USAGE
// #define MAX_RECVBUF_SZ (9100)
//#else
#else
#define MAX_RECVBUF_SZ (4000) // about 4K
//#endif
#define RX_MPDU_QUEUE 0
#define RX_CMD_QUEUE 1
#define RX_MAX_QUEUE 2
#endif
#define RECV_BULK_IN_ADDR 0x80
@ -89,8 +52,7 @@
#define PHY_RSSI_SLID_WIN_MAX 100
#define PHY_LINKQUALITY_SLID_WIN_MAX 20
struct phy_stat
{
struct phy_stat {
unsigned int phydw0;
unsigned int phydw1;
@ -111,7 +73,6 @@ struct phy_stat
// Rx smooth factor
#define Rx_Smooth_Factor (20)
#ifdef CONFIG_USB_HCI
typedef struct _INTERRUPT_MSG_FORMAT_EX{
unsigned int C2H_MSG0;
unsigned int C2H_MSG1;
@ -125,12 +86,6 @@ typedef struct _INTERRUPT_MSG_FORMAT_EX{
void rtl8192du_init_recvbuf(struct adapter *padapter, struct recv_buf *precvbuf);
int rtl8192du_init_recv_priv(struct adapter * padapter);
void rtl8192du_free_recv_priv(struct adapter * padapter);
#endif
#ifdef CONFIG_PCI_HCI
int rtl8192de_init_recv_priv(struct adapter * padapter);
void rtl8192de_free_recv_priv(struct adapter * padapter);
#endif
void rtl8192d_translate_rx_signal_stuff(union recv_frame *precvframe, struct phy_stat *pphy_status);
void rtl8192d_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *pdesc);

110
include/rtl8192d_spec.h
View file

@ -683,11 +683,7 @@ Default: 00b.
#define EEPROM_Default_internalPA_SP3T_C9 0xAA
#define EEPROM_Default_internalPA_SP3T_CC 0xAF
#define EEPROM_Default_internalPA_SPDT_C9 0xAA
#ifdef CONFIG_PCI_HCI
#define EEPROM_Default_internalPA_SPDT_CC 0xA0
#else
#define EEPROM_Default_internalPA_SPDT_CC 0xFA
#endif
#define EEPROM_CHANNEL_PLAN_FCC 0x0
#define EEPROM_CHANNEL_PLAN_IC 0x1
@ -714,87 +710,6 @@ Default: 00b.
#define RTL8192_EEPROM_ID 0x8129
#define EEPROM_WAPI_SUPPORT 0x78
#ifdef CONFIG_PCI_HCI
#define RT_IBSS_INT_MASKS (IMR_BcnInt | IMR_TBDOK | IMR_TBDER)
#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
#define RT_BSS_INT_MASKS (RT_IBSS_INT_MASKS)
#define RTL8190_EEPROM_ID 0x8129 // 0-1
#define EEPROM_HPON 0x02 // LDO settings.2-5
#define EEPROM_CLK 0x06 // Clock settings.6-7
#define EEPROM_MAC_FUNCTION 0x08 // SE Test mode.8
#define EEPROM_VID 0x28 // SE Vendor ID.A-B
#define EEPROM_DID 0x2A // SE Device ID. C-D
#define EEPROM_SVID 0x2C // SE Vendor ID.E-F
#define EEPROM_SMID 0x2E // SE PCI Subsystem ID. 10-11
#define EEPROM_MAC_ADDR 0x16 // SEMAC Address. 12-17
#define EEPROM_MAC_ADDR_MAC0_92D 0x55
#define EEPROM_MAC_ADDR_MAC1_92D 0x5B
//----------------------------------------------------------------
// 2.4G band Tx power index setting
#define EEPROM_CCK_TX_PWR_INX_2G 0x61
#define EEPROM_HT40_1S_TX_PWR_INX_2G 0x67
#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G 0x6D
#define EEPROM_HT20_TX_PWR_INX_DIFF_2G 0x70
#define EEPROM_OFDM_TX_PWR_INX_DIFF_2G 0x73
#define EEPROM_HT40_MAX_PWR_OFFSET_2G 0x76
#define EEPROM_HT20_MAX_PWR_OFFSET_2G 0x79
//5GL channel 32-64
#define EEPROM_HT40_1S_TX_PWR_INX_5GL 0x7C
#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GL 0x82
#define EEPROM_HT20_TX_PWR_INX_DIFF_5GL 0x85
#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GL 0x88
#define EEPROM_HT40_MAX_PWR_OFFSET_5GL 0x8B
#define EEPROM_HT20_MAX_PWR_OFFSET_5GL 0x8E
//5GM channel 100-140
#define EEPROM_HT40_1S_TX_PWR_INX_5GM 0x91
#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GM 0x97
#define EEPROM_HT20_TX_PWR_INX_DIFF_5GM 0x9A
#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GM 0x9D
#define EEPROM_HT40_MAX_PWR_OFFSET_5GM 0xA0
#define EEPROM_HT20_MAX_PWR_OFFSET_5GM 0xA3
//5GH channel 149-165
#define EEPROM_HT40_1S_TX_PWR_INX_5GH 0xA6
#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GH 0xAC
#define EEPROM_HT20_TX_PWR_INX_DIFF_5GH 0xAF
#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GH 0xB2
#define EEPROM_HT40_MAX_PWR_OFFSET_5GH 0xB5
#define EEPROM_HT20_MAX_PWR_OFFSET_5GH 0xB8
#define EEPROM_CHANNEL_PLAN 0xBB // Map of supported channels.
#define EEPROM_IQK_DELTA 0xBC
#define EEPROM_LCK_DELTA 0xBC
#define EEPROM_XTAL_K 0xBD //[7:5]
#define EEPROM_TSSI_A_5G 0xBE
#define EEPROM_TSSI_B_5G 0xBF
#define EEPROM_TSSI_AB_5G 0xC0
#define EEPROM_THERMAL_METER 0xC3 //[4:0]
#define EEPROM_PATHDIV 0xC4
#define EEPROM_RF_OPT1 0xC4
#define EEPROM_RF_OPT2 0xC5
#define EEPROM_RF_OPT3 0xC6
#define EEPROM_RF_OPT4 0xC7
#define EEPROM_RF_OPT5 0xC8
#define EEPROM_RF_OPT6 0xC9
#define EEPROM_VERSION 0xCA
#define EEPROM_CUSTOMER_ID 0xCB
#define EEPROM_RF_OPT7 0xCC
#define EEPROM_WIDIPAIRING_ADDR 0xF0
#define EEPROM_WIDIPAIRING_KEY 0xF6
#define EEPROM_DEF_PART_NO 0x3FD //Byte
#define EEPROME_CHIP_VERSION_L 0x3FF
#define EEPROME_CHIP_VERSION_H 0x3FE
#endif
#ifdef CONFIG_USB_HCI
#define RTL8190_EEPROM_ID 0x8129 // 0-1
#define EEPROM_HPON 0x02 // LDO settings.2-5
#define EEPROM_CLK 0x06 // Clock settings.6-7
@ -930,31 +845,6 @@ Default: 00b.
#define EEPROM_USB_DEVICE_PWR BIT(2)
#define EEPROM_EP_NUMBER (BIT(3)|BIT(4))
#if 0
#define EEPROM_CHANNEL_PLAN_FCC 0x0
#define EEPROM_CHANNEL_PLAN_IC 0x1
#define EEPROM_CHANNEL_PLAN_ETSI 0x2
#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
#define EEPROM_CHANNEL_PLAN_MKK 0x5
#define EEPROM_CHANNEL_PLAN_MKK1 0x6
#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
#define EEPROM_CHANNEL_PLAN_TELEC 0x8
#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
#define EEPROM_CID_DEFAULT 0x0
#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25.
#endif
#endif
/*===================================================================
=====================================================================
Here the register defines are for 92C. When the define is as same with 92C,

23
include/rtl8192d_xmit.h
View file

@ -133,11 +133,8 @@ void handle_txrpt_ccx_8192d(struct adapter *adapter, void *buf);
#define handle_txrpt_ccx_8192d(adapter, buf) do {} while(0)
#endif
#ifdef CONFIG_USB_HCI
#ifdef CONFIG_USB_TX_AGGREGATION
#define MAX_TX_AGG_PACKET_NUMBER 0xFF
#endif
s32 rtl8192du_init_xmit_priv(struct adapter * padapter);
@ -157,24 +154,4 @@ s32 rtl8192du_hostap_mgnt_xmit_entry(struct adapter *padapter, _pkt *pkt);
#endif
#ifdef CONFIG_PCI_HCI
s32 rtl8192de_init_xmit_priv(struct adapter * padapter);
void rtl8192de_free_xmit_priv(struct adapter * padapter);
s32 rtl8192de_enqueue_xmitbuf(struct rtw_tx_ring *ring, struct xmit_buf *pxmitbuf);
struct xmit_buf *rtl8192de_dequeue_xmitbuf(struct rtw_tx_ring *ring);
void rtl8192de_xmitframe_resume(struct adapter *padapter);
s32 rtl8192de_mgnt_xmit(struct adapter *padapter, struct xmit_frame *pmgntframe);
s32 rtl8192de_hal_xmit(struct adapter *padapter, struct xmit_frame *pxmitframe);
#ifdef CONFIG_HOSTAPD_MLME
s32 rtl8192de_hostap_mgnt_xmit_entry(struct adapter *padapter, _pkt *pkt);
#endif
#endif
#endif

5
include/rtw_cmd.h
View file

@ -104,11 +104,6 @@
u8 *evt_buf; //shall be non-paged, and 4 bytes aligned
u8 *evt_allocated_buf;
u32 evt_done_cnt;
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
u8 *c2h_mem;
u8 *allocated_c2h_mem;
#endif
};
#define init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code) \

13
include/rtw_eeprom.h
View file

@ -44,11 +44,6 @@
#define EUROPE 0x1 //temp, should be provided later
#define JAPAN 0x2 //temp, should be provided later
#ifdef CONFIG_SDIO_HCI
#define eeprom_cis0_sz 17
#define eeprom_cis1_sz 50
#endif
#define EEPROM_CID_DEFAULT 0x0
#define EEPROM_CID_ALPHA 0x1
#define EEPROM_CID_Senao 0x3
@ -140,16 +135,8 @@ struct eeprom_priv
u8 EEPROMRFGainOffset;
u8 EEPROMRFGainVal;
#endif //CONFIG_RF_GAIN_OFFSET
#ifdef CONFIG_SDIO_HCI
u8 sdio_setting;
u32 ocr;
u8 cis0[eeprom_cis0_sz];
u8 cis1[eeprom_cis1_sz];
#endif
};
extern void eeprom_write16(struct adapter *padapter, u16 reg, u16 data);
extern u16 eeprom_read16(struct adapter *padapter, u16 reg);
extern void read_eeprom_content(struct adapter *padapter);

51
include/rtw_io.h
View file

@ -36,7 +36,6 @@
#include <linux/spinlock.h>
#include <asm/atomic.h>
#ifdef CONFIG_USB_HCI
#include <linux/usb.h>
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21))
#include <linux/usb_ch9.h>
@ -44,8 +43,6 @@
#include <linux/usb/ch9.h>
#endif
#endif //CONFIG_USB_HCI
#define NUM_IOREQ 8
#define MAX_PROT_SZ (64-16)
@ -155,48 +152,12 @@ struct io_req {
u8 *pbuf;
_sema sema;
#ifdef PLATFORM_OS_CE
#ifdef CONFIG_USB_HCI
// URB handler for rtw_write_mem
USB_TRANSFER usb_transfer_write_mem;
#endif
#endif
void (*_async_io_callback)(struct adapter *padater, struct io_req *pio_req, u8 *cnxt);
u8 *cnxt;
#ifdef PLATFORM_OS_XP
PMDL pmdl;
PIRP pirp;
#ifdef CONFIG_SDIO_HCI
PSDBUS_REQUEST_PACKET sdrp;
#endif
#endif
};
struct intf_hdl {
/*
u32 intf_option;
u32 bus_status;
u32 do_flush;
u8 *adapter;
u8 *intf_dev;
struct intf_priv *pintfpriv;
u8 cnt;
void (*intf_hdl_init)(u8 *priv);
void (*intf_hdl_unload)(u8 *priv);
void (*intf_hdl_open)(u8 *priv);
void (*intf_hdl_close)(u8 *priv);
struct _io_ops io_ops;
//u8 intf_status;//moved to struct intf_priv
u16 len;
u16 done_len;
*/
struct adapter *padapter;
struct dvobj_priv *pintf_dev;// pointer to &(padapter->dvobjpriv);
@ -315,19 +276,7 @@ struct reg_protocol_wt {
#endif
};
#ifdef CONFIG_PCI_HCI
#define MAX_CONTINUAL_IO_ERR 4
#endif
#ifdef CONFIG_USB_HCI
#define MAX_CONTINUAL_IO_ERR 4
#endif
#ifdef CONFIG_SDIO_HCI
#define SD_IO_TRY_CNT (8)
#define MAX_CONTINUAL_IO_ERR SD_IO_TRY_CNT
#endif
int rtw_inc_and_chk_continual_io_error(struct dvobj_priv *dvobj);
void rtw_reset_continual_io_error(struct dvobj_priv *dvobj);

32
include/rtw_led.h
View file

@ -119,7 +119,6 @@ typedef struct _LED_871x{
_timer BlinkTimer; // Timer object for led blinking.
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
u8 bSWLedCtrl;
// ALPHA, added by chiyoko, 20090106
@ -131,16 +130,8 @@ typedef struct _LED_871x{
#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
_workitem BlinkWorkItem; // Workitem used by BlinkTimer to manipulate H/W to blink LED.
#endif
#endif //defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#if defined(CONFIG_PCI_HCI)
u8 bLedSlowBlinkInProgress;//added by vivi, for led new mode
#endif
} LED_871x, *PLED_871x;
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#define IS_LED_WPS_BLINKING(_LED_871x) (((PLED_871x)_LED_871x)->CurrLedState==LED_BLINK_WPS \
|| ((PLED_871x)_LED_871x)->CurrLedState==LED_BLINK_WPS_STOP \
|| ((PLED_871x)_LED_871x)->bLedWPSBlinkInProgress)
@ -169,29 +160,6 @@ LedControl871x(
struct adapter *padapter,
LED_CTL_MODE LedAction
);
#endif //defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#if defined(CONFIG_PCI_HCI)
//================================================================================
// LED customization.
//================================================================================
typedef enum _LED_STRATEGY_871x{
SW_LED_MODE0 = 0, // SW control 1 LED via GPIO0. It is default option.
SW_LED_MODE1 = 1, // SW control for PCI Express
SW_LED_MODE2 = 2, // SW control for Cameo.
SW_LED_MODE3 = 3, // SW contorl for RunTop.
SW_LED_MODE4 = 4, // SW control for Netcore
SW_LED_MODE5 = 5, //added by vivi, for led new mode, DLINK
SW_LED_MODE6 = 6, //added by vivi, for led new mode, PRONET
SW_LED_MODE7 = 7, //added by chiyokolin, for Lenovo, PCI Express Minicard Spec Rev.1.2 spec
SW_LED_MODE8 = 8, //added by chiyokolin, for QMI
SW_LED_MODE9 = 9, //added by chiyokolin, for BITLAND, PCI Express Minicard Spec Rev.1.1
SW_LED_MODE10 = 10, //added by chiyokolin, for Edimax-ASUS
HW_LED = 50, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
LED_ST_NONE = 99,
}LED_STRATEGY_871x, *PLED_STRATEGY_871x;
#endif //defined(CONFIG_PCI_HCI)
struct led_priv{
/* add for led controll */

15
include/rtw_mlme_ext.h
View file

@ -44,20 +44,7 @@
#define REASSOC_LIMIT (4)
#define READDBA_LIMIT (2)
#ifdef CONFIG_GSPI_HCI
#define ROAMING_LIMIT 5
#else
#define ROAMING_LIMIT 8
#endif
//#define IOCMD_REG0 0x10250370
//#define IOCMD_REG1 0x10250374
//#define IOCMD_REG2 0x10250378
//#define FW_DYNAMIC_FUN_SWITCH 0x10250364
//#define WRITE_BB_CMD 0xF0000001
//#define SET_CHANNEL_CMD 0xF3000000
//#define UPDATE_RA_CMD 0xFD0000A2
#define ROAMING_LIMIT 8
#define DYNAMIC_FUNC_DISABLE (0x0)

3
include/rtw_mp.h
View file

@ -115,8 +115,6 @@ struct mp_xmit_frame
struct adapter *padapter;
#ifdef CONFIG_USB_HCI
//insert urb, irp, and irpcnt info below...
//max frag_cnt = 8
@ -130,7 +128,6 @@ struct mp_xmit_frame
sint last[8];
uint irpcnt;
uint fragcnt;
#endif /* CONFIG_USB_HCI */
uint mem[(MAX_MP_XMITBUF_SZ >> 2)];
};

11
include/rtw_pwrctrl.h
View file

@ -212,17 +212,6 @@ struct pwrctrl_priv
u32 cur_ps_level;
u32 reg_rfps_level;
#ifdef CONFIG_PCI_HCI
//just for PCIE ASPM
u8 b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00.
u8 b_support_backdoor;
//just for PCIE ASPM
u8 const_amdpci_aspm;
#endif
uint ips_enter_cnts;
uint ips_leave_cnts;

44
include/rtw_recv.h
View file

@ -209,41 +209,17 @@ struct rx_pkt_attrib {
#define RXDESC_SIZE 24
#define RXDESC_OFFSET RXDESC_SIZE
struct recv_stat
{
struct recv_stat {
unsigned int rxdw0;
unsigned int rxdw1;
unsigned int rxdw2;
unsigned int rxdw3;
unsigned int rxdw4;
unsigned int rxdw5;
#ifdef CONFIG_PCI_HCI
unsigned int rxdw6;
unsigned int rxdw7;
#endif
};
#define EOR BIT(30)
#ifdef CONFIG_PCI_HCI
#define PCI_MAX_RX_QUEUE 1// MSDU packet queue, Rx Command Queue
#define PCI_MAX_RX_COUNT 128
struct rtw_rx_ring {
struct recv_stat *desc;
dma_addr_t dma;
unsigned int idx;
struct sk_buff *rx_buf[PCI_MAX_RX_COUNT];
};
#endif
/*
accesser of recv_priv: rtw_recv_entry(dispatch / passive level); recv_thread(passive) ; returnpkt(dispatch)
; halt(passive) ;
@ -283,7 +259,6 @@ struct recv_priv
uint rx_smallpacket_crcerr;
uint rx_middlepacket_crcerr;
#ifdef CONFIG_USB_HCI
//u8 *pallocated_urb_buf;
_sema allrxreturnevt;
uint ff_hwaddr;
@ -295,7 +270,6 @@ struct recv_priv
u8 *int_in_buf;
#endif //CONFIG_USB_INTERRUPT_IN_PIPE
#endif
struct tasklet_struct irq_prepare_beacon_tasklet;
struct tasklet_struct recv_tasklet;
struct sk_buff_head free_recv_skb_queue;
@ -314,18 +288,6 @@ struct recv_priv
_queue free_recv_buf_queue;
u32 free_recv_buf_queue_cnt;
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
_queue recv_buf_pending_queue;
#endif
#ifdef CONFIG_PCI_HCI
// Rx
struct rtw_rx_ring rx_ring[PCI_MAX_RX_QUEUE];
int rxringcount;
u16 rxbuffersize;
#endif
//For display the phy informatiom
u8 is_signal_dbg; // for debug
u8 signal_strength_dbg; // for debug
s8 rssi;
@ -390,8 +352,6 @@ struct recv_buf
u8 *ptail;
u8 *pend;
#ifdef CONFIG_USB_HCI
PURB purb;
dma_addr_t dma_transfer_addr; /* (in) dma addr for transfer_buffer */
u32 alloc_sz;
@ -399,8 +359,6 @@ struct recv_buf
u8 irp_pending;
int transfer_len;
#endif
_pkt *pskb;
u8 reuse;
};

118
include/rtw_xmit.h
View file

@ -24,23 +24,6 @@
#include <osdep_service.h>
#include <drv_types.h>
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
//#define MAX_XMITBUF_SZ (30720)// (2048)
#ifdef CONFIG_TX_AGGREGATION
#define MAX_XMITBUF_SZ (20480) // 20k
#else
#define MAX_XMITBUF_SZ (12288) //12k 1536*8
#endif
#if defined CONFIG_SDIO_HCI
#define NR_XMITBUFF (16)
#endif
#if defined(CONFIG_GSPI_HCI)
#define NR_XMITBUFF (128)
#endif
#elif defined (CONFIG_USB_HCI)
#ifdef CONFIG_USB_TX_AGGREGATION
#if defined(CONFIG_PLATFORM_ARM_SUNxI) || defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)
#define MAX_XMITBUF_SZ (12288) //12k 1536*8
@ -57,20 +40,8 @@
#else
#define NR_XMITBUFF (4)
#endif //CONFIG_SINGLE_XMIT_BUF
#elif defined (CONFIG_PCI_HCI)
#define MAX_XMITBUF_SZ (1664)
#define NR_XMITBUFF (128)
#endif
#ifdef PLATFORM_OS_CE
#define XMITBUF_ALIGN_SZ 4
#else
#ifdef CONFIG_PCI_HCI
#define XMITBUF_ALIGN_SZ 4
#else
#define XMITBUF_ALIGN_SZ 512
#endif
#endif
// xmit extension buff defination
#define MAX_XMIT_EXTBUF_SZ (1536)
@ -94,12 +65,6 @@
#define HW_QUEUE_ENTRY 8
#ifdef CONFIG_PCI_HCI
//#define TXDESC_NUM 64
#define TXDESC_NUM 128
#define TXDESC_NUM_BE_QUEUE 128
#endif
#define WEP_IV(pattrib_iv, dot11txpn, keyidx)\
do{\
pattrib_iv[0] = dot11txpn._byte_.TSC0;\
@ -147,22 +112,8 @@ do{\
#endif
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#define TXDESC_OFFSET TXDESC_SIZE
#endif
#ifdef CONFIG_USB_HCI
#define PACKET_OFFSET_SZ (8)
#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ)
#endif
#ifdef CONFIG_PCI_HCI
#define TXDESC_OFFSET 0
#define TX_DESC_NEXT_DESC_OFFSET 40
#endif
struct tx_desc{
/* DWORD 0 */
@ -181,19 +132,6 @@ union txdesc {
unsigned int value[TXDESC_SIZE>>2];
};
#ifdef CONFIG_PCI_HCI
#define PCI_MAX_TX_QUEUE_COUNT 8
struct rtw_tx_ring {
struct tx_desc *desc;
dma_addr_t dma;
unsigned int idx;
unsigned int entries;
_queue queue;
u32 qlen;
};
#endif
struct hw_xmit {
//_lock xmit_lock;
//_list pending;
@ -368,9 +306,6 @@ struct xmit_buf
struct submit_ctx *sctx;
#ifdef CONFIG_USB_HCI
//u32 sz[8];
u32 ff_hwaddr;
PURB pxmit_urb[8];
@ -379,23 +314,6 @@ struct xmit_buf
sint last[8];
#endif
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
u8 *phead;
u8 *pdata;
u8 *ptail;
u8 *pend;
u32 ff_hwaddr;
u8 pg_num;
u8 agg_num;
#ifdef PLATFORM_OS_XP
PMDL pxmitbuf_mdl;
PIRP pxmitbuf_irp;
PSDBUS_REQUEST_PACKET pxmitbuf_sdrp;
#endif
#endif
#if defined(DBG_XMIT_BUF )|| defined(DBG_XMIT_BUF_EXT)
u8 no;
#endif
@ -419,17 +337,10 @@ struct xmit_frame
struct xmit_buf *pxmitbuf;
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
u8 pg_num;
u8 agg_num;
#endif
#ifdef CONFIG_USB_HCI
#ifdef CONFIG_USB_TX_AGGREGATION
u8 agg_num;
#endif
s8 pkt_offset;
#endif
#ifdef CONFIG_XMIT_ACK
u8 ack_report;
@ -544,14 +455,9 @@ struct xmit_priv {
u8 wmm_para_seq[4];//sequence for wmm ac parameter strength from large to small. it's value is 0->vo, 1->vi, 2->be, 3->bk.
#ifdef CONFIG_USB_HCI
_sema tx_retevt;//all tx return event;
u8 txirp_cnt;//
#ifdef PLATFORM_OS_CE
USB_TRANSFER usb_transfer_write_port;
// USB_TRANSFER usb_transfer_write_mem;
#endif
struct tasklet_struct xmit_tasklet;
//per AC pending irp
int beq_cnt;
@ -559,26 +465,6 @@ struct xmit_priv {
int viq_cnt;
int voq_cnt;
#endif
#ifdef CONFIG_PCI_HCI
// Tx
struct rtw_tx_ring tx_ring[PCI_MAX_TX_QUEUE_COUNT];
int txringcount[PCI_MAX_TX_QUEUE_COUNT];
u8 beaconDMAing; //flag of indicating beacon is transmiting to HW by DMA
struct tasklet_struct xmit_tasklet;
#endif
#ifdef CONFIG_SDIO_HCI
#ifdef CONFIG_SDIO_TX_TASKLET
struct tasklet_struct xmit_tasklet;
#else
_thread_hdl_ SdioXmitThread;
_sema SdioXmitSema;
_sema SdioXmitTerminateSema;
#endif /* CONFIG_SDIO_TX_TASKLET */
#endif /* CONFIG_SDIO_HCI */
_queue free_xmitbuf_queue;
_queue pending_xmitbuf_queue;
u8 *pallocated_xmitbuf;
@ -593,11 +479,7 @@ struct xmit_priv {
u16 nqos_ssn;
#ifdef CONFIG_TX_EARLY_MODE
#ifdef CONFIG_SDIO_HCI
#define MAX_AGG_PKT_NUM 20
#else
#define MAX_AGG_PKT_NUM 256 //Max tx ampdu coounts
#endif
struct agg_pkt_info agg_pkt[MAX_AGG_PKT_NUM];
#endif

52
os_dep/ioctl_linux.c
View file

@ -34,15 +34,10 @@
#include <rtw_mp_ioctl.h>
#ifdef CONFIG_USB_HCI
#include <usb_ops.h>
#endif //CONFIG_USB_HCI
#include <rtw_version.h>
#include <rtl8188e_hal.h>
#ifdef CONFIG_GSPI_HCI
#include <gspi_ops.h>
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27))
#define iwe_stream_add_event(a, b, c, d, e) iwe_stream_add_event(b, c, d, e)
@ -6955,9 +6950,7 @@ static int rtw_dbg_port(struct net_device *dev,
pxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt,
pxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xframe_ext_cnt,
precvpriv->free_recvframe_cnt);
#ifdef CONFIG_USB_HCI
DBG_871X("rx_urb_pending_cn=%d\n", precvpriv->rx_pending_cnt);
#endif
}
break;
case 0x09:
@ -9210,11 +9203,7 @@ static int rtw_mp_efuse_get(struct net_device *dev,
}
else if (strcmp(tmp[0], "mac") == 0)
{
#ifdef CONFIG_SDIO_HCI
addr = EEPROM_MAC_ADDR_88ES;
#else
addr = EEPROM_MAC_ADDR_88EU;
#endif
addr = EEPROM_MAC_ADDR_88EU;
cnts = 6;
@ -9232,7 +9221,6 @@ static int rtw_mp_efuse_get(struct net_device *dev,
goto exit;
}
// DBG_871X("%s: MAC address={", __FUNCTION__);
*extra = 0;
for (i=0; i<cnts; i++)
{
@ -9721,16 +9709,7 @@ static int rtw_mp_efuse_set(struct net_device *dev,
goto exit;
}
//mac,00e04c871200
#ifdef CONFIG_USB_HCI
addr = EEPROM_MAC_ADDR_88EU;
#endif
#ifdef CONFIG_SDIO_HCI
addr = EEPROM_MAC_ADDR_88ES;
#endif
#ifdef CONFIG_PCI_HCI
addr = EEPROM_MAC_ADDR_88EE;
#endif
addr = EEPROM_MAC_ADDR_88EU;
cnts = strlen(tmp[1]);
if (cnts%2)
@ -9783,21 +9762,14 @@ static int rtw_mp_efuse_set(struct net_device *dev,
goto exit;
}
#ifdef CONFIG_USB_HCI
addr = EEPROM_VID_88EE;
#endif
#ifdef CONFIG_PCI_HCI
addr = EEPROM_VID_88EE;
#endif
addr = EEPROM_VID_88EE;
cnts = strlen(tmp[1]);
if (cnts%2)
{
if (cnts%2) {
err = -EINVAL;
goto exit;
}
cnts /= 2;
if (cnts == 0)
{
if (cnts == 0) {
err = -EINVAL;
goto exit;
}
@ -10702,10 +10674,6 @@ static int rtw_widi_set_probe_request(struct net_device *dev,
#include <rtl8188e_hal.h>
extern void rtl8188e_cal_txdesc_chksum(struct tx_desc *ptxdesc);
#define cal_txdesc_chksum rtl8188e_cal_txdesc_chksum
#ifdef CONFIG_SDIO_HCI
extern void rtl8188es_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf);
#define fill_default_txdesc rtl8188es_fill_default_txdesc
#endif // CONFIG_SDIO_HCI
static s32 initLoopback(struct adapter *padapter)
{
@ -10926,16 +10894,6 @@ static struct xmit_frame* createloopbackpkt(struct adapter *padapter, u32 size)
desc->txdw5 = cpu_to_le32(desc->txdw5);
desc->txdw6 = cpu_to_le32(desc->txdw6);
desc->txdw7 = cpu_to_le32(desc->txdw7);
#ifdef CONFIG_PCI_HCI
desc->txdw8 = cpu_to_le32(desc->txdw8);
desc->txdw9 = cpu_to_le32(desc->txdw9);
desc->txdw10 = cpu_to_le32(desc->txdw10);
desc->txdw11 = cpu_to_le32(desc->txdw11);
desc->txdw12 = cpu_to_le32(desc->txdw12);
desc->txdw13 = cpu_to_le32(desc->txdw13);
desc->txdw14 = cpu_to_le32(desc->txdw14);
desc->txdw15 = cpu_to_le32(desc->txdw15);
#endif
cal_txdesc_chksum(desc);

29
os_dep/os_intfs.c
View file

@ -30,14 +30,8 @@
#include <rtw_ioctl.h>
#include <rtw_version.h>
#include <rtw_br_ext.h>
#ifdef CONFIG_USB_HCI
#include <usb_hal.h>
#include <usb_osintf.h>
#endif
#ifdef CONFIG_PCI_HCI
#include <pci_osintf.h>
#endif
#ifdef CONFIG_BR_EXT
#include <rtw_br_ext.h>
@ -163,11 +157,7 @@ static int rtw_hwpwrp_detect = 1;
static int rtw_hwpwrp_detect = 0; //HW power ping detect 0:disable , 1:enable
#endif
#ifdef CONFIG_USB_HCI
static int rtw_hw_wps_pbc = 1;
#else
static int rtw_hw_wps_pbc = 0;
#endif
#ifdef CONFIG_TX_MCAST2UNI
int rtw_mc2u_disable = 0;
@ -713,15 +703,9 @@ u32 rtw_start_drv_threads(struct adapter *padapter)
RT_TRACE(_module_os_intfs_c_,_drv_info_,("+rtw_start_drv_threads\n"));
#ifdef CONFIG_XMIT_THREAD_MODE
#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_CONCURRENT_MODE)
if(padapter->adapter_type == PRIMARY_ADAPTER){
#endif
padapter->xmitThread = kthread_run(rtw_xmit_thread, padapter, "RTW_XMIT_THREAD");
if(IS_ERR(padapter->xmitThread))
_status = _FAIL;
#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_CONCURRENT_MODE)
}
#endif // CONFIG_SDIO_HCI+CONFIG_CONCURRENT_MODE
#endif
#ifdef CONFIG_RECV_THREAD_MODE
@ -805,10 +789,6 @@ void rtw_stop_drv_threads (struct adapter *padapter)
#ifdef CONFIG_XMIT_THREAD_MODE
// Below is to termindate tx_thread...
#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_CONCURRENT_MODE)
// Only wake-up primary adapter
if(padapter->adapter_type == PRIMARY_ADAPTER)
#endif //SDIO_HCI + CONCURRENT
{
_rtw_up_sema(&padapter->xmitpriv.xmit_sema);
_rtw_down_sema(&padapter->xmitpriv.terminate_xmitthread_sema);
@ -1344,13 +1324,6 @@ static const struct net_device_ops rtw_netdev_if2_ops = {
};
#endif
#ifdef CONFIG_USB_HCI
#include <usb_hal.h>
#endif
#ifdef CONFIG_SDIO_HCI
#include <sdio_hal.h>
#endif
struct adapter *rtw_drv_if2_init(struct adapter *primary_padapter, void (*set_intf_ops)(struct _io_ops *pops))
{
int res = _FAIL;

5
os_dep/osdep_service.c
View file

@ -196,7 +196,6 @@ void _rtw_skb_queue_purge(struct sk_buff_head *list)
_rtw_skb_free(skb);
}
#ifdef CONFIG_USB_HCI
inline void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35))
@ -214,8 +213,6 @@ inline void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr
usb_buffer_free(dev, size, addr, dma);
#endif
}
#endif /* CONFIG_USB_HCI */
#ifdef DBG_MEM_ALLOC
struct rtw_mem_stat {
@ -567,7 +564,6 @@ inline void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flag
dbg_rtw_skb_free(skb, flags, func, line);
}
#ifdef CONFIG_USB_HCI
inline void *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, int line)
{
void *p;
@ -596,7 +592,6 @@ inline void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *a
, size
);
}
#endif /* CONFIG_USB_HCI */
#endif /* DBG_MEM_ALLOC */
void* rtw_malloc2d(int h, int w, int size)

24
os_dep/recv_linux.c
View file

@ -28,10 +28,7 @@
#include <osdep_intf.h>
#include <ethernet.h>
#ifdef CONFIG_USB_HCI
#include <usb_ops.h>
#endif
//init os related resource in struct recv_priv
int rtw_os_recv_resource_init(struct recv_priv *precvpriv, struct adapter *padapter)
@ -77,7 +74,6 @@ int rtw_os_recvbuf_resource_alloc(struct adapter *padapter, struct recv_buf *pre
{
int res=_SUCCESS;
#ifdef CONFIG_USB_HCI
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
struct usb_device *pusbd = pdvobjpriv->pusbdev;
@ -105,9 +101,6 @@ int rtw_os_recvbuf_resource_alloc(struct adapter *padapter, struct recv_buf *pre
if(precvbuf->pallocated_buf == NULL)
return _FAIL;
#endif //CONFIG_USE_USB_BUFFER_ALLOC_RX
#endif //CONFIG_USB_HCI
return res;
}
@ -116,8 +109,6 @@ int rtw_os_recvbuf_resource_free(struct adapter *padapter, struct recv_buf *prec
{
int ret = _SUCCESS;
#ifdef CONFIG_USB_HCI
#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
@ -134,10 +125,6 @@ int rtw_os_recvbuf_resource_free(struct adapter *padapter, struct recv_buf *prec
//usb_kill_urb(precvbuf->purb);
usb_free_urb(precvbuf->purb);
}
#endif //CONFIG_USB_HCI
if(precvbuf->pskb)
rtw_skb_free(precvbuf->pskb);
@ -478,8 +465,6 @@ void rtw_os_read_port(struct adapter *padapter, struct recv_buf *precvbuf)
{
struct recv_priv *precvpriv = &padapter->recvpriv;
#ifdef CONFIG_USB_HCI
precvbuf->ref_cnt--;
//free skb in recv_buf
@ -492,15 +477,8 @@ void rtw_os_read_port(struct adapter *padapter, struct recv_buf *precvbuf)
{
rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
}
#endif
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
precvbuf->pskb = NULL;
#endif
}
void _rtw_reordering_ctrl_timeout_handler (void *FunctionContext);
void _rtw_reordering_ctrl_timeout_handler (void *FunctionContext)
{
struct recv_reorder_ctrl *preorder_ctrl = (struct recv_reorder_ctrl *)FunctionContext;

5
os_dep/usb_intf.c
View file

@ -26,11 +26,6 @@
#include <xmit_osdep.h>
#include <hal_intf.h>
#include <rtw_version.h>
#ifndef CONFIG_USB_HCI
#error "CONFIG_USB_HCI shall be on!\n"
#endif
#include <usb_vendor_req.h>
#include <usb_ops.h>

51
os_dep/usb_ops_linux.c
View file

@ -522,46 +522,35 @@ _func_enter_;
int bmcast = IS_MCAST(pattrib->dst);
u8 agg_num = 1;
#ifdef CONFIG_USB_HCI
#ifdef CONFIG_USB_TX_AGGREGATION
if(pxmitframe->agg_num>1)
agg_num = pxmitframe->agg_num;
#endif
#endif
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
if(pxmitframe->agg_num>1)
agg_num = pxmitframe->agg_num;
#endif
if(bmcast)
{
psta = rtw_get_bcmc_stainfo(padapter);
} else {
else
psta = rtw_get_stainfo(pstapriv, pattrib->dst);
}
if(psta)
{
switch(pattrib->priority)
{
case 1:
case 2:
psta->tx_bk_cnt += agg_num;
break;
case 4:
case 5:
psta->tx_vi_cnt += agg_num;
break;
case 6:
case 7:
psta->tx_vo_cnt += agg_num;
break;
case 0:
case 3:
default:
psta->tx_be_cnt += agg_num;
break;
if(psta) {
switch(pattrib->priority) {
case 1:
case 2:
psta->tx_bk_cnt += agg_num;
break;
case 4:
case 5:
psta->tx_vi_cnt += agg_num;
break;
case 6:
case 7:
psta->tx_vo_cnt += agg_num;
break;
case 0:
case 3:
default:
psta->tx_be_cnt += agg_num;
break;
}
}
}

34
os_dep/xmit_linux.c
View file

@ -125,7 +125,6 @@ void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib)
int rtw_os_xmit_resource_alloc(struct adapter *padapter, struct xmit_buf *pxmitbuf,u32 alloc_sz)
{
#ifdef CONFIG_USB_HCI
int i;
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
struct usb_device *pusbd = pdvobjpriv->pusbdev;
@ -158,23 +157,11 @@ int rtw_os_xmit_resource_alloc(struct adapter *padapter, struct xmit_buf *pxmitb
}
}
#endif
#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
pxmitbuf->pallocated_buf = rtw_zmalloc(alloc_sz);
if (pxmitbuf->pallocated_buf == NULL)
{
return _FAIL;
}
pxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), XMITBUF_ALIGN_SZ);
#endif
return _SUCCESS;
}
void rtw_os_xmit_resource_free(struct adapter *padapter, struct xmit_buf *pxmitbuf,u32 free_sz)
{
#ifdef CONFIG_USB_HCI
int i;
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
struct usb_device *pusbd = pdvobjpriv->pusbdev;
@ -197,12 +184,6 @@ void rtw_os_xmit_resource_free(struct adapter *padapter, struct xmit_buf *pxmitb
if(pxmitbuf->pallocated_buf)
rtw_mfree(pxmitbuf->pallocated_buf, free_sz);
#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX
#endif
#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
if(pxmitbuf->pallocated_buf)
rtw_mfree(pxmitbuf->pallocated_buf, free_sz);
#endif
}
#define WMM_XMIT_THRESHOLD (NR_XMITFRAME*2/5)
@ -244,20 +225,6 @@ void rtw_os_xmit_schedule(struct adapter *padapter)
{
struct adapter *pri_adapter = padapter;
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
if(!padapter)
return;
#ifdef CONFIG_CONCURRENT_MODE
if(padapter->adapter_type > PRIMARY_ADAPTER)
pri_adapter = padapter->pbuddy_adapter;
#endif
if (_rtw_queue_empty(&pri_adapter->xmitpriv.pending_xmitbuf_queue) == _FALSE)
_rtw_up_sema(&pri_adapter->xmitpriv.xmit_sema);
#else
_irqL irqL;
struct xmit_priv *pxmitpriv;
@ -274,7 +241,6 @@ void rtw_os_xmit_schedule(struct adapter *padapter)
}
_exit_critical_bh(&pxmitpriv->lock, &irqL);
#endif
}
static void rtw_check_xmit_resource(struct adapter *padapter, _pkt *pkt)