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rtl8188eu: Fix most sparse warnings other than endedness problems

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2013-06-03 14:52:18 -05:00
parent 925510ff1a
commit 327817d32a
47 changed files with 667 additions and 1771 deletions
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6
hal/HalHWImg8188E_BB.c
View file

@ -60,7 +60,7 @@ CheckCondition(
* AGC_TAB_1T.TXT
******************************************************************************/
u4Byte Array_AGC_TAB_1T_8188E[] = {
static u4Byte Array_AGC_TAB_1T_8188E[] = {
0xC78, 0xFB000001,
0xC78, 0xFB010001,
0xC78, 0xFB020001,
@ -327,7 +327,7 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E(
* PHY_REG_1T.TXT
******************************************************************************/
u4Byte Array_PHY_REG_1T_8188E[] = {
static u4Byte Array_PHY_REG_1T_8188E[] = {
0x800, 0x80040000,
0x804, 0x00000003,
0x808, 0x0000FC00,
@ -737,7 +737,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
* PHY_REG_PG.TXT
******************************************************************************/
u4Byte Array_PHY_REG_PG_8188E[] = {
static u4Byte Array_PHY_REG_PG_8188E[] = {
0xE00, 0xFFFFFFFF, 0x06070809,
0xE04, 0xFFFFFFFF, 0x02020405,
0xE08, 0x0000FF00, 0x00000006,

2
hal/HalHWImg8188E_MAC.c
View file

@ -58,7 +58,7 @@ CheckCondition(
* MAC_REG.TXT
******************************************************************************/
u4Byte Array_MAC_REG_8188E[] = {
static u4Byte Array_MAC_REG_8188E[] = {
0x026, 0x00000041,
0x027, 0x00000035,
0x428, 0x0000000A,

2
hal/HalHWImg8188E_RF.c
View file

@ -60,7 +60,7 @@ CheckCondition(
* RadioA_1T.TXT
******************************************************************************/
u4Byte Array_RadioA_1T_8188E[] = {
static u4Byte Array_RadioA_1T_8188E[] = {
0x000, 0x00030000,
0x008, 0x00084000,
0x018, 0x00000407,

56
hal/HalPhyRf_8188e.c
View file

@ -130,7 +130,7 @@ ODM_TxPwrTrackAdjust88E(
* 04/23/2012 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
void
static void
odm_TxPwrTrackSetPwr88E(
PDM_ODM_T pDM_Odm
)
@ -627,7 +627,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
#define MAX_TOLERANCE 5
#define IQK_DELAY_TIME 1 //ms
u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
static u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
phy_PathA_IQK_8188E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
PDM_ODM_T pDM_Odm,
@ -691,7 +691,7 @@ phy_PathA_IQK_8188E(
return result;
}
u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
static u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
phy_PathA_RxIQK(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
PDM_ODM_T pDM_Odm,
@ -836,7 +836,7 @@ phy_PathA_RxIQK(
}
u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
static u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
phy_PathB_IQK_8188E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
PDM_ODM_T pDM_Odm
@ -899,7 +899,7 @@ phy_PathB_IQK_8188E(
}
void
static void
_PHY_PathAFillIQKMatrix(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
PDM_ODM_T pDM_Odm,
@ -974,7 +974,7 @@ _PHY_PathAFillIQKMatrix(
}
}
void
static void
_PHY_PathBFillIQKMatrix(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
PDM_ODM_T pDM_Odm,
@ -1046,7 +1046,7 @@ _PHY_PathBFillIQKMatrix(
//
// MP Already declare in odm.c
#if !(DM_ODM_SUPPORT_TYPE & ODM_MP)
bool
static bool
ODM_CheckPowerStatus(
PADAPTER Adapter)
{
@ -1111,8 +1111,7 @@ _PHY_SaveADDARegisters(
}
void
_PHY_SaveMACRegisters(
static void _PHY_SaveMACRegisters(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
PDM_ODM_T pDM_Odm,
#else
@ -1141,7 +1140,7 @@ _PHY_SaveMACRegisters(
}
void
static void
_PHY_ReloadADDARegisters(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
PDM_ODM_T pDM_Odm,
@ -1171,7 +1170,7 @@ _PHY_ReloadADDARegisters(
}
}
void
static void
_PHY_ReloadMACRegisters(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
PDM_ODM_T pDM_Odm,
@ -1297,8 +1296,7 @@ _PHY_PathAStandBy(
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
}
void
_PHY_PIModeSwitch(
static void _PHY_PIModeSwitch(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
PDM_ODM_T pDM_Odm,
#else
@ -1324,8 +1322,7 @@ _PHY_PIModeSwitch(
ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode);
}
bool
phy_SimularityCompare_8188E(
static bool phy_SimularityCompare_8188E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
PDM_ODM_T pDM_Odm,
#else
@ -1457,10 +1454,7 @@ phy_SimularityCompare_8188E(
}
void
phy_IQCalibrate_8188E(
static void phy_IQCalibrate_8188E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
PDM_ODM_T pDM_Odm,
#else
@ -1519,8 +1513,6 @@ else
// Note: IQ calibration must be performed after loading
// PHY_REG.txt , and radio_a, radio_b.txt
//u4Byte bbvalue;
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#ifdef MP_TEST
if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific)
@ -1529,12 +1521,8 @@ else
#endif
if (t==0)
{
// bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord);
// RTPRINT(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));
if (t==0) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));
// Save ADDA parameters, turn Path A ADDA on
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
@ -1550,17 +1538,12 @@ else
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
_PHY_PathADDAOn(pAdapter, ADDA_REG, true, is2T);
#else
_PHY_PathADDAOn(pDM_Odm, ADDA_REG, true, is2T);
#endif
if (t==0)
{
pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8));
}
if (!pDM_Odm->RFCalibrateInfo.bRfPiEnable){
// Switch BB to PI mode to do IQ Calibration.
@ -1739,8 +1722,7 @@ else
}
void
phy_LCCalibrate_8188E(
static void phy_LCCalibrate_8188E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
PDM_ODM_T pDM_Odm,
#else
@ -1830,8 +1812,7 @@ phy_LCCalibrate_8188E(
#define APK_CURVE_REG_NUM 4
#define PATH_NUM 2
void
phy_APCalibrate_8188E(
static void phy_APCalibrate_8188E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
PDM_ODM_T pDM_Odm,
#else
@ -2729,7 +2710,8 @@ PHY_APCalibrate_8188E(
#endif
}
}
void phy_SetRFPathSwitch_8188E(
static void phy_SetRFPathSwitch_8188E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
PDM_ODM_T pDM_Odm,
#else

247
hal/odm.c
View file

@ -24,17 +24,16 @@
#include "odm_precomp.h"
const u2Byte dB_Invert_Table[8][12] = {
{ 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4},
{ 4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16},
{ 18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63},
{ 71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251},
{ 282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000},
{ 1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
{ 4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849},
{ 17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535}};
static const u2Byte dB_Invert_Table[8][12] = {
{1,1,1, 2, 2, 2, 2, 3, 3, 3, 4, 4},
{4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16},
{18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63},
{71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251},
{282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000},
{1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
{4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849},
{17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535}
};
// 20100515 Joseph: Add global variable to keep temporary scan list for antenna switching test.
//u1Byte tmpNumBssDesc;
@ -43,16 +42,16 @@ const u2Byte dB_Invert_Table[8][12] = {
#if (DM_ODM_SUPPORT_TYPE==ODM_MP)
static u4Byte edca_setting_UL[HT_IOT_PEER_MAX] =
// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MARVELL 92U_AP SELF_AP(DownLink/Tx)
{ 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea44f, 0x5e4322, 0x5e4322};
{ 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea44f, 0x5e4322, 0x5e4322};
static u4Byte edca_setting_DL[HT_IOT_PEER_MAX] =
// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MARVELL 92U_AP SELF_AP(UpLink/Rx)
{ 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0xa44f, 0xa42b, 0xa42b};
{ 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0xa44f, 0xa42b, 0xa42b};
static u4Byte edca_setting_DL_GMode[HT_IOT_PEER_MAX] =
// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MARVELL 92U_AP SELF_AP
{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0xa44f, 0x5e4322, 0x5ea42b};
{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0xa44f, 0x5e4322, 0x5ea42b};
//============================================================
@ -60,7 +59,7 @@ static u4Byte edca_setting_DL_GMode[HT_IOT_PEER_MAX] =
//avoid to warn in FreeBSD ==> To DO modify
u4Byte EDCAParam[HT_IOT_PEER_MAX][3] =
static u4Byte EDCAParam[HT_IOT_PEER_MAX][3] =
{ // UL DL
{0x5ea42b, 0x5ea42b, 0x5ea42b}, //0:unknown AP
{0xa44f, 0x5ea44f, 0x5e431c}, // 1:realtek AP
@ -68,15 +67,12 @@ u4Byte EDCAParam[HT_IOT_PEER_MAX][3] =
{0x5ea32b, 0x5ea42b, 0x5e4322}, // 3:broadcom AP
{0x5ea422, 0x00a44f, 0x00a44f}, // 4:ralink AP
{0x5ea322, 0x00a630, 0x00a44f}, // 5:atheros AP
//{0x5ea42b, 0x5ea42b, 0x5ea42b},// 6:cisco AP
{0x5e4322, 0x5e4322, 0x5e4322},// 6:cisco AP
//{0x3ea430, 0x00a630, 0x3ea44f}, // 7:cisco AP
{0x5ea44f, 0x00a44f, 0x5ea42b}, // 8:marvell AP
//{0x5ea44f, 0x5ea44f, 0x5ea44f}, // 9realtek AP
{0x5ea42b, 0x5ea42b, 0x5ea42b}, // 10:unknown AP=> 92U AP
{0x5ea42b, 0xa630, 0x5e431c}, // 11:airgocap AP
// {0x5e4322, 0x00a44f, 0x5ea44f}, // 12:unknown AP
};
//============================================================
// EDCA Paramter for AP/ADSL by Mingzhi 2011-11-22
//============================================================
@ -157,75 +153,75 @@ u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D] = {
u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = {
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0dB
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 1, -0.5dB
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 2, -1.0dB
{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 3, -1.5dB
{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 4, -2.0dB
{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 5, -2.5dB
{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 6, -3.0dB
{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 7, -3.5dB
{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 8, -4.0dB
{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 9, -4.5dB
{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 10, -5.0dB
{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 11, -5.5dB
{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 12, -6.0dB
{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 13, -6.5dB
{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 14, -7.0dB
{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 15, -7.5dB
{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB
{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 17, -8.5dB
{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 18, -9.0dB
{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 19, -9.5dB
{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 20, -10.0dB
{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 21, -10.5dB
{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 22, -11.0dB
{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 23, -11.5dB
{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 24, -12.0dB
{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 25, -12.5dB
{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 26, -13.0dB
{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 27, -13.5dB
{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 28, -14.0dB
{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 29, -14.5dB
{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 30, -15.0dB
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 31, -15.5dB
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0dB
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 1, -0.5dB
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 2, -1.0dB
{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 3, -1.5dB
{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 4, -2.0dB
{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 5, -2.5dB
{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 6, -3.0dB
{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 7, -3.5dB
{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 8, -4.0dB
{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 9, -4.5dB
{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 10, -5.0dB
{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 11, -5.5dB
{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 12, -6.0dB
{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 13, -6.5dB
{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 14, -7.0dB
{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 15, -7.5dB
{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB
{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 17, -8.5dB
{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 18, -9.0dB
{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 19, -9.5dB
{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 20, -10.0dB
{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 21, -10.5dB
{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 22, -11.0dB
{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 23, -11.5dB
{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 24, -12.0dB
{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 25, -12.5dB
{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 26, -13.0dB
{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 27, -13.5dB
{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 28, -14.0dB
{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 29, -14.5dB
{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 30, -15.0dB
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 31, -15.5dB
{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} // 32, -16.0dB
};
u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]= {
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0dB
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 1, -0.5dB
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 2, -1.0dB
{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 3, -1.5dB
{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 4, -2.0dB
{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 5, -2.5dB
{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 6, -3.0dB
{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 7, -3.5dB
{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 8, -4.0dB
{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 9, -4.5dB
{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 10, -5.0dB
{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 11, -5.5dB
{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 12, -6.0dB
{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 13, -6.5dB
{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 14, -7.0dB
{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 15, -7.5dB
{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB
{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 17, -8.5dB
{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 18, -9.0dB
{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 19, -9.5dB
{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 20, -10.0dB
{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 21, -10.5dB
{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 22, -11.0dB
{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 23, -11.5dB
{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 24, -12.0dB
{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 25, -12.5dB
{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 26, -13.0dB
{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 27, -13.5dB
{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 28, -14.0dB
{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 29, -14.5dB
{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 30, -15.0dB
{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 31, -15.5dB
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0dB
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 1, -0.5dB
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 2, -1.0dB
{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 3, -1.5dB
{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 4, -2.0dB
{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 5, -2.5dB
{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 6, -3.0dB
{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 7, -3.5dB
{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 8, -4.0dB
{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 9, -4.5dB
{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 10, -5.0dB
{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 11, -5.5dB
{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 12, -6.0dB
{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 13, -6.5dB
{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 14, -7.0dB
{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 15, -7.5dB
{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB
{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 17, -8.5dB
{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 18, -9.0dB
{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 19, -9.5dB
{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 20, -10.0dB
{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 21, -10.5dB
{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 22, -11.0dB
{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 23, -11.5dB
{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 24, -12.0dB
{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 25, -12.5dB
{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 26, -13.0dB
{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 27, -13.5dB
{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 28, -14.0dB
{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 29, -14.5dB
{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 30, -15.0dB
{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 31, -15.5dB
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} // 32, -16.0dB
};
@ -385,7 +381,7 @@ odm_PathDivChkAntSwitchWorkitemCallback(
void * pContext
);
void odm_SetRespPath_92C( PADAPTER Adapter, u1Byte DefaultRespPath);
void odm_SetRespPath_92C( PADAPTER Adapter, u1Byte DefaultRespPath);
void odm_OFDMTXPathDiversity_92C( PADAPTER Adapter);
void odm_CCKTXPathDiversity_92C( PADAPTER Adapter);
void odm_ResetPathDiversity_92C( PADAPTER Adapter);
@ -1473,8 +1469,7 @@ odm_IsLinked(
* When Who Remark
*
*---------------------------------------------------------------------------*/
void
ODM_ChangeDynamicInitGainThresh(
static void ODM_ChangeDynamicInitGainThresh(
PDM_ODM_T pDM_Odm,
u4Byte DM_Type,
u4Byte DM_Value
@ -1518,7 +1513,7 @@ ODM_ChangeDynamicInitGainThresh(
}
} /* DM_ChangeDynamicInitGainThresh */
int getIGIForDiff(int value_IGI)
static int getIGIForDiff(int value_IGI)
{
#define ONERCCA_LOW_TH 0x30
#define ONERCCA_LOW_DIFF 8
@ -2112,7 +2107,7 @@ odm_DIG(
if (FirstConnect)
{
CurrentIGI = pDM_Odm->RSSI_Min;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n"));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n"));
}
else
{
@ -2423,9 +2418,9 @@ odm_FalseAlarmCounterStatistics(
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 0);
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 1);
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n", FalseAlmCnt->Cnt_all));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n", FalseAlmCnt->Cnt_all));
}
//3============================================================
@ -2611,7 +2606,7 @@ odm_1R_CCA(
}
pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState;
}
//ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, ("CCAStage = %s\n",(pDM_PSTable->CurCCAState==0)?"1RCCA":"2RCCA"));
//ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, ("CCAStage = %s\n",(pDM_PSTable->CurCCAState==0)?"1RCCA":"2RCCA"));
}
void
@ -2684,7 +2679,7 @@ ODM_RF_Saving(
ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); //RegA75[7:4]=0x3
ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); //Reg818[28]=1'b0
ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); //Reg818[28]=1'b1
//ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, (" RF_Save"));
//ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, (" RF_Save"));
}
else
{
@ -2698,7 +2693,7 @@ ODM_RF_Saving(
{
ODM_SetBBReg(pDM_Odm,0x874 , BIT5, 0x0); //Reg874[5]=1b'0
}
//ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, (" RF_Normal"));
//ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, (" RF_Normal"));
}
pDM_PSTable->PreRFState =pDM_PSTable->CurRFState;
}
@ -4749,7 +4744,7 @@ odm_SwAntDivInit_NIC(
// 20100514 Joseph:
// Add new function to reset the state of antenna diversity before link.
//
void
static void
ODM_SwAntDivResetBeforeLink(
PDM_ODM_T pDM_Odm
)
@ -5473,7 +5468,10 @@ void odm_SwAntDivChkAntSwitch(
PDM_ODM_T pDM_Odm,
u1Byte Step
) {}
void ODM_SwAntDivResetBeforeLink( PDM_ODM_T pDM_Odm ){}
static void ODM_SwAntDivResetBeforeLink(PDM_ODM_T pDM_Odm)
{
}
void ODM_SwAntDivRestAfterLink( PDM_ODM_T pDM_Odm ){}
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
u1Byte odm_SwAntDivSelectChkChnl( PADAPTER Adapter ){ return 0;}
@ -5720,8 +5718,7 @@ ODM_SwAntDivCheckBeforeLink8192C(
//3============================================================
#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
void
odm_InitHybridAntDiv_88C_92D(
static void odm_InitHybridAntDiv_88C_92D(
PDM_ODM_T pDM_Odm
)
{
@ -5964,8 +5961,7 @@ ODM_AntselStatistics_88C(
#if (DM_ODM_SUPPORT_TYPE==ODM_MP)
void
ODM_SetTxAntByTxInfo_88C_92D(
static void ODM_SetTxAntByTxInfo_88C_92D(
PDM_ODM_T pDM_Odm,
pu1Byte pDesc,
u1Byte macId
@ -5987,7 +5983,7 @@ ODM_SetTxAntByTxInfo_88C_92D(
//ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("SET_TX_DESC_ANTSEL_A_92C=%d\n", pDM_SWAT_Table->TxAnt[macId]));
}
#elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
void
static void
ODM_SetTxAntByTxInfo_88C_92D(
PDM_ODM_T pDM_Odm
)
@ -6004,10 +6000,7 @@ ODM_SetTxAntByTxInfo_88C_92D(
}
#endif
void
odm_HwAntDiv_92C_92D(
PDM_ODM_T pDM_Odm
)
static void odm_HwAntDiv_92C_92D(PDM_ODM_T pDM_Odm)
{
SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
u4Byte RSSI_Min=0xFF, RSSI, RSSI_Ant1, RSSI_Ant2;
@ -8251,7 +8244,7 @@ odm_PSD_Monitor(
//2???
Is40MHz = pMgntInfo->pHTInfo->bCurBW40MHz;
ODM_RT_TRACE(pDM_Odm, COMP_PSD, DBG_LOUD,("PSD Scan Start\n"));
ODM_RT_TRACE(pDM_Odm, COMP_PSD, DBG_LOUD,("PSD Scan Start\n"));
//1 Turn off CCK
ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0);
//1 Turn off TX
@ -8862,7 +8855,7 @@ void odm_RXHP(
else
pRX_HP_Table->TP_Mode = High_TP_Mode;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP TP Mode = %d\n", pRX_HP_Table->TP_Mode));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP TP Mode = %d\n", pRX_HP_Table->TP_Mode));
// Since TP result would be sampled every 2 sec, it needs to delay 4sec to wait PSD processing.
// When LatchCnt = 0, we would Get PSD result.
if (TP_Degrade_flag == 1)
@ -8894,11 +8887,11 @@ void odm_RXHP(
Is40MHz = *(pDM_Odm->pBandWidth);
curRssi = pDM_Odm->RSSI_Min;
cur_channel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x0fff) & 0x0f;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP RX HP flag = %d\n", pRX_HP_Table->RXHP_flag));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP FA = %d\n", FalseAlmCnt->Cnt_all));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP cur RSSI = %d, pre RSSI=%d\n", curRssi, preRssi));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP current CH = %d\n", cur_channel));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP Is 40MHz = %d\n", Is40MHz));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP RX HP flag = %d\n", pRX_HP_Table->RXHP_flag));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP FA = %d\n", FalseAlmCnt->Cnt_all));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP cur RSSI = %d, pre RSSI=%d\n", curRssi, preRssi));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP current CH = %d\n", cur_channel));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP Is 40MHz = %d\n", Is40MHz));
//2 PSD function would be triggered
//3 1. Every 4 sec for PCIE
//3 2. Before TP Mode (Idle TP<4kbps) for USB
@ -9026,7 +9019,7 @@ void odm_RXHP(
}
}
#endif
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP psd_intf_flag = %d\n", psd_intf_flag));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP psd_intf_flag = %d\n", psd_intf_flag));
//2 Distance between target channel and interference
for (i = 0; i < 16; i++)
{
@ -9037,7 +9030,7 @@ void odm_RXHP(
MIN_Intf_diff_idx = Intf_diff_idx; // the min difference index between interference and target
}
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP MIN_Intf_diff_idx = %d\n", MIN_Intf_diff_idx));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP MIN_Intf_diff_idx = %d\n", MIN_Intf_diff_idx));
//2 Choose False Alarm Threshold
switch (MIN_Intf_diff_idx){
case 0:
@ -9067,7 +9060,7 @@ void odm_RXHP(
FA_TH = FA_RXHP_TH5;
break;
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP FA_TH = %d\n", FA_TH));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP FA_TH = %d\n", FA_TH));
pRX_HP_Table->PSD_func_trigger = 0;
}
//1 Monitor RSSI variation to choose the suitable IGI or Exit AGC RX High Power Mode
@ -9244,7 +9237,7 @@ odm_PSD_RXHP(
RXIQI = ODM_GetBBReg(pDM_Odm, 0xC14, bMaskDWord);
RxIdleLowPwr = (ODM_GetBBReg(pDM_Odm, 0x818, bMaskDWord)&BIT28)>>28;
Is40MHz = *(pDM_Odm->pBandWidth);
ODM_RT_TRACE(pDM_Odm, COMP_PSD, DBG_LOUD,("PSD Scan Start\n"));
ODM_RT_TRACE(pDM_Odm, COMP_PSD, DBG_LOUD,("PSD Scan Start\n"));
//1 Turn off CCK
ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0);
//1 Turn off TX
@ -10944,10 +10937,7 @@ ODM_SingleDualAntennaDefaultSetting(
//2 8723A ANT DETECT
void
odm_PHY_SaveAFERegisters(
PDM_ODM_T pDM_Odm,
static void odm_PHY_SaveAFERegisters(PDM_ODM_T pDM_Odm,
pu4Byte AFEReg,
pu4Byte AFEBackup,
u4Byte RegisterNum
@ -10961,8 +10951,7 @@ odm_PHY_SaveAFERegisters(
}
}
void
odm_PHY_ReloadAFERegisters(
static void odm_PHY_ReloadAFERegisters(
PDM_ODM_T pDM_Odm,
pu4Byte AFEReg,
pu4Byte AFEBackup,
@ -11006,13 +10995,13 @@ ODM_SingleDualAntennaDetection(
bool bResult = true;
u4Byte AFE_Backup[16];
u4Byte AFE_REG_8723A[16] = {
rRx_Wait_CCA, rTx_CCK_RFON,
rTx_CCK_BBON, rTx_OFDM_RFON,
rTx_OFDM_BBON, rTx_To_Rx,
rTx_To_Tx, rRx_CCK,
rRx_OFDM, rRx_Wait_RIFS,
rRx_TO_Rx, rStandby,
rSleep, rPMPD_ANAEN,
rRx_Wait_CCA, rTx_CCK_RFON,
rTx_CCK_BBON, rTx_OFDM_RFON,
rTx_OFDM_BBON, rTx_To_Rx,
rTx_To_Tx, rRx_CCK,
rRx_OFDM, rRx_Wait_RIFS,
rRx_TO_Rx, rStandby,
rSleep, rPMPD_ANAEN,
rFPGA0_XCD_SwitchControl, rBlue_Tooth};
if (!(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C)))

48
hal/odm_HWConfig.c
View file

@ -40,24 +40,14 @@
#define READ_AND_CONFIG_MP(ic, txt) (ODM_ReadAndConfig##txt##ic(pDM_Odm))
#define READ_AND_CONFIG_TC(ic, txt) (ODM_ReadAndConfig_TC##txt##ic(pDM_Odm))
u1Byte
odm_QueryRxPwrPercentage(
s1Byte AntPower
)
static u1Byte odm_QueryRxPwrPercentage(s1Byte AntPower)
{
if ((AntPower <= -100) || (AntPower >= 20))
{
return 0;
}
else if (AntPower >= 0)
{
return 100;
}
else
{
return (100+AntPower);
}
}
#if (DM_ODM_SUPPORT_TYPE != ODM_MP)
@ -65,8 +55,7 @@ odm_QueryRxPwrPercentage(
// 2012/01/12 MH MOve some signal strength smooth method to MP HAL layer.
// IF other SW team do not support the feature, remove this section.??
//
s4Byte
odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo(
static s4Byte odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo(
PDM_ODM_T pDM_Odm,
s4Byte CurrSig
)
@ -81,48 +70,29 @@ odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo(
// This modification makes the RSSI indication similar to Intel solution.
// 20100414 Joseph: Tunning RSSI for Lenovo according to RTL8191SE.
if (CurrSig >= 54 && CurrSig <= 100)
{
RetSig = 100;
}
else if (CurrSig>=42 && CurrSig <= 53)
{
RetSig = 95;
}
else if (CurrSig>=36 && CurrSig <= 41)
{
RetSig = 74 + ((CurrSig - 36) *20)/6;
}
else if (CurrSig>=33 && CurrSig <= 35)
{
RetSig = 65 + ((CurrSig - 33) *8)/2;
}
else if (CurrSig>=18 && CurrSig <= 32)
{
RetSig = 62 + ((CurrSig - 18) *2)/15;
}
else if (CurrSig>=15 && CurrSig <= 17)
{
RetSig = 33 + ((CurrSig - 15) *28)/2;
}
else if (CurrSig>=10 && CurrSig <= 14)
{
RetSig = 39;
}
else if (CurrSig>=8 && CurrSig <= 9)
{
RetSig = 33;
}
else if (CurrSig <= 8)
{
RetSig = 19;
}
}
#endif //ENDIF (DM_ODM_SUPPORT_TYPE == ODM_MP)
return RetSig;
}
s4Byte
odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore(
static s4Byte odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore(
PDM_ODM_T pDM_Odm,
s4Byte CurrSig
)
@ -182,7 +152,7 @@ odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore(
}
s4Byte
static s4Byte
odm_SignalScaleMapping_92CSeries(
PDM_ODM_T pDM_Odm,
s4Byte CurrSig
@ -275,7 +245,7 @@ odm_SignalScaleMapping_92CSeries(
#endif
return RetSig;
}
s4Byte
static s4Byte
odm_SignalScaleMapping(
PDM_ODM_T pDM_Odm,
s4Byte CurrSig
@ -377,7 +347,7 @@ odm_EVMdbToPercentage(
void
static void
odm_RxPhyStatus92CSeries_Parsing(
PDM_ODM_T pDM_Odm,
PODM_PHY_INFO_T pPhyInfo,
@ -746,7 +716,7 @@ odm_Init_RSSIForDM(
}
void
static void
odm_Process_RSSIForDM(
PDM_ODM_T pDM_Odm,
PODM_PHY_INFO_T pPhyInfo,
@ -968,7 +938,7 @@ odm_Process_RSSIForDM(
//
// Endianness before calling this API
//
void
static void
ODM_PhyStatusQuery_92CSeries(
PDM_ODM_T pDM_Odm,
PODM_PHY_INFO_T pPhyInfo,
@ -998,7 +968,7 @@ ODM_PhyStatusQuery_92CSeries(
//
// Endianness before calling this API
//
void
static void
ODM_PhyStatusQuery_JaguarSeries(
PDM_ODM_T pDM_Odm,
PODM_PHY_INFO_T pPhyInfo,

4
hal/odm_interface.c
View file

@ -229,7 +229,7 @@ ODM_SetRFReg(
PHY_SetRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, Data);
#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP))
PADAPTER Adapter = pDM_Odm->Adapter;
PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data);
PHY_SetRFReg(Adapter, (enum _RF_RADIO_PATH)eRFPath, RegAddr, BitMask, Data);
#endif
}
@ -246,7 +246,7 @@ ODM_GetRFReg(
return PHY_QueryRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, 1);
#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP))
PADAPTER Adapter = pDM_Odm->Adapter;
return PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask);
return PHY_QueryRFReg(Adapter, (enum _RF_RADIO_PATH)eRFPath, RegAddr, BitMask);
#endif
}

47
hal/rtl8188e_cmd.c
View file

@ -179,38 +179,6 @@ _func_exit_;
return ret;
}
u8 rtl8192c_h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf)
{
u8 ElementID, CmdLen;
u8 *pCmdBuffer;
struct cmd_msg_parm *pcmdmsg;
if (!pbuf)
return H2C_PARAMETERS_ERROR;
pcmdmsg = (struct cmd_msg_parm*)pbuf;
ElementID = pcmdmsg->eid;
CmdLen = pcmdmsg->sz;
pCmdBuffer = pcmdmsg->buf;
FillH2CCmd_88E(padapter, ElementID, CmdLen, pCmdBuffer);
return H2C_SUCCESS;
}
/*
#if defined(CONFIG_AUTOSUSPEND) && defined(SUPPORT_HW_RFOFF_DETECTED)
u8 rtl8192c_set_FwSelectSuspend_cmd(_adapter *padapter ,u8 bfwpoll, u16 period)
{
u8 res=_SUCCESS;
struct H2C_SS_RFOFF_PARAM param;
DBG_88E("==>%s bfwpoll(%x)\n",__func__,bfwpoll);
param.gpio_period = period;//Polling GPIO_11 period time
param.ROFOn = (true == bfwpoll)?1:0;
FillH2CCmd_88E(padapter, SELECTIVE_SUSPEND_ROF_CMD, sizeof(param), (u8*)(&param));
return res;
}
#endif //CONFIG_AUTOSUSPEND && SUPPORT_HW_RFOFF_DETECTED
*/
u8 rtl8188e_set_rssi_cmd(_adapter*padapter, u8 *param)
{
u8 res=_SUCCESS;
@ -234,11 +202,14 @@ u8 rtl8188e_set_raid_cmd(_adapter*padapter, u32 mask)
u8 buf[3];
u8 res=_SUCCESS;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
_func_enter_;
if (pHalData->fw_ractrl == true){
__le32 lmask;
_rtw_memset(buf, 0, 3);
mask = cpu_to_le32( mask );
_rtw_memcpy(buf, &mask, 3);
lmask = cpu_to_le32( mask );
_rtw_memcpy(buf, &lmask, 3);
FillH2CCmd_88E(padapter, H2C_DM_MACID_CFG, 3, buf);
}else{
@ -380,7 +351,7 @@ void rtl8188e_set_FwMediaStatus_cmd(PADAPTER padapter, u16 mstatus_rpt )
FillH2CCmd_88E(padapter, H2C_COM_MEDIA_STATUS_RPT, sizeof(mst_rpt), (u8 *)&mst_rpt);
}
void ConstructBeacon(_adapter *padapter, u8 *pframe, u32 *pLength)
static void ConstructBeacon(_adapter *padapter, u8 *pframe, u32 *pLength)
{
struct rtw_ieee80211_hdr *pwlanhdr;
u16 *fctrl;
@ -482,7 +453,7 @@ _ConstructBeacon:
}
void ConstructPSPoll(_adapter *padapter, u8 *pframe, u32 *pLength)
static void ConstructPSPoll(_adapter *padapter, u8 *pframe, u32 *pLength)
{
struct rtw_ieee80211_hdr *pwlanhdr;
u16 *fctrl;
@ -512,7 +483,7 @@ void ConstructPSPoll(_adapter *padapter, u8 *pframe, u32 *pLength)
*pLength = 16;
}
void ConstructNullFunctionData(
static void ConstructNullFunctionData(
PADAPTER padapter,
u8 *pframe,
u32 *pLength,
@ -585,7 +556,7 @@ void ConstructNullFunctionData(
*pLength = pktlen;
}
void ConstructProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength, u8 *StaAddr, bool bHideSSID)
static void ConstructProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength, u8 *StaAddr, bool bHideSSID)
{
struct rtw_ieee80211_hdr *pwlanhdr;
u16 *fctrl;

44
hal/rtl8188e_hal_init.c
View file

@ -217,7 +217,7 @@ exit:
rtw_mfree2d((void *)eFuseWord, EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, sizeof(u16));
}
void efuse_read_phymap_from_txpktbuf(
static void efuse_read_phymap_from_txpktbuf(
ADAPTER *adapter,
int bcnhead, //beacon head, where FW store len(2-byte) and efuse physical map.
u8 *content, //buffer to store efuse physical map
@ -352,7 +352,7 @@ static s32 iol_ioconfig(
return rst;
}
int rtl8188e_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms,u32 bndy_cnt)
static int rtl8188e_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms,u32 bndy_cnt)
{
u32 start_time = rtw_get_current_time();
@ -1358,7 +1358,7 @@ rtl8188e_ReadEFuse(
}
//Do not support BT
void
static void
Hal_EFUSEGetEfuseDefinition88E(
PADAPTER pAdapter,
u1Byte efuseType,
@ -1426,8 +1426,8 @@ Hal_EFUSEGetEfuseDefinition88E(
break;
}
}
void
Hal_EFUSEGetEfuseDefinition_Pseudo88E(
static void Hal_EFUSEGetEfuseDefinition_Pseudo88E(
PADAPTER pAdapter,
u8 efuseType,
u8 type,
@ -2515,7 +2515,7 @@ static void rtl8188e_read_chip_version(PADAPTER padapter)
ReadChipVersion8188E(padapter);
}
void rtl8188e_GetHalODMVar(
static void rtl8188e_GetHalODMVar(
PADAPTER Adapter,
HAL_ODM_VARIABLE eVariable,
void * pValue1,
@ -2530,7 +2530,7 @@ void rtl8188e_GetHalODMVar(
break;
}
}
void rtl8188e_SetHalODMVar(
static void rtl8188e_SetHalODMVar(
PADAPTER Adapter,
HAL_ODM_VARIABLE eVariable,
void * pValue1,
@ -2639,7 +2639,8 @@ void rtl8188e_stop_thread(_adapter *padapter)
#endif
#endif
}
void hal_notch_filter_8188e(_adapter *adapter, bool enable)
static void hal_notch_filter_8188e(_adapter *adapter, bool enable)
{
if (enable) {
DBG_88E("Enable notch filter\n");
@ -2734,7 +2735,7 @@ u8 GetEEPROMSize8188E(PADAPTER padapter)
// LLT R/W/Init function
//
//-------------------------------------------------------------------------
s32 _LLTWrite(PADAPTER padapter, u32 address, u32 data)
static s32 _LLTWrite(PADAPTER padapter, u32 address, u32 data)
{
s32 status = _SUCCESS;
s32 count = 0;
@ -2761,31 +2762,6 @@ s32 _LLTWrite(PADAPTER padapter, u32 address, u32 data)
return status;
}
u8 _LLTRead(PADAPTER padapter, u32 address)
{
s32 count = 0;
u32 value = _LLT_INIT_ADDR(address) | _LLT_OP(_LLT_READ_ACCESS);
u16 LLTReg = REG_LLT_INIT;
rtw_write32(padapter, LLTReg, value);
//polling and get value
do {
value = rtw_read32(padapter, LLTReg);
if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) {
return (u8)value;
}
if (count > POLLING_LLT_THRESHOLD) {
RT_TRACE(_module_hal_init_c_, _drv_err_, ("Failed to polling read LLT done at address %d!\n", address));
break;
}
} while (count++);
return 0xFF;
}
s32 InitLLTTable(PADAPTER padapter, u8 txpktbuf_bndy)
{
s32 status = _FAIL;

13
hal/rtl8188e_mp.c
View file

@ -488,19 +488,6 @@ void Hal_SetTxPower(PADAPTER pAdapter)
// SetOFDMTxPower(pAdapter, TxPower);
}
void Hal_SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset)
{
u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D,tmpAGC;
TxAGCOffset_B = (ulTxAGCOffset&0x000000ff);
TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8);
TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16);
tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B);
write_bbreg(pAdapter, rFPGA0_TxGainStage,
(bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC);
}
void Hal_SetDataRate(PADAPTER pAdapter)
{
Hal_mpt_SwitchRfSetting(pAdapter);

313
hal/rtl8188e_phycfg.c
View file

@ -1074,12 +1074,8 @@ phy_ConfigBBWithParaFile(
//****************************************
// The following is for High Power PA
//****************************************
void
phy_ConfigBBExternalPA(
PADAPTER Adapter
)
static void phy_ConfigBBExternalPA(PADAPTER Adapter)
{
#ifdef CONFIG_USB_HCI
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u16 i=0;
u32 temp=0;
@ -1089,7 +1085,6 @@ phy_ConfigBBExternalPA(
// 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the
// same code as SU. It is already updated in PHY_REG_1T_HP.txt.
#endif
}
/*-----------------------------------------------------------------------------
@ -1677,30 +1672,7 @@ rtl8188e_PHY_ConfigRFWithParaFile(
}
//****************************************
// The following is for High Power PA
//****************************************
#define HighPowerRadioAArrayLen 22
//This is for High power PA
u32 Rtl8192S_HighPower_RadioA_Array[HighPowerRadioAArrayLen] = {
0x013,0x00029ea4,
0x013,0x00025e74,
0x013,0x00020ea4,
0x013,0x0001ced0,
0x013,0x00019f40,
0x013,0x00014e70,
0x013,0x000106a0,
0x013,0x0000c670,
0x013,0x000082a0,
0x013,0x00004270,
0x013,0x00000240,
};
int
PHY_ConfigRFExternalPA(
PADAPTER Adapter,
RF_RADIO_PATH_E eRFPath
)
static int PHY_ConfigRFExternalPA(PADAPTER Adapter, RF_RADIO_PATH_E eRFPath)
{
int rtStatus = _SUCCESS;
#ifdef CONFIG_USB_HCI
@ -1901,97 +1873,6 @@ exit:
}
#endif//#ifndef CONFIG_PHY_SETTING_WITH_ODM
/*-----------------------------------------------------------------------------
* Function: PHY_CheckBBAndRFOK()
*
* Overview: This function is write register and then readback to make sure whether
* BB[PHY0, PHY1], RF[Patha, path b, path c, path d] is Ok
*
* Input: PADAPTER Adapter
* HW90_BLOCK_E CheckBlock
* RF_RADIO_PATH_E eRFPath // it is used only when CheckBlock is HW90_BLOCK_RF
*
* Output: NONE
*
* Return: RT_STATUS_SUCCESS: PHY is OK
*
* Note: This function may be removed in the ASIC
*---------------------------------------------------------------------------*/
int
PHY_CheckBBAndRFOK(
PADAPTER Adapter,
HW90_BLOCK_E CheckBlock,
RF_RADIO_PATH_E eRFPath
)
{
int rtStatus = _SUCCESS;
u32 i, CheckTimes = 4,ulRegRead = 0;
u32 WriteAddr[4];
u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
// Initialize register address offset to be checked
WriteAddr[HW90_BLOCK_MAC] = 0x100;
WriteAddr[HW90_BLOCK_PHY0] = 0x900;
WriteAddr[HW90_BLOCK_PHY1] = 0x800;
WriteAddr[HW90_BLOCK_RF] = 0x3;
for (i=0 ; i < CheckTimes ; i++)
{
//
// Write Data to register and readback
//
switch (CheckBlock)
{
case HW90_BLOCK_MAC:
//RT_ASSERT(false, ("PHY_CheckBBRFOK(): Never Write 0x100 here!"));
//RT_TRACE(COMP_INIT, DBG_LOUD, ("PHY_CheckBBRFOK(): Never Write 0x100 here!\n"));
break;
case HW90_BLOCK_PHY0:
case HW90_BLOCK_PHY1:
rtw_write32(Adapter, WriteAddr[CheckBlock], WriteData[i]);
ulRegRead = rtw_read32(Adapter, WriteAddr[CheckBlock]);
break;
case HW90_BLOCK_RF:
// When initialization, we want the delay function(delay_ms(), delay_us()
// ==> actually we call PlatformStallExecution()) to do NdisStallExecution()
// [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK
// to run at Dispatch level to achive it.
//cosa PlatformAcquireSpinLock(Adapter, RT_INITIAL_SPINLOCK);
WriteData[i] &= 0xfff;
PHY_SetRFReg(Adapter, eRFPath, WriteAddr[HW90_BLOCK_RF], bRFRegOffsetMask, WriteData[i]);
// TODO: we should not delay for such a long time. Ask SD3
rtw_mdelay_os(10);
ulRegRead = PHY_QueryRFReg(Adapter, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
rtw_mdelay_os(10);
//cosa PlatformReleaseSpinLock(Adapter, RT_INITIAL_SPINLOCK);
break;
default:
rtStatus = _FAIL;
break;
}
//
// Check whether readback data is correct
//
if (ulRegRead != WriteData[i])
{
//RT_TRACE(COMP_FPGA, DBG_LOUD, ("ulRegRead: %lx, WriteData: %lx\n", ulRegRead, WriteData[i]));
rtStatus = _FAIL;
break;
}
}
return rtStatus;
}
void
rtl8192c_PHY_GetHWRegOriginalValue(
PADAPTER Adapter
@ -2004,19 +1885,12 @@ rtl8192c_PHY_GetHWRegOriginalValue(
pHalData->DefaultInitialGain[1] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XBAGCCore1, bMaskByte0);
pHalData->DefaultInitialGain[2] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XCAGCCore1, bMaskByte0);
pHalData->DefaultInitialGain[3] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XDAGCCore1, bMaskByte0);
//RT_TRACE(COMP_INIT, DBG_LOUD,
//("Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
//pHalData->DefaultInitialGain[0], pHalData->DefaultInitialGain[1],
//pHalData->DefaultInitialGain[2], pHalData->DefaultInitialGain[3]));
// read framesync
pHalData->framesync = (u8)PHY_QueryBBReg(Adapter, rOFDM0_RxDetector3, bMaskByte0);
pHalData->framesyncC34 = PHY_QueryBBReg(Adapter, rOFDM0_RxDetector2, bMaskDWord);
//RT_TRACE(COMP_INIT, DBG_LOUD, ("Default framesync (0x%x) = 0x%x\n",
// rOFDM0_RxDetector3, pHalData->framesync));
}
//
// Description:
// Map dBm into Tx power index according to
@ -2080,12 +1954,7 @@ phy_DbmToTxPwrIdx(
// current wireless mode.
// By Bruce, 2008-01-29.
//
int
phy_TxPwrIdxToDbm(
PADAPTER Adapter,
WIRELESS_MODE WirelessMode,
u8 TxPwrIdx
)
static int phy_TxPwrIdxToDbm(PADAPTER Adapter, WIRELESS_MODE WirelessMode, u8 TxPwrIdx)
{
int Offset = 0;
int PwrOutDbm = 0;
@ -2165,30 +2034,21 @@ PHY_GetTxPowerLevel8188E(
*powerlevel = TxPwrDbm;
}
void getTxPowerIndex88E(
PADAPTER Adapter,
u8 channel,
u8* cckPowerLevel,
u8* ofdmPowerLevel,
u8* BW20PowerLevel,
u8* BW40PowerLevel
)
static void getTxPowerIndex88E(PADAPTER Adapter, u8 channel, u8 *cckPowerLevel,
u8 *ofdmPowerLevel, u8 *BW20PowerLevel,
u8 *BW40PowerLevel)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u8 index = (channel -1);
u8 TxCount=0,path_nums;
if ((RF_1T2R == pHalData->rf_type) ||(RF_1T1R ==pHalData->rf_type ))
if ((RF_1T2R == pHalData->rf_type) || (RF_1T1R ==pHalData->rf_type))
path_nums = 1;
else
path_nums = 2;
for (TxCount=0;TxCount< path_nums ;TxCount++)
{
if (TxCount==RF_PATH_A)
{
for (TxCount=0; TxCount < path_nums; TxCount++) {
if (TxCount==RF_PATH_A) {
// 1. CCK
cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index];
//2. OFDM
@ -2212,10 +2072,8 @@ void getTxPowerIndex88E(
pHalData->BW20_24G_Diff[TxCount][index];
//2. BW40
BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
}
else if (TxCount==RF_PATH_C)
{
// 1. CCK
} else if (TxCount==RF_PATH_C) {
// 1. CCK
cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index];
//2. OFDM
ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+
@ -2229,9 +2087,7 @@ void getTxPowerIndex88E(
pHalData->BW20_24G_Diff[TxCount][index];
//2. BW40
BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
}
else if (TxCount==RF_PATH_D)
{
} else if (TxCount==RF_PATH_D) {
// 1. CCK
cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index];
//2. OFDM
@ -2251,22 +2107,12 @@ void getTxPowerIndex88E(
//2. BW40
BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
}
else
{
}
}
}
void phy_PowerIndexCheck88E(
PADAPTER Adapter,
u8 channel,
u8 * cckPowerLevel,
u8 * ofdmPowerLevel,
u8 * BW20PowerLevel,
u8 * BW40PowerLevel
)
static void phy_PowerIndexCheck88E(PADAPTER Adapter, u8 channel, u8 *cckPowerLevel,
u8 *ofdmPowerLevel, u8 *BW20PowerLevel, u8 *BW40PowerLevel)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
pHalData->CurrentCckTxPwrIdx = cckPowerLevel[0];
@ -2370,26 +2216,6 @@ PHY_UpdateTxPowerDbm8188E(
return true;
}
/*
Description:
When beacon interval is changed, the values of the
hw registers should be modified.
By tynli, 2008.10.24.
*/
void
rtl8192c_PHY_SetBeaconHwReg(
PADAPTER Adapter,
u16 BeaconInterval
)
{
}
void
PHY_ScanOperationBackup8188E(
PADAPTER Adapter,
@ -2835,78 +2661,48 @@ PHY_SetMonitorMode8192C(
* 11/15/2007 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
bool
PHY_CheckIsLegalRfPath8192C(
PADAPTER pAdapter,
u32 eRFPath)
bool PHY_CheckIsLegalRfPath8192C(PADAPTER pAdapter, u32 eRFPath)
{
// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
bool rtValue = true;
// NOt check RF Path now.!
return rtValue;
return true;
} /* PHY_CheckIsLegalRfPath8192C */
static void _PHY_SetRFPathSwitch(
PADAPTER pAdapter,
bool bMain,
bool is2T
)
static void _PHY_SetRFPathSwitch(PADAPTER pAdapter, bool bMain, bool is2T)
{
u8 u1bTmp;
if (!pAdapter->hw_init_completed)
{
if (!pAdapter->hw_init_completed) {
u1bTmp = rtw_read8(pAdapter, REG_LEDCFG2) | BIT7;
rtw_write8(pAdapter, REG_LEDCFG2, u1bTmp);
//PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
}
if (is2T)
{
if (is2T) {
if (bMain)
PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A
else
PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT
}
else
{
} else {
if (bMain)
PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x2); //Main
else
PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x1); //Aux
}
}
//return value true => Main; false => Aux
static bool _PHY_QueryRFPathSwitch(
PADAPTER pAdapter,
bool is2T
)
static bool _PHY_QueryRFPathSwitch(PADAPTER pAdapter, bool is2T)
{
// if (is2T)
// return true;
if (!pAdapter->hw_init_completed)
{
if (!pAdapter->hw_init_completed) {
PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
}
if (is2T)
{
if (is2T) {
if (PHY_QueryBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01)
return true;
else
return false;
}
else
{
} else {
if (PHY_QueryBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300) == 0x02)
return true;
else
@ -2914,67 +2710,10 @@ static bool _PHY_QueryRFPathSwitch(
}
}
static void
_PHY_DumpRFReg( PADAPTER pAdapter)
static void _PHY_DumpRFReg(PADAPTER pAdapter)
{
u32 rfRegValue,rfRegOffset;
//RTPRINT(FINIT, INIT_RF, ("PHY_DumpRFReg()====>\n"));
for (rfRegOffset = 0x00;rfRegOffset<=0x30;rfRegOffset++){
for (rfRegOffset = 0x00;rfRegOffset<=0x30;rfRegOffset++)
rfRegValue = PHY_QueryRFReg(pAdapter,RF_PATH_A, rfRegOffset, bMaskDWord);
//RTPRINT(FINIT, INIT_RF, (" 0x%02x = 0x%08x\n",rfRegOffset,rfRegValue));
}
//RTPRINT(FINIT, INIT_RF, ("<===== PHY_DumpRFReg()\n"));
}
//
// Move from phycfg.c to gen.c to be code independent later
//
//-------------------------Move to other DIR later----------------------------*/
#ifdef CONFIG_USB_HCI
//
// Description:
// To dump all Tx FIFO LLT related link-list table.
// Added by Roger, 2009.03.10.
//
void
DumpBBDbgPort_92CU(
PADAPTER Adapter
)
{
//RT_TRACE(COMP_SEND, DBG_WARNING, ("\n>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"));
//RT_TRACE(COMP_SEND, DBG_WARNING, ("BaseBand Debug Ports:\n"));
PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0000);
//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0803);
//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0a06);
//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0007);
//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0100);
PHY_SetBBReg(Adapter, 0x0a28, 0x00ff0000, 0x000f0000);
//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0100);
PHY_SetBBReg(Adapter, 0x0a28, 0x00ff0000, 0x00150000);
//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0x800, PHY_QueryBBReg(Adapter, 0x0800, bMaskDWord)));
//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0x900, PHY_QueryBBReg(Adapter, 0x0900, bMaskDWord)));
//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa00, PHY_QueryBBReg(Adapter, 0x0a00, bMaskDWord)));
//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa54, PHY_QueryBBReg(Adapter, 0x0a54, bMaskDWord)));
//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa58, PHY_QueryBBReg(Adapter, 0x0a58, bMaskDWord)));
}
#endif

232
hal/rtl8188e_rf6052.c
View file

@ -282,7 +282,7 @@ rtl8188e_PHY_RF6052SetCckTxPower(
// powerbase0 for OFDM rates
// powerbase1 for HT MCS rates
//
void getPowerBase88E(
static void getPowerBase88E(
PADAPTER Adapter,
u8* pPowerLevelOFDM,
u8* pPowerLevelBW20,
@ -325,7 +325,7 @@ void getPowerBase88E(
}
}
void getTxPowerWriteValByRegulatory88E(
static void getTxPowerWriteValByRegulatory88E(
PADAPTER Adapter,
u8 Channel,
u8 index,
@ -779,232 +779,4 @@ PHY_RF6052_Config8188E(
return rtStatus;
}
//
// ==> RF shadow Operation API Code Section!!!
//
/*-----------------------------------------------------------------------------
* Function: PHY_RFShadowRead
* PHY_RFShadowWrite
* PHY_RFShadowCompare
* PHY_RFShadowRecorver
* PHY_RFShadowCompareAll
* PHY_RFShadowRecorverAll
* PHY_RFShadowCompareFlagSet
* PHY_RFShadowRecorverFlagSet
*
* Overview: When we set RF register, we must write shadow at first.
* When we are running, we must compare shadow abd locate error addr.
* Decide to recorver or not.
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 11/20/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
u32
PHY_RFShadowRead(
PADAPTER Adapter,
RF_RADIO_PATH_E eRFPath,
u32 Offset)
{
return RF_Shadow[eRFPath][Offset].Value;
} /* PHY_RFShadowRead */
void
PHY_RFShadowWrite(
PADAPTER Adapter,
RF_RADIO_PATH_E eRFPath,
u32 Offset,
u32 Data)
{
RF_Shadow[eRFPath][Offset].Value = (Data & bRFRegOffsetMask);
RF_Shadow[eRFPath][Offset].Driver_Write = true;
} /* PHY_RFShadowWrite */
bool
PHY_RFShadowCompare(
PADAPTER Adapter,
RF_RADIO_PATH_E eRFPath,
u32 Offset)
{
u32 reg;
// Check if we need to check the register
if (RF_Shadow[eRFPath][Offset].Compare == true)
{
reg = PHY_QueryRFReg(Adapter, eRFPath, Offset, bRFRegOffsetMask);
// Compare shadow and real rf register for 20bits!!
if (RF_Shadow[eRFPath][Offset].Value != reg)
{
// Locate error position.
RF_Shadow[eRFPath][Offset].ErrorOrNot = true;
//RT_TRACE(COMP_INIT, DBG_LOUD,
//("PHY_RFShadowCompare RF-%d Addr%02lx Err = %05lx\n",
//eRFPath, Offset, reg));
}
return RF_Shadow[eRFPath][Offset].ErrorOrNot ;
}
return false;
} /* PHY_RFShadowCompare */
void
PHY_RFShadowRecorver(
PADAPTER Adapter,
RF_RADIO_PATH_E eRFPath,
u32 Offset)
{
// Check if the address is error
if (RF_Shadow[eRFPath][Offset].ErrorOrNot == true)
{
// Check if we need to recorver the register.
if (RF_Shadow[eRFPath][Offset].Recorver == true)
{
PHY_SetRFReg(Adapter, eRFPath, Offset, bRFRegOffsetMask,
RF_Shadow[eRFPath][Offset].Value);
//RT_TRACE(COMP_INIT, DBG_LOUD,
//("PHY_RFShadowRecorver RF-%d Addr%02lx=%05lx",
//eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value));
}
}
} /* PHY_RFShadowRecorver */
void
PHY_RFShadowCompareAll(
PADAPTER Adapter)
{
u32 eRFPath;
u32 Offset;
for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
{
for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
{
PHY_RFShadowCompare(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset);
}
}
} /* PHY_RFShadowCompareAll */
void
PHY_RFShadowRecorverAll(
PADAPTER Adapter)
{
u32 eRFPath;
u32 Offset;
for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
{
for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
{
PHY_RFShadowRecorver(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset);
}
}
} /* PHY_RFShadowRecorverAll */
void
PHY_RFShadowCompareFlagSet(
PADAPTER Adapter,
RF_RADIO_PATH_E eRFPath,
u32 Offset,
u8 Type)
{
// Set True or False!!!
RF_Shadow[eRFPath][Offset].Compare = Type;
} /* PHY_RFShadowCompareFlagSet */
void
PHY_RFShadowRecorverFlagSet(
PADAPTER Adapter,
RF_RADIO_PATH_E eRFPath,
u32 Offset,
u8 Type)
{
// Set True or False!!!
RF_Shadow[eRFPath][Offset].Recorver= Type;
} /* PHY_RFShadowRecorverFlagSet */
void
PHY_RFShadowCompareFlagSetAll(
PADAPTER Adapter)
{
u32 eRFPath;
u32 Offset;
for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
{
for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
{
// 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!!
if (Offset != 0x26 && Offset != 0x27)
PHY_RFShadowCompareFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, false);
else
PHY_RFShadowCompareFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, true);
}
}
} /* PHY_RFShadowCompareFlagSetAll */
void
PHY_RFShadowRecorverFlagSetAll(
PADAPTER Adapter)
{
u32 eRFPath;
u32 Offset;
for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
{
for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
{
// 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!!
if (Offset != 0x26 && Offset != 0x27)
PHY_RFShadowRecorverFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, false);
else
PHY_RFShadowRecorverFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, true);
}
}
} /* PHY_RFShadowCompareFlagSetAll */
void
PHY_RFShadowRefresh(
PADAPTER Adapter)
{
u32 eRFPath;
u32 Offset;
for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
{
for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
{
RF_Shadow[eRFPath][Offset].Value = 0;
RF_Shadow[eRFPath][Offset].Compare = false;
RF_Shadow[eRFPath][Offset].Recorver = false;
RF_Shadow[eRFPath][Offset].ErrorOrNot = false;
RF_Shadow[eRFPath][Offset].Driver_Write = false;
}
}
} /* PHY_RFShadowRead */
/* End of HalRf6052.c */

2
hal/usb_halinit.c
View file

@ -3524,9 +3524,7 @@ _func_enter_;
// Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power
// saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang.
if ( (psmode != PS_MODE_ACTIVE) && (!IS_92C_SERIAL(pHalData->VersionID)))
{
ODM_RF_Saving(podmpriv, true);
}
rtl8188e_set_FwPwrMode_cmd(Adapter, psmode);
}
break;

2
hal/usb_ops_linux.c
View file

@ -377,7 +377,7 @@ static int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata
}
#ifdef CONFIG_SUPPORT_USB_INT
void interrupt_handler_8188eu(_adapter *padapter,u16 pkt_len,u8 *pbuf)
static void interrupt_handler_8188eu(_adapter *padapter,u16 pkt_len,u8 *pbuf)
{
HAL_DATA_TYPE *pHalData=GET_HAL_DATA(padapter);
struct reportpwrstate_parm pwr_rpt;