diff --git a/include/byteorder/big_endian.h b/include/big_endian.h similarity index 100% rename from include/byteorder/big_endian.h rename to include/big_endian.h diff --git a/include/byteorder/generic.h b/include/generic.h similarity index 100% rename from include/byteorder/generic.h rename to include/generic.h diff --git a/include/linux/wireless.h b/include/linux/wireless.h deleted file mode 100755 index 2fb0cd3..0000000 --- a/include/linux/wireless.h +++ /dev/null @@ -1,81 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef _LINUX_WIRELESS_H -#define _LINUX_WIRELESS_H - -/***************************** INCLUDES *****************************/ - -#define __user -//typedef uint16_t __u16; -#include /* for "struct sockaddr" et al */ -#include /* for IFNAMSIZ and co... */ - -/****************************** TYPES ******************************/ - -/* --------------------------- SUBTYPES --------------------------- */ -/* - * For all data larger than 16 octets, we need to use a - * pointer to memory allocated in user space. - */ -struct iw_point { - void __user *pointer; /* Pointer to the data (in user space) */ - __u16 length; /* number of fields or size in bytes */ - __u16 flags; /* Optional params */ -}; - - -/* ------------------------ IOCTL REQUEST ------------------------ */ -/* - * This structure defines the payload of an ioctl, and is used - * below. - * - * Note that this structure should fit on the memory footprint - * of iwreq (which is the same as ifreq), which mean a max size of - * 16 octets = 128 bits. Warning, pointers might be 64 bits wide... - * You should check this when increasing the structures defined - * above in this file... - */ -union iwreq_data { - /* Config - generic */ - char name[IFNAMSIZ]; - /* Name : used to verify the presence of wireless extensions. - * Name of the protocol/provider... */ - - struct iw_point data; /* Other large parameters */ -}; - -/* - * The structure to exchange data for ioctl. - * This structure is the same as 'struct ifreq', but (re)defined for - * convenience... - * Do I need to remind you about structure size (32 octets) ? - */ -struct iwreq { - union { - char ifrn_name[IFNAMSIZ]; /* if name, e.g. "eth0" */ - } ifr_ifrn; - - /* Data part (defined just above) */ - union iwreq_data u; -}; - -#endif /* _LINUX_WIRELESS_H */ - diff --git a/include/byteorder/little_endian.h b/include/little_endian.h similarity index 100% rename from include/byteorder/little_endian.h rename to include/little_endian.h diff --git a/include/rtl8192d_cmd.h b/include/rtl8192d_cmd.h deleted file mode 100755 index b178fa8..0000000 --- a/include/rtl8192d_cmd.h +++ /dev/null @@ -1,101 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8192D_CMD_H_ -#define __RTL8192D_CMD_H_ - - -//-------------------------------------------- -//3 Host Message Box -//-------------------------------------------- - -// User Define Message [31:8] - -//_SETPWRMODE_PARM -#define SET_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) -#define SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) - -//JOINBSSRPT_PARM -#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) - -//_RSVDPAGE_LOC -#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) -#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) -#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) - -//P2P_PS_OFFLOAD - -struct P2P_PS_Offload_t { - unsigned char Offload_En:1; - unsigned char role:1; // 1: Owner, 0: Client - unsigned char CTWindow_En:1; - unsigned char NoA0_En:1; - unsigned char NoA1_En:1; - unsigned char AllStaSleep:1; // Only valid in Owner - unsigned char discovery:1; - unsigned char rsvd:1; -}; - -#define SET_H2CCMD_P2P_PS_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) -#define SET_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) -#define SET_H2CCMD_P2P_PS_OFFLOAD_CTW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) -#define SET_H2CCMD_P2P_PS_OFFLOAD_NOA0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value) -#define SET_H2CCMD_P2P_PS_OFFLOAD_NOA1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value) -#define SET_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value) -#define SET_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value) - -// Description: Determine the types of H2C commands that are the same in driver and Fw. -// Fisrt constructed by tynli. 2009.10.09. -typedef enum _RTL8192D_H2C_CMD -{ - H2C_AP_OFFLOAD = 0, /*0*/ - H2C_SETPWRMODE = 1, /*1*/ - H2C_JOINBSSRPT = 2, /*2*/ - H2C_RSVDPAGE = 3, - H2C_RSSI_REPORT = 5, - H2C_RA_MASK = 6, - H2C_P2P_PS_OFFLOAD = 8, - H2C_MAC_MODE_SEL = 9, - H2C_PWRM=15, - H2C_P2P_PS_CTW_CMD = 24, - H2C_PathDiv = 26, //PathDiv--NeilChen--2011.07.15 - H2C_CMD_MAX -}RTL8192D_H2C_CMD; - -struct cmd_msg_parm { - u8 eid; //element id - u8 sz; // sz - u8 buf[6]; -}; - - -void FillH2CCmd92D(struct adapter* padapter, u8 ElementID, u32 CmdLen, u8* pCmdBuffer); - -// host message to firmware cmd -void rtl8192d_set_FwPwrMode_cmd(struct adapter*padapter, u8 Mode); -void rtl8192d_set_FwJoinBssReport_cmd(struct adapter* padapter, u8 mstatus); -u8 rtl8192d_set_rssi_cmd(struct adapter*padapter, u8 *param); -u8 rtl8192d_set_raid_cmd(struct adapter*padapter, u32 mask, u8 arg); -void rtl8192d_Add_RateATid(struct adapter *pAdapter, u32 bitmap, u8 arg, u8 rssi_level); -#ifdef CONFIG_P2P -void rtl8192d_set_p2p_ps_offload_cmd(struct adapter* padapter, u8 p2p_ps_state); -#endif //CONFIG_P2P - -#endif diff --git a/include/rtl8192d_dm.h b/include/rtl8192d_dm.h deleted file mode 100755 index 837fd58..0000000 --- a/include/rtl8192d_dm.h +++ /dev/null @@ -1,182 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8192D_DM_H__ -#define __RTL8192D_DM_H__ -//============================================================ -// Description: -// -// This file is for 92CE/92CU dynamic mechanism only -// -// -//============================================================ -enum{ - UP_LINK, - DOWN_LINK, -}; -/*------------------------Export global variable----------------------------*/ -/*------------------------Export global variable----------------------------*/ -/*------------------------Export Marco Definition---------------------------*/ -//#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;} -//============================================================ -// structure and define -//============================================================ - -//###### duplicate code,will move to ODM ######### -#define IQK_MAC_REG_NUM 4 -#define IQK_ADDA_REG_NUM 16 -#define IQK_BB_REG_NUM 10 -#define IQK_BB_REG_NUM_92C 9 -#define IQK_BB_REG_NUM_92D 10 -#define IQK_BB_REG_NUM_test 6 -#define index_mapping_NUM 13 -#define Rx_index_mapping_NUM 15 -#define AVG_THERMAL_NUM 8 -#define IQK_Matrix_REG_NUM 8 -#define IQK_Matrix_Settings_NUM 1+24+21 -//###### duplicate code,will move to ODM ######### -struct dm_priv -{ - u8 DM_Type; - u8 DMFlag; - u8 InitDMFlag; - u32 InitODMFlag; - - //* Upper and Lower Signal threshold for Rate Adaptive*/ - int UndecoratedSmoothedPWDB; - int EntryMinUndecoratedSmoothedPWDB; - int EntryMaxUndecoratedSmoothedPWDB; - int MinUndecoratedPWDBForDM; - int LastMinUndecoratedPWDBForDM; -//###### duplicate code,will move to ODM ######### -/* - //for DIG - u8 bDMInitialGainEnable; - //u8 binitialized; // for dm_initial_gain_Multi_STA use. - DIG_T DM_DigTable; - - PS_T DM_PSTable; - - FALSE_ALARM_STATISTICS FalseAlmCnt; - - //for rate adaptive, in fact, 88c/92c fw will handle this - u8 bUseRAMask; - RATE_ADAPTIVE RateAdaptive; -*/ - - //for High Power - u8 bDynamicTxPowerEnable; - u8 LastDTPLvl; - u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06 - - //for tx power tracking - u8 bTXPowerTracking; - u8 TXPowercount; - u8 bTXPowerTrackingInit; - u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default - u8 TM_Trigger; - - u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 - u8 ThermalValue; - u8 ThermalValue_LCK; - u8 ThermalValue_IQK; - u8 ThermalValue_AVG[AVG_THERMAL_NUM]; - u8 ThermalValue_AVG_index; - u8 ThermalValue_RxGain; - u8 ThermalValue_Crystal; - u8 Delta_IQK; - u8 Delta_LCK; - u8 bRfPiEnable; - u8 bReloadtxpowerindex; - u8 bDoneTxpower; - - //for APK - u32 APKoutput[2][2]; //path A/B; output1_1a/output1_2a - u8 bAPKdone; - u8 bAPKThermalMeterIgnore; - u32 RegA24; - - //for IQK - u32 Reg874; - u32 RegC08; - u32 Reg88C; - u8 Reg522; - u8 Reg550; - u8 Reg551; - u32 Reg870; - u32 ADDA_backup[IQK_ADDA_REG_NUM]; - u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; - u32 IQK_BB_backup[IQK_BB_REG_NUM]; - - u8 bCCKinCH14; - - char CCK_index; - //u8 Record_CCK_20Mindex; - //u8 Record_CCK_40Mindex; - char OFDM_index[2]; - - BOOLEAN bDPKdone[2]; - - u8 PowerIndex_backup[6]; - - //for Antenna diversity -//#ifdef CONFIG_ANTENNA_DIVERSITY - //SWAT_T DM_SWAT_Table; -//#endif - //Neil Chen----2011--06--23----- - //3 Path Diversity - BOOLEAN bPathDiv_Enable; //For 92D Non-interrupt Antenna Diversity by Neil ,add by wl.2011.07.19 - BOOLEAN RSSI_test; - s32 RSSI_sum_A; - s32 RSSI_cnt_A; - s32 RSSI_sum_B; - s32 RSSI_cnt_B; - struct sta_info *RSSI_target; - _timer PathDivSwitchTimer; - - //for TxPwrTracking - int RegE94; - int RegE9C; - int RegEB4; - int RegEBC; -#if MP_DRIVER == 1 - u8 RegC04_MP; - u32 RegD04_MP; -#endif - u32 TXPowerTrackingCallbackCnt; //cosa add for debug - - u32 prv_traffic_idx; // edca turbo - - u32 RegRF3C[2]; //pathA / pathB -//###### duplicate code,will move to ODM ######### - // Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas - u8 INIDATA_RATE[32]; -}; - - -//============================================================ -// function prototype -//============================================================ -void rtl8192d_init_dm_priv(IN struct adapter *Adapter); -void rtl8192d_deinit_dm_priv(IN struct adapter *Adapter); - -void rtl8192d_InitHalDm(IN struct adapter *Adapter); -void rtl8192d_HalDmWatchDog(IN struct adapter *Adapter); - -#endif //__HAL8190PCIDM_H__ diff --git a/include/rtl8192d_hal.h b/include/rtl8192d_hal.h deleted file mode 100755 index a788ae8..0000000 --- a/include/rtl8192d_hal.h +++ /dev/null @@ -1,759 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8192D_HAL_H__ -#define __RTL8192D_HAL_H__ - -#include "rtl8192d_spec.h" -#include "Hal8192DPhyReg.h" -#include "Hal8192DPhyCfg.h" -#include "rtl8192d_rf.h" -#include "rtl8192d_dm.h" -#include "rtl8192d_recv.h" -#include "rtl8192d_xmit.h" -#include "rtl8192d_cmd.h" -#include "rtw_efuse.h" - -#include "../hal/OUTSRC/odm_precomp.h" - -#define RTL819X_DEFAULT_RF_TYPE RF_1T2R - -//--------------------------------------------------------------------- -// RTL8192DU From file -//--------------------------------------------------------------------- -#define RTL8192D_FW_IMG "rtl8192DU\\rtl8192dfw.bin" - -#define RTL8192D_PHY_REG "rtl8192DU\\PHY_REG.txt" -#define RTL8192D_PHY_REG_PG "rtl8192DU\\PHY_REG_PG.txt" -#define RTL8192D_PHY_REG_MP "rtl8192DU\\PHY_REG_MP.txt" - -#define RTL8192D_AGC_TAB "rtl8192DU\\AGC_TAB.txt" -#define RTL8192D_AGC_TAB_2G "rtl8192DU\\AGC_TAB_2G.txt" -#define RTL8192D_AGC_TAB_5G "rtl8192DU\\AGC_TAB_5G.txt" -#define RTL8192D_PHY_RADIO_A "rtl8192DU\\radio_a.txt" -#define RTL8192D_PHY_RADIO_B "rtl8192DU\\radio_b.txt" -#define RTL8192D_PHY_RADIO_A_intPA "rtl8192DU\\radio_a_intPA.txt" -#define RTL8192D_PHY_RADIO_B_intPA "rtl8192DU\\radio_b_intPA.txt" -#define RTL8192D_PHY_MACREG "rtl8192DU\\MAC_REG.txt" - -//--------------------------------------------------------------------- -// RTL8192DU From header -//--------------------------------------------------------------------- - -// Fw Array -#define Rtl8192D_FwImageArray Rtl8192DUFwImgArray - -// MAC/BB/PHY Array -#define Rtl8192D_MAC_Array Rtl8192DUMAC_2T_Array -#define Rtl8192D_AGCTAB_Array Rtl8192DUAGCTAB_Array -#define Rtl8192D_AGCTAB_5GArray Rtl8192DUAGCTAB_5GArray -#define Rtl8192D_AGCTAB_2GArray Rtl8192DUAGCTAB_2GArray -#define Rtl8192D_AGCTAB_2TArray Rtl8192DUAGCTAB_2TArray -#define Rtl8192D_AGCTAB_1TArray Rtl8192DUAGCTAB_1TArray -#define Rtl8192D_PHY_REG_2TArray Rtl8192DUPHY_REG_2TArray -#define Rtl8192D_PHY_REG_1TArray Rtl8192DUPHY_REG_1TArray -#define Rtl8192D_PHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG -#define Rtl8192D_PHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP -#define Rtl8192D_RadioA_2TArray Rtl8192DURadioA_2TArray -#define Rtl8192D_RadioA_1TArray Rtl8192DURadioA_1TArray -#define Rtl8192D_RadioB_2TArray Rtl8192DURadioB_2TArray -#define Rtl8192D_RadioB_1TArray Rtl8192DURadioB_1TArray -#define Rtl8192D_RadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray -#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray - -// Array length -#define Rtl8192D_FwImageArrayLength Rtl8192DUImgArrayLength -#define Rtl8192D_MAC_ArrayLength Rtl8192DUMAC_2T_ArrayLength -#define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DUAGCTAB_5GArrayLength -#define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DUAGCTAB_2GArrayLength -#define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DUAGCTAB_2TArrayLength -#define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DUAGCTAB_1TArrayLength -#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DUAGCTAB_ArrayLength -#define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DUPHY_REG_2TArrayLength -#define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DUPHY_REG_1TArrayLength -#define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DUPHY_REG_Array_PGLength -#define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DUPHY_REG_Array_MPLength -#define Rtl8192D_RadioA_2TArrayLength Rtl8192DURadioA_2TArrayLength -#define Rtl8192D_RadioB_2TArrayLength Rtl8192DURadioB_2TArrayLength -#define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DURadioA_2T_intPAArrayLength -#define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DURadioB_2T_intPAArrayLength - -// The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24. -#define DRVINFO_SZ 4 // unit is 8bytes -#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0)) - -// -// Check if FW header exists. We do not consider the lower 4 bits in this case. -// By tynli. 2009.12.04. -// -#define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\ - (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\ - (le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D0 ||\ - (le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D1 ||\ - (le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D2 ||\ - (le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D3 ) - -#define FW_8192D_SIZE 0x8020 // Max FW len = 32k + 32(FW header length). -#define FW_8192D_START_ADDRESS 0x1000 -#define FW_8192D_END_ADDRESS 0x1FFF - -#define MAX_PAGE_SIZE 4096 // @ page : 4k bytes - -typedef enum _FIRMWARE_SOURCE{ - FW_SOURCE_IMG_FILE = 0, - FW_SOURCE_HEADER_FILE = 1, //from header file -}FIRMWARE_SOURCE, *PFIRMWARE_SOURCE; - -typedef struct _RT_FIRMWARE{ - FIRMWARE_SOURCE eFWSource; - u8* szFwBuffer; - u32 ulFwLength; -}RT_FIRMWARE, *PRT_FIRMWARE, RT_FIRMWARE_92D, *PRT_FIRMWARE_92D; - -// -// This structure must be cared byte-ordering -// -// Added by tynli. 2009.12.04. -typedef struct _RT_8192D_FIRMWARE_HDR {//8-byte alinment required - - //--- LONG WORD 0 ---- - u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut - u8 Category; // AP/NIC and USB/PCI - u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions - u16 Version; // FW Version - u8 Subversion; // FW Subversion, default 0x00 - u8 Rsvd1; - - - //--- LONG WORD 1 ---- - u8 Month; // Release time Month field - u8 Date; // Release time Date field - u8 Hour; // Release time Hour field - u8 Minute; // Release time Minute field - u16 RamCodeSize; // The size of RAM code - u16 Rsvd2; - - //--- LONG WORD 2 ---- - u32 SvnIdx; // The SVN entry index - u32 Rsvd3; - - //--- LONG WORD 3 ---- - u32 Rsvd4; - u32 Rsvd5; - -}RT_8192D_FIRMWARE_HDR, *PRT_8192D_FIRMWARE_HDR; - -#define DRIVER_EARLY_INT_TIME 0x05 -#define BCN_DMA_ATIME_INT_TIME 0x02 - -typedef enum _BT_CoType{ - BT_2Wire = 0, - BT_ISSC_3Wire = 1, - BT_Accel = 2, - BT_CSR = 3, - BT_CSR_ENHAN = 4, - BT_RTL8756 = 5, -} BT_CoType, *PBT_CoType; - -typedef enum _BT_CurState{ - BT_OFF = 0, - BT_ON = 1, -} BT_CurState, *PBT_CurState; - -typedef enum _BT_ServiceType{ - BT_SCO = 0, - BT_A2DP = 1, - BT_HID = 2, - BT_HID_Idle = 3, - BT_Scan = 4, - BT_Idle = 5, - BT_OtherAction = 6, - BT_Busy = 7, - BT_OtherBusy = 8, -} BT_ServiceType, *PBT_ServiceType; - -typedef enum _BT_RadioShared{ - BT_Radio_Shared = 0, - BT_Radio_Individual = 1, -} BT_RadioShared, *PBT_RadioShared; - -typedef struct _BT_COEXIST_STR{ - u8 BluetoothCoexist; - u8 BT_Ant_Num; - u8 BT_CoexistType; - u8 BT_State; - u8 BT_CUR_State; //0:on, 1:off - u8 BT_Ant_isolation; //0:good, 1:bad - u8 BT_PapeCtrl; //0:SW, 1:SW/HW dynamic - u8 BT_Service; - u8 BT_RadioSharedType; - u8 Ratio_Tx; - u8 Ratio_PRI; -}BT_COEXIST_STR, *PBT_COEXIST_STR; - - -#ifdef CONFIG_USB_RX_AGGREGATION - -typedef enum _USB_RX_AGG_MODE{ - USB_RX_AGG_DISABLE, - USB_RX_AGG_DMA, - USB_RX_AGG_USB, - USB_RX_AGG_DMA_USB -}USB_RX_AGG_MODE; - -#define MAX_RX_DMA_BUFFER_SIZE 10240 // 10K for 8192C RX DMA buffer - -#endif - - -#define TX_SELE_HQ BIT(0) // High Queue -#define TX_SELE_LQ BIT(1) // Low Queue -#define TX_SELE_NQ BIT(2) // Normal Queue - - -// Note: We will divide number of page equally for each queue other than public queue! - -#define TX_TOTAL_PAGE_NUMBER 0xF8 -#define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER + 1) - -// For Normal Chip Setting -// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER -#define NORMAL_PAGE_NUM_PUBQ 0x56 - - -// For Test Chip Setting -// (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER -#define TEST_PAGE_NUM_PUBQ 0x89 -#define TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC 0x7A -#define NORMAL_PAGE_NUM_PUBQ_92D_DUAL_MAC 0x5A -#define NORMAL_PAGE_NUM_HPQ_92D_DUAL_MAC 0x10 -#define NORMAL_PAGE_NUM_LPQ_92D_DUAL_MAC 0x10 -#define NORMAL_PAGE_NUM_NORMALQ_92D_DUAL_MAC 0 - -#define TX_PAGE_BOUNDARY_DUAL_MAC (TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC + 1) - -// For Test Chip Setting -#define WMM_TEST_TX_TOTAL_PAGE_NUMBER 0xF5 -#define WMM_TEST_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6 - -#define WMM_TEST_PAGE_NUM_PUBQ 0xA3 -#define WMM_TEST_PAGE_NUM_HPQ 0x29 -#define WMM_TEST_PAGE_NUM_LPQ 0x29 - - -//Note: For Normal Chip Setting ,modify later -#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5 -#define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6 - -#define WMM_NORMAL_PAGE_NUM_PUBQ 0xB0 -#define WMM_NORMAL_PAGE_NUM_HPQ 0x29 -#define WMM_NORMAL_PAGE_NUM_LPQ 0x1C -#define WMM_NORMAL_PAGE_NUM_NPQ 0x1C - -#define WMM_NORMAL_PAGE_NUM_PUBQ_92D 0X65//0x82 -#define WMM_NORMAL_PAGE_NUM_HPQ_92D 0X30//0x29 -#define WMM_NORMAL_PAGE_NUM_LPQ_92D 0X30 -#define WMM_NORMAL_PAGE_NUM_NPQ_92D 0X30 - -//------------------------------------------------------------------------- -// Chip specific -//------------------------------------------------------------------------- - -#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3) -#define CHIP_BONDING_92C_1T2R 0x1 -#define CHIP_BONDING_88C_USB_MCARD 0x2 -#define CHIP_BONDING_88C_USB_HP 0x1 - -#include "HalVerDef.h" -#include "hal_com.h" - -//------------------------------------------------------------------------- -// Channel Plan -//------------------------------------------------------------------------- -enum ChannelPlan{ - CHPL_FCC = 0, - CHPL_IC = 1, - CHPL_ETSI = 2, - CHPL_SPAIN = 3, - CHPL_FRANCE = 4, - CHPL_MKK = 5, - CHPL_MKK1 = 6, - CHPL_ISRAEL = 7, - CHPL_TELEC = 8, - CHPL_GLOBAL = 9, - CHPL_WORLD = 10, -}; - -typedef struct _TxPowerInfo{ - u8 CCKIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX]; - u8 HT40_1SIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX]; - u8 HT40_2SIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX]; - s8 HT20IndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX]; - u8 OFDMIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX]; - u8 HT40MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX]; - u8 HT20MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX]; - u8 TSSI_A[3]; - u8 TSSI_B[3]; - u8 TSSI_A_5G[3]; //5GL/5GM/5GH - u8 TSSI_B_5G[3]; -}TxPowerInfo, *PTxPowerInfo; - -#define EFUSE_REAL_CONTENT_LEN 1024 -#define EFUSE_MAP_LEN 256 -#define EFUSE_MAX_SECTION 32 -#define EFUSE_MAX_SECTION_BASE 16 -// To prevent out of boundary programming case, leave 1byte and program full section -// 9bytes + 1byt + 5bytes and pre 1byte. -// For worst case: -// | 2byte|----8bytes----|1byte|--7bytes--| //92D -#define EFUSE_OOB_PROTECT_BYTES 18 // PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. - -typedef enum _PA_MODE { - PA_MODE_EXTERNAL = 0x00, - PA_MODE_INTERNAL_SP3T = 0x01, - PA_MODE_INTERNAL_SPDT = 0x02 -} PA_MODE; - -/* Copy from rtl8192c */ -enum c2h_id_8192d { - C2H_DBG = 0, - C2H_TSF = 1, - C2H_AP_RPT_RSP = 2, - C2H_CCX_TX_RPT = 3, - C2H_BT_RSSI = 4, - C2H_BT_OP_MODE = 5, - C2H_EXT_RA_RPT = 6, - C2H_HW_INFO_EXCH = 10, - C2H_C2H_H2C_TEST = 11, - C2H_BT_INFO = 12, - C2H_BT_MP_INFO = 15, - MAX_C2HEVENT -}; - -struct hal_data_8192de { - HAL_VERSION VersionID; - // add for 92D Phy mode/mac/Band mode - MACPHY_MODE_8192D MacPhyMode92D; - BAND_TYPE CurrentBandType92D; //0:2.4G, 1:5G - BAND_TYPE BandSet92D; - BOOLEAN bIsVS; - BOOLEAN bSupportRemoteWakeUp; - u8 AutoLoadStatusFor8192D; - - BOOLEAN bNOPG; - - BOOLEAN bMasterOfDMSP; - BOOLEAN bSlaveOfDMSP; - - u16 CustomerID; - - u16 FirmwareVersion; - u16 FirmwareVersionRev; - u16 FirmwareSubVersion; - - u32 IntrMask[2]; - u32 IntrMaskToSet[2]; - - u32 DisabledFunctions; - - //current WIFI_PHY values - u32 ReceiveConfig; - u32 TransmitConfig; - WIRELESS_MODE CurrentWirelessMode; - HT_CHANNEL_WIDTH CurrentChannelBW; - u8 CurrentChannel; - u8 nCur40MhzPrimeSC;// Control channel sub-carrier - u16 BasicRateSet; - - //rf_ctrl - u8 rf_chip; - u8 rf_type; - u8 NumTotalRFPath; - - // - // EEPROM setting. - // - u16 EEPROMVID; - u16 EEPROMDID; - u16 EEPROMSVID; - u16 EEPROMSMID; - u16 EEPROMChannelPlan; - u16 EEPROMVersion; - - u8 EEPROMCustomerID; - u8 EEPROMBoardType; - u8 EEPROMRegulatory; - - u8 EEPROMThermalMeter; - - u8 EEPROMC9; - u8 EEPROMCC; - u8 PAMode; - - u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER_2G]; - u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr - u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr - s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff - u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff - // For power group - u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; - u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; - - u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff - - u8 CrystalCap; // CrystalCap. - -#ifdef CONFIG_BT_COEXIST - struct btcoexist_priv bt_coexist; -#endif - - // Read/write are allow for following hardware information variables - u8 framesync; - u32 framesyncC34; - u8 framesyncMonitor; - u8 DefaultInitialGain[4]; - u8 pwrGroupCnt; - u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16]; - u32 CCKTxPowerLevelOriginalOffset; - - u32 AntennaTxPath; // Antenna path Tx - u32 AntennaRxPath; // Antenna path Rx - u8 BluetoothCoexist; - u8 ExternalPA; - u8 InternalPA5G[2]; //pathA / pathB - - //u32 LedControlNum; - //u32 LedControlMode; - //u32 TxPowerTrackControl; - u8 b1x1RecvCombine; // for 1T1R receive combining - - u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo. - - //vivi, for tx power tracking, 20080407 - //u16 TSSI_13dBm; - //u32 Pwr_Track; - // The current Tx Power Level - u8 CurrentCckTxPwrIdx; - u8 CurrentOfdm24GTxPwrIdx; - - BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D - - u32 RfRegChnlVal[2]; - - - BOOLEAN bPhyValueInitReady; - - BOOLEAN bTXPowerDataReadFromEEPORM; - - BOOLEAN bInSetPower; - - //RDG enable - BOOLEAN bRDGEnable; - - BOOLEAN bLoadIMRandIQKSettingFor2G;// True if IMR or IQK have done for 2.4G in scan progress - BOOLEAN bNeedIQK; - - BOOLEAN bLCKInProgress; - - BOOLEAN bEarlyModeEnable; - -#if 1 - IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; -#else - //regc80、regc94、regc4c、regc88、regc9c、regc14、regca0、regc1c、regc78 - u4Byte IQKMatrixReg[IQK_Matrix_REG_NUM]; - IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; // 1->2G,24->5G 20M channel,21->5G 40M channel. -#endif - - //for host message to fw - u8 LastHMEBoxNum; - - u8 fw_ractrl; - // Beacon function related global variable. - u32 RegBcnCtrlVal; - u8 RegTxPause; - u8 RegFwHwTxQCtrl; - u8 RegReg542; - u8 RegCR_1; - - struct dm_priv dmpriv; - DM_ODM_T odmpriv; - //_lock odm_stainfo_lock; - u8 bInterruptMigration; - - u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. - - // Add for dual MAC 0--Mac0 1--Mac1 - u32 interfaceIndex; - - u16 RegRRSR; - - u16 EfuseUsedBytes; - - BOOLEAN EepromOrEfuse; - u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes) - u8 EfuseUsedPercentage; - EFUSE_HAL EfuseHal; - - u8 RTSInitRate; // 2010.11.24.by tynli. -#ifdef CONFIG_P2P - struct P2P_PS_Offload_t p2p_ps_offload; -#endif //CONFIG_P2P -}; - -typedef struct hal_data_8192de HAL_DATA_TYPE, *PHAL_DATA_TYPE; - -// -// Function disabled. -// -#define DF_TX_BIT BIT0 -#define DF_RX_BIT BIT1 -#define DF_IO_BIT BIT2 -#define DF_IO_D3_BIT BIT3 - -#define RT_DF_TYPE u32 -#define RT_DISABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions |= ((RT_DF_TYPE)(__FuncBits))) -#define RT_ENABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions &= (~((RT_DF_TYPE)(__FuncBits)))) -#define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) - -void InterruptRecognized8192DE(struct adapter *Adapter, PRT_ISR_CONTENT pIsrContent); -void UpdateInterruptMask8192DE(struct adapter *Adapter, u32 AddMSR, u32 RemoveMSR); - -//should be renamed and moved to another file -typedef enum _INTERFACE_SELECT_8192DUSB{ - INTF_SEL0_USB = 0, // USB - INTF_SEL1_MINICARD = 1, // Minicard - INTF_SEL2_EKB_PRO = 2, // Eee keyboard proprietary - INTF_SEL3_PRO = 3, // Customized proprietary -} INTERFACE_SELECT_8192DUSB, *PINTERFACE_SELECT_8192DUSB; - -typedef INTERFACE_SELECT_8192DUSB INTERFACE_SELECT_USB; - -struct hal_data_8192du -{ - HAL_VERSION VersionID; - - // add for 92D Phy mode/mac/Band mode - MACPHY_MODE_8192D MacPhyMode92D; - BAND_TYPE CurrentBandType92D; //0:2.4G, 1:5G - BAND_TYPE BandSet92D; - BOOLEAN bIsVS; - - BOOLEAN bNOPG; - - BOOLEAN bSupportRemoteWakeUp; - BOOLEAN bMasterOfDMSP; - BOOLEAN bSlaveOfDMSP; -#ifdef CONFIG_DUALMAC_CONCURRENT - BOOLEAN bInModeSwitchProcess; -#endif - - u16 CustomerID; - - u16 FirmwareVersion; - u16 FirmwareVersionRev; - u16 FirmwareSubVersion; - - //current WIFI_PHY values - u32 ReceiveConfig; - WIRELESS_MODE CurrentWirelessMode; - HT_CHANNEL_WIDTH CurrentChannelBW; - u8 CurrentChannel; - u8 nCur40MhzPrimeSC;// Control channel sub-carrier - u16 BasicRateSet; - - INTERFACE_SELECT_8192DUSB InterfaceSel; - - //rf_ctrl - u8 rf_chip; - u8 rf_type; - u8 NumTotalRFPath; - - // - // EEPROM setting. - // - u8 EEPROMVersion; - u16 EEPROMVID; - u16 EEPROMPID; - u16 EEPROMSVID; - u16 EEPROMSDID; - u8 EEPROMCustomerID; - u8 EEPROMSubCustomerID; - u8 EEPROMRegulatory; - - u8 EEPROMThermalMeter; - - u8 EEPROMC9; - u8 EEPROMCC; - u8 PAMode; - - u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER_2G]; - u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr - u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr - s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff - u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff - // For power group - u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; - u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; - - u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff - - u8 CrystalCap; // CrystalCap. - -#ifdef CONFIG_BT_COEXIST - struct btcoexist_priv bt_coexist; -#endif - - // Read/write are allow for following hardware information variables - u8 framesync; - u32 framesyncC34; - u8 framesyncMonitor; - u8 DefaultInitialGain[4]; - u8 pwrGroupCnt; - u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16]; - u32 CCKTxPowerLevelOriginalOffset; - - u32 AntennaTxPath; // Antenna path Tx - u32 AntennaRxPath; // Antenna path Rx - u8 BluetoothCoexist; - u8 ExternalPA; - u8 InternalPA5G[2]; //pathA / pathB - - //u32 LedControlNum; - //u32 LedControlMode; - //u32 TxPowerTrackControl; - u8 b1x1RecvCombine; // for 1T1R receive combining - - u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo. - - //vivi, for tx power tracking, 20080407 - //u16 TSSI_13dBm; - //u32 Pwr_Track; - // The current Tx Power Level - u8 CurrentCckTxPwrIdx; - u8 CurrentOfdm24GTxPwrIdx; - - BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D - - - u32 RfRegChnlVal[2]; - - - BOOLEAN bPhyValueInitReady; - - BOOLEAN bTXPowerDataReadFromEEPORM; - - BOOLEAN bInSetPower; - - //RDG enable - BOOLEAN bRDGEnable; - - BOOLEAN bLoadIMRandIQKSettingFor2G;// True if IMR or IQK have done for 2.4G in scan progress - BOOLEAN bNeedIQK; - - BOOLEAN bLCKInProgress; - - BOOLEAN bEarlyModeEnable; - -#if 1 - IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; -#else - //regc80、regc94、regc4c、regc88、regc9c、regc14、regca0、regc1c、regc78 - u4Byte IQKMatrixReg[IQK_Matrix_REG_NUM]; - IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; // 1->2G,24->5G 20M channel,21->5G 40M channel. -#endif - - //for host message to fw - u8 LastHMEBoxNum; - - u8 fw_ractrl; - // Beacon function related global variable. - u32 RegBcnCtrlVal; - u8 RegTxPause; - u8 RegFwHwTxQCtrl; - u8 RegReg542; - u8 RegCR_1; - - struct dm_priv dmpriv; - DM_ODM_T odmpriv; - //_lock odm_stainfo_lock; - u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. - - //Query RF by FW - BOOLEAN bReadRFbyFW; - - // For 92C USB endpoint setting - // - - u32 UsbBulkOutSize; - - // Add for dual MAC 0--Mac0 1--Mac1 - u32 interfaceIndex; - - u8 OutEpQueueSel; - u8 OutEpNumber; - -#ifdef CONFIG_USB_TX_AGGREGATION - u8 UsbTxAggMode; - u8 UsbTxAggDescNum; -#endif -#ifdef CONFIG_USB_RX_AGGREGATION - u16 HwRxPageSize; // Hardware setting - u32 MaxUsbRxAggBlock; - - USB_RX_AGG_MODE UsbRxAggMode; - u8 UsbRxAggBlockCount; // USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed - u8 UsbRxAggBlockTimeout; - u8 UsbRxAggPageCount; // 8192C DMA page count - u8 UsbRxAggPageTimeout; -#endif - - u16 RegRRSR; - - u16 EfuseUsedBytes; - - BOOLEAN EepromOrEfuse; - u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes) - u8 EfuseUsedPercentage; - EFUSE_HAL EfuseHal; - - u8 RTSInitRate; // 2010.11.24.by tynli. -#ifdef CONFIG_P2P - struct P2P_PS_Offload_t p2p_ps_offload; -#endif //CONFIG_P2P -}; - -typedef struct hal_data_8192du HAL_DATA_TYPE, *PHAL_DATA_TYPE; - -#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData)) -#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type) - -int FirmwareDownload92D(IN struct adapter *Adapter); -void rtl8192d_FirmwareSelfReset(IN struct adapter *Adapter); -void rtl8192d_ReadChipVersion(IN struct adapter *Adapter); -void rtl8192d_EfuseParseChnlPlan(struct adapter *Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void rtl8192d_ReadTxPowerInfo(struct adapter *Adapter, u8* PROMContent, BOOLEAN AutoLoadFail); -void rtl8192d_ResetDualMacSwitchVariables(IN struct adapter *Adapter); -u8 GetEEPROMSize8192D(struct adapter *Adapter); -BOOLEAN PHY_CheckPowerOffFor8192D(struct adapter *Adapter); -void PHY_SetPowerOnFor8192D(struct adapter *Adapter); -//void PHY_ConfigMacPhyMode92D(struct adapter *Adapter); -void rtl8192d_free_hal_data(struct adapter * padapter); -void rtl8192d_set_hal_ops(struct hal_ops *pHalFunc); -#endif diff --git a/include/rtl8192d_led.h b/include/rtl8192d_led.h deleted file mode 100755 index e072631..0000000 --- a/include/rtl8192d_led.h +++ /dev/null @@ -1,34 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __RTL8192D_LED_H_ -#define __RTL8192D_LED_H_ - -#include -#include -#include - - -//================================================================================ -// Interface to manipulate LED objects. -//================================================================================ -void rtl8192du_InitSwLeds(struct adapter *padapter); -void rtl8192du_DeInitSwLeds(struct adapter *padapter); - -#endif diff --git a/include/rtl8192d_recv.h b/include/rtl8192d_recv.h deleted file mode 100755 index ee72e44..0000000 --- a/include/rtl8192d_recv.h +++ /dev/null @@ -1,93 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef _RTL8192D_RECV_H_ -#define _RTL8192D_RECV_H_ - -#include -#include -#include - - -#ifdef CONFIG_SINGLE_RECV_BUF - #define NR_RECVBUFF (1) -#else - #define NR_RECVBUFF (4) -#endif //CONFIG_SINGLE_RECV_BUF -#define NR_PREALLOC_RECV_SKB (8) - -#define RECV_BLK_SZ 512 -#define RECV_BLK_CNT 16 -#define RECV_BLK_TH RECV_BLK_CNT - -#ifndef CONFIG_MINIMAL_MEMORY_USAGE - #ifdef CONFIG_PLATFORM_MSTAR - #define MAX_RECVBUF_SZ (8192) // 8K - #else - #define MAX_RECVBUF_SZ (15360) // 15k < 16k - #endif -#else - #define MAX_RECVBUF_SZ (4000) // about 4K -#endif - -#define RECV_BULK_IN_ADDR 0x80 -#define RECV_INT_IN_ADDR 0x81 - -#define PHY_RSSI_SLID_WIN_MAX 100 -#define PHY_LINKQUALITY_SLID_WIN_MAX 20 - -struct phy_stat { - unsigned int phydw0; - - unsigned int phydw1; - - unsigned int phydw2; - - unsigned int phydw3; - - unsigned int phydw4; - - unsigned int phydw5; - - unsigned int phydw6; - - unsigned int phydw7; -}; - -// Rx smooth factor -#define Rx_Smooth_Factor (20) - -typedef struct _INTERRUPT_MSG_FORMAT_EX{ - unsigned int C2H_MSG0; - unsigned int C2H_MSG1; - unsigned int C2H_MSG2; - unsigned int C2H_MSG3; - unsigned int HISR; // from HISR Reg0x124, read to clear - unsigned int HISRE;// from HISRE Reg0x12c, read to clear - unsigned int MSG_EX; -}INTERRUPT_MSG_FORMAT_EX,*PINTERRUPT_MSG_FORMAT_EX; - -void rtl8192du_init_recvbuf(struct adapter *padapter, struct recv_buf *precvbuf); -int rtl8192du_init_recv_priv(struct adapter * padapter); -void rtl8192du_free_recv_priv(struct adapter * padapter); - -void rtl8192d_translate_rx_signal_stuff(union recv_frame *precvframe, struct phy_stat *pphy_status); -void rtl8192d_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *pdesc); - -#endif diff --git a/include/rtl8192d_rf.h b/include/rtl8192d_rf.h deleted file mode 100755 index b6505d2..0000000 --- a/include/rtl8192d_rf.h +++ /dev/null @@ -1,96 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -/****************************************************************************** - * - * - * Module: rtl8192d_rf.h ( Header File) - * - * Note: Collect every HAL RF type exter API or constant. - * - * Function: - * - * Export: - * - * Abbrev: - * - * History: - * Data Who Remark - * - * 09/25/2008 MHC Create initial version. - * - * -******************************************************************************/ -#ifndef _RTL8192D_RF_H_ -#define _RTL8192D_RF_H_ -/* Check to see if the file has been included already. */ - - -/*--------------------------Define Parameters-------------------------------*/ - -// -// For RF 6052 Series -// -#define RF6052_MAX_TX_PWR 0x3F -#define RF6052_MAX_REG 0x3F -#define RF6052_MAX_PATH 2 -/*--------------------------Define Parameters-------------------------------*/ - - -/*------------------------------Define structure----------------------------*/ - -/*------------------------------Define structure----------------------------*/ - - -/*------------------------Export global variable----------------------------*/ -/*------------------------Export global variable----------------------------*/ - -/*------------------------Export Marco Definition---------------------------*/ - -/*------------------------Export Marco Definition---------------------------*/ - - -/*--------------------------Exported Function prototype---------------------*/ - -// -// RF RL6052 Series API -// -void rtl8192d_RF_ChangeTxPath( IN struct adapter *Adapter, - IN u16 DataRate); -void rtl8192d_PHY_RF6052SetBandwidth( - IN struct adapter * Adapter, - IN HT_CHANNEL_WIDTH Bandwidth); -void rtl8192d_PHY_RF6052SetCckTxPower( - IN struct adapter *Adapter, - IN u8* pPowerlevel); -void rtl8192d_PHY_RF6052SetOFDMTxPower( - IN struct adapter *Adapter, - IN u8* pPowerLevel, - IN u8 Channel); -int PHY_RF6052_Config8192D( IN struct adapter * Adapter ); - -BOOLEAN rtl8192d_PHY_EnableAnotherPHY(IN struct adapter *Adapter, IN BOOLEAN bMac0); - -void rtl8192d_PHY_PowerDownAnotherPHY(IN struct adapter *Adapter, IN BOOLEAN bMac0); - - -/*--------------------------Exported Function prototype---------------------*/ - - -#endif/* End of HalRf.h */ diff --git a/include/rtl8192d_spec.h b/include/rtl8192d_spec.h deleted file mode 100755 index 7173377..0000000 --- a/include/rtl8192d_spec.h +++ /dev/null @@ -1,1650 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __RTL8192D_SPEC_H__ -#define __RTL8192D_SPEC_H__ - -#include - -//============================================================ -// 8192D Regsiter offset definition -//============================================================ - - -//============================================================ -// -//============================================================ - -//----------------------------------------------------- -// -// 0x0000h ~ 0x00FFh System Configuration -// -//----------------------------------------------------- -#define REG_SYS_ISO_CTRL 0x0000 -#define REG_SYS_FUNC_EN 0x0002 -#define REG_APS_FSMCO 0x0004 -#define REG_SYS_CLKR 0x0008 -#define REG_9346CR 0x000A -#define REG_EE_VPD 0x000C -#define REG_AFE_MISC 0x0010 -#define REG_SPS0_CTRL 0x0011 -#define REG_POWER_OFF_IN_PROCESS 0x0017 -#define REG_SPS_OCP_CFG 0x0018 -#define REG_RSV_CTRL 0x001C -#define REG_RF_CTRL 0x001F -#define REG_LDOA15_CTRL 0x0020 -#define REG_LDOV12D_CTRL 0x0021 -#define REG_LDOHCI12_CTRL 0x0022 -#define REG_LPLDO_CTRL 0x0023 -#define REG_AFE_XTAL_CTRL 0x0024 -#define REG_AFE_PLL_CTRL 0x0028 -#define REG_MAC_PHY_CTRL 0x002c //for 92d, DMDP,SMSP,DMSP contrl -#define REG_EFUSE_CTRL 0x0030 -#define REG_EFUSE_TEST 0x0034 -#define REG_PWR_DATA 0x0038 -#define REG_CAL_TIMER 0x003C -#define REG_ACLK_MON 0x003E -#define REG_GPIO_MUXCFG 0x0040 -//#define REG_GPIO_MUXCFG 0x0041 -#define REG_GPIO_IO_SEL 0x0042 -#define REG_MAC_PINMUX_CFG 0x0043 -#define REG_GPIO_PIN_CTRL 0x0044 -#define REG_GPIO_INTM 0x0048 -#define REG_LEDCFG0 0x004C -#define REG_LEDCFG1 0x004D -#define REG_LEDCFG2 0x004E -#define REG_LEDCFG3 0x004F -#define REG_FSIMR 0x0050 -#define REG_FSISR 0x0054 - -#define REG_MCUFWDL 0x0080 - -#define REG_HMEBOX_EXT_0 0x0088 -#define REG_HMEBOX_EXT_1 0x008A -#define REG_HMEBOX_EXT_2 0x008C -#define REG_HMEBOX_EXT_3 0x008E - -#define REG_BIST_SCAN 0x00D0 -#define REG_BIST_RPT 0x00D4 -#define REG_BIST_ROM_RPT 0x00D8 -#define REG_USB_SIE_INTF 0x00E0 -#define REG_PCIE_MIO_INTF 0x00E4 -#define REG_PCIE_MIO_INTD 0x00E8 -#define REG_HPON_FSM 0x00EC -#define REG_SYS_CFG 0x00F0 -#define REG_MAC_PHY_CTRL_NORMAL 0x00f8 - -#define REG_MAC0 0x0081 -#define REG_MAC1 0x0053 -#define FW_MAC0_ready 0x18 -#define FW_MAC1_ready 0x1A -#define MAC0_ON BIT7 -#define MAC1_ON BIT0 -#define mac0_ready BIT0 -#define mac1_ready BIT0 - - -//----------------------------------------------------- -// -// 0x0100h ~ 0x01FFh MACTOP General Configuration -// -//----------------------------------------------------- -#define REG_CR 0x0100 -#define REG_PBP 0x0104 -#define REG_TRXDMA_CTRL 0x010C -#define REG_TRXFF_BNDY 0x0114 -#define REG_TRXFF_STATUS 0x0118 -#define REG_RXFF_PTR 0x011C -#define REG_HIMR 0x0120 -#define REG_HISR 0x0124 -#define REG_HIMRE 0x0128 -#define REG_HISRE 0x012C -#define REG_CPWM 0x012F -#define REG_FWIMR 0x0130 -#define REG_FWISR 0x0134 -#define REG_FTIMR 0x0138 -#define REG_PKTBUF_DBG_CTRL 0x0140 -#define REG_PKTBUF_DBG_DATA_L 0x0144 -#define REG_PKTBUF_DBG_DATA_H 0x0148 - -#define REG_TC0_CTRL 0x0150 -#define REG_TC1_CTRL 0x0154 -#define REG_TC2_CTRL 0x0158 -#define REG_TC3_CTRL 0x015C -#define REG_TC4_CTRL 0x0160 -#define REG_TCUNIT_BASE 0x0164 -#define REG_MBIST_START 0x0174 -#define REG_MBIST_DONE 0x0178 -#define REG_MBIST_FAIL 0x017C -#define REG_C2HEVT_MSG_NORMAL 0x01A0 -#define REG_C2HEVT_CLEAR 0x01AF -#define REG_C2HEVT_MSG_TEST 0x01B8 -#define REG_MCUTST_1 0x01c0 -#define REG_FMETHR 0x01C8 -#define REG_HMETFR 0x01CC -#define REG_HMEBOX_0 0x01D0 -#define REG_HMEBOX_1 0x01D4 -#define REG_HMEBOX_2 0x01D8 -#define REG_HMEBOX_3 0x01DC - -#define REG_LLT_INIT 0x01E0 -#define REG_BB_ACCEESS_CTRL 0x01E8 -#define REG_BB_ACCESS_DATA 0x01EC - - -//----------------------------------------------------- -// -// 0x0200h ~ 0x027Fh TXDMA Configuration -// -//----------------------------------------------------- -#define REG_RQPN 0x0200 -#define REG_FIFOPAGE 0x0204 -#define REG_TDECTRL 0x0208 -#define REG_TXDMA_OFFSET_CHK 0x020C -#define REG_TXDMA_STATUS 0x0210 -#define REG_RQPN_NPQ 0x0214 - -//----------------------------------------------------- -// -// 0x0280h ~ 0x02FFh RXDMA Configuration -// -//----------------------------------------------------- -#define REG_RXDMA_AGG_PG_TH 0x0280 -#define REG_RXPKT_NUM 0x0284 -#define REG_RXDMA_STATUS 0x0288 - - -//----------------------------------------------------- -// -// 0x0300h ~ 0x03FFh PCIe -// -//----------------------------------------------------- -#define REG_PCIE_CTRL_REG 0x0300 -#define REG_INT_MIG 0x0304 // Interrupt Migration -#define REG_BCNQ_DESA 0x0308 // TX Beacon Descriptor Address -#define REG_HQ_DESA 0x0310 // TX High Queue Descriptor Address -#define REG_MGQ_DESA 0x0318 // TX Manage Queue Descriptor Address -#define REG_VOQ_DESA 0x0320 // TX VO Queue Descriptor Address -#define REG_VIQ_DESA 0x0328 // TX VI Queue Descriptor Address -#define REG_BEQ_DESA 0x0330 // TX BE Queue Descriptor Address -#define REG_BKQ_DESA 0x0338 // TX BK Queue Descriptor Address -#define REG_RX_DESA 0x0340 // RX Queue Descriptor Address -#define REG_DBI 0x0348 // Backdoor REG for Access Configuration -//sherry added for DBI Read/Write 20091126 -#define REG_DBI_WDATA 0x0348 // Backdoor REG for Access Configuration -#define REG_DBI_RDATA 0x034C //Backdoor REG for Access Configuration -#define REG_DBI_CTRL 0x0350 //Backdoor REG for Access Configuration -#define REG_DBI_FLAG 0x0352 //Backdoor REG for Access Configuration#define REG_MDIO 0x0354 // MDIO for Access PCIE PHY -#define REG_MDIO 0x0354 // MDIO for Access PCIE PHY -#define REG_DBG_SEL 0x0360 // Debug Selection Register -#define REG_PCIE_HRPWM 0x0361 //PCIe RPWM -#define REG_PCIE_HCPWM 0x0363 //PCIe CPWM -#define REG_UART_CTRL 0x0364 // UART Control -#define REG_UART_TX_DESA 0x0370 // UART TX Descriptor Address -#define REG_UART_RX_DESA 0x0378 // UART Rx Descriptor Address - - -// spec version 11 -//----------------------------------------------------- -// -// 0x0400h ~ 0x047Fh Protocol Configuration -// -//----------------------------------------------------- -#define REG_VOQ_INFORMATION 0x0400 -#define REG_VIQ_INFORMATION 0x0404 -#define REG_BEQ_INFORMATION 0x0408 -#define REG_BKQ_INFORMATION 0x040C -#define REG_MGQ_INFORMATION 0x0410 -#define REG_HGQ_INFORMATION 0x0414 -#define REG_BCNQ_INFORMATION 0x0418 - - -#define REG_CPU_MGQ_INFORMATION 0x041C -#define REG_FWHW_TXQ_CTRL 0x0420 -#define REG_HWSEQ_CTRL 0x0423 -#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 -#define REG_TXPKTBUF_MGQ_BDNY 0x0425 -#define REG_LIFETIME_EN 0x0426 -#define REG_MULTI_BCNQ_OFFSET 0x0427 -#define REG_SPEC_SIFS 0x0428 -#define REG_RL 0x042A -#define REG_DARFRC 0x0430 -#define REG_RARFRC 0x0438 -#define REG_RRSR 0x0440 -#define REG_ARFR0 0x0444 -#define REG_ARFR1 0x0448 -#define REG_ARFR2 0x044C -#define REG_ARFR3 0x0450 -#define REG_AGGLEN_LMT 0x0458 -#define REG_AMPDU_MIN_SPACE 0x045C -#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D -#define REG_FAST_EDCA_CTRL 0x0460 -#define REG_RD_RESP_PKT_TH 0x0463 -#define REG_INIRTS_RATE_SEL 0x0480 -#define REG_INIDATA_RATE_SEL 0x0484 - -#define REG_FW_TSF_SYNC_CNT 0x04A0 -#define REG_FW_BCN_DIS_CNT 0x04A1 - -#define REG_POWER_STATUS 0x04A4 -#define REG_POWER_STAGE1 0x04B4 -#define REG_POWER_STAGE2 0x04B8 -#define REG_PKT_VO_VI_LIFE_TIME 0x04C0 -#define REG_PKT_BE_BK_LIFE_TIME 0x04C2 -#define REG_STBC_SETTING 0x04C4 -#define REG_PROT_MODE_CTRL 0x04C8 -#define REG_MAX_AGGR_NUM 0x04CA -#define REG_RTS_MAX_AGGR_NUM 0x04CB -#define REG_BAR_MODE_CTRL 0x04CC -#define REG_RA_TRY_RATE_AGG_LMT 0x04CF -#define REG_EARLY_MODE_CONTROL 0x04D0 -#define REG_NQOS_SEQ 0x04DC -#define REG_QOS_SEQ 0x04DE -#define REG_NEED_CPU_HANDLE 0x04E0 -#define REG_PKT_LOSE_RPT 0x04E1 -#define REG_PTCL_ERR_STATUS 0x04E2 -#define REG_DUMMY 0x04FC - - - -//----------------------------------------------------- -// -// 0x0500h ~ 0x05FFh EDCA Configuration -// -//----------------------------------------------------- -#define REG_EDCA_VO_PARAM 0x0500 -#define REG_EDCA_VI_PARAM 0x0504 -#define REG_EDCA_BE_PARAM 0x0508 -#define REG_EDCA_BK_PARAM 0x050C -#define REG_BCNTCFG 0x0510 -#define REG_PIFS 0x0512 -#define REG_RDG_PIFS 0x0513 -#define REG_SIFS_CTX 0x0514 -#define REG_SIFS_TRX 0x0516 -#define REG_TSFTR_SYN_OFFSET 0x0518 -#define REG_AGGR_BREAK_TIME 0x051A -#define REG_SLOT 0x051B -#define REG_TX_PTCL_CTRL 0x0520 -#define REG_TXPAUSE 0x0522 -#define REG_DIS_TXREQ_CLR 0x0523 -#define REG_RD_CTRL 0x0524 -#define REG_TBTT_PROHIBIT 0x0540 -#define REG_RD_NAV_NXT 0x0544 -#define REG_NAV_PROT_LEN 0x0546 -#define REG_BCN_CTRL 0x0550 -#define REG_BCN_CTRL_1 0x0551 -#define REG_MBID_NUM 0x0552 -#define REG_DUAL_TSF_RST 0x0553 -#define REG_BCN_INTERVAL 0x0554 // The same as REG_MBSSID_BCN_SPACE -#define REG_MBSSID_BCN_SPACE 0x0554 -#define REG_DRVERLYINT 0x0558 -#define REG_BCNDMATIM 0x0559 -#define REG_ATIMWND 0x055A -#define REG_USTIME_TSF 0x055C -#define REG_BCN_MAX_ERR 0x055D -#define REG_RXTSF_OFFSET_CCK 0x055E -#define REG_RXTSF_OFFSET_OFDM 0x055F -#define REG_TSFTR 0x0560 -#define REG_TSFTR1 0x0568 -#define REG_INIT_TSFTR 0x0564 -#define REG_ATIMWND_1 0x0570 -#define REG_PSTIMER 0x0580 -#define REG_TIMER0 0x0584 -#define REG_TIMER1 0x0588 -#define REG_ACMHWCTRL 0x05C0 -#define REG_ACMRSTCTRL 0x05C1 -#define REG_ACMAVG 0x05C2 -#define REG_VO_ADMTIME 0x05C4 -#define REG_VI_ADMTIME 0x05C6 -#define REG_BE_ADMTIME 0x05C8 -#define REG_EDCA_RANDOM_GEN 0x05CC -#define REG_SCH_TXCMD 0x05D0 - -#define REG_DMC 0x05F0 //Dual MAC Co-Existence Register - - -//----------------------------------------------------- -// -// 0x0600h ~ 0x07FFh WMAC Configuration -// -//----------------------------------------------------- -#define REG_APSD_CTRL 0x0600 -#define REG_BWOPMODE 0x0603 -#define REG_TCR 0x0604 -#define REG_RCR 0x0608 -#define REG_RX_PKT_LIMIT 0x060C -#define REG_RX_DLK_TIME 0x060D -#define REG_RX_DRVINFO_SZ 0x060F - -#define REG_MACID 0x0610 -#define REG_BSSID 0x0618 -#define REG_MAR 0x0620 -#define REG_MBIDCAMCFG 0x0628 - -#define REG_USTIME_EDCA 0x0638 -#define REG_MAC_SPEC_SIFS 0x063A -#define REG_RESP_SIFS_CCK 0x063C -#define REG_RESP_SIFS_OFDM 0x063E -#define REG_ACKTO 0x0640 -#define REG_CTS2TO 0x0641 -#define REG_EIFS 0x0642 - - -//WMA, BA, CCX -#define REG_NAV_CTRL 0x0650 -#define REG_BACAMCMD 0x0654 -#define REG_BACAMCONTENT 0x0658 -#define REG_LBDLY 0x0660 -#define REG_FWDLY 0x0661 -#define REG_RXERR_RPT 0x0664 -#define REG_WMAC_TRXPTCL_CTL 0x0668 - - -// Security -#define REG_CAMCMD 0x0670 -#define REG_CAMWRITE 0x0674 -#define REG_CAMREAD 0x0678 -#define REG_CAMDBG 0x067C -#define REG_SECCFG 0x0680 - -// Power -#define REG_WOW_CTRL 0x0690 -#define REG_PSSTATUS 0x0691 -#define REG_PS_RX_INFO 0x0692 -#define REG_LPNAV_CTRL 0x0694 -#define REG_WKFMCAM_CMD 0x0698 -#define REG_WKFMCAM_RWD 0x069C -#define REG_RXFLTMAP0 0x06A0 -#define REG_RXFLTMAP1 0x06A2 -#define REG_RXFLTMAP2 0x06A4 -#define REG_BCN_PSR_RPT 0x06A8 -#define REG_CALB32K_CTRL 0x06AC -#define REG_PKT_MON_CTRL 0x06B4 -#define REG_BT_COEX_TABLE 0x06C0 -#define REG_WMAC_RESP_TXINFO 0x06D8 - -#define REG_MACID1 0x0700 -#define REG_BSSID1 0x0708 - -//----------------------------------------------------- -// -// 0xFE00h ~ 0xFE55h USB Configuration -// -//----------------------------------------------------- -#define REG_USB_INFO 0xFE17 -#define REG_USB_SPECIAL_OPTION 0xFE55 -#define REG_USB_DMA_AGG_TO 0xFE5B -#define REG_USB_AGG_TO 0xFE5C -#define REG_USB_AGG_TH 0xFE5D - -// for 92DU high_Queue low_Queue Normal_Queue select -#define REG_USB_High_NORMAL_Queue_Select_MAC0 0xFE44 -//#define REG_USB_LOW_Queue_Select_MAC0 0xFE45 -#define REG_USB_High_NORMAL_Queue_Select_MAC1 0xFE47 -//#define REG_USB_LOW_Queue_Select_MAC1 0xFE48 - -// For test chip -#define REG_TEST_USB_TXQS 0xFE48 -#define REG_TEST_SIE_VID 0xFE60 // 0xFE60~0xFE61 -#define REG_TEST_SIE_PID 0xFE62 // 0xFE62~0xFE63 -#define REG_TEST_SIE_OPTIONAL 0xFE64 -#define REG_TEST_SIE_CHIRP_K 0xFE65 -#define REG_TEST_SIE_PHY 0xFE66 // 0xFE66~0xFE6B -#define REG_TEST_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75 -#define REG_TEST_SIE_STRING 0xFE80 // 0xFE80~0xFEB9 - - -// For normal chip -#define REG_NORMAL_SIE_VID 0xFE60 // 0xFE60~0xFE61 -#define REG_NORMAL_SIE_PID 0xFE62 // 0xFE62~0xFE63 -#define REG_NORMAL_SIE_OPTIONAL 0xFE64 -#define REG_NORMAL_SIE_EP 0xFE65 // 0xFE65~0xFE67 -#define REG_NORMAL_SIE_PHY 0xFE68 // 0xFE68~0xFE6B -#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75 -#define REG_NORMAL_SIE_STRING 0xFE80 // 0xFE80~0xFEDF - - -//----------------------------------------------------- -// -// Redifine 8192C register definition for compatibility -// -//----------------------------------------------------- - -// TODO: use these definition when using REG_xxx naming rule. -// NOTE: DO NOT Remove these definition. Use later. - -#define SYS_ISO_CTRL REG_SYS_ISO_CTRL // System Isolation Interface Control. -#define SYS_FUNC_EN REG_SYS_FUNC_EN // System Function Enable. -#define SYS_CLK REG_SYS_CLKR -#define CR9346 REG_9346CR // 93C46/93C56 Command Register. -#define EFUSE_CTRL REG_EFUSE_CTRL // E-Fuse Control. -#define EFUSE_TEST REG_EFUSE_TEST // E-Fuse Test. -#define MSR (REG_CR + 2) // Media Status register -#define ISR REG_HISR -#define TSFR REG_TSFTR // Timing Sync Function Timer Register. - -#define MACIDR0 REG_MACID // MAC ID Register, Offset 0x0050-0x0053 -#define MACIDR4 (REG_MACID + 4) // MAC ID Register, Offset 0x0054-0x0055 - -#define PBP REG_PBP - -// Redifine MACID register, to compatible prior ICs. -#define IDR0 MACIDR0 -#define IDR4 MACIDR4 - - -// -// 9. Security Control Registers (Offset: ) -// -#define RWCAM REG_CAMCMD //IN 8190 Data Sheet is called CAMcmd -#define WCAMI REG_CAMWRITE // Software write CAM input content -#define RCAMO REG_CAMREAD // Software read/write CAM config -#define CAMDBG REG_CAMDBG -#define SECR REG_SECCFG //Security Configuration Register - -// Unused register -#define UnusedRegister 0x1BF -#define DCAM UnusedRegister -#define PSR UnusedRegister -#define BBAddr UnusedRegister -#define PhyDataR UnusedRegister - -#define InvalidBBRFValue 0x12345678 - -// Min Spacing related settings. -#define MAX_MSS_DENSITY_2T 0x13 -#define MAX_MSS_DENSITY_1T 0x0A - -//---------------------------------------------------------------------------- -// 8192C Cmd9346CR bits (Offset 0xA, 16bit) -//---------------------------------------------------------------------------- -#define CmdEEPROM_En BIT5 // EEPROM enable when set 1 -#define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 -#define Cmd9346CR_9356SEL BIT4 -#define AutoLoadEEPROM (CmdEEPROM_En|CmdEERPOMSEL) -#define AutoLoadEFUSE CmdEEPROM_En - -// 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) -//---------------------------------------------------------------------------- -#define GPIOSEL_GPIO 0 -#define GPIOSEL_ENBT BIT5 - -//---------------------------------------------------------------------------- -// 8192C GPIO PIN Control Register (offset 0x44, 4 byte) -//---------------------------------------------------------------------------- -#define GPIO_IN REG_GPIO_PIN_CTRL // GPIO pins input value -#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) // GPIO pins output value -#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. -#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) - - -//---------------------------------------------------------------------------- -// 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) -//---------------------------------------------------------------------------- -/* -Network Type -00: No link -01: Link in ad hoc network -10: Link in infrastructure network -11: AP mode -Default: 00b. -*/ -#define MSR_NOLINK 0x00 -#define MSR_ADHOC 0x01 -#define MSR_INFRA 0x02 -#define MSR_AP 0x03 - -// -// 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) -// -//---------------------------------------------------------------------------- -// 8192C Response Rate Set Register (offset 0x181, 24bits) -//---------------------------------------------------------------------------- -#define RRSR_RSC_OFFSET 21 -#define RRSR_SHORT_OFFSET 23 -#define RRSR_RSC_BW_40M 0x600000 -#define RRSR_RSC_UPSUBCHNL 0x400000 -#define RRSR_RSC_LOWSUBCHNL 0x200000 -#define RRSR_SHORT 0x800000 -#define RRSR_1M BIT0 -#define RRSR_2M BIT1 -#define RRSR_5_5M BIT2 -#define RRSR_11M BIT3 -#define RRSR_6M BIT4 -#define RRSR_9M BIT5 -#define RRSR_12M BIT6 -#define RRSR_18M BIT7 -#define RRSR_24M BIT8 -#define RRSR_36M BIT9 -#define RRSR_48M BIT10 -#define RRSR_54M BIT11 -#define RRSR_MCS0 BIT12 -#define RRSR_MCS1 BIT13 -#define RRSR_MCS2 BIT14 -#define RRSR_MCS3 BIT15 -#define RRSR_MCS4 BIT16 -#define RRSR_MCS5 BIT17 -#define RRSR_MCS6 BIT18 -#define RRSR_MCS7 BIT19 -#define BRSR_AckShortPmb BIT23 -// CCK ACK: use Short Preamble or not - -//---------------------------------------------------------------------------- -// 8192C BW_OPMODE bits (Offset 0x203, 8bit) -//---------------------------------------------------------------------------- -#define BW_OPMODE_20MHZ BIT2 -#define BW_OPMODE_5G BIT1 -#define BW_OPMODE_11J BIT0 - - -//---------------------------------------------------------------------------- -// 8192C CAM Config Setting (offset 0x250, 1 byte) -//---------------------------------------------------------------------------- -#define CAM_VALID BIT15 -#define CAM_NOTVALID 0x0000 -#define CAM_USEDK BIT5 - -#define CAM_CONTENT_COUNT 8 - -#define CAM_NONE 0x0 -#define CAM_WEP40 0x01 -#define CAM_TKIP 0x02 -#define CAM_AES 0x04 -#define CAM_WEP104 0x05 -#define CAM_SMS4 0x6 - - -#define TOTAL_CAM_ENTRY 32 -#define HALF_CAM_ENTRY 16 - -#define CAM_CONFIG_USEDK true -#define CAM_CONFIG_NO_USEDK false - -#define CAM_WRITE BIT16 -#define CAM_READ 0x00000000 -#define CAM_POLLINIG BIT31 - -#define SCR_UseDK 0x01 -#define SCR_TxSecEnable 0x02 -#define SCR_RxSecEnable 0x04 - - -// -// 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) -// -//---------------------------------------------------------------------------- -// 8190 IMR/ISR bits (offset 0xfd, 8bits) -//---------------------------------------------------------------------------- -#define IMR8190_DISABLED 0x0 -// IMR DW0 Bit 0-31 -#define IMR_BCNDMAINT6 BIT31 // Beacon DMA Interrupt 6 -#define IMR_BCNDMAINT5 BIT30 // Beacon DMA Interrupt 5 -#define IMR_BCNDMAINT4 BIT29 // Beacon DMA Interrupt 4 -#define IMR_BCNDMAINT3 BIT28 // Beacon DMA Interrupt 3 -#define IMR_BCNDMAINT2 BIT27 // Beacon DMA Interrupt 2 -#define IMR_BCNDMAINT1 BIT26 // Beacon DMA Interrupt 1 -#define IMR_BCNDOK8 BIT25 // Beacon Queue DMA OK Interrup 8 -#define IMR_BCNDOK7 BIT24 // Beacon Queue DMA OK Interrup 7 -#define IMR_BCNDOK6 BIT23 // Beacon Queue DMA OK Interrup 6 -#define IMR_BCNDOK5 BIT22 // Beacon Queue DMA OK Interrup 5 -#define IMR_BCNDOK4 BIT21 // Beacon Queue DMA OK Interrup 4 -#define IMR_BCNDOK3 BIT20 // Beacon Queue DMA OK Interrup 3 -#define IMR_BCNDOK2 BIT19 // Beacon Queue DMA OK Interrup 2 -#define IMR_BCNDOK1 BIT18 // Beacon Queue DMA OK Interrup 1 -#define IMR_TIMEOUT2 BIT17 // Timeout interrupt 2 -#define IMR_TIMEOUT1 BIT16 // Timeout interrupt 1 -#define IMR_TXFOVW BIT15 // Transmit FIFO Overflow -#define IMR_PSTIMEOUT BIT14 // Power save time out interrupt -#define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0 -#define IMR_RXFOVW BIT12 // Receive FIFO Overflow -#define IMR_RDU BIT11 // Receive Descriptor Unavailable -#define IMR_ATIMEND BIT10 // For 92C,ATIM Window End Interrupt -#define IMR_BDOK BIT9 // Beacon Queue DMA OK Interrup -#define IMR_HIGHDOK BIT8 // High Queue DMA OK Interrupt -#define IMR_TBDOK BIT7 // Transmit Beacon OK interrup -#define IMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt -#define IMR_TBDER BIT5 // For 92C,Transmit Beacon Error Interrupt -#define IMR_BKDOK BIT4 // AC_BK DMA OK Interrupt -#define IMR_BEDOK BIT3 // AC_BE DMA OK Interrupt -#define IMR_VIDOK BIT2 // AC_VI DMA OK Interrupt -#define IMR_VODOK BIT1 // AC_VO DMA Interrupt -#define IMR_ROK BIT0 // Receive DMA OK Interrupt - -// 13. Host Interrupt Status Extension Register (Offset: 0x012C-012Eh) -#define IMR_TXERR BIT11 -#define IMR_RXERR BIT10 -#define IMR_C2HCMD BIT9 -#define IMR_CPWM BIT8 -//RSVD [2-7] -#define IMR_OCPINT BIT1 -#define IMR_WLANOFF BIT0 - - - -//---------------------------------------------------------------------------- -// 8192D EFUSE -//---------------------------------------------------------------------------- -#define HWSET_MAX_SIZE 256 - -//---------------------------------------------------------------------------- -// 8192C EEPROM/EFUSE share register definition. -//---------------------------------------------------------------------------- - -// -// Default Value for EEPROM or EFUSE!!! -// -#define EEPROM_Default_TSSI 0x0 -#define EEPROM_Default_TxPowerDiff 0x0 -#define EEPROM_Default_CrystalCap 0x0 //92D default 0x0 -#define EEPROM_Default_BoardType 0x02 // Default: 2X2, RTL8192CE(QFPN68) -#define EEPROM_Default_TxPower 0x1010 -#define EEPROM_Default_HT2T_TxPwr 0x10 - -#define EEPROM_Default_LegacyHTTxPowerDiff 0x4 -#define EEPROM_Default_ThermalMeter 0x12 - -#define EEPROM_Default_AntTxPowerDiff 0x0 -//#define EEPROM_Default_TxPwDiff_CrystalCap 0x5 -#define EEPROM_Default_TxPowerLevel_2G 0x2C -#define EEPROM_Default_TxPowerLevel_5G 0x22 - -#define EEPROM_Default_HT40_2SDiff 0x0 -#define EEPROM_Default_HT20_Diff 2 // HT20<->40 default Tx Power Index Difference -#define EEPROM_Default_LegacyHTTxPowerDiff 0x4 //OFDM Tx Power index diff -#define EEPROM_Default_HT40_PwrMaxOffset 0 -#define EEPROM_Default_HT20_PwrMaxOffset 0 - -// For debug -#define EEPROM_Default_PID 0x1234 -#define EEPROM_Default_VID 0x5678 -#define EEPROM_Default_CustomerID 0xAB -#define EEPROM_Default_SubCustomerID 0xCD -#define EEPROM_Default_Version 0 - -#define EEPROM_Default_externalPA_C9 0x00 -#define EEPROM_Default_externalPA_CC 0xFF -#define EEPROM_Default_internalPA_SP3T_C9 0xAA -#define EEPROM_Default_internalPA_SP3T_CC 0xAF -#define EEPROM_Default_internalPA_SPDT_C9 0xAA -#define EEPROM_Default_internalPA_SPDT_CC 0xFA - -#define EEPROM_CHANNEL_PLAN_FCC 0x0 -#define EEPROM_CHANNEL_PLAN_IC 0x1 -#define EEPROM_CHANNEL_PLAN_ETSI 0x2 -#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 -#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 -#define EEPROM_CHANNEL_PLAN_MKK 0x5 -#define EEPROM_CHANNEL_PLAN_MKK1 0x6 -#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 -#define EEPROM_CHANNEL_PLAN_TELEC 0x8 -#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 -#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA -#define EEPROM_CHANNEL_PLAN_NCC 0xB -#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 - - -#define EEPROM_CID_DEFAULT 0x0 -#define EEPROM_CID_TOSHIBA 0x4 -#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25. -#define EEPROM_CID_QMI 0x0D -#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108 - - -#define RTL8192_EEPROM_ID 0x8129 -#define EEPROM_WAPI_SUPPORT 0x78 - -#define RTL8190_EEPROM_ID 0x8129 // 0-1 -#define EEPROM_HPON 0x02 // LDO settings.2-5 -#define EEPROM_CLK 0x06 // Clock settings.6-7 -#define EEPROM_MAC_FUNCTION 0x08 // SE Test mode.8 - -#define EEPROM_VID 0xC // SE Vendor ID.A-B -#define EEPROM_PID 0xE // SE Device ID. C-D -#define EEPROM_ENDPOINT_SETTING 0x10 -#define EEPROM_CHIRP_K 0x12 // Changed -#define EEPROM_USB_PHY 0x13 // Changed -#define EEPROM_NORMAL_BoardType EEPROM_RF_OPT1 //[7:5] -#define EEPROM_MAC_ADDR 0x16 // SEMAC Address. 12-17 -#define EEPROM_STRING 0x1F -#define EEPROM_SUBCUSTOMER_ID 0x59 - -#define EEPROM_MAC_ADDR_MAC0_92D 0x19 -#define EEPROM_MAC_ADDR_MAC1_92D 0x5B -//---------------------------------------------------------------- -// 2.4G band Tx power index setting -#define EEPROM_CCK_TX_PWR_INX_2G 0x61 -#define EEPROM_HT40_1S_TX_PWR_INX_2G 0x67 -#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G 0x6D -#define EEPROM_HT20_TX_PWR_INX_DIFF_2G 0x70 -#define EEPROM_OFDM_TX_PWR_INX_DIFF_2G 0x73 -#define EEPROM_HT40_MAX_PWR_OFFSET_2G 0x76 -#define EEPROM_HT20_MAX_PWR_OFFSET_2G 0x79 - -//5GL channel 32-64 -#define EEPROM_HT40_1S_TX_PWR_INX_5GL 0x7C -#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GL 0x82 -#define EEPROM_HT20_TX_PWR_INX_DIFF_5GL 0x85 -#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GL 0x88 -#define EEPROM_HT40_MAX_PWR_OFFSET_5GL 0x8B -#define EEPROM_HT20_MAX_PWR_OFFSET_5GL 0x8E - -//5GM channel 100-140 -#define EEPROM_HT40_1S_TX_PWR_INX_5GM 0x91 -#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GM 0x97 -#define EEPROM_HT20_TX_PWR_INX_DIFF_5GM 0x9A -#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GM 0x9D -#define EEPROM_HT40_MAX_PWR_OFFSET_5GM 0xA0 -#define EEPROM_HT20_MAX_PWR_OFFSET_5GM 0xA3 - -//5GH channel 149-165 -#define EEPROM_HT40_1S_TX_PWR_INX_5GH 0xA6 -#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GH 0xAC -#define EEPROM_HT20_TX_PWR_INX_DIFF_5GH 0xAF -#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GH 0xB2 -#define EEPROM_HT40_MAX_PWR_OFFSET_5GH 0xB5 -#define EEPROM_HT20_MAX_PWR_OFFSET_5GH 0xB8 - -#define EEPROM_CHANNEL_PLAN 0xBB // Map of supported channels. -#define EEPROM_TEST_CHANNEL_PLAN 0xBB -#define EEPROM_IQK_DELTA 0xBC -#define EEPROM_LCK_DELTA 0xBC -#define EEPROM_XTAL_K 0xBD //[7:5] -#define EEPROM_TSSI_A_5G 0xBE -#define EEPROM_TSSI_B_5G 0xBF -#define EEPROM_TSSI_AB_5G 0xC0 -#define EEPROM_THERMAL_METER 0xC3 //[4:0] -#define EEPROM_RF_OPT1 0xC4 -#define EEPROM_RF_OPT2 0xC5 -#define EEPROM_RF_OPT3 0xC6 -#define EEPROM_RF_OPT4 0xC7 -#define EEPROM_RF_OPT5 0xC8 -#define EEPROM_RF_OPT6 0xC9 -#define EEPROM_VERSION 0xCA -#define EEPROM_CUSTOMER_ID 0xCB -#define EEPROM_RF_OPT7 0xCC - -#define EEPROM_DEF_PART_NO 0x3FD //Byte -#define EEPROME_CHIP_VERSION_L 0x3FF -#define EEPROME_CHIP_VERSION_H 0x3FE - -//------------------------------------------------------------- -// EEPROM content definitions -//------------------------------------------------------------- -#define OS_LINK_SPEED_NORMAL_MASK BIT3 | BIT2 -#define OS_LINK_SPEED_TEST_MASK BIT3 | BIT4 - -#define BOARD_TYPE_NORMAL_MASK 0xE0 -#define BOARD_TYPE_TEST_MASK 0xF - -#define BT_COEXISTENCE_TEST BIT4 -#define BT_COEXISTENCE_NORMAL BIT5 - -#define BT_CO_SHIFT_TEST 4 -#define BT_CO_SHIFT_NORMAL 5 - -#define EP_NUMBER_MASK_TEST 0x30 //bit 4:5 0Eh -#define EP_NUMBER_SHIFT_TEST 4 - -#define USB_PHY_PARA_SIZE_TEST 6 -#define USB_PHY_PARA_SIZE_NORMAL 4 - -//------------------------------------------------------------- -// EEPROM default value definitions -//------------------------------------------------------------- -// Use 0xABCD instead of 0x8192 for debug -#define EEPROM_DEF_ID_0 0xCD // Byte 0x00 -#define EEPROM_DEF_ID_1 0xAB // Byte 0x01 - -#define EEPROM_DEF_RTK_RSV_A3 0x74 // Byte 0x03 -#define EEPROM_DEF_RTK_RSV_A4 0x6D // Byte 0x04 -#define EEPROM_DEF_RTK_RSV_A8 0xFF // Byte 0x08 - -#define EEPROM_DEF_VID_0 0x0A // Byte 0x0A -#define EEPROM_DEF_VID_1 0x0B - -#define EEPROM_DEF_PID_0 0x92 // Byte 0x0C -#define EEPROM_DEF_PID_1 0x81 - - -#define EEPROM_TEST_DEF_USB_OPT 0x80 // Byte 0x0E -#define EEPROM_NORMAL_DEF_USB_OPT 0x00 // Byte 0x0E - -#define EEPROM_DEF_CHIRPK 0x15 // Byte 0x0F - -#define EEPROM_DEF_USB_PHY_0 0x85 // Byte 0x10 -#define EEPROM_DEF_USB_PHY_1 0x62 // Byte 0x11 -#define EEPROM_DEF_USB_PHY_2 0x9E // Byte 0x12 -#define EEPROM_DEF_USB_PHY_3 0x06 // Byte 0x13 - -#define EEPROM_DEF_TSSI_A 0x09 // Byte 0x78 -#define EEPROM_DEF_TSSI_B 0x09 // Byte 0x79 - - -#define EEPROM_DEF_THERMAL_METER 0x12 // Byte 0x7A - - -#define EEPROM_USB_SN BIT(0) -#define EEPROM_USB_REMOTE_WAKEUP BIT(1) -#define EEPROM_USB_DEVICE_PWR BIT(2) -#define EEPROM_EP_NUMBER (BIT(3)|BIT(4)) - -/*=================================================================== -===================================================================== -Here the register defines are for 92C. When the define is as same with 92C, -we will use the 92C's define for the consistency -So the following defines for 92C is not entire!!!!!! -===================================================================== -=====================================================================*/ -/* -Based on Datasheet V33---090401 -Register Summary -Current IOREG MAP -0x0000h ~ 0x00FFh System Configuration (256 Bytes) -0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) -0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) -0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) -0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) -0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) -0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) -0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) -0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) -*/ - -//---------------------------------------------------------------------------- -// 8192C (RCR) Receive Configuration Register (Offset 0x608, 32 bits) -//---------------------------------------------------------------------------- -#define RCR_APPFCS BIT31 //WMAC append FCS after pauload -#define RCR_APP_MIC BIT30 // -#define RCR_APP_ICV BIT29 // -#define RCR_APP_PHYST_RXFF BIT28 // -#define RCR_APP_BA_SSN BIT27 //Accept BA SSN -#define RCR_ENMBID BIT24 //Enable Multiple BssId. -#define RCR_LSIGEN BIT23 -#define RCR_MFBEN BIT22 -#define RCR_HTC_LOC_CTRL BIT14 //MFC<--HTC=1 MFC-->HTC=0 -#define RCR_AMF BIT13 //Accept management type frame -#define RCR_ACF BIT12 //Accept control type frame -#define RCR_ADF BIT11 //Accept data type frame -#define RCR_AICV BIT9 //Accept ICV error packet -#define RCR_ACRC32 BIT8 //Accept CRC32 error packet -#define RCR_CBSSID_BCN BIT7 //Accept BSSID match packet (Rx beacon, probe rsp) -#define RCR_CBSSID_DATA BIT6 //Accept BSSID match packet (Data) -#define RCR_CBSSID RCR_CBSSID_DATA //Accept BSSID match packet -#define RCR_APWRMGT BIT5 //Accept power management packet -#define RCR_ADD3 BIT4 //Accept address 3 match packet -#define RCR_AB BIT3 //Accept broadcast packet -#define RCR_AM BIT2 //Accept multicast packet -#define RCR_APM BIT1 //Accept physical match packet -#define RCR_AAP BIT0 //Accept all unicast packet -#define RCR_MXDMA_OFFSET 8 -#define RCR_FIFO_OFFSET 13 - - - -//============================================================================ -// 8192c USB specific Regsiter Offset and Content definition, -// 2009.08.18, added by vivi. for merge 92c and 92C into one driver -//============================================================================ -//#define APS_FSMCO 0x0004 same with 92Ce -#define RSV_CTRL 0x001C -#define RD_CTRL 0x0524 - -//----------------------------------------------------- -// -// 0xFE00h ~ 0xFE55h USB Configuration -// -//----------------------------------------------------- -#define REG_USB_INFO 0xFE17 -#define REG_USB_SPECIAL_OPTION 0xFE55 -#define REG_USB_DMA_AGG_TO 0xFE5B -#define REG_USB_AGG_TO 0xFE5C -#define REG_USB_AGG_TH 0xFE5D - -#define REG_USB_VID 0xFE60 -#define REG_USB_PID 0xFE62 -#define REG_USB_OPTIONAL 0xFE64 -#define REG_USB_CHIRP_K 0xFE65 -#define REG_USB_PHY 0xFE66 -#define REG_USB_MAC_ADDR 0xFE70 - -#define REG_USB_HRPWM 0xFE58 -#define REG_USB_HCPWM 0xFE57 - -#define InvalidBBRFValue 0x12345678 - -//============================================================================ -// 8192C Regsiter Bit and Content definition -//============================================================================ -//----------------------------------------------------- -// -// 0x0000h ~ 0x00FFh System Configuration -// -//----------------------------------------------------- - -//2 SPS0_CTRL -#define SW18_FPWM BIT(3) - - -//2 SYS_ISO_CTRL -#define ISO_MD2PP BIT(0) -#define ISO_UA2USB BIT(1) -#define ISO_UD2CORE BIT(2) -#define ISO_PA2PCIE BIT(3) -#define ISO_PD2CORE BIT(4) -#define ISO_IP2MAC BIT(5) -#define ISO_DIOP BIT(6) -#define ISO_DIOE BIT(7) -#define ISO_EB2CORE BIT(8) -#define ISO_DIOR BIT(9) - -#define PWC_EV25V BIT(14) -#define PWC_EV12V BIT(15) - - -//2 SYS_FUNC_EN -#define FEN_BBRSTB BIT(0) -#define FEN_BB_GLB_RSTn BIT(1) -#define FEN_USBA BIT(2) -#define FEN_UPLL BIT(3) -#define FEN_USBD BIT(4) -#define FEN_DIO_PCIE BIT(5) -#define FEN_PCIEA BIT(6) -#define FEN_PPLL BIT(7) -#define FEN_PCIED BIT(8) -#define FEN_DIOE BIT(9) -#define FEN_CPUEN BIT(10) -#define FEN_DCORE BIT(11) -#define FEN_ELDR BIT(12) -#define FEN_DIO_RF BIT(13) -#define FEN_HWPDN BIT(14) -#define FEN_MREGEN BIT(15) - -//2 APS_FSMCO -#define PFM_LDALL BIT(0) -#define PFM_ALDN BIT(1) -#define PFM_LDKP BIT(2) -#define PFM_WOWL BIT(3) -#define EnPDN BIT(4) -#define PDN_PL BIT(5) -#define APFM_ONMAC BIT(8) -#define APFM_OFF BIT(9) -#define APFM_RSM BIT(10) -#define AFSM_HSUS BIT(11) -#define AFSM_PCIE BIT(12) -#define APDM_MAC BIT(13) -#define APDM_HOST BIT(14) -#define APDM_HPDN BIT(15) -#define RDY_MACON BIT(16) -#define SUS_HOST BIT(17) -#define ROP_ALD BIT(20) -#define ROP_PWR BIT(21) -#define ROP_SPS BIT(22) -#define SOP_MRST BIT(25) -#define SOP_FUSE BIT(26) -#define SOP_ABG BIT(27) -#define SOP_AMB BIT(28) -#define SOP_RCK BIT(29) -#define SOP_A8M BIT(30) -#define XOP_BTCK BIT(31) - -//2 SYS_CLKR -#define ANAD16V_EN BIT(0) -#define ANA8M BIT(1) -#define MACSLP BIT(4) -#define LOADER_CLK_EN BIT(5) -#define _80M_SSC_DIS BIT(7) -#define _80M_SSC_EN_HO BIT(8) -#define PHY_SSC_RSTB BIT(9) -#define SEC_CLK_EN BIT(10) -#define MAC_CLK_EN BIT(11) -#define SYS_CLK_EN BIT(12) -#define RING_CLK_EN BIT(13) - - -//2 9346CR - -#define BOOT_FROM_EEPROM BIT(4) -#define EEPROM_EN BIT(5) - - -//2 AFE_MISC -#define AFE_BGEN BIT(0) -#define AFE_MBEN BIT(1) -#define MAC_ID_EN BIT(7) - - -//2 SPS0_CTRL - - -//2 SPS_OCP_CFG - - -//2 RSV_CTRL -#define WLOCK_ALL BIT(0) -#define WLOCK_00 BIT(1) -#define WLOCK_04 BIT(2) -#define WLOCK_08 BIT(3) -#define WLOCK_40 BIT(4) -#define R_DIS_PRST_0 BIT(5) -#define R_DIS_PRST_1 BIT(6) -#define LOCK_ALL_EN BIT(7) - -//2 RF_CTRL -#define RF_EN BIT(0) -#define RF_RSTB BIT(1) -#define RF_SDMRSTB BIT(2) - - - -//2 LDOA15_CTRL -#define LDA15_EN BIT(0) -#define LDA15_STBY BIT(1) -#define LDA15_OBUF BIT(2) -#define LDA15_REG_VOS BIT(3) -#define _LDA15_VOADJ(x) (((x) & 0x7) << 4) - - - -//2 LDOV12D_CTRL -#define LDV12_EN BIT(0) -#define LDV12_SDBY BIT(1) -#define LPLDO_HSM BIT(2) -#define LPLDO_LSM_DIS BIT(3) -#define _LDV12_VADJ(x) (((x) & 0xF) << 4) - - -//2 AFE_XTAL_CTRL -#define XTAL_EN BIT(0) -#define XTAL_BSEL BIT(1) -#define _XTAL_BOSC(x) (((x) & 0x3) << 2) -#define _XTAL_CADJ(x) (((x) & 0xF) << 4) -#define XTAL_GATE_USB BIT(8) -#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9) -#define XTAL_GATE_AFE BIT(11) -#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12) -#define XTAL_RF_GATE BIT(14) -#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15) -#define XTAL_GATE_DIG BIT(17) -#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18) -#define XTAL_BT_GATE BIT(20) -#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) -#define _XTAL_GPIO(x) (((x) & 0x7) << 23) - - -#define CKDLY_AFE BIT(26) -#define CKDLY_USB BIT(27) -#define CKDLY_DIG BIT(28) -#define CKDLY_BT BIT(29) - - -//2 AFE_PLL_CTRL -#define APLL_EN BIT(0) -#define APLL_320_EN BIT(1) -#define APLL_FREF_SEL BIT(2) -#define APLL_EDGE_SEL BIT(3) -#define APLL_WDOGB BIT(4) -#define APLL_LPFEN BIT(5) - -#define APLL_REF_CLK_13MHZ 0x1 -#define APLL_REF_CLK_19_2MHZ 0x2 -#define APLL_REF_CLK_20MHZ 0x3 -#define APLL_REF_CLK_25MHZ 0x4 -#define APLL_REF_CLK_26MHZ 0x5 -#define APLL_REF_CLK_38_4MHZ 0x6 -#define APLL_REF_CLK_40MHZ 0x7 - -#define APLL_320EN BIT(14) -#define APLL_80EN BIT(15) -#define APLL_1MEN BIT(24) - - -//2 EFUSE_CTRL -#define ALD_EN BIT(18) -#define EF_PD BIT(19) -#define EF_FLAG BIT(31) - -//2 EFUSE_TEST -#define EF_TRPT BIT(7) -#define LDOE25_EN BIT(31) - -//2 PWR_DATA - -//2 CAL_TIMER - -//2 ACLK_MON -#define RSM_EN BIT(0) -#define Timer_EN BIT(4) - - -//2 GPIO_MUXCFG -#define TRSW0EN BIT(2) -#define TRSW1EN BIT(3) -#define EROM_EN BIT(4) -#define EnBT BIT(5) -#define EnUart BIT(8) -#define Uart_910 BIT(9) -#define EnPMAC BIT(10) -#define SIC_SWRST BIT(11) -#define EnSIC BIT(12) -#define SIC_23 BIT(13) -#define EnHDP BIT(14) -#define SIC_LBK BIT(15) - -//2 GPIO_PIN_CTRL - - - -//2 GPIO_INTM - -//2 LEDCFG -#define LED0PL BIT(4) -#define LED1PL BIT(12) -#define LED0DIS BIT(7) - -#define SECCAM_CLR BIT(30) - -//2 FSIMR - -//2 FSISR - - -//2 8051FWDL -//2 MCUFWDL -#define MCUFWDL_EN BIT(0) -#define MCUFWDL_RDY BIT(1) -#define FWDL_ChkSum_rpt BIT(2) -#define MACINI_RDY BIT(3) -#define BBINI_RDY BIT(4) -#define RFINI_RDY BIT(5) -#define WINTINI_RDY BIT(6) -#define MAC1_WINTINI_RDY BIT(11)// 0X81 BIT3 -#define CPRST BIT(23) - - - - -//2 REG_SYS_CFG -#define XCLK_VLD BIT(0) -#define ACLK_VLD BIT(1) -#define UCLK_VLD BIT(2) -#define PCLK_VLD BIT(3) -#define PCIRSTB BIT(4) -#define V15_VLD BIT(5) -#define TRP_B15V_EN BIT(7) -#define SIC_IDLE BIT(8) -#define BD_MAC2 BIT(9) -#define BD_MAC1 BIT(10) -#define IC_MACPHY_MODE BIT(11) -#define PAD_HWPD_IDN BIT(22) -#define TRP_VAUX_EN BIT(23) -#define TRP_BT_EN BIT(24) -#define BD_PKG_SEL BIT(25) -#define BD_HCI_SEL BIT(26) -#define TYPE_ID BIT(27) - -#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15 -#define CHIP_VER_RTL_SHIFT 12 - -//----------------------------------------------------- -// -// 0x0100h ~ 0x01FFh MACTOP General Configuration -// -//----------------------------------------------------- - - -//2 Function Enable Registers -//2 CR - -#define REG_LBMODE (REG_CR + 3) - - -#define HCI_TXDMA_EN BIT(0) -#define HCI_RXDMA_EN BIT(1) -#define TXDMA_EN BIT(2) -#define RXDMA_EN BIT(3) -#define PROTOCOL_EN BIT(4) -#define SCHEDULE_EN BIT(5) -#define MACTXEN BIT(6) -#define MACRXEN BIT(7) -#define ENSWBCN BIT(8) -#define ENSEC BIT(9) - -// Network type -#define _NETTYPE(x) (((x) & 0x3) << 16) -#define MASK_NETTYPE 0x30000 -#define NT_NO_LINK 0x0 -#define NT_LINK_AD_HOC 0x1 -#define NT_LINK_AP 0x2 -#define NT_AS_AP 0x3 - -#define _LBMODE(x) (((x) & 0xF) << 24) -#define MASK_LBMODE 0xF000000 -#define LOOPBACK_NORMAL 0x0 -#define LOOPBACK_IMMEDIATELY 0xB -#define LOOPBACK_MAC_DELAY 0x3 -#define LOOPBACK_PHY 0x1 -#define LOOPBACK_DMA 0x7 - - -//2 PBP - Page Size Register -#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) -#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) -#define _PSRX_MASK 0xF -#define _PSTX_MASK 0xF0 -#define _PSRX(x) (x) -#define _PSTX(x) ((x) << 4) - -#define PBP_64 0x0 -#define PBP_128 0x1 -#define PBP_256 0x2 -#define PBP_512 0x3 -#define PBP_1024 0x4 - - -//2 TX/RXDMA -#define RXDMA_ARBBW_EN BIT(0) -#define RXSHFT_EN BIT(1) -#define RXDMA_AGG_EN BIT(2) -#define QS_VO_QUEUE BIT(8) -#define QS_VI_QUEUE BIT(9) -#define QS_BE_QUEUE BIT(10) -#define QS_BK_QUEUE BIT(11) -#define QS_MANAGER_QUEUE BIT(12) -#define QS_HIGH_QUEUE BIT(13) - -#define HQSEL_VOQ BIT(0) -#define HQSEL_VIQ BIT(1) -#define HQSEL_BEQ BIT(2) -#define HQSEL_BKQ BIT(3) -#define HQSEL_MGTQ BIT(4) -#define HQSEL_HIQ BIT(5) - -// For normal driver, 0x10C -#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) -#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) -#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) -#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) -#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) -#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) - -#define QUEUE_LOW 1 -#define QUEUE_NORMAL 2 -#define QUEUE_HIGH 3 - - - -//2 TRXFF_BNDY - - -//2 LLT_INIT -#define _LLT_NO_ACTIVE 0x0 -#define _LLT_WRITE_ACCESS 0x1 -#define _LLT_READ_ACCESS 0x2 - -#define _LLT_INIT_DATA(x) ((x) & 0xFF) -#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) -#define _LLT_OP(x) (((x) & 0x3) << 30) -#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) - - -//2 BB_ACCESS_CTRL -#define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) -#define BB_WRITE_EN BIT(30) -#define BB_READ_EN BIT(31) -//#define BB_ADDR_MASK 0xFFF -//#define _BB_ADDR(x) ((x) & BB_ADDR_MASK) - -//----------------------------------------------------- -// -// 0x0200h ~ 0x027Fh TXDMA Configuration -// -//----------------------------------------------------- -//2 RQPN -#define _HPQ(x) ((x) & 0xFF) -#define _LPQ(x) (((x) & 0xFF) << 8) -#define _PUBQ(x) (((x) & 0xFF) << 16) -#define _NPQ(x) ((x) & 0xFF) // NOTE: in RQPN_NPQ register - - -#define HPQ_PUBLIC_DIS BIT(24) -#define LPQ_PUBLIC_DIS BIT(25) -#define LD_RQPN BIT(31) - - -//2 TDECTRL -#define BCN_VALID BIT(16) -#define BCN_HEAD(x) (((x) & 0xFF) << 8) -#define BCN_HEAD_MASK 0xFF00 - -//2 TDECTL -#define BLK_DESC_NUM_SHIFT 4 -#define BLK_DESC_NUM_MASK 0xF - - -//2 TXDMA_OFFSET_CHK -#define DROP_DATA_EN BIT(9) - -//----------------------------------------------------- -// -// 0x0400h ~ 0x047Fh Protocol Configuration -// -//----------------------------------------------------- -//2 FWHW_TXQ_CTRL -#define EN_AMPDU_RTY_NEW BIT(7) - -//2 INIRTSMCS_SEL -#define _INIRTSMCS_SEL(x) ((x) & 0x3F) - - -//2 SPEC SIFS -#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) -#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) - - -//2 RRSR - -#define RATE_REG_BITMAP_ALL 0xFFFFF - -#define _RRSC_BITMAP(x) ((x) & 0xFFFFF) - -#define _RRSR_RSC(x) (((x) & 0x3) << 21) -#define RRSR_RSC_RESERVED 0x0 -#define RRSR_RSC_UPPER_SUBCHANNEL 0x1 -#define RRSR_RSC_LOWER_SUBCHANNEL 0x2 -#define RRSR_RSC_DUPLICATE_MODE 0x3 - - -//2 ARFR -#define USE_SHORT_G1 BIT(20) - -//2 AGGLEN_LMT_L -#define _AGGLMT_MCS0(x) ((x) & 0xF) -#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4) -#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8) -#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12) -#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16) -#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20) -#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) -#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) - - -//2 RL -#define RETRY_LIMIT_SHORT_SHIFT 8 -#define RETRY_LIMIT_LONG_SHIFT 0 - - -//2 DARFRC -#define _DARF_RC1(x) ((x) & 0x1F) -#define _DARF_RC2(x) (((x) & 0x1F) << 8) -#define _DARF_RC3(x) (((x) & 0x1F) << 16) -#define _DARF_RC4(x) (((x) & 0x1F) << 24) -// NOTE: shift starting from address (DARFRC + 4) -#define _DARF_RC5(x) ((x) & 0x1F) -#define _DARF_RC6(x) (((x) & 0x1F) << 8) -#define _DARF_RC7(x) (((x) & 0x1F) << 16) -#define _DARF_RC8(x) (((x) & 0x1F) << 24) - - -//2 RARFRC -#define _RARF_RC1(x) ((x) & 0x1F) -#define _RARF_RC2(x) (((x) & 0x1F) << 8) -#define _RARF_RC3(x) (((x) & 0x1F) << 16) -#define _RARF_RC4(x) (((x) & 0x1F) << 24) -// NOTE: shift starting from address (RARFRC + 4) -#define _RARF_RC5(x) ((x) & 0x1F) -#define _RARF_RC6(x) (((x) & 0x1F) << 8) -#define _RARF_RC7(x) (((x) & 0x1F) << 16) -#define _RARF_RC8(x) (((x) & 0x1F) << 24) - - - - -//----------------------------------------------------- -// -// 0x0500h ~ 0x05FFh EDCA Configuration -// -//----------------------------------------------------- - - - -//2 EDCA setting -#define AC_PARAM_TXOP_LIMIT_OFFSET 16 -#define AC_PARAM_ECW_MAX_OFFSET 12 -#define AC_PARAM_ECW_MIN_OFFSET 8 -#define AC_PARAM_AIFS_OFFSET 0 - - -//2 EDCA_VO_PARAM -#define _AIFS(x) (x) -#define _ECW_MAX_MIN(x) ((x) << 8) -#define _TXOP_LIMIT(x) ((x) << 16) - - -#define _BCNIFS(x) ((x) & 0xFF) -#define _BCNECW(x) (((x) & 0xF))<< 8) - - -#define _LRL(x) ((x) & 0x3F) -#define _SRL(x) (((x) & 0x3F) << 8) - - -//2 SIFS_CCK -#define _SIFS_CCK_CTX(x) ((x) & 0xFF) -#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8); - - -//2 SIFS_OFDM -#define _SIFS_OFDM_CTX(x) ((x) & 0xFF) -#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8); - - -//2 TBTT PROHIBIT -#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) - - -//2 REG_RD_CTRL -#define DIS_EDCA_CNT_DWN BIT(11) - - -//2 BCN_CTRL -#define EN_MBSSID BIT(1) -#define EN_TXBCN_RPT BIT(2) -#define EN_BCN_FUNCTION BIT(3) -#define DIS_TSF_UPDATE BIT(3) - -// The same function but different bit field. -#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) -#define DIS_TSF_UDT0_TEST_CHIP BIT(5) - -//2 ACMHWCTRL -#define AcmHw_HwEn BIT(0) -#define AcmHw_BeqEn BIT(1) -#define AcmHw_ViqEn BIT(2) -#define AcmHw_VoqEn BIT(3) -#define AcmHw_BeqStatus BIT(4) -#define AcmHw_ViqStatus BIT(5) -#define AcmHw_VoqStatus BIT(6) - - - -//----------------------------------------------------- -// -// 0x0600h ~ 0x07FFh WMAC Configuration -// -//----------------------------------------------------- - -//2 APSD_CTRL -#define APSDOFF BIT(6) -#define APSDOFF_STATUS BIT(7) - - -//2 BWOPMODE -#define BW_20MHZ BIT(2) -//#define BW_OPMODE_20MHZ BIT(2) // For compability - - -#define RATE_BITMAP_ALL 0xFFFFF - -// Only use CCK 1M rate for ACK -#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 -#define RATE_RRSR_WITHOUT_CCK 0xFFFF0 - -//2 TCR -#define TSFRST BIT(0) -#define DIS_GCLK BIT(1) -#define PAD_SEL BIT(2) -#define PWR_ST BIT(6) -#define PWRBIT_OW_EN BIT(7) -#define ACRC BIT(8) -#define CFENDFORM BIT(9) -#define ICV BIT(10) - - - -//2 RCR -#define AAP BIT(0) -#define APM BIT(1) -#define AM BIT(2) -#define AB BIT(3) -#define ADD3 BIT(4) -#define APWRMGT BIT(5) -#define CBSSID BIT(6) -#define CBSSID_BCN BIT(7) -#define ACRC32 BIT(8) -#define AICV BIT(9) -#define ADF BIT(11) -#define ACF BIT(12) -#define AMF BIT(13) -#define HTC_LOC_CTRL BIT(14) -#define UC_DATA_EN BIT(16) -#define BM_DATA_EN BIT(17) -#define MFBEN BIT(22) -#define LSIGEN BIT(23) -#define EnMBID BIT(24) -#define APP_BASSN BIT(27) -#define APP_PHYSTS BIT(28) -#define APP_ICV BIT(29) -#define APP_MIC BIT(30) -#define APP_FCS BIT(31) - -//2 RX_PKT_LIMIT - -//2 RX_DLK_TIME - -//2 MBIDCAMCFG - - - -//2 AMPDU_MIN_SPACE -#define _MIN_SPACE(x) ((x) & 0x7) -#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) - - -//2 RXERR_RPT -#define RXERR_TYPE_OFDM_PPDU 0 -#define RXERR_TYPE_OFDMfalse_ALARM 1 -#define RXERR_TYPE_OFDM_MPDU_OK 2 -#define RXERR_TYPE_OFDM_MPDU_FAIL 3 -#define RXERR_TYPE_CCK_PPDU 4 -#define RXERR_TYPE_CCKfalse_ALARM 5 -#define RXERR_TYPE_CCK_MPDU_OK 6 -#define RXERR_TYPE_CCK_MPDU_FAIL 7 -#define RXERR_TYPE_HT_PPDU 8 -#define RXERR_TYPE_HTfalse_ALARM 9 -#define RXERR_TYPE_HT_MPDU_TOTAL 10 -#define RXERR_TYPE_HT_MPDU_OK 11 -#define RXERR_TYPE_HT_MPDU_FAIL 12 -#define RXERR_TYPE_RX_FULL_DROP 15 - -#define RXERR_COUNTER_MASK 0xFFFFF -#define RXERR_RPT_RST BIT(27) -#define _RXERR_RPT_SEL(type) ((type) << 28) - - -//2 SECCFG -#define SCR_TxUseDK BIT(0) //Force Tx Use Default Key -#define SCR_RxUseDK BIT(1) //Force Rx Use Default Key -#define SCR_TxEncEnable BIT(2) //Enable Tx Encryption -#define SCR_RxDecEnable BIT(3) //Enable Rx Decryption -#define SCR_SKByA2 BIT(4) //Search kEY BY A2 -#define SCR_NoSKMC BIT(5) //No Key Search Multicast -#define SCR_TXBCUSEDK BIT(6) // Force Tx Broadcast packets Use Default Key -#define SCR_RXBCUSEDK BIT(7) // Force Rx Broadcast packets Use Default Key - -//vivi added for new cam search flow, 20091028 -#ifdef HW_EN_DE_CRYPTION_FOR_NEW_CAM_SEARCH_FLOW -#define SCR_TxUseBroadcastDK BIT6 //Force Tx Use Broadcast Default Key -#define SCR_RxUseBroadcastDK BIT7 //Force Rx Use Broadcast Default Key -#endif - - -//----------------------------------------------------- -// -// 0xFE00h ~ 0xFE55h USB Configuration -// -//----------------------------------------------------- - -//2 USB Information (0xFE17) -#define USB_IS_HIGH_SPEED 0 -#define USB_IS_FULL_SPEED 1 -#define USB_SPEED_MASK BIT(5) - -#define USB_NORMAL_SIE_EP_MASK 0xF -#define USB_NORMAL_SIE_EP_SHIFT 4 - -#define USB_TEST_EP_MASK 0x30 -#define USB_TEST_EP_SHIFT 4 - -//2 Special Option -#define USB_AGG_EN BIT(3) - - -//2REG_C2HEVT_CLEAR -#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message -#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. - -//2 8192D PartNo. -#define PARTNO_92D_NIC (BIT7|BIT6) -#define PARTNO_92D_NIC_REMARK (BIT5|BIT4) -#define PARTNO_SINGLE_BAND_VS BIT3 -#define PARTNO_SINGLE_BAND_VS_REMARK BIT1 -#define PARTNO_CONCURRENT_BAND_VC (BIT3|BIT2) -#define PARTNO_CONCURRENT_BAND_VC_REMARK (BIT1|BIT0) -//======================================================== -// General definitions -//======================================================== - -#define MAC_ADDR_LEN 6 -#define LAST_ENTRY_OF_TX_PKT_BUFFER 255 -#define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC 127 - -#define POLLING_LLT_THRESHOLD 20 -#define POLLING_READY_TIMEOUT_COUNT 1000 - -// Min Spacing related settings. -#define MAX_MSS_DENSITY_2T 0x13 -#define MAX_MSS_DENSITY_1T 0x0A -// GPIO BIT -#define HAL_8192C_HW_GPIO_WPS_BIT BIT2 - - -#include "basic_types.h" - -#endif diff --git a/include/rtl8192d_xmit.h b/include/rtl8192d_xmit.h deleted file mode 100755 index 158a8fe..0000000 --- a/include/rtl8192d_xmit.h +++ /dev/null @@ -1,157 +0,0 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef _RTL8192D_XMIT_H_ -#define _RTL8192D_XMIT_H_ - -// -//defined for TX DESC Operation -// - -#define MAX_TID (15) - -//OFFSET 0 -#define OFFSET_SZ 0 -#define OFFSET_SHT 16 -#define BMC BIT(24) -#define LSG BIT(26) -#define FSG BIT(27) -#define OWN BIT(31) - - -//OFFSET 4 -#define PKT_OFFSET_SZ 0 -#define BK BIT(6) -#define QSEL_SHT 8 -#define Rate_ID_SHT 16 -#define NAVUSEHDR BIT(20) -#define PKT_OFFSET_SHT 26 -#define HWPC BIT(31) - -//OFFSET 8 -#define AGG_EN BIT(29) - -//OFFSET 12 -#define SEQ_SHT 16 - -//OFFSET 16 -#define QoS BIT(6) -#define HW_SEQ_EN BIT(7) -#define USERATE BIT(8) -#define DISDATAFB BIT(10) -#define DATA_SHORT BIT(24) -#define DATA_BW BIT(25) - -//OFFSET 20 -#define SGI BIT(6) - -// -// Queue Select Value in TxDesc -// -#define QSLT_BK 0x2//0x01 -#define QSLT_BE 0x0 -#define QSLT_VI 0x5//0x4 -#define QSLT_VO 0x7//0x6 -#define QSLT_BEACON 0x10 -#define QSLT_HIGH 0x11 -#define QSLT_MGNT 0x12 -#define QSLT_CMD 0x13 - -//Because we open EM for normal case, we just always insert 2*8 bytes.by wl -#define USB_92D_DUMMY_OFFSET 2 -#define USB_92D_DUMMY_LENGTH (USB_92D_DUMMY_OFFSET * PACKET_OFFSET_SZ) -#define USB_HWDESC_HEADER_LEN (TXDESC_SIZE + USB_92D_DUMMY_LENGTH) - -//For 92D early mode -#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value) -#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value) -#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value) -#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value) -#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value) -#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value) -#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value) - -/* Copy from rtl8192c */ -struct txrpt_ccx_8192d { - /* offset 0 */ - u8 retry_cnt:6; - u8 rsvd_0:2; - - /* offset 1 */ - u8 rts_retry_cnt:6; - u8 rsvd_1:2; - - /* offset 2 */ - u8 ccx_qtime0; - u8 ccx_qtime1; - - /* offset 4 */ - u8 missed_pkt_num:5; - u8 rsvd_4:3; - - /* offset 5 */ - u8 mac_id:5; - u8 des1_fragssn:3; - - /* offset 6 */ - u8 rpt_pkt_num:5; - u8 pkt_drop:1; - u8 lifetime_over:1; - u8 retry_over:1; - - /* offset 7*/ - u8 edca_tx_queue:4; - u8 rsvd_7:1; - u8 bmc:1; - u8 pkt_ok:1; - u8 int_ccx:1; -}; - -#define txrpt_ccx_qtime_8192d(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8)) - -#ifdef CONFIG_XMIT_ACK -void dump_txrpt_ccx_8192d(void *buf); -void handle_txrpt_ccx_8192d(struct adapter *adapter, void *buf); -#else -#define dump_txrpt_ccx_8192d(buf) do {} while(0) -#define handle_txrpt_ccx_8192d(adapter, buf) do {} while(0) -#endif - -#ifdef CONFIG_USB_TX_AGGREGATION -#define MAX_TX_AGG_PACKET_NUMBER 0xFF - -s32 rtl8192du_init_xmit_priv(struct adapter * padapter); - -void rtl8192du_free_xmit_priv(struct adapter * padapter); - -void rtl8192du_cal_txdesc_chksum(struct tx_desc *ptxdesc); - -s32 rtl8192du_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); - -s32 rtl8192du_mgnt_xmit(struct adapter *padapter, struct xmit_frame *pmgntframe); - -s32 rtl8192du_hal_xmit(struct adapter *padapter, struct xmit_frame *pxmitframe); - -#ifdef CONFIG_HOSTAPD_MLME -s32 rtl8192du_hostap_mgnt_xmit_entry(struct adapter *padapter, _pkt *pkt); -#endif - -#endif - -#endif diff --git a/include/rtw_byteorder.h b/include/rtw_byteorder.h index 80dbcb5..74a9b5f 100755 --- a/include/rtw_byteorder.h +++ b/include/rtw_byteorder.h @@ -28,10 +28,10 @@ #if defined (CONFIG_LITTLE_ENDIAN) #ifndef CONFIG_PLATFORM_MSTAR -# include +# include #endif #elif defined (CONFIG_BIG_ENDIAN) -# include +# include #else # error "Must be LITTLE/BIG Endian Host" #endif diff --git a/include/byteorder/swab.h b/include/swab.h similarity index 100% rename from include/byteorder/swab.h rename to include/swab.h diff --git a/include/byteorder/swabb.h b/include/swabb.h similarity index 100% rename from include/byteorder/swabb.h rename to include/swabb.h