mirror of
https://github.com/lwfinger/rtl8188eu.git
synced 2024-11-25 05:53:41 +00:00
rtl8188eu: Set load parameter debug for dynamic debugging
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
parent
f8e677c4b4
commit
3ad757d04a
6 changed files with 103 additions and 765 deletions
|
|
@ -11630,7 +11630,8 @@ ODM_SingleDualAntennaDetection(
|
|||
{
|
||||
pDM_SWAT_Table->ANTA_ON=TRUE;
|
||||
pDM_SWAT_Table->ANTB_ON=TRUE;
|
||||
RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
|
||||
("ODM_SingleDualAntennaDetection(): Dual Antenna\n"));
|
||||
}
|
||||
}
|
||||
else
|
||||
|
|
|
|||
589
hal/odm_debug.c
589
hal/odm_debug.c
|
|
@ -33,595 +33,8 @@ pDM_Odm->DebugLevel = ODM_DBG_TRACE;
|
|||
|
||||
pDM_Odm->DebugComponents =
|
||||
\
|
||||
#if DBG
|
||||
//BB Functions
|
||||
// ODM_COMP_DIG |
|
||||
// ODM_COMP_RA_MASK |
|
||||
// ODM_COMP_DYNAMIC_TXPWR |
|
||||
// ODM_COMP_FA_CNT |
|
||||
// ODM_COMP_RSSI_MONITOR |
|
||||
// ODM_COMP_CCK_PD |
|
||||
// ODM_COMP_ANT_DIV |
|
||||
// ODM_COMP_PWR_SAVE |
|
||||
// ODM_COMP_PWR_TRAIN |
|
||||
// ODM_COMP_RATE_ADAPTIVE |
|
||||
// ODM_COMP_PATH_DIV |
|
||||
// ODM_COMP_DYNAMIC_PRICCA |
|
||||
// ODM_COMP_RXHP |
|
||||
|
||||
//MAC Functions
|
||||
// ODM_COMP_EDCA_TURBO |
|
||||
// ODM_COMP_EARLY_MODE |
|
||||
//RF Functions
|
||||
// ODM_COMP_TX_PWR_TRACK |
|
||||
// ODM_COMP_RX_GAIN_TRACK |
|
||||
// ODM_COMP_CALIBRATION |
|
||||
//Common
|
||||
// ODM_COMP_COMMON |
|
||||
// ODM_COMP_INIT |
|
||||
#endif
|
||||
0;
|
||||
}
|
||||
|
||||
#if 0
|
||||
/*------------------Declare variable-----------------------
|
||||
// Define debug flag array for common debug print macro. */
|
||||
u4Byte ODM_DBGP_Type[ODM_DBGP_TYPE_MAX];
|
||||
|
||||
/* Define debug print header for every service module. */
|
||||
ODM_DBGP_HEAD_T ODM_DBGP_Head;
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Function: DBGP_Flag_Init
|
||||
*
|
||||
* Overview: Refresh all debug print control flag content to zero.
|
||||
*
|
||||
* Input: NONE
|
||||
*
|
||||
* Output: NONE
|
||||
*
|
||||
* Return: NONE
|
||||
*
|
||||
* Revised History:
|
||||
* When Who Remark
|
||||
* 10/20/2006 MHC Create Version 0.
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
extern void ODM_DBGP_Flag_Init(void)
|
||||
{
|
||||
u1Byte i;
|
||||
|
||||
for (i = 0; i < ODM_DBGP_TYPE_MAX; i++)
|
||||
{
|
||||
ODM_DBGP_Type[i] = 0;
|
||||
}
|
||||
|
||||
#ifndef ADSL_AP_BUILD_WORKAROUND
|
||||
#if DBG
|
||||
// 2010/06/02 MH Free build driver can not out any debug message!!!
|
||||
// Init Debug flag enable condition
|
||||
|
||||
ODM_DBGP_Type[FINIT] = \
|
||||
// INIT_EEPROM |
|
||||
// INIT_TxPower |
|
||||
// INIT_IQK |
|
||||
// INIT_RF |
|
||||
0;
|
||||
|
||||
ODM_DBGP_Type[FDM] = \
|
||||
// WA_IOT |
|
||||
// DM_PWDB |
|
||||
// DM_Monitor |
|
||||
// DM_DIG |
|
||||
// DM_EDCA_Turbo |
|
||||
// DM_BT30 |
|
||||
0;
|
||||
|
||||
ODM_DBGP_Type[FIOCTL] = \
|
||||
// IOCTL_IRP |
|
||||
// IOCTL_IRP_DETAIL |
|
||||
// IOCTL_IRP_STATISTICS |
|
||||
// IOCTL_IRP_HANDLE |
|
||||
// IOCTL_BT_HCICMD |
|
||||
// IOCTL_BT_HCICMD_DETAIL |
|
||||
// IOCTL_BT_HCICMD_EXT |
|
||||
// IOCTL_BT_EVENT |
|
||||
// IOCTL_BT_EVENT_DETAIL |
|
||||
// IOCTL_BT_EVENT_PERIODICAL |
|
||||
// IOCTL_BT_TX_ACLDATA |
|
||||
// IOCTL_BT_TX_ACLDATA_DETAIL |
|
||||
// IOCTL_BT_RX_ACLDATA |
|
||||
// IOCTL_BT_RX_ACLDATA_DETAIL |
|
||||
// IOCTL_BT_TP |
|
||||
// IOCTL_STATE |
|
||||
// IOCTL_BT_LOGO |
|
||||
// IOCTL_CALLBACK_FUN |
|
||||
// IOCTL_PARSE_BT_PKT |
|
||||
0;
|
||||
|
||||
ODM_DBGP_Type[FBT] = \
|
||||
// BT_TRACE |
|
||||
0;
|
||||
|
||||
ODM_DBGP_Type[FEEPROM] = \
|
||||
// EEPROM_W |
|
||||
// EFUSE_PG |
|
||||
// EFUSE_READ_ALL |
|
||||
// EFUSE_ANALYSIS |
|
||||
// EFUSE_PG_DETAIL |
|
||||
0;
|
||||
|
||||
ODM_DBGP_Type[FDBG_CTRL] = \
|
||||
// DBG_CTRL_TRACE |
|
||||
// DBG_CTRL_INBAND_NOISE |
|
||||
0;
|
||||
|
||||
// 2011/07/20 MH Add for short cut
|
||||
ODM_DBGP_Type[FSHORT_CUT] = \
|
||||
// SHCUT_TX |
|
||||
// SHCUT_RX |
|
||||
0;
|
||||
|
||||
#endif
|
||||
#endif
|
||||
/* Define debug header of every service module. */
|
||||
//ODM_DBGP_Head.pMANS = "\n\r[MANS] ";
|
||||
//ODM_DBGP_Head.pRTOS = "\n\r[RTOS] ";
|
||||
//ODM_DBGP_Head.pALM = "\n\r[ALM] ";
|
||||
//ODM_DBGP_Head.pPEM = "\n\r[PEM] ";
|
||||
//ODM_DBGP_Head.pCMPK = "\n\r[CMPK] ";
|
||||
//ODM_DBGP_Head.pRAPD = "\n\r[RAPD] ";
|
||||
//ODM_DBGP_Head.pTXPB = "\n\r[TXPB] ";
|
||||
//ODM_DBGP_Head.pQUMG = "\n\r[QUMG] ";
|
||||
|
||||
} /* DBGP_Flag_Init */
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if 0
|
||||
u4Byte GlobalDebugLevel = DBG_LOUD;
|
||||
//
|
||||
// 2009/06/22 MH Allow Fre build to print none debug info at init time.
|
||||
//
|
||||
#if DBG
|
||||
u8Byte GlobalDebugComponents = \
|
||||
// COMP_TRACE |
|
||||
// COMP_DBG |
|
||||
// COMP_INIT |
|
||||
// COMP_OID_QUERY |
|
||||
// COMP_OID_SET |
|
||||
// COMP_RECV |
|
||||
// COMP_SEND |
|
||||
// COMP_IO |
|
||||
// COMP_POWER |
|
||||
// COMP_MLME |
|
||||
// COMP_SCAN |
|
||||
// COMP_SYSTEM |
|
||||
// COMP_SEC |
|
||||
// COMP_AP |
|
||||
// COMP_TURBO |
|
||||
// COMP_QOS |
|
||||
// COMP_AUTHENTICATOR |
|
||||
// COMP_BEACON |
|
||||
// COMP_ANTENNA |
|
||||
// COMP_RATE |
|
||||
// COMP_EVENTS |
|
||||
// COMP_FPGA |
|
||||
// COMP_RM |
|
||||
// COMP_MP |
|
||||
// COMP_RXDESC |
|
||||
// COMP_CKIP |
|
||||
// COMP_DIG |
|
||||
// COMP_TXAGC |
|
||||
// COMP_HIPWR |
|
||||
// COMP_HALDM |
|
||||
// COMP_RSNA |
|
||||
// COMP_INDIC |
|
||||
// COMP_LED |
|
||||
// COMP_RF |
|
||||
// COMP_DUALMACSWITCH |
|
||||
// COMP_EASY_CONCURRENT |
|
||||
|
||||
//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
||||
//1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
|
||||
//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
||||
|
||||
// COMP_HT |
|
||||
// COMP_POWER_TRACKING |
|
||||
// COMP_RX_REORDER |
|
||||
// COMP_AMSDU |
|
||||
// COMP_WPS |
|
||||
// COMP_RATR |
|
||||
// COMP_RESET |
|
||||
// COMP_CMD |
|
||||
// COMP_EFUSE |
|
||||
// COMP_MESH_INTERWORKING |
|
||||
// COMP_CCX |
|
||||
// COMP_IOCTL |
|
||||
// COMP_GP |
|
||||
// COMP_TXAGG |
|
||||
// COMP_BB_POWERSAVING |
|
||||
// COMP_SWAS |
|
||||
// COMP_P2P |
|
||||
// COMP_MUX |
|
||||
// COMP_FUNC |
|
||||
// COMP_TDLS |
|
||||
// COMP_OMNIPEEK |
|
||||
// COMP_PSD |
|
||||
0;
|
||||
|
||||
|
||||
#else
|
||||
#define FuncEntry
|
||||
#define FuncExit
|
||||
u8Byte GlobalDebugComponents = 0;
|
||||
#endif
|
||||
|
||||
#if (RT_PLATFORM==PLATFORM_LINUX)
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
|
||||
EXPORT_SYMBOL(GlobalDebugComponents);
|
||||
EXPORT_SYMBOL(GlobalDebugLevel);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*------------------Declare variable-----------------------
|
||||
// Define debug flag array for common debug print macro. */
|
||||
u4Byte DBGP_Type[DBGP_TYPE_MAX];
|
||||
|
||||
/* Define debug print header for every service module. */
|
||||
DBGP_HEAD_T DBGP_Head;
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Function: DBGP_Flag_Init
|
||||
*
|
||||
* Overview: Refresh all debug print control flag content to zero.
|
||||
*
|
||||
* Input: NONE
|
||||
*
|
||||
* Output: NONE
|
||||
*
|
||||
* Return: NONE
|
||||
*
|
||||
* Revised History:
|
||||
* When Who Remark
|
||||
* 10/20/2006 MHC Create Version 0.
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
extern void DBGP_Flag_Init(void)
|
||||
{
|
||||
u1Byte i;
|
||||
|
||||
for (i = 0; i < DBGP_TYPE_MAX; i++)
|
||||
{
|
||||
DBGP_Type[i] = 0;
|
||||
}
|
||||
|
||||
#if DBG
|
||||
// 2010/06/02 MH Free build driver can not out any debug message!!!
|
||||
// Init Debug flag enable condition
|
||||
|
||||
DBGP_Type[FINIT] = \
|
||||
// INIT_EEPROM |
|
||||
// INIT_TxPower |
|
||||
// INIT_IQK |
|
||||
// INIT_RF |
|
||||
0;
|
||||
|
||||
DBGP_Type[FDM] = \
|
||||
// WA_IOT |
|
||||
// DM_PWDB |
|
||||
// DM_Monitor |
|
||||
// DM_DIG |
|
||||
// DM_EDCA_Turbo |
|
||||
// DM_BT30 |
|
||||
0;
|
||||
|
||||
DBGP_Type[FIOCTL] = \
|
||||
// IOCTL_IRP |
|
||||
// IOCTL_IRP_DETAIL |
|
||||
// IOCTL_IRP_STATISTICS |
|
||||
// IOCTL_IRP_HANDLE |
|
||||
// IOCTL_BT_HCICMD |
|
||||
// IOCTL_BT_HCICMD_DETAIL |
|
||||
// IOCTL_BT_HCICMD_EXT |
|
||||
// IOCTL_BT_EVENT |
|
||||
// IOCTL_BT_EVENT_DETAIL |
|
||||
// IOCTL_BT_EVENT_PERIODICAL |
|
||||
// IOCTL_BT_TX_ACLDATA |
|
||||
// IOCTL_BT_TX_ACLDATA_DETAIL |
|
||||
// IOCTL_BT_RX_ACLDATA |
|
||||
// IOCTL_BT_RX_ACLDATA_DETAIL |
|
||||
// IOCTL_BT_TP |
|
||||
// IOCTL_STATE |
|
||||
// IOCTL_BT_LOGO |
|
||||
// IOCTL_CALLBACK_FUN |
|
||||
// IOCTL_PARSE_BT_PKT |
|
||||
0;
|
||||
|
||||
DBGP_Type[FBT] = \
|
||||
// BT_TRACE |
|
||||
0;
|
||||
|
||||
DBGP_Type[FEEPROM] = \
|
||||
// EEPROM_W |
|
||||
// EFUSE_PG |
|
||||
// EFUSE_READ_ALL |
|
||||
// EFUSE_ANALYSIS |
|
||||
// EFUSE_PG_DETAIL |
|
||||
0;
|
||||
|
||||
DBGP_Type[FDBG_CTRL] = \
|
||||
// DBG_CTRL_TRACE |
|
||||
// DBG_CTRL_INBAND_NOISE |
|
||||
0;
|
||||
|
||||
// 2011/07/20 MH Add for short cut
|
||||
DBGP_Type[FSHORT_CUT] = \
|
||||
// SHCUT_TX |
|
||||
// SHCUT_RX |
|
||||
0;
|
||||
|
||||
#endif
|
||||
/* Define debug header of every service module. */
|
||||
DBGP_Head.pMANS = "\n\r[MANS] ";
|
||||
DBGP_Head.pRTOS = "\n\r[RTOS] ";
|
||||
DBGP_Head.pALM = "\n\r[ALM] ";
|
||||
DBGP_Head.pPEM = "\n\r[PEM] ";
|
||||
DBGP_Head.pCMPK = "\n\r[CMPK] ";
|
||||
DBGP_Head.pRAPD = "\n\r[RAPD] ";
|
||||
DBGP_Head.pTXPB = "\n\r[TXPB] ";
|
||||
DBGP_Head.pQUMG = "\n\r[QUMG] ";
|
||||
|
||||
} /* DBGP_Flag_Init */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Function: DBG_PrintAllFlag
|
||||
*
|
||||
* Overview: Print All debug flag
|
||||
*
|
||||
* Input: NONE
|
||||
*
|
||||
* Output: NONE
|
||||
*
|
||||
* Return: NONE
|
||||
*
|
||||
* Revised History:
|
||||
* When Who Remark
|
||||
* 12/10/2008 MHC Create Version 0.
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
extern void DBG_PrintAllFlag(void)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 0 FQoS\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 1 FTX\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 2 FRX\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 3 FSEC\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 4 FMGNT\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 5 FMLME\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 6 FRESOURCE\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 7 FBEACON\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 8 FISR\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 9 FPHY\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 11 FMP\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 12 FPWR\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 13 FDM\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 14 FDBG_CTRL\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 15 FC2H\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 16 FBT\n"));
|
||||
} // DBG_PrintAllFlag
|
||||
|
||||
|
||||
extern void DBG_PrintAllComp(void)
|
||||
{
|
||||
u1Byte i;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("GlobalDebugComponents Definition\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT0 COMP_TRACE\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT1 COMP_DBG\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT2 COMP_INIT\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT3 COMP_OID_QUERY\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT4 COMP_OID_SET\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT5 COMP_RECV\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT6 COMP_SEND\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT7 COMP_IO\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT8 COMP_POWER\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT9 COMP_MLME\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT10 COMP_SCAN\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT11 COMP_SYSTEM\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT12 COMP_SEC\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT13 COMP_AP\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT14 COMP_TURBO\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT15 COMP_QOS\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT16 COMP_AUTHENTICATOR\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT17 COMP_BEACON\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT18 COMP_BEACON\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT19 COMP_RATE\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT20 COMP_EVENTS\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT21 COMP_FPGA\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT22 COMP_RM\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT23 COMP_MP\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT24 COMP_RXDESC\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT25 COMP_CKIP\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT26 COMP_DIG\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT27 COMP_TXAGC\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT28 COMP_HIPWR\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT29 COMP_HALDM\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT30 COMP_RSNA\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT31 COMP_INDIC\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT32 COMP_LED\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT33 COMP_RF\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT34 COMP_HT\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT35 COMP_POWER_TRACKING\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT36 COMP_POWER_TRACKING\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT37 COMP_AMSDU\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT38 COMP_WPS\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT39 COMP_RATR\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT40 COMP_RESET\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT41 COMP_CMD\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT42 COMP_EFUSE\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT43 COMP_MESH_INTERWORKING\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT43 COMP_CCX\n"));
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("GlobalDebugComponents = %"i64fmt"x\n", GlobalDebugComponents));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("Enable DBG COMP ="));
|
||||
for (i = 0; i < 64; i++)
|
||||
{
|
||||
if (GlobalDebugComponents & ((u8Byte)0x1 << i) )
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT%02d |\n", i));
|
||||
}
|
||||
}
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("\n"));
|
||||
|
||||
} // DBG_PrintAllComp
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Function: DBG_PrintFlagEvent
|
||||
*
|
||||
* Overview: Print dedicated debug flag event
|
||||
*
|
||||
* Input: NONE
|
||||
*
|
||||
* Output: NONE
|
||||
*
|
||||
* Return: NONE
|
||||
*
|
||||
* Revised History:
|
||||
* When Who Remark
|
||||
* 12/10/2008 MHC Create Version 0.
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
extern void DBG_PrintFlagEvent(u1Byte DbgFlag)
|
||||
{
|
||||
switch (DbgFlag)
|
||||
{
|
||||
case FQoS:
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 QoS_INIT\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 QoS_VISTA\n"));
|
||||
break;
|
||||
|
||||
case FTX:
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 TX_DESC\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 TX_DESC_TID\n"));
|
||||
break;
|
||||
|
||||
case FRX:
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 RX_DATA\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 RX_PHY_STS\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 RX_PHY_SS\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 RX_PHY_SQ\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 4 RX_PHY_ASTS\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 5 RX_ERR_LEN\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 6 RX_DEFRAG\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 7 RX_ERR_RATE\n"));
|
||||
break;
|
||||
|
||||
case FSEC:
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("NA\n"));
|
||||
break;
|
||||
|
||||
case FMGNT:
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("NA\n"));
|
||||
break;
|
||||
|
||||
case FMLME:
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 MEDIA_STS\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 LINK_STS\n"));
|
||||
break;
|
||||
|
||||
case FRESOURCE:
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 OS_CHK\n"));
|
||||
break;
|
||||
|
||||
case FBEACON:
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 BCN_SHOW\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 BCN_PEER\n"));
|
||||
break;
|
||||
|
||||
case FISR:
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 ISR_CHK\n"));
|
||||
break;
|
||||
|
||||
case FPHY:
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 PHY_BBR\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 PHY_BBW\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 PHY_RFR\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 PHY_RFW\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 4 PHY_MACR\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 5 PHY_MACW\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 6 PHY_ALLR\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 7 PHY_ALLW\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 8 PHY_TXPWR\n"));
|
||||
break;
|
||||
|
||||
case FMP:
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 MP_RX\n"));
|
||||
break;
|
||||
|
||||
case FEEPROM:
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 EEPROM_W\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 EFUSE_PG\n"));
|
||||
break;
|
||||
|
||||
case FPWR:
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 LPS\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 IPS\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 PWRSW\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 PWRHW\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 4 PWRHAL\n"));
|
||||
break;
|
||||
|
||||
case FDM:
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 WA_IOT\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 DM_PWDB\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 DM_Monitor\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 DM_DIG\n"));
|
||||
break;
|
||||
|
||||
case FDBG_CTRL:
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 DBG_CTRL_TRACE\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 DBG_CTRL_INBAND_NOISE\n"));
|
||||
break;
|
||||
|
||||
case FC2H:
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 C2H_Summary\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 C2H_PacketData\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 C2H_ContentData\n"));
|
||||
break;
|
||||
|
||||
case FBT:
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 BT_TRACE\n"));
|
||||
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 BT_RFPoll\n"));
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
} // DBG_PrintFlagEvent
|
||||
|
||||
|
||||
extern void DBG_DumpMem(const u1Byte DbgComp,
|
||||
const u1Byte DbgLevel,
|
||||
pu1Byte pMem,
|
||||
u2Byte Len)
|
||||
{
|
||||
u2Byte i;
|
||||
|
||||
for (i=0;i<((Len>>3) + 1);i++)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,DbgComp, DbgLevel, ("%02X %02X %02X %02X %02X %02X %02X %02X\n",
|
||||
*(pMem+(i*8)), *(pMem+(i*8+1)), *(pMem+(i*8+2)), *(pMem+(i*8+3)),
|
||||
*(pMem+(i*8+4)), *(pMem+(i*8+5)), *(pMem+(i*8+6)), *(pMem+(i*8+7))));
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
u32 GlobalDebugLevel;
|
||||
|
||||
|
|
|
|||
|
|
@ -2030,7 +2030,6 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
|
|||
|
||||
//tynli_test_tx_report.
|
||||
rtw_write16(Adapter, REG_TX_RPT_TIME, 0x3DF0);
|
||||
//RT_TRACE(COMP_INIT, DBG_TRACE, ("InitializeAdapter8188EUsb() <====\n"));
|
||||
|
||||
//enable tx DMA to drop the redundate data of packet
|
||||
rtw_write16(Adapter,REG_TXDMA_OFFSET_CHK, (rtw_read16(Adapter,REG_TXDMA_OFFSET_CHK) | DROP_DATA_EN));
|
||||
|
|
@ -2113,7 +2112,7 @@ CardDisableRTL8188EU(
|
|||
u32 val32;
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
|
||||
RT_TRACE(COMP_INIT, DBG_LOUD, ("CardDisableRTL8188EU\n"));
|
||||
RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("CardDisableRTL8188EU\n"));
|
||||
|
||||
//Stop Tx Report Timer. 0x4EC[Bit1]=b'0
|
||||
val8 = rtw_read8(Adapter, REG_TX_RPT_CTRL);
|
||||
|
|
@ -2127,25 +2126,16 @@ CardDisableRTL8188EU(
|
|||
|
||||
|
||||
// 2. 0x1F[7:0] = 0 // turn off RF
|
||||
//rtw_write8(Adapter, REG_RF_CTRL, 0x00);
|
||||
|
||||
val8 = rtw_read8(Adapter, REG_MCUFWDL);
|
||||
if ((val8 & RAM_DL_SEL) && Adapter->bFWReady) //8051 RAM code
|
||||
{
|
||||
//rtl8723a_FirmwareSelfReset(padapter);
|
||||
//_8051Reset88E(padapter);
|
||||
|
||||
// Reset MCU 0x2[10]=0.
|
||||
val8 = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
|
||||
val8 &= ~BIT(2); // 0x2[10], FEN_CPUEN
|
||||
rtw_write8(Adapter, REG_SYS_FUNC_EN+1, val8);
|
||||
}
|
||||
|
||||
//val8 = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
|
||||
//val8 &= ~BIT(2); // 0x2[10], FEN_CPUEN
|
||||
//rtw_write8(Adapter, REG_SYS_FUNC_EN+1, val8);
|
||||
|
||||
// MCUFWDL 0x80[1:0]=0
|
||||
// reset MCU ready status
|
||||
rtw_write8(Adapter, REG_MCUFWDL, 0);
|
||||
|
||||
|
|
@ -2163,23 +2153,16 @@ CardDisableRTL8188EU(
|
|||
val8 = rtw_read8(Adapter, REG_RSV_CTRL+1);
|
||||
rtw_write8(Adapter, REG_RSV_CTRL+1, val8|BIT3);
|
||||
|
||||
#if 0
|
||||
// 7. RSV_CTRL 0x1C[7:0] = 0x0E // lock ISO/CLK/Power control register
|
||||
rtw_write8(Adapter, REG_RSV_CTRL, 0x0e);
|
||||
#endif
|
||||
#if 1
|
||||
//YJ,test add, 111207. For Power Consumption.
|
||||
val8 = rtw_read8(Adapter, GPIO_IN);
|
||||
rtw_write8(Adapter, GPIO_OUT, val8);
|
||||
rtw_write8(Adapter, GPIO_IO_SEL, 0xFF);//Reg0x46
|
||||
|
||||
val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL);
|
||||
//rtw_write8(Adapter, REG_GPIO_IO_SEL, (val8<<4)|val8);
|
||||
rtw_write8(Adapter, REG_GPIO_IO_SEL, (val8<<4));
|
||||
val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL+1);
|
||||
rtw_write8(Adapter, REG_GPIO_IO_SEL+1, val8|0x0F);//Reg0x43
|
||||
rtw_write32(Adapter, REG_BB_PAD_CTRL, 0x00080808);//set LNA ,TRSW,EX_PA Pin to output mode
|
||||
#endif
|
||||
pHalData->bMacPwrCtrlOn = _FALSE;
|
||||
Adapter->bFWReady = _FALSE;
|
||||
}
|
||||
|
|
@ -2247,16 +2230,15 @@ _func_enter_;
|
|||
|
||||
status = _SUCCESS;
|
||||
|
||||
RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("===> usb_inirp_init\n"));
|
||||
RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
|
||||
("===> usb_inirp_init\n"));
|
||||
|
||||
precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR;
|
||||
|
||||
//issue Rx irp to receive data
|
||||
precvbuf = (struct recv_buf *)precvpriv->precv_buf;
|
||||
for (i=0; i<NR_RECVBUFF; i++)
|
||||
{
|
||||
if (_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == _FALSE )
|
||||
{
|
||||
for (i = 0; i < NR_RECVBUFF; i++) {
|
||||
if (_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == _FALSE ) {
|
||||
RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_port error\n"));
|
||||
status = _FAIL;
|
||||
goto exit;
|
||||
|
|
@ -2267,16 +2249,16 @@ _func_enter_;
|
|||
}
|
||||
|
||||
#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
|
||||
if (pHalData->RtIntInPipe != 0x05)
|
||||
{
|
||||
if (pHalData->RtIntInPipe != 0x05) {
|
||||
status = _FAIL;
|
||||
DBG_871X("%s =>Warning !! Have not USB Int-IN pipe, pHalData->RtIntInPipe(%d)!!!\n",__func__,pHalData->RtIntInPipe);
|
||||
DBG_871X("%s =>Warning !! Have not USB Int-IN pipe, pHalData->RtIntInPipe(%d)!!!\n",
|
||||
__func__,i pHalData->RtIntInPipe);
|
||||
goto exit;
|
||||
}
|
||||
_read_interrupt = pintfhdl->io_ops._read_interrupt;
|
||||
if (_read_interrupt(pintfhdl, RECV_INT_IN_ADDR) == _FALSE )
|
||||
{
|
||||
RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_interrupt error\n"));
|
||||
if (_read_interrupt(pintfhdl, RECV_INT_IN_ADDR) == _FALSE ) {
|
||||
RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
|
||||
("usb_rx_init: usb_read_interrupt error\n"));
|
||||
status = _FAIL;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -25,16 +25,15 @@
|
|||
#include <drv_types.h>
|
||||
|
||||
|
||||
#define _drv_always_ 1
|
||||
#define _drv_always_ 1
|
||||
#define _drv_emerg_ 2
|
||||
#define _drv_alert_ 3
|
||||
#define _drv_crit_ 4
|
||||
#define _drv_err_ 5
|
||||
#define _drv_warning_ 6
|
||||
#define _drv_notice_ 7
|
||||
#define _drv_warning_ 6
|
||||
#define _drv_notice_ 7
|
||||
#define _drv_info_ 8
|
||||
#define _drv_dump_ 9
|
||||
#define _drv_debug_ 10
|
||||
#define _drv_debug_ 9
|
||||
|
||||
|
||||
#define _module_rtl871x_xmit_c_ BIT(0)
|
||||
|
|
@ -43,30 +42,29 @@
|
|||
#define _module_recv_osdep_c_ BIT(3)
|
||||
#define _module_rtl871x_mlme_c_ BIT(4)
|
||||
#define _module_mlme_osdep_c_ BIT(5)
|
||||
#define _module_rtl871x_sta_mgt_c_ BIT(6)
|
||||
#define _module_rtl871x_cmd_c_ BIT(7)
|
||||
#define _module_rtl871x_sta_mgt_c_ BIT(6)
|
||||
#define _module_rtl871x_cmd_c_ BIT(7)
|
||||
#define _module_cmd_osdep_c_ BIT(8)
|
||||
#define _module_rtl871x_io_c_ BIT(9)
|
||||
#define _module_rtl871x_io_c_ BIT(9)
|
||||
#define _module_io_osdep_c_ BIT(10)
|
||||
#define _module_os_intfs_c_ BIT(11)
|
||||
#define _module_rtl871x_security_c_ BIT(12)
|
||||
#define _module_rtl871x_eeprom_c_ BIT(13)
|
||||
#define _module_os_intfs_c_ BIT(11)
|
||||
#define _module_rtl871x_security_c_ BIT(12)
|
||||
#define _module_rtl871x_eeprom_c_ BIT(13)
|
||||
#define _module_hal_init_c_ BIT(14)
|
||||
#define _module_hci_hal_init_c_ BIT(15)
|
||||
#define _module_rtl871x_ioctl_c_ BIT(16)
|
||||
#define _module_rtl871x_ioctl_set_c_ BIT(17)
|
||||
#define _module_rtl871x_ioctl_c_ BIT(16)
|
||||
#define _module_rtl871x_ioctl_set_c_ BIT(17)
|
||||
#define _module_rtl871x_ioctl_query_c_ BIT(18)
|
||||
#define _module_rtl871x_pwrctrl_c_ BIT(19)
|
||||
#define _module_hci_intfs_c_ BIT(20)
|
||||
#define _module_hci_ops_c_ BIT(21)
|
||||
#define _module_osdep_service_c_ BIT(22)
|
||||
#define _module_rtl871x_pwrctrl_c_ BIT(19)
|
||||
#define _module_hci_intfs_c_ BIT(20)
|
||||
#define _module_hci_ops_c_ BIT(21)
|
||||
#define _module_osdep_service_c_ BIT(22)
|
||||
#define _module_mp_ BIT(23)
|
||||
#define _module_hci_ops_os_c_ BIT(24)
|
||||
#define _module_rtl871x_ioctl_os_c BIT(25)
|
||||
#define _module_hci_ops_os_c_ BIT(24)
|
||||
#define _module_rtl871x_ioctl_os_c BIT(25)
|
||||
#define _module_rtl8712_cmd_c_ BIT(26)
|
||||
//#define _module_efuse_ BIT(27)
|
||||
#define _module_rtl8192c_xmit_c_ BIT(28)
|
||||
#define _module_hal_xmit_c_ BIT(28)
|
||||
#define _module_rtl8192c_xmit_c_ BIT(27)
|
||||
#define _module_hal_xmit_c_ BIT(28)
|
||||
#define _module_efuse_ BIT(29)
|
||||
#define _module_rtl8712_recv_c_ BIT(30)
|
||||
#define _module_rtl8712_led_c_ BIT(31)
|
||||
|
|
@ -151,134 +149,78 @@
|
|||
#define _MODULE_DEFINE_ _module_efuse_
|
||||
#endif
|
||||
|
||||
#ifdef PLATFORM_OS_CE
|
||||
extern void rtl871x_cedbg(const char *fmt, ...);
|
||||
#endif
|
||||
|
||||
#define RT_TRACE(_Comp, _Level, Fmt) do{}while (0)
|
||||
#define _func_enter_ do{}while (0)
|
||||
#define _func_exit_ do{}while (0)
|
||||
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) do{}while (0)
|
||||
|
||||
#ifdef PLATFORM_WINDOWS
|
||||
#define DBG_871X do {} while (0)
|
||||
#define MSG_8192C do {} while (0)
|
||||
#define DBG_8192C do {} while (0)
|
||||
#define DBG_871X_LEVEL do {} while (0)
|
||||
#ifdef pr_info
|
||||
#define _dbgdump pr_info
|
||||
#else
|
||||
#define DBG_871X(x, ...) do {} while (0)
|
||||
#define MSG_8192C(x, ...) do {} while (0)
|
||||
#define DBG_8192C(x,...) do {} while (0)
|
||||
#define DBG_871X_LEVEL(x,...) do {} while (0)
|
||||
#define _dbgdump printk
|
||||
#endif
|
||||
|
||||
#undef _dbgdump
|
||||
#ifdef PLATFORM_WINDOWS
|
||||
#define DRIVER_PREFIX "RTL8188: "
|
||||
|
||||
#ifdef PLATFORM_OS_XP
|
||||
#define _dbgdump DbgPrint
|
||||
#elif defined PLATFORM_OS_CE
|
||||
#define _dbgdump rtl871x_cedbg
|
||||
#endif
|
||||
#define DBG_871X_LEVEL(_Level, fmt, arg...) \
|
||||
do { \
|
||||
if (_Level <= GlobalDebugLevel) \
|
||||
_dbgdump(DRIVER_PREFIX"ERROR " fmt, ##arg); \
|
||||
} while (0)
|
||||
|
||||
#elif defined PLATFORM_LINUX
|
||||
#define _dbgdump printk
|
||||
#elif defined PLATFORM_FREEBSD
|
||||
#define _dbgdump printf
|
||||
#endif
|
||||
#define DBG_871X(...) \
|
||||
do { \
|
||||
_dbgdump(DRIVER_PREFIX __VA_ARGS__); \
|
||||
} while (0)
|
||||
|
||||
#define DRIVER_PREFIX "RTL871X: "
|
||||
#define DEBUG_LEVEL (_drv_err_)
|
||||
#if defined (_dbgdump)
|
||||
#undef DBG_871X_LEVEL
|
||||
#define DBG_871X_LEVEL(level, fmt, arg...) \
|
||||
do {\
|
||||
if (level <= DEBUG_LEVEL) {\
|
||||
if (level <= _drv_err_ && level > _drv_always_) \
|
||||
_dbgdump(DRIVER_PREFIX"ERROR " fmt, ##arg);\
|
||||
else \
|
||||
_dbgdump(DRIVER_PREFIX fmt, ##arg);\
|
||||
}\
|
||||
}while (0)
|
||||
#endif
|
||||
#define MSG_8192C(...) \
|
||||
do { \
|
||||
_dbgdump(DRIVER_PREFIX __VA_ARGS__); \
|
||||
} while (0)
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#if defined (_dbgdump)
|
||||
#undef DBG_871X
|
||||
#define DBG_871X(...) do {\
|
||||
_dbgdump(DRIVER_PREFIX __VA_ARGS__);\
|
||||
}while (0)
|
||||
#define DBG_8192C(...) \
|
||||
do { \
|
||||
_dbgdump(DRIVER_PREFIX __VA_ARGS__); \
|
||||
} while (0)
|
||||
|
||||
#undef MSG_8192C
|
||||
#define MSG_8192C(...) do {\
|
||||
_dbgdump(DRIVER_PREFIX __VA_ARGS__);\
|
||||
}while (0)
|
||||
|
||||
#undef DBG_8192C
|
||||
#define DBG_8192C(...) do {\
|
||||
_dbgdump(DRIVER_PREFIX __VA_ARGS__);\
|
||||
}while (0)
|
||||
#endif
|
||||
#endif /* CONFIG_DEBUG */
|
||||
|
||||
#ifdef CONFIG_DEBUG_RTL871X
|
||||
#ifndef _RTL871X_DEBUG_C_
|
||||
extern u32 GlobalDebugLevel;
|
||||
extern u64 GlobalDebugComponents;
|
||||
#endif
|
||||
|
||||
#if defined (_dbgdump) && defined (_MODULE_DEFINE_)
|
||||
|
||||
#undef RT_TRACE
|
||||
#define RT_TRACE(_Comp, _Level, Fmt)\
|
||||
do {\
|
||||
if ((_Comp & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) {\
|
||||
_dbgdump("%s [0x%08x,%d]", DRIVER_PREFIX, (unsigned int)_Comp, _Level);\
|
||||
_dbgdump Fmt;\
|
||||
}\
|
||||
}while (0)
|
||||
|
||||
#endif
|
||||
extern u32 GlobalDebugLevel;
|
||||
|
||||
|
||||
#if defined (_dbgdump)
|
||||
#define RT_TRACE(_Comp, _Level, Fmt) \
|
||||
do { \
|
||||
if (_Level <= GlobalDebugLevel) { \
|
||||
_dbgdump("%s [0x%08x,%d]", DRIVER_PREFIX, \
|
||||
(unsigned int)_Comp, _Level); \
|
||||
_dbgdump Fmt; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#undef _func_enter_
|
||||
#define _func_enter_ \
|
||||
do { \
|
||||
if (GlobalDebugLevel >= _drv_debug_) \
|
||||
{ \
|
||||
_dbgdump("\n %s : %s enters at %d\n", DRIVER_PREFIX, __func__, __LINE__);\
|
||||
} \
|
||||
} while (0)
|
||||
#define _func_enter_ \
|
||||
do { \
|
||||
if (GlobalDebugLevel >= _drv_debug_) \
|
||||
_dbgdump("%s : %s enters at %d\n", \
|
||||
DRIVER_PREFIX, __func__, __LINE__); \
|
||||
} while (0)
|
||||
|
||||
#undef _func_exit_
|
||||
#define _func_exit_ \
|
||||
do { \
|
||||
if (GlobalDebugLevel >= _drv_debug_) \
|
||||
{ \
|
||||
_dbgdump("\n %s : %s exits at %d\n", DRIVER_PREFIX, __func__, __LINE__); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#undef RT_PRINT_DATA
|
||||
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) \
|
||||
if (((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
|
||||
{ \
|
||||
int __i; \
|
||||
u8 *ptr = (u8 *)_HexData; \
|
||||
_dbgdump("%s", DRIVER_PREFIX); \
|
||||
_dbgdump(_TitleString); \
|
||||
for ( __i=0; __i<(int)_HexDataLen; __i++ ) \
|
||||
{ \
|
||||
_dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" "); \
|
||||
if (((__i + 1) % 16) == 0) _dbgdump("\n"); \
|
||||
} \
|
||||
_dbgdump("\n"); \
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_DEBUG_RTL871X */
|
||||
#define _func_exit_ \
|
||||
do { \
|
||||
if (GlobalDebugLevel >= _drv_debug_) \
|
||||
_dbgdump("%s : %s exits at %d\n", \
|
||||
DRIVER_PREFIX, __func__, __LINE__); \
|
||||
} while (0)
|
||||
|
||||
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)\
|
||||
do { \
|
||||
if (_Level <= GlobalDebugLevel) { \
|
||||
int __i; \
|
||||
u8 *ptr = (u8 *)_HexData; \
|
||||
_dbgdump("%s", DRIVER_PREFIX); \
|
||||
_dbgdump(_TitleString); \
|
||||
for (__i = 0; __i < (int)_HexDataLen; __i++ ) { \
|
||||
_dbgdump("%02X%s", ptr[__i], \
|
||||
(((__i + 1) % 4) == 0) ? \
|
||||
" " : " "); \
|
||||
if (((__i + 1) % 16) == 0) \
|
||||
printk("\n"); \
|
||||
} \
|
||||
printk("\n"); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#ifdef CONFIG_PROC_DEBUG
|
||||
|
||||
|
|
|
|||
|
|
@ -96,6 +96,7 @@ int rtw_early_mode=1;
|
|||
module_param(rtw_ips_mode, int, 0644);
|
||||
MODULE_PARM_DESC(rtw_ips_mode,"The default IPS mode");
|
||||
|
||||
static int rtw_debug = 1;
|
||||
int rtw_radio_enable = 1;
|
||||
int rtw_long_retry_lmt = 7;
|
||||
int rtw_short_retry_lmt = 7;
|
||||
|
|
@ -285,6 +286,8 @@ MODULE_PARM_DESC(rtw_btcoex_enable, "Enable BT co-existence mechanism");
|
|||
uint rtw_notch_filter = RTW_NOTCH_FILTER;
|
||||
module_param(rtw_notch_filter, uint, 0644);
|
||||
MODULE_PARM_DESC(rtw_notch_filter, "0:Disable, 1:Enable, 2:Enable only for P2P");
|
||||
module_param_named(debug, rtw_debug, int, 0444);
|
||||
MODULE_PARM_DESC(debug, "Set debug level (1-9) (default 1)");
|
||||
|
||||
static uint loadparam(PADAPTER padapter, _nic_hdl pnetdev);
|
||||
int _netdev_open(struct net_device *pnetdev);
|
||||
|
|
@ -743,10 +746,10 @@ uint loadparam( _adapter *padapter, _nic_hdl pnetdev)
|
|||
|
||||
_func_enter_;
|
||||
|
||||
GlobalDebugLevel = rtw_debug;
|
||||
registry_par->chip_version = (u8)rtw_chip_version;
|
||||
registry_par->rfintfs = (u8)rtw_rfintfs;
|
||||
registry_par->lbkmode = (u8)rtw_lbkmode;
|
||||
//registry_par->hci = (u8)hci;
|
||||
registry_par->network_mode = (u8)rtw_network_mode;
|
||||
|
||||
_rtw_memcpy(registry_par->ssid.Ssid, "ANY", 3);
|
||||
|
|
|
|||
|
|
@ -291,10 +291,11 @@ _func_enter_;
|
|||
|
||||
skb->len = precv_frame->u.hdr.len;
|
||||
|
||||
RT_TRACE(_module_recv_osdep_c_,_drv_info_,("\n skb->head=%p skb->data=%p skb->tail=%p skb->end=%p skb->len=%d\n", skb->head, skb->data, skb->tail, skb->end, skb->len));
|
||||
RT_TRACE(_module_recv_osdep_c_,_drv_info_,
|
||||
("skb->head=%p skb->data=%p skb->tail=%p skb->end=%p skb->len=%d\n",
|
||||
skb->head, skb->data, skb_tail_pointer(skb), skb_end_pointer(skb), skb->len));
|
||||
|
||||
if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
|
||||
{
|
||||
if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
|
||||
_pkt *pskb2=NULL;
|
||||
struct sta_info *psta = NULL;
|
||||
struct sta_priv *pstapriv = &padapter->stapriv;
|
||||
|
|
@ -303,12 +304,8 @@ _func_enter_;
|
|||
|
||||
//DBG_871X("bmcast=%d\n", bmcast);
|
||||
|
||||
if (_rtw_memcmp(pattrib->dst, myid(&padapter->eeprompriv), ETH_ALEN)==_FALSE)
|
||||
{
|
||||
//DBG_871X("not ap psta=%p, addr=%pM\n", psta, pattrib->dst);
|
||||
|
||||
if (bmcast)
|
||||
{
|
||||
if (_rtw_memcmp(pattrib->dst, myid(&padapter->eeprompriv), ETH_ALEN)==_FALSE) {
|
||||
if (bmcast) {
|
||||
psta = rtw_get_bcmc_stainfo(padapter);
|
||||
pskb2 = skb_clone(skb, GFP_ATOMIC);
|
||||
} else {
|
||||
|
|
|
|||
Loading…
Reference in a new issue