diff --git a/hal/Hal8188EFWImg_CE.h b/hal/Hal8188EFWImg_CE.h index 2328ec3..af2dd43 100755 --- a/hal/Hal8188EFWImg_CE.h +++ b/hal/Hal8188EFWImg_CE.h @@ -20,10 +20,10 @@ #ifndef __INC_HAL8188E_FW_IMG_H #define __INC_HAL8188E_FW_IMG_H -//V10(1641) +/* V10(1641) */ #define Rtl8188EFWImgArrayLength 13904 extern const u8 Rtl8188EFwImgArray[Rtl8188EFWImgArrayLength]; -#endif //__INC_HAL8188E_FW_IMG_H +#endif /* __INC_HAL8188E_FW_IMG_H */ diff --git a/hal/Hal8188EPwrSeq.c b/hal/Hal8188EPwrSeq.c index 06b9813..29c2b60 100755 --- a/hal/Hal8188EPwrSeq.c +++ b/hal/Hal8188EPwrSeq.c @@ -24,21 +24,21 @@ /* drivers should parse below arrays and do the corresponding actions */ -//3 Power on Array +/* 3 Power on Array */ WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]= { RTL8188E_TRANS_CARDEMU_TO_ACT RTL8188E_TRANS_END }; -//3Radio off Array +/* 3Radio off Array */ WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS]= { RTL8188E_TRANS_ACT_TO_CARDEMU RTL8188E_TRANS_END }; -//3Card Disable Array +/* 3Card Disable Array */ WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]= { RTL8188E_TRANS_ACT_TO_CARDEMU @@ -46,7 +46,7 @@ WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8 RTL8188E_TRANS_END }; -//3 Card Enable Array +/* 3 Card Enable Array */ WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]= { RTL8188E_TRANS_CARDDIS_TO_CARDEMU @@ -54,7 +54,7 @@ WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL81 RTL8188E_TRANS_END }; -//3Suspend Array +/* 3Suspend Array */ WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]= { RTL8188E_TRANS_ACT_TO_CARDEMU @@ -62,7 +62,7 @@ WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_ RTL8188E_TRANS_END }; -//3 Resume Array +/* 3 Resume Array */ WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]= { RTL8188E_TRANS_SUS_TO_CARDEMU @@ -71,7 +71,7 @@ WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_T }; -//3HWPDN Array +/* 3HWPDN Array */ WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]= { RTL8188E_TRANS_ACT_TO_CARDEMU @@ -79,18 +79,18 @@ WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TR RTL8188E_TRANS_END }; -//3 Enter LPS +/* 3 Enter LPS */ WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS]= { - //FW behavior + /* FW behavior */ RTL8188E_TRANS_ACT_TO_LPS RTL8188E_TRANS_END }; -//3 Leave LPS +/* 3 Leave LPS */ WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]= { - //FW behavior + /* FW behavior */ RTL8188E_TRANS_LPS_TO_ACT RTL8188E_TRANS_END }; diff --git a/hal/Hal8188ERateAdaptive.c b/hal/Hal8188ERateAdaptive.c index 4b380b5..6eb530b 100755 --- a/hal/Hal8188ERateAdaptive.c +++ b/hal/Hal8188ERateAdaptive.c @@ -16,47 +16,47 @@ Major Change History: #include "odm_precomp.h" #if (RATE_ADAPTIVE_SUPPORT == 1) -// Rate adaptive parameters +/* Rate adaptive parameters */ -static u8 RETRY_PENALTY[PERENTRY][RETRYSIZE+1] = {{5,4,3,2,0,3},//92 , idx=0 - {6,5,4,3,0,4},//86 , idx=1 - {6,5,4,2,0,4},//81 , idx=2 - {8,7,6,4,0,6},//75 , idx=3 - {10,9,8,6,0,8},//71 , idx=4 - {10,9,8,4,0,8},//66 , idx=5 - {10,9,8,2,0,8},//62 , idx=6 - {10,9,8,0,0,8},//59 , idx=7 - {18,17,16,8,0,16},//53 , idx=8 - {26,25,24,16,0,24},//50 , idx=9 - {34,33,32,24,0,32},//47 , idx=0x0a - {34,31,28,20,0,32},//43 , idx=0x0b - {34,31,27,18,0,32},//40 , idx=0x0c - {34,31,26,16,0,32},//37 , idx=0x0d - {34,30,22,16,0,32},//32 , idx=0x0e - {34,30,24,16,0,32},//26 , idx=0x0f - {49,46,40,16,0,48},//20 , idx=0x10 - {49,45,32,0,0,48},//17 , idx=0x11 - {49,45,22,18,0,48},//15 , idx=0x12 - {49,40,24,16,0,48},//12 , idx=0x13 - {49,32,18,12,0,48},//9 , idx=0x14 - {49,22,18,14,0,48},//6 , idx=0x15 - {49,16,16,0,0,48}};//3 //3, idx=0x16 +static u8 RETRY_PENALTY[PERENTRY][RETRYSIZE+1] = {{5,4,3,2,0,3},/* 92 , idx=0 */ + {6,5,4,3,0,4},/* 86 , idx=1 */ + {6,5,4,2,0,4},/* 81 , idx=2 */ + {8,7,6,4,0,6},/* 75 , idx=3 */ + {10,9,8,6,0,8},/* 71 , idx=4 */ + {10,9,8,4,0,8},/* 66 , idx=5 */ + {10,9,8,2,0,8},/* 62 , idx=6 */ + {10,9,8,0,0,8},/* 59 , idx=7 */ + {18,17,16,8,0,16},/* 53 , idx=8 */ + {26,25,24,16,0,24},/* 50 , idx=9 */ + {34,33,32,24,0,32},/* 47 , idx=0x0a */ + {34,31,28,20,0,32},/* 43 , idx=0x0b */ + {34,31,27,18,0,32},/* 40 , idx=0x0c */ + {34,31,26,16,0,32},/* 37 , idx=0x0d */ + {34,30,22,16,0,32},/* 32 , idx=0x0e */ + {34,30,24,16,0,32},/* 26 , idx=0x0f */ + {49,46,40,16,0,48},/* 20 , idx=0x10 */ + {49,45,32,0,0,48},/* 17 , idx=0x11 */ + {49,45,22,18,0,48},/* 15 , idx=0x12 */ + {49,40,24,16,0,48},/* 12 , idx=0x13 */ + {49,32,18,12,0,48},/* 9 , idx=0x14 */ + {49,22,18,14,0,48},/* 6 , idx=0x15 */ + {49,16,16,0,0,48}};/* 3 idx=0x16 */ -static u8 RETRY_PENALTY_UP[RETRYSIZE+1]={49,44,16,16,0,48}; // 12% for rate up +static u8 RETRY_PENALTY_UP[RETRYSIZE+1]={49,44,16,16,0,48}; /* 12% for rate up */ static u8 PT_PENALTY[RETRYSIZE+1]={34,31,30,24,0,32}; -// wilson modify -static u8 RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH +/* wilson modify */ +static u8 RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, /* SS>TH */ 4,4,4,4,6,0x0a,0x0b,0x0d, - 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 - {0x0a,0x0a,0x0b,0x0c,0x0a,0x0a,0x0b,0x0c,0x0d,0x10,0x13,0x14, // SSTH +static u8 RETRY_PENALTY_UP_IDX[RATESIZE] = {0x0c,0x0d,0x0d,0x0f,0x0d,0x0e,0x0f,0x0f,0x10,0x12,0x13,0x14, /* SS>TH */ 0x0f,0x10,0x10,0x12,0x12,0x13,0x14,0x15, 0x11,0x11,0x12,0x13,0x13,0x13,0x14,0x15}; @@ -76,32 +76,32 @@ static u16 N_THRESHOLD_LOW[RATESIZE] = {2,2,4,8, static u8 TRYING_NECESSARY[RATESIZE] = {2,2,2,2, 2,2,3,3,4,4,5,7, 4,4,7,10,10,12,12,18, - 5,7,7,8,11,18,36,60}; // 0329 // 1207 + 5,7,7,8,11,18,36,60}; /* 0329 */ static u8 DROPING_NECESSARY[RATESIZE] = {1,1,1,1, 1,2,3,4,5,6,7,8, 1,2,3,4,5,6,7,8, 5,6,7,8,9,10,11,12}; -static u32 INIT_RATE_FALLBACK_TABLE[16]={0x0f8ff015, // 0: 40M BGN mode - 0x0f8ff010, // 1: 40M GN mode - 0x0f8ff005, // 2: BN mode/ 40M BGN mode - 0x0f8ff000, // 3: N mode - 0x00000ff5, // 4: BG mode - 0x00000ff0, // 5: G mode - 0x0000000d, // 6: B mode - 0, // 7: - 0, // 8: - 0, // 9: - 0, // 10: - 0, // 11: - 0, // 12: - 0, // 13: - 0, // 14: - 0, // 15: +static u32 INIT_RATE_FALLBACK_TABLE[16]={0x0f8ff015, /* 0: 40M BGN mode */ + 0x0f8ff010, /* 1: 40M GN mode */ + 0x0f8ff005, /* 2: BN mode/ 40M BGN mode */ + 0x0f8ff000, /* 3: N mode */ + 0x00000ff5, /* 4: BG mode */ + 0x00000ff0, /* 5: G mode */ + 0x0000000d, /* 6: B mode */ + 0, /* 7: */ + 0, /* 8: */ + 0, /* 9: */ + 0, /* 10: */ + 0, /* 11: */ + 0, /* 12: */ + 0, /* 13: */ + 0, /* 14: */ + 0, /* 15: */ }; static u8 PendingForRateUpFail[5]={2,10,24,40,60}; -static u16 DynamicTxRPTTiming[6]={0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12 ,0x927c}; // 200ms-1200ms +static u16 DynamicTxRPTTiming[6]={0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12 ,0x927c}; /* 200ms-1200ms */ -// End Rate adaptive parameters +/* End Rate adaptive parameters */ static void odm_SetTxRPTTiming_8188E( @@ -116,14 +116,14 @@ odm_SetTxRPTTiming_8188E( if(DynamicTxRPTTiming[idx] == pRaInfo->RptTime) break; - if (extend==0) // back to default timing - idx=0; //200ms - else if (extend==1) {// increase the timing + if (extend==0) /* back to default timing */ + idx=0; /* 200ms */ + else if (extend==1) {/* increase the timing */ idx+=1; if (idx>5) idx=5; } - else if (extend==2) {// decrease the timing + else if (extend==2) {/* decrease the timing */ if(idx!=0) idx-=1; } @@ -254,13 +254,13 @@ odm_RateUp_8188E( else if((pRaInfo->SGIEnable) !=1 ) pRaInfo->RateSGI = 0; } - else //if((sta_info_ra->Decision_rate) > (sta_info_ra->Highest_rate)) + else /* if((sta_info_ra->Decision_rate) > (sta_info_ra->Highest_rate)) */ { RateID = HighestRate; } RateUpfinish: - //if(pRaInfo->RAWaitingCounter==10) + /* if(pRaInfo->RAWaitingCounter==10) */ if(pRaInfo->RAWaitingCounter==(4+PendingForRateUpFail[pRaInfo->RAPendingCounter])) pRaInfo->RAWaitingCounter=0; else @@ -287,18 +287,18 @@ odm_RateDecision_8188E( ) { u8 RateID = 0, RtyPtID = 0, PenaltyID1 = 0, PenaltyID2 = 0; - //u32 pool_retry; + /* u32 pool_retry; */ static u8 DynamicTxRPTTimingCounter=0; ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateDecision_8188E() \n")); - if (pRaInfo->Active && (pRaInfo->TOTAL > 0)) // STA used and data packet exits + if (pRaInfo->Active && (pRaInfo->TOTAL > 0)) /* STA used and data packet exits */ { if ( (pRaInfo->RssiStaRA<(pRaInfo->PreRssiStaRA-3))|| (pRaInfo->RssiStaRA>(pRaInfo->PreRssiStaRA+3))){ pRaInfo->RAWaitingCounter=0; pRaInfo->RAPendingCounter=0; } - // Start RA decision + /* Start RA decision */ if (pRaInfo->PreRate > pRaInfo->HighestRate) RateID = pRaInfo->HighestRate; else @@ -307,11 +307,11 @@ odm_RateDecision_8188E( RtyPtID=0; else RtyPtID=1; - PenaltyID1 = RETRY_PENALTY_IDX[RtyPtID][RateID]; //TODO by page + PenaltyID1 = RETRY_PENALTY_IDX[RtyPtID][RateID]; /* TODO by page */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, (" NscDown init is %d\n", pRaInfo->NscDown)); - //pool_retry=pRaInfo->RTY[2]+pRaInfo->RTY[3]+pRaInfo->RTY[4]+pRaInfo->DROP; + /* pool_retry=pRaInfo->RTY[2]+pRaInfo->RTY[3]+pRaInfo->RTY[4]+pRaInfo->DROP; */ pRaInfo->NscDown += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID1][0]; pRaInfo->NscDown += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID1][1]; pRaInfo->NscDown += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID1][2]; @@ -325,7 +325,7 @@ odm_RateDecision_8188E( else pRaInfo->NscDown=0; - // rate up + /* rate up */ PenaltyID2 = RETRY_PENALTY_UP_IDX[RateID]; ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, (" NscUp init is %d\n", pRaInfo->NscUp)); @@ -347,7 +347,7 @@ odm_RateDecision_8188E( pRaInfo->RssiStaRA,RtyPtID, PenaltyID1,PenaltyID2, RateID, pRaInfo->NscDown, pRaInfo->NscUp, pRaInfo->RateSGI)); if ((pRaInfo->NscDown < N_THRESHOLD_LOW[RateID]) ||(pRaInfo->DROP>DROPING_NECESSARY[RateID])) odm_RateDown_8188E(pDM_Odm,pRaInfo); - //else if ((pRaInfo->NscUp > N_THRESHOLD_HIGH[RateID])&&(pool_retryNscUp > N_THRESHOLD_HIGH[RateID])&&(pool_retryNscUp > N_THRESHOLD_HIGH[RateID]) odm_RateUp_8188E(pDM_Odm,pRaInfo); @@ -365,7 +365,7 @@ odm_RateDecision_8188E( DynamicTxRPTTimingCounter=0; } - pRaInfo->PreRate = pRaInfo->DecisionRate; //YJ,add,120120 + pRaInfo->PreRate = pRaInfo->DecisionRate; /* YJ,add,120120 */ odm_ResetRaCounter_8188E( pRaInfo); } @@ -377,7 +377,7 @@ odm_ARFBRefresh_8188E( IN PDM_ODM_T pDM_Odm, IN PODM_RA_INFO_T pRaInfo ) -{ // Wilson 2011/10/26 +{ /* Wilson 2011/10/26 */ u32 MaskFromReg; s8 i; @@ -424,7 +424,7 @@ odm_ARFBRefresh_8188E( pRaInfo->RAUseRate=(pRaInfo->RateMask); break; } - // Highest rate + /* Highest rate */ if (pRaInfo->RAUseRate){ for (i=RATESIZE;i>=0;i--) { @@ -437,7 +437,7 @@ odm_ARFBRefresh_8188E( else{ pRaInfo->HighestRate=0; } - // Lowest rate + /* Lowest rate */ if (pRaInfo->RAUseRate){ for (i=0;iODM_RASupport_Init()\n")); - // 2012/02/14 MH Be noticed, the init must be after IC type is recognized!!!!! + /* 2012/02/14 MH Be noticed, the init must be after IC type is recognized!!!!! */ if (pDM_Odm->SupportICType == ODM_RTL8188E) pDM_Odm->RaSupport88E = TRUE; @@ -621,8 +621,8 @@ ODM_RAInfo_Init( { PODM_RA_INFO_T pRaInfo = &pDM_Odm->RAInfo[MacID]; #if 1 - u8 WirelessMode=0xFF; //invalid value - u8 max_rate_idx = 0x13; //MCS7 + u8 WirelessMode=0xFF; /* invalid value */ + u8 max_rate_idx = 0x13; /* MCS7 */ if(pDM_Odm->pWirelessMode!=NULL){ WirelessMode=*(pDM_Odm->pWirelessMode); } @@ -636,7 +636,7 @@ ODM_RAInfo_Init( max_rate_idx = 0x03; } - //printk("%s ==>WirelessMode:0x%08x ,max_raid_idx:0x%02x\n ",__FUNCTION__,WirelessMode,max_rate_idx); + /* printk("%s ==>WirelessMode:0x%08x ,max_raid_idx:0x%02x\n ",__FUNCTION__,WirelessMode,max_rate_idx); */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("ODM_RAInfo_Init(): WirelessMode:0x%08x ,max_raid_idx:0x%02x \n", WirelessMode,max_rate_idx)); @@ -659,7 +659,7 @@ ODM_RAInfo_Init( pRaInfo->NscDown=(N_THRESHOLD_HIGH[0x13]+N_THRESHOLD_LOW[0x13])/2; pRaInfo->NscUp=(N_THRESHOLD_HIGH[0x13]+N_THRESHOLD_LOW[0x13])/2; pRaInfo->RateSGI=0; - pRaInfo->Active=1; //Active is not used at present. by page, 110819 + pRaInfo->Active=1; /* Active is not used at present. by page, 110819 */ pRaInfo->RptTime = 0x927c; pRaInfo->DROP=0; pRaInfo->DROP1=0; @@ -672,9 +672,9 @@ ODM_RAInfo_Init( pRaInfo->RAWaitingCounter=0; pRaInfo->RAPendingCounter=0; #if POWER_TRAINING_ACTIVE == 1 - pRaInfo->PTActive=1; // Active when this STA is use + pRaInfo->PTActive=1; /* Active when this STA is use */ pRaInfo->PTTryState=0; - pRaInfo->PTStage=5; // Need to fill into HW_PWR_STATUS + pRaInfo->PTStage=5; /* Need to fill into HW_PWR_STATUS */ pRaInfo->PTSmoothFactor=192; pRaInfo->PTStopCount=0; pRaInfo->PTPreRate=0; @@ -864,14 +864,14 @@ ODM_RA_TxRPT2Handle_8188E( if(pRAInfo->RAstage<5){ odm_RateDecision_8188E(pDM_Odm,pRAInfo); } - else if(pRAInfo->RAstage==5){ // Power training try state + else if(pRAInfo->RAstage==5){ /* Power training try state */ odm_PTTryState_8188E(pRAInfo); } - else {// RAstage==6 + else {/* RAstage==6 */ odm_PTDecision_8188E(pRAInfo); } - // Stage_RA counter + /* Stage_RA counter */ if (pRAInfo->RAstage<=5) pRAInfo->RAstage++; else diff --git a/hal/Hal8188ERateAdaptive.h b/hal/Hal8188ERateAdaptive.h index 4bbdf75..c0c251a 100755 --- a/hal/Hal8188ERateAdaptive.h +++ b/hal/Hal8188ERateAdaptive.h @@ -15,15 +15,15 @@ Major Change History: 2011-08-12 Page Create. --*/ -// Rate adaptive define +/* Rate adaptive define */ #define PERENTRY 23 #define RETRYSIZE 5 #define RATESIZE 28 #define TX_RPT2_ITEM_SIZE 8 -// -// TX report 2 format in Rx desc -// +/* */ +/* TX report 2 format in Rx desc */ +/* */ #define GET_TX_RPT2_DESC_PKT_LEN_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 9) #define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+16, 0, 32) #define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32) @@ -36,7 +36,7 @@ Major Change History: #define GET_TX_REPORT_TYPE1_DROP_0(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+2, 0, 8) #define GET_TX_REPORT_TYPE1_DROP_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+3, 0, 8) -// End rate adaptive define +/* End rate adaptive define */ void ODM_RASupport_Init( diff --git a/hal/Hal8188EReg.h b/hal/Hal8188EReg.h index a5086c9..0d41ea2 100755 --- a/hal/Hal8188EReg.h +++ b/hal/Hal8188EReg.h @@ -17,29 +17,29 @@ * * ******************************************************************************/ -//============================================================ -// File Name: Hal8188EReg.h -// -// Description: -// -// This file is for RTL8188E register definition. -// -// -//============================================================ +/* */ +/* File Name: Hal8188EReg.h */ +/* */ +/* Description: */ +/* */ +/* This file is for RTL8188E register definition. */ +/* */ +/* */ +/* */ #ifndef __HAL_8188E_REG_H__ #define __HAL_8188E_REG_H__ -// -// Register Definition -// +/* */ +/* Register Definition */ +/* */ #define TRX_ANTDIV_PATH 0x860 #define RX_ANTDIV_PATH 0xb2c #define ODM_R_A_AGC_CORE1_8188E 0xc50 -// -// Bitmap Definition -// +/* */ +/* Bitmap Definition */ +/* */ #define BIT_FA_RESET_8188E BIT0 diff --git a/hal/HalHWImg8188E_BB.c b/hal/HalHWImg8188E_BB.c index 356bfbc..557a694 100755 --- a/hal/HalHWImg8188E_BB.c +++ b/hal/HalHWImg8188E_BB.c @@ -348,7 +348,7 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E( PADAPTER Adapter = pDM_Odm->Adapter; struct xmit_frame *pxmit_frame; u8 bndy_cnt=1; -#endif//#ifdef CONFIG_IOL_IOREG_CFG +#endif/* ifdef CONFIG_IOL_IOREG_CFG */ HAL_STATUS rst =HAL_STATUS_SUCCESS; hex += board; @@ -364,14 +364,14 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E( return HAL_STATUS_FAILURE; } } -#endif//#ifdef CONFIG_IOL_IOREG_CFG +#endif/* ifdef CONFIG_IOL_IOREG_CFG */ for (i = 0; i < ArrayLen; i += 2 ) { u32 v1 = Array[i]; u32 v2 = Array[i+1]; - // This (offset, data) pair meets the condition. + /* This (offset, data) pair meets the condition. */ if ( v1 < 0xCDCDCDCD ) { #ifdef CONFIG_IOL_IOREG_CFG @@ -381,16 +381,16 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E( rtw_IOL_append_WD_cmd(pxmit_frame,(u16)v1, v2,bMaskDWord); } else - #endif //#ifdef CONFIG_IOL_IOREG_CFG + #endif /* ifdef CONFIG_IOL_IOREG_CFG */ { odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2); } continue; } else - { // This line is the start line of branch. + { /* This line is the start line of branch. */ if ( !CheckCondition(Array[i], hex) ) - { // Discard the following (offset, data) pairs. + { /* Discard the following (offset, data) pairs. */ READ_NEXT_PAIR(v1, v2, i); while ( v2 != 0xDEAD && v2 != 0xCDEF && @@ -398,9 +398,9 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E( { READ_NEXT_PAIR(v1, v2, i); } - i -= 2; // prevent from for-loop += 2 + i -= 2; /* prevent from for-loop += 2 */ } - else // Configure matched pairs and skip to end of if-else. + else /* Configure matched pairs and skip to end of if-else. */ { READ_NEXT_PAIR(v1, v2, i); while ( v2 != 0xDEAD && @@ -414,7 +414,7 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E( rtw_IOL_append_WD_cmd(pxmit_frame,(u16)v1, v2,bMaskDWord); } else - #endif //#ifdef CONFIG_IOL_IOREG_CFG + #endif /* ifdef CONFIG_IOL_IOREG_CFG */ { odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2); } @@ -431,31 +431,31 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E( } #ifdef CONFIG_IOL_IOREG_CFG if(biol){ - //printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); + /* printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); */ if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt)) { #ifdef CONFIG_IOL_IOREG_CFG_DBG printk("~~~ %s Success !!! \n",__FUNCTION__); { - //dump data from TX packet buffer + /* dump data from TX packet buffer */ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); } - #endif //CONFIG_IOL_IOREG_CFG_DBG + #endif /* CONFIG_IOL_IOREG_CFG_DBG */ } else{ printk("~~~ %s IOL_exec_cmds Failed !!! \n",__FUNCTION__); #ifdef CONFIG_IOL_IOREG_CFG_DBG { - //dump data from TX packet buffer + /* dump data from TX packet buffer */ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); } - #endif //CONFIG_IOL_IOREG_CFG_DBG + #endif /* CONFIG_IOL_IOREG_CFG_DBG */ rst = HAL_STATUS_FAILURE; } } -#endif //#ifdef CONFIG_IOL_IOREG_CFG +#endif /* ifdef CONFIG_IOL_IOREG_CFG */ return rst; } @@ -626,16 +626,16 @@ ODM_ReadAndConfig_AGC_TAB_1T_ICUT_8188E( u32 v1 = Array[i]; u32 v2 = Array[i+1]; - // This (offset, data) pair meets the condition. + /* This (offset, data) pair meets the condition. */ if ( v1 < 0xCDCDCDCD ) { odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2); continue; } else - { // This line is the start line of branch. + { /* This line is the start line of branch. */ if ( !CheckCondition(Array[i], hex) ) - { // Discard the following (offset, data) pairs. + { /* Discard the following (offset, data) pairs. */ READ_NEXT_PAIR(v1, v2, i); while (v2 != 0xDEAD && v2 != 0xCDEF && @@ -643,9 +643,9 @@ ODM_ReadAndConfig_AGC_TAB_1T_ICUT_8188E( { READ_NEXT_PAIR(v1, v2, i); } - i -= 2; // prevent from for-loop += 2 + i -= 2; /* prevent from for-loop += 2 */ } - else // Configure matched pairs and skip to end of if-else. + else /* Configure matched pairs and skip to end of if-else. */ { READ_NEXT_PAIR(v1, v2, i); while (v2 != 0xDEAD && @@ -914,7 +914,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E( struct cmd_cmp cmpdata[ArrayLen]; u32 cmpdata_idx=0; #endif -#endif//#ifdef CONFIG_IOL_IOREG_CFG +#endif/* ifdef CONFIG_IOL_IOREG_CFG */ HAL_STATUS rst =HAL_STATUS_SUCCESS; hex += board; hex += interfaceValue << 8; @@ -930,7 +930,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E( return HAL_STATUS_FAILURE; } } -#endif//#ifdef CONFIG_IOL_IOREG_CFG +#endif/* ifdef CONFIG_IOL_IOREG_CFG */ for (i = 0; i < ArrayLen; i += 2 ) { @@ -938,7 +938,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E( u32 v2 = Array[i+1]; - // This (offset, data) pair meets the condition. + /* This (offset, data) pair meets the condition. */ if ( v1 < 0xCDCDCDCD ) { #ifdef CONFIG_IOL_IOREG_CFG @@ -978,16 +978,16 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E( } } else - #endif //#ifdef CONFIG_IOL_IOREG_CFG + #endif /* ifdef CONFIG_IOL_IOREG_CFG */ { odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2); } continue; } else - { // This line is the start line of branch. + { /* This line is the start line of branch. */ if ( !CheckCondition(Array[i], hex) ) - { // Discard the following (offset, data) pairs. + { /* Discard the following (offset, data) pairs. */ READ_NEXT_PAIR(v1, v2, i); while (v2 != 0xDEAD && v2 != 0xCDEF && @@ -995,9 +995,9 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E( { READ_NEXT_PAIR(v1, v2, i); } - i -= 2; // prevent from for-loop += 2 + i -= 2; /* prevent from for-loop += 2 */ } - else // Configure matched pairs and skip to end of if-else. + else /* Configure matched pairs and skip to end of if-else. */ { READ_NEXT_PAIR(v1, v2, i); while (v2 != 0xDEAD && @@ -1039,7 +1039,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E( } } else - #endif //#ifdef CONFIG_IOL_IOREG_CFG + #endif /* ifdef CONFIG_IOL_IOREG_CFG */ { odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2); } @@ -1056,7 +1056,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E( } #ifdef CONFIG_IOL_IOREG_CFG if(biol){ - //printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); + /* printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); */ if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt)) { #ifdef CONFIG_IOL_IOREG_CFG_DBG @@ -1076,13 +1076,13 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E( } } printk("### %s data compared !!###\n",__FUNCTION__); - //if(rst == HAL_STATUS_FAILURE) - {//dump data from TX packet buffer + /* if(rst == HAL_STATUS_FAILURE) */ + {/* dump data from TX packet buffer */ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); } } - #endif //CONFIG_IOL_IOREG_CFG_DBG + #endif /* CONFIG_IOL_IOREG_CFG_DBG */ } else{ @@ -1090,13 +1090,13 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E( printk("~~~ IOL Config %s Failed !!! \n",__FUNCTION__); #ifdef CONFIG_IOL_IOREG_CFG_DBG { - //dump data from TX packet buffer + /* dump data from TX packet buffer */ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); } - #endif //CONFIG_IOL_IOREG_CFG_DBG + #endif /* CONFIG_IOL_IOREG_CFG_DBG */ } } -#endif //#ifdef CONFIG_IOL_IOREG_CFG +#endif /* ifdef CONFIG_IOL_IOREG_CFG */ return rst; } /****************************************************************************** @@ -1327,16 +1327,16 @@ ODM_ReadAndConfig_PHY_REG_1T_ICUT_8188E( u32 v1 = Array[i]; u32 v2 = Array[i+1]; - // This (offset, data) pair meets the condition. + /* This (offset, data) pair meets the condition. */ if ( v1 < 0xCDCDCDCD ) { odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2); continue; } else - { // This line is the start line of branch. + { /* This line is the start line of branch. */ if ( !CheckCondition(Array[i], hex) ) - { // Discard the following (offset, data) pairs. + { /* Discard the following (offset, data) pairs. */ READ_NEXT_PAIR(v1, v2, i); while (v2 != 0xDEAD && v2 != 0xCDEF && @@ -1344,9 +1344,9 @@ ODM_ReadAndConfig_PHY_REG_1T_ICUT_8188E( { READ_NEXT_PAIR(v1, v2, i); } - i -= 2; // prevent from for-loop += 2 + i -= 2; /* prevent from for-loop += 2 */ } - else // Configure matched pairs and skip to end of if-else. + else /* Configure matched pairs and skip to end of if-else. */ { READ_NEXT_PAIR(v1, v2, i); while (v2 != 0xDEAD && @@ -1412,7 +1412,7 @@ ODM_ReadAndConfig_PHY_REG_PG_8188E( u32 v5 = Array[i+4]; u32 v6 = Array[i+5]; - // this line is a line of pure_body + /* this line is a line of pure_body */ if ( v1 < 0xCDCDCDCD ) { @@ -1421,10 +1421,10 @@ ODM_ReadAndConfig_PHY_REG_PG_8188E( continue; } else - { // this line is the start of branch + { /* this line is the start of branch */ if ( !CheckCondition(Array[i], hex) ) - { // don't need the hw_body - i += 2; // skip the pair of expression + { /* don't need the hw_body */ + i += 2; /* skip the pair of expression */ v1 = Array[i]; v2 = Array[i+1]; v3 = Array[i+2]; diff --git a/hal/HalHWImg8188E_BB.h b/hal/HalHWImg8188E_BB.h index 953b8c0..dc8fcb2 100755 --- a/hal/HalHWImg8188E_BB.h +++ b/hal/HalHWImg8188E_BB.h @@ -21,7 +21,7 @@ #ifndef __INC_BB_8188E_HW_IMG_H #define __INC_BB_8188E_HW_IMG_H -//static BOOLEAN CheckCondition(const u32 Condition, const u32 Hex); +/* static BOOLEAN CheckCondition(const u32 Condition, const u32 Hex); */ /****************************************************************************** * AGC_TAB_1T.TXT @@ -36,7 +36,7 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E( ******************************************************************************/ void -ODM_ReadAndConfig_AGC_TAB_1T_ICUT_8188E( // TC: Test Chip, MP: MP Chip +ODM_ReadAndConfig_AGC_TAB_1T_ICUT_8188E( /* TC: Test Chip, MP: MP Chip */ IN PDM_ODM_T pDM_Odm ); /****************************************************************************** @@ -52,7 +52,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E( ******************************************************************************/ void -ODM_ReadAndConfig_PHY_REG_1T_ICUT_8188E( // TC: Test Chip, MP: MP Chip +ODM_ReadAndConfig_PHY_REG_1T_ICUT_8188E( /* TC: Test Chip, MP: MP Chip */ IN PDM_ODM_T pDM_Odm ); @@ -65,4 +65,4 @@ ODM_ReadAndConfig_PHY_REG_PG_8188E( IN PDM_ODM_T pDM_Odm ); -#endif // end of HWIMG_SUPPORT +#endif /* end of HWIMG_SUPPORT */ diff --git a/hal/HalHWImg8188E_MAC.c b/hal/HalHWImg8188E_MAC.c index f7a7d1a..749019c 100755 --- a/hal/HalHWImg8188E_MAC.c +++ b/hal/HalHWImg8188E_MAC.c @@ -181,7 +181,7 @@ ODM_ReadAndConfig_MAC_REG_8188E( struct cmd_cmp cmpdata[ArrayLen]; u32 cmpdata_idx=0; #endif -#endif //CONFIG_IOL_IOREG_CFG +#endif /* CONFIG_IOL_IOREG_CFG */ HAL_STATUS rst =HAL_STATUS_SUCCESS; hex += board; hex += interfaceValue << 8; @@ -199,14 +199,14 @@ ODM_ReadAndConfig_MAC_REG_8188E( } } -#endif //CONFIG_IOL_IOREG_CFG +#endif /* CONFIG_IOL_IOREG_CFG */ for (i = 0; i < ArrayLen; i += 2 ) { u32 v1 = Array[i]; u32 v2 = Array[i+1]; - // This (offset, data) pair meets the condition. + /* This (offset, data) pair meets the condition. */ if ( v1 < 0xCDCDCDCD ) { #ifdef CONFIG_IOL_IOREG_CFG @@ -223,16 +223,16 @@ ODM_ReadAndConfig_MAC_REG_8188E( #endif } else - #endif //endif CONFIG_IOL_IOREG_CFG + #endif /* endif CONFIG_IOL_IOREG_CFG */ { odm_ConfigMAC_8188E(pDM_Odm, v1, (u8)v2); } continue; } else - { // This line is the start line of branch. + { /* This line is the start line of branch. */ if ( !CheckCondition(Array[i], hex) ) - { // Discard the following (offset, data) pairs. + { /* Discard the following (offset, data) pairs. */ READ_NEXT_PAIR(v1, v2, i); while ( v2 != 0xDEAD && v2 != 0xCDEF && @@ -240,9 +240,9 @@ ODM_ReadAndConfig_MAC_REG_8188E( { READ_NEXT_PAIR(v1, v2, i); } - i -= 2; // prevent from for-loop += 2 + i -= 2; /* prevent from for-loop += 2 */ } - else // Configure matched pairs and skip to end of if-else. + else /* Configure matched pairs and skip to end of if-else. */ { READ_NEXT_PAIR(v1, v2, i); while ( v2 != 0xDEAD && @@ -261,7 +261,7 @@ ODM_ReadAndConfig_MAC_REG_8188E( #endif } else - #endif //#ifdef CONFIG_IOL_IOREG_CFG + #endif /* ifdef CONFIG_IOL_IOREG_CFG */ { odm_ConfigMAC_8188E(pDM_Odm, v1, (u8)v2); } @@ -280,17 +280,17 @@ ODM_ReadAndConfig_MAC_REG_8188E( #ifdef CONFIG_IOL_IOREG_CFG if(biol){ - //printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); + /* printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); */ if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt)) { #ifdef CONFIG_IOL_IOREG_CFG_DBG printk("~~~ IOL Config MAC Success !!! \n"); - //compare writed data + /* compare writed data */ { u32 idx; u8 cdata; - // HAL_STATUS_FAILURE; + /* HAL_STATUS_FAILURE; */ printk(" MAC data compare => array_len:%d \n",cmpdata_idx); for(idx=0;idx< cmpdata_idx;idx++) { @@ -298,34 +298,34 @@ ODM_ReadAndConfig_MAC_REG_8188E( if(cdata != cmpdata[idx].value){ printk("### MAC data compared failed !! addr:0x%04x, data:(0x%02x : 0x%02x) ###\n", cmpdata[idx].addr,cmpdata[idx].value,cdata); - //rst = HAL_STATUS_FAILURE; + /* rst = HAL_STATUS_FAILURE; */ } } - //dump data from TX packet buffer - //if(rst == HAL_STATUS_FAILURE) + /* dump data from TX packet buffer */ + /* if(rst == HAL_STATUS_FAILURE) */ { rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); } } - #endif //CONFIG_IOL_IOREG_CFG_DBG + #endif /* CONFIG_IOL_IOREG_CFG_DBG */ } else{ printk("~~~ MAC IOL_exec_cmds Failed !!! \n"); #ifdef CONFIG_IOL_IOREG_CFG_DBG { - //dump data from TX packet buffer + /* dump data from TX packet buffer */ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); } - #endif //CONFIG_IOL_IOREG_CFG_DBG + #endif /* CONFIG_IOL_IOREG_CFG_DBG */ rst = HAL_STATUS_FAILURE; } } -#endif //#ifdef CONFIG_IOL_IOREG_CFG +#endif /* ifdef CONFIG_IOL_IOREG_CFG */ return rst; } @@ -456,16 +456,16 @@ ODM_ReadAndConfig_MAC_REG_ICUT_8188E( u32 v1 = Array[i]; u32 v2 = Array[i+1]; - // This (offset, data) pair meets the condition. + /* This (offset, data) pair meets the condition. */ if ( v1 < 0xCDCDCDCD ) { odm_ConfigMAC_8188E(pDM_Odm, v1, (u8)v2); continue; } else - { // This line is the start line of branch. + { /* This line is the start line of branch. */ if ( !CheckCondition(Array[i], hex) ) - { // Discard the following (offset, data) pairs. + { /* Discard the following (offset, data) pairs. */ READ_NEXT_PAIR(v1, v2, i); while (v2 != 0xDEAD && v2 != 0xCDEF && @@ -473,9 +473,9 @@ ODM_ReadAndConfig_MAC_REG_ICUT_8188E( { READ_NEXT_PAIR(v1, v2, i); } - i -= 2; // prevent from for-loop += 2 + i -= 2; /* prevent from for-loop += 2 */ } - else // Configure matched pairs and skip to end of if-else. + else /* Configure matched pairs and skip to end of if-else. */ { READ_NEXT_PAIR(v1, v2, i); while (v2 != 0xDEAD && diff --git a/hal/HalHWImg8188E_MAC.h b/hal/HalHWImg8188E_MAC.h index 300a83a..4a2f38d 100755 --- a/hal/HalHWImg8188E_MAC.h +++ b/hal/HalHWImg8188E_MAC.h @@ -21,7 +21,7 @@ #ifndef __INC_MAC_8188E_HW_IMG_H #define __INC_MAC_8188E_HW_IMG_H -//static BOOLEAN CheckCondition(const u32 Condition, const u32 Hex); +/* static BOOLEAN CheckCondition(const u32 Condition, const u32 Hex); */ /****************************************************************************** * MAC_REG.TXT @@ -37,7 +37,7 @@ ODM_ReadAndConfig_MAC_REG_8188E( ******************************************************************************/ void -ODM_ReadAndConfig_MAC_REG_ICUT_8188E( // TC: Test Chip, MP: MP Chip +ODM_ReadAndConfig_MAC_REG_ICUT_8188E( /* TC: Test Chip, MP: MP Chip */ IN PDM_ODM_T pDM_Odm ); diff --git a/hal/HalHWImg8188E_RF.c b/hal/HalHWImg8188E_RF.c index 71e74f3..7e7a4ee 100755 --- a/hal/HalHWImg8188E_RF.c +++ b/hal/HalHWImg8188E_RF.c @@ -201,7 +201,7 @@ ODM_ReadAndConfig_RadioA_1T_8188E( struct cmd_cmp cmpdata[ArrayLen]; u32 cmpdata_idx=0; #endif -#endif//#ifdef CONFIG_IOL_IOREG_CFG +#endif/* ifdef CONFIG_IOL_IOREG_CFG */ HAL_STATUS rst =HAL_STATUS_SUCCESS; hex += board; @@ -218,14 +218,14 @@ ODM_ReadAndConfig_RadioA_1T_8188E( return HAL_STATUS_FAILURE; } } -#endif//#ifdef CONFIG_IOL_IOREG_CFG +#endif/* ifdef CONFIG_IOL_IOREG_CFG */ for (i = 0; i < ArrayLen; i += 2 ) { u32 v1 = Array[i]; u32 v2 = Array[i+1]; - // This (offset, data) pair meets the condition. + /* This (offset, data) pair meets the condition. */ if ( v1 < 0xCDCDCDCD ) { #ifdef CONFIG_IOL_IOREG_CFG @@ -263,16 +263,16 @@ ODM_ReadAndConfig_RadioA_1T_8188E( } else - #endif //#ifdef CONFIG_IOL_IOREG_CFG + #endif /* ifdef CONFIG_IOL_IOREG_CFG */ { odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2); } continue; } else - { // This line is the start line of branch. + { /* This line is the start line of branch. */ if ( !CheckCondition(Array[i], hex) ) - { // Discard the following (offset, data) pairs. + { /* Discard the following (offset, data) pairs. */ READ_NEXT_PAIR(v1, v2, i); while (v2 != 0xDEAD && v2 != 0xCDEF && @@ -280,9 +280,9 @@ ODM_ReadAndConfig_RadioA_1T_8188E( { READ_NEXT_PAIR(v1, v2, i); } - i -= 2; // prevent from for-loop += 2 + i -= 2; /* prevent from for-loop += 2 */ } - else // Configure matched pairs and skip to end of if-else. + else /* Configure matched pairs and skip to end of if-else. */ { READ_NEXT_PAIR(v1, v2, i); while (v2 != 0xDEAD && @@ -325,7 +325,7 @@ ODM_ReadAndConfig_RadioA_1T_8188E( } else - #endif //#ifdef CONFIG_IOL_IOREG_CFG + #endif /* ifdef CONFIG_IOL_IOREG_CFG */ { odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2); } @@ -342,7 +342,7 @@ ODM_ReadAndConfig_RadioA_1T_8188E( } #ifdef CONFIG_IOL_IOREG_CFG if(biol){ - //printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); + /* printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); */ if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt)) { #ifdef CONFIG_IOL_IOREG_CFG_DBG @@ -362,12 +362,12 @@ ODM_ReadAndConfig_RadioA_1T_8188E( } } printk("### %s data compared !!###\n",__FUNCTION__); - //if(rst == HAL_STATUS_FAILURE) - {//dump data from TX packet buffer + /* if(rst == HAL_STATUS_FAILURE) */ + {/* dump data from TX packet buffer */ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); } } - #endif //CONFIG_IOL_IOREG_CFG_DBG + #endif /* CONFIG_IOL_IOREG_CFG_DBG */ } else{ @@ -375,15 +375,15 @@ ODM_ReadAndConfig_RadioA_1T_8188E( printk("~~~ IOL Config %s Failed !!! \n",__FUNCTION__); #ifdef CONFIG_IOL_IOREG_CFG_DBG { - //dump data from TX packet buffer + /* dump data from TX packet buffer */ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32); } - #endif //CONFIG_IOL_IOREG_CFG_DBG + #endif /* CONFIG_IOL_IOREG_CFG_DBG */ } } -#endif //#ifdef CONFIG_IOL_IOREG_CFG +#endif /* ifdef CONFIG_IOL_IOREG_CFG */ return rst; } /****************************************************************************** @@ -522,16 +522,16 @@ ODM_ReadAndConfig_RadioA_1T_ICUT_8188E( u32 v1 = Array[i]; u32 v2 = Array[i+1]; - // This (offset, data) pair meets the condition. + /* This (offset, data) pair meets the condition. */ if ( v1 < 0xCDCDCDCD ) { odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2); continue; } else - { // This line is the start line of branch. + { /* This line is the start line of branch. */ if ( !CheckCondition(Array[i], hex) ) - { // Discard the following (offset, data) pairs. + { /* Discard the following (offset, data) pairs. */ READ_NEXT_PAIR(v1, v2, i); while (v2 != 0xDEAD && v2 != 0xCDEF && @@ -539,9 +539,9 @@ ODM_ReadAndConfig_RadioA_1T_ICUT_8188E( { READ_NEXT_PAIR(v1, v2, i); } - i -= 2; // prevent from for-loop += 2 + i -= 2; /* prevent from for-loop += 2 */ } - else // Configure matched pairs and skip to end of if-else. + else /* Configure matched pairs and skip to end of if-else. */ { READ_NEXT_PAIR(v1, v2, i); while (v2 != 0xDEAD && diff --git a/hal/HalHWImg8188E_RF.h b/hal/HalHWImg8188E_RF.h index 8b46675..25d209f 100755 --- a/hal/HalHWImg8188E_RF.h +++ b/hal/HalHWImg8188E_RF.h @@ -21,7 +21,7 @@ #ifndef __INC_RF_8188E_HW_IMG_H #define __INC_RF_8188E_HW_IMG_H -//static BOOLEAN CheckCondition(const u32 Condition, const u32 Hex); +/* static BOOLEAN CheckCondition(const u32 Condition, const u32 Hex); */ /****************************************************************************** * RadioA_1T.TXT @@ -36,7 +36,7 @@ ODM_ReadAndConfig_RadioA_1T_8188E( ******************************************************************************/ void -ODM_ReadAndConfig_RadioA_1T_ICUT_8188E( // TC: Test Chip, MP: MP Chip +ODM_ReadAndConfig_RadioA_1T_ICUT_8188E( /* TC: Test Chip, MP: MP Chip */ IN PDM_ODM_T pDM_Odm ); diff --git a/hal/HalPhyRf.c b/hal/HalPhyRf.c index e645306..327914d 100755 --- a/hal/HalPhyRf.c +++ b/hal/HalPhyRf.c @@ -20,9 +20,9 @@ #include "odm_precomp.h" -//3============================================================ -//3 IQ Calibration -//3============================================================ +/* 3============================================================ */ +/* 3 IQ Calibration */ +/* 3============================================================ */ void ODM_ResetIQKResult( @@ -35,7 +35,7 @@ ODM_ResetIQKResult( if (!IS_HARDWARE_TYPE_8192D(Adapter)) return; ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("PHY_ResetIQKResult:: settings regs %d default regs %d\n", (u32)(sizeof(pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting)/sizeof(IQK_MATRIX_REGS_SETTING)), IQK_Matrix_Settings_NUM)); - //0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc + /* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */ for(i = 0; i < IQK_Matrix_Settings_NUM; i++) { diff --git a/hal/HalPhyRf.h b/hal/HalPhyRf.h index d76353e..1f1dce9 100755 --- a/hal/HalPhyRf.h +++ b/hal/HalPhyRf.h @@ -26,5 +26,5 @@ void ODM_ResetIQKResult(PDM_ODM_T pDM_Odm ); u8 ODM_GetRightChnlPlaceforIQK(u8 chnl); -#endif // #ifndef __HAL_PHY_RF_H__ +#endif /* #ifndef __HAL_PHY_RF_H__ */ diff --git a/hal/HalPhyRf_8188e.c b/hal/HalPhyRf_8188e.c index d7b888b..10b15ae 100755 --- a/hal/HalPhyRf_8188e.c +++ b/hal/HalPhyRf_8188e.c @@ -24,7 +24,7 @@ /*---------------------------Define Local Constant---------------------------*/ -// 2010/04/25 MH Define the max tx power tracking tx agc power. +/* 2010/04/25 MH Define the max tx power tracking tx agc power. */ #define ODM_TXPWRTRACK_MAX_IDX_88E 6 #define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \ @@ -42,9 +42,9 @@ _offset = _size-1;\ } while(0) -//3============================================================ -//3 Tx Power Tracking -//3============================================================ +/* 3============================================================ */ +/* 3 Tx Power Tracking */ +/* 3============================================================ */ static void setIqkMatrix( PDM_ODM_T pDM_Odm, u8 OFDM_index, @@ -55,22 +55,22 @@ static void setIqkMatrix( { s32 ele_A=0, ele_D, ele_C=0, TempCCk, value32; - //printk("%s==> OFDM_index:%d \n",__FUNCTION__,OFDM_index); + /* printk("%s==> OFDM_index:%d \n",__FUNCTION__,OFDM_index); */ - //if(OFDM_index> OFDM_TABLE_SIZE_92D) - //{ - //printk("%s==> OFDM_index> 43\n",__FUNCTION__); - //} + /* if(OFDM_index> OFDM_TABLE_SIZE_92D) */ + /* */ + /* printk("%s==> OFDM_index> 43\n",__FUNCTION__); */ + /* */ ele_D = (OFDMSwingTable[OFDM_index] & 0xFFC00000)>>22; - //new element A = element D x X + /* new element A = element D x X */ if((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) { - if ((IqkResult_X & 0x00000200) != 0) //consider minus + if ((IqkResult_X & 0x00000200) != 0) /* consider minus */ IqkResult_X = IqkResult_X | 0xFFFFFC00; ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF; - //new element C = element D x Y + /* new element C = element D x Y */ if ((IqkResult_Y & 0x00000200) != 0) IqkResult_Y = IqkResult_Y | 0xFFFFFC00; ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF; @@ -79,7 +79,7 @@ static void setIqkMatrix( switch (RFPath) { case RF_PATH_A: - //wirte new elements A, C, D to regC80 and regC94, element B is always 0 + /* wirte new elements A, C, D to regC80 and regC94, element B is always 0 */ value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); @@ -90,7 +90,7 @@ static void setIqkMatrix( ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); break; case RF_PATH_B: - //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 + /* wirte new elements A, C, D to regC88 and regC9C, element B is always 0 */ value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A; ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); @@ -168,22 +168,22 @@ static void doIQK( void ODM_TxPwrTrackAdjust88E( PDM_ODM_T pDM_Odm, - u8 Type, // 0 = OFDM, 1 = CCK - u8 * pDirection, // 1 = +(increase) 2 = -(decrease) - u32 * pOutWriteVal // Tx tracking CCK/OFDM BB swing index adjust + u8 Type, /* 0 = OFDM, 1 = CCK */ + u8 * pDirection, /* 1 = +(increase) 2 = -(decrease) */ + u32 * pOutWriteVal /* Tx tracking CCK/OFDM BB swing index adjust */ ) { u8 pwr_value = 0; - // - // Tx power tracking BB swing table. - // The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB - // - if (Type == 0) // For OFDM afjust + /* */ + /* Tx power tracking BB swing table. */ + /* The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */ + /* */ + if (Type == 0) /* For OFDM afjust */ { ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("BbSwingIdxOfdm = %d BbSwingFlagOfdm=%d\n", pDM_Odm->BbSwingIdxOfdm, pDM_Odm->BbSwingFlagOfdm)); - //printk("BbSwingIdxOfdm = %d BbSwingFlagOfdm=%d\n", pDM_Odm->BbSwingIdxOfdm, pDM_Odm->BbSwingFlagOfdm); + /* printk("BbSwingIdxOfdm = %d BbSwingFlagOfdm=%d\n", pDM_Odm->BbSwingIdxOfdm, pDM_Odm->BbSwingFlagOfdm); */ if (pDM_Odm->BbSwingIdxOfdm <= pDM_Odm->BbSwingIdxOfdmBase) { *pDirection = 1; @@ -197,15 +197,15 @@ ODM_TxPwrTrackAdjust88E( ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("BbSwingIdxOfdm = %d BbSwingIdxOfdmBase=%d\n", pDM_Odm->BbSwingIdxOfdm, pDM_Odm->BbSwingIdxOfdmBase)); - //printk("BbSwingIdxOfdm = %d BbSwingIdxOfdmBase=%d pwr_value=%d\n", pDM_Odm->BbSwingIdxOfdm, pDM_Odm->BbSwingIdxOfdmBase,pwr_value); + /* printk("BbSwingIdxOfdm = %d BbSwingIdxOfdmBase=%d pwr_value=%d\n", pDM_Odm->BbSwingIdxOfdm, pDM_Odm->BbSwingIdxOfdmBase,pwr_value); */ } - else if (Type == 1) // For CCK adjust. + else if (Type == 1) /* For CCK adjust. */ { ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("pDM_Odm->BbSwingIdxCck = %d pDM_Odm->BbSwingIdxCckBase = %d\n", pDM_Odm->BbSwingIdxCck, pDM_Odm->BbSwingIdxCckBase)); - //printk("pDM_Odm->BbSwingIdxCck = %d pDM_Odm->BbSwingIdxCckBase = %d\n", pDM_Odm->BbSwingIdxCck, pDM_Odm->BbSwingIdxCckBase); + /* printk("pDM_Odm->BbSwingIdxCck = %d pDM_Odm->BbSwingIdxCckBase = %d\n", pDM_Odm->BbSwingIdxCck, pDM_Odm->BbSwingIdxCckBase); */ if (pDM_Odm->BbSwingIdxCck <= pDM_Odm->BbSwingIdxCckBase) { *pDirection = 1; @@ -216,19 +216,19 @@ ODM_TxPwrTrackAdjust88E( *pDirection = 2; pwr_value = (pDM_Odm->BbSwingIdxCck - pDM_Odm->BbSwingIdxCckBase); } - //printk("pDM_Odm->BbSwingIdxCck = %d pDM_Odm->BbSwingIdxCckBase = %d pwr_value:%d\n", pDM_Odm->BbSwingIdxCck, pDM_Odm->BbSwingIdxCckBase,pwr_value); + /* printk("pDM_Odm->BbSwingIdxCck = %d pDM_Odm->BbSwingIdxCckBase = %d pwr_value:%d\n", pDM_Odm->BbSwingIdxCck, pDM_Odm->BbSwingIdxCckBase,pwr_value); */ } - // - // 2012/04/25 MH According to Ed/Luke.Lees estimate for EVM the max tx power tracking - // need to be less than 6 power index for 88E. - // + /* */ + /* 2012/04/25 MH According to Ed/Luke.Lees estimate for EVM the max tx power tracking */ + /* need to be less than 6 power index for 88E. */ + /* */ if (pwr_value >= ODM_TXPWRTRACK_MAX_IDX_88E && *pDirection == 1) pwr_value = ODM_TXPWRTRACK_MAX_IDX_88E; *pOutWriteVal = pwr_value | (pwr_value<<8) | (pwr_value<<16) | (pwr_value<<24); -} // ODM_TxPwrTrackAdjust88E +} /* ODM_TxPwrTrackAdjust88E */ /*----------------------------------------------------------------------------- @@ -262,10 +262,10 @@ odm_TxPwrTrackSetPwr88E( u8 rf = 0; u32 pwr = 0, TxAGC = 0; struct adapter *Adapter = pDM_Odm->Adapter; - //printk("odm_TxPwrTrackSetPwr88E CH=%d, modify TXAGC \n", *(pDM_Odm->pChannel)); + /* printk("odm_TxPwrTrackSetPwr88E CH=%d, modify TXAGC \n", *(pDM_Odm->pChannel)); */ ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr88E CH=%d\n", *(pDM_Odm->pChannel))); - //#if (MP_DRIVER != 1) + /* if (MP_DRIVER != 1) */ if ( *(pDM_Odm->mp_mode) != 1){ PHY_SetTxPowerLevel8188E(pDM_Odm->Adapter, *pDM_Odm->pChannel); } @@ -316,7 +316,7 @@ odm_TxPwrTrackSetPwr88E( ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14[pDM_Odm->BbSwingIdxCck][7]); } - // Adjust BB swing by OFDM IQ matrix + /* Adjust BB swing by OFDM IQ matrix */ if (RFPath == RF_PATH_A) { setIqkMatrix(pDM_Odm, pDM_Odm->BbSwingIdxOfdm, RF_PATH_A, @@ -335,7 +335,7 @@ odm_TxPwrTrackSetPwr88E( { return; } -} // odm_TxPwrTrackSetPwr88E +} /* odm_TxPwrTrackSetPwr88E */ void @@ -356,38 +356,38 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E( BOOLEAN is2T = FALSE; BOOLEAN bInteralPA = FALSE; - u8 OFDM_min_index = 6, rf = (is2T) ? 2 : 1; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur + u8 OFDM_min_index = 6, rf = (is2T) ? 2 : 1; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */ u8 Indexforchannel = 0;/*GetRightChnlPlaceforIQK(pHalData->CurrentChannel)*/ enum _POWER_DEC_INC { POWER_DEC, POWER_INC }; PDM_ODM_T pDM_Odm = &pHalData->odmpriv; struct dm_priv *pdmpriv = &pHalData->dmpriv; - //4 0.1 The following TWO tables decide the final index of OFDM/CCK swing table. + /* 4 0.1 The following TWO tables decide the final index of OFDM/CCK swing table. */ s8 deltaSwingTableIdx[2][index_mapping_NUM_88E] = { - // {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} + /* {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} */ {0,0,2,3,4,4,5,6,7,7,8,9,10,10,11}, {0,0,-1,-2,-3,-4,-4,-4,-4,-5,-7,-8,-9,-9,-10} }; u8 thermalThreshold[2][index_mapping_NUM_88E]={ - // {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} + /* {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} */ {0,2,4,6,8,10,12,14,16,18,20,22,24,26,27}, {0,2,4,6,8,10,12,14,16,18,20,22,25,25,25} }; - //4 0.1 Initilization ( 7 steps in total ) + /* 4 0.1 Initilization ( 7 steps in total ) */ - pDM_Odm->RFCalibrateInfo.TXPowerTrackingCallbackCnt++; //cosa add for debug + pDM_Odm->RFCalibrateInfo.TXPowerTrackingCallbackCnt++; /* cosa add for debug */ pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = TRUE; #if (MP_DRIVER == 1) - // RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. + /* RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. */ pDM_Odm->RFCalibrateInfo.RegA24 = 0x090e1317; #endif ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>odm_TXPowerTrackingCallback_ThermalMeter_8188E, pDM_Odm->BbSwingIdxCckBase: %d, pDM_Odm->BbSwingIdxOfdmBase: %d \n", pDM_Odm->BbSwingIdxCckBase, pDM_Odm->BbSwingIdxOfdmBase)); - ThermalValue = (u8)ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_T_METER_88E, 0xfc00); //0x42: RF Reg[15:10] 88E + ThermalValue = (u8)ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_T_METER_88E, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ if( ! ThermalValue || ! pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) return; - //4 3. Initialize ThermalValues of RFCalibrateInfo + /* 4 3. Initialize ThermalValues of RFCalibrateInfo */ if( ! pDM_Odm->RFCalibrateInfo.ThermalValue) { @@ -400,7 +400,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E( ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n")); } - //4 4. Calculate average thermal meter + /* 4 4. Calculate average thermal meter */ pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue; pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++; @@ -422,28 +422,28 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E( ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("AVG Thermal Meter = 0x%x \n", ThermalValue)); } - //4 5. Calculate delta, delta_LCK, delta_IQK. + /* 4 5. Calculate delta, delta_LCK, delta_IQK. */ delta = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue):(pDM_Odm->RFCalibrateInfo.ThermalValue - ThermalValue); delta_LCK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_LCK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK):(pDM_Odm->RFCalibrateInfo.ThermalValue_LCK - ThermalValue); delta_IQK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_IQK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK):(pDM_Odm->RFCalibrateInfo.ThermalValue_IQK - ThermalValue); - //4 6. If necessary, do LCK. + /* 4 6. If necessary, do LCK. */ - //if((delta_LCK > pHalData->Delta_LCK) && (pHalData->Delta_LCK != 0)) - if ((delta_LCK >= 8)) // Delta temperature is equal to or larger than 20 centigrade. + /* if((delta_LCK > pHalData->Delta_LCK) && (pHalData->Delta_LCK != 0)) */ + if ((delta_LCK >= 8)) /* Delta temperature is equal to or larger than 20 centigrade. */ { pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; PHY_LCCalibrate_8188E(Adapter); } - //3 7. If necessary, move the index of swing table to adjust Tx power. + /* 3 7. If necessary, move the index of swing table to adjust Tx power. */ if (delta > 0 && pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) { delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue); - //4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset + /* 4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset */ if(ThermalValue > pHalData->EEPROMThermalMeter) { CALCULATE_SWINGTALBE_OFFSET(offset, POWER_INC, index_mapping_NUM_88E, delta); @@ -472,7 +472,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E( ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pDM_Odm->BbSwingIdxCck, pDM_Odm->BbSwingIdxCckBase, pDM_Odm->RFCalibrateInfo.PowerIndexOffset)); ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("The 'OFDM' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pDM_Odm->BbSwingIdxOfdm, pDM_Odm->BbSwingIdxOfdmBase, pDM_Odm->RFCalibrateInfo.PowerIndexOffset)); - //4 7.1 Handle boundary conditions of index. + /* 4 7.1 Handle boundary conditions of index. */ for(i = 0; i < rf; i++) @@ -506,21 +506,21 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E( if (pDM_Odm->RFCalibrateInfo.PowerIndexOffset != 0 && pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) { - //4 7.2 Configure the Swing Table to adjust Tx Power. + /* 4 7.2 Configure the Swing Table to adjust Tx Power. */ - pDM_Odm->RFCalibrateInfo.bTxPowerChanged = TRUE; // Always TRUE after Tx Power is adjusted by power tracking. - // - // 2012/04/23 MH According to Luke's suggestion, we can not write BB digital - // to increase TX power. Otherwise, EVM will be bad. - // - // 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. + pDM_Odm->RFCalibrateInfo.bTxPowerChanged = TRUE; /* Always TRUE after Tx Power is adjusted by power tracking. */ + /* */ + /* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */ + /* to increase TX power. Otherwise, EVM will be bad. */ + /* */ + /* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */ if (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue) { ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Temperature Increasing: delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", pDM_Odm->RFCalibrateInfo.PowerIndexOffset, delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue)); } - else if (ThermalValue < pDM_Odm->RFCalibrateInfo.ThermalValue)// Low temperature + else if (ThermalValue < pDM_Odm->RFCalibrateInfo.ThermalValue)/* Low temperature */ { ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Temperature Decreasing: delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", @@ -536,8 +536,8 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E( { ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Temperature(%d) lower than PG value(%d), increases the power by TxAGC\n", ThermalValue, pHalData->EEPROMThermalMeter)); odm_TxPwrTrackSetPwr88E(pDM_Odm, BBSWING, RF_PATH_A, Indexforchannel); - //if(is2T) - // odm_TxPwrTrackSetPwr88E(pDM_Odm, BBSWING, RF_PATH_B, Indexforchannel); + /* if(is2T) */ + /* odm_TxPwrTrackSetPwr88E(pDM_Odm, BBSWING, RF_PATH_B, Indexforchannel); */ } pDM_Odm->BbSwingIdxCckBase = pDM_Odm->BbSwingIdxCck; @@ -546,9 +546,9 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E( } - // if((delta_IQK > pHalData->Delta_IQK) && (pHalData->Delta_IQK != 0)) - if ((delta_IQK >= 8)){ // Delta temperature is equal to or larger than 20 centigrade. - //printk("delta_IQK(%d) >=8 do_IQK\n",delta_IQK); + /* if((delta_IQK > pHalData->Delta_IQK) && (pHalData->Delta_IQK != 0)) */ + if ((delta_IQK >= 8)){ /* Delta temperature is equal to or larger than 20 centigrade. */ + /* printk("delta_IQK(%d) >=8 do_IQK\n",delta_IQK); */ doIQK(pDM_Odm, delta_IQK, ThermalValue, 8); } @@ -562,11 +562,11 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E( -//1 7. IQK +/* 1 7. IQK */ #define MAX_TOLERANCE 5 -#define IQK_DELAY_TIME 1 //ms +#define IQK_DELAY_TIME 1 /* ms */ -static u8 //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +static u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ phy_PathA_IQK_8188E( IN struct adapter *pAdapter, IN BOOLEAN configPathB @@ -578,29 +578,29 @@ phy_PathA_IQK_8188E( PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); - //1 Tx IQK - //path-A IQK setting + /* 1 Tx IQK */ + /* path-A IQK setting */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214032a); ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); - //LO calibration setting + /* LO calibration setting */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); - //One shot, path A LOK & IQK + /* One shot, path A LOK & IQK */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - // delay x ms + /* delay x ms */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); - //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); + /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */ ODM_delay_ms(IQK_DELAY_TIME_88E); - // Check failed + /* Check failed */ regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); @@ -614,12 +614,12 @@ phy_PathA_IQK_8188E( (((regE94 & 0x03FF0000)>>16) != 0x142) && (((regE9C & 0x03FF0000)>>16) != 0x42) ) result |= 0x01; - else //if Tx not OK, ignore Rx + else /* if Tx not OK, ignore Rx */ return result; return result; } -static u8 //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +static u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ phy_PathA_RxIQK( IN struct adapter *pAdapter, IN BOOLEAN configPathB @@ -631,8 +631,8 @@ phy_PathA_RxIQK( PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); - //1 Get TXIMR setting - //modify RXIQK mode table + /* 1 Get TXIMR setting */ + /* modify RXIQK mode table */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); @@ -640,38 +640,38 @@ phy_PathA_RxIQK( ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B ); - //PA,PAD off + /* PA,PAD off */ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980 ); ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000 ); ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000); - //IQK setting + /* IQK setting */ ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800); - //path-A IQK setting + /* path-A IQK setting */ ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); - //LO calibration setting + /* LO calibration setting */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - //One shot, path A LOK & IQK + /* One shot, path A LOK & IQK */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - // delay x ms + /* delay x ms */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); - //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); + /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */ ODM_delay_ms(IQK_DELAY_TIME_88E); - // Check failed + /* Check failed */ regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); @@ -687,9 +687,9 @@ phy_PathA_RxIQK( } else { - //reload RF 0xdf + /* reload RF 0xdf */ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); - ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180 );//if Tx not OK, ignore Rx + ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180 );/* if Tx not OK, ignore Rx */ return result; } @@ -698,8 +698,8 @@ phy_PathA_RxIQK( ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); - //1 RX IQK - //modify RXIQK mode table + /* 1 RX IQK */ + /* modify RXIQK mode table */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); @@ -708,31 +708,31 @@ phy_PathA_RxIQK( ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa ); ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000); - //IQK setting + /* IQK setting */ ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); - //path-A IQK setting + /* path-A IQK setting */ ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c05); ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160c1f); - //LO calibration setting + /* LO calibration setting */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); - //One shot, path A LOK & IQK + /* One shot, path A LOK & IQK */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); - // delay x ms + /* delay x ms */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); - //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); + /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */ ODM_delay_ms(IQK_DELAY_TIME_88E); - // Check failed + /* Check failed */ regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); @@ -742,11 +742,11 @@ phy_PathA_RxIQK( regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4)); - //reload RF 0xdf + /* reload RF 0xdf */ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180 ); - if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK + if(!(regEAC & BIT27) && /* if Tx is OK, check whether Rx is OK */ (((regEA4 & 0x03FF0000)>>16) != 0x132) && (((regEAC & 0x03FF0000)>>16) != 0x36)) result |= 0x02; @@ -756,7 +756,7 @@ phy_PathA_RxIQK( return result; } -static u8 //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +static u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ phy_PathB_IQK_8188E( IN struct adapter *pAdapter ) @@ -767,17 +767,17 @@ phy_PathB_IQK_8188E( PDM_ODM_T pDM_Odm = &pHalData->odmpriv; ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); - //One shot, path B LOK & IQK + /* One shot, path B LOK & IQK */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002); ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000); - // delay x ms + /* delay x ms */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_88E)); - //PlatformStallExecution(IQK_DELAY_TIME_88E*1000); + /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */ ODM_delay_ms(IQK_DELAY_TIME_88E); - // Check failed + /* Check failed */ regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); @@ -874,7 +874,7 @@ _PHY_PathBFillIQKMatrix( IN BOOLEAN bIQKOK, IN s32 result[][8], IN u8 final_candidate, - IN BOOLEAN bTxOnly //do Tx only + IN BOOLEAN bTxOnly /* do Tx only */ ) { u32 Oldval_1, X, TX1_A, reg; @@ -924,10 +924,10 @@ _PHY_PathBFillIQKMatrix( } } -// -// 2011/07/26 MH Add an API for testing IQK fail case. -// -// MP Already declare in odm.c +/* */ +/* 2011/07/26 MH Add an API for testing IQK fail case. */ +/* */ +/* MP Already declare in odm.c */ static BOOLEAN ODM_CheckPowerStatus( IN struct adapter * Adapter) @@ -1109,7 +1109,7 @@ phy_SimularityCompare_8188E( u32 i, j, diff, SimularityBitMap, bound = 0; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - u8 final_candidate[2] = {0xFF, 0xFF}; //for path A and path B + u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */ BOOLEAN bResult = TRUE; BOOLEAN is2T; s32 tmp1 = 0,tmp2 = 0; @@ -1133,7 +1133,7 @@ phy_SimularityCompare_8188E( for( i = 0; i < bound; i++ ) { -// diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); +/* diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); */ if((i==1) || (i==3) || (i==5) || (i==7)) { if((result[c1][i]& 0x00000200) != 0) @@ -1190,26 +1190,26 @@ phy_SimularityCompare_8188E( else { - if (!(SimularityBitMap & 0x03)) //path A TX OK + if (!(SimularityBitMap & 0x03)) /* path A TX OK */ { for(i = 0; i < 2; i++) result[3][i] = result[c1][i]; } - if (!(SimularityBitMap & 0x0c)) //path A RX OK + if (!(SimularityBitMap & 0x0c)) /* path A RX OK */ { for(i = 2; i < 4; i++) result[3][i] = result[c1][i]; } - if (!(SimularityBitMap & 0x30)) //path B TX OK + if (!(SimularityBitMap & 0x30)) /* path B TX OK */ { for(i = 4; i < 6; i++) result[3][i] = result[c1][i]; } - if (!(SimularityBitMap & 0xc0)) //path B RX OK + if (!(SimularityBitMap & 0xc0)) /* path B RX OK */ { for(i = 6; i < 8; i++) result[3][i] = result[c1][i]; @@ -1245,7 +1245,7 @@ phy_IQCalibrate_8188E( REG_TXPAUSE, REG_BCN_CTRL, REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; - //since 92C & 92D have the different define in IQK_BB_REG + /* since 92C & 92D have the different define in IQK_BB_REG */ u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = { rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, @@ -1262,14 +1262,14 @@ if ( *(pDM_Odm->mp_mode) == 1) retryCount = 9; else retryCount = 2; - // Note: IQ calibration must be performed after loading - // PHY_REG.txt , and radio_a, radio_b.txt + /* Note: IQ calibration must be performed after loading */ + /* PHY_REG.txt , and radio_a, radio_b.txt */ if(t==0) { ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); - // Save ADDA parameters, turn Path A ADDA on + /* Save ADDA parameters, turn Path A ADDA on */ _PHY_SaveADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); _PHY_SaveMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); @@ -1283,11 +1283,11 @@ else } if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ - // Switch BB to PI mode to do IQ Calibration. + /* Switch BB to PI mode to do IQ Calibration. */ _PHY_PIModeSwitch(pAdapter, TRUE); } - //BB setting + /* BB setting */ ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00); ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); @@ -1306,11 +1306,11 @@ else ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000); } - //MAC settings + /* MAC settings */ _PHY_MACSettingCalibration(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); - //Page B init - //AP or IQK + /* Page B init */ + /* AP or IQK */ ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); if(is2T) @@ -1318,7 +1318,7 @@ else ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000); } - // IQ calibration setting + /* IQ calibration setting */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n")); ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000); ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); @@ -1353,7 +1353,7 @@ else if(is2T){ _PHY_PathAStandBy(pAdapter); - // Turn Path B ADDA on + /* Turn Path B ADDA on */ _PHY_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T); for(i = 0 ; i < retryCount ; i++){ @@ -1366,7 +1366,7 @@ else result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; break; } - else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK + else if (i == (retryCount - 1) && PathBOK == 0x01) /* Tx IQK OK */ { ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Only Tx IQK Success!!\n")); result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; @@ -1379,32 +1379,32 @@ else } } - //Back to BB mode, load original value + /* Back to BB mode, load original value */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0); if(t!=0) { if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){ - // Switch back BB to SI mode after finish IQ Calibration. + /* Switch back BB to SI mode after finish IQ Calibration. */ _PHY_PIModeSwitch(pAdapter, FALSE); } - // Reload ADDA power saving parameters + /* Reload ADDA power saving parameters */ _PHY_ReloadADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); - // Reload MAC parameters + /* Reload MAC parameters */ _PHY_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); - // Restore RX initial gain + /* Restore RX initial gain */ ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3); if(is2T){ ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3); } - //load 0xe30 IQC default value + /* load 0xe30 IQC default value */ ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); @@ -1425,60 +1425,60 @@ phy_LCCalibrate_8188E( HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); PDM_ODM_T pDM_Odm = &pHalData->odmpriv; - //Check continuous TX and Packet TX + /* Check continuous TX and Packet TX */ tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); - if((tmpReg&0x70) != 0) //Deal with contisuous TX case - ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); //disable all continuous TX - else // Deal with Packet TX case - ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // block all queues + if((tmpReg&0x70) != 0) /* Deal with contisuous TX case */ + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); /* disable all continuous TX */ + else /* Deal with Packet TX case */ + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); /* block all queues */ if((tmpReg&0x70) != 0) { - //1. Read original RF mode - //Path-A + /* 1. Read original RF mode */ + /* Path-A */ RF_Amode = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits); - //Path-B + /* Path-B */ if(is2T) RF_Bmode = PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits); - //2. Set RF mode = standby mode - //Path-A + /* 2. Set RF mode = standby mode */ + /* Path-A */ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); - //Path-B + /* Path-B */ if(is2T) ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); } - //3. Read RF reg18 + /* 3. Read RF reg18 */ LC_Cal = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits); - //4. Set LC calibration begin bit15 + /* 4. Set LC calibration begin bit15 */ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); ODM_sleep_ms(100); - //Restore original situation - if((tmpReg&0x70) != 0) //Deal with contisuous TX case + /* Restore original situation */ + if((tmpReg&0x70) != 0) /* Deal with contisuous TX case */ { - //Path-A + /* Path-A */ ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); - //Path-B + /* Path-B */ if(is2T) ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); } - else // Deal with Packet TX case + else /* Deal with Packet TX case */ { ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); } } -//Analog Pre-distortion calibration +/* Analog Pre-distortion calibration */ #define APK_BB_REG_NUM 8 #define APK_CURVE_REG_NUM 4 #define PATH_NUM 2 @@ -1530,7 +1530,7 @@ phy_APCalibrate_8188E( }; u32 APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { - {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings + {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, /* path settings equal to path b settings */ {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} }; @@ -1540,12 +1540,12 @@ phy_APCalibrate_8188E( }; u32 APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { - {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, /* path settings equal to path b settings */ {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} }; u32 AFE_on_off[PATH_NUM] = { - 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on + 0x04db25a4, 0x0b1b25a4}; /* path A on path B off / path A off path B on */ u32 APK_offset[PATH_NUM] = { rConfig_AntA, rConfig_AntB}; @@ -1580,8 +1580,8 @@ phy_APCalibrate_8188E( 0x00050006 }; - u32 APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a -// u32 AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; + u32 APK_result[PATH_NUM][APK_BB_REG_NUM]; /* val_1_1a, val_1_2a, val_2a, val_3a, val_4a */ +/* u32 AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; */ s32 BB_offset, delta_V, delta_offset; @@ -1599,17 +1599,17 @@ if ( *(pDM_Odm->mp_mode) == 1) if(!is2T) pathbound = 1; - //2 FOR NORMAL CHIP SETTINGS + /* 2 FOR NORMAL CHIP SETTINGS */ -// Temporarily do not allow normal driver to do the following settings because these offset -// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal -// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the -// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. -//#if MP_DRIVER != 1 +/* Temporarily do not allow normal driver to do the following settings because these offset */ +/* and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal */ +/* will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the */ +/* root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. */ +/* if MP_DRIVER != 1 */ if (*(pDM_Odm->mp_mode) != 1) return; -//#endif - //settings adjust for normal chip +/* endif */ + /* settings adjust for normal chip */ for(index = 0; index < PATH_NUM; index ++) { APK_offset[index] = APK_normal_offset[index]; @@ -1629,18 +1629,18 @@ if (*(pDM_Odm->mp_mode) != 1) apkbound = 6; - //save BB default value + /* save BB default value */ for(index = 0; index < APK_BB_REG_NUM ; index++) { - if(index == 0) //skip + if(index == 0) /* skip */ continue; BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); } - //save MAC default value + /* save MAC default value */ _PHY_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup); - //save AFE default value + /* save AFE default value */ _PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); for(path = 0; path < pathbound; path++) @@ -1649,9 +1649,9 @@ if (*(pDM_Odm->mp_mode) != 1) if(path == RF_PATH_A) { - //path A APK - //load APK setting - //path-A + /* path A APK */ + /* load APK setting */ + /* path-A */ offset = rPdp_AntA; for(index = 0; index < 11; index ++) { @@ -1672,10 +1672,10 @@ if (*(pDM_Odm->mp_mode) != 1) offset += 0x04; } - //page-B1 + /* page-B1 */ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); - //path A + /* path A */ offset = rPdp_AntA; for(index = 0; index < 16; index++) { @@ -1688,9 +1688,9 @@ if (*(pDM_Odm->mp_mode) != 1) } else if(path == RF_PATH_B) { - //path B APK - //load APK setting - //path-B + /* path B APK */ + /* load APK setting */ + /* path-B */ offset = rPdp_AntB; for(index = 0; index < 10; index ++) { @@ -1704,7 +1704,7 @@ if (*(pDM_Odm->mp_mode) != 1) offset = rConfig_AntA; index = 11; - for(; index < 13; index ++) //offset 0xb68, 0xb6c + for(; index < 13; index ++) /* offset 0xb68, 0xb6c */ { ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); @@ -1712,10 +1712,10 @@ if (*(pDM_Odm->mp_mode) != 1) offset += 0x04; } - //page-B1 + /* page-B1 */ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000); - //path B + /* path B */ offset = 0xb60; for(index = 0; index < 16; index++) { @@ -1727,21 +1727,21 @@ if (*(pDM_Odm->mp_mode) != 1) ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0); } - //save RF default value + /* save RF default value */ regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); - //Path A AFE all on, path B AFE All off or vise versa + /* Path A AFE all on, path B AFE All off or vise versa */ for(index = 0; index < IQK_ADDA_REG_NUM ; index++) ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); - //BB to AP mode + /* BB to AP mode */ if(path == 0) { for(index = 0; index < APK_BB_REG_NUM ; index++) { - if(index == 0) //skip + if(index == 0) /* skip */ continue; else if (index < 5) ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); @@ -1754,7 +1754,7 @@ if (*(pDM_Odm->mp_mode) != 1) ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); } - else //path B + else /* path B */ { ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); @@ -1763,14 +1763,14 @@ if (*(pDM_Odm->mp_mode) != 1) ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); - //MAC settings + /* MAC settings */ _PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup); - if(path == RF_PATH_A) //Path B to standby mode + if(path == RF_PATH_A) /* Path B to standby mode */ { ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x10000); } - else //Path A to standby mode + else /* Path A to standby mode */ { ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000); ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); @@ -1783,10 +1783,10 @@ if (*(pDM_Odm->mp_mode) != 1) else if (delta_offset > 12) delta_offset = 12; - //AP calibration + /* AP calibration */ for(index = 0; index < APK_BB_REG_NUM; index++) { - if(index != 1) //only DO PA11+PAD01001, AP RF setting + if(index != 1) /* only DO PA11+PAD01001, AP RF setting */ continue; tmpReg = APK_RF_init_value[path][index]; @@ -1795,7 +1795,7 @@ if (*(pDM_Odm->mp_mode) != 1) { BB_offset = (tmpReg & 0xF0000) >> 16; - if(!(tmpReg & BIT15)) //sign bit 0 + if(!(tmpReg & BIT15)) /* sign bit 0 */ { BB_offset = -BB_offset; } @@ -1826,7 +1826,7 @@ if (*(pDM_Odm->mp_mode) != 1) ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); - // PA11+PAD01111, one shot + /* PA11+PAD01111, one shot */ i = 0; do { @@ -1857,22 +1857,22 @@ if (*(pDM_Odm->mp_mode) != 1) } } - //reload MAC default value + /* reload MAC default value */ _PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup); - //reload BB default value + /* reload BB default value */ for(index = 0; index < APK_BB_REG_NUM ; index++) { - if(index == 0) //skip + if(index == 0) /* skip */ continue; ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); } - //reload AFE default value + /* reload AFE default value */ _PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); - //reload RF path default value + /* reload RF path default value */ for(path = 0; path < pathbound; path++) { ODM_SetRFReg(pDM_Odm, path, 0xd, bMaskDWord, regD[path]); @@ -1882,7 +1882,7 @@ if (*(pDM_Odm->mp_mode) != 1) ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); } - //note no index == 0 + /* note no index == 0 */ if (APK_result[path][1] > 6) APK_result[path][1] = 6; ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); @@ -1936,9 +1936,9 @@ PHY_IQCalibrate_8188E( #if (MP_DRIVER == 1) PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif//(MP_DRIVER == 1) + #endif/* MP_DRIVER == 1) */ - s32 result[4][8]; //last is final result + s32 result[4][8]; /* last is final result */ u8 i, final_candidate, Indexforchannel; u8 channelToIQK = 7; BOOLEAN bPathAOK, bPathBOK; @@ -1971,7 +1971,7 @@ if (*(pDM_Odm->mp_mode) == 1) } #endif - // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + /* 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) */ if(bSingleTone || bCarrierSuppression) return; @@ -2004,8 +2004,8 @@ if (*(pDM_Odm->mp_mode) == 1) is13simular = FALSE; - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK !!!interface %d currentband %d ishardwareD %d \n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, IS_HARDWARE_TYPE_8192D(pAdapter))); -// RT_TRACE(COMP_INIT,DBG_LOUD,("Acquire Mutex in IQCalibrate \n")); + /* ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK !!!interface %d currentband %d ishardwareD %d \n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, IS_HARDWARE_TYPE_8192D(pAdapter))); */ +/* RT_TRACE(COMP_INIT,DBG_LOUD,("Acquire Mutex in IQCalibrate \n")); */ for (i=0; i<3; i++) { @@ -2048,7 +2048,7 @@ if (*(pDM_Odm->mp_mode) == 1) } } } -// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n")); +/* RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n")); */ for (i=0; i<4; i++) { @@ -2079,8 +2079,8 @@ if (*(pDM_Odm->mp_mode) == 1) } else { ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n")); - pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; //X default value - pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; //Y default value + pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; /* X default value */ + pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; /* Y default value */ } if((RegE94 != 0)/*&&(RegEA4 != 0)*/) @@ -2093,15 +2093,15 @@ if (*(pDM_Odm->mp_mode) == 1) Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); -//To Fix BSOD when final_candidate is 0xff -//by sherry 20120321 +/* To Fix BSOD when final_candidate is 0xff */ +/* by sherry 20120321 */ if(final_candidate < 4) { for(i = 0; i < IQK_Matrix_REG_NUM; i++) pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; } - //RTPRINT(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); + /* RTPRINT(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); @@ -2121,7 +2121,7 @@ PHY_LCCalibrate_8188E( #if (MP_DRIVER == 1) PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - #endif//(MP_DRIVER == 1) + #endif/* MP_DRIVER == 1) */ @@ -2144,7 +2144,7 @@ if (*(pDM_Odm->mp_mode) == 1) { return; } - // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + /* 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) */ if(bSingleTone || bCarrierSuppression) return; @@ -2156,7 +2156,7 @@ if (*(pDM_Odm->mp_mode) == 1) pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount)); + /* ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount)); */ if(pDM_Odm->RFType == ODM_2T2R) { @@ -2164,7 +2164,7 @@ if (*(pDM_Odm->mp_mode) == 1) } else { - // For 88C 1T1R + /* For 88C 1T1R */ phy_LCCalibrate_8188E(pAdapter, FALSE); } @@ -2200,7 +2200,7 @@ PHY_APCalibrate_8188E( } else { - // For 88C 1T1R + /* For 88C 1T1R */ phy_APCalibrate_8188E(pAdapter, delta, FALSE); } } @@ -2219,23 +2219,23 @@ static void phy_SetRFPathSwitch_8188E( u8 u1bTmp; u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7; ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp); - //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); + /* ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); */ ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01); } - if(is2T) //92C + if(is2T) /* 92C */ { if(bMain) - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); /* 92C_Path_A */ else - ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); /* BT */ } - else //88C + else /* 88C */ { if(bMain) - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2); //Main + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2); /* Main */ else - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1); //Aux + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1); /* Aux */ } } void PHY_SetRFPathSwitch_8188E( @@ -2256,7 +2256,7 @@ void PHY_SetRFPathSwitch_8188E( } else { - // For 88C 1T1R + /* For 88C 1T1R */ phy_SetRFPathSwitch_8188E(pAdapter, bMain, FALSE); } } diff --git a/hal/HalPhyRf_8188e.h b/hal/HalPhyRf_8188e.h index 2bc9778..735144b 100755 --- a/hal/HalPhyRf_8188e.h +++ b/hal/HalPhyRf_8188e.h @@ -23,7 +23,7 @@ /*--------------------------Define Parameters-------------------------------*/ -#define IQK_DELAY_TIME_88E 10 //ms +#define IQK_DELAY_TIME_88E 10 /* ms */ #define index_mapping_NUM_88E 15 #define AVG_THERMAL_NUM_88E 4 @@ -36,9 +36,9 @@ typedef enum _PWRTRACK_CONTROL_METHOD { void ODM_TxPwrTrackAdjust88E( PDM_ODM_T pDM_Odm, - u8 Type, // 0 = OFDM, 1 = CCK - u8 * pDirection, // 1 = +(increase) 2 = -(decrease) - u32 * pOutWriteVal // Tx tracking CCK/OFDM BB swing index adjust + u8 Type, /* 0 = OFDM, 1 = CCK */ + u8 * pDirection, /* 1 = +(increase) 2 = -(decrease) */ + u32 * pOutWriteVal /* Tx tracking CCK/OFDM BB swing index adjust */ ); @@ -48,7 +48,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E( ); -//1 7. IQK +/* 1 7. IQK */ void PHY_IQCalibrate_8188E( @@ -56,17 +56,17 @@ PHY_IQCalibrate_8188E( IN BOOLEAN bReCovery); -// -// LC calibrate -// +/* */ +/* LC calibrate */ +/* */ void PHY_LCCalibrate_8188E( IN struct adapter * pAdapter ); -// -// AP calibrate -// +/* */ +/* AP calibrate */ +/* */ void PHY_APCalibrate_8188E( IN struct adapter * pAdapter, @@ -106,5 +106,5 @@ _PHY_PathAStandBy( ); -#endif // #ifndef __HAL_PHY_RF_8188E_H__ +#endif /* #ifndef __HAL_PHY_RF_8188E_H__ */ diff --git a/hal/HalPwrSeqCmd.c b/hal/HalPwrSeqCmd.c index 7104bfe..a40ce03 100755 --- a/hal/HalPwrSeqCmd.c +++ b/hal/HalPwrSeqCmd.c @@ -35,15 +35,15 @@ Major Change History: --*/ #include -// -// Description: -// This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC. -// -// Assumption: -// We should follow specific format which was released from HW SD. -// -// 2011.07.07, added by Roger. -// +/* */ +/* Description: */ +/* This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC. */ +/* */ +/* Assumption: */ +/* We should follow specific format which was released from HW SD. */ +/* */ +/* 2011.07.07, added by Roger. */ +/* */ u8 HalPwrSeqCmdParsing( struct adapter * padapter, u8 CutVersion, @@ -56,7 +56,7 @@ u8 HalPwrSeqCmdParsing( u32 AryIdx = 0; u8 value = 0; u32 offset = 0; - u32 pollingCount = 0; // polling autoload done. + u32 pollingCount = 0; /* polling autoload done. */ u32 maxPollingCnt = 5000; do { @@ -73,7 +73,7 @@ u8 HalPwrSeqCmdParsing( GET_PWR_CFG_MASK(PwrCfgCmd), GET_PWR_CFG_VALUE(PwrCfgCmd))); - //2 Only Handle the command whose FAB, CUT, and Interface are matched + /* 2 Only Handle the command whose FAB, CUT, and Interface are matched */ if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) && (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) && (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)) @@ -88,13 +88,13 @@ u8 HalPwrSeqCmdParsing( RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n")); offset = GET_PWR_CFG_OFFSET(PwrCfgCmd); - // Read the value from system register + /* Read the value from system register */ value = rtw_read8(padapter, offset); value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd)); value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)); - // Write the value back to sytem register + /* Write the value back to sytem register */ rtw_write8(padapter, offset, value); break; case PWR_CMD_POLLING: @@ -128,7 +128,7 @@ u8 HalPwrSeqCmdParsing( break; case PWR_CMD_END: - // When this command is parsed, end the process + /* When this command is parsed, end the process */ RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n")); return true; break; @@ -139,7 +139,7 @@ u8 HalPwrSeqCmdParsing( } } - AryIdx++;//Add Array Index + AryIdx++;/* Add Array Index */ }while(1); return true; diff --git a/hal/hal_com.c b/hal/hal_com.c index 8e7cd5a..1e1d9b3 100755 --- a/hal/hal_com.c +++ b/hal/hal_com.c @@ -71,12 +71,12 @@ void dump_chip_info(HAL_VERSION ChipVersion) #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 -u8 //return the final channel plan decision +u8 /* return the final channel plan decision */ hal_com_get_channel_plan( IN struct adapter *padapter, - IN u8 hw_channel_plan, //channel plan from HW (efuse/eeprom) - IN u8 sw_channel_plan, //channel plan from SW (registry/module param) - IN u8 def_channel_plan, //channel plan used when the former two is invalid + IN u8 hw_channel_plan, /* channel plan from HW (efuse/eeprom) */ + IN u8 sw_channel_plan, /* channel plan from SW (registry/module param) */ + IN u8 def_channel_plan, /* channel plan used when the former two is invalid */ IN BOOLEAN AutoLoadFail ) { @@ -109,7 +109,7 @@ u8 MRateToHwRate(u8 rate) switch(rate) { - // CCK and OFDM non-HT rates + /* CCK and OFDM non-HT rates */ case IEEE80211_CCK_RATE_1MB: ret = DESC_RATE1M; break; case IEEE80211_CCK_RATE_2MB: ret = DESC_RATE2M; break; case IEEE80211_CCK_RATE_5MB: ret = DESC_RATE5_5M; break; @@ -123,15 +123,15 @@ u8 MRateToHwRate(u8 rate) case IEEE80211_OFDM_RATE_48MB: ret = DESC_RATE48M; break; case IEEE80211_OFDM_RATE_54MB: ret = DESC_RATE54M; break; - // HT rates since here - //case MGN_MCS0: ret = DESC_RATEMCS0; break; - //case MGN_MCS1: ret = DESC_RATEMCS1; break; - //case MGN_MCS2: ret = DESC_RATEMCS2; break; - //case MGN_MCS3: ret = DESC_RATEMCS3; break; - //case MGN_MCS4: ret = DESC_RATEMCS4; break; - //case MGN_MCS5: ret = DESC_RATEMCS5; break; - //case MGN_MCS6: ret = DESC_RATEMCS6; break; - //case MGN_MCS7: ret = DESC_RATEMCS7; break; + /* HT rates since here */ + /* case MGN_MCS0: ret = DESC_RATEMCS0; break; */ + /* case MGN_MCS1: ret = DESC_RATEMCS1; break; */ + /* case MGN_MCS2: ret = DESC_RATEMCS2; break; */ + /* case MGN_MCS3: ret = DESC_RATEMCS3; break; */ + /* case MGN_MCS4: ret = DESC_RATEMCS4; break; */ + /* case MGN_MCS5: ret = DESC_RATEMCS5; break; */ + /* case MGN_MCS6: ret = DESC_RATEMCS6; break; */ + /* case MGN_MCS7: ret = DESC_RATEMCS7; break; */ default: break; } @@ -179,15 +179,15 @@ _OneOutPipeMapping( { struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter); - pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO - pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];//VI - pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];//BE - pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];//BK + pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */ + pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */ + pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];/* BE */ + pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */ - pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN - pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT - pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH - pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD + pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */ + pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */ + pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */ + pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */ } static void @@ -198,39 +198,39 @@ _TwoOutPipeMapping( { struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter); - if(bWIFICfg){ //WMM + if(bWIFICfg){ /* WMM */ - // BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA - //{ 0, 1, 0, 1, 0, 0, 0, 0, 0 }; - //0:H, 1:L + /* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */ + /* 0, 1, 0, 1, 0, 0, 0, 0, 0 }; */ + /* 0:H, 1:L */ - pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];//VO - pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];//VI - pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];//BE - pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];//BK + pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];/* VO */ + pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */ + pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */ + pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */ - pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN - pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT - pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH - pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD + pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */ + pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */ + pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */ + pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */ } - else{//typical setting + else{/* typical setting */ - //BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA - //{ 1, 1, 0, 0, 0, 0, 0, 0, 0 }; - //0:H, 1:L + /* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */ + /* 1, 1, 0, 0, 0, 0, 0, 0, 0 }; */ + /* 0:H, 1:L */ - pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO - pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];//VI - pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];//BE - pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];//BK + pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */ + pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */ + pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */ + pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */ - pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN - pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT - pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH - pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD + pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */ + pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */ + pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */ + pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */ } @@ -243,39 +243,39 @@ static void _ThreeOutPipeMapping( { struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter); - if(bWIFICfg){//for WMM + if(bWIFICfg){/* for WMM */ - // BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA - //{ 1, 2, 1, 0, 0, 0, 0, 0, 0 }; - //0:H, 1:N, 2:L + /* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */ + /* 1, 2, 1, 0, 0, 0, 0, 0, 0 }; */ + /* 0:H, 1:N, 2:L */ - pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO - pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];//VI - pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];//BE - pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];//BK + pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */ + pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */ + pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */ + pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */ - pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN - pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT - pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH - pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD + pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */ + pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */ + pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */ + pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */ } - else{//typical setting + else{/* typical setting */ - // BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA - //{ 2, 2, 1, 0, 0, 0, 0, 0, 0 }; - //0:H, 1:N, 2:L + /* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */ + /* 2, 2, 1, 0, 0, 0, 0, 0, 0 }; */ + /* 0:H, 1:N, 2:L */ - pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO - pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];//VI - pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];//BE - pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];//BK + pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */ + pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */ + pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */ + pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];/* BK */ - pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN - pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT - pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH - pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD + pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */ + pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */ + pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */ + pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */ } } diff --git a/hal/hal_intf.c b/hal/hal_intf.c index ac83021..8f3d130 100755 --- a/hal/hal_intf.c +++ b/hal/hal_intf.c @@ -63,7 +63,7 @@ void rtw_hal_dm_init(struct adapter *padapter) } void rtw_hal_dm_deinit(struct adapter *padapter) { - // cancel dm timer + /* cancel dm timer */ if (is_primary_adapter(padapter)) if(padapter->HalFunc.dm_deinit) padapter->HalFunc.dm_deinit(padapter); @@ -282,7 +282,7 @@ s32 rtw_hal_mgnt_xmit(struct adapter *padapter, struct xmit_frame *pmgntframe) if(IS_MCAST(pmgntframe->attrib.ra)) { pmgntframe->attrib.encrypt = _BIP_; - //pmgntframe->attrib.bswenc = true; + /* pmgntframe->attrib.bswenc = true; */ } else { @@ -291,7 +291,7 @@ s32 rtw_hal_mgnt_xmit(struct adapter *padapter, struct xmit_frame *pmgntframe) } rtw_mgmt_xmitframe_coalesce(padapter, pmgntframe->pkt, pmgntframe); } -#endif //CONFIG_IEEE80211W +#endif /* CONFIG_IEEE80211W */ if(padapter->HalFunc.mgnt_xmit) ret = padapter->HalFunc.mgnt_xmit(padapter, pmgntframe); @@ -444,7 +444,7 @@ s32 rtw_hal_hostap_mgnt_xmit_entry(struct adapter *padapter, _pkt *pkt) return padapter->HalFunc.hostap_mgnt_xmit_entry(padapter, pkt); return _FAIL; } -#endif //CONFIG_HOSTAPD_MLME +#endif /* CONFIG_HOSTAPD_MLME */ #ifdef DBG_CONFIG_ERROR_DETECT void rtw_hal_sreset_init(struct adapter *padapter) @@ -500,7 +500,7 @@ bool rtw_hal_sreset_inprogress(struct adapter *padapter) inprogress = padapter->HalFunc.sreset_inprogress(padapter); return inprogress; } -#endif //DBG_CONFIG_ERROR_DETECT +#endif /* DBG_CONFIG_ERROR_DETECT */ #ifdef CONFIG_IOL int rtw_hal_iol_cmd(struct adapter *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt) diff --git a/hal/odm.c b/hal/odm.c index fbf8f61..4436c73 100755 --- a/hal/odm.c +++ b/hal/odm.c @@ -18,9 +18,9 @@ * ******************************************************************************/ -//============================================================ -// include files -//============================================================ +/* */ +/* include files */ +/* */ #include "odm_precomp.h" @@ -36,152 +36,148 @@ static const u16 dB_Invert_Table[8][12] = { { 4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849}, { 17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535}}; -// 20100515 Joseph: Add global variable to keep temporary scan list for antenna switching test. -//u8 tmpNumBssDesc; -//RT_WLAN_BSS tmpbssDesc[MAX_BSS_DESC]; +/* 20100515 Joseph: Add global variable to keep temporary scan list for antenna switching test. */ +/* u8 tmpNumBssDesc; */ +/* RT_WLAN_BSS tmpbssDesc[MAX_BSS_DESC]; */ -//============================================================ +/* */ -//avoid to warn in FreeBSD ==> To DO modify +/* avoid to warn in FreeBSD ==> To DO modify */ static u32 EDCAParam[HT_IOT_PEER_MAX][3] = -{ // UL DL - {0x5ea42b, 0x5ea42b, 0x5ea42b}, //0:unknown AP - {0xa44f, 0x5ea44f, 0x5e431c}, // 1:realtek AP - {0x5ea42b, 0x5ea42b, 0x5ea42b}, // 2:unknown AP => realtek_92SE - {0x5ea32b, 0x5ea42b, 0x5e4322}, // 3:broadcom AP - {0x5ea422, 0x00a44f, 0x00a44f}, // 4:ralink AP - {0x5ea322, 0x00a630, 0x00a44f}, // 5:atheros AP - //{0x5ea42b, 0x5ea42b, 0x5ea42b},// 6:cisco AP - {0x5e4322, 0x5e4322, 0x5e4322},// 6:cisco AP - //{0x3ea430, 0x00a630, 0x3ea44f}, // 7:cisco AP - {0x5ea44f, 0x00a44f, 0x5ea42b}, // 8:marvell AP - //{0x5ea44f, 0x5ea44f, 0x5ea44f}, // 9realtek AP - {0x5ea42b, 0x5ea42b, 0x5ea42b}, // 10:unknown AP=> 92U AP - {0x5ea42b, 0xa630, 0x5e431c}, // 11:airgocap AP -// {0x5e4322, 0x00a44f, 0x5ea44f}, // 12:unknown AP +{ /* UL DL */ + {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */ + {0xa44f, 0x5ea44f, 0x5e431c}, /* 1:realtek AP */ + {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 2:unknown AP => realtek_92SE */ + {0x5ea32b, 0x5ea42b, 0x5e4322}, /* 3:broadcom AP */ + {0x5ea422, 0x00a44f, 0x00a44f}, /* 4:ralink AP */ + {0x5ea322, 0x00a630, 0x00a44f}, /* 5:atheros AP */ + {0x5e4322, 0x5e4322, 0x5e4322},/* 6:cisco AP */ + {0x5ea44f, 0x00a44f, 0x5ea42b}, /* 8:marvell AP */ + {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 10:unknown AP=> 92U AP */ + {0x5ea42b, 0xa630, 0x5e431c}, /* 11:airgocap AP */ }; -//============================================================ -// Global var -//============================================================ +/* */ +/* Global var */ +/* */ u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] = { - 0x7f8001fe, // 0, +6.0dB - 0x788001e2, // 1, +5.5dB - 0x71c001c7, // 2, +5.0dB - 0x6b8001ae, // 3, +4.5dB - 0x65400195, // 4, +4.0dB - 0x5fc0017f, // 5, +3.5dB - 0x5a400169, // 6, +3.0dB - 0x55400155, // 7, +2.5dB - 0x50800142, // 8, +2.0dB - 0x4c000130, // 9, +1.5dB - 0x47c0011f, // 10, +1.0dB - 0x43c0010f, // 11, +0.5dB - 0x40000100, // 12, +0dB - 0x3c8000f2, // 13, -0.5dB - 0x390000e4, // 14, -1.0dB - 0x35c000d7, // 15, -1.5dB - 0x32c000cb, // 16, -2.0dB - 0x300000c0, // 17, -2.5dB - 0x2d4000b5, // 18, -3.0dB - 0x2ac000ab, // 19, -3.5dB - 0x288000a2, // 20, -4.0dB - 0x26000098, // 21, -4.5dB - 0x24000090, // 22, -5.0dB - 0x22000088, // 23, -5.5dB - 0x20000080, // 24, -6.0dB - 0x1e400079, // 25, -6.5dB - 0x1c800072, // 26, -7.0dB - 0x1b00006c, // 27. -7.5dB - 0x19800066, // 28, -8.0dB - 0x18000060, // 29, -8.5dB - 0x16c0005b, // 30, -9.0dB - 0x15800056, // 31, -9.5dB - 0x14400051, // 32, -10.0dB - 0x1300004c, // 33, -10.5dB - 0x12000048, // 34, -11.0dB - 0x11000044, // 35, -11.5dB - 0x10000040, // 36, -12.0dB - 0x0f00003c,// 37, -12.5dB - 0x0e400039,// 38, -13.0dB - 0x0d800036,// 39, -13.5dB - 0x0cc00033,// 40, -14.0dB - 0x0c000030,// 41, -14.5dB - 0x0b40002d,// 42, -15.0dB + 0x7f8001fe, /* 0, +6.0dB */ + 0x788001e2, /* 1, +5.5dB */ + 0x71c001c7, /* 2, +5.0dB */ + 0x6b8001ae, /* 3, +4.5dB */ + 0x65400195, /* 4, +4.0dB */ + 0x5fc0017f, /* 5, +3.5dB */ + 0x5a400169, /* 6, +3.0dB */ + 0x55400155, /* 7, +2.5dB */ + 0x50800142, /* 8, +2.0dB */ + 0x4c000130, /* 9, +1.5dB */ + 0x47c0011f, /* 10, +1.0dB */ + 0x43c0010f, /* 11, +0.5dB */ + 0x40000100, /* 12, +0dB */ + 0x3c8000f2, /* 13, -0.5dB */ + 0x390000e4, /* 14, -1.0dB */ + 0x35c000d7, /* 15, -1.5dB */ + 0x32c000cb, /* 16, -2.0dB */ + 0x300000c0, /* 17, -2.5dB */ + 0x2d4000b5, /* 18, -3.0dB */ + 0x2ac000ab, /* 19, -3.5dB */ + 0x288000a2, /* 20, -4.0dB */ + 0x26000098, /* 21, -4.5dB */ + 0x24000090, /* 22, -5.0dB */ + 0x22000088, /* 23, -5.5dB */ + 0x20000080, /* 24, -6.0dB */ + 0x1e400079, /* 25, -6.5dB */ + 0x1c800072, /* 26, -7.0dB */ + 0x1b00006c, /* 27. -7.5dB */ + 0x19800066, /* 28, -8.0dB */ + 0x18000060, /* 29, -8.5dB */ + 0x16c0005b, /* 30, -9.0dB */ + 0x15800056, /* 31, -9.5dB */ + 0x14400051, /* 32, -10.0dB */ + 0x1300004c, /* 33, -10.5dB */ + 0x12000048, /* 34, -11.0dB */ + 0x11000044, /* 35, -11.5dB */ + 0x10000040, /* 36, -12.0dB */ + 0x0f00003c,/* 37, -12.5dB */ + 0x0e400039,/* 38, -13.0dB */ + 0x0d800036,/* 39, -13.5dB */ + 0x0cc00033,/* 40, -14.0dB */ + 0x0c000030,/* 41, -14.5dB */ + 0x0b40002d,/* 42, -15.0dB */ }; u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { - {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0dB - {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 1, -0.5dB - {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 2, -1.0dB - {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 3, -1.5dB - {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 4, -2.0dB - {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 5, -2.5dB - {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 6, -3.0dB - {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 7, -3.5dB - {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 8, -4.0dB - {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 9, -4.5dB - {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 10, -5.0dB - {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 11, -5.5dB - {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 12, -6.0dB - {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 13, -6.5dB - {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 14, -7.0dB - {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 15, -7.5dB - {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB - {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 17, -8.5dB - {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 18, -9.0dB - {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 19, -9.5dB - {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 20, -10.0dB - {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 21, -10.5dB - {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 22, -11.0dB - {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 23, -11.5dB - {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 24, -12.0dB - {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 25, -12.5dB - {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 26, -13.0dB - {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 27, -13.5dB - {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 28, -14.0dB - {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 29, -14.5dB - {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 30, -15.0dB - {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 31, -15.5dB - {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} // 32, -16.0dB + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */ + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */ + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */ + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */ + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */ + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */ + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */ + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */ + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */ + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */ + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */ + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */ + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */ + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */ + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */ + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */ + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */ + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */ + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */ + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */ + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */ + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */ + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */ + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */ + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */ }; u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]= { - {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0dB - {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 1, -0.5dB - {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 2, -1.0dB - {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 3, -1.5dB - {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 4, -2.0dB - {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 5, -2.5dB - {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 6, -3.0dB - {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 7, -3.5dB - {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 8, -4.0dB - {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 9, -4.5dB - {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 10, -5.0dB - {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 11, -5.5dB - {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 12, -6.0dB - {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 13, -6.5dB - {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 14, -7.0dB - {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 15, -7.5dB - {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB - {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 17, -8.5dB - {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 18, -9.0dB - {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 19, -9.5dB - {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 20, -10.0dB - {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 21, -10.5dB - {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 22, -11.0dB - {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 23, -11.5dB - {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 24, -12.0dB - {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 25, -12.5dB - {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 26, -13.0dB - {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 27, -13.5dB - {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 28, -14.0dB - {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 29, -14.5dB - {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 30, -15.0dB - {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 31, -15.5dB - {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} // 32, -16.0dB + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */ + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */ + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */ + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */ + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */ + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */ + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */ + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */ + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */ + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */ + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */ + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */ + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */ + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */ + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */ + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */ + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */ + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */ + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */ + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */ + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */ }; @@ -228,11 +224,11 @@ unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = { }; #endif -//============================================================ -// Local Function predefine. -//============================================================ +/* */ +/* Local Function predefine. */ +/* */ -//START------------COMMON INFO RELATED---------------// +/* START------------COMMON INFO RELATED--------------- */ void odm_CommonInfoSelfInit( IN PDM_ODM_T pDM_Odm @@ -268,9 +264,9 @@ odm_IsLinked( IN PDM_ODM_T pDM_Odm ); */ -//END------------COMMON INFO RELATED---------------// +/* END------------COMMON INFO RELATED--------------- */ -//START---------------DIG---------------------------// +/* START---------------DIG--------------------------- */ void odm_FalseAlarmCounterStatistics( IN PDM_ODM_T pDM_Odm @@ -290,9 +286,9 @@ void odm_CCKPacketDetectionThresh( IN PDM_ODM_T pDM_Odm ); -//END---------------DIG---------------------------// +/* END---------------DIG--------------------------- */ -//START-------BB POWER SAVE-----------------------// +/* START-------BB POWER SAVE----------------------- */ void odm_DynamicBBPowerSavingInit( IN PDM_ODM_T pDM_Odm @@ -317,7 +313,7 @@ odm_Adaptivity( IN PDM_ODM_T pDM_Odm, IN u8 IGI ); -//END---------BB POWER SAVE-----------------------// +/* END---------BB POWER SAVE----------------------- */ void odm_RefreshRateAdaptiveMaskMP( @@ -529,13 +525,13 @@ odm_HwAntDiv( IN PDM_ODM_T pDM_Odm ); -//============================================================ -//3 Export Interface -//============================================================ +/* */ +/* 3 Export Interface */ +/* */ -// -// 2011/09/21 MH Add to describe different team necessary resource allocate?? -// +/* */ +/* 2011/09/21 MH Add to describe different team necessary resource allocate?? */ +/* */ void ODM_DMInit( IN PDM_ODM_T pDM_Odm @@ -547,7 +543,7 @@ ODM_DMInit( return; #endif - //2012.05.03 Luke: For all IC series + /* 2012.05.03 Luke: For all IC series */ odm_CommonInfoSelfInit(pDM_Odm); odm_CmnInfoInit_Debug(pDM_Odm); odm_DIGInit(pDM_Odm); @@ -560,7 +556,7 @@ ODM_DMInit( } else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - odm_PrimaryCCA_Init(pDM_Odm); // Gary + odm_PrimaryCCA_Init(pDM_Odm); /* Gary */ odm_DynamicBBPowerSavingInit(pDM_Odm); odm_DynamicTxPowerInit(pDM_Odm); odm_TXPowerTrackingInit(pDM_Odm); @@ -579,17 +575,17 @@ ODM_DMInit( } } -// -// 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. -// You can not add any dummy function here, be care, you can only use DM structure -// to perform any new ODM_DM. -// +/* */ +/* 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */ +/* You can not add any dummy function here, be care, you can only use DM structure */ +/* to perform any new ODM_DM. */ +/* */ void ODM_DMWatchdog( IN PDM_ODM_T pDM_Odm ) { - //2012.05.03 Luke: For all IC series + /* 2012.05.03 Luke: For all IC series */ odm_GlobalAdapterCheck(); odm_CmnInfoHook_Debug(pDM_Odm); odm_CmnInfoUpdate_Debug(pDM_Odm); @@ -597,11 +593,11 @@ ODM_DMWatchdog( odm_FalseAlarmCounterStatistics(pDM_Odm); odm_RSSIMonitorCheck(pDM_Odm); - //Fix Leave LPS issue - if( (adapter_to_pwrctl(pDM_Odm->Adapter)->pwr_mode != PS_MODE_ACTIVE) &&// in LPS mode + /* Fix Leave LPS issue */ + if( (adapter_to_pwrctl(pDM_Odm->Adapter)->pwr_mode != PS_MODE_ACTIVE) &&/* in LPS mode */ ( (pDM_Odm->SupportICType & (ODM_RTL8723A ) )|| - (pDM_Odm->SupportICType & (ODM_RTL8188E) )//&&((pDM_Odm->SupportInterface == ODM_ITRF_SDIO)) ) + (pDM_Odm->SupportICType & (ODM_RTL8188E) )/* pDM_Odm->SupportInterface == ODM_ITRF_SDIO)) ) */ ) ) @@ -652,9 +648,9 @@ ODM_DMWatchdog( } -// -// Init /.. Fixed HW value. Only init time. -// +/* */ +/* Init /.. Fixed HW value. Only init time. */ +/* */ void ODM_CmnInfoInit( IN PDM_ODM_T pDM_Odm, @@ -662,16 +658,16 @@ ODM_CmnInfoInit( IN u32 Value ) { - //ODM_RT_TRACE(pDM_Odm,); + /* ODM_RT_TRACE(pDM_Odm,); */ - // - // This section is used for init value - // + /* */ + /* This section is used for init value */ + /* */ switch (CmnInfo) { - // - // Fixed ODM value. - // + /* */ + /* Fixed ODM value. */ + /* */ case ODM_CMNINFO_ABILITY: pDM_Odm->SupportAbility = (u32)Value; break; @@ -736,9 +732,9 @@ ODM_CmnInfoInit( pDM_Odm->bDualMacSmartConcurrent = (BOOLEAN )Value; break; - //To remove the compiler warning, must add an empty default statement to handle the other values. + /* To remove the compiler warning, must add an empty default statement to handle the other values. */ default: - //do nothing + /* do nothing */ break; } @@ -754,14 +750,14 @@ ODM_CmnInfoHook( IN void * pValue ) { - // - // Hook call by reference pointer. - // + /* */ + /* Hook call by reference pointer. */ + /* */ switch (CmnInfo) { - // - // Dynamic call by reference pointer. - // + /* */ + /* Dynamic call by reference pointer. */ + /* */ case ODM_CMNINFO_MAC_PHY_MODE: pDM_Odm->pMacPhyMode = (u8 *)pValue; break; @@ -845,23 +841,23 @@ ODM_CmnInfoHook( pDM_Odm->mp_mode = (u8 *)pValue; break; - //case ODM_CMNINFO_BT_COEXIST: - // pDM_Odm->BTCoexist = (BOOLEAN *)pValue; + /* case ODM_CMNINFO_BT_COEXIST: */ + /* pDM_Odm->BTCoexist = (BOOLEAN *)pValue; */ - //case ODM_CMNINFO_STA_STATUS: - //pDM_Odm->pODM_StaInfo[] = (PSTA_INFO_T)pValue; - //break; + /* case ODM_CMNINFO_STA_STATUS: */ + /* pDM_Odm->pODM_StaInfo[] = (PSTA_INFO_T)pValue; */ + /* break; */ - //case ODM_CMNINFO_PHY_STATUS: - // pDM_Odm->pPhyInfo = (ODM_PHY_INFO *)pValue; - // break; + /* case ODM_CMNINFO_PHY_STATUS: */ + /* pDM_Odm->pPhyInfo = (ODM_PHY_INFO *)pValue; */ + /* break; */ - //case ODM_CMNINFO_MAC_STATUS: - // pDM_Odm->pMacInfo = (ODM_MAC_INFO *)pValue; - // break; - //To remove the compiler warning, must add an empty default statement to handle the other values. + /* case ODM_CMNINFO_MAC_STATUS: */ + /* pDM_Odm->pMacInfo = (ODM_MAC_INFO *)pValue; */ + /* break; */ + /* To remove the compiler warning, must add an empty default statement to handle the other values. */ default: - //do nothing + /* do nothing */ break; } @@ -877,29 +873,29 @@ ODM_CmnInfoPtrArrayHook( IN void * pValue ) { - // - // Hook call by reference pointer. - // + /* */ + /* Hook call by reference pointer. */ + /* */ switch (CmnInfo) { - // - // Dynamic call by reference pointer. - // + /* */ + /* Dynamic call by reference pointer. */ + /* */ case ODM_CMNINFO_STA_STATUS: pDM_Odm->pODM_StaInfo[Index] = (PSTA_INFO_T)pValue; break; - //To remove the compiler warning, must add an empty default statement to handle the other values. + /* To remove the compiler warning, must add an empty default statement to handle the other values. */ default: - //do nothing + /* do nothing */ break; } } -// -// Update Band/CHannel/.. The values are dynamic but non-per-packet. -// +/* */ +/* Update Band/CHannel/.. The values are dynamic but non-per-packet. */ +/* */ void ODM_CmnInfoUpdate( IN PDM_ODM_T pDM_Odm, @@ -907,9 +903,9 @@ ODM_CmnInfoUpdate( IN u64 Value ) { - // - // This init variable may be changed in run time. - // + /* */ + /* This init variable may be changed in run time. */ + /* */ switch (CmnInfo) { case ODM_CMNINFO_ABILITY: @@ -953,7 +949,7 @@ ODM_CmnInfoUpdate( pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value; break; #if(BT_30_SUPPORT == 1) - // The following is for BT HS mode and BT coexist mechanism. + /* The following is for BT HS mode and BT coexist mechanism. */ case ODM_CMNINFO_BT_DISABLED: pDM_Odm->bBtDisabled = (BOOLEAN)Value; break; @@ -1086,9 +1082,9 @@ odm_CmnInfoUpdate_Debug( ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min=%d\n",pDM_Odm->RSSI_Min) ); } -//3============================================================ -//3 DIG -//3============================================================ +/* 3============================================================ */ +/* 3 DIG */ +/* 3============================================================ */ /*----------------------------------------------------------------------------- * Function: odm_DIGInit() * @@ -1175,7 +1171,7 @@ ODM_Write_DIG( ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_REG(IGI_A,pDM_Odm)=0x%x, ODM_BIT(IGI,pDM_Odm)=0x%x \n", ODM_REG(IGI_A,pDM_Odm),ODM_BIT(IGI,pDM_Odm))); - if(pDM_DigTable->CurIGValue != CurrentIGI)//if(pDM_DigTable->PreIGValue != CurrentIGI) + if(pDM_DigTable->CurIGValue != CurrentIGI)/* if(pDM_DigTable->PreIGValue != CurrentIGI) */ { if(pDM_Odm->SupportPlatform & (ODM_CE|ODM_MP)) { @@ -1205,14 +1201,14 @@ ODM_Write_DIG( } } ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x). \n",CurrentIGI)); - //pDM_DigTable->PreIGValue = pDM_DigTable->CurIGValue; + /* pDM_DigTable->PreIGValue = pDM_DigTable->CurIGValue; */ pDM_DigTable->CurIGValue = CurrentIGI; } ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG():CurrentIGI=0x%x \n",CurrentIGI)); } -//Need LPS mode for CE platform --2012--08--24--- -//8723AS/8189ES +/* Need LPS mode for CE platform --2012--08--24--- */ +/* 8723AS/8189ES */ void odm_DIGbyRSSI_LPS( @@ -1222,7 +1218,7 @@ odm_DIGbyRSSI_LPS( struct adapter * pAdapter =pDM_Odm->Adapter; pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; PFALSE_ALARM_STATISTICS pFalseAlmCnt = &pDM_Odm->FalseAlmCnt; - u8 RSSI_Lower=DM_DIG_MIN_NIC; //0x1E or 0x1C + u8 RSSI_Lower=DM_DIG_MIN_NIC; /* 0x1E or 0x1C */ u8 bFwCurrentInPSMode = FALSE; u8 CurrentIGI=pDM_Odm->RSSI_Min; @@ -1236,11 +1232,11 @@ odm_DIGbyRSSI_LPS( ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("==>pDM_Odm->RSSI_Min=%d ()\n",pDM_Odm->RSSI_Min)); - // Using FW PS mode to make IGI + /* Using FW PS mode to make IGI */ if(bFwCurrentInPSMode) { ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("---Neil---odm_DIG is in LPS mode\n")); - //Adjust by FA in LPS MODE + /* Adjust by FA in LPS MODE */ if(pFalseAlmCnt->Cnt_all> DM_DIG_FA_TH2_LPS) CurrentIGI = CurrentIGI+2; else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS) @@ -1253,21 +1249,21 @@ odm_DIGbyRSSI_LPS( CurrentIGI = RSSI_Lower; } - //Lower bound checking + /* Lower bound checking */ - //RSSI Lower bound check + /* RSSI Lower bound check */ if((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC) RSSI_Lower =(pDM_Odm->RSSI_Min-10); else RSSI_Lower =DM_DIG_MIN_NIC; - //Upper and Lower Bound checking + /* Upper and Lower Bound checking */ if(CurrentIGI > DM_DIG_MAX_NIC) CurrentIGI=DM_DIG_MAX_NIC; else if(CurrentIGI < RSSI_Lower) CurrentIGI =RSSI_Lower; - ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); + ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */ } @@ -1278,15 +1274,15 @@ IN PDM_ODM_T pDM_Odm { if(pDM_Odm->SupportICType == ODM_RTL8723B) { - pDM_Odm->TH_L2H_ini = 0xf8; // -8 + pDM_Odm->TH_L2H_ini = 0xf8; /* -8 */ } if((pDM_Odm->SupportICType == ODM_RTL8192E)&&(pDM_Odm->SupportInterface == ODM_ITRF_PCIE)) { - pDM_Odm->TH_L2H_ini = 0xf0; // -16 + pDM_Odm->TH_L2H_ini = 0xf0; /* -16 */ } else { - pDM_Odm->TH_L2H_ini = 0xf9; // -7 + pDM_Odm->TH_L2H_ini = 0xf9; /* -7 */ } pDM_Odm->TH_EDCCA_HL_diff = 7; @@ -1294,10 +1290,6 @@ IN PDM_ODM_T pDM_Odm pDM_Odm->IGI_target = 0x1c; pDM_Odm->ForceEDCCA = 0; pDM_Odm->AdapEn_RSSI = 20; - - //Reg524[11]=0 is easily to transmit packets during adaptivity test - - //ODM_SetBBReg(pDM_Odm, 0x524, BIT11, 1);// stop counting if EDCCA is asserted } @@ -1322,9 +1314,9 @@ odm_Adaptivity( pDM_Odm->ForceEDCCA, pDM_Odm->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff, pDM_Odm->AdapEn_RSSI)); if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) - ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); //ADC_mask enable + ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); /* ADC_mask enable */ - if((!pDM_Odm->bLinked)||(*pDM_Odm->pChannel > 149)) // Band4 doesn't need adaptivity + if((!pDM_Odm->bLinked)||(*pDM_Odm->pChannel > 149)) /* Band4 doesn't need adaptivity */ { if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { @@ -1345,7 +1337,7 @@ odm_Adaptivity( EDCCA_State = 1; { - if(*pDM_Odm->pBandWidth == ODM_BW20M) //CHANNEL_WIDTH_20 + if(*pDM_Odm->pBandWidth == ODM_BW20M) /* CHANNEL_WIDTH_20 */ IGI_target = pDM_Odm->IGI_Base; else if(*pDM_Odm->pBandWidth == ODM_BW40M) IGI_target = pDM_Odm->IGI_Base + 2; @@ -1392,12 +1384,12 @@ odm_DIGInit( { pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - //pDM_DigTable->Dig_Enable_Flag = TRUE; - //pDM_DigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_MAX; + /* pDM_DigTable->Dig_Enable_Flag = TRUE; */ + /* pDM_DigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_MAX; */ pDM_DigTable->CurIGValue = (u8) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm)); - //pDM_DigTable->PreIGValue = 0x0; - //pDM_DigTable->CurSTAConnectState = pDM_DigTable->PreSTAConnectState = DIG_STA_DISCONNECT; - //pDM_DigTable->CurMultiSTAConnectState = DIG_MultiSTA_DISCONNECT; + /* pDM_DigTable->PreIGValue = 0x0; */ + /* pDM_DigTable->CurSTAConnectState = pDM_DigTable->PreSTAConnectState = DIG_STA_DISCONNECT; */ + /* pDM_DigTable->CurMultiSTAConnectState = DIG_MultiSTA_DISCONNECT; */ pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW; pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH; pDM_DigTable->FALowThresh = DMfalseALARM_THRESH_LOW; @@ -1425,10 +1417,10 @@ odm_DIGInit( pDM_DigTable->bMediaConnect_0 = FALSE; pDM_DigTable->bMediaConnect_1 = FALSE; - //To Initialize pDM_Odm->bDMInitialGainEnable == FALSE to avoid DIG error + /* To Initialize pDM_Odm->bDMInitialGainEnable == FALSE to avoid DIG error */ pDM_Odm->bDMInitialGainEnable = TRUE; - //To Initi BT30 IGI + /* To Initi BT30 IGI */ pDM_DigTable->BT30_CurIGI=0x32; } @@ -1465,7 +1457,7 @@ odm_DIG( #endif ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n")); - //if(!(pDM_Odm->SupportAbility & (ODM_BB_DIG|ODM_BB_FA_CNT))) + /* if(!(pDM_Odm->SupportAbility & (ODM_BB_DIG|ODM_BB_FA_CNT))) */ if((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) ||(!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) { ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n")); @@ -1478,7 +1470,7 @@ odm_DIG( return; } - //add by Neil Chen to avoid PSD is processing + /* add by Neil Chen to avoid PSD is processing */ if(pDM_Odm->SupportICType==ODM_RTL8723A) { if(pDM_Odm->bDMInitialGainEnable == FALSE) @@ -1528,7 +1520,7 @@ odm_DIG( FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE); } - //1 Boundary Decision + /* 1 Boundary Decision */ if(pDM_Odm->SupportICType & (ODM_RTL8192C) &&(pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA))) { if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) @@ -1573,7 +1565,7 @@ odm_DIG( { if(pDM_Odm->SupportICType&(ODM_RTL8723A/*|ODM_RTL8821*/)) { - //2 Upper Bound + /* 2 Upper Bound */ if(( pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC ) pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; else if(( pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC ) @@ -1581,7 +1573,7 @@ odm_DIG( else pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10; - //BT is Concurrent + /* BT is Concurrent */ if(pDM_Odm->bBtLimitedDig) { @@ -1611,7 +1603,7 @@ odm_DIG( else { if((pDM_Odm->SupportICType & (ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8812|ODM_RTL8821)) && (pDM_Odm->bBtLimitedDig==1)){ - //2 Modify DIG upper bound for 92E, 8723B, 8821 & 8812 BT + /* 2 Modify DIG upper bound for 92E, 8723B, 8821 & 8812 BT */ if((pDM_Odm->RSSI_Min + 10) > dm_dig_max ) pDM_DigTable->rx_gain_range_max = dm_dig_max; else if((pDM_Odm->RSSI_Min + 10) < dm_dig_min ) @@ -1621,8 +1613,8 @@ odm_DIG( } else{ - //2 Modify DIG upper bound - //2013.03.19 Luke: Modified upper bound for Netgear rental house test + /* 2 Modify DIG upper bound */ + /* 2013.03.19 Luke: Modified upper bound for Netgear rental house test */ if(pDM_Odm->SupportICType != ODM_RTL8821) offset = 20; else @@ -1637,7 +1629,7 @@ odm_DIG( } - //2 Modify DIG lower bound + /* 2 Modify DIG lower bound */ /* if((pFalseAlmCnt->Cnt_all > 500)&&(DIG_Dynamic_MIN < 0x25)) DIG_Dynamic_MIN++; @@ -1646,7 +1638,7 @@ odm_DIG( */ - //1 Lower Bound for 88E AntDiv + /* 1 Lower Bound for 88E AntDiv */ if((pDM_Odm->SupportICType == ODM_RTL8188E)&&(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { if((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ||(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)) @@ -1683,16 +1675,16 @@ odm_DIG( ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : No Link\n")); } - //1 Modify DIG lower bound, deal with abnorally large false alarm + /* 1 Modify DIG lower bound, deal with abnorally large false alarm */ if(pFalseAlmCnt->Cnt_all > 10000) { ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("dm_DIG(): Abnornally false alarm case. \n")); if(pDM_DigTable->LargeFAHit != 3) pDM_DigTable->LargeFAHit++; - if(pDM_DigTable->ForbiddenIGI < CurrentIGI)//if(pDM_DigTable->ForbiddenIGI < pDM_DigTable->CurIGValue) + if(pDM_DigTable->ForbiddenIGI < CurrentIGI)/* if(pDM_DigTable->ForbiddenIGI < pDM_DigTable->CurIGValue) */ { - pDM_DigTable->ForbiddenIGI = (u8)CurrentIGI;//pDM_DigTable->ForbiddenIGI = pDM_DigTable->CurIGValue; + pDM_DigTable->ForbiddenIGI = (u8)CurrentIGI;/* pDM_DigTable->ForbiddenIGI = pDM_DigTable->CurIGValue; */ pDM_DigTable->LargeFAHit = 1; } @@ -1702,23 +1694,23 @@ odm_DIG( pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max; else pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); - pDM_DigTable->Recover_cnt = 3600; //3600=2hr + pDM_DigTable->Recover_cnt = 3600; /* 3600=2hr */ } } else { - //Recovery mechanism for IGI lower bound + /* Recovery mechanism for IGI lower bound */ if(pDM_DigTable->Recover_cnt != 0) pDM_DigTable->Recover_cnt --; else { if(pDM_DigTable->LargeFAHit < 3) { - if((pDM_DigTable->ForbiddenIGI -1) < DIG_Dynamic_MIN) //DM_DIG_MIN) + if((pDM_DigTable->ForbiddenIGI -1) < DIG_Dynamic_MIN) /* DM_DIG_MIN) */ { - pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; //DM_DIG_MIN; - pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; //DM_DIG_MIN; + pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ + pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n")); } else @@ -1742,7 +1734,7 @@ odm_DIG( if(pDM_DigTable->rx_gain_range_min > pDM_DigTable->rx_gain_range_max) pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max; - //1 Adjust initial gain by false alarm + /* 1 Adjust initial gain by false alarm */ if(pDM_Odm->bLinked) { ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG AfterLink\n")); @@ -1754,25 +1746,25 @@ odm_DIG( CurrentIGI = DIG_MaxOfMin; ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n")); - //ODM_ConfigBBWithHeaderFile(pDM_Odm, CONFIG_BB_AGC_TAB_DIFF); + /* ODM_ConfigBBWithHeaderFile(pDM_Odm, CONFIG_BB_AGC_TAB_DIFF); */ } else { if(pDM_Odm->SupportICType == ODM_RTL8192D) { if(pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_92D) - CurrentIGI = CurrentIGI + 4;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; + CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_92D) - CurrentIGI = CurrentIGI + 2; //pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; + CurrentIGI = CurrentIGI + 2; /* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_92D) - CurrentIGI = CurrentIGI - 2;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; + CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ } else { - //FA for Combo IC--NeilChen--2012--09--28 + /* FA for Combo IC--NeilChen--2012--09--28 */ if(pDM_Odm->SupportICType == ODM_RTL8723A) { - //WLAN and BT ConCurrent + /* WLAN and BT ConCurrent */ if(pDM_Odm->bBtLimitedDig) { if(pFalseAlmCnt->Cnt_all > 0x300) @@ -1782,24 +1774,24 @@ odm_DIG( else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) CurrentIGI = CurrentIGI -2; } - else //Not Concurrent + else /* Not Concurrent */ { if(pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2) - CurrentIGI = CurrentIGI + 4;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; + CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1) - CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; + CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) - CurrentIGI = CurrentIGI - 2;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; + CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ } } else { if(pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2) - CurrentIGI = CurrentIGI + 4;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; + CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1) - CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; + CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) - CurrentIGI = CurrentIGI - 2;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; + CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ if((pDM_Odm->SupportPlatform&(ODM_MP|ODM_CE))&&(pDM_Odm->PhyDbgInfo.NumQryBeaconPkt < 10) &&(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH1) && (pDM_Odm->bsta_state)) @@ -1810,10 +1802,7 @@ odm_DIG( } } } - } - else - { - //CurrentIGI = pDM_DigTable->rx_gain_range_min;//pDM_DigTable->CurIGValue = pDM_DigTable->rx_gain_range_min + } else { ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n")); if(FirstDisConnect) { @@ -1822,7 +1811,7 @@ odm_DIG( } else { - //2012.03.30 LukeLee: enable DIG before link but with very high thresholds + /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */ if(pFalseAlmCnt->Cnt_all > 10000) CurrentIGI = CurrentIGI + 4; else if (pFalseAlmCnt->Cnt_all > 8000) @@ -1833,7 +1822,7 @@ odm_DIG( } } ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG End Adjust IGI\n")); - //1 Check initial gain by upper/lower bound + /* 1 Check initial gain by upper/lower bound */ if(CurrentIGI > pDM_DigTable->rx_gain_range_max) CurrentIGI = pDM_DigTable->rx_gain_range_max; @@ -1854,7 +1843,7 @@ odm_DIG( ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TotalFA=%d\n", pFalseAlmCnt->Cnt_all)); ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x\n", CurrentIGI)); - //2 High power RSSI threshold + /* 2 High power RSSI threshold */ { #if(BT_30_SUPPORT == 1) @@ -1886,14 +1875,14 @@ odm_DIG( } else { - ODM_Write_DIG(pDM_Odm, pDM_DigTable->BT30_CurIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); + ODM_Write_DIG(pDM_Odm, pDM_DigTable->BT30_CurIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */ } } } - else // BT is not using + else /* BT is not using */ #endif { - ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); + ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */ pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; } @@ -1946,7 +1935,7 @@ odm_DIGInit( pDM_DigTable->bMediaConnect_0 = FALSE; pDM_DigTable->bMediaConnect_1 = FALSE; - //To Initialize pDM_Odm->bDMInitialGainEnable == FALSE to avoid DIG error + /* To Initialize pDM_Odm->bDMInitialGainEnable == FALSE to avoid DIG error */ pDM_Odm->bDMInitialGainEnable = TRUE; } @@ -1988,7 +1977,7 @@ odm_DIG( return; } - //add by Neil Chen to avoid PSD is processing + /* add by Neil Chen to avoid PSD is processing */ if(pDM_Odm->bDMInitialGainEnable == FALSE) { ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: PSD is Processing \n")); @@ -2035,7 +2024,7 @@ odm_DIG( FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE); } - //1 Boundary Decision + /* 1 Boundary Decision */ if((pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8723A)) && ((if(pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA))) || pDM_Odm->ExtLNA)) { @@ -2071,10 +2060,10 @@ odm_DIG( if(pDM_Odm->bLinked) { - //2 8723A Series, offset need to be 10 //neil + /* 2 8723A Series, offset need to be 10 */ if(pDM_Odm->SupportICType==(ODM_RTL8723A)) { - //2 Upper Bound + /* 2 Upper Bound */ if(( pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC ) pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; else if(( pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC ) @@ -2082,7 +2071,7 @@ odm_DIG( else pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10; - //2 If BT is Concurrent, need to set Lower Bound + /* 2 If BT is Concurrent, need to set Lower Bound */ #if(BT_30_SUPPORT == 1) if(pDM_Odm->bBtBusy) @@ -2107,7 +2096,7 @@ odm_DIG( } else { - //2 Modify DIG upper bound + /* 2 Modify DIG upper bound */ if((pDM_Odm->RSSI_Min + 20) > dm_dig_max ) pDM_DigTable->rx_gain_range_max = dm_dig_max; else if((pDM_Odm->RSSI_Min + 20) < dm_dig_min ) @@ -2116,7 +2105,7 @@ odm_DIG( pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20; - //2 Modify DIG lower bound + /* 2 Modify DIG lower bound */ /* if((pFalseAlmCnt->Cnt_all > 500)&&(DIG_Dynamic_MIN < 0x25)) DIG_Dynamic_MIN++; @@ -2134,7 +2123,7 @@ odm_DIG( ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : bOneEntryOnly=TRUE, DIG_Dynamic_MIN=0x%x\n",DIG_Dynamic_MIN)); ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : pDM_Odm->RSSI_Min=%d\n",pDM_Odm->RSSI_Min)); } - //1 Lower Bound for 88E AntDiv + /* 1 Lower Bound for 88E AntDiv */ else if((pDM_Odm->SupportICType == ODM_RTL8188E)&&(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) @@ -2156,16 +2145,16 @@ odm_DIG( ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : No Link\n")); } - //1 Modify DIG lower bound, deal with abnormally large false alarm + /* 1 Modify DIG lower bound, deal with abnormally large false alarm */ if(pFalseAlmCnt->Cnt_all > 10000) { ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("dm_DIG(): Abnornally false alarm case. \n")); if(pDM_DigTable->LargeFAHit != 3) pDM_DigTable->LargeFAHit++; - if(pDM_DigTable->ForbiddenIGI < CurrentIGI)//if(pDM_DigTable->ForbiddenIGI < pDM_DigTable->CurIGValue) + if(pDM_DigTable->ForbiddenIGI < CurrentIGI)/* if(pDM_DigTable->ForbiddenIGI < pDM_DigTable->CurIGValue) */ { - pDM_DigTable->ForbiddenIGI = CurrentIGI;//pDM_DigTable->ForbiddenIGI = pDM_DigTable->CurIGValue; + pDM_DigTable->ForbiddenIGI = CurrentIGI;/* pDM_DigTable->ForbiddenIGI = pDM_DigTable->CurIGValue; */ pDM_DigTable->LargeFAHit = 1; } @@ -2175,23 +2164,23 @@ odm_DIG( pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max; else pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); - pDM_DigTable->Recover_cnt = 3600; //3600=2hr + pDM_DigTable->Recover_cnt = 3600; /* 3600=2hr */ } } else { - //Recovery mechanism for IGI lower bound + /* Recovery mechanism for IGI lower bound */ if(pDM_DigTable->Recover_cnt != 0) pDM_DigTable->Recover_cnt --; else { if(pDM_DigTable->LargeFAHit < 3) { - if((pDM_DigTable->ForbiddenIGI -1) < DIG_Dynamic_MIN) //DM_DIG_MIN) + if((pDM_DigTable->ForbiddenIGI -1) < DIG_Dynamic_MIN) /* DM_DIG_MIN) */ { - pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; //DM_DIG_MIN; - pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; //DM_DIG_MIN; + pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ + pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n")); } else @@ -2209,7 +2198,7 @@ odm_DIG( } ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): pDM_DigTable->LargeFAHit=%d\n",pDM_DigTable->LargeFAHit)); - //1 Adjust initial gain by false alarm + /* 1 Adjust initial gain by false alarm */ if(pDM_Odm->bLinked) { ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG AfterLink\n")); @@ -2223,11 +2212,11 @@ odm_DIG( if(pDM_Odm->SupportICType == ODM_RTL8192D) { if(pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_92D) - CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; + CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_92D) - CurrentIGI = CurrentIGI + 1; //pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; + CurrentIGI = CurrentIGI + 1; /* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_92D) - CurrentIGI = CurrentIGI - 1;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; + CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ } else { @@ -2245,11 +2234,11 @@ odm_DIG( #endif { if(pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2) - CurrentIGI = CurrentIGI + 4;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; + CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1) - CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; + CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) - CurrentIGI = CurrentIGI - 2;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; + CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ } @@ -2258,7 +2247,6 @@ odm_DIG( } else { - //CurrentIGI = pDM_DigTable->rx_gain_range_min;//pDM_DigTable->CurIGValue = pDM_DigTable->rx_gain_range_min ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n")); if(FirstDisConnect) { @@ -2267,18 +2255,18 @@ odm_DIG( } else { - //2012.03.30 LukeLee: enable DIG before link but with very high thresholds + /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */ if(pFalseAlmCnt->Cnt_all > 10000) - CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; + CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ else if (pFalseAlmCnt->Cnt_all > 8000) - CurrentIGI = CurrentIGI + 1;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; + CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ else if(pFalseAlmCnt->Cnt_all < 500) - CurrentIGI = CurrentIGI - 1;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; + CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): England DIG \n")); } } ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG End Adjust IGI\n")); - //1 Check initial gain by upper/lower bound + /* 1 Check initial gain by upper/lower bound */ /* if(pDM_DigTable->CurIGValue > pDM_DigTable->rx_gain_range_max) pDM_DigTable->CurIGValue = pDM_DigTable->rx_gain_range_max; @@ -2295,18 +2283,18 @@ odm_DIG( ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TotalFA=%d\n", pFalseAlmCnt->Cnt_all)); ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x\n", CurrentIGI)); - //2 High power RSSI threshold + /* 2 High power RSSI threshold */ { - ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); + ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */ pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; } } #endif -//3============================================================ -//3 FASLE ALARM CHECK -//3============================================================ +/* 3============================================================ */ +/* 3 FASLE ALARM CHECK */ +/* 3============================================================ */ void odm_FalseAlarmCounterStatistics( @@ -2322,9 +2310,9 @@ odm_FalseAlarmCounterStatistics( if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { - //hold ofdm counter - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); //hold page C counter - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); //hold page D counter + /* hold ofdm counter */ + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */ + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */ ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord); FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff); @@ -2350,7 +2338,7 @@ odm_FalseAlarmCounterStatistics( } { - //hold cck counter + /* hold cck counter */ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT12, 1); ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT14, 1); @@ -2375,19 +2363,19 @@ odm_FalseAlarmCounterStatistics( if(pDM_Odm->SupportICType >=ODM_RTL8723A) { - //reset false alarm counter registers + /* reset false alarm counter registers */ ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 1); ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 0); ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 1); ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 0); - //update ofdm counter - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 0); //update page C counter - ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 0); //update page D counter + /* update ofdm counter */ + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 0); /* update page C counter */ + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 0); /* update page D counter */ - //reset CCK CCA counter + /* reset CCK CCA counter */ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 0); ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 2); - //reset CCK FA counter + /* reset CCK FA counter */ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 0); ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 2); } @@ -2400,17 +2388,17 @@ odm_FalseAlarmCounterStatistics( ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n", FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail)); } - else //FOR ODM_IC_11AC_SERIES + else /* FOR ODM_IC_11AC_SERIES */ { - //read OFDM FA counter + /* read OFDM FA counter */ FalseAlmCnt->Cnt_Ofdm_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_11AC, bMaskLWord); FalseAlmCnt->Cnt_Cck_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_11AC, bMaskLWord); FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail + FalseAlmCnt->Cnt_Cck_fail; - // reset OFDM FA coutner + /* reset OFDM FA coutner */ ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 1); ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 0); - // reset CCK FA counter + /* reset CCK FA counter */ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 0); ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 1); } @@ -2419,9 +2407,9 @@ odm_FalseAlarmCounterStatistics( ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n", FalseAlmCnt->Cnt_all)); } -//3============================================================ -//3 CCK Packet Detect Threshold -//3============================================================ +/* 3============================================================ */ +/* 3 CCK Packet Detect Threshold */ +/* 3============================================================ */ void odm_CCKPacketDetectionThresh( @@ -2472,7 +2460,7 @@ ODM_Write_CCK_CCA_Thres( { pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - if(pDM_DigTable->CurCCK_CCAThres!=CurCCK_CCAThres) //modify by Guo.Mingzhi 2012-01-03 + if(pDM_DigTable->CurCCK_CCAThres!=CurCCK_CCAThres) /* modify by Guo.Mingzhi 2012-01-03 */ { ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA,pDM_Odm), CurCCK_CCAThres); } @@ -2481,9 +2469,9 @@ ODM_Write_CCK_CCA_Thres( } -//3============================================================ -//3 BB Power Save -//3============================================================ +/* 3============================================================ */ +/* 3 BB Power Save */ +/* 3============================================================ */ void odm_DynamicBBPowerSavingInit( IN PDM_ODM_T pDM_Odm @@ -2512,15 +2500,15 @@ odm_DynamicBBPowerSaving( if(!(pDM_Odm->SupportPlatform & (ODM_MP|ODM_CE))) return; - //1 2.Power Saving for 92C + /* 1 2.Power Saving for 92C */ if((pDM_Odm->SupportICType == ODM_RTL8192C) &&(pDM_Odm->RFType == ODM_2T2R)) { odm_1R_CCA(pDM_Odm); } - // 20100628 Joseph: Turn off BB power save for 88CE because it makesthroughput unstable. - // 20100831 Joseph: Turn ON BB power save again after modifying AGC delay from 900ns ot 600ns. - //1 3.Power Saving for 88C + /* 20100628 Joseph: Turn off BB power save for 88CE because it makesthroughput unstable. */ + /* 20100831 Joseph: Turn ON BB power save again after modifying AGC delay from 900ns ot 600ns. */ + /* 1 3.Power Saving for 88C */ else { ODM_RF_Saving(pDM_Odm, FALSE); @@ -2551,34 +2539,22 @@ odm_1R_CCA( else pDM_PSTable->CurCCAState = CCA_1R; } - } - else{ + } else{ pDM_PSTable->CurCCAState=CCA_MAX; } - if(pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState) - { - if(pDM_PSTable->CurCCAState == CCA_1R) - { + if(pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState) { + if(pDM_PSTable->CurCCAState == CCA_1R) { if( pDM_Odm->RFType ==ODM_2T2R ) - { ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x13); - //PHY_SetBBReg(pAdapter, 0xe70, bMaskByte3, 0x20); - } else - { ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x23); - //PHY_SetBBReg(pAdapter, 0xe70, 0x7fc00000, 0x10c); // Set RegE70[30:22] = 9b'100001100 - } - } - else - { + } else { ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x33); - //PHY_SetBBReg(pAdapter,0xe70, bMaskByte3, 0x63); + /* PHY_SetBBReg(pAdapter,0xe70, bMaskByte3, 0x63); */ } pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState; } - //ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, ("CCAStage = %s\n",(pDM_PSTable->CurCCAState==0)?"1RCCA":"2RCCA")); } void @@ -2590,7 +2566,7 @@ ODM_RF_Saving( pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable; u8 Rssi_Up_bound = 30 ; u8 Rssi_Low_bound = 25; - if(pDM_Odm->PatchID == 40 ) //RT_CID_819x_FUNAI_TV + if(pDM_Odm->PatchID == 40 ) /* RT_CID_819x_FUNAI_TV */ { Rssi_Up_bound = 50 ; Rssi_Low_bound = 45; @@ -2601,7 +2577,7 @@ ODM_RF_Saving( pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3; pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24; pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12; - //Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord); + /* Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord); */ pDM_PSTable->initialize = 1; } @@ -2635,20 +2611,20 @@ ODM_RF_Saving( { if(pDM_PSTable->CurRFState == RF_Save) { - // 8723 RSSI report will be wrong. Set 0x874[5]=1 when enter BB power saving mode. - // Suggested by SD3 Yu-Nan. 2011.01.20. + /* 8723 RSSI report will be wrong. Set 0x874[5]=1 when enter BB power saving mode. */ + /* Suggested by SD3 Yu-Nan. 2011.01.20. */ if(pDM_Odm->SupportICType == ODM_RTL8723A) { - ODM_SetBBReg(pDM_Odm, 0x874 , BIT5, 0x1); //Reg874[5]=1b'1 + ODM_SetBBReg(pDM_Odm, 0x874 , BIT5, 0x1); /* Reg874[5]=1b'1 */ } - ODM_SetBBReg(pDM_Odm, 0x874 , 0x1C0000, 0x2); //Reg874[20:18]=3'b010 - ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, 0); //RegC70[3]=1'b0 - ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); //Reg85C[31:24]=0x63 - ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); //Reg874[15:14]=2'b10 - ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); //RegA75[7:4]=0x3 - ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); //Reg818[28]=1'b0 - ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); //Reg818[28]=1'b1 - //ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, (" RF_Save")); + ODM_SetBBReg(pDM_Odm, 0x874 , 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */ + ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, 0); /* RegC70[3]=1'b0 */ + ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */ + ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */ + ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */ + ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); /* Reg818[28]=1'b0 */ + ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); /* Reg818[28]=1'b1 */ + /* ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, (" RF_Save")); */ } else { @@ -2660,21 +2636,21 @@ ODM_RF_Saving( if(pDM_Odm->SupportICType == ODM_RTL8723A) { - ODM_SetBBReg(pDM_Odm,0x874 , BIT5, 0x0); //Reg874[5]=1b'0 + ODM_SetBBReg(pDM_Odm,0x874 , BIT5, 0x0); /* Reg874[5]=1b'0 */ } - //ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, (" RF_Normal")); + /* ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, (" RF_Normal")); */ } pDM_PSTable->PreRFState =pDM_PSTable->CurRFState; } } -//3============================================================ -//3 RATR MASK -//3============================================================ -//3============================================================ -//3 Rate Adaptive -//3============================================================ +/* 3============================================================ */ +/* 3 RATR MASK */ +/* 3============================================================ */ +/* 3============================================================ */ +/* 3 Rate Adaptive */ +/* 3============================================================ */ void odm_RateAdaptiveMaskInit( @@ -2702,7 +2678,7 @@ u32 ODM_Get_Rate_Bitmap( PSTA_INFO_T pEntry; u32 rate_bitmap = 0x0fffffff; u8 WirelessMode; - //u8 WirelessMode =*(pDM_Odm->pWirelessMode); + /* u8 WirelessMode =*(pDM_Odm->pWirelessMode); */ pEntry = pDM_Odm->pODM_StaInfo[macid]; @@ -2714,7 +2690,7 @@ u32 ODM_Get_Rate_Bitmap( switch(WirelessMode) { case ODM_WM_B: - if(ra_mask & 0x0000000c) //11M or 5.5M enable + if(ra_mask & 0x0000000c) /* 11M or 5.5M enable */ rate_bitmap = 0x0000000d; else rate_bitmap = 0x0000000f; @@ -2778,8 +2754,8 @@ u32 ODM_Get_Rate_Bitmap( } break; default: - //case WIRELESS_11_24N: - //case WIRELESS_11_5N: + /* case WIRELESS_11_24N: */ + /* case WIRELESS_11_5N: */ if(pDM_Odm->RFType == RF_1T2R) rate_bitmap = 0x000fffff; else @@ -2788,7 +2764,7 @@ u32 ODM_Get_Rate_Bitmap( } - //printk("%s ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n",__FUNCTION__,rssi_level,WirelessMode,rate_bitmap); + /* printk("%s ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n",__FUNCTION__,rssi_level,WirelessMode,rate_bitmap); */ ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n",rssi_level,WirelessMode,rate_bitmap)); return rate_bitmap; @@ -2818,11 +2794,11 @@ odm_RefreshRateAdaptiveMask( { if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK)) return; - // - // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate - // at the same time. In the stage2/3, we need to prive universal interface and merge all - // HW dynamic mechanism. - // + /* */ + /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ + /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ + /* HW dynamic mechanism. */ + /* */ switch (pDM_Odm->SupportPlatform) { case ODM_MP: @@ -2869,12 +2845,12 @@ odm_RefreshRateAdaptiveMaskCE( for(i=0; ipODM_StaInfo[i]; if(IS_STA_VALID(pstat) ) { - if(IS_MCAST( pstat->hwaddr)) //if(psta->mac_id ==1) + if(IS_MCAST( pstat->hwaddr)) /* if(psta->mac_id ==1) */ continue; if( TRUE == ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, FALSE , &pstat->rssi_level) ) { ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level)); - //printk("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level); + /* printk("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level); */ rtw_hal_update_ra_mask(pstat, pstat->rssi_level); } @@ -2889,8 +2865,8 @@ odm_RefreshRateAdaptiveMaskAPADSL( { } -// Return Value: BOOLEAN -// - TRUE: RATRState is changed. +/* Return Value: BOOLEAN */ +/* - TRUE: RATRState is changed. */ BOOLEAN ODM_RAStateCheck( IN PDM_ODM_T pDM_Odm, @@ -2905,9 +2881,9 @@ ODM_RAStateCheck( u8 LowRSSIThreshForRA = pRA->LowRSSIThresh; u8 RATRState; - // Threshold Adjustment: - // when RSSI state trends to go up one or two levels, make sure RSSI is high enough. - // Here GoUpGap is added to solve the boundary's level alternation issue. + /* Threshold Adjustment: */ + /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */ + /* Here GoUpGap is added to solve the boundary's level alternation issue. */ switch (*pRATRState) { case DM_RATR_STA_INIT: @@ -2928,14 +2904,14 @@ ODM_RAStateCheck( break; } - // Decide RATRState by RSSI. + /* Decide RATRState by RSSI. */ if(RSSI > HighRSSIThreshForRA) RATRState = DM_RATR_STA_HIGH; else if(RSSI > LowRSSIThreshForRA) RATRState = DM_RATR_STA_MIDDLE; else RATRState = DM_RATR_STA_LOW; - //printk("==>%s,RATRState:0x%02x ,RSSI:%d \n",__FUNCTION__,RATRState,RSSI); + /* printk("==>%s,RATRState:0x%02x ,RSSI:%d \n",__FUNCTION__,RATRState,RSSI); */ if( *pRATRState!=RATRState || bForceUpdate) { @@ -2948,11 +2924,11 @@ ODM_RAStateCheck( } -//============================================================ +/* */ -//3============================================================ -//3 Dynamic Tx Power -//3============================================================ +/* 3============================================================ */ +/* 3 Dynamic Tx Power */ +/* 3============================================================ */ void odm_DynamicTxPowerInit( @@ -3008,7 +2984,7 @@ odm_DynamicTxPowerWritePowerIndex( u32 Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; for(index = 0; index< 6; index++) - //PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], Value); + /* PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], Value); */ ODM_Write1Byte(pDM_Odm, Power_Index_REG[index], Value); } @@ -3019,26 +2995,26 @@ odm_DynamicTxPower( IN PDM_ODM_T pDM_Odm ) { - // - // For AP/ADSL use prtl8192cd_priv - // For CE/NIC use PADAPTER - // - //struct adapter * pAdapter = pDM_Odm->Adapter; -// prtl8192cd_priv priv = pDM_Odm->priv; + /* */ + /* For AP/ADSL use prtl8192cd_priv */ + /* For CE/NIC use PADAPTER */ + /* */ + /* struct adapter * pAdapter = pDM_Odm->Adapter; */ +/* prtl8192cd_priv priv = pDM_Odm->priv; */ if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) return; - // 2012/01/12 MH According to Luke's suggestion, only high power will support the feature. + /* 2012/01/12 MH According to Luke's suggestion, only high power will support the feature. */ if (pDM_Odm->ExtPA == FALSE) return; - // - // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate - // at the same time. In the stage2/3, we need to prive universal interface and merge all - // HW dynamic mechanism. - // + /* */ + /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ + /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ + /* HW dynamic mechanism. */ + /* */ switch (pDM_Odm->SupportPlatform) { case ODM_MP: @@ -3050,7 +3026,7 @@ odm_DynamicTxPower( break; case ODM_ADSL: - //odm_DIGAP(pDM_Odm); + /* odm_DIGAP(pDM_Odm); */ break; } @@ -3076,12 +3052,12 @@ odm_DynamicTxPowerNIC( } else if (pDM_Odm->SupportICType & ODM_RTL8188E) { - // Add Later. + /* Add Later. */ } else if (pDM_Odm->SupportICType == ODM_RTL8188E) { - // ??? - // This part need to be redefined. + /* ??? */ + /* This part need to be redefined. */ } } @@ -3108,9 +3084,9 @@ odm_DynamicTxPower_92D( } -//3============================================================ -//3 RSSI Monitor -//3============================================================ +/* 3============================================================ */ +/* 3 RSSI Monitor */ +/* 3============================================================ */ void odm_RSSIMonitorInit( @@ -3124,21 +3100,21 @@ odm_RSSIMonitorCheck( IN PDM_ODM_T pDM_Odm ) { - // - // For AP/ADSL use prtl8192cd_priv - // For CE/NIC use PADAPTER - // + /* */ + /* For AP/ADSL use prtl8192cd_priv */ + /* For CE/NIC use PADAPTER */ + /* */ struct adapter * pAdapter = pDM_Odm->Adapter; prtl8192cd_priv priv = pDM_Odm->priv; if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)) return; - // - // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate - // at the same time. In the stage2/3, we need to prive universal interface and merge all - // HW dynamic mechanism. - // + /* */ + /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ + /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ + /* HW dynamic mechanism. */ + /* */ switch (pDM_Odm->SupportPlatform) { case ODM_MP: @@ -3154,11 +3130,11 @@ odm_RSSIMonitorCheck( break; case ODM_ADSL: - //odm_DIGAP(pDM_Odm); + /* odm_DIGAP(pDM_Odm); */ break; } -} // odm_RSSIMonitorCheck +} /* odm_RSSIMonitorCheck */ void @@ -3168,9 +3144,9 @@ odm_RSSIMonitorCheckMP( { } -// -//sherry move from DUSC to here 20110517 -// +/* */ +/* sherry move from DUSC to here 20110517 */ +/* */ static void FindMinimumRSSI_Dmsp( IN struct adapter *pAdapter @@ -3187,7 +3163,7 @@ IN struct adapter *pAdapter struct dm_priv *pdmpriv = &pHalData->dmpriv; PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); - //1 1.Determine the minimum RSSI + /* 1 1.Determine the minimum RSSI */ if((pDM_Odm->bLinked != true) && (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0)) @@ -3207,7 +3183,7 @@ odm_RSSIMonitorCheckCE( int i; int tmpEntryMaxPWDB=0, tmpEntryMinPWDB=0xff; u8 sta_cnt=0; - u32 PWDB_rssi[NUM_STA]={0};//[0~15]:MACID, [16~31]:PWDB_rssi + u32 PWDB_rssi[NUM_STA]={0};/* 0~15]:MACID, [16~31]:PWDB_rssi */ if(pDM_Odm->bLinked != true) return; @@ -3217,7 +3193,7 @@ odm_RSSIMonitorCheckCE( for(i=0; ipODM_StaInfo[i])) { - if(IS_MCAST( psta->hwaddr)) //if(psta->mac_id ==1) + if(IS_MCAST( psta->hwaddr)) /* if(psta->mac_id ==1) */ continue; if(psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) @@ -3235,7 +3211,7 @@ odm_RSSIMonitorCheckCE( for(i=0; i< sta_cnt; i++) { if(PWDB_rssi[i] != (0)){ - if(pHalData->fw_ractrl == true)// Report every sta's RSSI to FW + if(pHalData->fw_ractrl == true)/* Report every sta's RSSI to FW */ { } else{ @@ -3248,7 +3224,7 @@ odm_RSSIMonitorCheckCE( } } - if(tmpEntryMaxPWDB != 0) // If associated entry is found + if(tmpEntryMaxPWDB != 0) /* If associated entry is found */ { pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; } @@ -3257,7 +3233,7 @@ odm_RSSIMonitorCheckCE( pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0; } - if(tmpEntryMinPWDB != 0xff) // If associated entry is found + if(tmpEntryMinPWDB != 0xff) /* If associated entry is found */ { pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; } @@ -3266,7 +3242,7 @@ odm_RSSIMonitorCheckCE( pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0; } - FindMinimumRSSI(Adapter);//get pdmpriv->MinUndecoratedPWDBForDM + FindMinimumRSSI(Adapter);/* get pdmpriv->MinUndecoratedPWDBForDM */ pDM_Odm->RSSI_Min = pdmpriv->MinUndecoratedPWDBForDM; } @@ -3306,9 +3282,9 @@ ODM_ReleaseAllTimers( ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer); } -//3============================================================ -//3 Tx Power Tracking -//3============================================================ +/* 3============================================================ */ +/* 3 Tx Power Tracking */ +/* 3============================================================ */ void odm_TXPowerTrackingInit( @@ -3328,10 +3304,8 @@ odm_TXPowerTrackingThermalMeterInit( pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true; pDM_Odm->RFCalibrateInfo.TXPowercount = 0; pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = false; - //#if (MP_DRIVER != 1) //for mp driver, turn off txpwrtracking as default if ( *(pDM_Odm->mp_mode) != 1) pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true; - //#endif//#if (MP_DRIVER != 1) MSG_8192C("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl); } pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = TRUE; @@ -3358,21 +3332,21 @@ ODM_TXPowerTrackingCheck( IN PDM_ODM_T pDM_Odm ) { - // - // For AP/ADSL use prtl8192cd_priv - // For CE/NIC use PADAPTER - // + /* */ + /* For AP/ADSL use prtl8192cd_priv */ + /* For CE/NIC use PADAPTER */ + /* */ struct adapter * pAdapter = pDM_Odm->Adapter; prtl8192cd_priv priv = pDM_Odm->priv; - //if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) - //return; + /* if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) */ + /* return; */ - // - // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate - // at the same time. In the stage2/3, we need to prive universal interface and merge all - // HW dynamic mechanism. - // + /* */ + /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ + /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ + /* HW dynamic mechanism. */ + /* */ switch (pDM_Odm->SupportPlatform) { case ODM_MP: @@ -3388,7 +3362,7 @@ ODM_TXPowerTrackingCheck( break; case ODM_ADSL: - //odm_DIGAP(pDM_Odm); + /* odm_DIGAP(pDM_Odm); */ break; } @@ -3406,7 +3380,7 @@ odm_TXPowerTrackingCheckCE( return; } - if(!pDM_Odm->RFCalibrateInfo.TM_Trigger) //at least delay 1 sec + if(!pDM_Odm->RFCalibrateInfo.TM_Trigger) /* at least delay 1 sec */ { PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; @@ -3433,17 +3407,17 @@ odm_TXPowerTrackingCheckAP( { } -//antenna mapping info -// 1: right-side antenna -// 2/0: left-side antenna -//PDM_SWAT_Table->CCK_Ant1_Cnt /OFDM_Ant1_Cnt: for right-side antenna: Ant:1 RxDefaultAnt1 -//PDM_SWAT_Table->CCK_Ant2_Cnt /OFDM_Ant2_Cnt: for left-side antenna: Ant:0 RxDefaultAnt2 -// We select left antenna as default antenna in initial process, modify it as needed -// +/* antenna mapping info */ +/* 1: right-side antenna */ +/* 2/0: left-side antenna */ +/* PDM_SWAT_Table->CCK_Ant1_Cnt /OFDM_Ant1_Cnt: for right-side antenna: Ant:1 RxDefaultAnt1 */ +/* PDM_SWAT_Table->CCK_Ant2_Cnt /OFDM_Ant2_Cnt: for left-side antenna: Ant:0 RxDefaultAnt2 */ +/* We select left antenna as default antenna in initial process, modify it as needed */ +/* */ -//3============================================================ -//3 SW Antenna Diversity -//3============================================================ +/* 3============================================================ */ +/* 3 SW Antenna Diversity */ +/* 3============================================================ */ #if(defined(CONFIG_SW_ANTENNA_DIVERSITY)) void odm_SwAntDivInit( @@ -3459,8 +3433,8 @@ odm_SwAntDivInit_NIC( ) { pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; -// Init SW ANT DIV mechanism for 8723AE/AU/AS// Neil Chen--2012--07--17--- -// CE/AP/ADSL no using SW ANT DIV for 8723A Series IC +/* Init SW ANT DIV mechanism for 8723AE/AU/AS*/ +/* CE/AP/ADSL no using SW ANT DIV for 8723A Series IC */ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS:Init SW Antenna Switch\n")); pDM_SWAT_Table->RSSI_sum_A = 0; pDM_SWAT_Table->RSSI_cnt_A = 0; @@ -3483,10 +3457,10 @@ odm_SwAntDivInit_NIC( pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ODM_Read4Byte(pDM_Odm, 0x860); } -// -// 20100514 Joseph: -// Add new function to reset the state of antenna diversity before link. -// +/* */ +/* 20100514 Joseph: */ +/* Add new function to reset the state of antenna diversity before link. */ +/* */ void ODM_SwAntDivResetBeforeLink( IN PDM_ODM_T pDM_Odm @@ -3499,10 +3473,10 @@ ODM_SwAntDivResetBeforeLink( } -// -// 20100514 Luke/Joseph: -// Add new function to reset antenna diversity state after link. -// +/* */ +/* 20100514 Luke/Joseph: */ +/* Add new function to reset antenna diversity state after link. */ +/* */ void ODM_SwAntDivRestAfterLink( IN PDM_ODM_T pDM_Odm @@ -3532,7 +3506,7 @@ ODM_SwAntDivChkPerPktRssi( if(StationID == pDM_SWAT_Table->RSSI_target) { - //1 RSSI for SW Antenna Switch + /* 1 RSSI for SW Antenna Switch */ if(pDM_SWAT_Table->CurAntenna == Antenna_A) { pDM_SWAT_Table->RSSI_sum_A += pPhyInfo->RxPWDBAll; @@ -3548,25 +3522,25 @@ ODM_SwAntDivChkPerPktRssi( } -// +/* */ void odm_SwAntDivChkAntSwitch( IN PDM_ODM_T pDM_Odm, IN u8 Step ) { - // - // For AP/ADSL use prtl8192cd_priv - // For CE/NIC use PADAPTER - // + /* */ + /* For AP/ADSL use prtl8192cd_priv */ + /* For CE/NIC use PADAPTER */ + /* */ struct adapter * pAdapter = pDM_Odm->Adapter; prtl8192cd_priv priv = pDM_Odm->priv; - // - // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate - // at the same time. In the stage2/3, we need to prive universal interface and merge all - // HW dynamic mechanism. - // + /* */ + /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ + /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ + /* HW dynamic mechanism. */ + /* */ switch (pDM_Odm->SupportPlatform) { case ODM_MP: case ODM_CE: @@ -3578,18 +3552,18 @@ odm_SwAntDivChkAntSwitch( } } -// -// 20100514 Luke/Joseph: -// Add new function for antenna diversity after link. -// This is the main function of antenna diversity after link. -// This function is called in HalDmWatchDog() and ODM_SwAntDivChkAntSwitchCallback(). -// HalDmWatchDog() calls this function with SWAW_STEP_PEAK to initialize the antenna test. -// In SWAW_STEP_PEAK, another antenna and a 500ms timer will be set for testing. -// After 500ms, ODM_SwAntDivChkAntSwitchCallback() calls this function to compare the signal just -// listened on the air with the RSSI of original antenna. -// It chooses the antenna with better RSSI. -// There is also a aged policy for error trying. Each error trying will cost more 5 seconds waiting -// penalty to get next try. +/* */ +/* 20100514 Luke/Joseph: */ +/* Add new function for antenna diversity after link. */ +/* This is the main function of antenna diversity after link. */ +/* This function is called in HalDmWatchDog() and ODM_SwAntDivChkAntSwitchCallback(). */ +/* HalDmWatchDog() calls this function with SWAW_STEP_PEAK to initialize the antenna test. */ +/* In SWAW_STEP_PEAK, another antenna and a 500ms timer will be set for testing. */ +/* After 500ms, ODM_SwAntDivChkAntSwitchCallback() calls this function to compare the signal just */ +/* listened on the air with the RSSI of original antenna. */ +/* It chooses the antenna with better RSSI. */ +/* There is also a aged policy for error trying. Each error trying will cost more 5 seconds waiting */ +/* penalty to get next try. */ void @@ -3599,10 +3573,10 @@ ODM_SetAntenna( { ODM_SetBBReg(pDM_Odm, 0x860, BIT8|BIT9, Antenna); } -//--------------------------------2012--09--06-- -//Note: Antenna_Main--> Antenna_A -// Antenna_Aux---> Antenna_B -//---------------------------------- +/* 2012--09--06-- */ +/* Note: Antenna_Main--> Antenna_A */ +/* Antenna_Aux---> Antenna_B */ +/* */ void odm_SwAntDivChkAntSwitchNIC( IN PDM_ODM_T pDM_Odm, @@ -3611,10 +3585,10 @@ odm_SwAntDivChkAntSwitchNIC( { } -// -// 20100514 Luke/Joseph: -// Callback function for 500ms antenna test trying. -// +/* */ +/* 20100514 Luke/Joseph: */ +/* Callback function for 500ms antenna test trying. */ +/* */ void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext) { PDM_ODM_T pDM_Odm= (PDM_ODM_T)FunctionContext; @@ -3624,7 +3598,7 @@ void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext) odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_DETERMINE); } -#else //#if(defined(CONFIG_SW_ANTENNA_DIVERSITY)) +#else /* if(defined(CONFIG_SW_ANTENNA_DIVERSITY)) */ void odm_SwAntDivInit( IN PDM_ODM_T pDM_Odm ) {} void ODM_SwAntDivChkPerPktRssi( @@ -3640,11 +3614,11 @@ static void ODM_SwAntDivResetBeforeLink( IN PDM_ODM_T pDM_Odm ){} void ODM_SwAntDivRestAfterLink( IN PDM_ODM_T pDM_Odm ){} void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext){} -#endif //#if(defined(CONFIG_SW_ANTENNA_DIVERSITY)) +#endif /* if(defined(CONFIG_SW_ANTENNA_DIVERSITY)) */ -//3============================================================ -//3 SW Antenna Diversity -//3============================================================ +/* 3============================================================ */ +/* 3 SW Antenna Diversity */ +/* 3============================================================ */ #if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) static void @@ -3653,52 +3627,52 @@ odm_InitHybridAntDiv_88C_92D( ) { SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - u8 bTxPathSel=0; //0:Path-A 1:Path-B + u8 bTxPathSel=0; /* 0:Path-A 1:Path-B */ u8 i; ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_InitHybridAntDiv==============>\n")); - //whether to do antenna diversity or not + /* whether to do antenna diversity or not */ if((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8192D)) return; bTxPathSel=(pDM_Odm->RFType==ODM_1T1R)?FALSE:TRUE; - ODM_SetBBReg(pDM_Odm,ODM_REG_BB_PWR_SAV1_11N, BIT23, 0); //No update ANTSEL during GNT_BT=1 - ODM_SetBBReg(pDM_Odm,ODM_REG_TX_ANT_CTRL_11N, BIT21, 1); //TX atenna selection from tx_info - ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PIN_11N, BIT23, 1); //enable LED[1:0] pin as ANTSEL - ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_CTRL_11N, BIT8|BIT9, 0x01); // 0x01: left antenna, 0x02: right antenna + ODM_SetBBReg(pDM_Odm,ODM_REG_BB_PWR_SAV1_11N, BIT23, 0); /* No update ANTSEL during GNT_BT=1 */ + ODM_SetBBReg(pDM_Odm,ODM_REG_TX_ANT_CTRL_11N, BIT21, 1); /* TX atenna selection from tx_info */ + ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PIN_11N, BIT23, 1); /* enable LED[1:0] pin as ANTSEL */ + ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_CTRL_11N, BIT8|BIT9, 0x01); /* 0x01: left antenna, 0x02: right antenna */ - // only AP support different path selection temperarly - if(!bTxPathSel){ //PATH-A - ODM_SetBBReg(pDM_Odm,ODM_REG_PIN_CTRL_11N, BIT8|BIT9, 0 ); // ANTSEL as HW control - ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PATH_11N, BIT13, 1); //select TX ANTESEL from path A + /* only AP support different path selection temperarly */ + if(!bTxPathSel){ /* PATH-A */ + ODM_SetBBReg(pDM_Odm,ODM_REG_PIN_CTRL_11N, BIT8|BIT9, 0 ); /* ANTSEL as HW control */ + ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PATH_11N, BIT13, 1); /* select TX ANTESEL from path A */ } else { - ODM_SetBBReg(pDM_Odm,ODM_REG_PIN_CTRL_11N, BIT24|BIT25, 0 ); // ANTSEL as HW control - ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PATH_11N, BIT13, 0); //select ANTESEL from path B + ODM_SetBBReg(pDM_Odm,ODM_REG_PIN_CTRL_11N, BIT24|BIT25, 0 ); /* ANTSEL as HW control */ + ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PATH_11N, BIT13, 0); /* select ANTESEL from path B */ } - //Set OFDM HW RX Antenna Diversity - ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA1_11N, 0x7FF, 0x0c0); //Pwdb threshold=8dB - ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA1_11N, BIT11, 0); //Switch to another antenna by checking pwdb threshold - ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA3_11N, BIT23, 1); // Decide final antenna by comparing 2 antennas' pwdb + /* Set OFDM HW RX Antenna Diversity */ + ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA1_11N, 0x7FF, 0x0c0); /* Pwdb threshold=8dB */ + ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA1_11N, BIT11, 0); /* Switch to another antenna by checking pwdb threshold */ + ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA3_11N, BIT23, 1); /* Decide final antenna by comparing 2 antennas' pwdb */ - //Set CCK HW RX Antenna Diversity - ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 0); //Antenna diversity decision period = 32 sample - ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA2_11N, 0xf, 0xf); //Threshold for antenna diversity. Check another antenna power if input power < ANT_lim*4 - ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA3_11N, BIT13, 1); //polarity ana_A=1 and ana_B=0 - ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA4_11N, 0x1f, 0x8); //default antenna power = inpwr*(0.5 + r_ant_step/16) + /* Set CCK HW RX Antenna Diversity */ + ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 0); /* Antenna diversity decision period = 32 sample */ + ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA2_11N, 0xf, 0xf); /* Threshold for antenna diversity. Check another antenna power if input power < ANT_lim*4 */ + ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA3_11N, BIT13, 1); /* polarity ana_A=1 and ana_B=0 */ + ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA4_11N, 0x1f, 0x8); /* default antenna power = inpwr*(0.5 + r_ant_step/16) */ - //Enable HW Antenna Diversity - if(!bTxPathSel) //PATH-A - ODM_SetBBReg(pDM_Odm,ODM_REG_IGI_A_11N, BIT7,1); // Enable Hardware antenna switch + /* Enable HW Antenna Diversity */ + if(!bTxPathSel) /* PATH-A */ + ODM_SetBBReg(pDM_Odm,ODM_REG_IGI_A_11N, BIT7,1); /* Enable Hardware antenna switch */ else - ODM_SetBBReg(pDM_Odm,ODM_REG_IGI_B_11N, BIT7,1); // Enable Hardware antenna switch - ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 1);//Enable antenna diversity + ODM_SetBBReg(pDM_Odm,ODM_REG_IGI_B_11N, BIT7,1); /* Enable Hardware antenna switch */ + ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 1);/* Enable antenna diversity */ - pDM_SWAT_Table->CurAntenna=0; //choose left antenna as default antenna + pDM_SWAT_Table->CurAntenna=0; /* choose left antenna as default antenna */ pDM_SWAT_Table->PreAntenna=0; for(i=0; i OFDM_Ant2_Cnt) (*pDefAnt)=1; else (*pDefAnt)=0; } - // else if RX CCK packet number larger than 10 + /* else if RX CCK packet number larger than 10 */ else if((CCK_Ant1_Cnt + CCK_Ant2_Cnt) >=10 ) { if(CCK_Ant1_Cnt > (5*CCK_Ant2_Cnt)) @@ -3782,8 +3756,8 @@ odm_StaDefAntSel( ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("TxAnt = %s\n",((*pDefAnt)==1)?"Ant1":"Ant2")); #endif - //u32 antsel = ODM_GetBBReg(pDM_Odm, 0xc88, bMaskByte0); - //(*pDefAnt)= (u8) antsel; + /* u32 antsel = ODM_GetBBReg(pDM_Odm, 0xc88, bMaskByte0); */ + /* pDefAnt)= (u8) antsel; */ @@ -3805,28 +3779,28 @@ odm_SetRxIdleAnt( { SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_SetRxIdleAnt==============>\n")); + /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_SetRxIdleAnt==============>\n")); */ if(Ant != pDM_SWAT_Table->RxIdleAnt) { - //for path-A + /* for path-A */ if(Ant==1) - ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF, 0x65a9); //right-side antenna + ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF, 0x65a9); /* right-side antenna */ else - ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF, 0x569a); //left-side antenna + ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF, 0x569a); /* left-side antenna */ - //for path-B + /* for path-B */ if(bDualPath){ if(Ant==0) - ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF0000, 0x65a9); //right-side antenna + ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF0000, 0x65a9); /* right-side antenna */ else - ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF0000, 0x569a); //left-side antenna + ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF0000, 0x569a); /* left-side antenna */ } } pDM_SWAT_Table->RxIdleAnt = Ant; ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("RxIdleAnt: %s Reg858=0x%x\n",(Ant==1)?"Ant1":"Ant2",(Ant==1)?0x65a9:0x569a)); - //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============odm_SetRxIdleAnt\n")); + /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============odm_SetRxIdleAnt\n")); */ } @@ -3884,7 +3858,7 @@ odm_HwAntDiv_92C_92D( ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_HwAntDiv==============>\n")); - if(!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV)) //if don't support antenna diveristy + if(!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV)) /* if don't support antenna diveristy */ { ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_HwAntDiv: Not supported!\n")); return; @@ -3919,7 +3893,7 @@ odm_HwAntDiv_92C_92D( RSSI_Min = RSSI; } } - ///STA: found out default antenna + /* STA: found out default antenna */ bRet=odm_StaDefAntSel(pDM_Odm, pDM_SWAT_Table->OFDM_Ant1_Cnt[i], pDM_SWAT_Table->OFDM_Ant2_Cnt[i], @@ -3927,7 +3901,7 @@ odm_HwAntDiv_92C_92D( pDM_SWAT_Table->CCK_Ant2_Cnt[i], &pDM_SWAT_Table->TxAnt[i]); - //if Tx antenna selection: successful + /* if Tx antenna selection: successful */ if(bRet){ pDM_SWAT_Table->RSSI_Ant1_Sum[i] = 0; pDM_SWAT_Table->RSSI_Ant2_Sum[i] = 0; @@ -3939,7 +3913,7 @@ odm_HwAntDiv_92C_92D( } } - //set RX Idle Ant + /* set RX Idle Ant */ RxIdleAnt = pDM_SWAT_Table->TxAnt[pDM_SWAT_Table->TargetSTA]; odm_SetRxIdleAnt(pDM_Odm, RxIdleAnt, FALSE); @@ -3967,19 +3941,19 @@ odm_HwAntDiv( } -#else //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) +#else /* if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) */ void odm_InitHybridAntDiv( IN PDM_ODM_T pDM_Odm ){} void odm_HwAntDiv( IN PDM_ODM_T pDM_Odm){} void ODM_SetTxAntByTxInfo_88C_92D( IN PDM_ODM_T pDM_Odm){ } -#endif //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) +#endif /* if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) */ -//============================================================ -//EDCA Turbo -//============================================================ +/* */ +/* EDCA Turbo */ +/* */ void ODM_EdcaTurboInit( IN PDM_ODM_T pDM_Odm) @@ -3992,25 +3966,25 @@ ODM_EdcaTurboInit( ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VI PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VI_PARAM))); ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM))); ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BK PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BK_PARAM))); -} // ODM_InitEdcaTurbo +} /* ODM_InitEdcaTurbo */ void odm_EdcaTurboCheck( IN PDM_ODM_T pDM_Odm ) { - // - // For AP/ADSL use prtl8192cd_priv - // For CE/NIC use PADAPTER - // + /* */ + /* For AP/ADSL use prtl8192cd_priv */ + /* For CE/NIC use PADAPTER */ + /* */ struct adapter * pAdapter = pDM_Odm->Adapter; prtl8192cd_priv priv = pDM_Odm->priv; - // - // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate - // at the same time. In the stage2/3, we need to prive universal interface and merge all - // HW dynamic mechanism. - // + /* */ + /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ + /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ + /* HW dynamic mechanism. */ + /* */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheck========================>\n")); if(!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO )) @@ -4028,7 +4002,7 @@ odm_EdcaTurboCheck( } ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("<========================odm_EdcaTurboCheck\n")); -} // odm_CheckEdcaTurbo +} /* odm_CheckEdcaTurbo */ void odm_EdcaTurboCheckCE( @@ -4051,7 +4025,7 @@ odm_EdcaTurboCheckCE( struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - if ((pregpriv->wifi_spec == 1) )//|| (pmlmeinfo->HT_enable == 0)) + if ((pregpriv->wifi_spec == 1) )/* (pmlmeinfo->HT_enable == 0)) */ { goto dm_CheckEdcaTurbo_EXIT; } @@ -4068,32 +4042,32 @@ odm_EdcaTurboCheckCE( } #endif - // Check if the status needs to be changed. + /* Check if the status needs to be changed. */ if((bbtchange) || (!precvpriv->bIsAnyNonBEPkts) ) { cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes; cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes; - //traffic, TX or RX + /* traffic, TX or RX */ if((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK)||(pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) { if (cur_tx_bytes > (cur_rx_bytes << 2)) - { // Uplink TP is present. + { /* Uplink TP is present. */ trafficIndex = UP_LINK; } else - { // Balance TP is present. + { /* Balance TP is present. */ trafficIndex = DOWN_LINK; } } else { if (cur_rx_bytes > (cur_tx_bytes << 2)) - { // Downlink TP is present. + { /* Downlink TP is present. */ trafficIndex = DOWN_LINK; } else - { // Balance TP is present. + { /* Balance TP is present. */ trafficIndex = UP_LINK; } } @@ -4119,10 +4093,10 @@ odm_EdcaTurboCheckCE( pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true; } else { - // - // Turn Off EDCA turbo here. - // Restore original EDCA according to the declaration of AP. - // + /* */ + /* Turn Off EDCA turbo here. */ + /* Restore original EDCA according to the declaration of AP. */ + /* */ if(pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) { rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE); @@ -4131,13 +4105,13 @@ odm_EdcaTurboCheckCE( } dm_CheckEdcaTurbo_EXIT: - // Set variables for next time. + /* Set variables for next time. */ precvpriv->bIsAnyNonBEPkts = false; pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes; precvpriv->last_rx_bytes = precvpriv->rx_bytes; } -//move to here for ANT detection mechanism using +/* move to here for ANT detection mechanism using */ u32 GetPSDData( @@ -4145,19 +4119,19 @@ GetPSDData( unsigned int point, u8 initial_gain_psd) { - //unsigned int val, rfval; - //int psd_report; + /* unsigned int val, rfval; */ + /* int psd_report; */ u32 psd_report; - //Set DCO frequency index, offset=(40MHz/SamplePts)*point + /* Set DCO frequency index, offset=(40MHz/SamplePts)*point */ ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point); - //Start PSD calculation, Reg808[22]=0->1 + /* Start PSD calculation, Reg808[22]=0->1 */ ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1); - //Need to wait for HW PSD report + /* Need to wait for HW PSD report */ ODM_StallExecution(30); ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0); - //Read PSD report, Reg8B4[15:0] + /* Read PSD report, Reg8B4[15:0] */ psd_report = ODM_GetBBReg(pDM_Odm,0x8B4, bMaskDWord) & 0x0000FFFF; psd_report = (u32) (ConvertTo_dB(psd_report))+(u32)(initial_gain_psd-0x1c); @@ -4181,7 +4155,7 @@ ConvertTo_dB( } if (i >= 8) - return 96; // maximum 96 dB + return 96; /* maximum 96 dB */ for (j=0;j<12;j++) { if (Value <= dB_Invert_Table[i][j]) @@ -4193,22 +4167,22 @@ ConvertTo_dB( return dB; } -// -// 2011/09/22 MH Add for 92D global spin lock utilization. -// +/* */ +/* 2011/09/22 MH Add for 92D global spin lock utilization. */ +/* */ void odm_GlobalAdapterCheck( IN void ) { -} // odm_GlobalAdapterCheck +} /* odm_GlobalAdapterCheck */ -// -// Description: -// Set Single/Dual Antenna default setting for products that do not do detection in advance. -// -// Added by Joseph, 2012.03.22 -// +/* */ +/* Description: */ +/* Set Single/Dual Antenna default setting for products that do not do detection in advance. */ +/* */ +/* Added by Joseph, 2012.03.22 */ +/* */ void ODM_SingleDualAntennaDefaultSetting( IN PDM_ODM_T pDM_Odm @@ -4220,7 +4194,7 @@ ODM_SingleDualAntennaDefaultSetting( } -//2 8723A ANT DETECT +/* 2 8723A ANT DETECT */ static void @@ -4233,7 +4207,7 @@ odm_PHY_SaveAFERegisters( { u32 i; - //RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n")); + /* RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n")); */ for( i = 0 ; i < RegisterNum ; i++){ AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord); } @@ -4249,7 +4223,7 @@ odm_PHY_ReloadAFERegisters( { u32 i; - //RTPRINT(FINIT, INIT_IQK, ("Reload ADDA power saving parameters !\n")); + /* RTPRINT(FINIT, INIT_IQK, ("Reload ADDA power saving parameters !\n")); */ for(i = 0 ; i < RegiesterNum; i++) { @@ -4257,14 +4231,14 @@ odm_PHY_ReloadAFERegisters( } } -//2 8723A ANT DETECT -// -// Description: -// Implement IQK single tone for RF DPK loopback and BB PSD scanning. -// This function is cooperated with BB team Neil. -// -// Added by Roger, 2011.12.15 -// +/* 2 8723A ANT DETECT */ +/* */ +/* Description: */ +/* Implement IQK single tone for RF DPK loopback and BB PSD scanning. */ +/* This function is cooperated with BB team Neil. */ +/* */ +/* Added by Roger, 2011.12.15 */ +/* */ BOOLEAN ODM_SingleDualAntennaDetection( IN PDM_ODM_T pDM_Odm, @@ -4272,8 +4246,8 @@ ODM_SingleDualAntennaDetection( ) { - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - //PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + /* HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); */ + /* PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; */ pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; u32 CurrentChannel,RfLoopReg; u8 n; @@ -4301,39 +4275,39 @@ ODM_SingleDualAntennaDetection( if(pDM_Odm->SupportICType == ODM_RTL8192C) { - //Which path in ADC/DAC is turnned on for PSD: both I/Q + /* Which path in ADC/DAC is turnned on for PSD: both I/Q */ ODM_SetBBReg(pDM_Odm, 0x808, BIT10|BIT11, 0x3); - //Ageraged number: 8 + /* Ageraged number: 8 */ ODM_SetBBReg(pDM_Odm, 0x808, BIT12|BIT13, 0x1); - //pts = 128; + /* pts = 128; */ ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0); } - //1 Backup Current RF/BB Settings + /* 1 Backup Current RF/BB Settings */ CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask); RfLoopReg = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask); - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A); // change to Antenna A - // Step 1: USE IQK to transmitter single tone + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A); /* change to Antenna A */ + /* Step 1: USE IQK to transmitter single tone */ ODM_StallExecution(10); - //Store A Path Register 88c, c08, 874, c50 + /* Store A Path Register 88c, c08, 874, c50 */ Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord); Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord); Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord); Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord); - // Store AFE Registers + /* Store AFE Registers */ odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16); - //Set PSD 128 pts - ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); //128 pts + /* Set PSD 128 pts */ + ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); /* 128 pts */ - // To SET CH1 to do - ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01); //Channel 1 + /* To SET CH1 to do */ + ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01); /* Channel 1 */ - // AFE all on step + /* AFE all on step */ ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4); ODM_SetBBReg(pDM_Odm, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4); ODM_SetBBReg(pDM_Odm, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4); @@ -4351,19 +4325,19 @@ ODM_SingleDualAntennaDetection( ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4); ODM_SetBBReg(pDM_Odm, rBlue_Tooth, bMaskDWord, 0x6FDB25A4); - // 3 wire Disable + /* 3 wire Disable */ ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0); - //BB IQK Setting + /* BB IQK Setting */ ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4); ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000); - //IQK setting tone@ 4.34Mhz + /* IQK setting tone@ 4.34Mhz */ ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C); ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); - //Page B init + /* Page B init */ ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000); ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); @@ -4372,10 +4346,10 @@ ODM_SingleDualAntennaDetection( ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150008); ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0); - //RF loop Setting + /* RF loop Setting */ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0, 0xFFFFF, 0x50008); - //IQK Single tone start + /* IQK Single tone start */ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000); ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); ODM_StallExecution(1000); @@ -4390,7 +4364,7 @@ ODM_SingleDualAntennaDetection( PSD_report_tmp=0x0; - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B); // change to Antenna B + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B); /* change to Antenna B */ ODM_StallExecution(10); @@ -4401,8 +4375,8 @@ ODM_SingleDualAntennaDetection( AntB_report=PSD_report_tmp; } - // change to open case - ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, 0); // change to Ant A and B all open case + /* change to open case */ + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, 0); /* change to Ant A and B all open case */ ODM_StallExecution(10); for (n=0;n<2;n++) @@ -4412,11 +4386,11 @@ ODM_SingleDualAntennaDetection( AntO_report=PSD_report_tmp; } - //Close IQK Single Tone function + /* Close IQK Single Tone function */ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); PSD_report_tmp = 0x0; - //1 Return to antanna A + /* 1 Return to antanna A */ ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A); ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c); ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08); @@ -4426,7 +4400,7 @@ ODM_SingleDualAntennaDetection( ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,CurrentChannel); ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask,RfLoopReg); - //Reload AFE Registers + /* Reload AFE Registers */ odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16); ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d \n", 2416, AntA_report)); @@ -4436,7 +4410,7 @@ ODM_SingleDualAntennaDetection( if(pDM_Odm->SupportICType == ODM_RTL8723A) { - //2 Test Ant B based on Ant A is ON + /* 2 Test Ant B based on Ant A is ON */ if(mode==ANTTESTB) { if(AntA_report >= 100) @@ -4455,11 +4429,11 @@ ODM_SingleDualAntennaDetection( else { ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n")); - pDM_SWAT_Table->ANTB_ON=FALSE; // Set Antenna B off as default + pDM_SWAT_Table->ANTB_ON=FALSE; /* Set Antenna B off as default */ bResult = FALSE; } } - //2 Test Ant A and B based on DPDT Open + /* 2 Test Ant A and B based on DPDT Open */ else if(mode==ANTTESTALL) { if((AntO_report >=100)&(AntO_report <118)) @@ -4467,26 +4441,26 @@ ODM_SingleDualAntennaDetection( if(AntA_report > (AntO_report+1)) { pDM_SWAT_Table->ANTA_ON=FALSE; - //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna A is OFF\n")); + /* RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna A is OFF\n")); */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant A is OFF")); } else { pDM_SWAT_Table->ANTA_ON=TRUE; - //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna A is ON\n")); + /* RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna A is ON\n")); */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant A is ON")); } if(AntB_report > (AntO_report+2)) { pDM_SWAT_Table->ANTB_ON=FALSE; - //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna B is OFF\n")); + /* RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna B is OFF\n")); */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant B is OFF")); } else { pDM_SWAT_Table->ANTB_ON=TRUE; - //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna B is ON\n")); + /* RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna B is ON\n")); */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant B is ON")); } } @@ -4520,8 +4494,8 @@ ODM_SingleDualAntennaDetection( else { ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n")); - pDM_SWAT_Table->ANTA_ON=TRUE; // Set Antenna A on as default - pDM_SWAT_Table->ANTB_ON=FALSE; // Set Antenna B off as default + pDM_SWAT_Table->ANTA_ON=TRUE; /* Set Antenna A on as default */ + pDM_SWAT_Table->ANTB_ON=FALSE; /* Set Antenna B off as default */ bResult = FALSE; } } diff --git a/hal/odm.h b/hal/odm.h index 00d76b6..3e1efe6 100755 --- a/hal/odm.h +++ b/hal/odm.h @@ -22,60 +22,60 @@ #ifndef __HALDMOUTSRC_H__ #define __HALDMOUTSRC_H__ -//============================================================ -// Definition -//============================================================ -// -// 2011/09/22 MH Define all team supprt ability. -// +/* */ +/* Definition */ +/* */ +/* */ +/* 2011/09/22 MH Define all team supprt ability. */ +/* */ -// -// 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header. -// -//#define DM_ODM_SUPPORT_AP 0 -//#define DM_ODM_SUPPORT_ADSL 0 -//#define DM_ODM_SUPPORT_CE 0 -//#define DM_ODM_SUPPORT_MP 1 +/* */ +/* 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header. */ +/* */ +/* define DM_ODM_SUPPORT_AP 0 */ +/* define DM_ODM_SUPPORT_ADSL 0 */ +/* define DM_ODM_SUPPORT_CE 0 */ +/* define DM_ODM_SUPPORT_MP 1 */ -// -// 2011/09/28 MH Define ODM SW team support flag. -// +/* */ +/* 2011/09/28 MH Define ODM SW team support flag. */ +/* */ -// -// Antenna Switch Relative Definition. -// +/* */ +/* Antenna Switch Relative Definition. */ +/* */ -// -// 20100503 Joseph: -// Add new function SwAntDivCheck8192C(). -// This is the main function of Antenna diversity function before link. -// Mainly, it just retains last scan result and scan again. -// After that, it compares the scan result to see which one gets better RSSI. -// It selects antenna with better receiving power and returns better scan result. -// +/* */ +/* 20100503 Joseph: */ +/* Add new function SwAntDivCheck8192C(). */ +/* This is the main function of Antenna diversity function before link. */ +/* Mainly, it just retains last scan result and scan again. */ +/* After that, it compares the scan result to see which one gets better RSSI. */ +/* It selects antenna with better receiving power and returns better scan result. */ +/* */ #define TP_MODE 0 #define RSSI_MODE 1 #define TRAFFIC_LOW 0 #define TRAFFIC_HIGH 1 -//============================================================ -//3 Tx Power Tracking -//3============================================================ +/* */ +/* 3 Tx Power Tracking */ +/* 3============================================================ */ #define DPK_DELTA_MAPPING_NUM 13 #define index_mapping_HP_NUM 15 -//============================================================ -//3 PSD Handler -//3============================================================ +/* */ +/* 3 PSD Handler */ +/* 3============================================================ */ -#define AFH_PSD 1 //0:normal PSD scan, 1: only do 20 pts PSD -#define MODE_40M 0 //0:20M, 1:40M +#define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */ +#define MODE_40M 0 /* 0:20M, 1:40M */ #define PSD_TH2 3 -#define PSD_CHMIN 20 // Minimum channel number for BT AFH +#define PSD_CHMIN 20 /* Minimum channel number for BT AFH */ #define SIR_STEP_SIZE 3 #define Smooth_Size_1 5 #define Smooth_TH_1 3 @@ -90,41 +90,41 @@ #else #define PSD_RESCAN 4 #endif -#define PSD_SCAN_INTERVAL 700 //ms +#define PSD_SCAN_INTERVAL 700 /* ms */ -//8723A High Power IGI Setting +/* 8723A High Power IGI Setting */ #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a #define DM_DIG_LOW_PWR_THRESHOLD 0x14 -//ANT Test -#define ANTTESTALL 0x00 //Ant A or B will be Testing -#define ANTTESTA 0x01 //Ant A will be Testing -#define ANTTESTB 0x02 //Ant B will be testing +/* ANT Test */ +#define ANTTESTALL 0x00 /* Ant A or B will be Testing */ +#define ANTTESTA 0x01 /* Ant A will be Testing */ +#define ANTTESTB 0x02 /* Ant B will be testing */ -// LPS define -#define DM_DIG_FA_TH0_LPS 4 //-> 4 in lps -#define DM_DIG_FA_TH1_LPS 15 //-> 15 lps -#define DM_DIG_FA_TH2_LPS 30 //-> 30 lps +/* LPS define */ +#define DM_DIG_FA_TH0_LPS 4 /* 4 in lps */ +#define DM_DIG_FA_TH1_LPS 15 /* 15 lps */ +#define DM_DIG_FA_TH2_LPS 30 /* 30 lps */ #define RSSI_OFFSET_DIG 0x05; -//ANT Test -#define ANTTESTALL 0x00 //Ant A or B will be Testing -#define ANTTESTA 0x01 //Ant A will be Testing -#define ANTTESTB 0x02 //Ant B will be testing +/* ANT Test */ +#define ANTTESTALL 0x00 /* Ant A or B will be Testing */ +#define ANTTESTA 0x01 /* Ant A will be Testing */ +#define ANTTESTB 0x02 /* Ant B will be testing */ -//============================================================ -// structure and define -//============================================================ +/* */ +/* structure and define */ +/* */ -// -// 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement. -// We need to remove to other position??? -// +/* */ +/* 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement. */ +/* We need to remove to other position??? */ +/* */ typedef struct rtl8192cd_priv { u8 temp; @@ -203,8 +203,8 @@ typedef struct false_ALARM_STATISTICS{ u32 Cnt_OFDM_CCA; u32 Cnt_CCK_CCA; u32 Cnt_CCA_all; - u32 Cnt_BW_USC; //Gary - u32 Cnt_BW_LSC; //Gary + u32 Cnt_BW_USC; /* Gary */ + u32 Cnt_BW_LSC; /* Gary */ }FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS; typedef struct _Dynamic_Primary_CCA{ @@ -230,14 +230,14 @@ typedef struct _RX_High_Power_ RT_TIMER PSDTimer; }RXHP_T, *pRXHP_T; -#define ASSOCIATE_ENTRY_NUM 32 // Max size of AsocEntry[]. +#define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM -//#ifdef CONFIG_ANTENNA_DIVERSITY -// This indicates two different the steps. -// In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. -// In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK -// with original RSSI to determine if it is necessary to switch antenna. +/* ifdef CONFIG_ANTENNA_DIVERSITY */ +/* This indicates two different the steps. */ +/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ +/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ +/* with original RSSI to determine if it is necessary to switch antenna. */ #define SWAW_STEP_PEAK 0 #define SWAW_STEP_DETERMINE 1 @@ -258,11 +258,11 @@ typedef struct _SW_Antenna_Switch_ u8 SelectAntennaMap; u8 RSSI_target; - // Before link Antenna Switch check + /* Before link Antenna Switch check */ u8 SWAS_NoLink_State; u32 SWAS_NoLink_BK_Reg860; - BOOLEAN ANTA_ON; //To indicate Ant A is or not - BOOLEAN ANTB_ON; //To indicate Ant B is on or not + BOOLEAN ANTA_ON; /* To indicate Ant A is or not */ + BOOLEAN ANTB_ON; /* To indicate Ant B is on or not */ s32 RSSI_sum_A; s32 RSSI_sum_B; @@ -278,7 +278,7 @@ typedef struct _SW_Antenna_Switch_ u8 TrafficLoad; RT_TIMER SwAntennaSwitchTimer; #ifdef CONFIG_HW_ANTENNA_DIVERSITY - //Hybrid Antenna Diversity + /* Hybrid Antenna Diversity */ u32 CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM]; u32 CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM]; u32 OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM]; @@ -296,17 +296,17 @@ typedef struct _SW_Antenna_Switch_ typedef struct _EDCA_TURBO_ { BOOLEAN bCurrentTurboEDCA; BOOLEAN bIsCurRDLState; - u32 prv_traffic_idx; // edca turbo + u32 prv_traffic_idx; /* edca turbo */ }EDCA_T,*pEDCA_T; typedef struct _ODM_RATE_ADAPTIVE { - u8 Type; // DM_Type_ByFW/DM_Type_ByDriver - u8 HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH - u8 LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW - u8 RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW - u32 LastRATR; // RATR Register Content + u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */ + u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ + u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ + u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ + u32 LastRATR; /* RATR Register Content */ } ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE; @@ -327,37 +327,37 @@ typedef struct _ODM_RATE_ADAPTIVE #define DM_Type_ByFW 0 #define DM_Type_ByDriver 1 -// -// Declare for common info -// -// Declare for common info -// +/* */ +/* Declare for common info */ +/* */ +/* Declare for common info */ +/* */ #define MAX_PATH_NUM_92CS 2 typedef struct _ODM_Phy_Status_Info_ { u8 RxPWDBAll; - u8 SignalQuality; // in 0-100 index. - u8 RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; //EVM - u8 RxMIMOSignalStrength[MAX_PATH_NUM_92CS];// in 0~100 index - s8 RxPower; // in dBm Translate from PWdB - s8 RecvSignalPower;// Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. + u8 SignalQuality; /* in 0-100 index. */ + u8 RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; /* EVM */ + u8 RxMIMOSignalStrength[MAX_PATH_NUM_92CS];/* in 0~100 index */ + s8 RxPower; /* in dBm Translate from PWdB */ + s8 RecvSignalPower;/* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ u8 BTRxRSSIPercentage; - u8 SignalStrength; // in 0-100 index. - u8 RxPwr[MAX_PATH_NUM_92CS];//per-path's pwdb - u8 RxSNR[MAX_PATH_NUM_92CS];//per-path's SNR + u8 SignalStrength; /* in 0-100 index. */ + u8 RxPwr[MAX_PATH_NUM_92CS];/* per-path's pwdb */ + u8 RxSNR[MAX_PATH_NUM_92CS];/* per-path's SNR */ }ODM_PHY_INFO_T,*PODM_PHY_INFO_T; typedef struct _ODM_Phy_Dbg_Info_ { - //ODM Write,debug info + /* ODM Write,debug info */ s8 RxSNRdB[MAX_PATH_NUM_92CS]; u64 NumQryPhyStatus; u64 NumQryPhyStatusCCK; u64 NumQryPhyStatusOFDM; u8 NumQryBeaconPkt; - //Others + /* Others */ s32 RxEVM[MAX_PATH_NUM_92CS]; }ODM_PHY_DBG_INFO_T; @@ -381,7 +381,7 @@ typedef struct _ODM_Mac_Status_Info_ typedef enum tag_Dynamic_ODM_Support_Ability_Type { - // BB Team + /* BB Team */ ODM_DIG = 0x00000001, ODM_HIGH_POWER = 0x00000002, ODM_CCK_CCA_TH = 0x00000004, @@ -396,72 +396,71 @@ typedef enum tag_Dynamic_ODM_Support_Ability_Type ODM_PSD2AFH = 0x00000800 }ODM_Ability_E; -// -// 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T -// Please declare below ODM relative info in your STA info structure. -// +/* */ +/* 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T */ +/* Please declare below ODM relative info in your STA info structure. */ +/* */ typedef struct _ODM_STA_INFO{ - // Driver Write - BOOLEAN bUsed; // record the sta status link or not? - //u8 WirelessMode; // - u8 IOTPeer; // Enum value. HT_IOT_PEER_E + /* Driver Write */ + BOOLEAN bUsed; /* record the sta status link or not? */ + u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */ - // ODM Write - //1 PHY_STATUS_INFO - u8 RSSI_Path[4]; // + /* ODM Write */ + /* 1 PHY_STATUS_INFO */ + u8 RSSI_Path[4]; /* */ u8 RSSI_Ave; u8 RXEVM[4]; u8 RXSNR[4]; } ODM_STA_INFO_T, *PODM_STA_INFO_T; -// -// 2011/10/20 MH Define Common info enum for all team. -// +/* */ +/* 2011/10/20 MH Define Common info enum for all team. */ +/* */ typedef enum _ODM_Common_Info_Definition { -//-------------REMOVED CASE-----------// - //ODM_CMNINFO_CCK_HP, - //ODM_CMNINFO_RFPATH_ENABLE, // Define as ODM write??? - //ODM_CMNINFO_BT_COEXIST, // ODM_BT_COEXIST_E - //ODM_CMNINFO_OP_MODE, // ODM_OPERATION_MODE_E -//-------------REMOVED CASE-----------// +/* REMOVED CASE----------- */ + /* ODM_CMNINFO_CCK_HP, */ + /* ODM_CMNINFO_RFPATH_ENABLE, Define as ODM write??? */ + /* ODM_CMNINFO_BT_COEXIST, ODM_BT_COEXIST_E */ + /* ODM_CMNINFO_OP_MODE, ODM_OPERATION_MODE_E */ +/* REMOVED CASE----------- */ - // - // Fixed value: - // + /* */ + /* Fixed value: */ + /* */ - //-----------HOOK BEFORE REG INIT-----------// + /* HOOK BEFORE REG INIT----------- */ ODM_CMNINFO_PLATFORM = 0, - ODM_CMNINFO_ABILITY, // ODM_ABILITY_E - ODM_CMNINFO_INTERFACE, // ODM_INTERFACE_E + ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */ + ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */ ODM_CMNINFO_MP_TEST_CHIP, - ODM_CMNINFO_IC_TYPE, // ODM_IC_TYPE_E - ODM_CMNINFO_CUT_VER, // ODM_CUT_VERSION_E - ODM_CMNINFO_FAB_VER, // ODM_FAB_E - ODM_CMNINFO_RF_TYPE, // ODM_RF_PATH_E or ODM_RF_TYPE_E? - ODM_CMNINFO_BOARD_TYPE, // ODM_BOARD_TYPE_E - ODM_CMNINFO_EXT_LNA, // TRUE + ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */ + ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */ + ODM_CMNINFO_FAB_VER, /* ODM_FAB_E */ + ODM_CMNINFO_RF_TYPE, /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */ + ODM_CMNINFO_BOARD_TYPE, /* ODM_BOARD_TYPE_E */ + ODM_CMNINFO_EXT_LNA, /* TRUE */ ODM_CMNINFO_EXT_PA, ODM_CMNINFO_EXT_TRSW, - ODM_CMNINFO_PATCH_ID, //CUSTOMER ID + ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */ ODM_CMNINFO_BINHCT_TEST, ODM_CMNINFO_BWIFI_TEST, ODM_CMNINFO_SMART_CONCURRENT, - //-----------HOOK BEFORE REG INIT-----------// + /* HOOK BEFORE REG INIT----------- */ - // - // Dynamic value: - // -//--------- POINTER REFERENCE-----------// - ODM_CMNINFO_MAC_PHY_MODE, // ODM_MAC_PHY_MODE_E + /* */ + /* Dynamic value: */ + /* */ +/* POINTER REFERENCE----------- */ + ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */ ODM_CMNINFO_TX_UNI, ODM_CMNINFO_RX_UNI, - ODM_CMNINFO_WM_MODE, // ODM_WIRELESS_MODE_E - ODM_CMNINFO_BAND, // ODM_BAND_TYPE_E - ODM_CMNINFO_SEC_CHNL_OFFSET, // ODM_SEC_CHNL_OFFSET_E - ODM_CMNINFO_SEC_MODE, // ODM_SECURITY_E - ODM_CMNINFO_BW, // ODM_BW_E + ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */ + ODM_CMNINFO_BAND, /* ODM_BAND_TYPE_E */ + ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */ + ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */ + ODM_CMNINFO_BW, /* ODM_BW_E */ ODM_CMNINFO_CHNL, ODM_CMNINFO_DMSP_GET_VALUE, @@ -469,36 +468,36 @@ typedef enum _ODM_Common_Info_Definition ODM_CMNINFO_DMSP_IS_MASTER, ODM_CMNINFO_SCAN, ODM_CMNINFO_POWER_SAVING, - ODM_CMNINFO_ONE_PATH_CCA, // ODM_CCA_PATH_E + ODM_CMNINFO_ONE_PATH_CCA, /* ODM_CCA_PATH_E */ ODM_CMNINFO_DRV_STOP, ODM_CMNINFO_PNP_IN, ODM_CMNINFO_INIT_ON, ODM_CMNINFO_ANT_TEST, ODM_CMNINFO_NET_CLOSED, ODM_CMNINFO_MP_MODE, -//--------- POINTER REFERENCE-----------// +/* POINTER REFERENCE----------- */ -//------------CALL BY VALUE-------------// +/* CALL BY VALUE------------- */ ODM_CMNINFO_WIFI_DIRECT, ODM_CMNINFO_WIFI_DISPLAY, ODM_CMNINFO_LINK, ODM_CMNINFO_RSSI_MIN, - ODM_CMNINFO_DBG_COMP, // u64 - ODM_CMNINFO_DBG_LEVEL, // u32 - ODM_CMNINFO_RA_THRESHOLD_HIGH, // u8 - ODM_CMNINFO_RA_THRESHOLD_LOW, // u8 - ODM_CMNINFO_RF_ANTENNA_TYPE, // u8 + ODM_CMNINFO_DBG_COMP, /* u64 */ + ODM_CMNINFO_DBG_LEVEL, /* u32 */ + ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */ + ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */ + ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ ODM_CMNINFO_BT_DISABLED, ODM_CMNINFO_BT_OPERATION, ODM_CMNINFO_BT_DIG, - ODM_CMNINFO_BT_BUSY, //Check Bt is using or not//neil + ODM_CMNINFO_BT_BUSY, /* Check Bt is using or not */ ODM_CMNINFO_BT_DISABLE_EDCA, ODM_CMNINFO_STATION_STATE, -//------------CALL BY VALUE-------------// +/* CALL BY VALUE------------- */ - // - // Dynamic ptr array hook itms. - // + /* */ + /* Dynamic ptr array hook itms. */ + /* */ ODM_CMNINFO_STA_STATUS, ODM_CMNINFO_PHY_STATUS, ODM_CMNINFO_MAC_STATUS, @@ -508,14 +507,14 @@ typedef enum _ODM_Common_Info_Definition }ODM_CMNINFO_E; -// -// 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY -// +/* */ +/* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */ +/* */ typedef enum _ODM_Support_Ability_Definition { - // - // BB ODM section BIT 0-15 - // + /* */ + /* BB ODM section BIT 0-15 */ + /* */ ODM_BB_DIG = BIT0, ODM_BB_RA_MASK = BIT1, ODM_BB_DYNAMIC_TXPWR = BIT2, @@ -532,22 +531,22 @@ typedef enum _ODM_Support_Ability_Definition ODM_BB_ADAPTIVITY = BIT13, ODM_BB_DYNAMIC_ATC = BIT14, - // - // MAC DM section BIT 16-23 - // + /* */ + /* MAC DM section BIT 16-23 */ + /* */ ODM_MAC_EDCA_TURBO = BIT16, ODM_MAC_EARLY_MODE = BIT17, - // - // RF ODM section BIT 24-31 - // + /* */ + /* RF ODM section BIT 24-31 */ + /* */ ODM_RF_TX_PWR_TRACK = BIT24, ODM_RF_RX_GAIN_TRACK = BIT25, ODM_RF_CALIBRATION = BIT26, }ODM_ABILITY_E; -// ODM_CMNINFO_INTERFACE +/* ODM_CMNINFO_INTERFACE */ typedef enum tag_ODM_Support_Interface_Definition { ODM_ITRF_PCIE = 0x1, @@ -556,7 +555,7 @@ typedef enum tag_ODM_Support_Interface_Definition ODM_ITRF_ALL = 0x7, }ODM_INTERFACE_E; -// ODM_CMNINFO_IC_TYPE +/* ODM_CMNINFO_IC_TYPE */ typedef enum tag_ODM_Support_IC_Type_Definition { ODM_RTL8192S = BIT0, @@ -575,7 +574,7 @@ typedef enum tag_ODM_Support_IC_Type_Definition #define ODM_IC_11N_SERIES (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E) #define ODM_IC_11AC_SERIES (ODM_RTL8812) -//ODM_CMNINFO_CUT_VER +/* ODM_CMNINFO_CUT_VER */ typedef enum tag_ODM_Cut_Version_Definition { ODM_CUT_A = 1, @@ -587,17 +586,17 @@ typedef enum tag_ODM_Cut_Version_Definition ODM_CUT_TEST = 7, }ODM_CUT_VERSION_E; -// ODM_CMNINFO_FAB_VER +/* ODM_CMNINFO_FAB_VER */ typedef enum tag_ODM_Fab_Version_Definition { ODM_TSMC = 0, ODM_UMC = 1, }ODM_FAB_E; -// ODM_CMNINFO_RF_TYPE -// -// For example 1T2R (A+AB = BIT0|BIT4|BIT5) -// +/* ODM_CMNINFO_RF_TYPE */ +/* */ +/* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */ +/* */ typedef enum tag_ODM_RF_Path_Bit_Definition { ODM_RF_TX_A = BIT0, @@ -624,16 +623,16 @@ typedef enum tag_ODM_RF_Type_Definition }ODM_RF_TYPE_E; -// -// ODM Dynamic common info value definition -// +/* */ +/* ODM Dynamic common info value definition */ +/* */ -//typedef enum _MACPHY_MODE_8192D{ -// SINGLEMAC_SINGLEPHY, -// DUALMAC_DUALPHY, -// DUALMAC_SINGLEPHY, -//}MACPHY_MODE_8192D,*PMACPHY_MODE_8192D; -// Above is the original define in MP driver. Please use the same define. THX. +/* typedef enum _MACPHY_MODE_8192D{ */ +/* SINGLEMAC_SINGLEPHY, */ +/* DUALMAC_DUALPHY, */ +/* DUALMAC_SINGLEPHY, */ +/* MACPHY_MODE_8192D,*PMACPHY_MODE_8192D; */ +/* Above is the original define in MP driver. Please use the same define. THX. */ typedef enum tag_ODM_MAC_PHY_Mode_Definition { ODM_SMSP = 0, @@ -650,7 +649,7 @@ typedef enum tag_BT_Coexist_Definition ODM_BT_NONE = 4, }ODM_BT_COEXIST_E; -// ODM_CMNINFO_OP_MODE +/* ODM_CMNINFO_OP_MODE */ typedef enum tag_Operation_Mode_Definition { ODM_NO_LINK = BIT0, @@ -664,7 +663,7 @@ typedef enum tag_Operation_Mode_Definition ODM_WIFI_DISPLAY = BIT8, }ODM_OPERATION_MODE_E; -// ODM_CMNINFO_WM_MODE +/* ODM_CMNINFO_WM_MODE */ typedef enum tag_Wireless_Mode_Definition { ODM_WM_UNKNOW = 0x0, @@ -677,7 +676,7 @@ typedef enum tag_Wireless_Mode_Definition ODM_WM_AC = BIT6, }ODM_WIRELESS_MODE_E; -// ODM_CMNINFO_BAND +/* ODM_CMNINFO_BAND */ typedef enum tag_Band_Type_Definition { ODM_BAND_2_4G = BIT0, @@ -685,7 +684,7 @@ typedef enum tag_Band_Type_Definition }ODM_BAND_TYPE_E; -// ODM_CMNINFO_SEC_CHNL_OFFSET +/* ODM_CMNINFO_SEC_CHNL_OFFSET */ typedef enum tag_Secondary_Channel_Offset_Definition { ODM_DONT_CARE = 0, @@ -693,7 +692,7 @@ typedef enum tag_Secondary_Channel_Offset_Definition ODM_ABOVE = 2 }ODM_SEC_CHNL_OFFSET_E; -// ODM_CMNINFO_SEC_MODE +/* ODM_CMNINFO_SEC_MODE */ typedef enum tag_Security_Definition { ODM_SEC_OPEN = 0, @@ -702,11 +701,11 @@ typedef enum tag_Security_Definition ODM_SEC_RESERVE = 3, ODM_SEC_AESCCMP = 4, ODM_SEC_WEP104 = 5, - ODM_WEP_WPA_MIXED = 6, // WEP + WPA + ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */ ODM_SEC_SMS4 = 7, }ODM_SECURITY_E; -// ODM_CMNINFO_BW +/* ODM_CMNINFO_BW */ typedef enum tag_Bandwidth_Definition { ODM_BW20M = 0, @@ -716,21 +715,21 @@ typedef enum tag_Bandwidth_Definition ODM_BW10M = 4, }ODM_BW_E; -// ODM_CMNINFO_CHNL +/* ODM_CMNINFO_CHNL */ -// ODM_CMNINFO_BOARD_TYPE +/* ODM_CMNINFO_BOARD_TYPE */ #if 1 typedef enum tag_Board_Definition { - ODM_BOARD_DEFAULT = 0, // The DEFAULT case. - ODM_BOARD_MINICARD = BIT(0), // 0 = non-mini card, 1= mini card. - ODM_BOARD_SLIM = BIT(1), // 0 = non-slim card, 1 = slim card - ODM_BOARD_BT = BIT(2), // 0 = without BT card, 1 = with BT - ODM_BOARD_EXT_PA = BIT(3), // 0 = no 2G ext-PA, 1 = existing 2G ext-PA - ODM_BOARD_EXT_LNA = BIT(4), // 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA - ODM_BOARD_EXT_TRSW = BIT(5), // 0 = no ext-TRSW, 1 = existing ext-TRSW - ODM_BOARD_EXT_PA_5G = BIT(6), // 0 = no 5G ext-PA, 1 = existing 5G ext-PA - ODM_BOARD_EXT_LNA_5G = BIT(7), // 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA + ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */ + ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1= mini card. */ + ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */ + ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */ + ODM_BOARD_EXT_PA = BIT(3), /* 0 = no 2G ext-PA, 1 = existing 2G ext-PA */ + ODM_BOARD_EXT_LNA = BIT(4), /* 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */ + ODM_BOARD_EXT_TRSW = BIT(5), /* 0 = no ext-TRSW, 1 = existing ext-TRSW */ + ODM_BOARD_EXT_PA_5G = BIT(6), /* 0 = no 5G ext-PA, 1 = existing 5G ext-PA */ + ODM_BOARD_EXT_LNA_5G = BIT(7), /* 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */ }ODM_BOARD_TYPE_E; #else typedef enum tag_Board_Definition @@ -746,7 +745,7 @@ typedef enum tag_Board_Definition -// ODM_CMNINFO_ONE_PATH_CCA +/* ODM_CMNINFO_ONE_PATH_CCA */ typedef enum tag_CCA_Path { ODM_CCA_2R = 0, @@ -772,21 +771,21 @@ typedef struct _ODM_RA_Info_ u32 NscDown; u16 RTY[5]; u32 TOTAL; - u16 DROP;//Retry over or drop - u16 DROP1;//LifeTime over + u16 DROP;/* Retry over or drop */ + u16 DROP1;/* LifeTime over */ u8 Active; u16 RptTime; u8 RAWaitingCounter; u8 RAPendingCounter; -#if 1 //POWER_TRAINING_ACTIVE == 1 // For compile pass only~! - u8 PTActive; // on or off - u8 PTTryState; // 0 trying state, 1 for decision state - u8 PTStage; // 0~6 - u8 PTStopCount; //Stop PT counter - u8 PTPreRate; // if rate change do PT - u8 PTPreRssi; // if RSSI change 5% do PT - u8 PTModeSS; // decide whitch rate should do PT - u8 RAstage; // StageRA, decide how many times RA will be done between PT +#if 1 /* POWER_TRAINING_ACTIVE == 1 For compile pass only~! */ + u8 PTActive; /* on or off */ + u8 PTTryState; /* 0 trying state, 1 for decision state */ + u8 PTStage; /* 0~6 */ + u8 PTStopCount; /* Stop PT counter */ + u8 PTPreRate; /* if rate change do PT */ + u8 PTPreRssi; /* if RSSI change 5% do PT */ + u8 PTModeSS; /* decide whitch rate should do PT */ + u8 RAstage; /* StageRA, decide how many times RA will be done between PT */ u8 PTSmoothFactor; #endif } ODM_RA_INFO_T,*PODM_RA_INFO_T; @@ -798,23 +797,23 @@ typedef struct _IQK_MATRIX_REGS_SETTING{ typedef struct ODM_RF_Calibration_Structure { - //for tx power tracking + /* for tx power tracking */ - u32 RegA24; // for TempCCK + u32 RegA24; /* for TempCCK */ s32 RegE94; s32 RegE9C; s32 RegEB4; s32 RegEBC; - //u8 bTXPowerTracking; + /* u8 bTXPowerTracking; */ u8 TXPowercount; BOOLEAN bTXPowerTrackingInit; BOOLEAN bTXPowerTracking; - u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default + u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ u8 TM_Trigger; - u8 InternalPA5G[2]; //pathA / pathB + u8 InternalPA5G[2]; /* pathA / pathB */ - u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 + u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ u8 ThermalValue; u8 ThermalValue_LCK; u8 ThermalValue_IQK; @@ -830,7 +829,7 @@ typedef struct ODM_RF_Calibration_Structure BOOLEAN bReloadtxpowerindex; u8 bRfPiEnable; - u32 TXPowerTrackingCallbackCnt; //cosa add for debug + u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ u8 bCCKinCH14; u8 CCK_index; @@ -848,7 +847,7 @@ typedef struct ODM_RF_Calibration_Structure u8 Delta_IQK; u8 Delta_LCK; - //for IQK + /* for IQK */ u32 RegC04; u32 Reg874; u32 RegC08; @@ -866,17 +865,17 @@ typedef struct ODM_RF_Calibration_Structure u32 IQK_BB_backup_recover[9]; u32 IQK_BB_backup[IQK_BB_REG_NUM]; - //for APK - u32 APKoutput[2][2]; //path A/B; output1_1a/output1_2a + /* for APK */ + u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ u8 bAPKdone; u8 bAPKThermalMeterIgnore; u8 bDPdone; u8 bDPPathAOK; u8 bDPPathBOK; }ODM_RF_CAL_T,*PODM_RF_CAL_T; -// -// ODM Dynamic common info value definition -// +/* */ +/* ODM Dynamic common info value definition */ +/* */ typedef struct _FAST_ANTENNA_TRAINNING_ { @@ -930,140 +929,140 @@ typedef enum _ANT_DIV_TYPE -// -// 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. -// +/* */ +/* 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */ +/* */ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure { - //RT_TIMER FastAntTrainingTimer; - // - // Add for different team use temporarily - // - struct adapter * Adapter; // For CE/NIC team - prtl8192cd_priv priv; // For AP/ADSL team - // WHen you use Adapter or priv pointer, you must make sure the pointer is ready. + /* RT_TIMER FastAntTrainingTimer; */ + /* */ + /* Add for different team use temporarily */ + /* */ + struct adapter * Adapter; /* For CE/NIC team */ + prtl8192cd_priv priv; /* For AP/ADSL team */ + /* WHen you use Adapter or priv pointer, you must make sure the pointer is ready. */ BOOLEAN odm_ready; rtl8192cd_priv fake_priv; u64 DebugComponents; u32 DebugLevel; -//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// +/* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ BOOLEAN bCckHighPower; - u8 RFPathRxEnable; // ODM_CMNINFO_RFPATH_ENABLE + u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ u8 ControlChannel; -//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// +/* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ -//--------REMOVED COMMON INFO----------// - //u8 PseudoMacPhyMode; - //BOOLEAN *BTCoexist; - //BOOLEAN PseudoBtCoexist; - //u8 OPMode; - //BOOLEAN bAPMode; - //BOOLEAN bClientMode; - //BOOLEAN bAdHocMode; - //BOOLEAN bSlaveOfDMSP; -//--------REMOVED COMMON INFO----------// +/* REMOVED COMMON INFO---------- */ + /* u8 PseudoMacPhyMode; */ + /* BOOLEAN *BTCoexist; */ + /* BOOLEAN PseudoBtCoexist; */ + /* u8 OPMode; */ + /* BOOLEAN bAPMode; */ + /* BOOLEAN bClientMode; */ + /* BOOLEAN bAdHocMode; */ + /* BOOLEAN bSlaveOfDMSP; */ +/* REMOVED COMMON INFO---------- */ -//1 COMMON INFORMATION +/* 1 COMMON INFORMATION */ - // - // Init Value - // -//-----------HOOK BEFORE REG INIT-----------// - // ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 + /* */ + /* Init Value */ + /* */ +/* HOOK BEFORE REG INIT----------- */ + /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */ u8 SupportPlatform; - // ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K + /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K */ u32 SupportAbility; - // ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 + /* ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 */ u8 SupportInterface; - // ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... + /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */ u32 SupportICType; - // Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... + /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */ u8 CutVersion; - // Fab Version TSMC/UMC = 0/1 + /* Fab Version TSMC/UMC = 0/1 */ u8 FabVersion; - // RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... + /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */ u8 RFType; - // Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... + /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */ u8 BoardType; - // with external LNA NO/Yes = 0/1 + /* with external LNA NO/Yes = 0/1 */ u8 ExtLNA; - // with external PA NO/Yes = 0/1 + /* with external PA NO/Yes = 0/1 */ u8 ExtPA; - // with external TRSW NO/Yes = 0/1 + /* with external TRSW NO/Yes = 0/1 */ u8 ExtTRSW; - u8 PatchID; //Customer ID + u8 PatchID; /* Customer ID */ BOOLEAN bInHctTest; BOOLEAN bWIFITest; BOOLEAN bDualMacSmartConcurrent; u32 BK_SupportAbility; u8 AntDivType; -//-----------HOOK BEFORE REG INIT-----------// +/* HOOK BEFORE REG INIT----------- */ - // - // Dynamic Value - // -//--------- POINTER REFERENCE-----------// + /* */ + /* Dynamic Value */ + /* */ +/* POINTER REFERENCE----------- */ u8 u8_temp; BOOLEAN BOOLEAN_temp; struct adapter *_temp; - // MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 + /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */ u8 *pMacPhyMode; - //TX Unicast byte count + /* TX Unicast byte count */ u64 *pNumTxBytesUnicast; - //RX Unicast byte count + /* RX Unicast byte count */ u64 *pNumRxBytesUnicast; - // Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 - u8 *pWirelessMode; //ODM_WIRELESS_MODE_E - // Frequence band 2.4G/5G = 0/1 + /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */ + u8 *pWirelessMode; /* ODM_WIRELESS_MODE_E */ + /* Frequence band 2.4G/5G = 0/1 */ u8 *pBandType; - // Secondary channel offset don't_care/below/above = 0/1/2 + /* Secondary channel offset don't_care/below/above = 0/1/2 */ u8 *pSecChOffset; - // Security mode Open/WEP/AES/TKIP = 0/1/2/3 + /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */ u8 *pSecurity; - // BW info 20M/40M/80M = 0/1/2 + /* BW info 20M/40M/80M = 0/1/2 */ u8 *pBandWidth; - // Central channel location Ch1/Ch2/.... - u8 *pChannel; //central channel number - // Common info for 92D DMSP + /* Central channel location Ch1/Ch2/.... */ + u8 *pChannel; /* central channel number */ + /* Common info for 92D DMSP */ BOOLEAN *pbGetValueFromOtherMac; struct adapter * *pBuddyAdapter; - BOOLEAN *pbMasterOfDMSP; //MAC0: master, MAC1: slave - // Common info for Status + BOOLEAN *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */ + /* Common info for Status */ BOOLEAN *pbScanInProcess; BOOLEAN *pbPowerSaving; - // CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. + /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */ u8 *pOnePathCCA; - //pMgntInfo->AntennaTest + /* pMgntInfo->AntennaTest */ u8 *pAntennaTest; BOOLEAN *pbNet_closed; -//--------- POINTER REFERENCE-----------// - // -//------------CALL BY VALUE-------------// +/* POINTER REFERENCE----------- */ + /* */ +/* CALL BY VALUE------------- */ BOOLEAN bLinkInProcess; BOOLEAN bWIFI_Direct; BOOLEAN bWIFI_Display; BOOLEAN bLinked; BOOLEAN bsta_state; u8 RSSI_Min; - u8 InterfaceIndex; // Add for 92D dual MAC: 0--Mac0 1--Mac1 + u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ BOOLEAN bIsMPChip; BOOLEAN bOneEntryOnly; - // Common info for BTDM - BOOLEAN bBtDisabled; // BT is disabled - BOOLEAN bBtConnectProcess; // BT HS is under connection progress. - u8 btHsRssi; // BT HS mode wifi rssi value. - BOOLEAN bBtHsOperation; // BT HS mode is under progress - u8 btHsDigVal; // use BT rssi to decide the DIG value - BOOLEAN bBtDisableEdcaTurbo; // Under some condition, don't enable the EDCA Turbo - BOOLEAN bBtLimitedDig; // BT is busy. -//------------CALL BY VALUE-------------// + /* Common info for BTDM */ + BOOLEAN bBtDisabled; /* BT is disabled */ + BOOLEAN bBtConnectProcess; /* BT HS is under connection progress. */ + u8 btHsRssi; /* BT HS mode wifi rssi value. */ + BOOLEAN bBtHsOperation; /* BT HS mode is under progress */ + u8 btHsDigVal; /* use BT rssi to decide the DIG value */ + BOOLEAN bBtDisableEdcaTurbo; /* Under some condition, don't enable the EDCA Turbo */ + BOOLEAN bBtLimitedDig; /* BT is busy. */ +/* CALL BY VALUE------------- */ u8 RSSI_A; u8 RSSI_B; u64 RSSI_TRSW; @@ -1099,41 +1098,41 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure u32 Force_TH_L; u8 IGI_LowerBound; - //2 Define STA info. - // _ODM_STA_INFO - // 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? + /* 2 Define STA info. */ + /* _ODM_STA_INFO */ + /* 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */ PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; #if (RATE_ADAPTIVE_SUPPORT == 1) u16 CurrminRptTime; - ODM_RA_INFO_T RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119 + ODM_RA_INFO_T RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; /* Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} */ #endif - // - // 2012/02/14 MH Add to share 88E ra with other SW team. - // We need to colelct all support abilit to a proper area. - // + /* */ + /* 2012/02/14 MH Add to share 88E ra with other SW team. */ + /* We need to colelct all support abilit to a proper area. */ + /* */ BOOLEAN RaSupport88E; - // Define ........... + /* Define ........... */ - // Latest packet phy info (ODM write) + /* Latest packet phy info (ODM write) */ ODM_PHY_DBG_INFO_T PhyDbgInfo; - //PHY_INFO_88E PhyInfo; + /* PHY_INFO_88E PhyInfo; */ - // Latest packet phy info (ODM write) + /* Latest packet phy info (ODM write) */ ODM_MAC_INFO *pMacInfo; - //MAC_INFO_88E MacInfo; + /* MAC_INFO_88E MacInfo; */ - // Different Team independt structure?? + /* Different Team independt structure?? */ - // - //TX_RTP_CMN TX_retrpo; - //TX_RTP_88E TX_retrpo; - //TX_RTP_8195 TX_retrpo; + /* */ + /* TX_RTP_CMN TX_retrpo; */ + /* TX_RTP_88E TX_retrpo; */ + /* TX_RTP_8195 TX_retrpo; */ - // - //ODM Structure - // + /* */ + /* ODM Structure */ + /* */ FAT_T DM_FatTable; DIG_T DM_DigTable; PS_T DM_PSTable; @@ -1146,23 +1145,23 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure EDCA_T DM_EDCA_Table; u32 WMMEDCA_BE; - // Copy from SD4 structure - // - // ================================================== - // + /* Copy from SD4 structure */ + /* */ + /* ================================================== */ + /* */ BOOLEAN *pbDriverStopped; BOOLEAN *pbDriverIsGoingToPnpSetPowerSleep; BOOLEAN *pinit_adpt_in_progress; - //PSD + /* PSD */ BOOLEAN bUserAssignLevel; RT_TIMER PSDTimer; - u8 RSSI_BT; //come from BT + u8 RSSI_BT; /* come from BT */ BOOLEAN bPSDinProcess; BOOLEAN bDMInitialGainEnable; - //for rate adaptive, in fact, 88c/92c fw will handle this + /* for rate adaptive, in fact, 88c/92c fw will handle this */ u8 bUseRAMask; ODM_RATE_ADAPTIVE RateAdaptive; @@ -1170,9 +1169,9 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure ODM_RF_CAL_T RFCalibrateInfo; - // - // TX power tracking - // + /* */ + /* TX power tracking */ + /* */ u8 BbSwingIdxOfdm; u8 BbSwingIdxOfdmCurrent; u8 BbSwingIdxOfdmBase; @@ -1186,27 +1185,27 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure u8 *mp_mode; - // - // ODM system resource. - // + /* */ + /* ODM system resource. */ + /* */ - // ODM relative time. + /* ODM relative time. */ RT_TIMER PathDivSwitchTimer; - //2011.09.27 add for Path Diversity + /* 2011.09.27 add for Path Diversity */ RT_TIMER CCKPathDiversityTimer; RT_TIMER FastAntTrainingTimer; - // ODM relative workitem. -} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure + /* ODM relative workitem. */ +} DM_ODM_T, *PDM_ODM_T; /* DM_Dynamic_Mechanism_Structure */ #define ODM_RF_PATH_MAX 2 typedef enum _ODM_RF_RADIO_PATH { - ODM_RF_PATH_A = 0, //Radio Path A - ODM_RF_PATH_B = 1, //Radio Path B - ODM_RF_PATH_C = 2, //Radio Path C - ODM_RF_PATH_D = 3, //Radio Path D - // ODM_RF_PATH_MAX, //Max RF number 90 support + ODM_RF_PATH_A = 0, /* Radio Path A */ + ODM_RF_PATH_B = 1, /* Radio Path B */ + ODM_RF_PATH_C = 2, /* Radio Path C */ + ODM_RF_PATH_D = 3, /* Radio Path D */ + /* ODM_RF_PATH_MAX, Max RF number 90 support */ } ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E; typedef enum _ODM_RF_CONTENT{ @@ -1224,7 +1223,7 @@ typedef enum _ODM_BB_Config_Type{ CONFIG_BB_PHY_REG_PG, } ODM_BB_Config_Type, *PODM_BB_Config_Type; -// Status code +/* Status code */ typedef enum _RT_STATUS{ RT_STATUS_SUCCESS, RT_STATUS_FAILURE, @@ -1236,9 +1235,9 @@ typedef enum _RT_STATUS{ RT_STATUS_OS_API_FAILED, }RT_STATUS,*PRT_STATUS; -//3=========================================================== -//3 DIG -//3=========================================================== +/* 3=========================================================== */ +/* 3 DIG */ +/* 3=========================================================== */ typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition { @@ -1295,7 +1294,7 @@ typedef enum tag_DIG_Connect_Definition #define DMfalseALARM_THRESH_HIGH 1000 #define DM_DIG_MAX_NIC 0x4A -#define DM_DIG_MIN_NIC 0x1e //0x22//0x1c +#define DM_DIG_MIN_NIC 0x1e /* 0x22/0x1c */ #define DM_DIG_MAX_AP 0x32 #define DM_DIG_MIN_AP 0x20 @@ -1306,16 +1305,16 @@ typedef enum tag_DIG_Connect_Definition #define DM_DIG_MAX_AP_HP 0x42 #define DM_DIG_MIN_AP_HP 0x30 -//vivi 92c&92d has different definition, 20110504 -//this is for 92c +/* vivi 92c&92d has different definition, 20110504 */ +/* this is for 92c */ #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV -#define DM_DIG_FA_TH0 0x80//0x20 +#define DM_DIG_FA_TH0 0x80/* 0x20 */ #else -#define DM_DIG_FA_TH0 0x200//0x20 +#define DM_DIG_FA_TH0 0x200/* 0x20 */ #endif -#define DM_DIG_FA_TH1 0x300//0x100 -#define DM_DIG_FA_TH2 0x400//0x200 -//this is for 92d +#define DM_DIG_FA_TH1 0x300/* 0x100 */ +#define DM_DIG_FA_TH2 0x400/* 0x200 */ +/* this is for 92d */ #define DM_DIG_FA_TH0_92D 0x100 #define DM_DIG_FA_TH1_92D 0x400 #define DM_DIG_FA_TH2_92D 0x600 @@ -1324,9 +1323,9 @@ typedef enum tag_DIG_Connect_Definition #define DM_DIG_BACKOFF_MIN -4 #define DM_DIG_BACKOFF_DEFAULT 10 -//3=========================================================== -//3 AGC RX High Power Mode -//3=========================================================== +/* 3=========================================================== */ +/* 3 AGC RX High Power Mode */ +/* 3=========================================================== */ #define LNA_Low_Gain_1 0x64 #define LNA_Low_Gain_2 0x5A #define LNA_Low_Gain_3 0x58 @@ -1337,14 +1336,14 @@ typedef enum tag_DIG_Connect_Definition #define FA_RXHP_TH4 600 #define FA_RXHP_TH5 500 -//3=========================================================== -//3 EDCA -//3=========================================================== +/* 3=========================================================== */ +/* 3 EDCA */ +/* 3=========================================================== */ -//3=========================================================== -//3 Dynamic Tx Power -//3=========================================================== -//Dynamic Tx Power Control Threshold +/* 3=========================================================== */ +/* 3 Dynamic Tx Power */ +/* 3=========================================================== */ +/* Dynamic Tx Power Control Threshold */ #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 #define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F @@ -1360,21 +1359,21 @@ typedef enum tag_DIG_Connect_Definition #define TxHighPwrLevel_70 8 #define TxHighPwrLevel_100 9 -//3=========================================================== -//3 Tx Power Tracking -//3=========================================================== +/* 3=========================================================== */ +/* 3 Tx Power Tracking */ +/* 3=========================================================== */ -//3=========================================================== -//3 Rate Adaptive -//3=========================================================== +/* 3=========================================================== */ +/* 3 Rate Adaptive */ +/* 3=========================================================== */ #define DM_RATR_STA_INIT 0 #define DM_RATR_STA_HIGH 1 #define DM_RATR_STA_MIDDLE 2 #define DM_RATR_STA_LOW 3 -//3=========================================================== -//3 BB Power Save -//3=========================================================== +/* 3=========================================================== */ +/* 3 BB Power Save */ +/* 3=========================================================== */ typedef enum tag_1R_CCA_Type_Definition @@ -1391,9 +1390,9 @@ typedef enum tag_RF_Type_Definition RF_MAX = 2, }DM_RF_E; -//3=========================================================== -//3 Antenna Diversity -//3=========================================================== +/* 3=========================================================== */ +/* 3 Antenna Diversity */ +/* 3=========================================================== */ typedef enum tag_SW_Antenna_Switch_Definition { Antenna_A = 1, @@ -1402,12 +1401,12 @@ typedef enum tag_SW_Antenna_Switch_Definition }DM_SWAS_E; -// Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. +/* Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */ #define MAX_ANTENNA_DETECTION_CNT 10 -// -// Extern Global Variables. -// +/* */ +/* Extern Global Variables. */ +/* */ #define OFDM_TABLE_SIZE_92C 37 #define OFDM_TABLE_SIZE_92D 43 #define CCK_TABLE_SIZE 33 @@ -1418,16 +1417,16 @@ extern u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; -// -// check Sta pointer valid or not -// +/* */ +/* check Sta pointer valid or not */ +/* */ #define IS_STA_VALID(pSta) (pSta) -// 20100514 Joseph: Add definition for antenna switching test after link. -// This indicates two different the steps. -// In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. -// In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK -// with original RSSI to determine if it is necessary to switch antenna. +/* 20100514 Joseph: Add definition for antenna switching test after link. */ +/* This indicates two different the steps. */ +/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ +/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ +/* with original RSSI to determine if it is necessary to switch antenna. */ #define SWAW_STEP_PEAK 0 #define SWAW_STEP_DETERMINE 1 @@ -1491,7 +1490,7 @@ void ODM_DMInit(PDM_ODM_T pDM_Odm); void ODM_DMWatchdog( - PDM_ODM_T pDM_Odm // For common use in the future + PDM_ODM_T pDM_Odm /* For common use in the future */ ); void diff --git a/hal/odm_HWConfig.c b/hal/odm_HWConfig.c index 7204df2..7b116f6 100755 --- a/hal/odm_HWConfig.c +++ b/hal/odm_HWConfig.c @@ -18,9 +18,9 @@ * ******************************************************************************/ -//============================================================ -// include files -//============================================================ +/* */ +/* include files */ +/* */ #include "odm_precomp.h" @@ -60,10 +60,10 @@ odm_QueryRxPwrPercentage( } -// -// 2012/01/12 MH MOve some signal strength smooth method to MP HAL layer. -// IF other SW team do not support the feature, remove this section.?? -// +/* */ +/* 2012/01/12 MH MOve some signal strength smooth method to MP HAL layer. */ +/* IF other SW team do not support the feature, remove this section.?? */ +/* */ static s32 odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo( IN OUT PDM_ODM_T pDM_Odm, @@ -95,7 +95,7 @@ odm_SignalScaleMapping_92CSeries( #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) if(pDM_Odm->SupportInterface == ODM_ITRF_PCIE) { - // Step 1. Scale mapping. + /* Step 1. Scale mapping. */ if(CurrSig >= 61 && CurrSig <= 100) { RetSig = 90 + ((CurrSig - 60) / 4); @@ -185,14 +185,14 @@ odm_SignalScaleMapping( ) { if( (pDM_Odm->SupportPlatform == ODM_MP) && - (pDM_Odm->SupportInterface != ODM_ITRF_PCIE) && //USB & SDIO - (pDM_Odm->PatchID==10))//pMgntInfo->CustomerID == RT_CID_819x_Netcore + (pDM_Odm->SupportInterface != ODM_ITRF_PCIE) && /* USB & SDIO */ + (pDM_Odm->PatchID==10))/* pMgntInfo->CustomerID == RT_CID_819x_Netcore */ { return odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore(pDM_Odm,CurrSig); } else if( (pDM_Odm->SupportPlatform == ODM_MP) && (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) && - (pDM_Odm->PatchID==19))//pMgntInfo->CustomerID == RT_CID_819x_Lenovo) + (pDM_Odm->PatchID==19))/* pMgntInfo->CustomerID == RT_CID_819x_Lenovo) */ { return odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo(pDM_Odm, CurrSig); } @@ -202,7 +202,7 @@ odm_SignalScaleMapping( } -//pMgntInfo->CustomerID == RT_CID_819x_Lenovo +/* pMgntInfo->CustomerID == RT_CID_819x_Lenovo */ static u8 odm_SQ_process_patch_RT_CID_819x_Lenovo( IN PDM_ODM_T pDM_Odm, IN u8 isCCKrate, @@ -220,15 +220,15 @@ odm_EVMdbToPercentage( IN s8 Value ) { - // - // -33dB~0dB to 0%~99% - // + /* */ + /* -33dB~0dB to 0%~99% */ + /* */ s8 ret_val; ret_val = Value; - //ret_val /= 2; + /* ret_val /= 2; */ - //ODM_RTPRINT(FRX, RX_PHY_SQ, ("EVMdbToPercentage92C Value=%d / %x \n", ret_val, ret_val)); + /* ODM_RTPRINT(FRX, RX_PHY_SQ, ("EVMdbToPercentage92C Value=%d / %x \n", ret_val, ret_val)); */ if(ret_val >= 0) ret_val = 0; @@ -278,21 +278,21 @@ odm_RxPhyStatus92CSeries_Parsing( u8 cck_agc_rpt; pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK++; - // - // (1)Hardware does not provide RSSI for CCK - // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) - // + /* */ + /* (1)Hardware does not provide RSSI for CCK */ + /* (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) */ + /* */ - //if(pHalData->eRFPowerState == eRfOn) + /* if(pHalData->eRFPowerState == eRfOn) */ cck_highpwr = pDM_Odm->bCckHighPower; - //else - // cck_highpwr = FALSE; + /* else */ + /* cck_highpwr = FALSE; */ cck_agc_rpt = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a ; - //2011.11.28 LukeLee: 88E use different LNA & VGA gain table - //The RSSI formula should be modified according to the gain table - //In 88E, cck_highpwr is always set to 1 + /* 2011.11.28 LukeLee: 88E use different LNA & VGA gain table */ + /* The RSSI formula should be modified according to the gain table */ + /* In 88E, cck_highpwr is always set to 1 */ if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8812)) { LNA_idx = ((cck_agc_rpt & 0xE0) >>5); @@ -301,37 +301,35 @@ odm_RxPhyStatus92CSeries_Parsing( { case 7: if(VGA_idx <= 27) - rx_pwr_all = -100 + 2*(27-VGA_idx); //VGA_idx = 27~2 + rx_pwr_all = -100 + 2*(27-VGA_idx); /* VGA_idx = 27~2 */ else rx_pwr_all = -100; break; case 6: - rx_pwr_all = -48 + 2*(2-VGA_idx); //VGA_idx = 2~0 + rx_pwr_all = -48 + 2*(2-VGA_idx); /* VGA_idx = 2~0 */ break; case 5: - rx_pwr_all = -42 + 2*(7-VGA_idx); //VGA_idx = 7~5 + rx_pwr_all = -42 + 2*(7-VGA_idx); /* VGA_idx = 7~5 */ break; case 4: - rx_pwr_all = -36 + 2*(7-VGA_idx); //VGA_idx = 7~4 + rx_pwr_all = -36 + 2*(7-VGA_idx); /* VGA_idx = 7~4 */ break; case 3: - //rx_pwr_all = -28 + 2*(7-VGA_idx); //VGA_idx = 7~0 - rx_pwr_all = -24 + 2*(7-VGA_idx); //VGA_idx = 7~0 + rx_pwr_all = -24 + 2*(7-VGA_idx); /* VGA_idx = 7~0 */ break; case 2: if(cck_highpwr) - rx_pwr_all = -12 + 2*(5-VGA_idx); //VGA_idx = 5~0 + rx_pwr_all = -12 + 2*(5-VGA_idx); /* VGA_idx = 5~0 */ else rx_pwr_all = -6+ 2*(5-VGA_idx); break; case 1: - rx_pwr_all = 8-2*VGA_idx; + rx_pwr_all = 8-2*VGA_idx; break; case 0: - rx_pwr_all = 14-2*VGA_idx; + rx_pwr_all = 14-2*VGA_idx; break; default: - //DbgPrint("CCK Exception default\n"); break; } rx_pwr_all += 6; @@ -353,9 +351,9 @@ odm_RxPhyStatus92CSeries_Parsing( report =( cck_agc_rpt & 0xc0 )>>6; switch(report) { - // 03312009 modified by cosa - // Modify the RF RNA gain value to -40, -20, -2, 14 by Jenyu's suggestion - // Note: different RF with the different RNA gain. + /* 03312009 modified by cosa */ + /* Modify the RF RNA gain value to -40, -20, -2, 14 by Jenyu's suggestion */ + /* Note: different RF with the different RNA gain. */ case 0x3: rx_pwr_all = -46 - (cck_agc_rpt & 0x3e); break; @@ -372,8 +370,8 @@ odm_RxPhyStatus92CSeries_Parsing( } else { - //report = pDrvInfo->cfosho[0] & 0x60; - //report = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a& 0x60; + /* report = pDrvInfo->cfosho[0] & 0x60; */ + /* report = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a& 0x60; */ report = (cck_agc_rpt & 0x60)>>5; switch(report) @@ -395,7 +393,7 @@ odm_RxPhyStatus92CSeries_Parsing( PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); - //Modification for ext-LNA board + /* Modification for ext-LNA board */ if(pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA)) { if((cck_agc_rpt>>7) == 0){ @@ -409,13 +407,13 @@ odm_RxPhyStatus92CSeries_Parsing( PWDB_ALL = (PWDB_ALL<=16)?(PWDB_ALL>>2):(PWDB_ALL -12); } - //CCK modification + /* CCK modification */ if(PWDB_ALL > 25 && PWDB_ALL <= 60) PWDB_ALL += 6; - //else if (PWDB_ALL <= 25) - // PWDB_ALL += 8; + /* else if (PWDB_ALL <= 25) */ + /* PWDB_ALL += 8; */ } - else//Modification for int-LNA board + else/* Modification for int-LNA board */ { if(PWDB_ALL > 99) PWDB_ALL -= 8; @@ -427,14 +425,14 @@ odm_RxPhyStatus92CSeries_Parsing( pPhyInfo->RxPWDBAll = PWDB_ALL; pPhyInfo->BTRxRSSIPercentage = PWDB_ALL; pPhyInfo->RecvSignalPower = rx_pwr_all; - // - // (3) Get Signal Quality (EVM) - // + /* */ + /* (3) Get Signal Quality (EVM) */ + /* */ if(pPktinfo->bPacketMatchBSSID) { u8 SQ,SQ_rpt; - if((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)){//pMgntInfo->CustomerID == RT_CID_819x_Lenovo + if((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)){/* pMgntInfo->CustomerID == RT_CID_819x_Lenovo */ SQ = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm,isCCKrate,PWDB_ALL,0,0); } else if(pPhyInfo->RxPWDBAll > 40 && !pDM_Odm->bInHctTest){ @@ -452,27 +450,27 @@ odm_RxPhyStatus92CSeries_Parsing( } - //DbgPrint("cck SQ = %d\n", SQ); + /* DbgPrint("cck SQ = %d\n", SQ); */ pPhyInfo->SignalQuality = SQ; pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = SQ; pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1; } } - else //is OFDM rate + else /* is OFDM rate */ { pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++; - // - // (1)Get RSSI for HT rate - // + /* */ + /* (1)Get RSSI for HT rate */ + /* */ for(i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) { - // 2008/01/30 MH we will judge RF RX path now. + /* 2008/01/30 MH we will judge RF RX path now. */ if (pDM_Odm->RFPathRxEnable & BIT(i)) rf_rx_num++; - //else - //continue; + /* else */ + /* continue; */ rx_pwr[i] = ((pPhyStaRpt->path_agc[i].gain& 0x3F)*2) - 110; @@ -481,9 +479,9 @@ odm_RxPhyStatus92CSeries_Parsing( /* Translate DBM to percentage. */ RSSI = odm_QueryRxPwrPercentage(rx_pwr[i]); total_rssi += RSSI; - //RTPRINT(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI)); + /* RTPRINT(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI)); */ - //Modification for ext-LNA board + /* Modification for ext-LNA board */ if(pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA)) { if((pPhyStaRpt->path_agc[i].trsw) == 1) @@ -497,7 +495,7 @@ odm_RxPhyStatus92CSeries_Parsing( pPhyInfo->RxMIMOSignalStrength[i] =(u8) RSSI; - //Get Rx snr value in DB + /* Get Rx snr value in DB */ pPhyInfo->RxSNR[i] = pDM_Odm->PhyDbgInfo.RxSNRdB[i] = (s32)(pPhyStaRpt->path_rxsnr[i]/2); /* Record Signal Strength for next packet */ @@ -514,9 +512,9 @@ odm_RxPhyStatus92CSeries_Parsing( } - // - // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) - // + /* */ + /* (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) */ + /* */ rx_pwr_all = (((pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all) >> 1 )& 0x7f) -110; PWDB_ALL_BT = PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); @@ -527,28 +525,28 @@ odm_RxPhyStatus92CSeries_Parsing( pPhyInfo->RecvSignalPower = rx_pwr_all; if((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)){ - //do nothing - } else{//pMgntInfo->CustomerID != RT_CID_819x_Lenovo - // - // (3)EVM of HT rate - // + /* do nothing */ + } else{/* pMgntInfo->CustomerID != RT_CID_819x_Lenovo */ + /* */ + /* (3)EVM of HT rate */ + /* */ if(pPktinfo->Rate >=DESC92C_RATEMCS8 && pPktinfo->Rate <=DESC92C_RATEMCS15) - Max_spatial_stream = 2; //both spatial stream make sense + Max_spatial_stream = 2; /* both spatial stream make sense */ else - Max_spatial_stream = 1; //only spatial stream 1 makes sense + Max_spatial_stream = 1; /* only spatial stream 1 makes sense */ for(i=0; i>= 1" because the compilor of free build environment - // fill most significant bit to "zero" when doing shifting operation which may change a negative - // value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. - EVM = odm_EVMdbToPercentage( (pPhyStaRpt->stream_rxevm[i] )); //dbm + /* Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment */ + /* fill most significant bit to "zero" when doing shifting operation which may change a negative */ + /* value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. */ + EVM = odm_EVMdbToPercentage( (pPhyStaRpt->stream_rxevm[i] )); /* dbm */ - //RTPRINT(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n", - //GET_RX_STATUS_DESC_RX_MCS(pDesc), pDrvInfo->rxevm[i], "%", EVM)); + /* RTPRINT(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n", */ + /* GET_RX_STATUS_DESC_RX_MCS(pDesc), pDrvInfo->rxevm[i], "%", EVM)); */ if(pPktinfo->bPacketMatchBSSID) { - if(i==ODM_RF_PATH_A) // Fill value in RFD, Get the first spatial stream only + if(i==ODM_RF_PATH_A) /* Fill value in RFD, Get the first spatial stream only */ { pPhyInfo->SignalQuality = (u8)(EVM & 0xff); } @@ -558,11 +556,11 @@ odm_RxPhyStatus92CSeries_Parsing( } } - //UI BSS List signal strength(in percentage), make it good looking, from 0~100. - //It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). + /* UI BSS List signal strength(in percentage), make it good looking, from 0~100. */ + /* It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). */ if(isCCKrate) { - pPhyInfo->SignalStrength = (u8)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));//PWDB_ALL; + pPhyInfo->SignalStrength = (u8)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));/* PWDB_ALL; */ } else { @@ -572,10 +570,10 @@ odm_RxPhyStatus92CSeries_Parsing( } } - //For 92C/92D HW (Hybrid) Antenna Diversity + /* For 92C/92D HW (Hybrid) Antenna Diversity */ #if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) pDM_SWAT_Table->antsel = pPhyStaRpt->ant_sel; - //For 88E HW Antenna Diversity + /* For 88E HW Antenna Diversity */ pDM_Odm->DM_FatTable.antsel_rx_keep_0 = pPhyStaRpt->ant_sel; pDM_Odm->DM_FatTable.antsel_rx_keep_1 = pPhyStaRpt->ant_sel_b; pDM_Odm->DM_FatTable.antsel_rx_keep_2 = pPhyStaRpt->antsel_rx_keep_2; @@ -609,8 +607,8 @@ odm_Process_RSSIForDM( if(pPktinfo->StationID == 0xFF) return; - // 2011/11/17 MH Need to debug - //if (pDM_Odm->SupportPlatform == ODM_MP) + /* 2011/11/17 MH Need to debug */ + /* if (pDM_Odm->SupportPlatform == ODM_MP) */ { } @@ -630,7 +628,7 @@ odm_Process_RSSIForDM( pDM_Odm->RxRate = pPktinfo->Rate; #if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) - //-----------------Smart Antenna Debug Message------------------// + /* Smart Antenna Debug Message------------------ */ if(pDM_Odm->SupportICType == ODM_RTL8188E) { u8 antsel_tr_mux; @@ -640,33 +638,23 @@ odm_Process_RSSIForDM( { if(pDM_FatTable->FAT_State == FAT_TRAINING_STATE) { - if(pPktinfo->bPacketToSelf) //(pPktinfo->bPacketMatchBSSID && (!pPktinfo->bPacketBeacon)) + if(pPktinfo->bPacketToSelf) /* pPktinfo->bPacketMatchBSSID && (!pPktinfo->bPacketBeacon)) */ { antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2<<2) |(pDM_FatTable->antsel_rx_keep_1 <<1) |pDM_FatTable->antsel_rx_keep_0; pDM_FatTable->antSumRSSI[antsel_tr_mux] += pPhyInfo->RxPWDBAll; pDM_FatTable->antRSSIcnt[antsel_tr_mux]++; - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("isCCKrate=%d, PWDB_ALL=%d\n",isCCKrate, pPhyInfo->RxPWDBAll)); - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n", - //pDM_FatTable->antsel_rx_keep_2, pDM_FatTable->antsel_rx_keep_1, pDM_FatTable->antsel_rx_keep_0)); - } } - } - else if((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)) - { - if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) - { + } else if((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)) { + if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) { antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2<<2) |(pDM_FatTable->antsel_rx_keep_1 <<1) |pDM_FatTable->antsel_rx_keep_0; - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n", - // pDM_FatTable->antsel_rx_keep_2, pDM_FatTable->antsel_rx_keep_1, pDM_FatTable->antsel_rx_keep_0)); - ODM_AntselStatistics_88E(pDM_Odm, antsel_tr_mux, pPktinfo->StationID, pPhyInfo->RxPWDBAll); } } } -#endif //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) - //-----------------Smart Antenna Debug Message------------------// +#endif /* if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) */ + /* Smart Antenna Debug Message------------------ */ UndecoratedSmoothedCCK = pEntry->rssi_stat.UndecoratedSmoothedCCK; UndecoratedSmoothedOFDM = pEntry->rssi_stat.UndecoratedSmoothedOFDM; @@ -675,7 +663,7 @@ odm_Process_RSSIForDM( if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) { - if(!isCCKrate)//ofdm rate + if(!isCCKrate)/* ofdm rate */ { if(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B] == 0){ RSSI_Ave = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; @@ -684,8 +672,8 @@ odm_Process_RSSIForDM( } else { - //DbgPrint("pRfd->Status.RxMIMOSignalStrength[0] = %d, pRfd->Status.RxMIMOSignalStrength[1] = %d \n", - //pRfd->Status.RxMIMOSignalStrength[0], pRfd->Status.RxMIMOSignalStrength[1]); + /* DbgPrint("pRfd->Status.RxMIMOSignalStrength[0] = %d, pRfd->Status.RxMIMOSignalStrength[1] = %d \n", */ + /* pRfd->Status.RxMIMOSignalStrength[0], pRfd->Status.RxMIMOSignalStrength[1]); */ pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; pDM_Odm->RSSI_B = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; @@ -709,8 +697,8 @@ odm_Process_RSSIForDM( RSSI_Ave = RSSI_max - 3; } - //1 Process OFDM RSSI - if(UndecoratedSmoothedOFDM <= 0) // initialize + /* 1 Process OFDM RSSI */ + if(UndecoratedSmoothedOFDM <= 0) /* initialize */ { UndecoratedSmoothedOFDM = pPhyInfo->RxPWDBAll; } @@ -740,8 +728,8 @@ odm_Process_RSSIForDM( pDM_Odm->RSSI_A = (u8) pPhyInfo->RxPWDBAll; pDM_Odm->RSSI_B = 0xFF; - //1 Process CCK RSSI - if(UndecoratedSmoothedCCK <= 0) // initialize + /* 1 Process CCK RSSI */ + if(UndecoratedSmoothedCCK <= 0) /* initialize */ { UndecoratedSmoothedCCK = pPhyInfo->RxPWDBAll; } @@ -764,9 +752,9 @@ odm_Process_RSSIForDM( pEntry->rssi_stat.PacketMap = pEntry->rssi_stat.PacketMap<<1; } - //if(pEntry) + /* if(pEntry) */ { - //2011.07.28 LukeLee: modified to prevent unstable CCK RSSI + /* 2011.07.28 LukeLee: modified to prevent unstable CCK RSSI */ if(pEntry->rssi_stat.ValidBit >= 64) pEntry->rssi_stat.ValidBit = 64; else @@ -792,18 +780,18 @@ odm_Process_RSSIForDM( pEntry->rssi_stat.UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM; pEntry->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; - //DbgPrint("OFDM_pkt=%d, Weighting=%d\n", OFDM_pkt, Weighting); - //DbgPrint("UndecoratedSmoothedOFDM=%d, UndecoratedSmoothedPWDB=%d, UndecoratedSmoothedCCK=%d\n", - // UndecoratedSmoothedOFDM, UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK); + /* DbgPrint("OFDM_pkt=%d, Weighting=%d\n", OFDM_pkt, Weighting); */ + /* DbgPrint("UndecoratedSmoothedOFDM=%d, UndecoratedSmoothedPWDB=%d, UndecoratedSmoothedCCK=%d\n", */ + /* UndecoratedSmoothedOFDM, UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK); */ } } } -// -// Endianness before calling this API -// +/* */ +/* Endianness before calling this API */ +/* */ static void ODM_PhyStatusQuery_92CSeries( IN OUT PDM_ODM_T pDM_Odm, @@ -820,7 +808,7 @@ ODM_PhyStatusQuery_92CSeries( pPktinfo); if( pDM_Odm->RSSI_test == TRUE) { - // Select the packets to do RSSI checking for antenna switching. + /* Select the packets to do RSSI checking for antenna switching. */ if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon ) ODM_SwAntDivChkPerPktRssi(pDM_Odm,pPktinfo->StationID,pPhyInfo); } else { @@ -829,9 +817,9 @@ ODM_PhyStatusQuery_92CSeries( } -// -// Endianness before calling this API -// +/* */ +/* Endianness before calling this API */ +/* */ static void ODM_PhyStatusQuery_JaguarSeries( IN OUT PDM_ODM_T pDM_Odm, @@ -855,7 +843,7 @@ ODM_PhyStatusQuery( ODM_PhyStatusQuery_92CSeries(pDM_Odm,pPhyInfo,pPhyStatus,pPktinfo); } -// For future use. +/* For future use. */ void ODM_MacStatusQuery( IN OUT PDM_ODM_T pDM_Odm, @@ -866,7 +854,7 @@ ODM_MacStatusQuery( IN BOOLEAN bPacketBeacon ) { - // 2011/10/19 Driver team will handle in the future. + /* 2011/10/19 Driver team will handle in the future. */ } @@ -877,7 +865,7 @@ ODM_ConfigRFWithHeaderFile( IN ODM_RF_RADIO_PATH_E eRFPath ) { - //RT_STATUS rtStatus = RT_STATUS_SUCCESS; + /* RT_STATUS rtStatus = RT_STATUS_SUCCESS; */ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===>ODM_ConfigRFWithHeaderFile\n")); @@ -894,7 +882,6 @@ ODM_ConfigRFWithHeaderFile( } ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("ODM_ConfigRFWithHeaderFile: Radio No %x\n", eRFPath)); - //rtStatus = RT_STATUS_SUCCESS; return HAL_STATUS_SUCCESS; } diff --git a/hal/odm_HWConfig.h b/hal/odm_HWConfig.h index 6e29935..7937aee 100755 --- a/hal/odm_HWConfig.h +++ b/hal/odm_HWConfig.h @@ -22,18 +22,18 @@ #ifndef __HALHWOUTSRC_H__ #define __HALHWOUTSRC_H__ -//============================================================ -// Definition -//============================================================ -// -//----------------------------------------------------------- -// CCK Rates, TxHT = 0 +/* */ +/* Definition */ +/* */ +/* */ +/* */ +/* CCK Rates, TxHT = 0 */ #define DESC92C_RATE1M 0x00 #define DESC92C_RATE2M 0x01 #define DESC92C_RATE5_5M 0x02 #define DESC92C_RATE11M 0x03 -// OFDM Rates, TxHT = 0 +/* OFDM Rates, TxHT = 0 */ #define DESC92C_RATE6M 0x04 #define DESC92C_RATE9M 0x05 #define DESC92C_RATE12M 0x06 @@ -43,7 +43,7 @@ #define DESC92C_RATE48M 0x0a #define DESC92C_RATE54M 0x0b -// MCS Rates, TxHT = 1 +/* MCS Rates, TxHT = 1 */ #define DESC92C_RATEMCS0 0x0c #define DESC92C_RATEMCS1 0x0d #define DESC92C_RATEMCS2 0x0e @@ -64,9 +64,9 @@ #define DESC92C_RATEMCS32 0x20 -//============================================================ -// structure and define -//============================================================ +/* */ +/* structure and define */ +/* */ typedef struct _Phy_Rx_AGC_Info { @@ -84,7 +84,7 @@ typedef struct _Phy_Status_Rpt_8192cd u8 cck_sig_qual_ofdm_pwdb_all; u8 cck_agc_rpt_ofdm_cfosho_a; u8 cck_rpt_b_ofdm_cfosho_b; - u8 rsvd_1;//ch_corr_msb; + u8 rsvd_1;/* ch_corr_msb; */ u8 noise_power_db_msb; u8 path_cfotail[2]; u8 pcts_mask[2]; @@ -98,21 +98,21 @@ typedef struct _Phy_Status_Rpt_8192cd u8 rsvd_3; #ifdef __LITTLE_ENDIAN - u8 antsel_rx_keep_2:1; //ex_intf_flg:1; + u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ u8 sgi_en:1; u8 rxsc:2; u8 idle_long:1; u8 r_ant_train_en:1; u8 ant_sel_b:1; u8 ant_sel:1; -#else // _BIG_ENDIAN_ +#else /* _BIG_ENDIAN_ */ u8 ant_sel:1; u8 ant_sel_b:1; u8 r_ant_train_en:1; u8 idle_long:1; u8 rxsc:2; u8 sgi_en:1; - u8 antsel_rx_keep_2:1; //ex_intf_flg:1; + u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ #endif } PHY_STATUS_RPT_8192CD_T,*PPHY_STATUS_RPT_8192CD_T; @@ -124,7 +124,7 @@ typedef struct _Phy_Status_Rpt_8195 u8 cck_sig_qual_ofdm_pwdb_all; u8 cck_agc_rpt_ofdm_cfosho_a; u8 cck_bb_pwr_ofdm_cfosho_b; - u8 cck_rx_path; //CCK_RX_PATH [3:0] (with regA07[3:0] definition) + u8 cck_rx_path; /* CCK_RX_PATH [3:0] (with regA07[3:0] definition) */ u8 rsvd_1; u8 path_cfotail[2]; u8 pcts_mask[2]; @@ -140,7 +140,7 @@ typedef struct _Phy_Status_Rpt_8195 u8 antidx_anta:3; u8 antidx_antb:3; u8 rsvd_5:2; -#else // _BIG_ENDIAN_ +#else /* _BIG_ENDIAN_ */ u8 rsvd_5:2; u8 antidx_antb:3; u8 antidx_anta:3; diff --git a/hal/odm_RTL8188E.c b/hal/odm_RTL8188E.c index 5467d00..f93297d 100755 --- a/hal/odm_RTL8188E.c +++ b/hal/odm_RTL8188E.c @@ -18,9 +18,9 @@ * ******************************************************************************/ -//============================================================ -// include files -//============================================================ +/* */ +/* include files */ +/* */ #include "odm_precomp.h" @@ -36,7 +36,7 @@ ODM_DIG_LowerBound_88E( pDM_DigTable->rx_gain_range_min = (u8) pDM_DigTable->AntDiv_RSSI_max; ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_DIG_LowerBound_88E(): pDM_DigTable->AntDiv_RSSI_max=%d \n",pDM_DigTable->AntDiv_RSSI_max)); } - //If only one Entry connected + /* If only one Entry connected */ @@ -54,31 +54,31 @@ odm_RX_HWAntDivInit( if (*(pDM_Odm->mp_mode) == 1) { pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV; - ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv - ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); // 1:CG, 0:CS + ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); /* disable HW AntDiv */ + ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); /* 1:CG, 0:CS */ return; } #endif ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_RX_HWAntDivInit() \n")); - //MAC Setting + /* MAC Setting */ value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); - ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output - //Pin Settings - ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW - ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1); //Regb2c[22]=1'b0 //disable CS/CG switch - ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only - //OFDM Settings + ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ + /* Pin Settings */ + ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0antsel antselb by HW */ + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */ + ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1); /* Regb2c[22]=1'b0 disable CS/CG switch */ + ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */ + /* OFDM Settings */ ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0); - //CCK Settings - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples + /* CCK Settings */ + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); /* Fix CCK PHY status report issue */ + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); /* CCK complete HW AntDiv within 64 samples */ ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT); - ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0201); //antenna mapping table + ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0201); /* antenna mapping table */ - //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //Enable HW AntDiv - //ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); //Enable CCK AntDiv + /* ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); Enable HW AntDiv */ + /* ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); Enable CCK AntDiv */ } static void @@ -93,8 +93,8 @@ odm_TRX_HWAntDivInit( if (*(pDM_Odm->mp_mode) == 1) { pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV; - ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); //Default RX (0/1) + ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); /* disable HW AntDiv */ + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); /* Default RX (0/1) */ return; } @@ -102,34 +102,34 @@ odm_TRX_HWAntDivInit( ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_TRX_HWAntDivInit() \n")); - //MAC Setting + /* MAC Setting */ value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); - ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output - //Pin Settings - ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW - ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch - ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only - //OFDM Settings + ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ + /* Pin Settings */ + ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */ + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */ + ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0); /* Regb2c[22]=1'b0 disable CS/CG switch */ + ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */ + /* OFDM Settings */ ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0); - //CCK Settings - ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples - //Tx Settings - ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from TX Reg + /* CCK Settings */ + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); /* Fix CCK PHY status report issue */ + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); /* CCK complete HW AntDiv within 64 samples */ + /* Tx Settings */ + ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); /* Reg80c[21]=1'b0 from TX Reg */ ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT); - //antenna mapping table - if(!pDM_Odm->bIsMPChip) //testchip + /* antenna mapping table */ + if(!pDM_Odm->bIsMPChip) /* testchip */ { - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001 - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010 + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); /* Reg858[10:8]=3'b001 */ + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); /* Reg858[13:11]=3'b010 */ } - else //MPchip - ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); //Reg914=3'b010, Reg915=3'b001 + else /* MPchip */ + ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); /* Reg914=3'b010, Reg915=3'b001 */ - //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //Enable HW AntDiv - //ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); //Enable CCK AntDiv + /* ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); Enable HW AntDiv */ + /* ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); Enable CCK AntDiv */ } void @@ -161,33 +161,33 @@ odm_FastAntTrainingInit( pDM_FatTable->TrainIdx = 0; pDM_FatTable->FAT_State = FAT_NORMAL_STATE; - //MAC Setting + /* MAC Setting */ value32 = ODM_GetMACReg(pDM_Odm, 0x4c, bMaskDWord); - ODM_SetMACReg(pDM_Odm, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output + ODM_SetMACReg(pDM_Odm, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ value32 = ODM_GetMACReg(pDM_Odm, 0x7B4, bMaskDWord); - ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); //Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match - //value32 = PlatformEFIORead4Byte(Adapter, 0x7B4); - //PlatformEFIOWrite4Byte(Adapter, 0x7b4, value32|BIT18); //append MACID in reponse packet + ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */ + /* value32 = PlatformEFIORead4Byte(Adapter, 0x7B4); */ + /* PlatformEFIOWrite4Byte(Adapter, 0x7b4, value32|BIT18); append MACID in reponse packet */ - //Match MAC ADDR + /* Match MAC ADDR */ ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, 0); ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, 0); - ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW - ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW - ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch - ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only + ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */ + ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */ + ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0); /* Regb2c[22]=1'b0 disable CS/CG switch */ + ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */ ODM_SetBBReg(pDM_Odm, 0xca4 , bMaskDWord, 0x000000a0); - //antenna mapping table + /* antenna mapping table */ if(AntCombination == 2) { - if(!pDM_Odm->bIsMPChip) //testchip + if(!pDM_Odm->bIsMPChip) /* testchip */ { - ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001 - ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010 + ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1); /* Reg858[10:8]=3'b001 */ + ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 2); /* Reg858[13:11]=3'b010 */ } - else //MPchip + else /* MPchip */ { ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 1); ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2); @@ -195,19 +195,19 @@ odm_FastAntTrainingInit( } else if(AntCombination == 7) { - if(!pDM_Odm->bIsMPChip) //testchip + if(!pDM_Odm->bIsMPChip) /* testchip */ { - ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); //Reg858[10:8]=3'b000 - ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 1); //Reg858[13:11]=3'b001 + ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); /* Reg858[10:8]=3'b000 */ + ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 1); /* Reg858[13:11]=3'b001 */ ODM_SetBBReg(pDM_Odm, 0x878 , BIT16, 0); - ODM_SetBBReg(pDM_Odm, 0x858 , BIT15|BIT14, 2); //(Reg878[0],Reg858[14:15])=3'b010 - ODM_SetBBReg(pDM_Odm, 0x878 , BIT19|BIT18|BIT17, 3);//Reg878[3:1]=3b'011 - ODM_SetBBReg(pDM_Odm, 0x878 , BIT22|BIT21|BIT20, 4);//Reg878[6:4]=3b'100 - ODM_SetBBReg(pDM_Odm, 0x878 , BIT25|BIT24|BIT23, 5);//Reg878[9:7]=3b'101 - ODM_SetBBReg(pDM_Odm, 0x878 , BIT28|BIT27|BIT26, 6);//Reg878[12:10]=3b'110 - ODM_SetBBReg(pDM_Odm, 0x878 , BIT31|BIT30|BIT29, 7);//Reg878[15:13]=3b'111 + ODM_SetBBReg(pDM_Odm, 0x858 , BIT15|BIT14, 2); /* Reg878[0],Reg858[14:15])=3'b010 */ + ODM_SetBBReg(pDM_Odm, 0x878 , BIT19|BIT18|BIT17, 3);/* Reg878[3:1]=3b'011 */ + ODM_SetBBReg(pDM_Odm, 0x878 , BIT22|BIT21|BIT20, 4);/* Reg878[6:4]=3b'100 */ + ODM_SetBBReg(pDM_Odm, 0x878 , BIT25|BIT24|BIT23, 5);/* Reg878[9:7]=3b'101 */ + ODM_SetBBReg(pDM_Odm, 0x878 , BIT28|BIT27|BIT26, 6);/* Reg878[12:10]=3b'110 */ + ODM_SetBBReg(pDM_Odm, 0x878 , BIT31|BIT30|BIT29, 7);/* Reg878[15:13]=3b'111 */ } - else //MPchip + else /* MPchip */ { ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0); ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1); @@ -220,27 +220,22 @@ odm_FastAntTrainingInit( } } - //Default Ant Setting when no fast training - ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info - ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0); //Default RX - ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1); //Optional RX - //ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, 1); //Default TX + /* Default Ant Setting when no fast training */ + ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); /* Reg80c[21]=1'b1 from TX Info */ + ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0); /* Default RX */ + ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1); /* Optional RX */ - //Enter Traing state - ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, (AntCombination-1)); //Reg864[2:0]=3'd6 //ant combination=reg864[2:0]+1 - //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv - //ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training - //ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1); //RegE08[16]=1'b1 //enable fast training - ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv + /* Enter Traing state */ + ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, (AntCombination-1)); /* Reg864[2:0]=3'd6 ant combination=reg864[2:0]+1 */ + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); /* RegC50[7]=1'b1 enable HW AntDiv */ - - //SW Control - //PHY_SetBBReg(Adapter, 0x864 , BIT10, 1); - //PHY_SetBBReg(Adapter, 0x870 , BIT9, 1); - //PHY_SetBBReg(Adapter, 0x870 , BIT8, 1); - //PHY_SetBBReg(Adapter, 0x864 , BIT11, 1); - //PHY_SetBBReg(Adapter, 0x860 , BIT9, 0); - //PHY_SetBBReg(Adapter, 0x860 , BIT8, 0); + /* SW Control */ + /* PHY_SetBBReg(Adapter, 0x864 , BIT10, 1); */ + /* PHY_SetBBReg(Adapter, 0x870 , BIT9, 1); */ + /* PHY_SetBBReg(Adapter, 0x870 , BIT8, 1); */ + /* PHY_SetBBReg(Adapter, 0x864 , BIT11, 1); */ + /* PHY_SetBBReg(Adapter, 0x860 , BIT9, 0); */ + /* PHY_SetBBReg(Adapter, 0x860 , BIT8, 0); */ } void @@ -248,20 +243,11 @@ ODM_AntennaDiversityInit_88E( IN PDM_ODM_T pDM_Odm ) { -/* - //2012.03.27 LukeLee: For temp use, should be removed later - //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; - //{ - struct adapter * Adapter = pDM_Odm->Adapter; - HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter); - //pHalData->AntDivCfg = 1; - //} -*/ if(pDM_Odm->SupportICType != ODM_RTL8188E) return; - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d, pHalData->AntDivCfg=%d\n", - // pDM_Odm->AntDivType, pHalData->AntDivCfg)); + /* ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d, pHalData->AntDivCfg=%d\n", */ + /* pDM_Odm->AntDivType, pHalData->AntDivCfg)); */ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d\n",pDM_Odm->AntDivType)); ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->bIsMPChip=%s\n",(pDM_Odm->bIsMPChip?"TRUE":"FALSE"))); @@ -296,16 +282,16 @@ ODM_UpdateRxIdleAnt_88E(IN PDM_ODM_T pDM_Odm, IN u8 Ant) if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) { - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); //Default RX - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX - ODM_SetBBReg(pDM_Odm, ODM_REG_ANTSEL_CTRL_11N , BIT14|BIT13|BIT12, DefaultAnt); //Default TX - ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11N , BIT6|BIT7, DefaultAnt); //Resp Tx + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); /* Default RX */ + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); /* Optional RX */ + ODM_SetBBReg(pDM_Odm, ODM_REG_ANTSEL_CTRL_11N , BIT14|BIT13|BIT12, DefaultAnt); /* Default TX */ + ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11N , BIT6|BIT7, DefaultAnt); /* Resp Tx */ } else if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) { - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); //Default RX - ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); /* Default RX */ + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); /* Optional RX */ } } pDM_FatTable->RxIdleAnt = Ant; @@ -349,8 +335,8 @@ ODM_SetTxAntByTxInfo_88E( SET_TX_DESC_ANTSEL_A_88E(pDesc, pDM_FatTable->antsel_a[macId]); SET_TX_DESC_ANTSEL_B_88E(pDesc, pDM_FatTable->antsel_b[macId]); SET_TX_DESC_ANTSEL_C_88E(pDesc, pDM_FatTable->antsel_c[macId]); - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SetTxAntByTxInfo_88E_WIN(): MacID=%d, antsel_tr_mux=3'b%d%d%d\n", - // macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId])); + /* ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SetTxAntByTxInfo_88E_WIN(): MacID=%d, antsel_tr_mux=3'b%d%d%d\n", */ + /* macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId])); */ } } @@ -415,7 +401,7 @@ odm_HWAntDiv( pEntry = pDM_Odm->pODM_StaInfo[i]; if(IS_STA_VALID(pEntry)) { - //2 Caculate RSSI per Antenna + /* 2 Caculate RSSI per Antenna */ Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0; Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0; TargetAnt = (Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT; @@ -423,14 +409,14 @@ odm_HWAntDiv( ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, AuxAnt_Sum=%d, AuxAnt_Cnt=%d\n",i, pDM_FatTable->AuxAnt_Sum[i], pDM_FatTable->AuxAnt_Cnt[i])); ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, Main_RSSI= %d, Aux_RSSI= %d\n", i, Main_RSSI, Aux_RSSI)); - //2 Select MaxRSSI for DIG + /* 2 Select MaxRSSI for DIG */ LocalMaxRSSI = (Main_RSSI>Aux_RSSI)?Main_RSSI:Aux_RSSI; if((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40)) AntDivMaxRSSI = LocalMaxRSSI; if(LocalMaxRSSI > MaxRSSI) MaxRSSI = LocalMaxRSSI; - //2 Select RX Idle Antenna + /* 2 Select RX Idle Antenna */ if((pDM_FatTable->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0)) Main_RSSI = Aux_RSSI; else if((pDM_FatTable->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0)) @@ -445,7 +431,7 @@ odm_HWAntDiv( #if TX_BY_REG #else - //2 Select TRX Antenna + /* 2 Select TRX Antenna */ if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) odm_UpdateTxAnt_88E(pDM_Odm, TargetAnt, i); #endif @@ -456,7 +442,7 @@ odm_HWAntDiv( pDM_FatTable->AuxAnt_Cnt[i] = 0; } - //2 Set RX Idle Antenna + /* 2 Set RX Idle Antenna */ ODM_UpdateRxIdleAnt_88E(pDM_Odm, RxIdleAnt); pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI; @@ -471,7 +457,7 @@ ODM_AntennaDiversity_88E( pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; if((pDM_Odm->SupportICType != ODM_RTL8188E) || (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))) { - //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E: Not Support 88E AntDiv\n")); + /* ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E: Not Support 88E AntDiv\n")); */ return; } #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV @@ -512,29 +498,24 @@ ODM_AntennaDiversity_88E( if(pDM_FatTable->bBecomeLinked == TRUE) { ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn off HW AntDiv\n")); - ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); //RegC50[7]=1'b1 //enable HW AntDiv - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 0); //Enable CCK AntDiv + ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); /* RegC50[7]=1'b1 enable HW AntDiv */ + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 0); /* Enable CCK AntDiv */ if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) - ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from TX Reg + ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); /* Reg80c[21]=1'b0 from TX Reg */ pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; } return; - } - else - { - if(pDM_FatTable->bBecomeLinked ==FALSE) - { + } else { + if(pDM_FatTable->bBecomeLinked ==FALSE) { ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn on HW AntDiv\n")); - //Because HW AntDiv is disabled before Link, we enable HW AntDiv after link - ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv - ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 1); //Enable CCK AntDiv - //ODM_SetMACReg(pDM_Odm, 0x7B4 , BIT18, 1); //Response Tx by current HW antdiv - if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) - { + /* Because HW AntDiv is disabled before Link, we enable HW AntDiv after link */ + ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 1); /* RegC50[7]=1'b1 enable HW AntDiv */ + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 1); /* Enable CCK AntDiv */ + if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) { #if TX_BY_REG - ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from Reg + ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); /* Reg80c[21]=1'b0 from Reg */ #else - ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info + ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 1); /* Reg80c[21]=1'b1 from TX Info */ #endif } pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; @@ -548,7 +529,7 @@ ODM_AntennaDiversity_88E( } -#else //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) +#else /* if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) */ void ODM_SetTxAntByTxInfo_88E( IN PDM_ODM_T pDM_Odm, @@ -557,10 +538,10 @@ ODM_SetTxAntByTxInfo_88E( ) { } -#endif //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) -//3============================================================ -//3 Dynamic Primary CCA -//3============================================================ +#endif /* if(defined(CONFIG_HW_ANTENNA_DIVERSITY)) */ +/* 3============================================================ */ +/* 3 Dynamic Primary CCA */ +/* 3============================================================ */ void odm_PrimaryCCA_Init( @@ -589,14 +570,14 @@ odm_DynamicPrimaryCCA( IN PDM_ODM_T pDM_Odm ) { - struct adapter *Adapter = pDM_Odm->Adapter; // for NIC - prtl8192cd_priv priv = pDM_Odm->priv; // for AP + struct adapter *Adapter = pDM_Odm->Adapter; /* for NIC */ + prtl8192cd_priv priv = pDM_Odm->priv; /* for AP */ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA); BOOLEAN Is40MHz; - BOOLEAN Client_40MHz = FALSE, Client_tmp = FALSE; // connected client BW - BOOLEAN bConnected = FALSE; // connected or not + BOOLEAN Client_40MHz = FALSE, Client_tmp = FALSE; /* connected client BW */ + BOOLEAN bConnected = FALSE; /* connected or not */ static u8 Client_40MHz_pre = 0; static u64 lastTxOkCnt = 0; static u64 lastRxOkCnt = 0; diff --git a/hal/odm_RegConfig8188E.c b/hal/odm_RegConfig8188E.c index fba3281..a55d067 100755 --- a/hal/odm_RegConfig8188E.c +++ b/hal/odm_RegConfig8188E.c @@ -60,7 +60,7 @@ odm_ConfigRFReg_8188E( else { ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); - // Add 1us delay between BB/RF register setting. + /* Add 1us delay between BB/RF register setting. */ ODM_delay_us(1); } } @@ -73,7 +73,7 @@ odm_ConfigRF_RadioA_8188E( IN u32 Data ) { - u32 content = 0x1000; // RF_Content: radioa_txt + u32 content = 0x1000; /* RF_Content: radioa_txt */ u32 maskforPhySet= (u32)(content&0xE000); odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); @@ -88,7 +88,7 @@ odm_ConfigRF_RadioB_8188E( IN u32 Data ) { - u32 content = 0x1001; // RF_Content: radiob_txt + u32 content = 0x1001; /* RF_Content: radiob_txt */ u32 maskforPhySet= (u32)(content&0xE000); odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); @@ -117,7 +117,7 @@ odm_ConfigBB_AGC_8188E( ) { ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); - // Add 1us delay between BB/RF register setting. + /* Add 1us delay between BB/RF register setting. */ ODM_delay_us(1); ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); @@ -190,7 +190,7 @@ odm_ConfigBB_PHY_8188E( pDM_Odm->RFCalibrateInfo.RegA24 = Data; ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); - // Add 1us delay between BB/RF register setting. + /* Add 1us delay between BB/RF register setting. */ ODM_delay_us(1); ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); } diff --git a/hal/odm_RegConfig8188E.h b/hal/odm_RegConfig8188E.h index 82fdfd1..c9d05ee 100755 --- a/hal/odm_RegConfig8188E.h +++ b/hal/odm_RegConfig8188E.h @@ -74,5 +74,5 @@ odm_ConfigBB_PHY_8188E( IN u32 Data ); -#endif // end of SUPPORT +#endif /* end of SUPPORT */ diff --git a/hal/odm_RegDefine11AC.h b/hal/odm_RegDefine11AC.h index b2a318a..6a68c48 100755 --- a/hal/odm_RegDefine11AC.h +++ b/hal/odm_RegDefine11AC.h @@ -21,32 +21,32 @@ #ifndef __ODM_REGDEFINE11AC_H__ #define __ODM_REGDEFINE11AC_H__ -//2 RF REG LIST +/* 2 RF REG LIST */ -//2 BB REG LIST -//PAGE 8 -//PAGE 9 +/* 2 BB REG LIST */ +/* PAGE 8 */ +/* PAGE 9 */ #define ODM_REG_OFDM_FA_RST_11AC 0x9A4 -//PAGE A +/* PAGE A */ #define ODM_REG_CCK_CCA_11AC 0xA0A #define ODM_REG_CCK_FA_RST_11AC 0xA2C #define ODM_REG_CCK_FA_11AC 0xA5C -//PAGE C +/* PAGE C */ #define ODM_REG_IGI_A_11AC 0xC50 -//PAGE E +/* PAGE E */ #define ODM_REG_IGI_B_11AC 0xE50 -//PAGE F +/* PAGE F */ #define ODM_REG_OFDM_FA_11AC 0xF48 -//2 MAC REG LIST +/* 2 MAC REG LIST */ -//DIG Related +/* DIG Related */ #define ODM_BIT_IGI_11AC 0xFFFFFFFF diff --git a/hal/odm_RegDefine11N.h b/hal/odm_RegDefine11N.h index 841b1b4..b7553ba 100755 --- a/hal/odm_RegDefine11N.h +++ b/hal/odm_RegDefine11N.h @@ -22,7 +22,7 @@ #define __ODM_REGDEFINE11N_H__ -//2 RF REG LIST +/* 2 RF REG LIST */ #define ODM_REG_RF_MODE_11N 0x00 #define ODM_REG_RF_0B_11N 0x0B #define ODM_REG_CHNBW_11N 0x18 @@ -38,8 +38,8 @@ -//2 BB REG LIST -//PAGE 8 +/* 2 BB REG LIST */ +/* PAGE 8 */ #define ODM_REG_BB_CTRL_11N 0x800 #define ODM_REG_RF_PIN_11N 0x804 #define ODM_REG_PSD_CTRL_11N 0x808 @@ -57,10 +57,10 @@ #define ODM_REG_BB_3WIRE_11N 0x88C #define ODM_REG_SC_CNT_11N 0x8C4 #define ODM_REG_PSD_DATA_11N 0x8B4 -//PAGE 9 +/* PAGE 9 */ #define ODM_REG_ANT_MAPPING1_11N 0x914 #define ODM_REG_ANT_MAPPING2_11N 0x918 -//PAGE A +/* PAGE A */ #define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00 #define ODM_REG_CCK_CCA_11N 0xA0A #define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C @@ -79,13 +79,13 @@ #define ODM_REG_CCK_FA_LSB_11N 0xA5C #define ODM_REG_CCK_CCA_CNT_11N 0xA60 #define ODM_REG_BB_PWR_SAV4_11N 0xA74 -//PAGE B +/* PAGE B */ #define ODM_REG_LNA_SWITCH_11N 0xB2C #define ODM_REG_PATH_SWITCH_11N 0xB30 #define ODM_REG_RSSI_CTRL_11N 0xB38 #define ODM_REG_CONFIG_ANTA_11N 0xB68 #define ODM_REG_RSSI_BT_11N 0xB9C -//PAGE C +/* PAGE C */ #define ODM_REG_OFDM_FA_HOLDC_11N 0xC00 #define ODM_REG_RX_PATH_11N 0xC04 #define ODM_REG_TRMUX_11N 0xC08 @@ -105,12 +105,12 @@ #define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0 #define ODM_REG_ANTDIV_PARA1_11N 0xCA4 #define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0 -//PAGE D +/* PAGE D */ #define ODM_REG_OFDM_FA_RSTD_11N 0xD00 #define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0 #define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4 #define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8 -//PAGE E +/* PAGE E */ #define ODM_REG_TXAGC_A_6_18_11N 0xE00 #define ODM_REG_TXAGC_A_24_54_11N 0xE04 #define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08 @@ -149,7 +149,7 @@ -//2 MAC REG LIST +/* 2 MAC REG LIST */ #define ODM_REG_BB_RST_11N 0x02 #define ODM_REG_ANTSEL_PIN_11N 0x4C #define ODM_REG_EARLY_MODE_11N 0x4D0 @@ -164,7 +164,7 @@ #define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4 -//DIG Related +/* DIG Related */ #define ODM_BIT_IGI_11N 0x0000007F diff --git a/hal/odm_debug.c b/hal/odm_debug.c index 9a5f40d..c84da86 100755 --- a/hal/odm_debug.c +++ b/hal/odm_debug.c @@ -18,9 +18,9 @@ * ******************************************************************************/ -//============================================================ -// include files -//============================================================ +/* */ +/* include files */ +/* */ #include "odm_precomp.h" @@ -34,31 +34,31 @@ pDM_Odm->DebugLevel = ODM_DBG_TRACE; pDM_Odm->DebugComponents = \ #if DBG -//BB Functions -// ODM_COMP_DIG | -// ODM_COMP_RA_MASK | -// ODM_COMP_DYNAMIC_TXPWR | -// ODM_COMP_FA_CNT | -// ODM_COMP_RSSI_MONITOR | -// ODM_COMP_CCK_PD | -// ODM_COMP_ANT_DIV | -// ODM_COMP_PWR_SAVE | -// ODM_COMP_PWR_TRAIN | -// ODM_COMP_RATE_ADAPTIVE | -// ODM_COMP_PATH_DIV | -// ODM_COMP_DYNAMIC_PRICCA | -// ODM_COMP_RXHP | +/* BB Functions */ +/* ODM_COMP_DIG | */ +/* ODM_COMP_RA_MASK | */ +/* ODM_COMP_DYNAMIC_TXPWR | */ +/* ODM_COMP_FA_CNT | */ +/* ODM_COMP_RSSI_MONITOR | */ +/* ODM_COMP_CCK_PD | */ +/* ODM_COMP_ANT_DIV | */ +/* ODM_COMP_PWR_SAVE | */ +/* ODM_COMP_PWR_TRAIN | */ +/* ODM_COMP_RATE_ADAPTIVE | */ +/* ODM_COMP_PATH_DIV | */ +/* ODM_COMP_DYNAMIC_PRICCA | */ +/* ODM_COMP_RXHP | */ -//MAC Functions -// ODM_COMP_EDCA_TURBO | -// ODM_COMP_EARLY_MODE | -//RF Functions -// ODM_COMP_TX_PWR_TRACK | -// ODM_COMP_RX_GAIN_TRACK | -// ODM_COMP_CALIBRATION | -//Common -// ODM_COMP_COMMON | -// ODM_COMP_INIT | +/* MAC Functions */ +/* ODM_COMP_EDCA_TURBO | */ +/* ODM_COMP_EARLY_MODE | */ +/* RF Functions */ +/* ODM_COMP_TX_PWR_TRACK | */ +/* ODM_COMP_RX_GAIN_TRACK | */ +/* ODM_COMP_CALIBRATION | */ +/* Common */ +/* ODM_COMP_COMMON | */ +/* ODM_COMP_INIT | */ #endif 0; } diff --git a/hal/odm_debug.h b/hal/odm_debug.h index cd57b47..64c8e68 100755 --- a/hal/odm_debug.h +++ b/hal/odm_debug.h @@ -23,53 +23,53 @@ #define __ODM_DBG_H__ -//----------------------------------------------------------------------------- -// Define the debug levels -// -// 1. DBG_TRACE and DBG_LOUD are used for normal cases. -// So that, they can help SW engineer to develope or trace states changed -// and also help HW enginner to trace every operation to and from HW, -// e.g IO, Tx, Rx. -// -// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, -// which help us to debug SW or HW. -// -//----------------------------------------------------------------------------- -// -// Never used in a call to ODM_RT_TRACE()! -// +/* */ +/* Define the debug levels */ +/* */ +/* 1. DBG_TRACE and DBG_LOUD are used for normal cases. */ +/* So that, they can help SW engineer to develope or trace states changed */ +/* and also help HW enginner to trace every operation to and from HW, */ +/* e.g IO, Tx, Rx. */ +/* */ +/* 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, */ +/* which help us to debug SW or HW. */ +/* */ +/* */ +/* */ +/* Never used in a call to ODM_RT_TRACE()! */ +/* */ #define ODM_DBG_OFF 1 -// -// Fatal bug. -// For example, Tx/Rx/IO locked up, OS hangs, memory access violation, -// resource allocation failed, unexpected HW behavior, HW BUG and so on. -// +/* */ +/* Fatal bug. */ +/* For example, Tx/Rx/IO locked up, OS hangs, memory access violation, */ +/* resource allocation failed, unexpected HW behavior, HW BUG and so on. */ +/* */ #define ODM_DBG_SERIOUS 2 -// -// Abnormal, rare, or unexpeted cases. -// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. -// +/* */ +/* Abnormal, rare, or unexpeted cases. */ +/* For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. */ +/* */ #define ODM_DBG_WARNING 3 -// -// Normal case with useful information about current SW or HW state. -// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, -// SW protocol state change, dynamic mechanism state change and so on. -// +/* */ +/* Normal case with useful information about current SW or HW state. */ +/* For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, */ +/* SW protocol state change, dynamic mechanism state change and so on. */ +/* */ #define ODM_DBG_LOUD 4 -// -// Normal case with detail execution flow or information. -// +/* */ +/* Normal case with detail execution flow or information. */ +/* */ #define ODM_DBG_TRACE 5 -//----------------------------------------------------------------------------- -// Define the tracing components -// -//----------------------------------------------------------------------------- -//BB Functions +/* */ +/* Define the tracing components */ +/* */ +/* */ +/* BB Functions */ #define ODM_COMP_DIG BIT0 #define ODM_COMP_RA_MASK BIT1 #define ODM_COMP_DYNAMIC_TXPWR BIT2 @@ -84,14 +84,14 @@ #define ODM_COMP_PSD BIT11 #define ODM_COMP_DYNAMIC_PRICCA BIT12 #define ODM_COMP_RXHP BIT13 -//MAC Functions +/* MAC Functions */ #define ODM_COMP_EDCA_TURBO BIT16 #define ODM_COMP_EARLY_MODE BIT17 -//RF Functions +/* RF Functions */ #define ODM_COMP_TX_PWR_TRACK BIT24 #define ODM_COMP_RX_GAIN_TRACK BIT25 #define ODM_COMP_CALIBRATION BIT26 -//Common Functions +/* Common Functions */ #define ODM_COMP_COMMON BIT30 #define ODM_COMP_INIT BIT31 @@ -166,5 +166,5 @@ ODM_InitDebugSetting( IN PDM_ODM_T pDM_Odm ); -#endif // __ODM_DBG_H__ +#endif /* __ODM_DBG_H__ */ diff --git a/hal/odm_interface.c b/hal/odm_interface.c index 3ea7bcb..bee5f0b 100755 --- a/hal/odm_interface.c +++ b/hal/odm_interface.c @@ -18,14 +18,14 @@ * ******************************************************************************/ -//============================================================ -// include files -//============================================================ +/* */ +/* include files */ +/* */ #include "odm_precomp.h" -// -// ODM IO Relative API. -// +/* */ +/* ODM IO Relative API. */ +/* */ u8 ODM_Read1Byte( @@ -165,9 +165,9 @@ ODM_GetRFReg( RegAddr, BitMask); } -// -// ODM Memory relative API. -// +/* */ +/* ODM Memory relative API. */ +/* */ void ODM_AllocateMemory( IN PDM_ODM_T pDM_Odm, @@ -178,7 +178,7 @@ ODM_AllocateMemory( *pPtr = rtw_zvmalloc(length); } -// length could be ignored, used to detect memory leakage. +/* length could be ignored, used to detect memory leakage. */ void ODM_FreeMemory( IN PDM_ODM_T pDM_Odm, @@ -199,9 +199,9 @@ s32 ODM_CompareMemory( return _rtw_memcmp(pBuf1,pBuf2,length); } -// -// ODM MISC relative API. -// +/* */ +/* ODM MISC relative API. */ +/* */ void ODM_AcquireSpinLock( IN PDM_ODM_T pDM_Odm, @@ -218,9 +218,9 @@ ODM_ReleaseSpinLock( { } -// -// Work item relative API. FOr MP driver only~! -// +/* */ +/* Work item relative API. FOr MP driver only~! */ +/* */ void ODM_InitializeWorkItem( IN PDM_ODM_T pDM_Odm, @@ -267,9 +267,9 @@ ODM_IsWorkItemScheduled( { } -// -// ODM Timer relative API. -// +/* */ +/* ODM Timer relative API. */ +/* */ void ODM_StallExecution( IN u32 usDelay @@ -309,7 +309,7 @@ ODM_SetTimer( IN u32 msDelay ) { - _set_timer(pTimer,msDelay ); //ms + _set_timer(pTimer,msDelay ); /* ms */ } void @@ -342,9 +342,9 @@ ODM_ReleaseTimer( { } -// -// ODM FW relative API. -// +/* */ +/* ODM FW relative API. */ +/* */ u32 ODM_FillH2CCmd( IN u8 * pH2CBuffer, diff --git a/hal/odm_interface.h b/hal/odm_interface.h index a2de46d..943845c 100755 --- a/hal/odm_interface.h +++ b/hal/odm_interface.h @@ -24,15 +24,15 @@ -// -// =========== Constant/Structure/Enum/... Define -// +/* */ +/* =========== Constant/Structure/Enum/... Define */ +/* */ -// -// =========== Macro Define -// +/* */ +/* =========== Macro Define */ +/* */ #define _reg_all(_name) ODM_##_name #define _reg_ic(_name, _ic) ODM_##_name##_ic @@ -58,9 +58,9 @@ ODM_REG(DIG,_pDM_Odm) _func##_11AC(_name) \ ) -// _name: name of register or bit. -// Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)" -// gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType. +/* _name: name of register or bit. */ +/* Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)" */ +/* gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType. */ #define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg) #define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit) @@ -73,22 +73,22 @@ typedef enum _ODM_H2C_CMD }ODM_H2C_CMD; -// -// 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem. -// Suggest HW team to use thread instead of workitem. Windows also support the feature. -// +/* */ +/* 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem. */ +/* Suggest HW team to use thread instead of workitem. Windows also support the feature. */ +/* */ typedef void *PRT_WORK_ITEM ; typedef void RT_WORKITEM_HANDLE,*PRT_WORKITEM_HANDLE; typedef void (*RT_WORKITEM_CALL_BACK)(void * pContext); -// -// =========== Extern Variable ??? It should be forbidden. -// +/* */ +/* =========== Extern Variable ??? It should be forbidden. */ +/* */ -// -// =========== EXtern Function Prototype -// +/* */ +/* =========== EXtern Function Prototype */ +/* */ u8 @@ -178,9 +178,9 @@ ODM_GetRFReg( ); -// -// Memory Relative Function. -// +/* */ +/* Memory Relative Function. */ +/* */ void ODM_AllocateMemory( IN PDM_ODM_T pDM_Odm, @@ -201,9 +201,9 @@ s32 ODM_CompareMemory( IN u32 length ); -// -// ODM MISC-spin lock relative API. -// +/* */ +/* ODM MISC-spin lock relative API. */ +/* */ void ODM_AcquireSpinLock( IN PDM_ODM_T pDM_Odm, @@ -217,9 +217,9 @@ ODM_ReleaseSpinLock( ); -// -// ODM MISC-workitem relative API. -// +/* */ +/* ODM MISC-workitem relative API. */ +/* */ void ODM_InitializeWorkItem( IN PDM_ODM_T pDM_Odm, @@ -254,9 +254,9 @@ ODM_IsWorkItemScheduled( IN PRT_WORK_ITEM pRtWorkItem ); -// -// ODM Timer relative API. -// +/* */ +/* ODM Timer relative API. */ +/* */ void ODM_StallExecution( IN u32 usDelay @@ -304,9 +304,9 @@ ODM_ReleaseTimer( ); -// -// ODM FW relative API. -// +/* */ +/* ODM FW relative API. */ +/* */ u32 ODM_FillH2CCmd( IN u8 * pH2CBuffer, @@ -318,4 +318,4 @@ ODM_FillH2CCmd( IN u8 * CmdStartSeq ); -#endif // __ODM_INTERFACE_H__ +#endif /* __ODM_INTERFACE_H__ */ diff --git a/hal/odm_precomp.h b/hal/odm_precomp.h index ed997c3..49c6550 100755 --- a/hal/odm_precomp.h +++ b/hal/odm_precomp.h @@ -25,7 +25,7 @@ #define TEST_FALG___ 1 -//2 Config Flags and Structs - defined by each ODM Type +/* 2 Config Flags and Structs - defined by each ODM Type */ #include #include @@ -33,11 +33,11 @@ #include -//2 Hardware Parameter Files +/* 2 Hardware Parameter Files */ #include "Hal8188EFWImg_CE.h" -//2 OutSrc Header Files +/* 2 OutSrc Header Files */ #include "odm.h" #include "odm_HWConfig.h" @@ -46,8 +46,8 @@ #include "odm_RegDefine11N.h" #include "HalPhyRf.h" -#include "HalPhyRf_8188e.h"//for IQK,LCK,Power-tracking -#include "Hal8188ERateAdaptive.h"//for RA,Power training +#include "HalPhyRf_8188e.h"/* for IQK,LCK,Power-tracking */ +#include "Hal8188ERateAdaptive.h"/* for RA,Power training */ #include "rtl8188e_hal.h" #include "odm_interface.h" @@ -66,10 +66,10 @@ #ifdef CONFIG_WOWLAN #include "HalHWImg8188E_FW.h" -#endif //CONFIG_WOWLAN +#endif /* CONFIG_WOWLAN */ #include "odm_RegConfig8188E.h" #include "odm_RTL8188E.h" -#endif // __ODM_PRECOMP_H__ +#endif /* __ODM_PRECOMP_H__ */ diff --git a/hal/odm_reg.h b/hal/odm_reg.h index 361ac79..43b1fb9 100755 --- a/hal/odm_reg.h +++ b/hal/odm_reg.h @@ -17,23 +17,23 @@ * * ******************************************************************************/ -//============================================================ -// File Name: odm_reg.h -// -// Description: -// -// This file is for general register definition. -// -// -//============================================================ +/* */ +/* File Name: odm_reg.h */ +/* */ +/* Description: */ +/* */ +/* This file is for general register definition. */ +/* */ +/* */ +/* */ #ifndef __HAL_ODM_REG_H__ #define __HAL_ODM_REG_H__ -// -// Register Definition -// +/* */ +/* Register Definition */ +/* */ -//MAC REG +/* MAC REG */ #define ODM_BB_RESET 0x002 #define ODM_DUMMY 0x4fe #define ODM_EDCA_VO_PARAM 0x500 @@ -42,7 +42,7 @@ #define ODM_EDCA_BK_PARAM 0x50C #define ODM_TXPAUSE 0x522 -//BB REG +/* BB REG */ #define ODM_FPGA_PHY0_PAGE8 0x800 #define ODM_PSD_SETTING 0x808 #define ODM_AFE_SETTING 0x818 @@ -93,24 +93,24 @@ #define ODM_TXAGC_A_MCS8_MCS11 0xe18 #define ODM_TXAGC_A_MCS12_MCS15 0xe1c -//RF REG +/* RF REG */ #define ODM_GAIN_SETTING 0x00 #define ODM_CHANNEL 0x18 -//Ant Detect Reg +/* Ant Detect Reg */ #define ODM_DPDT 0x300 -//PSD Init +/* PSD Init */ #define ODM_PSDREG 0x808 -//92D Path Div +/* 92D Path Div */ #define PATHDIV_REG 0xB30 #define PATHDIV_TRI 0xBA0 -// -// Bitmap Definition -// +/* */ +/* Bitmap Definition */ +/* */ #define BIT_FA_RESET BIT0 diff --git a/hal/odm_types.h b/hal/odm_types.h index 3873584..4b97696 100755 --- a/hal/odm_types.h +++ b/hal/odm_types.h @@ -20,15 +20,15 @@ #ifndef __ODM_TYPES_H__ #define __ODM_TYPES_H__ -// -// Define Different SW team support -// -#define ODM_AP 0x01 //BIT0 -#define ODM_ADSL 0x02 //BIT1 -#define ODM_CE 0x04 //BIT2 -#define ODM_MP 0x08 //BIT3 +/* */ +/* Define Different SW team support */ +/* */ +#define ODM_AP 0x01 /* BIT0 */ +#define ODM_ADSL 0x02 /* BIT1 */ +#define ODM_CE 0x04 /* BIT2 */ +#define ODM_MP 0x08 /* BIT3 */ -// Deifne HW endian support +/* Deifne HW endian support */ #define ODM_ENDIAN_BIG 0 #define ODM_ENDIAN_LITTLE 1 @@ -79,11 +79,11 @@ typedef void * RT_TIMER_CALL_BACK; #define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) \ SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value) -//define useless flag to avoid compile warning +/* define useless flag to avoid compile warning */ #define USE_WORKITEM 0 #define FOR_BRAZIL_PRETEST 0 #define BT_30_SUPPORT 0 #define FPGA_TWO_MAC_VERIFICATION 0 -#endif // __ODM_TYPES_H__ +#endif /* __ODM_TYPES_H__ */ diff --git a/hal/rtl8188e_cmd.c b/hal/rtl8188e_cmd.c index fe92d75..8ab0dc0 100755 --- a/hal/rtl8188e_cmd.c +++ b/hal/rtl8188e_cmd.c @@ -46,7 +46,7 @@ static u8 _is_fw_read_cmd_down(struct adapter* padapter, u8 msgbox_num) u8 valid; - //DBG_8192C(" _is_fw_read_cmd_down ,reg_1cc(%x),msg_box(%d)...\n",rtw_read8(padapter,REG_HMETFR),msgbox_num); + /* DBG_8192C(" _is_fw_read_cmd_down ,reg_1cc(%x),msg_box(%d)...\n",rtw_read8(padapter,REG_HMETFR),msgbox_num); */ do{ valid = rtw_read8(padapter,REG_HMETFR) & BIT(msgbox_num); @@ -108,7 +108,7 @@ static s32 FillH2CCmd_88E(struct adapter *padapter, u8 ElementID, u32 CmdLen, u8 if (padapter->bSurpriseRemoved == true) goto exit; - //pay attention to if race condition happened in H2C cmd setting. + /* pay attention to if race condition happened in H2C cmd setting. */ do{ h2c_box_num = pHalData->LastHMEBoxNum; @@ -128,7 +128,7 @@ static s32 FillH2CCmd_88E(struct adapter *padapter, u8 ElementID, u32 CmdLen, u8 ext_cmd_len = CmdLen-3; memcpy((u8*)(&h2c_cmd_ex), pCmdBuffer+3,ext_cmd_len ); - //Write Ext command + /* Write Ext command */ msgbox_ex_addr = REG_HMEBOX_EXT_0 + (h2c_box_num *RTL88E_EX_MESSAGE_BOX_SIZE); #ifdef CONFIG_H2C_EF for(cmd_idx=0;cmd_idxh2c_cmd:0x%x, reg:0x%x =>h2c_cmd_ex:0x%x ..\n" - // ,pHalData->LastHMEBoxNum ,CmdLen,msgbox_addr,h2c_cmd,msgbox_ex_addr,h2c_cmd_ex); - pHalData->LastHMEBoxNum = (h2c_box_num+1) % RTL88E_MAX_H2C_BOX_NUMS; - }while((!bcmd_down) && (retry_cnts--)); ret = _SUCCESS; @@ -205,15 +201,13 @@ u8 rtl8188e_set_raid_cmd(struct adapter*padapter, u32 mask) return res; } -//bitmap[0:27] = tx_rate_bitmap -//bitmap[28:31]= Rate Adaptive id -//arg[0:4] = macid -//arg[5] = Short GI +/* bitmap[0:27] = tx_rate_bitmap */ +/* bitmap[28:31]= Rate Adaptive id */ +/* arg[0:4] = macid */ +/* arg[5] = Short GI */ void rtl8188e_Add_RateATid(struct adapter *pAdapter, u32 bitmap, u8 arg, u8 rssi_level) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - //struct dm_priv *pdmpriv = &pHalData->dmpriv; - u8 macid, init_rate, raid, shortGIrate=false; macid = arg&0x1f; @@ -226,7 +220,7 @@ void rtl8188e_Add_RateATid(struct adapter *pAdapter, u32 bitmap, u8 arg, u8 rssi bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv, macid, bitmap, rssi_level); bitmap |= ((raid<<28)&0xf0000000); -#endif //CONFIG_ODM_REFRESH_RAMASK +#endif /* CONFIG_ODM_REFRESH_RAMASK */ init_rate = get_highest_rate_idx(bitmap&0x0fffffff)&0x3f; @@ -237,7 +231,7 @@ void rtl8188e_Add_RateATid(struct adapter *pAdapter, u32 bitmap, u8 arg, u8 rssi init_rate |= BIT(6); - //rtw_write8(pAdapter, (REG_INIDATA_RATE_SEL+macid), (u8)init_rate); + /* rtw_write8(pAdapter, (REG_INIDATA_RATE_SEL+macid), (u8)init_rate); */ raid = (bitmap>>28) & 0x0f; @@ -263,13 +257,13 @@ void rtl8188e_set_FwPwrMode_cmd(struct adapter *padapter, u8 Mode) { SETPWRMODE_PARM H2CSetPwrMode; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - u8 RLBM = 0; // 0:Min, 1:Max , 2:User define + u8 RLBM = 0; /* 0:Min, 1:Max , 2:User define */ ; DBG_871X("%s: Mode=%d SmartPS=%d UAPSD=%d\n", __FUNCTION__, Mode, pwrpriv->smart_ps, padapter->registrypriv.uapsd_enable); - H2CSetPwrMode.AwakeInterval = 2; //DTIM =1 + H2CSetPwrMode.AwakeInterval = 2; /* DTIM =1 */ switch(Mode) { @@ -295,7 +289,7 @@ void rtl8188e_set_FwPwrMode_cmd(struct adapter *padapter, u8 Mode) break; } - //H2CSetPwrMode.Mode = Mode; + /* H2CSetPwrMode.Mode = Mode; */ H2CSetPwrMode.SmartPS_RLBM = (((pwrpriv->smart_ps<<4)&0xf0) | (RLBM & 0x0f)); @@ -303,13 +297,13 @@ void rtl8188e_set_FwPwrMode_cmd(struct adapter *padapter, u8 Mode) if(Mode > 0) { - H2CSetPwrMode.PwrState = 0x00;// AllON(0x0C), RFON(0x04), RFOFF(0x00) + H2CSetPwrMode.PwrState = 0x00;/* AllON(0x0C), RFON(0x04), RFOFF(0x00) */ #ifdef CONFIG_EXT_CLK - H2CSetPwrMode.Mode |= BIT(7);//supporting 26M XTAL CLK_Request feature. -#endif //CONFIG_EXT_CLK + H2CSetPwrMode.Mode |= BIT(7);/* supporting 26M XTAL CLK_Request feature. */ +#endif /* CONFIG_EXT_CLK */ } else - H2CSetPwrMode.PwrState = 0x0C;// AllON(0x0C), RFON(0x04), RFOFF(0x00) + H2CSetPwrMode.PwrState = 0x0C;/* AllON(0x0C), RFON(0x04), RFOFF(0x00) */ FillH2CCmd_88E(padapter, H2C_PS_PWR_MODE, sizeof(H2CSetPwrMode), (u8 *)&H2CSetPwrMode); @@ -332,12 +326,12 @@ void rtl8188e_set_FwMediaStatus_cmd(struct adapter *padapter, __le16 mstatus_rpt reg_macid_no_link = REG_MACID_NO_LINK_1; } - //Delete select macid (MACID 0~63) from queue list. - if(opmode == 1)// 1:connect + /* Delete select macid (MACID 0~63) from queue list. */ + if(opmode == 1)/* 1:connect */ { rtw_write32(padapter,reg_macid_no_link, (rtw_read32(padapter,reg_macid_no_link) & (~BIT(macid)))); } - else//0: disconnect + else/* 0: disconnect */ { rtw_write32(padapter,reg_macid_no_link, (rtw_read32(padapter,reg_macid_no_link)|BIT(macid))); } @@ -357,7 +351,7 @@ static void ConstructBeacon(struct adapter *padapter, u8 *pframe, u32 *pLength) u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - //DBG_871X("%s\n", __FUNCTION__); + /* DBG_871X("%s\n", __FUNCTION__); */ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; @@ -369,23 +363,23 @@ static void ConstructBeacon(struct adapter *padapter, u8 *pframe, u32 *pLength) memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); - //pmlmeext->mgnt_seq++; + /* pmlmeext->mgnt_seq++; */ SetFrameSubType(pframe, WIFI_BEACON); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pktlen = sizeof (struct rtw_ieee80211_hdr_3addr); - //timestamp will be inserted by hardware + /* timestamp will be inserted by hardware */ pframe += 8; pktlen += 8; - // beacon interval: 2 bytes + /* beacon interval: 2 bytes */ memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); pframe += 2; pktlen += 2; - // capability info: 2 bytes + /* capability info: 2 bytes */ memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); pframe += 2; @@ -393,46 +387,46 @@ static void ConstructBeacon(struct adapter *padapter, u8 *pframe, u32 *pLength) if( (pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) { - //DBG_871X("ie len=%d\n", cur_network->IELength); + /* DBG_871X("ie len=%d\n", cur_network->IELength); */ pktlen += cur_network->IELength - sizeof(NDIS_802_11_FIXED_IEs); memcpy(pframe, cur_network->IEs+sizeof(NDIS_802_11_FIXED_IEs), pktlen); goto _ConstructBeacon; } - //below for ad-hoc mode + /* below for ad-hoc mode */ - // SSID + /* SSID */ pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen); - // supported rates... + /* supported rates... */ rate_len = rtw_get_rateset_len(cur_network->SupportedRates); pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &pktlen); - // DS parameter set + /* DS parameter set */ pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen); if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) { u32 ATIMWindow; - // IBSS Parameter Set... - //ATIMWindow = cur->Configuration.ATIMWindow; + /* IBSS Parameter Set... */ + /* ATIMWindow = cur->Configuration.ATIMWindow; */ ATIMWindow = 0; pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen); } - //todo: ERP IE + /* todo: ERP IE */ - // EXTERNDED SUPPORTED RATE + /* EXTERNDED SUPPORTED RATE */ if (rate_len > 8) { pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen); } - //todo:HT for adhoc + /* todo:HT for adhoc */ _ConstructBeacon: @@ -444,7 +438,7 @@ _ConstructBeacon: *pLength = pktlen; - //DBG_871X("%s bcn_sz=%d\n", __FUNCTION__, pktlen); + /* DBG_871X("%s bcn_sz=%d\n", __FUNCTION__, pktlen); */ } @@ -456,23 +450,23 @@ static void ConstructPSPoll(struct adapter *padapter, u8 *pframe, u32 *pLength) struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - //DBG_871X("%s\n", __FUNCTION__); + /* DBG_871X("%s\n", __FUNCTION__); */ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - // Frame control. + /* Frame control. */ fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; SetPwrMgt(fctrl); SetFrameSubType(pframe, WIFI_PSPOLL); - // AID. + /* AID. */ SetDuration(pframe, (pmlmeinfo->aid | 0xc000)); - // BSSID. + /* BSSID. */ memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - // TA. + /* TA. */ memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); *pLength = 16; @@ -497,7 +491,7 @@ static void ConstructNullFunctionData( struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - //DBG_871X("%s:%d\n", __FUNCTION__, bForcePowerSave); + /* DBG_871X("%s:%d\n", __FUNCTION__, bForcePowerSave); */ pwlanhdr = (struct rtw_ieee80211_hdr*)pframe; @@ -552,10 +546,10 @@ static void ConstructNullFunctionData( } #ifdef CONFIG_WOWLAN -// -// Description: -// Construct the ARP response packet to support ARP offload. -// +/* */ +/* Description: */ +/* Construct the ARP response packet to support ARP offload. */ +/* */ static void ConstructARPResponse( struct adapter *padapter, u8 *pframe, @@ -574,7 +568,7 @@ static void ConstructARPResponse( __le16 *fctrl; u32 pktlen; u8 *pARPRspPkt = pframe; - //for TKIP Cal MIC + /* for TKIP Cal MIC */ u8 *payload = pframe; u8 EncryptionHeadOverhead = 0; @@ -583,11 +577,11 @@ static void ConstructARPResponse( fctrl = &pwlanhdr->frame_ctl; *(fctrl) = 0; - //------------------------------------------------------------------------- - // MAC Header. - //------------------------------------------------------------------------- + /* */ + /* MAC Header. */ + /* */ SetFrameType(fctrl, WIFI_DATA); - //SetFrameSubType(fctrl, 0); + /* SetFrameSubType(fctrl, 0); */ SetToDs(fctrl); memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); @@ -595,21 +589,21 @@ static void ConstructARPResponse( SetSeqNum(pwlanhdr, 0); SetDuration(pwlanhdr, 0); - //SET_80211_HDR_FRAME_CONTROL(pARPRspPkt, 0); - //SET_80211_HDR_TYPE_AND_SUBTYPE(pARPRspPkt, Type_Data); - //SET_80211_HDR_TO_DS(pARPRspPkt, 1); - //SET_80211_HDR_ADDRESS1(pARPRspPkt, pMgntInfo->Bssid); - //SET_80211_HDR_ADDRESS2(pARPRspPkt, Adapter->CurrentAddress); - //SET_80211_HDR_ADDRESS3(pARPRspPkt, pMgntInfo->Bssid); + /* SET_80211_HDR_FRAME_CONTROL(pARPRspPkt, 0); */ + /* SET_80211_HDR_TYPE_AND_SUBTYPE(pARPRspPkt, Type_Data); */ + /* SET_80211_HDR_TO_DS(pARPRspPkt, 1); */ + /* SET_80211_HDR_ADDRESS1(pARPRspPkt, pMgntInfo->Bssid); */ + /* SET_80211_HDR_ADDRESS2(pARPRspPkt, Adapter->CurrentAddress); */ + /* SET_80211_HDR_ADDRESS3(pARPRspPkt, pMgntInfo->Bssid); */ - //SET_80211_HDR_DURATION(pARPRspPkt, 0); - //SET_80211_HDR_FRAGMENT_SEQUENCE(pARPRspPkt, 0); + /* SET_80211_HDR_DURATION(pARPRspPkt, 0); */ + /* SET_80211_HDR_FRAGMENT_SEQUENCE(pARPRspPkt, 0); */ *pLength = 24; -//YJ,del,120503 - //------------------------------------------------------------------------- - // Security Header: leave space for it if necessary. - //------------------------------------------------------------------------- +/* YJ,del,120503 */ + /* */ + /* Security Header: leave space for it if necessary. */ + /* */ switch (psecuritypriv->dot11PrivacyAlgrthm) { @@ -636,25 +630,24 @@ static void ConstructARPResponse( { memset(&(pframe[*pLength]), 0,EncryptionHeadOverhead); *pLength += EncryptionHeadOverhead; - //SET_80211_HDR_WEP(pARPRspPkt, 1); //Suggested by CCW. SetPrivacy(fctrl); } - //------------------------------------------------------------------------- - // Frame Body. - //------------------------------------------------------------------------- + /* */ + /* Frame Body. */ + /* */ pARPRspPkt = (u8*)(pframe+ *pLength); - // LLC header + /* LLC header */ memcpy(pARPRspPkt, ARPLLCHeader, 8); *pLength += 8; - // ARP element + /* ARP element */ pARPRspPkt += 8; SET_ARP_PKT_HW(pARPRspPkt, 0x0100); - SET_ARP_PKT_PROTOCOL(pARPRspPkt, 0x0008); // IP protocol + SET_ARP_PKT_PROTOCOL(pARPRspPkt, 0x0008); /* IP protocol */ SET_ARP_PKT_HW_ADDR_LEN(pARPRspPkt, 6); SET_ARP_PKT_PROTOCOL_ADDR_LEN(pARPRspPkt, 4); - SET_ARP_PKT_OPERATION(pARPRspPkt, 0x0200); // ARP response + SET_ARP_PKT_OPERATION(pARPRspPkt, 0x0200); /* ARP response */ SET_ARP_PKT_SENDER_MAC_ADDR(pARPRspPkt, myid(&(padapter->eeprompriv))); SET_ARP_PKT_SENDER_IP_ADDR(pARPRspPkt, pIPAddress); #ifdef CONFIG_ARP_KEEP_ALIVE @@ -686,18 +679,18 @@ static void ConstructARPResponse( if(_rtw_memcmp(&psta->dot11tkiptxmickey.skey[0],null_key, 16)==true){ DBG_871X("%s(): STA dot11tkiptxmickey==0\n",__FUNCTION__); } - //start to calculate the mic code + /* start to calculate the mic code */ rtw_secmicsetkey(&micdata, &psta->dot11tkiptxmickey.skey[0]); } - rtw_secmicappend(&micdata, pwlanhdr->addr3, 6); //DA + rtw_secmicappend(&micdata, pwlanhdr->addr3, 6); /* DA */ - rtw_secmicappend(&micdata, pwlanhdr->addr2, 6); //SA + rtw_secmicappend(&micdata, pwlanhdr->addr2, 6); /* SA */ priority[0]=0; rtw_secmicappend(&micdata, &priority[0], 4); - rtw_secmicappend(&micdata, payload, 36); //payload length = 8 + 28 + rtw_secmicappend(&micdata, payload, 36); /* payload length = 8 + 28 */ rtw_secgetmic(&micdata,&(mic[0])); @@ -714,8 +707,8 @@ static void rtl8188e_set_FwRsvdPage_cmd(struct adapter *padapter, PRSVDPAGE_LOC u8 u1H2CRsvdPageParm[H2C_8188E_RSVDPAGE_LOC_LEN]={0}; u8 u1H2CAoacRsvdPageParm[H2C_8188E_AOAC_RSVDPAGE_LOC_LEN]={0}; - //DBG_871X("8188RsvdPageLoc: PsPoll=%d Null=%d QoSNull=%d\n", - // rsvdpageloc->LocPsPoll, rsvdpageloc->LocNullData, rsvdpageloc->LocQosNull); + /* DBG_871X("8188RsvdPageLoc: PsPoll=%d Null=%d QoSNull=%d\n", */ + /* rsvdpageloc->LocPsPoll, rsvdpageloc->LocNullData, rsvdpageloc->LocQosNull); */ SET_8188E_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1H2CRsvdPageParm, rsvdpageloc->LocPsPoll); SET_8188E_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocNullData); @@ -724,7 +717,7 @@ static void rtl8188e_set_FwRsvdPage_cmd(struct adapter *padapter, PRSVDPAGE_LOC FillH2CCmd_88E(padapter, H2C_COM_RSVD_PAGE, H2C_8188E_RSVDPAGE_LOC_LEN, u1H2CRsvdPageParm); #ifdef CONFIG_WOWLAN - //DBG_871X("8188E_AOACRsvdPageLoc: RWC=%d ArpRsp=%d\n", rsvdpageloc->LocRemoteCtrlInfo, rsvdpageloc->LocArpRsp); + /* DBG_871X("8188E_AOACRsvdPageLoc: RWC=%d ArpRsp=%d\n", rsvdpageloc->LocRemoteCtrlInfo, rsvdpageloc->LocArpRsp); */ SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(u1H2CAoacRsvdPageParm, rsvdpageloc->LocRemoteCtrlInfo); SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(u1H2CAoacRsvdPageParm, rsvdpageloc->LocArpRsp); @@ -732,8 +725,8 @@ static void rtl8188e_set_FwRsvdPage_cmd(struct adapter *padapter, PRSVDPAGE_LOC #endif } -// To check if reserved page content is destroyed by beacon beacuse beacon is too large. -// 2010.06.23. Added by tynli. +/* To check if reserved page content is destroyed by beacon beacuse beacon is too large. */ +/* 2010.06.23. Added by tynli. */ void CheckFwRsvdPageContent( IN struct adapter * Adapter @@ -752,16 +745,16 @@ CheckFwRsvdPageContent( } } -// -// Description: Fill the reserved packets that FW will use to RSVD page. -// Now we just send 4 types packet to rsvd page. -// (1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp. -// Input: -// bDLFinished - FALSE: At the first time we will send all the packets as a large packet to Hw, -// so we need to set the packet length to total lengh. -// TRUE: At the second time, we should send the first packet (default:beacon) -// to Hw again and set the lengh in descriptor to the real beacon lengh. -// 2009.10.15 by tynli. +/* */ +/* Description: Fill the reserved packets that FW will use to RSVD page. */ +/* Now we just send 4 types packet to rsvd page. */ +/* (1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp. */ +/* Input: */ +/* bDLFinished - FALSE: At the first time we will send all the packets as a large packet to Hw, */ +/* so we need to set the packet length to total lengh. */ +/* TRUE: At the second time, we should send the first packet (default:beacon) */ +/* to Hw again and set the lengh in descriptor to the real beacon lengh. */ +/* 2009.10.15 by tynli. */ static void SetFwRsvdPagePkt(struct adapter *padapter, BOOLEAN bDLFinished) { PHAL_DATA_TYPE pHalData; @@ -800,14 +793,14 @@ static void SetFwRsvdPagePkt(struct adapter *padapter, BOOLEAN bDLFinished) TxDescLen = TXDESC_SIZE; PageNum = 0; - //3 (1) beacon * 2 pages + /* 3 (1) beacon * 2 pages */ BufIndex = TXDESC_OFFSET; ConstructBeacon(padapter, &ReservedPagePacket[BufIndex], &BeaconLength); - // When we count the first page size, we need to reserve description size for the RSVD - // packet, it will be filled in front of the packet in TXPKTBUF. + /* When we count the first page size, we need to reserve description size for the RSVD */ + /* packet, it will be filled in front of the packet in TXPKTBUF. */ PageNeed = (u8)PageNum_128(TxDescLen + BeaconLength); - // To reserved 2 pages for beacon buffer. 2010.06.24. + /* To reserved 2 pages for beacon buffer. 2010.06.24. */ if (PageNeed == 1) PageNeed += 1; PageNum += PageNeed; @@ -815,7 +808,7 @@ static void SetFwRsvdPagePkt(struct adapter *padapter, BOOLEAN bDLFinished) BufIndex += PageNeed*128; - //3 (2) ps-poll *1 page + /* 3 (2) ps-poll *1 page */ RsvdPageLoc.LocPsPoll = PageNum; ConstructPSPoll(padapter, &ReservedPagePacket[BufIndex], &PSPollLength); rtl8188e_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], PSPollLength, true, false); @@ -825,7 +818,7 @@ static void SetFwRsvdPagePkt(struct adapter *padapter, BOOLEAN bDLFinished) BufIndex += PageNeed*128; - //3 (3) null data * 1 page + /* 3 (3) null data * 1 page */ RsvdPageLoc.LocNullData = PageNum; ConstructNullFunctionData( padapter, @@ -840,7 +833,7 @@ static void SetFwRsvdPagePkt(struct adapter *padapter, BOOLEAN bDLFinished) BufIndex += PageNeed*128; - //3 (5) Qos null data + /* 3 (5) Qos null data */ RsvdPageLoc.LocQosNull = PageNum; ConstructNullFunctionData( padapter, @@ -856,7 +849,7 @@ static void SetFwRsvdPagePkt(struct adapter *padapter, BOOLEAN bDLFinished) BufIndex += PageNeed*128; #ifdef CONFIG_WOWLAN - //3(7) ARP + /* 3(7) ARP */ rtw_get_current_ip_address(padapter, currentip); RsvdPageLoc.LocArpRsp = PageNum; ConstructARPResponse( @@ -891,12 +884,12 @@ static void SetFwRsvdPagePkt(struct adapter *padapter, BOOLEAN bDLFinished) BufIndex += PageNeed*128; - //3(8) sec IV + /* 3(8) sec IV */ rtw_get_sec_iv(padapter, cur_dot11txpn, get_my_bssid(&pmlmeinfo->network)); RsvdPageLoc.LocRemoteCtrlInfo = PageNum; memcpy(ReservedPagePacket+BufIndex-TxDescLen, cur_dot11txpn, 8); - TotalPacketLen = BufIndex-TxDescLen + sizeof (union pn48); //IV len + TotalPacketLen = BufIndex-TxDescLen + sizeof (union pn48); /* IV len */ #else TotalPacketLen = BufIndex + QosNullLength; #endif @@ -905,7 +898,7 @@ static void SetFwRsvdPagePkt(struct adapter *padapter, BOOLEAN bDLFinished) if (pmgntframe == NULL) goto exit; - // update attribute + /* update attribute */ pattrib = &pmgntframe->attrib; update_mgntframe_attrib(padapter, pattrib); pattrib->qsel = 0x10; @@ -920,7 +913,7 @@ static void SetFwRsvdPagePkt(struct adapter *padapter, BOOLEAN bDLFinished) DBG_871X("%s: Set RSVD page location to Fw\n", __FUNCTION__); rtl8188e_set_FwRsvdPage_cmd(padapter, &RsvdPageLoc); - //FillH2CCmd_88E(padapter, H2C_COM_RSVD_PAGE, sizeof(RsvdPageLoc), (u8*)&RsvdPageLoc); + /* FillH2CCmd_88E(padapter, H2C_COM_RSVD_PAGE, sizeof(RsvdPageLoc), (u8*)&RsvdPageLoc); */ exit: rtw_mfree(ReservedPagePacket, RTL88E_RSVDPAGE_SIZE); @@ -947,24 +940,24 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus) if(mstatus == 1) { - // We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. - // Suggested by filen. Added by tynli. + /* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. */ + /* Suggested by filen. Added by tynli. */ rtw_write16(padapter, REG_BCN_PSR_RPT, (0xC000|pmlmeinfo->aid)); - // Do not set TSF again here or vWiFi beacon DMA INT will not work. - //correct_TSF(padapter, pmlmeext); - // Hw sequende enable by dedault. 2010.06.23. by tynli. - //rtw_write16(padapter, REG_NQOS_SEQ, ((pmlmeext->mgnt_seq+100)&0xFFF)); - //rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF); + /* Do not set TSF again here or vWiFi beacon DMA INT will not work. */ + /* correct_TSF(padapter, pmlmeext); */ + /* Hw sequende enable by dedault. 2010.06.23. by tynli. */ + /* rtw_write16(padapter, REG_NQOS_SEQ, ((pmlmeext->mgnt_seq+100)&0xFFF)); */ + /* rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF); */ - //Set REG_CR bit 8. DMA beacon by SW. + /* Set REG_CR bit 8. DMA beacon by SW. */ pHalData->RegCR_1 |= BIT0; rtw_write8(padapter, REG_CR+1, pHalData->RegCR_1); - // Disable Hw protection for a time which revserd for Hw sending beacon. - // Fix download reserved page packet fail that access collision with the protection time. - // 2010.05.11. Added by tynli. - //SetBcnCtrlReg(padapter, 0, BIT3); - //SetBcnCtrlReg(padapter, BIT4, 0); + /* Disable Hw protection for a time which revserd for Hw sending beacon. */ + /* Fix download reserved page packet fail that access collision with the protection time. */ + /* 2010.05.11. Added by tynli. */ + /* SetBcnCtrlReg(padapter, 0, BIT3); */ + /* SetBcnCtrlReg(padapter, BIT4, 0); */ rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)&(~BIT(3))); rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(4)); @@ -974,31 +967,31 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus) bSendBeacon = true; } - // Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. + /* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */ rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl&(~BIT6))); pHalData->RegFwHwTxQCtrl &= (~BIT6); - // Clear beacon valid check bit. + /* Clear beacon valid check bit. */ rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL); DLBcnCount = 0; poll = 0; do { - // download rsvd page. + /* download rsvd page. */ SetFwRsvdPagePkt(padapter, false); DLBcnCount++; do { rtw_yield_os(); - //rtw_mdelay_os(10); - // check rsvd page download OK. + /* rtw_mdelay_os(10); */ + /* check rsvd page download OK. */ rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8*)(&bcn_valid)); poll++; } while(!bcn_valid && (poll%10)!=0 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped); }while(!bcn_valid && DLBcnCount<=100 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped); - //RT_ASSERT(bcn_valid, ("HalDownloadRSVDPage88ES(): 1 Download RSVD page failed!\n")); + /* RT_ASSERT(bcn_valid, ("HalDownloadRSVDPage88ES(): 1 Download RSVD page failed!\n")); */ if(padapter->bSurpriseRemoved || padapter->bDriverStopped) { } @@ -1006,13 +999,13 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus) DBG_871X("%s: 1 Download RSVD page failed! DLBcnCount:%u, poll:%u\n", __FUNCTION__ ,DLBcnCount, poll); else DBG_871X("%s: 1 Download RSVD success! DLBcnCount:%u, poll:%u\n", __FUNCTION__, DLBcnCount, poll); - // - // We just can send the reserved page twice during the time that Tx thread is stopped (e.g. pnpsetpower) - // becuase we need to free the Tx BCN Desc which is used by the first reserved page packet. - // At run time, we cannot get the Tx Desc until it is released in TxHandleInterrupt() so we will return - // the beacon TCB in the following code. 2011.11.23. by tynli. - // - //if(bcn_valid && padapter->bEnterPnpSleep) + /* */ + /* We just can send the reserved page twice during the time that Tx thread is stopped (e.g. pnpsetpower) */ + /* becuase we need to free the Tx BCN Desc which is used by the first reserved page packet. */ + /* At run time, we cannot get the Tx Desc until it is released in TxHandleInterrupt() so we will return */ + /* the beacon TCB in the following code. 2011.11.23. by tynli. */ + /* */ + /* if(bcn_valid && padapter->bEnterPnpSleep) */ if(0) { if(bSendBeacon) @@ -1028,14 +1021,14 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus) do { rtw_yield_os(); - //rtw_mdelay_os(10); - // check rsvd page download OK. + /* rtw_mdelay_os(10); */ + /* check rsvd page download OK. */ rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8*)(&bcn_valid)); poll++; } while(!bcn_valid && (poll%10)!=0 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped); }while(!bcn_valid && DLBcnCount<=100 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped); - //RT_ASSERT(bcn_valid, ("HalDownloadRSVDPage(): 2 Download RSVD page failed!\n")); + /* RT_ASSERT(bcn_valid, ("HalDownloadRSVDPage(): 2 Download RSVD page failed!\n")); */ if(padapter->bSurpriseRemoved || padapter->bDriverStopped) { } @@ -1046,37 +1039,37 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus) } } - // Enable Bcn - //SetBcnCtrlReg(padapter, BIT3, 0); - //SetBcnCtrlReg(padapter, 0, BIT4); + /* Enable Bcn */ + /* SetBcnCtrlReg(padapter, BIT3, 0); */ + /* SetBcnCtrlReg(padapter, 0, BIT4); */ rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(3)); rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)&(~BIT(4))); - // To make sure that if there exists an adapter which would like to send beacon. - // If exists, the origianl value of 0x422[6] will be 1, we should check this to - // prevent from setting 0x422[6] to 0 after download reserved page, or it will cause - // the beacon cannot be sent by HW. - // 2010.06.23. Added by tynli. + /* To make sure that if there exists an adapter which would like to send beacon. */ + /* If exists, the origianl value of 0x422[6] will be 1, we should check this to */ + /* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */ + /* the beacon cannot be sent by HW. */ + /* 2010.06.23. Added by tynli. */ if(bSendBeacon) { rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl|BIT6)); pHalData->RegFwHwTxQCtrl |= BIT6; } - // - // Update RSVD page location H2C to Fw. - // + /* */ + /* Update RSVD page location H2C to Fw. */ + /* */ if(bcn_valid) { rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL); DBG_871X("Set RSVD page location to Fw.\n"); - //FillH2CCmd88E(Adapter, H2C_88E_RSVDPAGE, H2C_RSVDPAGE_LOC_LENGTH, pMgntInfo->u1RsvdPageLoc); + /* FillH2CCmd88E(Adapter, H2C_88E_RSVDPAGE, H2C_RSVDPAGE_LOC_LENGTH, pMgntInfo->u1RsvdPageLoc); */ } - // Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli. - //if(!padapter->bEnterPnpSleep) + /* Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli. */ + /* if(!padapter->bEnterPnpSleep) */ { - // Clear CR[8] or beacon packet will not be send to TxBuf anymore. + /* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */ pHalData->RegCR_1 &= (~BIT0); rtw_write8(padapter, REG_CR+1, pHalData->RegCR_1); } @@ -1095,7 +1088,7 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus) } else { DBG_871X_LEVEL(_drv_info_, "%s wowlan_mode is off\n", __func__); } -#endif //CONFIG_WOWLAN +#endif /* CONFIG_WOWLAN */ ; } @@ -1119,40 +1112,40 @@ void rtl8188e_set_p2p_ps_offload_cmd(struct adapter* padapter, u8 p2p_ps_state) break; case P2P_PS_ENABLE: DBG_8192C("P2P_PS_ENABLE \n"); - // update CTWindow value. + /* update CTWindow value. */ if( pwdinfo->ctwindow > 0 ) { p2p_ps_offload->CTWindow_En = 1; rtw_write8(padapter, REG_P2P_CTWIN, pwdinfo->ctwindow); } - // hw only support 2 set of NoA + /* hw only support 2 set of NoA */ for( i=0 ; inoa_num ; i++) { - // To control the register setting for which NOA + /* To control the register setting for which NOA */ rtw_write8(padapter, REG_NOA_DESC_SEL, (i << 4)); if(i == 0) p2p_ps_offload->NoA0_En = 1; else p2p_ps_offload->NoA1_En = 1; - // config P2P NoA Descriptor Register - //DBG_8192C("%s(): noa_duration = %x\n",__FUNCTION__,pwdinfo->noa_duration[i]); + /* config P2P NoA Descriptor Register */ + /* DBG_8192C("%s(): noa_duration = %x\n",__FUNCTION__,pwdinfo->noa_duration[i]); */ rtw_write32(padapter, REG_NOA_DESC_DURATION, pwdinfo->noa_duration[i]); - //DBG_8192C("%s(): noa_interval = %x\n",__FUNCTION__,pwdinfo->noa_interval[i]); + /* DBG_8192C("%s(): noa_interval = %x\n",__FUNCTION__,pwdinfo->noa_interval[i]); */ rtw_write32(padapter, REG_NOA_DESC_INTERVAL, pwdinfo->noa_interval[i]); - //DBG_8192C("%s(): start_time = %x\n",__FUNCTION__,pwdinfo->noa_start_time[i]); + /* DBG_8192C("%s(): start_time = %x\n",__FUNCTION__,pwdinfo->noa_start_time[i]); */ rtw_write32(padapter, REG_NOA_DESC_START, pwdinfo->noa_start_time[i]); - //DBG_8192C("%s(): noa_count = %x\n",__FUNCTION__,pwdinfo->noa_count[i]); + /* DBG_8192C("%s(): noa_count = %x\n",__FUNCTION__,pwdinfo->noa_count[i]); */ rtw_write8(padapter, REG_NOA_DESC_COUNT, pwdinfo->noa_count[i]); } if( (pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0) ) { - // rst p2p circuit + /* rst p2p circuit */ rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(4)); p2p_ps_offload->Offload_En = 1; @@ -1189,7 +1182,7 @@ void rtl8188e_set_p2p_ps_offload_cmd(struct adapter* padapter, u8 p2p_ps_state) ; } -#endif //CONFIG_P2P_PS +#endif /* CONFIG_P2P_PS */ #ifdef CONFIG_TSF_RESET_OFFLOAD /* @@ -1237,7 +1230,7 @@ int reset_tsf(struct adapter *Adapter, u8 reset_port ) } -#endif // CONFIG_TSF_RESET_OFFLOAD +#endif /* CONFIG_TSF_RESET_OFFLOAD */ #ifdef CONFIG_WOWLAN #ifdef CONFIG_GPIO_WAKEUP @@ -1281,7 +1274,7 @@ void rtl8188es_set_output_gpio(struct adapter* padapter, u8 index, u8 outputval) } } } -#endif //CONFIG_GPIO_WAKEUP +#endif /* CONFIG_GPIO_WAKEUP */ void rtl8188es_set_wowlan_cmd(struct adapter* padapter, u8 enable) { @@ -1294,7 +1287,7 @@ void rtl8188es_set_wowlan_cmd(struct adapter* padapter, u8 enable) struct security_priv *psecpriv = &padapter->securitypriv; #ifdef CONFIG_GPIO_WAKEUP u8 gpio_wake_pin = 7; - u8 gpio_high_active = 0; //default low active + u8 gpio_high_active = 0; /* default low active */ #endif ; @@ -1329,16 +1322,16 @@ void rtl8188es_set_wowlan_cmd(struct adapter* padapter, u8 enable) pwowlan_parm.mode |=FW_WOWLAN_REKEY_WAKEUP; pwowlan_parm.mode |=FW_WOWLAN_DEAUTH_WAKEUP; - //DataPinWakeUp + /* DataPinWakeUp */ pwowlan_parm.gpio_index=0x0; #ifdef CONFIG_GPIO_WAKEUP pwowlan_parm.gpio_index = gpio_wake_pin; - //WOWLAN_GPIO_ACTIVE means GPIO high active - //pwowlan_parm.mode |=FW_WOWLAN_GPIO_ACTIVE; + /* WOWLAN_GPIO_ACTIVE means GPIO high active */ + /* pwowlan_parm.mode |=FW_WOWLAN_GPIO_ACTIVE; */ if (gpio_high_active) pwowlan_parm.mode |=FW_WOWLAN_GPIO_ACTIVE; -#endif //CONFIG_GPIO_WAKEUP +#endif /* CONFIG_GPIO_WAKEUP */ DBG_871X_LEVEL(_drv_info_, "%s 5.pwowlan_parm.mode=0x%x \n",__FUNCTION__,pwowlan_parm.mode); DBG_871X_LEVEL(_drv_info_, "%s 6.pwowlan_parm.index=0x%x \n",__FUNCTION__,pwowlan_parm.gpio_index); @@ -1346,19 +1339,19 @@ void rtl8188es_set_wowlan_cmd(struct adapter* padapter, u8 enable) rtw_msleep_os(2); - //disconnect decision + /* disconnect decision */ pwowlan_parm.mode =1; pwowlan_parm.gpio_index=0; pwowlan_parm.gpio_duration=0; FillH2CCmd_88E(padapter, H2C_COM_DISCNT_DECISION, 3, (u8 *)&pwowlan_parm); - //keep alive period = 10 * 10 BCN interval + /* keep alive period = 10 * 10 BCN interval */ pwowlan_parm.mode = FW_WOWLAN_KEEP_ALIVE_EN | FW_ADOPT_USER | FW_WOWLAN_KEEP_ALIVE_PKT_TYPE; pwowlan_parm.gpio_index=10; res = FillH2CCmd_88E(padapter, H2C_COM_KEEP_ALIVE, 2, (u8 *)&pwowlan_parm); rtw_msleep_os(2); - //Configure STA security information for GTK rekey wakeup event. + /* Configure STA security information for GTK rekey wakeup event. */ paoac_global_info_parm.pairwiseEncAlg= padapter->securitypriv.dot11PrivacyAlgrthm; paoac_global_info_parm.groupEncAlg= @@ -1366,7 +1359,7 @@ void rtl8188es_set_wowlan_cmd(struct adapter* padapter, u8 enable) res = FillH2CCmd_88E(padapter, H2C_COM_AOAC_GLOBAL_INFO, 2, (u8 *)&paoac_global_info_parm); rtw_msleep_os(2); - //enable Remote wake ctrl + /* enable Remote wake ctrl */ pwowlan_parm.mode = FW_REMOTE_WAKE_CTRL_EN | FW_WOW_FW_UNICAST_EN | FW_ARP_EN; if (psecpriv->dot11PrivacyAlgrthm == _AES_ || psecpriv->dot11PrivacyAlgrthm == _NO_PRIVACY_) { @@ -1381,7 +1374,7 @@ void rtl8188es_set_wowlan_cmd(struct adapter* padapter, u8 enable) pwrpriv->wowlan_magic =false; #ifdef CONFIG_GPIO_WAKEUP rtl8188es_set_output_gpio(padapter, gpio_wake_pin, !gpio_high_active); -#endif //CONFIG_GPIO_WAKEUP +#endif /* CONFIG_GPIO_WAKEUP */ res = FillH2CCmd_88E(padapter, H2C_COM_WWLAN, 2, (u8 *)&pwowlan_parm); rtw_msleep_os(2); res = FillH2CCmd_88E(padapter, H2C_COM_REMOTE_WAKE_CTRL, 3, (u8 *)&pwowlan_parm); @@ -1390,4 +1383,4 @@ void rtl8188es_set_wowlan_cmd(struct adapter* padapter, u8 enable) DBG_871X_LEVEL(_drv_always_, "-%s res:%d-\n", __func__, res); return ; } -#endif //CONFIG_WOWLAN +#endif /* CONFIG_WOWLAN */ diff --git a/hal/rtl8188e_dm.c b/hal/rtl8188e_dm.c index 983c317..68ebb4e 100755 --- a/hal/rtl8188e_dm.c +++ b/hal/rtl8188e_dm.c @@ -17,27 +17,27 @@ * * ******************************************************************************/ -//============================================================ -// Description: -// -// This file is for 92CE/92CU dynamic mechanism only -// -// -//============================================================ +/* */ +/* Description: */ +/* */ +/* This file is for 92CE/92CU dynamic mechanism only */ +/* */ +/* */ +/* */ #define _RTL8188E_DM_C_ -//============================================================ -// include files -//============================================================ +/* */ +/* include files */ +/* */ #include #include #include #include -//============================================================ -// Global var -//============================================================ +/* */ +/* Global var */ +/* */ static void @@ -64,14 +64,14 @@ static void dm_CheckPbcGPIO(struct adapter *padapter) tmp1byte = rtw_read8(padapter, GPIO_IO_SEL); tmp1byte |= (HAL_8188E_HW_GPIO_WPS_BIT); - rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); //enable GPIO[2] as output mode + rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); /* enable GPIO[2] as output mode */ tmp1byte &= ~(HAL_8188E_HW_GPIO_WPS_BIT); - rtw_write8(padapter, GPIO_IN, tmp1byte); //reset the floating voltage level + rtw_write8(padapter, GPIO_IN, tmp1byte); /* reset the floating voltage level */ tmp1byte = rtw_read8(padapter, GPIO_IO_SEL); tmp1byte &= ~(HAL_8188E_HW_GPIO_WPS_BIT); - rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); //enable GPIO[2] as input mode + rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); /* enable GPIO[2] as input mode */ tmp1byte =rtw_read8(padapter, GPIO_IN); @@ -84,8 +84,8 @@ static void dm_CheckPbcGPIO(struct adapter *padapter) } if( true == bPbcPressed) { - // Here we only set bPbcPressed to true - // After trigger PBC, the variable will be set to false + /* Here we only set bPbcPressed to true */ + /* After trigger PBC, the variable will be set to false */ DBG_8192C("CheckPbcGPIO - PBC is pressed\n"); #ifdef RTK_DMP_PLATFORM @@ -97,7 +97,7 @@ static void dm_CheckPbcGPIO(struct adapter *padapter) #else if ( padapter->pid[0] == 0 ) - { // 0 is the default value and it means the application monitors the HW PBC doesn't privde its pid to driver. + { /* 0 is the default value and it means the application monitors the HW PBC doesn't privde its pid to driver. */ return; } rtw_signal_process(padapter->pid[0], SIGUSR1); @@ -105,9 +105,9 @@ static void dm_CheckPbcGPIO(struct adapter *padapter) } } -// -// Initialize GPIO setting registers -// +/* */ +/* Initialize GPIO setting registers */ +/* */ static void dm_InitGPIOSetting( IN struct adapter *Adapter @@ -121,7 +121,7 @@ dm_InitGPIOSetting( tmp1byte &= (GPIOSEL_GPIO | ~GPIOSEL_ENBT); #ifdef CONFIG_BT_COEXIST - // UMB-B cut bug. We need to support the modification. + /* UMB-B cut bug. We need to support the modification. */ if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID) && pHalData->bt_coexist.BT_Coexist) { @@ -132,9 +132,9 @@ dm_InitGPIOSetting( } -//============================================================ -// functions -//============================================================ +/* */ +/* functions */ +/* */ static void Init_ODM_ComInfo_88E(struct adapter *Adapter) { @@ -143,9 +143,9 @@ static void Init_ODM_ComInfo_88E(struct adapter *Adapter) PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); u8 cut_ver,fab_ver; - // - // Init Value - // + /* */ + /* Init Value */ + /* */ memset(pDM_Odm, 0, sizeof(*pDM_Odm)); pDM_Odm->Adapter = Adapter; @@ -155,7 +155,7 @@ static void Init_ODM_ComInfo_88E(struct adapter *Adapter) if(Adapter->interface_type == RTW_GSPI ) ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,ODM_ITRF_SDIO); else - ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,Adapter->interface_type);//RTL871X_HCI_TYPE + ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,Adapter->interface_type);/* RTL871X_HCI_TYPE */ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_IC_TYPE,ODM_RTL8188E); @@ -168,7 +168,7 @@ static void Init_ODM_ComInfo_88E(struct adapter *Adapter) ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP,IS_NORMAL_CHIP(pHalData->VersionID)); ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_PATCH_ID,pHalData->CustomerID); - // ODM_CMNINFO_BINHCT_TEST only for MP Team + /* ODM_CMNINFO_BINHCT_TEST only for MP Team */ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_BWIFI_TEST,Adapter->registrypriv.wifi_spec); @@ -188,10 +188,10 @@ static void Init_ODM_ComInfo_88E(struct adapter *Adapter) pdmpriv->InitODMFlag = 0; #else pdmpriv->InitODMFlag = ODM_RF_CALIBRATION | - ODM_RF_TX_PWR_TRACK //| + ODM_RF_TX_PWR_TRACK /* */ ; - //if(pHalData->AntDivCfg) - // pdmpriv->InitODMFlag |= ODM_BB_ANT_DIV; + /* if(pHalData->AntDivCfg) */ + /* pdmpriv->InitODMFlag |= ODM_BB_ANT_DIV; */ #endif ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_ABILITY,pdmpriv->InitODMFlag); @@ -238,11 +238,11 @@ static void Update_ODM_ComInfo_88E(struct adapter *Adapter) | ODM_RF_TX_PWR_TRACK ; } -#endif//(MP_DRIVER==1) +#endif/* MP_DRIVER==1) */ #ifdef CONFIG_DISABLE_ODM pdmpriv->InitODMFlag = 0; -#endif//CONFIG_DISABLE_ODM +#endif/* CONFIG_DISABLE_ODM */ ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_ABILITY,pdmpriv->InitODMFlag); @@ -257,18 +257,7 @@ static void Update_ODM_ComInfo_88E(struct adapter *Adapter) ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_MP_MODE,&(Adapter->registrypriv.mp_mode)); ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BAND,&(pDM_Odm->u8_temp)); - //================= only for 8192D ================= - /* - //pHalData->CurrentBandType92D - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BAND,&(pDM_Odm->u8_temp)); - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_GET_VALUE,&(pDM_Odm->u8_temp)); - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BUDDY_ADAPTOR,&(pDM_Odm->PADAPTER_temp)); - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_IS_MASTER,&(pDM_Odm->u8_temp)); - //================= only for 8192D ================= - // driver havn't those variable now - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_OPERATION,&(pDM_Odm->u8_temp)); - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_DISABLE_EDCA,&(pDM_Odm->u8_temp)); - */ + /* only for 8192D ================= */ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SCAN,&(pmlmepriv->bScanInProcess)); ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_POWER_SAVING,&(pwrctrlpriv->bpower_saving)); @@ -276,7 +265,7 @@ static void Update_ODM_ComInfo_88E(struct adapter *Adapter) for(i=0; i< NUM_STA; i++) { - //pDM_Odm->pODM_StaInfo[i] = NULL; + /* pDM_Odm->pODM_StaInfo[i] = NULL; */ ODM_CmnInfoPtrArrayHook(pDM_Odm, ODM_CMNINFO_STA_STATUS,i,NULL); } } @@ -327,23 +316,23 @@ rtl8188e_HalDmWatchDog( #endif #ifdef CONFIG_P2P_PS - // Fw is under p2p powersaving mode, driver should stop dynamic mechanism. - // modifed by thomas. 2011.06.11. + /* Fw is under p2p powersaving mode, driver should stop dynamic mechanism. */ + /* modifed by thomas. 2011.06.11. */ if(Adapter->wdinfo.p2p_ps_mode) bFwPSAwake = false; -#endif //CONFIG_P2P_PS +#endif /* CONFIG_P2P_PS */ if( (hw_init_completed == true) && ((!bFwCurrentInPSMode) && bFwPSAwake)) { - // - // Calculate Tx/Rx statistics. - // + /* */ + /* Calculate Tx/Rx statistics. */ + /* */ dm_CheckStatistics(Adapter); } - //ODM + /* ODM */ if (hw_init_completed == true) { u8 bLinked=false; @@ -369,8 +358,8 @@ rtl8188e_HalDmWatchDog( skip_dm: - // Check GPIO to determine current RF on/off and Pbc status. - // Check Hardware Radio ON/OFF or not + /* Check GPIO to determine current RF on/off and Pbc status. */ + /* Check Hardware Radio ON/OFF or not */ return; } @@ -380,10 +369,10 @@ void rtl8188e_init_dm_priv(IN struct adapter *Adapter) struct dm_priv *pdmpriv = &pHalData->dmpriv; PDM_ODM_T podmpriv = &pHalData->odmpriv; memset(pdmpriv, 0, sizeof(struct dm_priv)); - //_rtw_spinlock_init(&(pHalData->odm_stainfo_lock)); + /* _rtw_spinlock_init(&(pHalData->odm_stainfo_lock)); */ Init_ODM_ComInfo_88E(Adapter); #ifdef CONFIG_SW_ANTENNA_DIVERSITY - //_init_timer(&(pdmpriv->SwAntennaSwitchTimer), Adapter->pnetdev , odm_SW_AntennaSwitchCallback, Adapter); + /* _init_timer(&(pdmpriv->SwAntennaSwitchTimer), Adapter->pnetdev , odm_SW_AntennaSwitchCallback, Adapter); */ ODM_InitAllTimers(podmpriv ); #endif ODM_InitDebugSetting(podmpriv); @@ -394,29 +383,29 @@ void rtl8188e_deinit_dm_priv(IN struct adapter *Adapter) PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); struct dm_priv *pdmpriv = &pHalData->dmpriv; PDM_ODM_T podmpriv = &pHalData->odmpriv; - //_rtw_spinlock_free(&pHalData->odm_stainfo_lock); + /* _rtw_spinlock_free(&pHalData->odm_stainfo_lock); */ #ifdef CONFIG_SW_ANTENNA_DIVERSITY - //_cancel_timer_ex(&pdmpriv->SwAntennaSwitchTimer); + /* _cancel_timer_ex(&pdmpriv->SwAntennaSwitchTimer); */ ODM_CancelAllTimers(podmpriv); #endif } #ifdef CONFIG_ANTENNA_DIVERSITY -// Add new function to reset the state of antenna diversity before link. -// -// Compare RSSI for deciding antenna +/* Add new function to reset the state of antenna diversity before link. */ +/* */ +/* Compare RSSI for deciding antenna */ void AntDivCompare8188E(struct adapter *Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src) { - //struct adapter *Adapter = pDM_Odm->Adapter ; + /* struct adapter *Adapter = pDM_Odm->Adapter ; */ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); if(0 != pHalData->AntDivCfg ) { - //DBG_8192C("update_network=> orgRSSI(%d)(%d),newRSSI(%d)(%d)\n",dst->Rssi,query_rx_pwr_percentage(dst->Rssi), - // src->Rssi,query_rx_pwr_percentage(src->Rssi)); - //select optimum_antenna for before linked =>For antenna diversity - if(dst->Rssi >= src->Rssi )//keep org parameter + /* DBG_8192C("update_network=> orgRSSI(%d)(%d),newRSSI(%d)(%d)\n",dst->Rssi,query_rx_pwr_percentage(dst->Rssi), */ + /* src->Rssi,query_rx_pwr_percentage(src->Rssi)); */ + /* select optimum_antenna for before linked =>For antenna diversity */ + if(dst->Rssi >= src->Rssi )/* keep org parameter */ { src->Rssi = dst->Rssi; src->PhyInfo.Optimum_antenna = dst->PhyInfo.Optimum_antenna; @@ -424,7 +413,7 @@ void AntDivCompare8188E(struct adapter *Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_ } } -// Add new function to reset the state of antenna diversity before link. +/* Add new function to reset the state of antenna diversity before link. */ u8 AntDivBeforeLink8188E(struct adapter *Adapter ) { @@ -433,10 +422,10 @@ u8 AntDivBeforeLink8188E(struct adapter *Adapter ) SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); - // Condition that does not need to use antenna diversity. + /* Condition that does not need to use antenna diversity. */ if(pHalData->AntDivCfg==0) { - //DBG_8192C("odm_AntDivBeforeLink8192C(): No AntDiv Mechanism.\n"); + /* DBG_8192C("odm_AntDivBeforeLink8192C(): No AntDiv Mechanism.\n"); */ return false; } @@ -447,13 +436,13 @@ u8 AntDivBeforeLink8188E(struct adapter *Adapter ) if(pDM_SWAT_Table->SWAS_NoLink_State == 0){ - //switch channel + /* switch channel */ pDM_SWAT_Table->SWAS_NoLink_State = 1; pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A; - //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, pDM_SWAT_Table->CurAntenna); + /* PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, pDM_SWAT_Table->CurAntenna); */ rtw_antenna_select_cmd(Adapter, pDM_SWAT_Table->CurAntenna, false); - //DBG_8192C("%s change antenna to ANT_( %s ).....\n",__FUNCTION__, (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B"); + /* DBG_8192C("%s change antenna to ANT_( %s ).....\n",__FUNCTION__, (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B"); */ return true; } else diff --git a/hal/rtl8188e_hal_init.c b/hal/rtl8188e_hal_init.c index 596d78f..3c51774 100755 --- a/hal/rtl8188e_hal_init.c +++ b/hal/rtl8188e_hal_init.c @@ -35,9 +35,9 @@ static void iol_mode_enable(struct adapter *padapter, u8 enable) if(enable) { - //Enable initial offload + /* Enable initial offload */ reg_0xf0 = rtw_read8(padapter, REG_SYS_CFG); - //DBG_871X("%s reg_0xf0:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0xf0, reg_0xf0|SW_OFFLOAD_EN); + /* DBG_871X("%s reg_0xf0:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0xf0, reg_0xf0|SW_OFFLOAD_EN); */ rtw_write8(padapter, REG_SYS_CFG, reg_0xf0|SW_OFFLOAD_EN); if(padapter->bFWReady == false) @@ -49,9 +49,9 @@ static void iol_mode_enable(struct adapter *padapter, u8 enable) } else { - //disable initial offload + /* disable initial offload */ reg_0xf0 = rtw_read8(padapter, REG_SYS_CFG); - //DBG_871X("%s reg_0xf0:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0xf0, reg_0xf0& ~SW_OFFLOAD_EN); + /* DBG_871X("%s reg_0xf0:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0xf0, reg_0xf0& ~SW_OFFLOAD_EN); */ rtw_write8(padapter, REG_SYS_CFG, reg_0xf0 & ~SW_OFFLOAD_EN); } } @@ -65,17 +65,17 @@ static s32 iol_execute(struct adapter *padapter, u8 control) u32 t1,t2; control = control&0x0f; reg_0x88 = rtw_read8(padapter, REG_HMEBOX_E0); - //DBG_871X("%s reg_0x88:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0x88, reg_0x88|control); + /* DBG_871X("%s reg_0x88:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0x88, reg_0x88|control); */ rtw_write8(padapter, REG_HMEBOX_E0, reg_0x88|control); t1 = start = rtw_get_current_time(); while( - //(reg_1c7 = rtw_read8(padapter, 0x1c7) >1) && + /* reg_1c7 = rtw_read8(padapter, 0x1c7) >1) && */ (reg_0x88=rtw_read8(padapter, REG_HMEBOX_E0)) & control && (passing_time=rtw_get_passing_time_ms(start))<1000 ) { - //DBG_871X("%s polling reg_0x88:0x%02x,reg_0x1c7:0x%02x\n", __FUNCTION__, reg_0x88,rtw_read8(padapter, 0x1c7) ); - //rtw_udelay_os(100); + /* DBG_871X("%s polling reg_0x88:0x%02x,reg_0x1c7:0x%02x\n", __FUNCTION__, reg_0x88,rtw_read8(padapter, 0x1c7) ); */ + /* rtw_udelay_os(100); */ } reg_0x88 = rtw_read8(padapter, REG_HMEBOX_E0); @@ -83,8 +83,8 @@ static s32 iol_execute(struct adapter *padapter, u8 control) if(reg_0x88 & control<<4) status = _FAIL; t2= rtw_get_current_time(); - //printk("==> step iol_execute : %5u reg-0x1c0= 0x%02x\n",rtw_get_time_interval_ms(t1,t2),rtw_read8(padapter, 0x1c0)); - //DBG_871X("%s in %u ms, reg_0x88:0x%02x\n", __FUNCTION__, passing_time, reg_0x88); + /* printk("==> step iol_execute : %5u reg-0x1c0= 0x%02x\n",rtw_get_time_interval_ms(t1,t2),rtw_read8(padapter, 0x1c0)); */ + /* DBG_871X("%s in %u ms, reg_0x88:0x%02x\n", __FUNCTION__, passing_time, reg_0x88); */ return status; } @@ -96,7 +96,7 @@ static s32 iol_InitLLTTable( { s32 rst = _SUCCESS; iol_mode_enable(padapter, 1); - //DBG_871X("%s txpktbuf_bndy:%u\n", __FUNCTION__, txpktbuf_bndy); + /* DBG_871X("%s txpktbuf_bndy:%u\n", __FUNCTION__, txpktbuf_bndy); */ rtw_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy); rst = iol_execute(padapter, CMD_INIT_LLT); iol_mode_enable(padapter, 0); @@ -131,20 +131,20 @@ efuse_phymap_to_logical(u8 * phymap, u16 _offset, u16 _size_byte, u8 *pbuf) goto exit; } - // 0. Refresh efuse init map as all oxFF. + /* 0. Refresh efuse init map as all oxFF. */ for (i = 0; i < EFUSE_MAX_SECTION_88E; i++) for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) eFuseWord[i][j] = 0xFFFF; - // - // 1. Read the first byte to check if efuse is empty!!! - // - // + /* */ + /* 1. Read the first byte to check if efuse is empty!!! */ + /* */ + /* */ rtemp8 = *(phymap+eFuse_Addr); if(rtemp8 != 0xFF) { efuse_utilized++; - //printk("efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8); + /* printk("efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8); */ eFuse_Addr++; } else @@ -154,24 +154,24 @@ efuse_phymap_to_logical(u8 * phymap, u16 _offset, u16 _size_byte, u8 *pbuf) } - // - // 2. Read real efuse content. Filter PG header and every section data. - // + /* */ + /* 2. Read real efuse content. Filter PG header and every section data. */ + /* */ while((rtemp8 != 0xFF) && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) { - //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("efuse_Addr-%d efuse_data=%x\n", eFuse_Addr-1, *rtemp8)); + /* RTPRINT(FEEPROM, EFUSE_READ_ALL, ("efuse_Addr-%d efuse_data=%x\n", eFuse_Addr-1, *rtemp8)); */ - // Check PG header for section num. - if((rtemp8 & 0x1F ) == 0x0F) //extended header + /* Check PG header for section num. */ + if((rtemp8 & 0x1F ) == 0x0F) /* extended header */ { u1temp =( (rtemp8 & 0xE0) >> 5); - //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header u1temp=%x *rtemp&0xE0 0x%x\n", u1temp, *rtemp8 & 0xE0)); + /* RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header u1temp=%x *rtemp&0xE0 0x%x\n", u1temp, *rtemp8 & 0xE0)); */ - //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header u1temp=%x \n", u1temp)); + /* RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header u1temp=%x \n", u1temp)); */ rtemp8 = *(phymap+eFuse_Addr); - //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8)); + /* RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8)); */ if((rtemp8 & 0x0F) == 0x0F) { @@ -199,18 +199,18 @@ efuse_phymap_to_logical(u8 * phymap, u16 _offset, u16 _size_byte, u8 *pbuf) if(offset < EFUSE_MAX_SECTION_88E) { - // Get word enable value from PG header - //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Offset-%d Worden=%x\n", offset, wren)); + /* Get word enable value from PG header */ + /* RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Offset-%d Worden=%x\n", offset, wren)); */ for(i=0; i= EFUSE_REAL_CONTENT_LEN_88E) break; - //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d", eFuse_Addr)); + /* RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d", eFuse_Addr)); */ rtemp8 = *(phymap+eFuse_Addr); eFuse_Addr++; - //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Data=0x%x\n", *rtemp8)); + /* RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Data=0x%x\n", *rtemp8)); */ efuse_utilized++; eFuseWord[offset][i] |= (((u16)rtemp8 << 8) & 0xff00); @@ -235,9 +235,9 @@ efuse_phymap_to_logical(u8 * phymap, u16 _offset, u16 _size_byte, u8 *pbuf) } } - // Read next PG header + /* Read next PG header */ rtemp8 = *(phymap+eFuse_Addr); - //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d rtemp 0x%x\n", eFuse_Addr, *rtemp8)); + /* RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d rtemp 0x%x\n", eFuse_Addr, *rtemp8)); */ if(rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) { @@ -246,9 +246,9 @@ efuse_phymap_to_logical(u8 * phymap, u16 _offset, u16 _size_byte, u8 *pbuf) } } - // - // 3. Collect 16 sections and 4 word unit into Efuse map. - // + /* */ + /* 3. Collect 16 sections and 4 word unit into Efuse map. */ + /* */ for(i=0; iHalFunc.SetHwRegHandler(Adapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_utilized); + /* Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_utilized); */ exit: if(efuseTbl) @@ -283,9 +283,9 @@ exit: static void efuse_read_phymap_from_txpktbuf( struct adapter *adapter, - int bcnhead, //beacon head, where FW store len(2-byte) and efuse physical map. - u8 *content, //buffer to store efuse physical map - u16 *size //for efuse content: the max byte to read. will update to byte read + int bcnhead, /* beacon head, where FW store len(2-byte) and efuse physical map. */ + u8 *content, /* buffer to store efuse physical map */ + u16 *size /* for efuse content: the max byte to read. will update to byte read */ ) { u16 dbg_addr = 0; @@ -299,28 +299,28 @@ static void efuse_read_phymap_from_txpktbuf( u8 *pos = content; - if(bcnhead<0) //if not valid + if(bcnhead<0) /* if not valid */ bcnhead = rtw_read8(adapter, REG_TDECTRL+1); DBG_871X("%s bcnhead:%d\n", __FUNCTION__, bcnhead); - //reg_0x106 = rtw_read8(adapter, REG_PKT_BUFF_ACCESS_CTRL); - //DBG_871X("%s reg_0x106:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0x106, 0x69); + /* reg_0x106 = rtw_read8(adapter, REG_PKT_BUFF_ACCESS_CTRL); */ + /* DBG_871X("%s reg_0x106:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0x106, 0x69); */ rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT); - //DBG_871X("%s reg_0x106:0x%02x\n", __FUNCTION__, rtw_read8(adapter, 0x106)); + /* DBG_871X("%s reg_0x106:0x%02x\n", __FUNCTION__, rtw_read8(adapter, 0x106)); */ - dbg_addr = bcnhead*128/8; //8-bytes addressing + dbg_addr = bcnhead*128/8; /* 8-bytes addressing */ while(1) { - //DBG_871X("%s dbg_addr:0x%x\n", __FUNCTION__, dbg_addr+i); + /* DBG_871X("%s dbg_addr:0x%x\n", __FUNCTION__, dbg_addr+i); */ rtw_write16(adapter, REG_PKTBUF_DBG_ADDR, dbg_addr+i); - //DBG_871X("%s write reg_0x143:0x00\n", __FUNCTION__); + /* DBG_871X("%s write reg_0x143:0x00\n", __FUNCTION__); */ rtw_write8(adapter, REG_TXPKTBUF_DBG, 0); start = rtw_get_current_time(); - while(!(reg_0x143=rtw_read8(adapter, REG_TXPKTBUF_DBG))//dbg - //while(rtw_read8(adapter, REG_TXPKTBUF_DBG) & BIT0 + while(!(reg_0x143=rtw_read8(adapter, REG_TXPKTBUF_DBG))/* dbg */ + /* while(rtw_read8(adapter, REG_TXPKTBUF_DBG) & BIT0 */ && (passing_time=rtw_get_passing_time_ms(start))<1000 ) { DBG_871X("%s polling reg_0x143:0x%02x, reg_0x106:0x%02x\n", __FUNCTION__, reg_0x143, rtw_read8(adapter, 0x106)); @@ -388,10 +388,10 @@ static s32 iol_read_efuse( rtw_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy); memset(physical_map, 0xFF, 512); - ///reg_0x106 = rtw_read8(padapter, REG_PKT_BUFF_ACCESS_CTRL); - //DBG_871X("%s reg_0x106:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0x106, 0x69); + /* reg_0x106 = rtw_read8(padapter, REG_PKT_BUFF_ACCESS_CTRL); */ + /* DBG_871X("%s reg_0x106:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0x106, 0x69); */ rtw_write8(padapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT); - //DBG_871X("%s reg_0x106:0x%02x\n", __FUNCTION__, rtw_read8(padapter, 0x106)); + /* DBG_871X("%s reg_0x106:0x%02x\n", __FUNCTION__, rtw_read8(padapter, 0x106)); */ status = iol_execute(padapter, CMD_READ_EFUSE_MAP); @@ -426,7 +426,7 @@ static s32 iol_ioconfig( { s32 rst = _SUCCESS; - //DBG_871X("%s iocfg_bndy:%u\n", __FUNCTION__, iocfg_bndy); + /* DBG_871X("%s iocfg_bndy:%u\n", __FUNCTION__, iocfg_bndy); */ rtw_write8(padapter, REG_TDECTRL+1, iocfg_bndy); rst = iol_execute(padapter, CMD_IOCONFIG); @@ -442,7 +442,7 @@ static int rtl8188e_IOL_exec_cmds_sync(struct adapter *adapter, struct xmit_fram int ret = _FAIL; u32 t1,t2; - //printk("===> %s ,bndy_cnt = %d \n",__FUNCTION__,bndy_cnt); + /* printk("===> %s ,bndy_cnt = %d \n",__FUNCTION__,bndy_cnt); */ if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS) goto exit; { @@ -461,7 +461,7 @@ static int rtl8188e_IOL_exec_cmds_sync(struct adapter *adapter, struct xmit_fram for(i=0;i %s : %5u\n",__FUNCTION__,rtw_get_time_interval_ms(t1,t2)); + /* printk("==> %s : %5u\n",__FUNCTION__,rtw_get_time_interval_ms(t1,t2)); */ exit: - //restore BCN_HEAD + /* restore BCN_HEAD */ rtw_write8(adapter, REG_TDECTRL+1, 0); return ret; } @@ -488,20 +488,20 @@ void rtw_IOL_cmd_tx_pkt_buf_dump(struct adapter *Adapter,int data_len) rtw_write8(Adapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT); if(pbuf){ for(addr=0;addr< data_cnts;addr++){ - //printk("==> addr:0x%02x\n",addr); + /* printk("==> addr:0x%02x\n",addr); */ rtw_write32(Adapter,0x140,addr); rtw_usleep_os(2); loop=0; do{ rstatus=(reg_140=rtw_read32(Adapter,REG_PKTBUF_DBG_CTRL)&BIT24); - //printk("rstatus = %02x, reg_140:0x%08x\n",rstatus,reg_140); + /* printk("rstatus = %02x, reg_140:0x%08x\n",rstatus,reg_140); */ if(rstatus){ fifo_data = rtw_read32(Adapter,REG_PKTBUF_DBG_DATA_L); - //printk("fifo_data_144:0x%08x\n",fifo_data); + /* printk("fifo_data_144:0x%08x\n",fifo_data); */ memcpy(pbuf+(addr*8),&fifo_data , 4); fifo_data = rtw_read32(Adapter,REG_PKTBUF_DBG_DATA_H); - //printk("fifo_data_148:0x%08x\n",fifo_data); + /* printk("fifo_data_148:0x%08x\n",fifo_data); */ memcpy(pbuf+(addr*8+4), &fifo_data, 4); } @@ -528,22 +528,22 @@ _FWDownloadEnable( if(enable) { - // MCU firmware download enable. + /* MCU firmware download enable. */ tmp = rtw_read8(padapter, REG_MCUFWDL); rtw_write8(padapter, REG_MCUFWDL, tmp|0x01); - // 8051 reset + /* 8051 reset */ tmp = rtw_read8(padapter, REG_MCUFWDL+2); rtw_write8(padapter, REG_MCUFWDL+2, tmp&0xf7); } else { - // MCU firmware download disable. + /* MCU firmware download disable. */ tmp = rtw_read8(padapter, REG_MCUFWDL); rtw_write8(padapter, REG_MCUFWDL, tmp&0xfe); - // Reserved for fw extension. + /* Reserved for fw extension. */ rtw_write8(padapter, REG_MCUFWDL+1, 0x00); } } @@ -557,16 +557,16 @@ _BlockWrite( { int ret = _SUCCESS; - u32 blockSize_p1 = 4; // (Default) Phase #1 : PCI muse use 4-byte write to download FW - u32 blockSize_p2 = 8; // Phase #2 : Use 8-byte, if Phase#1 use big size to write FW. - u32 blockSize_p3 = 1; // Phase #3 : Use 1-byte, the remnant of FW image. + u32 blockSize_p1 = 4; /* (Default) Phase #1 : PCI muse use 4-byte write to download FW */ + u32 blockSize_p2 = 8; /* Phase #2 : Use 8-byte, if Phase#1 use big size to write FW. */ + u32 blockSize_p3 = 1; /* Phase #3 : Use 1-byte, the remnant of FW image. */ u32 blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0; u32 remainSize_p1 = 0, remainSize_p2 = 0; u8 *bufferPtr = (u8*)buffer; u32 i=0, offset=0; blockSize_p1 = MAX_REG_BOLCK_SIZE; - //3 Phase #1 + /* 3 Phase #1 */ blockCount_p1 = buffSize / blockSize_p1; remainSize_p1 = buffSize % blockSize_p1; @@ -583,7 +583,7 @@ _BlockWrite( goto exit; } - //3 Phase #2 + /* 3 Phase #2 */ if (remainSize_p1) { offset = blockCount_p1 * blockSize_p1; @@ -605,7 +605,7 @@ _BlockWrite( } } - //3 Phase #3 + /* 3 Phase #3 */ if (remainSize_p2) { offset = (blockCount_p1 * blockSize_p1) + (blockCount_p2 * blockSize_p2); @@ -672,8 +672,8 @@ _WriteFW( IN u32 size ) { - // Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. - // We can remove _ReadChipVersion from ReadpadapterInfo8192C later. + /* Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. */ + /* We can remove _ReadChipVersion from ReadpadapterInfo8192C later. */ int ret = _SUCCESS; u32 pageNums,remainSize ; u32 page, offset; @@ -709,11 +709,11 @@ static void _MCUIO_Reset88E(struct adapter *padapter,u8 bReset) u8 u1bTmp; if(bReset==true){ - // Reset MCU IO Wrapper- sugggest by SD1-Gimmy + /* Reset MCU IO Wrapper- sugggest by SD1-Gimmy */ u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1); rtw_write8(padapter,REG_RSV_CTRL+1, (u1bTmp&(~BIT3))); }else{ - // Enable MCU IO Wrapper + /* Enable MCU IO Wrapper */ u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1); rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp|BIT3); } @@ -738,7 +738,7 @@ static s32 _FWFreeToGo(struct adapter *padapter) u32 value32; u8 value8; - // polling CheckSum report + /* polling CheckSum report */ do { value32 = rtw_read32(padapter, REG_MCUFWDL); if (value32 & FWDL_ChkSum_rpt) break; @@ -758,7 +758,7 @@ static s32 _FWFreeToGo(struct adapter *padapter) _8051Reset88E(padapter); - // polling for FW ready + /* polling for FW ready */ counter = 0; do { value32 = rtw_read32(padapter, REG_MCUFWDL); @@ -779,13 +779,13 @@ static s32 _FWFreeToGo(struct adapter *padapter) #ifdef CONFIG_FILE_FWIMG extern char *rtw_fw_file_path; u8 FwBuffer8188E[FW_8188E_SIZE]; -#endif //CONFIG_FILE_FWIMG +#endif /* CONFIG_FILE_FWIMG */ #ifdef CONFIG_WOWLAN -// -// Description: -// Download 8192C firmware code. -// -// +/* */ +/* Description: */ +/* Download 8192C firmware code. */ +/* */ +/* */ s32 rtl8188e_FirmwareDownload(struct adapter *padapter, BOOLEAN bUsedWoWLANFw) #else s32 rtl8188e_FirmwareDownload(struct adapter *padapter) @@ -825,9 +825,9 @@ s32 rtl8188e_FirmwareDownload(struct adapter *padapter) #ifdef CONFIG_WOWLAN FwImageWoWLAN = (u8*)Rtl8188E_FwWoWImageArray; FwImageWoWLANLen = Rtl8188E_FwWoWImgArrayLength; -#endif //CONFIG_WOWLAN +#endif /* CONFIG_WOWLAN */ -// RT_TRACE(_module_hal_init_c_, _drv_err_, ("rtl8723a_FirmwareDownload: %s\n", pFwImageFileName)); +/* RT_TRACE(_module_hal_init_c_, _drv_err_, ("rtl8723a_FirmwareDownload: %s\n", pFwImageFileName)); */ #ifdef CONFIG_FILE_FWIMG if(rtw_is_file_readable(rtw_fw_file_path) == true) @@ -836,7 +836,7 @@ s32 rtl8188e_FirmwareDownload(struct adapter *padapter) pFirmware->eFWSource = FW_SOURCE_IMG_FILE; } else - #endif //CONFIG_FILE_FWIMG + #endif /* CONFIG_FILE_FWIMG */ { pFirmware->eFWSource = FW_SOURCE_HEADER_FILE; } @@ -848,7 +848,7 @@ s32 rtl8188e_FirmwareDownload(struct adapter *padapter) rtStatus = rtw_retrive_from_file(rtw_fw_file_path, FwBuffer8188E, FW_8188E_SIZE); pFirmware->ulFwLength = rtStatus>=0?rtStatus:0; pFirmware->szFwBuffer = FwBuffer8188E; - #endif //CONFIG_FILE_FWIMG + #endif /* CONFIG_FILE_FWIMG */ break; case FW_SOURCE_HEADER_FILE: if (FwImageLen > FW_8188E_SIZE) { @@ -864,7 +864,7 @@ s32 rtl8188e_FirmwareDownload(struct adapter *padapter) pFirmware->szWoWLANFwBuffer = FwImageWoWLAN; pFirmware->ulWoWLANFwLength = FwImageWoWLANLen; } -#endif //CONFIG_WOWLAN +#endif /* CONFIG_WOWLAN */ break; } #ifdef CONFIG_WOWLAN @@ -879,7 +879,7 @@ s32 rtl8188e_FirmwareDownload(struct adapter *padapter) FirmwareLen = pFirmware->ulFwLength; DBG_871X_LEVEL(_drv_info_, "+%s: !bUsedWoWLANFw, FmrmwareLen:%d+\n", __func__, FirmwareLen); - // To Check Fw header. Added by tynli. 2009.12.04. + /* To Check Fw header. Added by tynli. 2009.12.04. */ pFwHdr = (PRT_8188E_FIRMWARE_HDR)pFirmware->szFwBuffer; } @@ -892,14 +892,14 @@ s32 rtl8188e_FirmwareDownload(struct adapter *padapter) if (IS_FW_HEADER_EXIST(pFwHdr)) { - // Shift 32 bytes for FW header + /* Shift 32 bytes for FW header */ pFirmwareBuf = pFirmwareBuf + 32; FirmwareLen = FirmwareLen - 32; } - // Suggested by Filen. If 8051 is running in RAM code, driver should inform Fw to reset by itself, - // or it will cause download Fw fail. 2010.02.01. by tynli. - if (rtw_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) //8051 RAM code + /* Suggested by Filen. If 8051 is running in RAM code, driver should inform Fw to reset by itself, */ + /* or it will cause download Fw fail. 2010.02.01. by tynli. */ + if (rtw_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) /* 8051 RAM code */ { rtw_write8(padapter, REG_MCUFWDL, 0x00); _8051Reset88E(padapter); @@ -908,7 +908,7 @@ s32 rtl8188e_FirmwareDownload(struct adapter *padapter) _FWDownloadEnable(padapter, true); fwdl_start_time = rtw_get_current_time(); while(1) { - //reset the FWDL chksum + /* reset the FWDL chksum */ rtw_write8(padapter, REG_MCUFWDL, rtw_read8(padapter, REG_MCUFWDL)|FWDL_ChkSum_rpt); rtStatus = _WriteFW(padapter, pFirmwareBuf, FirmwareLen); @@ -942,7 +942,7 @@ Exit: if (pFirmware) rtw_mfree((u8*)pFirmware, sizeof(RT_FIRMWARE_8188E)); - //RT_TRACE(COMP_INIT, DBG_LOUD, (" <=== FirmwareDownload91C()\n")); + /* RT_TRACE(COMP_INIT, DBG_LOUD, (" <=== FirmwareDownload91C()\n")); */ #ifdef CONFIG_WOWLAN if (adapter_to_pwrctl(padapter)->wowlan_mode) rtl8188e_InitializeFirmwareVars(padapter); @@ -961,22 +961,22 @@ void rtl8188e_InitializeFirmwareVars(struct adapter *padapter) PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - // Init Fw LPS related. + /* Init Fw LPS related. */ pwrpriv->bFwCurrentInPSMode = false; - // Init H2C counter. by tynli. 2009.12.09. + /* Init H2C counter. by tynli. 2009.12.09. */ pHalData->LastHMEBoxNum = 0; } -//=========================================== +/* */ -// -// Description: Prepare some information to Fw for WoWLAN. -// (1) Download wowlan Fw. -// (2) Download RSVD page packets. -// (3) Enable AP offload if needed. -// -// 2011.04.12 by tynli. -// +/* */ +/* Description: Prepare some information to Fw for WoWLAN. */ +/* (1) Download wowlan Fw. */ +/* (2) Download RSVD page packets. */ +/* (3) Enable AP offload if needed. */ +/* */ +/* 2011.04.12 by tynli. */ +/* */ void SetFwRelatedForWoWLAN8188ES( IN struct adapter * padapter, @@ -986,9 +986,9 @@ SetFwRelatedForWoWLAN8188ES( int status=_FAIL; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); u8 bRecover = false; - // - // 1. Before WoWLAN we need to re-download WoWLAN Fw. - // + /* */ + /* 1. Before WoWLAN we need to re-download WoWLAN Fw. */ + /* */ status = rtl8188e_FirmwareDownload(padapter, bHostIsGoingtoSleep); if(status != _SUCCESS) { DBG_871X("ConfigFwRelatedForWoWLAN8188ES(): Re-Download Firmware failed!!\n"); @@ -996,9 +996,9 @@ SetFwRelatedForWoWLAN8188ES( } else { DBG_871X("ConfigFwRelatedForWoWLAN8188ES(): Re-Download Firmware Success !!\n"); } - // - // 2. Re-Init the variables about Fw related setting. - // + /* */ + /* 2. Re-Init the variables about Fw related setting. */ + /* */ rtl8188e_InitializeFirmwareVars(padapter); } #else @@ -1006,16 +1006,16 @@ void rtl8188e_InitializeFirmwareVars(struct adapter *padapter) { PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - // Init Fw LPS related. + /* Init Fw LPS related. */ adapter_to_pwrctl(padapter)->bFwCurrentInPSMode = false; - // Init H2C counter. by tynli. 2009.12.09. + /* Init H2C counter. by tynli. 2009.12.09. */ pHalData->LastHMEBoxNum = 0; -// pHalData->H2CQueueHead = 0; -// pHalData->H2CQueueTail = 0; -// pHalData->H2CStopInsertQueue = FALSE; +/* pHalData->H2CQueueHead = 0; */ +/* pHalData->H2CQueueTail = 0; */ +/* pHalData->H2CStopInsertQueue = FALSE; */ } -#endif //CONFIG_WOWLAN +#endif /* CONFIG_WOWLAN */ static void rtl8188e_free_hal_data(struct adapter *padapter) { @@ -1030,9 +1030,9 @@ static void rtl8188e_free_hal_data(struct adapter *padapter) ; } -//=========================================================== -// Efuse related code -//=========================================================== +/* */ +/* Efuse related code */ +/* */ enum{ VOLTAGE_V25 = 0x03, LDOE25_SHIFT = 28 , @@ -1073,20 +1073,20 @@ hal_EfusePowerSwitch_RTL8188E( { rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); - // 1.2V Power: From VDDON with Power Cut(0x0000h[15]), defualt valid + /* 1.2V Power: From VDDON with Power Cut(0x0000h[15]), defualt valid */ tmpV16 = rtw_read16(pAdapter,REG_SYS_ISO_CTRL); if( ! (tmpV16 & PWC_EV12V ) ){ tmpV16 |= PWC_EV12V ; rtw_write16(pAdapter,REG_SYS_ISO_CTRL,tmpV16); } - // Reset: 0x0000h[28], default valid + /* Reset: 0x0000h[28], default valid */ tmpV16 = rtw_read16(pAdapter,REG_SYS_FUNC_EN); if( !(tmpV16 & FEN_ELDR) ){ tmpV16 |= FEN_ELDR ; rtw_write16(pAdapter,REG_SYS_FUNC_EN,tmpV16); } - // Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid + /* Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid */ tmpV16 = rtw_read16(pAdapter,REG_SYS_CLKR); if( (!(tmpV16 & LOADER_CLK_EN) ) ||(!(tmpV16 & ANA8M) ) ){ tmpV16 |= (LOADER_CLK_EN |ANA8M ) ; @@ -1095,7 +1095,7 @@ hal_EfusePowerSwitch_RTL8188E( if(bWrite == true) { - // Enable LDO 2.5V before read/write action + /* Enable LDO 2.5V before read/write action */ tempval = rtw_read8(pAdapter, EFUSE_TEST+3); tempval &= 0x0F; tempval |= (VOLTAGE_V25 << 4); @@ -1107,7 +1107,7 @@ hal_EfusePowerSwitch_RTL8188E( rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF); if(bWrite == true){ - // Disable LDO 2.5V after read/write action + /* Disable LDO 2.5V after read/write action */ tempval = rtw_read8(pAdapter, EFUSE_TEST+3); rtw_write8(pAdapter, EFUSE_TEST+3, (tempval & 0x7F)); } @@ -1127,8 +1127,8 @@ rtl8188e_EfusePowerSwitch( static bool efuse_read_phymap( struct adapter *Adapter, - u8 *pbuf, //buffer to store efuse physical map - u16 *size //the max byte to read. will update to byte read + u8 *pbuf, /* buffer to store efuse physical map */ + u16 *size /* the max byte to read. will update to byte read */ ) { u8 *pos = pbuf; @@ -1136,15 +1136,15 @@ static bool efuse_read_phymap( u16 addr = 0; bool reach_end = false; - // - // Refresh efuse init map as all 0xFF. - // + /* */ + /* Refresh efuse init map as all 0xFF. */ + /* */ memset(pbuf, 0xFF, limit); - // - // Read physical efuse content. - // + /* */ + /* Read physical efuse content. */ + /* */ while(addr < limit) { ReadEFuseByte(Adapter, addr, pos, false); @@ -1175,23 +1175,23 @@ Hal_EfuseReadEFuse88E( IN BOOLEAN bPseudoTest ) { - //u8 efuseTbl[EFUSE_MAP_LEN_88E]; + /* u8 efuseTbl[EFUSE_MAP_LEN_88E]; */ u8 *efuseTbl = NULL; u8 rtemp8[1]; u16 eFuse_Addr = 0; u8 offset, wren; u16 i, j; - //u16 eFuseWord[EFUSE_MAX_SECTION_88E][EFUSE_MAX_WORD_UNIT]; + /* u16 eFuseWord[EFUSE_MAX_SECTION_88E][EFUSE_MAX_WORD_UNIT]; */ u16 **eFuseWord = NULL; u16 efuse_utilized = 0; u8 efuse_usage = 0; u8 u1temp = 0; - // - // Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. - // + /* */ + /* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */ + /* */ if((_offset + _size_byte)>EFUSE_MAP_LEN_88E) - {// total E-Fuse table is 512bytes + {/* total E-Fuse table is 512bytes */ DBG_8192C("Hal_EfuseReadEFuse88E(): Invalid offset(%#x) with read bytes(%#x)!!\n",_offset, _size_byte); goto exit; } @@ -1210,20 +1210,20 @@ Hal_EfuseReadEFuse88E( goto exit; } - // 0. Refresh efuse init map as all oxFF. + /* 0. Refresh efuse init map as all oxFF. */ for (i = 0; i < EFUSE_MAX_SECTION_88E; i++) for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) eFuseWord[i][j] = 0xFFFF; - // - // 1. Read the first byte to check if efuse is empty!!! - // - // + /* */ + /* 1. Read the first byte to check if efuse is empty!!! */ + /* */ + /* */ ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest); if(*rtemp8 != 0xFF) { efuse_utilized++; - //DBG_8192C("efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8); + /* DBG_8192C("efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8); */ eFuse_Addr++; } else @@ -1233,24 +1233,24 @@ Hal_EfuseReadEFuse88E( } - // - // 2. Read real efuse content. Filter PG header and every section data. - // + /* */ + /* 2. Read real efuse content. Filter PG header and every section data. */ + /* */ while((*rtemp8 != 0xFF) && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) { - //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("efuse_Addr-%d efuse_data=%x\n", eFuse_Addr-1, *rtemp8)); + /* RTPRINT(FEEPROM, EFUSE_READ_ALL, ("efuse_Addr-%d efuse_data=%x\n", eFuse_Addr-1, *rtemp8)); */ - // Check PG header for section num. - if((*rtemp8 & 0x1F ) == 0x0F) //extended header + /* Check PG header for section num. */ + if((*rtemp8 & 0x1F ) == 0x0F) /* extended header */ { u1temp =( (*rtemp8 & 0xE0) >> 5); - //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header u1temp=%x *rtemp&0xE0 0x%x\n", u1temp, *rtemp8 & 0xE0)); + /* RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header u1temp=%x *rtemp&0xE0 0x%x\n", u1temp, *rtemp8 & 0xE0)); */ - //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header u1temp=%x \n", u1temp)); + /* RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header u1temp=%x \n", u1temp)); */ ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest); - //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8)); + /* RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8)); */ if((*rtemp8 & 0x0F) == 0x0F) { @@ -1278,18 +1278,18 @@ Hal_EfuseReadEFuse88E( if(offset < EFUSE_MAX_SECTION_88E) { - // Get word enable value from PG header - //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Offset-%d Worden=%x\n", offset, wren)); + /* Get word enable value from PG header */ + /* RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Offset-%d Worden=%x\n", offset, wren)); */ for(i=0; i= EFUSE_REAL_CONTENT_LEN_88E) break; - //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d", eFuse_Addr)); + /* RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d", eFuse_Addr)); */ ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest); eFuse_Addr++; - //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Data=0x%x\n", *rtemp8)); + /* RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Data=0x%x\n", *rtemp8)); */ efuse_utilized++; eFuseWord[offset][i] |= (((u16)*rtemp8 << 8) & 0xff00); @@ -1314,9 +1314,9 @@ Hal_EfuseReadEFuse88E( } } - // Read next PG header + /* Read next PG header */ ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest); - //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d rtemp 0x%x\n", eFuse_Addr, *rtemp8)); + /* RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d rtemp 0x%x\n", eFuse_Addr, *rtemp8)); */ if(*rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) { @@ -1325,9 +1325,9 @@ Hal_EfuseReadEFuse88E( } } - // - // 3. Collect 16 sections and 4 word unit into Efuse map. - // + /* */ + /* 3. Collect 16 sections and 4 word unit into Efuse map. */ + /* */ for(i=0; i Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP. - // Skip dummy parts to prevent unexpected data read from Efuse. - // By pass right now. 2009.02.19. - // + /* */ + /* Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP. */ + /* Skip dummy parts to prevent unexpected data read from Efuse. */ + /* By pass right now. 2009.02.19. */ + /* */ while(bContinual && AVAILABLE_EFUSE_ADDR(efuse_addr) ) { - //------- Header Read ------------- + /* Header Read ------------- */ if(ReadState & PG_STATE_HEADER) { if(efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest)&&(efuse_data!=0xFF)) @@ -1951,12 +1951,12 @@ hal_EfusePgPacketRead_8188e( } if(bDataEmpty==false){ ReadState = PG_STATE_DATA; - }else{//read next header + }else{/* read next header */ efuse_addr = efuse_addr + (word_cnts*2)+1; ReadState = PG_STATE_HEADER; } } - else{//read next header + else{/* read next header */ efuse_addr = efuse_addr + (word_cnts*2)+1; ReadState = PG_STATE_HEADER; } @@ -1966,7 +1966,7 @@ hal_EfusePgPacketRead_8188e( bContinual = false ; } } - //------- Data section Read ------------- + /* Data section Read ------------- */ else if(ReadState & PG_STATE_DATA) { efuse_WordEnableDataRead(hworden,tmpdata,data); @@ -2047,10 +2047,10 @@ hal_EfuseFixHeaderProcess( memset((void *)originaldata, 0xff, 8); if(Efuse_PgPacketRead(pAdapter, pFixPkt->offset, originaldata, bPseudoTest)) - { //check if data exist + { /* check if data exist */ badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr+1, pFixPkt->word_en, originaldata, bPseudoTest); - if(badworden != 0xf) // write fail + if(badworden != 0xf) /* write fail */ { PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pFixPkt->offset, badworden, originaldata, bPseudoTest); @@ -2085,13 +2085,13 @@ hal_EfusePgPacketWrite2ByteHeader( u8 pg_header=0, tmp_header=0, pg_header_temp=0; u8 repeatcnt=0; - //RTPRINT(FEEPROM, EFUSE_PG, ("Wirte 2byte header\n")); + /* RTPRINT(FEEPROM, EFUSE_PG, ("Wirte 2byte header\n")); */ EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, (void *)&efuse_max_available_len, bPseudoTest); while(efuse_addr < efuse_max_available_len) { pg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F; - //RTPRINT(FEEPROM, EFUSE_PG, ("pg_header = 0x%x\n", pg_header)); + /* RTPRINT(FEEPROM, EFUSE_PG, ("pg_header = 0x%x\n", pg_header)); */ efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest); efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest); @@ -2099,7 +2099,7 @@ hal_EfusePgPacketWrite2ByteHeader( { if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) { - //RTPRINT(FEEPROM, EFUSE_PG, ("Repeat over limit for pg_header!!\n")); + /* RTPRINT(FEEPROM, EFUSE_PG, ("Repeat over limit for pg_header!!\n")); */ return false; } @@ -2107,7 +2107,7 @@ hal_EfusePgPacketWrite2ByteHeader( efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest); } - //to write ext_header + /* to write ext_header */ if(tmp_header == pg_header) { efuse_addr++; @@ -2121,7 +2121,7 @@ hal_EfusePgPacketWrite2ByteHeader( { if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) { - //RTPRINT(FEEPROM, EFUSE_PG, ("Repeat over limit for ext_header!!\n")); + /* RTPRINT(FEEPROM, EFUSE_PG, ("Repeat over limit for ext_header!!\n")); */ return false; } @@ -2129,11 +2129,11 @@ hal_EfusePgPacketWrite2ByteHeader( efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest); } - if((tmp_header & 0x0F) == 0x0F) //word_en PG fail + if((tmp_header & 0x0F) == 0x0F) /* word_en PG fail */ { if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) { - //RTPRINT(FEEPROM, EFUSE_PG, ("Repeat over limit for word_en!!\n")); + /* RTPRINT(FEEPROM, EFUSE_PG, ("Repeat over limit for word_en!!\n")); */ return false; } else @@ -2142,10 +2142,10 @@ hal_EfusePgPacketWrite2ByteHeader( continue; } } - else if(pg_header != tmp_header) //offset PG fail + else if(pg_header != tmp_header) /* offset PG fail */ { PGPKT_STRUCT fixPkt; - //RTPRINT(FEEPROM, EFUSE_PG, ("Error condition for offset PG fail, need to cover the existed data\n")); + /* RTPRINT(FEEPROM, EFUSE_PG, ("Error condition for offset PG fail, need to cover the existed data\n")); */ fixPkt.offset = ((pg_header_temp & 0xE0) >> 5) | ((tmp_header & 0xF0) >> 1); fixPkt.word_en = tmp_header & 0x0F; fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en); @@ -2158,7 +2158,7 @@ hal_EfusePgPacketWrite2ByteHeader( break; } } - else if ((tmp_header & 0x1F) == 0x0F) //wrong extended header + else if ((tmp_header & 0x1F) == 0x0F) /* wrong extended header */ { efuse_addr+=2; continue; @@ -2182,7 +2182,7 @@ hal_EfusePgPacketWrite1ByteHeader( u16 efuse_addr=*pAddr; u8 repeatcnt=0; - //RTPRINT(FEEPROM, EFUSE_PG, ("Wirte 1byte header\n")); + /* RTPRINT(FEEPROM, EFUSE_PG, ("Wirte 1byte header\n")); */ pg_header = ((pTargetPkt->offset << 4) & 0xf0) |pTargetPkt->word_en; efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest); @@ -2205,7 +2205,7 @@ hal_EfusePgPacketWrite1ByteHeader( else { PGPKT_STRUCT fixPkt; - //RTPRINT(FEEPROM, EFUSE_PG, ("Error condition for fixed PG packet, need to cover the existed data\n")); + /* RTPRINT(FEEPROM, EFUSE_PG, ("Error condition for fixed PG packet, need to cover the existed data\n")); */ fixPkt.offset = (tmp_header>>4) & 0x0F; fixPkt.word_en = tmp_header & 0x0F; fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en); @@ -2234,14 +2234,14 @@ hal_EfusePgPacketWriteData( badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr+1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest); if(badworden == 0x0F) { - // write ok - //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgPacketWriteData ok!!\n")); + /* write ok */ + /* RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgPacketWriteData ok!!\n")); */ return true; } else { - //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgPacketWriteData Fail!!\n")); - //reorganize other pg packet + /* RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgPacketWriteData Fail!!\n")); */ + /* reorganize other pg packet */ PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest); @@ -2283,29 +2283,29 @@ wordEnMatched( IN u8 *pWden ) { - u8 match_word_en = 0x0F; // default all words are disabled + u8 match_word_en = 0x0F; /* default all words are disabled */ u8 i; - // check if the same words are enabled both target and current PG packet + /* check if the same words are enabled both target and current PG packet */ if( ((pTargetPkt->word_en & BIT0) == 0) && ((pCurPkt->word_en & BIT0) == 0) ) { - match_word_en &= ~BIT0; // enable word 0 + match_word_en &= ~BIT0; /* enable word 0 */ } if( ((pTargetPkt->word_en & BIT1) == 0) && ((pCurPkt->word_en & BIT1) == 0) ) { - match_word_en &= ~BIT1; // enable word 1 + match_word_en &= ~BIT1; /* enable word 1 */ } if( ((pTargetPkt->word_en & BIT2) == 0) && ((pCurPkt->word_en & BIT2) == 0) ) { - match_word_en &= ~BIT2; // enable word 2 + match_word_en &= ~BIT2; /* enable word 2 */ } if( ((pTargetPkt->word_en & BIT3) == 0) && ((pCurPkt->word_en & BIT3) == 0) ) { - match_word_en &= ~BIT3; // enable word 3 + match_word_en &= ~BIT3; /* enable word 3 */ } *pWden = match_word_en; @@ -2377,7 +2377,7 @@ hal_EfusePartialWriteCheck( startAddr = (u16)(BTEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN); } } - //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePartialWriteCheck(), startAddr=%d\n", startAddr)); + /* RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePartialWriteCheck(), startAddr=%d\n", startAddr)); */ while(1) { @@ -2396,7 +2396,7 @@ hal_EfusePartialWriteCheck( efuse_OneByteRead(pAdapter, startAddr, &efuse_data, bPseudoTest); if(ALL_WORDS_DISABLED(efuse_data)) { - //RTPRINT(FEEPROM, EFUSE_PG, ("Error condition, all words disabled")); + /* RTPRINT(FEEPROM, EFUSE_PG, ("Error condition, all words disabled")); */ bRet = false; break; } @@ -2414,46 +2414,46 @@ hal_EfusePartialWriteCheck( } curPkt.word_cnts = Efuse_CalculateWordCnts(curPkt.word_en); - // if same header is found but no data followed - // write some part of data followed by the header. + /* if same header is found but no data followed */ + /* write some part of data followed by the header. */ if( (curPkt.offset == pTargetPkt->offset) && (!hal_EfuseCheckIfDatafollowed(pAdapter, curPkt.word_cnts, startAddr+1, bPseudoTest)) && wordEnMatched(pTargetPkt, &curPkt, &matched_wden) ) { - //RTPRINT(FEEPROM, EFUSE_PG, ("Need to partial write data by the previous wrote header\n")); - // Here to write partial data + /* RTPRINT(FEEPROM, EFUSE_PG, ("Need to partial write data by the previous wrote header\n")); */ + /* Here to write partial data */ badworden = Efuse_WordEnableDataWrite(pAdapter, startAddr+1, matched_wden, pTargetPkt->data, bPseudoTest); if(badworden != 0x0F) { u32 PgWriteSuccess=0; - // if write fail on some words, write these bad words again + /* if write fail on some words, write these bad words again */ PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest); if(!PgWriteSuccess) { - bRet = false; // write fail, return + bRet = false; /* write fail, return */ break; } } - // partial write ok, update the target packet for later use + /* partial write ok, update the target packet for later use */ for(i=0; i<4; i++) { - if((matched_wden & (0x1<word_en |= (0x1<word_en |= (0x1<word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en); } - // read from next header + /* read from next header */ startAddr = startAddr + (curPkt.word_cnts*2) +1; } else { - // not used header, 0xff + /* not used header, 0xff */ *pAddr = startAddr; - //RTPRINT(FEEPROM, EFUSE_PG, ("Started from unused header offset=%d\n", startAddr)); + /* RTPRINT(FEEPROM, EFUSE_PG, ("Started from unused header offset=%d\n", startAddr)); */ bRet = true; break; } @@ -2470,15 +2470,15 @@ hal_EfusePgCheckAvailableAddr( { u16 efuse_max_available_len=0; - //Change to check TYPE_EFUSE_MAP_LEN ,beacuse 8188E raw 256,logic map over 256. + /* Change to check TYPE_EFUSE_MAP_LEN ,beacuse 8188E raw 256,logic map over 256. */ EFUSE_GetEfuseDefinition(pAdapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&efuse_max_available_len, false); - //EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (void *)&efuse_max_available_len, bPseudoTest); - //RTPRINT(FEEPROM, EFUSE_PG, ("efuse_max_available_len = %d\n", efuse_max_available_len)); + /* EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (void *)&efuse_max_available_len, bPseudoTest); */ + /* RTPRINT(FEEPROM, EFUSE_PG, ("efuse_max_available_len = %d\n", efuse_max_available_len)); */ if(Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest) >= efuse_max_available_len) { - //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgCheckAvailableAddr error!!\n")); + /* RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgCheckAvailableAddr error!!\n")); */ return false; } return true; @@ -2499,7 +2499,7 @@ hal_EfuseConstructPGPkt( efuse_WordEnableDataRead(word_en, pData, pTargetPkt->data); pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en); - //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseConstructPGPkt(), targetPkt, offset=%d, word_en=0x%x, word_cnts=%d\n", pTargetPkt->offset, pTargetPkt->word_en, pTargetPkt->word_cnts)); + /* RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseConstructPGPkt(), targetPkt, offset=%d, word_en=0x%x, word_cnts=%d\n", pTargetPkt->offset, pTargetPkt->word_en, pTargetPkt->word_cnts)); */ } static BOOLEAN @@ -2629,16 +2629,16 @@ ReadChipVersion8188E( ChipVersion.RFType = RF_TYPE_1T1R; ChipVersion.VendorType = ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC); - ChipVersion.CUTVersion = (value32 & CHIP_VER_RTL_MASK)>>CHIP_VER_RTL_SHIFT; // IC version (CUT) + ChipVersion.CUTVersion = (value32 & CHIP_VER_RTL_MASK)>>CHIP_VER_RTL_SHIFT; /* IC version (CUT) */ - // For regulator mode. by tynli. 2011.01.14 + /* For regulator mode. by tynli. 2011.01.14 */ pHalData->RegulatorMode = ((value32 & TRP_BT_EN) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR); - ChipVersion.ROMVer = 0; // ROM code version. + ChipVersion.ROMVer = 0; /* ROM code version. */ pHalData->MultiFunc = RT_MULTI_FUNC_NONE; -//#if DBG +/* if DBG */ #if 1 dump_chip_info(ChipVersion); #endif @@ -2692,7 +2692,7 @@ static void rtl8188e_SetHalODMVar( { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); PDM_ODM_T podmpriv = &pHalData->odmpriv; - //_irqL irqL; + /* _irqL irqL; */ switch(eVariable){ case HAL_ODM_STA_INFO: { @@ -2706,10 +2706,10 @@ static void rtl8188e_SetHalODMVar( } else{ DBG_8192C("### Clean STA_(%d) info\n",psta->mac_id); - //_enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); + /* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */ ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS,psta->mac_id,NULL); - //_exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); + /* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */ } } break; @@ -2773,7 +2773,7 @@ void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc) pHalFunc->write_rfreg = &rtl8188e_PHY_SetRFReg; - // Efuse related function + /* Efuse related function */ pHalFunc->EfusePowerSwitch = &rtl8188e_EfusePowerSwitch; pHalFunc->ReadEFuse = &rtl8188e_ReadEFuse; pHalFunc->EFUSEGetEfuseDefinition = &rtl8188e_EFUSE_GetEfuseDefinition; @@ -2790,7 +2790,7 @@ void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc) pHalFunc->sreset_linked_status_check = &rtl8188e_sreset_linked_status_check; pHalFunc->sreset_get_wifi_status = &sreset_get_wifi_status; pHalFunc->sreset_inprogress= &sreset_inprogress; -#endif //DBG_CONFIG_ERROR_DETECT +#endif /* DBG_CONFIG_ERROR_DETECT */ pHalFunc->GetHalODMVarHandler = &rtl8188e_GetHalODMVar; pHalFunc->SetHalODMVarHandler = &rtl8188e_SetHalODMVar; @@ -2813,7 +2813,7 @@ u8 GetEEPROMSize8188E(struct adapter *padapter) u32 cr; cr = rtw_read16(padapter, REG_9346CR); - // 6: EEPROM used is 93C46, 4: boot from E-Fuse. + /* 6: EEPROM used is 93C46, 4: boot from E-Fuse. */ size = (cr & BOOT_FROM_EEPROM) ? 6 : 4; MSG_8192C("EEPROM type is %s\n", size==4 ? "E-FUSE" : "93C46"); @@ -2821,11 +2821,11 @@ u8 GetEEPROMSize8188E(struct adapter *padapter) return size; } -//------------------------------------------------------------------------- -// -// LLT R/W/Init function -// -//------------------------------------------------------------------------- +/* */ +/* */ +/* LLT R/W/Init function */ +/* */ +/* */ static s32 _LLTWrite(struct adapter *padapter, u32 address, u32 data) { s32 status = _SUCCESS; @@ -2836,7 +2836,7 @@ static s32 _LLTWrite(struct adapter *padapter, u32 address, u32 data) rtw_write32(padapter, LLTReg, value); - //polling + /* polling */ do { value = rtw_read32(padapter, LLTReg); if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) { @@ -2862,7 +2862,7 @@ static u8 _LLTRead(struct adapter *padapter, u32 address) rtw_write32(padapter, LLTReg, value); - //polling and get value + /* polling and get value */ do { value = rtw_read32(padapter, LLTReg); if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) { @@ -2896,7 +2896,7 @@ s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy) { s32 status = _FAIL; u32 i; - u32 Last_Entry_Of_TxPktBuf = LAST_ENTRY_OF_TX_PKT_BUFFER;// 176, 22k + u32 Last_Entry_Of_TxPktBuf = LAST_ENTRY_OF_TX_PKT_BUFFER;/* 176, 22k */ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); #if defined(CONFIG_IOL_LLT) @@ -2914,15 +2914,15 @@ s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy) } } - // end of list + /* end of list */ status = _LLTWrite(padapter, (txpktbuf_bndy - 1), 0xFF); if (_SUCCESS != status) { return status; } - // Make the other pages as ring buffer - // This ring buffer is used as beacon buffer if we config this MAC as two MAC transfer. - // Otherwise used as local loopback buffer. + /* Make the other pages as ring buffer */ + /* This ring buffer is used as beacon buffer if we config this MAC as two MAC transfer. */ + /* Otherwise used as local loopback buffer. */ for (i = txpktbuf_bndy; i < Last_Entry_Of_TxPktBuf; i++) { status = _LLTWrite(padapter, i, (i + 1)); if (_SUCCESS != status) { @@ -2930,7 +2930,7 @@ s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy) } } - // Let last entry point to the start entry of ring buffer + /* Let last entry point to the start entry of ring buffer */ status = _LLTWrite(padapter, Last_Entry_Of_TxPktBuf, txpktbuf_bndy); if (_SUCCESS != status) { return status; @@ -2944,32 +2944,32 @@ void Hal_InitPGData88E(struct adapter *padapter) { EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); -// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); +/* HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); */ u32 i; u16 value16; if(false == pEEPROM->bautoload_fail_flag) - { // autoload OK. + { /* autoload OK. */ if (is_boot_from_eeprom(padapter)) { - // Read all Content from EEPROM or EFUSE. + /* Read all Content from EEPROM or EFUSE. */ for(i = 0; i < HWSET_MAX_SIZE_88E; i += 2) { -// value16 = EF2Byte(ReadEEprom(pAdapter, (u16) (i>>1))); -// *((u16*)(&PROMContent[i])) = value16; +/* value16 = EF2Byte(ReadEEprom(pAdapter, (u16) (i>>1))); */ +/* *((u16*)(&PROMContent[i])) = value16; */ } } else { - // Read EFUSE real map to shadow. + /* Read EFUSE real map to shadow. */ EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, false); } } else - {//autoload fail + {/* autoload fail */ RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("AutoLoad Fail reported from CR9346!!\n")); -// pHalData->AutoloadFailFlag = true; - //update to default value 0xFF +/* pHalData->AutoloadFailFlag = true; */ + /* update to default value 0xFF */ if (!is_boot_from_eeprom(padapter)) EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, false); } @@ -2982,11 +2982,11 @@ Hal_EfuseParseIDCode88E( ) { EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); -// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); +/* HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); */ u16 EEPROMId; - // Checl 0x8129 again for making sure autoload status!! + /* Checl 0x8129 again for making sure autoload status!! */ EEPROMId = le16_to_cpu(*((__le16*)hwinfo)); if (EEPROMId != RTL_EEPROM_ID) { DBG_8192C("EEPROM ID(%#x) is invalid!!\n", EEPROMId); @@ -3046,7 +3046,7 @@ Hal_ReadPowerValueFromPROM_8188E( { for(rfPath = 0 ; rfPath < pHalData->NumTotalRFPath ; rfPath++) { - //2.4G default value + /* 2.4G default value */ for(group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; @@ -3071,29 +3071,29 @@ Hal_ReadPowerValueFromPROM_8188E( } - //pHalData->bNOPG = TRUE; + /* pHalData->bNOPG = TRUE; */ return; } for(rfPath = 0 ; rfPath < pHalData->NumTotalRFPath ; rfPath++) { - //2.4G default value + /* 2.4G default value */ for(group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { - //printk(" IndexCCK_Base rfPath:%d group:%d,eeAddr:0x%02x ",rfPath,group,eeAddr); + /* printk(" IndexCCK_Base rfPath:%d group:%d,eeAddr:0x%02x ",rfPath,group,eeAddr); */ pwrInfo24G->IndexCCK_Base[rfPath][group] = PROMContent[eeAddr++]; - //printk(" IndexCCK_Base:%02x \n",pwrInfo24G->IndexCCK_Base[rfPath][group] ); + /* printk(" IndexCCK_Base:%02x \n",pwrInfo24G->IndexCCK_Base[rfPath][group] ); */ if(pwrInfo24G->IndexCCK_Base[rfPath][group] == 0xFF) { pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; -// pHalData->bNOPG = TRUE; +/* pHalData->bNOPG = TRUE; */ } } for(group = 0 ; group < MAX_CHNL_GROUP_24G-1; group++) { - //printk(" IndexBW40_Base rfPath:%d group:%d,eeAddr:0x%02x ",rfPath,group,eeAddr); + /* printk(" IndexBW40_Base rfPath:%d group:%d,eeAddr:0x%02x ",rfPath,group,eeAddr); */ pwrInfo24G->IndexBW40_Base[rfPath][group] = PROMContent[eeAddr++]; - //printk(" IndexBW40_Base: %02x \n",pwrInfo24G->IndexBW40_Base[rfPath][group] ); + /* printk(" IndexBW40_Base: %02x \n",pwrInfo24G->IndexBW40_Base[rfPath][group] ); */ if(pwrInfo24G->IndexBW40_Base[rfPath][group] == 0xFF) pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; } @@ -3107,7 +3107,7 @@ Hal_ReadPowerValueFromPROM_8188E( else { pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4; - if(pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) //4bit sign number to 8 bit sign number + if(pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0; } @@ -3116,7 +3116,7 @@ Hal_ReadPowerValueFromPROM_8188E( else { pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f); - if(pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) //4bit sign number to 8 bit sign number + if(pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0; } pwrInfo24G->CCK_Diff[rfPath][TxCount] = 0; @@ -3129,7 +3129,7 @@ Hal_ReadPowerValueFromPROM_8188E( else { pwrInfo24G->BW40_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4; - if(pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT3) //4bit sign number to 8 bit sign number + if(pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ pwrInfo24G->BW40_Diff[rfPath][TxCount] |= 0xF0; } @@ -3138,7 +3138,7 @@ Hal_ReadPowerValueFromPROM_8188E( else { pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f); - if(pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) //4bit sign number to 8 bit sign number + if(pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0; } eeAddr++; @@ -3148,7 +3148,7 @@ Hal_ReadPowerValueFromPROM_8188E( else { pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4; - if(pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) //4bit sign number to 8 bit sign number + if(pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0; } @@ -3157,7 +3157,7 @@ Hal_ReadPowerValueFromPROM_8188E( else { pwrInfo24G->CCK_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f); - if(pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT3) //4bit sign number to 8 bit sign number + if(pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ pwrInfo24G->CCK_Diff[rfPath][TxCount] |= 0xF0; } eeAddr++; @@ -3176,11 +3176,11 @@ Hal_GetChnlGroup( { u8 group=0; - if (chnl < 3) // Cjanel 1-3 + if (chnl < 3) /* Cjanel 1-3 */ group = 0; - else if (chnl < 9) // Channel 4-9 + else if (chnl < 9) /* Channel 4-9 */ group = 1; - else // Channel 10-14 + else /* Channel 10-14 */ group = 2; return group; @@ -3197,21 +3197,21 @@ Hal_GetChnlGroup88E( { bIn24G=true; - if (chnl < 3) // Chanel 1-2 + if (chnl < 3) /* Chanel 1-2 */ *pGroup = 0; - else if (chnl < 6) // Channel 3-5 + else if (chnl < 6) /* Channel 3-5 */ *pGroup = 1; - else if(chnl <9) // Channel 6-8 + else if(chnl <9) /* Channel 6-8 */ *pGroup = 2; - else if(chnl <12) // Channel 9-11 + else if(chnl <12) /* Channel 9-11 */ *pGroup = 3; - else if(chnl <14) // Channel 12-13 + else if(chnl <14) /* Channel 12-13 */ *pGroup = 4; - else if(chnl ==14) // Channel 14 + else if(chnl ==14) /* Channel 14 */ *pGroup = 5; else { - //RT_TRACE(COMP_EFUSE,DBG_LOUD,("==>Hal_GetChnlGroup88E in 2.4 G, but Channel %d in Group not found \n",chnl)); + /* RT_TRACE(COMP_EFUSE,DBG_LOUD,("==>Hal_GetChnlGroup88E in 2.4 G, but Channel %d in Group not found \n",chnl)); */ } } else @@ -3246,11 +3246,11 @@ Hal_GetChnlGroup88E( *pGroup = 11; else { - //RT_TRACE(COMP_EFUSE,DBG_LOUD,("==>Hal_GetChnlGroup88E in 5G, but Channel %d in Group not found \n",chnl)); + /* RT_TRACE(COMP_EFUSE,DBG_LOUD,("==>Hal_GetChnlGroup88E in 5G, but Channel %d in Group not found \n",chnl)); */ } } - //RT_TRACE(COMP_EFUSE,DBG_LOUD,("<==Hal_GetChnlGroup88E, Channel = %d, bIn24G =%d,\n",chnl,bIn24G)); + /* RT_TRACE(COMP_EFUSE,DBG_LOUD,("<==Hal_GetChnlGroup88E, Channel = %d, bIn24G =%d,\n",chnl,bIn24G)); */ return bIn24G; } @@ -3270,7 +3270,7 @@ void Hal_ReadPowerSavingMode88E( } else { - //hw power down mode selection , 0:rf-off / 1:power down + /* hw power down mode selection , 0:rf-off / 1:power down */ if(padapter->registrypriv.hwpdn_mode==2) pwrctl->bHWPowerdown = (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & BIT4)?true:false; @@ -3279,8 +3279,8 @@ void Hal_ReadPowerSavingMode88E( pwrctl->bHWPwrPindetect = padapter->registrypriv.hwpwrp_detect; - // decide hw if support remote wakeup function - // if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume + /* decide hw if support remote wakeup function */ + /* if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume */ pwrctl->bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0] & BIT1)?true :false; DBG_8192C("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) ,bSupportRemoteWakeup(%x)\n",__FUNCTION__, @@ -3309,7 +3309,7 @@ Hal_ReadTxPowerInfo88E( if(!AutoLoadFail) pHalData->bTXPowerDataReadFromEEPORM = TRUE; - //for(rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) + /* for(rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) */ for(rfPath = 0 ; rfPath < pHalData->NumTotalRFPath ; rfPath++) { for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++) @@ -3351,15 +3351,15 @@ Hal_ReadTxPowerInfo88E( } - // 2010/10/19 MH Add Regulator recognize for EU. + /* 2010/10/19 MH Add Regulator recognize for EU. */ if(!AutoLoadFail) { struct registry_priv *registry_par = &padapter->registrypriv; if( registry_par->regulatory_tid == 0xff){ if(PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF) - pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION&0x7); //bit0~2 + pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION&0x7); /* bit0~2 */ else - pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_88E]&0x7); //bit0~2 + pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_88E]&0x7); /* bit0~2 */ }else{ pHalData->EEPROMRegulatory = registry_par->regulatory_tid; } @@ -3462,7 +3462,7 @@ Hal_EfuseParseCustomerID88E( if (!AutoLoadFail) { pHalData->EEPROMCustomerID = hwinfo[EEPROM_CUSTOMERID_88E]; - //pHalData->EEPROMSubCustomerID = hwinfo[EEPROM_CUSTOMERID_88E]; + /* pHalData->EEPROMSubCustomerID = hwinfo[EEPROM_CUSTOMERID_88E]; */ } else { @@ -3470,7 +3470,7 @@ Hal_EfuseParseCustomerID88E( pHalData->EEPROMSubCustomerID = 0; } DBG_871X("EEPROM Customer ID: 0x%2x\n", pHalData->EEPROMCustomerID); - //DBG_871X("EEPROM SubCustomer ID: 0x%02x\n", pHalData->EEPROMSubCustomerID); + /* DBG_871X("EEPROM SubCustomer ID: 0x%02x\n", pHalData->EEPROMSubCustomerID); */ } @@ -3486,8 +3486,8 @@ Hal_ReadAntennaDiversity88E( if(!AutoLoadFail) { - // Antenna Diversity setting. - if(registry_par->antdiv_cfg == 2)// 2:By EFUSE + /* Antenna Diversity setting. */ + if(registry_par->antdiv_cfg == 2)/* 2:By EFUSE */ { pHalData->AntDivCfg = (PROMContent[EEPROM_RF_BOARD_OPTION_88E]&0x18)>>3; if(PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF) @@ -3495,26 +3495,26 @@ Hal_ReadAntennaDiversity88E( } else { - pHalData->AntDivCfg = registry_par->antdiv_cfg ; // 0:OFF , 1:ON, 2:By EFUSE + pHalData->AntDivCfg = registry_par->antdiv_cfg ; /* 0:OFF , 1:ON, 2:By EFUSE */ } - if(registry_par->antdiv_type == 0)// If TRxAntDivType is AUTO in advanced setting, use EFUSE value instead. + if(registry_par->antdiv_type == 0)/* If TRxAntDivType is AUTO in advanced setting, use EFUSE value instead. */ { pHalData->TRxAntDivType = PROMContent[EEPROM_RF_ANTENNA_OPT_88E]; if (pHalData->TRxAntDivType == 0xFF) - pHalData->TRxAntDivType = CG_TRX_HW_ANTDIV; // For 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port) + pHalData->TRxAntDivType = CG_TRX_HW_ANTDIV; /* For 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port) */ } else{ pHalData->TRxAntDivType = registry_par->antdiv_type ; } if (pHalData->TRxAntDivType == CG_TRX_HW_ANTDIV || pHalData->TRxAntDivType == CGCS_RX_HW_ANTDIV) - pHalData->AntDivCfg = 1; // 0xC1[3] is ignored. + pHalData->AntDivCfg = 1; /* 0xC1[3] is ignored. */ } else { pHalData->AntDivCfg = 0; - pHalData->TRxAntDivType = pHalData->TRxAntDivType; // The value in the driver setting of device manager. + pHalData->TRxAntDivType = pHalData->TRxAntDivType; /* The value in the driver setting of device manager. */ } DBG_871X("EEPROM : AntDivCfg = %x, TRxAntDivType = %x\n",pHalData->AntDivCfg, pHalData->TRxAntDivType); @@ -3532,14 +3532,13 @@ Hal_ReadThermalMeter_88E( HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); u8 tempval; - // - // ThermalMeter from EEPROM - // + /* */ + /* ThermalMeter from EEPROM */ + /* */ if(!AutoloadFail) pHalData->EEPROMThermalMeter = PROMContent[EEPROM_THERMAL_METER_88E]; else pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_88E; -// pHalData->EEPROMThermalMeter = (tempval&0x1f); //[4:0] if(pHalData->EEPROMThermalMeter == 0xff || AutoloadFail) { @@ -3547,7 +3546,7 @@ Hal_ReadThermalMeter_88E( pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_88E; } - //pHalData->ThermalMeter[0] = pHalData->EEPROMThermalMeter; + /* pHalData->ThermalMeter[0] = pHalData->EEPROMThermalMeter; */ DBG_871X("ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter); } @@ -3568,7 +3567,7 @@ BOOLEAN HalDetectPwrDownMode88E(struct adapter *Adapter) EFUSE_ShadowRead(Adapter, 1, EEPROM_RF_FEATURE_OPTION_88E, (u32 *)&tmpvalue); - // 2010/08/25 MH INF priority > PDN Efuse value. + /* 2010/08/25 MH INF priority > PDN Efuse value. */ if(tmpvalue & BIT(4) && pwrctrlpriv->reg_pdnmode) { pHalData->pwrdown = true; @@ -3581,7 +3580,7 @@ BOOLEAN HalDetectPwrDownMode88E(struct adapter *Adapter) DBG_8192C("HalDetectPwrDownMode(): PDN=%d\n", pHalData->pwrdown); return pHalData->pwrdown; -} // HalDetectPwrDownMode +} /* HalDetectPwrDownMode */ #ifdef CONFIG_WOWLAN void Hal_DetectWoWMode(struct adapter *pAdapter) @@ -3599,10 +3598,10 @@ void Hal_ReadRFGainOffset( { u8 buff[EFUSE_MAX_SIZE]; u32 res; - // - // BB_RF Gain Offset from EEPROM - // - //res = rtw_efuse_access(Adapter, false, 0, EFUSE_MAX_SIZE, buff); + /* */ + /* BB_RF Gain Offset from EEPROM */ + /* */ + /* res = rtw_efuse_access(Adapter, false, 0, EFUSE_MAX_SIZE, buff); */ if(!AutoloadFail ){ Adapter->eeprompriv.EEPROMRFGainOffset = PROMContent[EEPROM_RF_GAIN_OFFSET_88E]; Adapter->eeprompriv.EEPROMRFGainVal=EFUSE_Read1Byte(Adapter, EEPROM_RF_GAIN_VAL_88E); @@ -3613,17 +3612,17 @@ void Hal_ReadRFGainOffset( } DBG_871X("EEPRORFGainOffset = 0x%02x\n", Adapter->eeprompriv.EEPROMRFGainOffset); } -#endif //CONFIG_RF_GAIN_OFFSET +#endif /* CONFIG_RF_GAIN_OFFSET */ -//==================================================================================== -// -// 20100209 Joseph: -// This function is used only for 92C to set REG_BCN_CTRL(0x550) register. -// We just reserve the value of the register in variable pHalData->RegBcnCtrlVal and then operate -// the value of the register via atomic operation. -// This prevents from race condition when setting this register. -// The value of pHalData->RegBcnCtrlVal is initialized in HwConfigureRTL8192CE() function. -// +/* */ +/* */ +/* 20100209 Joseph: */ +/* This function is used only for 92C to set REG_BCN_CTRL(0x550) register. */ +/* We just reserve the value of the register in variable pHalData->RegBcnCtrlVal and then operate */ +/* the value of the register via atomic operation. */ +/* This prevents from race condition when setting this register. */ +/* The value of pHalData->RegBcnCtrlVal is initialized in HwConfigureRTL8192CE() function. */ +/* */ void SetBcnCtrlReg( struct adapter *padapter, u8 SetBits, diff --git a/hal/rtl8188e_phycfg.c b/hal/rtl8188e_phycfg.c index aff5e9c..b04c7be 100755 --- a/hal/rtl8188e_phycfg.c +++ b/hal/rtl8188e_phycfg.c @@ -47,13 +47,13 @@ /*--------------------Define export function prototype-----------------------*/ -// Please refer to header file +/* Please refer to header file */ /*--------------------Define export function prototype-----------------------*/ /*----------------------------Function Body----------------------------------*/ -// -// 1. BB register R/W API -// +/* */ +/* 1. BB register R/W API */ +/* */ /** * Function: phy_CalculateBitShift @@ -96,49 +96,31 @@ sic_IsSICReady( { if(retryCnt++ >= SIC_MAX_POLL_CNT) { - //RTPRINT(FPHY, (PHY_SICR|PHY_SICW), ("[SIC], sic_IsSICReady() return FALSE\n")); + /* RTPRINT(FPHY, (PHY_SICR|PHY_SICW), ("[SIC], sic_IsSICReady() return FALSE\n")); */ return false; } - //if(RT_SDIO_CANNOT_IO(Adapter)) - // return false; + /* if(RT_SDIO_CANNOT_IO(Adapter)) */ + /* return false; */ sic_cmd = rtw_read8(Adapter, SIC_CMD_REG); - //sic_cmd = PlatformEFIORead1Byte(Adapter, SIC_CMD_REG); + /* sic_cmd = PlatformEFIORead1Byte(Adapter, SIC_CMD_REG); */ #if(SIC_HW_SUPPORT == 1) - sic_cmd &= 0xf0; // [7:4] + sic_cmd &= 0xf0; /* [7:4] */ #endif - //RTPRINT(FPHY, (PHY_SICR|PHY_SICW), ("[SIC], sic_IsSICReady(), readback 0x%x=0x%x\n", SIC_CMD_REG, sic_cmd)); + /* RTPRINT(FPHY, (PHY_SICR|PHY_SICW), ("[SIC], sic_IsSICReady(), readback 0x%x=0x%x\n", SIC_CMD_REG, sic_cmd)); */ if(sic_cmd == SIC_CMD_READY) return true; else { rtw_msleep_os(1); - //delay_ms(1); + /* delay_ms(1); */ } } return bRet; } -/* -u32 -sic_CalculateBitShift( - u32 BitMask - ) -{ - u32 i; - - for(i=0; i<=31; i++) - { - if ( ((BitMask>>i) & 0x1 ) == 1) - break; - } - - return (i); -} -*/ - static u32 sic_Read4Byte( void * Adapter, @@ -148,36 +130,36 @@ sic_Read4Byte( u32 u4ret=0xffffffff; u8 retry = 0; - //RTPRINT(FPHY, PHY_SICR, ("[SIC], sic_Read4Byte(): read offset(%#x)\n", offset)); + /* RTPRINT(FPHY, PHY_SICR, ("[SIC], sic_Read4Byte(): read offset(%#x)\n", offset)); */ if(sic_IsSICReady(Adapter)) { #if(SIC_HW_SUPPORT == 1) rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_PREREAD); - //PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_PREREAD); - //RTPRINT(FPHY, PHY_SICR, ("write cmdreg 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_PREREAD)); + /* PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_PREREAD); */ + /* RTPRINT(FPHY, PHY_SICR, ("write cmdreg 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_PREREAD)); */ #endif rtw_write8(Adapter, SIC_ADDR_REG, (u8)(offset&0xff)); - //PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG, (u8)(offset&0xff)); - //RTPRINT(FPHY, PHY_SICR, ("write 0x%x = 0x%x\n", SIC_ADDR_REG, (u8)(offset&0xff))); + /* PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG, (u8)(offset&0xff)); */ + /* RTPRINT(FPHY, PHY_SICR, ("write 0x%x = 0x%x\n", SIC_ADDR_REG, (u8)(offset&0xff))); */ rtw_write8(Adapter, SIC_ADDR_REG+1, (u8)((offset&0xff00)>>8)); - //PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG+1, (u8)((offset&0xff00)>>8)); - //RTPRINT(FPHY, PHY_SICR, ("write 0x%x = 0x%x\n", SIC_ADDR_REG+1, (u8)((offset&0xff00)>>8))); + /* PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG+1, (u8)((offset&0xff00)>>8)); */ + /* RTPRINT(FPHY, PHY_SICR, ("write 0x%x = 0x%x\n", SIC_ADDR_REG+1, (u8)((offset&0xff00)>>8))); */ rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_READ); - //PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_READ); - //RTPRINT(FPHY, PHY_SICR, ("write cmdreg 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_READ)); + /* PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_READ); */ + /* RTPRINT(FPHY, PHY_SICR, ("write cmdreg 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_READ)); */ retry = 4; while(retry--){ rtw_udelay_os(50); - //PlatformStallExecution(50); + /* PlatformStallExecution(50); */ } if(sic_IsSICReady(Adapter)) { u4ret = rtw_read32(Adapter, SIC_DATA_REG); - //u4ret = PlatformEFIORead4Byte(Adapter, SIC_DATA_REG); - //RTPRINT(FPHY, PHY_SICR, ("read 0x%x = 0x%x\n", SIC_DATA_REG, u4ret)); - //DbgPrint("<===Read 0x%x = 0x%x\n", offset, u4ret); + /* u4ret = PlatformEFIORead4Byte(Adapter, SIC_DATA_REG); */ + /* RTPRINT(FPHY, PHY_SICR, ("read 0x%x = 0x%x\n", SIC_DATA_REG, u4ret)); */ + /* DbgPrint("<===Read 0x%x = 0x%x\n", offset, u4ret); */ } } @@ -207,9 +189,9 @@ sic_Write4Byte( } } } -//============================================================ -// extern function -//============================================================ +/* */ +/* extern function */ +/* */ static void SIC_SetBBReg( IN struct adapter *Adapter, @@ -222,37 +204,23 @@ SIC_SetBBReg( u32 OriginalValue, BitShift; u16 BBWaitCounter = 0; - //RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg() start\n")); -/* - while(PlatformAtomicExchange(&pHalData->bChangeBBInProgress, true) == true) - { - BBWaitCounter ++; - delay_ms(10); // 1 ms + /* */ + /* Critical section start */ + /* */ - if((BBWaitCounter > 100) || RT_CANNOT_IO(Adapter)) - {// Wait too long, return FALSE to avoid to be stuck here. - RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg(), Fail to set BB offset(%#x)!!, WaitCnt(%d)\n", RegAddr, BBWaitCounter)); - return; - } - } -*/ - // - // Critical section start - // + /* RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg(), mask=0x%x, addr[0x%x]=0x%x\n", BitMask, RegAddr, Data)); */ - //RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg(), mask=0x%x, addr[0x%x]=0x%x\n", BitMask, RegAddr, Data)); - - if(BitMask!= bMaskDWord){//if not "double word" write + if(BitMask!= bMaskDWord){/* if not "double word" write */ OriginalValue = sic_Read4Byte(Adapter, RegAddr); - //BitShift = sic_CalculateBitShift(BitMask); + /* BitShift = sic_CalculateBitShift(BitMask); */ BitShift = phy_CalculateBitShift(BitMask); Data = (((OriginalValue) & (~BitMask)) | (Data << BitShift)); } sic_Write4Byte(Adapter, RegAddr, Data); - //PlatformAtomicExchange(&pHalData->bChangeBBInProgress, false); - //RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg() end\n")); + /* PlatformAtomicExchange(&pHalData->bChangeBBInProgress, false); */ + /* RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg() end\n")); */ } static u32 @@ -266,30 +234,17 @@ SIC_QueryBBReg( u32 ReturnValue = 0, OriginalValue, BitShift; u16 BBWaitCounter = 0; - //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_QueryBBReg() start\n")); + /* RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_QueryBBReg() start\n")); */ -/* - while(PlatformAtomicExchange(&pHalData->bChangeBBInProgress, true) == true) - { - BBWaitCounter ++; - delay_ms(10); // 10 ms - - if((BBWaitCounter > 100) || RT_CANNOT_IO(Adapter)) - {// Wait too long, return FALSE to avoid to be stuck here. - RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_QueryBBReg(), Fail to query BB offset(%#x)!!, WaitCnt(%d)\n", RegAddr, BBWaitCounter)); - return ReturnValue; - } - } -*/ OriginalValue = sic_Read4Byte(Adapter, RegAddr); - //BitShift = sic_CalculateBitShift(BitMask); + /* BitShift = sic_CalculateBitShift(BitMask); */ BitShift = phy_CalculateBitShift(BitMask); ReturnValue = (OriginalValue & BitMask) >> BitShift; - //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_QueryBBReg(), 0x%x=0x%x\n", RegAddr, OriginalValue)); - //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_QueryBBReg() end\n")); + /* RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_QueryBBReg(), 0x%x=0x%x\n", RegAddr, OriginalValue)); */ + /* RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_QueryBBReg() end\n")); */ - //PlatformAtomicExchange(&pHalData->bChangeBBInProgress, false); + /* PlatformAtomicExchange(&pHalData->bChangeBBInProgress, false); */ return (ReturnValue); } @@ -298,24 +253,24 @@ SIC_Init( IN struct adapter *Adapter ) { - // Here we need to write 0x1b8~0x1bf = 0 after fw is downloaded - // because for 8723E at beginning 0x1b8=0x1e, that will cause - // sic always not be ready + /* Here we need to write 0x1b8~0x1bf = 0 after fw is downloaded */ + /* because for 8723E at beginning 0x1b8=0x1e, that will cause */ + /* sic always not be ready */ #if(SIC_HW_SUPPORT == 1) - //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_Init(), write 0x%x = 0x%x\n", - // SIC_INIT_REG, SIC_INIT_VAL)); + /* RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_Init(), write 0x%x = 0x%x\n", */ + /* SIC_INIT_REG, SIC_INIT_VAL)); */ rtw_write8(Adapter, SIC_INIT_REG, SIC_INIT_VAL); - //PlatformEFIOWrite1Byte(Adapter, SIC_INIT_REG, SIC_INIT_VAL); - //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_Init(), write 0x%x = 0x%x\n", - // SIC_CMD_REG, SIC_CMD_INIT)); + /* PlatformEFIOWrite1Byte(Adapter, SIC_INIT_REG, SIC_INIT_VAL); */ + /* RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_Init(), write 0x%x = 0x%x\n", */ + /* SIC_CMD_REG, SIC_CMD_INIT)); */ rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_INIT); - //PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_INIT); + /* PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_INIT); */ #else - //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_Init(), write 0x1b8~0x1bf = 0x0\n")); + /* RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_Init(), write 0x1b8~0x1bf = 0x0\n")); */ rtw_write32(Adapter, SIC_CMD_REG, 0); - //PlatformEFIOWrite4Byte(Adapter, SIC_CMD_REG, 0); + /* PlatformEFIOWrite4Byte(Adapter, SIC_CMD_REG, 0); */ rtw_write32(Adapter, SIC_CMD_REG+4, 0); - //PlatformEFIOWrite4Byte(Adapter, SIC_CMD_REG+4, 0); + /* PlatformEFIOWrite4Byte(Adapter, SIC_CMD_REG+4, 0); */ #endif } @@ -324,8 +279,8 @@ SIC_LedOff( IN struct adapter *Adapter ) { - // When SIC is enabled, led pin will be used as debug pin, - // so don't execute led function when SIC is enabled. + /* When SIC is enabled, led pin will be used as debug pin, */ + /* so don't execute led function when SIC is enabled. */ return true; } #endif @@ -337,11 +292,11 @@ SIC_LedOff( * * Input: * struct adapter * Adapter, -* u32 RegAddr, //The target address to be readback -* u32 BitMask //The target bit position in the target address -* //to be readback +* u32 RegAddr, The target address to be readback +* u32 BitMask The target bit position in the target address +* to be readback * Output: None -* Return: u32 Data //The readback register value +* Return: u32 Data The readback register value * Note: This function is equal to "GetRegSetting" in PHY programming guide */ u32 @@ -362,17 +317,12 @@ rtl8188e_PHY_QueryBBReg( return SIC_QueryBBReg(Adapter, RegAddr, BitMask); #endif - //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx)\n", RegAddr, BitMask)); + /* RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx)\n", RegAddr, BitMask)); */ OriginalValue = rtw_read32(Adapter, RegAddr); BitShift = phy_CalculateBitShift(BitMask); ReturnValue = (OriginalValue & BitMask) >> BitShift; - - //RTPRINT(FPHY, PHY_BBR, ("BBR MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, OriginalValue)); - //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx), OriginalValue(%#lx)\n", RegAddr, BitMask, OriginalValue)); - return (ReturnValue); - } @@ -383,11 +333,11 @@ rtl8188e_PHY_QueryBBReg( * * Input: * struct adapter * Adapter, -* u32 RegAddr, //The target address to be modified -* u32 BitMask //The target bit position in the target address -* //to be modified -* u32 Data //The new register value in the target bit position -* //of the target address +* u32 RegAddr, The target address to be modified +* u32 BitMask The target bit position in the target address +* to be modified +* u32 Data The new register value in the target bit position +* of the target address * * Output: None * Return: None @@ -403,7 +353,7 @@ rtl8188e_PHY_SetBBReg( ) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - //u16 BBWaitCounter = 0; + /* u16 BBWaitCounter = 0; */ u32 OriginalValue, BitShift; #if (DISABLE_BB_RF == 1) @@ -415,25 +365,19 @@ rtl8188e_PHY_SetBBReg( return; #endif - //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data)); - - if(BitMask!= bMaskDWord){//if not "double word" write + if(BitMask!= bMaskDWord){/* if not "double word" write */ OriginalValue = rtw_read32(Adapter, RegAddr); BitShift = phy_CalculateBitShift(BitMask); Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask)); } rtw_write32(Adapter, RegAddr, Data); - - //RTPRINT(FPHY, PHY_BBW, ("BBW MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, Data)); - //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data)); - } -// -// 2. RF register R/W API -// +/* */ +/* 2. RF register R/W API */ +/* */ /** * Function: phy_RFSerialRead * @@ -441,8 +385,8 @@ rtl8188e_PHY_SetBBReg( * * Input: * struct adapter * Adapter, -* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D -* u32 Offset, //The target address to be read +* RF_RADIO_PATH_E eRFPath, Radio path of A/B/C/D +* u32 Offset, The target address to be read * * Output: None * Return: u32 reback value @@ -467,42 +411,42 @@ phy_RFSerialRead( u32 tmplong,tmplong2; u8 RfPiEnable=0; - // - // Make sure RF register offset is correct - // + /* */ + /* Make sure RF register offset is correct */ + /* */ Offset &= 0xff; - // - // Switch page for 8256 RF IC - // + /* */ + /* Switch page for 8256 RF IC */ + /* */ NewOffset = Offset; - // 2009/06/17 MH We can not execute IO for power save or other accident mode. - //if(RT_CANNOT_IO(Adapter)) - //{ - // RTPRINT(FPHY, PHY_RFR, ("phy_RFSerialRead return all one\n")); - // return 0xFFFFFFFF; - //} + /* 2009/06/17 MH We can not execute IO for power save or other accident mode. */ + /* if(RT_CANNOT_IO(Adapter)) */ + /* */ + /* RTPRINT(FPHY, PHY_RFR, ("phy_RFSerialRead return all one\n")); */ + /* return 0xFFFFFFFF; */ + /* */ - // For 92S LSSI Read RFLSSIRead - // For RF A/B write 0x824/82c(does not work in the future) - // We must use 0x824 for RF A and B to execute read trigger + /* For 92S LSSI Read RFLSSIRead */ + /* For RF A/B write 0x824/82c(does not work in the future) */ + /* We must use 0x824 for RF A and B to execute read trigger */ tmplong = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord); if(eRFPath == RF_PATH_A) tmplong2 = tmplong; else tmplong2 = PHY_QueryBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord); - tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; //T65 RF + tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; /* T65 RF */ PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge)); - rtw_udelay_os(10);// PlatformStallExecution(10); + rtw_udelay_os(10);/* PlatformStallExecution(10); */ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2); - rtw_udelay_os(100);//PlatformStallExecution(100); + rtw_udelay_os(100);/* PlatformStallExecution(100); */ - //PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge); - rtw_udelay_os(10);//PlatformStallExecution(10); + /* PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge); */ + rtw_udelay_os(10);/* PlatformStallExecution(10); */ if(eRFPath == RF_PATH_A) RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT8); @@ -510,16 +454,16 @@ phy_RFSerialRead( RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1, BIT8); if(RfPiEnable) - { // Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF + { /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */ retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData); - //DBG_8192C("Readback from RF-PI : 0x%x\n", retValue); + /* DBG_8192C("Readback from RF-PI : 0x%x\n", retValue); */ } else - { //Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF + { /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */ retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); - //DBG_8192C("Readback from RF-SI : 0x%x\n", retValue); + /* DBG_8192C("Readback from RF-SI : 0x%x\n", retValue); */ } - //DBG_8192C("RFR-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue); + /* DBG_8192C("RFR-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue); */ return retValue; @@ -534,10 +478,10 @@ phy_RFSerialRead( * * Input: * struct adapter * Adapter, -* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D -* u32 Offset, //The target address to be read -* u32 Data //The new register Data in the target bit position -* //of the target to be read +* RF_RADIO_PATH_E eRFPath, Radio path of A/B/C/D +* u32 Offset, The target address to be read +* u32 Data The new register Data in the target bit position +* of the target to be read * * Output: None * Return: None @@ -585,19 +529,19 @@ phy_RFSerialWrite( Offset &= 0xff; - // - // Switch page for 8256 RF IC - // + /* */ + /* Switch page for 8256 RF IC */ + /* */ NewOffset = Offset; - // - // Put write addr in [5:0] and write data in [31:16] - // - DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; // T65 RF + /* */ + /* Put write addr in [5:0] and write data in [31:16] */ + /* */ + DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; /* T65 RF */ - // - // Write Operation - // + /* */ + /* Write Operation */ + /* */ PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); } @@ -608,10 +552,10 @@ phy_RFSerialWrite( * * Input: * struct adapter * Adapter, -* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D -* u32 RegAddr, //The target address to be read -* u32 BitMask //The target bit position in the target address -* //to be read +* RF_RADIO_PATH_E eRFPath, Radio path of A/B/C/D +* u32 RegAddr, The target address to be read +* u32 BitMask The target bit position in the target address +* to be read * * Output: None * Return: u32 Readback value @@ -640,12 +584,12 @@ u32 rtl8188e_PHY_QueryRFReg(struct adapter *Adapter, RF_RADIO_PATH_E eRFPath, u3 * * Input: * struct adapter * Adapter, -* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D -* u32 RegAddr, //The target address to be modified -* u32 BitMask //The target bit position in the target address -* //to be modified -* u32 Data //The new register Data in the target bit position -* //of the target address +* RF_RADIO_PATH_E eRFPath, Radio path of A/B/C/D +* u32 RegAddr, The target address to be modified +* u32 BitMask The target bit position in the target address +* to be modified +* u32 Data The new register Data in the target bit position +* of the target address * * Output: None * Return: None @@ -661,16 +605,16 @@ rtl8188e_PHY_SetRFReg( ) { - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - //u8 RFWaitCounter = 0; + /* HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); */ + /* u8 RFWaitCounter = 0; */ u32 Original_Value, BitShift; - //_irqL irqL; + /* _irqL irqL; */ #if (DISABLE_BB_RF == 1) return; #endif - // RF data is 12 bits only + /* RF data is 12 bits only */ if (BitMask != bRFRegOffsetMask) { Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr); @@ -682,9 +626,9 @@ rtl8188e_PHY_SetRFReg( } -// -// 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. -// +/* */ +/* 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. */ +/* */ /*----------------------------------------------------------------------------- * Function: phy_ConfigMACWithParaFile() @@ -740,10 +684,10 @@ phy_ConfigMACWithHeaderFile( u32 i = 0; u32 ArrayLength = 0; u32* ptrArray; - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + /* HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); */ - //2008.11.06 Modified by tynli. - //RT_TRACE(COMP_INIT, DBG_LOUD, ("Read Rtl819XMACPHY_Array\n")); + /* 2008.11.06 Modified by tynli. */ + /* RT_TRACE(COMP_INIT, DBG_LOUD, ("Read Rtl819XMACPHY_Array\n")); */ ArrayLength = Rtl8188E_MAC_ArrayLength; ptrArray = (u32*)Rtl8188E_MAC_Array; @@ -753,14 +697,14 @@ phy_ConfigMACWithHeaderFile( if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) return _FAIL; - for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column + for(i = 0 ;i < ArrayLength;i=i+2){ /* Add by tynli for 2 column */ rtw_IOL_append_WB_cmd(xmit_frame, ptrArray[i], (u8)ptrArray[i+1]); } return rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0); } #else - for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column + for(i = 0 ;i < ArrayLength;i=i+2){ /* Add by tynli for 2 column */ rtw_write8(Adapter, ptrArray[i], (u8)ptrArray[i+1]); } #endif @@ -768,7 +712,7 @@ phy_ConfigMACWithHeaderFile( return _SUCCESS; } -#endif //#ifndef CONFIG_PHY_SETTING_WITH_ODM +#endif /* ifndef CONFIG_PHY_SETTING_WITH_ODM */ /*----------------------------------------------------------------------------- * Function: PHY_MACConfig8192C @@ -795,27 +739,27 @@ s32 PHY_MACConfig8188E(struct adapter *Adapter) pszMACRegFile = sz8188EMACRegFile; - // - // Config MAC - // + /* */ + /* Config MAC */ + /* */ #ifdef CONFIG_EMBEDDED_FWIMG #ifdef CONFIG_PHY_SETTING_WITH_ODM if(HAL_STATUS_FAILURE == ODM_ConfigMACWithHeaderFile(&pHalData->odmpriv)) rtStatus = _FAIL; #else rtStatus = phy_ConfigMACWithHeaderFile(Adapter); - #endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM + #endif/* ifdef CONFIG_PHY_SETTING_WITH_ODM */ #else - // Not make sure EEPROM, add later - //RT_TRACE(COMP_INIT, DBG_LOUD, ("Read MACREG.txt\n")); + /* Not make sure EEPROM, add later */ + /* RT_TRACE(COMP_INIT, DBG_LOUD, ("Read MACREG.txt\n")); */ rtStatus = phy_ConfigMACWithParaFile(Adapter, pszMACRegFile); -#endif//CONFIG_EMBEDDED_FWIMG +#endif/* CONFIG_EMBEDDED_FWIMG */ - // 2010.07.13 AMPDU aggregation number B + /* 2010.07.13 AMPDU aggregation number B */ rtw_write8(Adapter, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); - //rtw_write8(Adapter, REG_MAX_AGGR_NUM, 0x0B); + /* rtw_write8(Adapter, REG_MAX_AGGR_NUM, 0x0B); */ return rtStatus; @@ -841,103 +785,103 @@ phy_InitBBRFRegisterDefinition( { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - // RF Interface Sowrtware Control - pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870 - pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) - pHalData->PHYRegDef[RF_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874 - pHalData->PHYRegDef[RF_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) + /* RF Interface Sowrtware Control */ + pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */ + pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ + pHalData->PHYRegDef[RF_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;/* 16 LSBs if read 32-bit from 0x874 */ + pHalData->PHYRegDef[RF_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;/* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */ - // RF Interface Readback Value - pHalData->PHYRegDef[RF_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0 - pHalData->PHYRegDef[RF_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) - pHalData->PHYRegDef[RF_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4 - pHalData->PHYRegDef[RF_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) + /* RF Interface Readback Value */ + pHalData->PHYRegDef[RF_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; /* 16 LSBs if read 32-bit from 0x8E0 */ + pHalData->PHYRegDef[RF_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;/* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */ + pHalData->PHYRegDef[RF_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;/* 16 LSBs if read 32-bit from 0x8E4 */ + pHalData->PHYRegDef[RF_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;/* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */ - // RF Interface Output (and Enable) - pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860 - pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864 + /* RF Interface Output (and Enable) */ + pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */ + pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x864 */ - // RF Interface (Output and) Enable - pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) - pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) + /* RF Interface (Output and) Enable */ + pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ + pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ - //Addr of LSSI. Wirte RF register by driver - pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter + /* Addr of LSSI. Wirte RF register by driver */ + pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */ pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; - // RF parameter - pHalData->PHYRegDef[RF_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select + /* RF parameter */ + pHalData->PHYRegDef[RF_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; /* BB Band Select */ pHalData->PHYRegDef[RF_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; pHalData->PHYRegDef[RF_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; pHalData->PHYRegDef[RF_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; - // Tx AGC Gain Stage (same for all path. Should we remove this?) - pHalData->PHYRegDef[RF_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage - pHalData->PHYRegDef[RF_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage - pHalData->PHYRegDef[RF_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage - pHalData->PHYRegDef[RF_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage + /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ + pHalData->PHYRegDef[RF_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */ + pHalData->PHYRegDef[RF_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */ + pHalData->PHYRegDef[RF_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */ + pHalData->PHYRegDef[RF_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */ - // Tranceiver A~D HSSI Parameter-1 - pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1 - pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1 + /* Tranceiver A~D HSSI Parameter-1 */ + pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; /* wire control parameter1 */ + pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; /* wire control parameter1 */ - // Tranceiver A~D HSSI Parameter-2 - pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2 - pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2 + /* Tranceiver A~D HSSI Parameter-2 */ + pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; /* wire control parameter2 */ + pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; /* wire control parameter2 */ - // RF switch Control - pHalData->PHYRegDef[RF_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control + /* RF switch Control */ + pHalData->PHYRegDef[RF_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; /* TR/Ant switch control */ pHalData->PHYRegDef[RF_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; pHalData->PHYRegDef[RF_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; pHalData->PHYRegDef[RF_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; - // AGC control 1 + /* AGC control 1 */ pHalData->PHYRegDef[RF_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; pHalData->PHYRegDef[RF_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; pHalData->PHYRegDef[RF_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; pHalData->PHYRegDef[RF_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; - // AGC control 2 + /* AGC control 2 */ pHalData->PHYRegDef[RF_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; pHalData->PHYRegDef[RF_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; pHalData->PHYRegDef[RF_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; pHalData->PHYRegDef[RF_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; - // RX AFE control 1 + /* RX AFE control 1 */ pHalData->PHYRegDef[RF_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; pHalData->PHYRegDef[RF_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; pHalData->PHYRegDef[RF_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; pHalData->PHYRegDef[RF_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; - // RX AFE control 1 + /* RX AFE control 1 */ pHalData->PHYRegDef[RF_PATH_A].rfRxAFE = rOFDM0_XARxAFE; pHalData->PHYRegDef[RF_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; pHalData->PHYRegDef[RF_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; pHalData->PHYRegDef[RF_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; - // Tx AFE control 1 + /* Tx AFE control 1 */ pHalData->PHYRegDef[RF_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; pHalData->PHYRegDef[RF_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; pHalData->PHYRegDef[RF_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; pHalData->PHYRegDef[RF_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; - // Tx AFE control 2 + /* Tx AFE control 2 */ pHalData->PHYRegDef[RF_PATH_A].rfTxAFE = rOFDM0_XATxAFE; pHalData->PHYRegDef[RF_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; pHalData->PHYRegDef[RF_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; pHalData->PHYRegDef[RF_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; - // Tranceiver LSSI Readback SI mode + /* Tranceiver LSSI Readback SI mode */ pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; - // Tranceiver LSSI Readback PI mode + /* Tranceiver LSSI Readback PI mode */ pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback; pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback; - //pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack; - //pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack; + /* pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack; */ + /* pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack; */ } @@ -973,9 +917,9 @@ phy_ConfigBBWithParaFile( -//**************************************** -// The following is for High Power PA -//**************************************** +/* */ +/* The following is for High Power PA */ +/* */ static void phy_ConfigBBExternalPA( IN struct adapter * Adapter @@ -1018,8 +962,8 @@ phy_ConfigBBWithHeaderFile( Rtl819XAGCTAB_Array_Table = (u32*)Rtl8188E_AGCTAB_1TArray; PHY_REGArrayLen = Rtl8188E_PHY_REG_1TArrayLength; Rtl819XPHY_REGArray_Table = (u32*)Rtl8188E_PHY_REG_1TArray; -// RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8188EAGCTAB_1TArray\n")); -// RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8188EPHY_REG_1TArray\n")); +/* RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8188EAGCTAB_1TArray\n")); */ +/* RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8188EPHY_REG_1TArray\n")); */ if(ConfigType == CONFIG_BB_PHY_REG) { @@ -1053,7 +997,7 @@ phy_ConfigBBWithHeaderFile( podmpriv->RFCalibrateInfo.RegA24 = Rtl819XPHY_REGArray_Table[i+1]; rtw_IOL_append_WD_cmd(xmit_frame, Rtl819XPHY_REGArray_Table[i], tmp_value); - //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1])); + /* RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1])); */ } ret = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0); @@ -1083,13 +1027,13 @@ phy_ConfigBBWithHeaderFile( PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]); - // Add 1us delay between BB/RF register setting. + /* Add 1us delay between BB/RF register setting. */ rtw_udelay_os(1); - //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1])); + /* RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1])); */ } #endif - // for External PA + /* for External PA */ phy_ConfigBBExternalPA(Adapter); } else if(ConfigType == CONFIG_BB_AGC_TAB) @@ -1106,7 +1050,7 @@ phy_ConfigBBWithHeaderFile( for(i=0;iMCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0] = Data; - //printk("MCSTxPowerLevelOriginalOffset[%d][0]-TxAGC_A_Rate18_06 = 0x%x\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0]); + /* printk("MCSTxPowerLevelOriginalOffset[%d][0]-TxAGC_A_Rate18_06 = 0x%x\n", pHalData->pwrGroupCnt, */ + /* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0]); */ } if(RegAddr == rTxAGC_A_Rate54_24) { pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1] = Data; - //printk("MCSTxPowerLevelOriginalOffset[%d][1]-TxAGC_A_Rate54_24 = 0x%x\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1]); + /* printk("MCSTxPowerLevelOriginalOffset[%d][1]-TxAGC_A_Rate54_24 = 0x%x\n", pHalData->pwrGroupCnt, */ + /* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1]); */ } if(RegAddr == rTxAGC_A_CCK1_Mcs32) { pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6] = Data; - //printk("MCSTxPowerLevelOriginalOffset[%d][6]-TxAGC_A_CCK1_Mcs32 = 0x%x\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6]); + /* printk("MCSTxPowerLevelOriginalOffset[%d][6]-TxAGC_A_CCK1_Mcs32 = 0x%x\n", pHalData->pwrGroupCnt, */ + /* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6]); */ } if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0xffffff00) { pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7] = Data; - //printk("MCSTxPowerLevelOriginalOffset[%d][7]-TxAGC_B_CCK11_A_CCK2_11 = 0x%x\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7]); + /* printk("MCSTxPowerLevelOriginalOffset[%d][7]-TxAGC_B_CCK11_A_CCK2_11 = 0x%x\n", pHalData->pwrGroupCnt, */ + /* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7]); */ } if(RegAddr == rTxAGC_A_Mcs03_Mcs00) { pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2] = Data; - //printk("MCSTxPowerLevelOriginalOffset[%d][2]-TxAGC_A_Mcs03_Mcs00 = 0x%x\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2]); + /* printk("MCSTxPowerLevelOriginalOffset[%d][2]-TxAGC_A_Mcs03_Mcs00 = 0x%x\n", pHalData->pwrGroupCnt, */ + /* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2]); */ } if(RegAddr == rTxAGC_A_Mcs07_Mcs04) { pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3] = Data; - //printk("MCSTxPowerLevelOriginalOffset[%d][3]-TxAGC_A_Mcs07_Mcs04 = 0x%x\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3]); + /* printk("MCSTxPowerLevelOriginalOffset[%d][3]-TxAGC_A_Mcs07_Mcs04 = 0x%x\n", pHalData->pwrGroupCnt, */ + /* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3]); */ } if(RegAddr == rTxAGC_A_Mcs11_Mcs08) { pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4] = Data; - //printk("MCSTxPowerLevelOriginalOffset[%d][4]-TxAGC_A_Mcs11_Mcs08 = 0x%x\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4]); + /* printk("MCSTxPowerLevelOriginalOffset[%d][4]-TxAGC_A_Mcs11_Mcs08 = 0x%x\n", pHalData->pwrGroupCnt, */ + /* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4]); */ } if(RegAddr == rTxAGC_A_Mcs15_Mcs12) { pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5] = Data; - //printk("MCSTxPowerLevelOriginalOffset[%d][5]-TxAGC_A_Mcs15_Mcs12 = 0x%x\n", pHalData->pwrGroupCnt,pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5]); + /* printk("MCSTxPowerLevelOriginalOffset[%d][5]-TxAGC_A_Mcs15_Mcs12 = 0x%x\n", pHalData->pwrGroupCnt,pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5]); */ if(pHalData->rf_type== RF_1T1R) { - //printk("pwrGroupCnt = %d\n", pHalData->pwrGroupCnt); + /* printk("pwrGroupCnt = %d\n", pHalData->pwrGroupCnt); */ pHalData->pwrGroupCnt++; } } if(RegAddr == rTxAGC_B_Rate18_06) { pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8] = Data; - //printk("MCSTxPowerLevelOriginalOffset[%d][8]-TxAGC_B_Rate18_06 = 0x%x\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8]); + /* printk("MCSTxPowerLevelOriginalOffset[%d][8]-TxAGC_B_Rate18_06 = 0x%x\n", pHalData->pwrGroupCnt, */ + /* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8]); */ } if(RegAddr == rTxAGC_B_Rate54_24) { pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9] = Data; - //printk("MCSTxPowerLevelOriginalOffset[%d][9]-TxAGC_B_Rate54_24 = 0x%x\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9]); + /* printk("MCSTxPowerLevelOriginalOffset[%d][9]-TxAGC_B_Rate54_24 = 0x%x\n", pHalData->pwrGroupCnt, */ + /* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9]); */ } if(RegAddr == rTxAGC_B_CCK1_55_Mcs32) { pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14] = Data; - //printk("MCSTxPowerLevelOriginalOffset[%d][14]-TxAGC_B_CCK1_55_Mcs32 = 0x%x\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14]); + /* printk("MCSTxPowerLevelOriginalOffset[%d][14]-TxAGC_B_CCK1_55_Mcs32 = 0x%x\n", pHalData->pwrGroupCnt, */ + /* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14]); */ } if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0x000000ff) { pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15] = Data; - //printk("MCSTxPowerLevelOriginalOffset[%d][15]-TxAGC_B_CCK11_A_CCK2_11 = 0x%x\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15]); + /* printk("MCSTxPowerLevelOriginalOffset[%d][15]-TxAGC_B_CCK11_A_CCK2_11 = 0x%x\n", pHalData->pwrGroupCnt, */ + /* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15]); */ } if(RegAddr == rTxAGC_B_Mcs03_Mcs00) { pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10] = Data; - //printk("MCSTxPowerLevelOriginalOffset[%d][10]-TxAGC_B_Mcs03_Mcs00 = 0x%x\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10]); + /* printk("MCSTxPowerLevelOriginalOffset[%d][10]-TxAGC_B_Mcs03_Mcs00 = 0x%x\n", pHalData->pwrGroupCnt, */ + /* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10]); */ } if(RegAddr == rTxAGC_B_Mcs07_Mcs04) { pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11] = Data; - //printk("MCSTxPowerLevelOriginalOffset[%d][11]-TxAGC_B_Mcs07_Mcs04 = 0x%x\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11]); + /* printk("MCSTxPowerLevelOriginalOffset[%d][11]-TxAGC_B_Mcs07_Mcs04 = 0x%x\n", pHalData->pwrGroupCnt, */ + /* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11]); */ } if(RegAddr == rTxAGC_B_Mcs11_Mcs08) { pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12] = Data; - //printk("MCSTxPowerLevelOriginalOffset[%d][12]-TxAGC_B_Mcs11_Mcs08 = 0x%x\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12]); + /* printk("MCSTxPowerLevelOriginalOffset[%d][12]-TxAGC_B_Mcs11_Mcs08 = 0x%x\n", pHalData->pwrGroupCnt, */ + /* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12]); */ } if(RegAddr == rTxAGC_B_Mcs15_Mcs12) { pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13] = Data; - //printk("MCSTxPowerLevelOriginalOffset[%d][13]-TxAGC_B_Mcs15_Mcs12 = 0x%x\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13]); + /* printk("MCSTxPowerLevelOriginalOffset[%d][13]-TxAGC_B_Mcs15_Mcs12 = 0x%x\n", pHalData->pwrGroupCnt, */ + /* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13]); */ if(pHalData->rf_type != RF_1T1R) { - //printk("pwrGroupCnt = %d\n", pHalData->pwrGroupCnt); + /* printk("pwrGroupCnt = %d\n", pHalData->pwrGroupCnt); */ pHalData->pwrGroupCnt++; } } @@ -1318,7 +1262,7 @@ phy_ConfigBBWithPgHeaderFile( return _SUCCESS; } /* phy_ConfigBBWithPgHeaderFile */ -#endif //CONFIG_PHY_SETTING_WITH_ODM +#endif /* CONFIG_PHY_SETTING_WITH_ODM */ @@ -1327,14 +1271,14 @@ phy_BB8192C_Config_1T( IN struct adapter *Adapter ) { - //for path - B + /* for path - B */ PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x2); PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x300033, 0x200022); - // 20100519 Joseph: Add for 1T2R config. Suggested by Kevin, Jenyu and Yunan. + /* 20100519 Joseph: Add for 1T2R config. Suggested by Kevin, Jenyu and Yunan. */ PHY_SetBBReg(Adapter, rCCK0_AFESetting, bMaskByte3, 0x45); PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskByte0, 0x23); - PHY_SetBBReg(Adapter, rOFDM0_AGCParameter1, 0x30, 0x1); // B path first AGC + PHY_SetBBReg(Adapter, rOFDM0_AGCParameter1, 0x30, 0x1); /* B path first AGC */ PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x2); PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x2); @@ -1345,15 +1289,15 @@ phy_BB8192C_Config_1T( } -// Joseph test: new initialize order!! -// Test only!! This part need to be re-organized. -// Now it is just for 8256. +/* Joseph test: new initialize order!! */ +/* Test only!! This part need to be re-organized. */ +/* Now it is just for 8256. */ static int phy_BB8190_Config_HardCode( IN struct adapter *Adapter ) { - //RT_ASSERT(FALSE, ("This function is not implement yet!! \n")); + /* RT_ASSERT(FALSE, ("This function is not implement yet!! \n")); */ return _SUCCESS; } @@ -1374,47 +1318,47 @@ phy_BB8188E_Config_ParaFile( u8 *pszBBRegFile = NULL, *pszAGCTableFile = NULL, *pszBBRegPgFile = NULL, *pszBBRegMpFile=NULL; - //RT_TRACE(COMP_INIT, DBG_TRACE, ("==>phy_BB8192S_Config_ParaFile\n")); + /* RT_TRACE(COMP_INIT, DBG_TRACE, ("==>phy_BB8192S_Config_ParaFile\n")); */ pszBBRegFile = sz8188EBBRegFile ; pszAGCTableFile = sz8188EAGCTableFile; pszBBRegPgFile = sz8188EBBRegPgFile; pszBBRegMpFile = sz8188EBBRegMpFile; - // - // 1. Read PHY_REG.TXT BB INIT!! - // We will seperate as 88C / 92C according to chip version - // + /* */ + /* 1. Read PHY_REG.TXT BB INIT!! */ + /* We will seperate as 88C / 92C according to chip version */ + /* */ #ifdef CONFIG_EMBEDDED_FWIMG #ifdef CONFIG_PHY_SETTING_WITH_ODM if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG)) rtStatus = _FAIL; #else rtStatus = phy_ConfigBBWithHeaderFile(Adapter, CONFIG_BB_PHY_REG); - #endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM + #endif/* ifdef CONFIG_PHY_SETTING_WITH_ODM */ #else - // No matter what kind of CHIP we always read PHY_REG.txt. We must copy different - // type of parameter files to phy_reg.txt at first. + /* No matter what kind of CHIP we always read PHY_REG.txt. We must copy different */ + /* type of parameter files to phy_reg.txt at first. */ rtStatus = phy_ConfigBBWithParaFile(Adapter,pszBBRegFile); -#endif//#ifdef CONFIG_EMBEDDED_FWIMG +#endif/* ifdef CONFIG_EMBEDDED_FWIMG */ if(rtStatus != _SUCCESS){ - //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!")); + /* RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!")); */ goto phy_BB8190_Config_ParaFile_Fail; } - // - // 20100318 Joseph: Config 2T2R to 1T2R if necessary. - // - //if(pHalData->rf_type == RF_1T2R) - //{ - //phy_BB8192C_Config_1T(Adapter); - //DBG_8192C("phy_BB8188E_Config_ParaFile():Config to 1T!!\n"); - //} + /* */ + /* 20100318 Joseph: Config 2T2R to 1T2R if necessary. */ + /* */ + /* if(pHalData->rf_type == RF_1T2R) */ + /* */ + /* phy_BB8192C_Config_1T(Adapter); */ + /* DBG_8192C("phy_BB8188E_Config_ParaFile():Config to 1T!!\n"); */ + /* */ - // - // 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt - // + /* */ + /* 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */ + /* */ if (pEEPROM->bautoload_fail_flag == false) { pHalData->pwrGroupCnt = 0; @@ -1432,27 +1376,27 @@ phy_BB8188E_Config_ParaFile( } if(rtStatus != _SUCCESS){ - //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!")); + /* RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!")); */ goto phy_BB8190_Config_ParaFile_Fail; } - // - // 3. BB AGC table Initialization - // + /* */ + /* 3. BB AGC table Initialization */ + /* */ #ifdef CONFIG_EMBEDDED_FWIMG #ifdef CONFIG_PHY_SETTING_WITH_ODM if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB)) rtStatus = _FAIL; #else rtStatus = phy_ConfigBBWithHeaderFile(Adapter, CONFIG_BB_AGC_TAB); - #endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM + #endif/* ifdef CONFIG_PHY_SETTING_WITH_ODM */ #else - //RT_TRACE(COMP_INIT, DBG_LOUD, ("phy_BB8192S_Config_ParaFile AGC_TAB.txt\n")); + /* RT_TRACE(COMP_INIT, DBG_LOUD, ("phy_BB8192S_Config_ParaFile AGC_TAB.txt\n")); */ rtStatus = phy_ConfigBBWithParaFile(Adapter, pszAGCTableFile); -#endif//#ifdef CONFIG_EMBEDDED_FWIMG +#endif/* ifdef CONFIG_EMBEDDED_FWIMG */ if(rtStatus != _SUCCESS){ - //RT_TRACE(COMP_FPGA, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():AGC Table Fail\n")); + /* RT_TRACE(COMP_FPGA, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():AGC Table Fail\n")); */ goto phy_BB8190_Config_ParaFile_Fail; } @@ -1477,24 +1421,24 @@ PHY_BBConfig8188E( phy_InitBBRFRegisterDefinition(Adapter); - // Enable BB and RF + /* Enable BB and RF */ RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN); rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1)); - // 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF. - //rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x83); - //rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xdb); + /* 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF. */ + /* rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x83); */ + /* rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xdb); */ rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB); rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB); - // - // Config BB and AGC - // + /* */ + /* Config BB and AGC */ + /* */ rtStatus = phy_BB8188E_Config_ParaFile(Adapter); - // write 0x24[16:11] = 0x24[22:17] = CrystalCap + /* write 0x24[16:11] = 0x24[22:17] = CrystalCap */ CrystalCap = pHalData->CrystalCap & 0x3F; PHY_SetBBReg(Adapter, REG_AFE_XTAL_CTRL, 0x7ff800, (CrystalCap | (CrystalCap << 6))); @@ -1511,9 +1455,9 @@ PHY_RFConfig8188E( HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); int rtStatus = _SUCCESS; - // - // RF config - // + /* */ + /* RF config */ + /* */ rtStatus = PHY_RF6052_Config8188E(Adapter); return rtStatus; } @@ -1550,11 +1494,11 @@ rtl8188e_PHY_ConfigRFWithParaFile( } -//**************************************** -// The following is for High Power PA -//**************************************** +/* */ +/* The following is for High Power PA */ +/* */ #define HighPowerRadioAArrayLen 22 -//This is for High power PA +/* This is for High power PA */ static u32 Rtl8192S_HighPower_RadioA_Array[HighPowerRadioAArrayLen] = { 0x013,0x00029ea4, 0x013,0x00025e74, @@ -1583,7 +1527,7 @@ PHY_ConfigRFExternalPA( return rtStatus; return rtStatus; } -//**************************************** +/* */ /*----------------------------------------------------------------------------- * Function: PHY_ConfigRFWithHeaderFile() * @@ -1619,8 +1563,8 @@ rtl8188e_PHY_ConfigRFWithHeaderFile( Rtl819XRadioA_Array_Table = (u32*)Rtl8188E_RadioA_1TArray; RadioB_ArrayLen = Rtl8188E_RadioB_1TArrayLength; Rtl819XRadioB_Array_Table = (u32*)Rtl8188E_RadioB_1TArray; -// RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> PHY_ConfigRFWithHeaderFile() Radio_A:Rtl8188ERadioA_1TArray\n")); -// RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> PHY_ConfigRFWithHeaderFile() Radio_B:Rtl8188ERadioB_1TArray\n")); +/* RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> PHY_ConfigRFWithHeaderFile() Radio_A:Rtl8188ERadioA_1TArray\n")); */ +/* RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> PHY_ConfigRFWithHeaderFile() Radio_B:Rtl8188ERadioB_1TArray\n")); */ switch (eRFPath) { @@ -1654,7 +1598,7 @@ rtl8188e_PHY_ConfigRFWithHeaderFile( u32 DataAndAddr = 0; NewOffset = Rtl819XRadioA_Array_Table[i] & 0x3f; - DataAndAddr = ((NewOffset<<20) | (Rtl819XRadioA_Array_Table[i+1]&0x000fffff)) & 0x0fffffff; // T65 RF + DataAndAddr = ((NewOffset<<20) | (Rtl819XRadioA_Array_Table[i+1]&0x000fffff)) & 0x0fffffff; /* T65 RF */ rtw_IOL_append_WD_cmd(xmit_frame, pPhyReg->rf3wireOffset, DataAndAddr); } } @@ -1683,12 +1627,12 @@ rtl8188e_PHY_ConfigRFWithHeaderFile( else { PHY_SetRFReg(Adapter, eRFPath, Rtl819XRadioA_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioA_Array_Table[i+1]); - // Add 1us delay between BB/RF register setting. + /* Add 1us delay between BB/RF register setting. */ rtw_udelay_os(1); } } #endif - //Add for High Power PA + /* Add for High Power PA */ PHY_ConfigRFExternalPA(Adapter, eRFPath); break; case RF_PATH_B: @@ -1721,7 +1665,7 @@ rtl8188e_PHY_ConfigRFWithHeaderFile( u32 DataAndAddr = 0; NewOffset = Rtl819XRadioB_Array_Table[i] & 0x3f; - DataAndAddr = ((NewOffset<<20) | (Rtl819XRadioB_Array_Table[i+1]&0x000fffff)) & 0x0fffffff; // T65 RF + DataAndAddr = ((NewOffset<<20) | (Rtl819XRadioB_Array_Table[i+1]&0x000fffff)) & 0x0fffffff; /* T65 RF */ rtw_IOL_append_WD_cmd(xmit_frame, pPhyReg->rf3wireOffset, DataAndAddr); } } @@ -1731,7 +1675,7 @@ rtl8188e_PHY_ConfigRFWithHeaderFile( for(i = 0;i actually we call PlatformStallExecution()) to do NdisStallExecution() - // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK - // to run at Dispatch level to achive it. - //cosa PlatformAcquireSpinLock(Adapter, RT_INITIAL_SPINLOCK); + /* When initialization, we want the delay function(delay_ms(), delay_us() */ + /* ==> actually we call PlatformStallExecution()) to do NdisStallExecution() */ + /* [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK */ + /* to run at Dispatch level to achive it. */ + /* cosa PlatformAcquireSpinLock(Adapter, RT_INITIAL_SPINLOCK); */ WriteData[i] &= 0xfff; PHY_SetRFReg(Adapter, eRFPath, WriteAddr[HW90_BLOCK_RF], bRFRegOffsetMask, WriteData[i]); - // TODO: we should not delay for such a long time. Ask SD3 + /* TODO: we should not delay for such a long time. Ask SD3 */ rtw_mdelay_os(10); ulRegRead = PHY_QueryRFReg(Adapter, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord); rtw_mdelay_os(10); - //cosa PlatformReleaseSpinLock(Adapter, RT_INITIAL_SPINLOCK); + /* cosa PlatformReleaseSpinLock(Adapter, RT_INITIAL_SPINLOCK); */ break; default: @@ -1845,12 +1789,12 @@ PHY_CheckBBAndRFOK( } - // - // Check whether readback data is correct - // + /* */ + /* Check whether readback data is correct */ + /* */ if(ulRegRead != WriteData[i]) { - //RT_TRACE(COMP_FPGA, DBG_LOUD, ("ulRegRead: %lx, WriteData: %lx \n", ulRegRead, WriteData[i])); + /* RT_TRACE(COMP_FPGA, DBG_LOUD, ("ulRegRead: %lx, WriteData: %lx \n", ulRegRead, WriteData[i])); */ rtStatus = _FAIL; break; } @@ -1867,31 +1811,31 @@ rtl8192c_PHY_GetHWRegOriginalValue( { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - // read rx initial gain + /* read rx initial gain */ pHalData->DefaultInitialGain[0] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XAAGCCore1, bMaskByte0); pHalData->DefaultInitialGain[1] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XBAGCCore1, bMaskByte0); pHalData->DefaultInitialGain[2] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XCAGCCore1, bMaskByte0); pHalData->DefaultInitialGain[3] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XDAGCCore1, bMaskByte0); - //RT_TRACE(COMP_INIT, DBG_LOUD, - //("Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n", - //pHalData->DefaultInitialGain[0], pHalData->DefaultInitialGain[1], - //pHalData->DefaultInitialGain[2], pHalData->DefaultInitialGain[3])); + /* RT_TRACE(COMP_INIT, DBG_LOUD, */ + /* Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n", */ + /* pHalData->DefaultInitialGain[0], pHalData->DefaultInitialGain[1], */ + /* pHalData->DefaultInitialGain[2], pHalData->DefaultInitialGain[3])); */ - // read framesync + /* read framesync */ pHalData->framesync = (u8)PHY_QueryBBReg(Adapter, rOFDM0_RxDetector3, bMaskByte0); pHalData->framesyncC34 = PHY_QueryBBReg(Adapter, rOFDM0_RxDetector2, bMaskDWord); - //RT_TRACE(COMP_INIT, DBG_LOUD, ("Default framesync (0x%x) = 0x%x \n", - // rOFDM0_RxDetector3, pHalData->framesync)); + /* RT_TRACE(COMP_INIT, DBG_LOUD, ("Default framesync (0x%x) = 0x%x \n", */ + /* rOFDM0_RxDetector3, pHalData->framesync)); */ } -// -// Description: -// Map dBm into Tx power index according to -// current HW model, for example, RF and PA, and -// current wireless mode. -// By Bruce, 2008-01-29. -// +/* */ +/* Description: */ +/* Map dBm into Tx power index according to */ +/* current HW model, for example, RF and PA, and */ +/* current wireless mode. */ +/* By Bruce, 2008-01-29. */ +/* */ static u8 phy_DbmToTxPwrIdx( IN struct adapter * Adapter, @@ -1903,13 +1847,13 @@ phy_DbmToTxPwrIdx( int Offset = 0; - // - // Tested by MP, we found that CCK Index 0 equals to 8dbm, OFDM legacy equals to - // 3dbm, and OFDM HT equals to 0dbm repectively. - // Note: - // The mapping may be different by different NICs. Do not use this formula for what needs accurate result. - // By Bruce, 2008-01-29. - // + /* */ + /* Tested by MP, we found that CCK Index 0 equals to 8dbm, OFDM legacy equals to */ + /* 3dbm, and OFDM HT equals to 0dbm repectively. */ + /* Note: */ + /* The mapping may be different by different NICs. Do not use this formula for what needs accurate result. */ + /* By Bruce, 2008-01-29. */ + /* */ switch(WirelessMode) { case WIRELESS_MODE_B: @@ -1934,20 +1878,20 @@ phy_DbmToTxPwrIdx( TxPwrIdx = 0; } - // Tx Power Index is too large. + /* Tx Power Index is too large. */ if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S) TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S; return TxPwrIdx; } -// -// Description: -// Map Tx power index into dBm according to -// current HW model, for example, RF and PA, and -// current wireless mode. -// By Bruce, 2008-01-29. -// +/* */ +/* Description: */ +/* Map Tx power index into dBm according to */ +/* current HW model, for example, RF and PA, and */ +/* current wireless mode. */ +/* By Bruce, 2008-01-29. */ +/* */ static int phy_TxPwrIdxToDbm( IN struct adapter * Adapter, @@ -1958,12 +1902,12 @@ phy_TxPwrIdxToDbm( int Offset = 0; int PwrOutDbm = 0; - // - // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to -8dbm. - // Note: - // The mapping may be different by different NICs. Do not use this formula for what needs accurate result. - // By Bruce, 2008-01-29. - // + /* */ + /* Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to -8dbm. */ + /* Note: */ + /* The mapping may be different by different NICs. Do not use this formula for what needs accurate result. */ + /* By Bruce, 2008-01-29. */ + /* */ switch(WirelessMode) { case WIRELESS_MODE_B: @@ -1978,7 +1922,7 @@ phy_TxPwrIdxToDbm( break; } - PwrOutDbm = TxPwrIdx / 2 + Offset; // Discard the decimal part. + PwrOutDbm = TxPwrIdx / 2 + Offset; /* Discard the decimal part. */ return PwrOutDbm; } @@ -2007,26 +1951,26 @@ PHY_GetTxPowerLevel8188E( u8 TxPwrLevel = 0; int TxPwrDbm; - // - // Because the Tx power indexes are different, we report the maximum of them to - // meet the CCX TPC request. By Bruce, 2008-01-31. - // + /* */ + /* Because the Tx power indexes are different, we report the maximum of them to */ + /* meet the CCX TPC request. By Bruce, 2008-01-31. */ + /* */ - // CCK + /* CCK */ TxPwrLevel = pHalData->CurrentCckTxPwrIdx; TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_B, TxPwrLevel); - // Legacy OFDM + /* Legacy OFDM */ TxPwrLevel = pHalData->CurrentOfdm24GTxPwrIdx + pHalData->LegacyHTTxPowerDiff; - // Compare with Legacy OFDM Tx power. + /* Compare with Legacy OFDM Tx power. */ if(phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm) TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel); - // HT OFDM + /* HT OFDM */ TxPwrLevel = pHalData->CurrentOfdm24GTxPwrIdx; - // Compare with HT OFDM Tx power. + /* Compare with HT OFDM Tx power. */ if(phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm) TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel); @@ -2057,72 +2001,72 @@ static void getTxPowerIndex88E( { if(TxCount==RF_PATH_A) { - // 1. CCK + /* 1. CCK */ cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index]; - //2. OFDM + /* 2. OFDM */ ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ pHalData->OFDM_24G_Diff[TxCount][RF_PATH_A]; - // 1. BW20 + /* 1. BW20 */ BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ pHalData->BW20_24G_Diff[TxCount][RF_PATH_A]; - //2. BW40 + /* 2. BW40 */ BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index]; - //RTPRINT(FPHY, PHY_TXPWR, ("getTxPowerIndex88E(): 40MBase=0x%x 20Mdiff=%d 20MBase=0x%x!!\n", - // pHalData->Index24G_BW40_Base[RF_PATH_A][index], - // pHalData->BW20_24G_Diff[TxCount][RF_PATH_A], - // BW20PowerLevel[TxCount])); + /* RTPRINT(FPHY, PHY_TXPWR, ("getTxPowerIndex88E(): 40MBase=0x%x 20Mdiff=%d 20MBase=0x%x!!\n", */ + /* pHalData->Index24G_BW40_Base[RF_PATH_A][index], */ + /* pHalData->BW20_24G_Diff[TxCount][RF_PATH_A], */ + /* BW20PowerLevel[TxCount])); */ } else if(TxCount==RF_PATH_B) { - // 1. CCK + /* 1. CCK */ cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index]; - //2. OFDM + /* 2. OFDM */ ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ pHalData->BW20_24G_Diff[RF_PATH_A][index]+ pHalData->BW20_24G_Diff[TxCount][index]; - // 1. BW20 + /* 1. BW20 */ BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ pHalData->BW20_24G_Diff[TxCount][RF_PATH_A]+ pHalData->BW20_24G_Diff[TxCount][index]; - //2. BW40 + /* 2. BW40 */ BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index]; } else if(TxCount==RF_PATH_C) { - // 1. CCK + /* 1. CCK */ cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index]; - //2. OFDM + /* 2. OFDM */ ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ pHalData->BW20_24G_Diff[RF_PATH_A][index]+ pHalData->BW20_24G_Diff[RF_PATH_B][index]+ pHalData->BW20_24G_Diff[TxCount][index]; - // 1. BW20 + /* 1. BW20 */ BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ pHalData->BW20_24G_Diff[RF_PATH_A][index]+ pHalData->BW20_24G_Diff[RF_PATH_B][index]+ pHalData->BW20_24G_Diff[TxCount][index]; - //2. BW40 + /* 2. BW40 */ BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index]; } else if(TxCount==RF_PATH_D) { - // 1. CCK + /* 1. CCK */ cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index]; - //2. OFDM + /* 2. OFDM */ ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ pHalData->BW20_24G_Diff[RF_PATH_A][index]+ pHalData->BW20_24G_Diff[RF_PATH_B][index]+ pHalData->BW20_24G_Diff[RF_PATH_C][index]+ pHalData->BW20_24G_Diff[TxCount][index]; - // 1. BW20 + /* 1. BW20 */ BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+ pHalData->BW20_24G_Diff[RF_PATH_A][index]+ pHalData->BW20_24G_Diff[RF_PATH_B][index]+ pHalData->BW20_24G_Diff[RF_PATH_C][index]+ pHalData->BW20_24G_Diff[TxCount][index]; - //2. BW40 + /* 2. BW40 */ BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index]; } else @@ -2174,7 +2118,7 @@ PHY_SetTxPowerLevel8188E( { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u8 cckPowerLevel[MAX_TX_COUNT], ofdmPowerLevel[MAX_TX_COUNT];// [0]:RF-A, [1]:RF-B + u8 cckPowerLevel[MAX_TX_COUNT], ofdmPowerLevel[MAX_TX_COUNT];/* [0]:RF-A, [1]:RF-B */ u8 BW20PowerLevel[MAX_TX_COUNT], BW40PowerLevel[MAX_TX_COUNT]; u8 i=0; /* @@ -2183,16 +2127,16 @@ PHY_SetTxPowerLevel8188E( return; #endif */ - //getTxPowerIndex(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]); + /* getTxPowerIndex(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]); */ getTxPowerIndex88E(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0],&BW20PowerLevel[0],&BW40PowerLevel[0]); - //printk("Channel-%d, cckPowerLevel = 0x%x, ofdmPowerLeve = 0x%x, BW20PowerLevel = 0x%x, BW40PowerLevel = 0x%x,\n", - // channel, cckPowerLevel[0], ofdmPowerLevel[0], BW20PowerLevel[0] ,BW40PowerLevel[0]); + /* printk("Channel-%d, cckPowerLevel = 0x%x, ofdmPowerLeve = 0x%x, BW20PowerLevel = 0x%x, BW40PowerLevel = 0x%x,\n", */ + /* channel, cckPowerLevel[0], ofdmPowerLevel[0], BW20PowerLevel[0] ,BW40PowerLevel[0]); */ - //RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n", - // channel, cckPowerLevel[0], cckPowerLevel[1], ofdmPowerLevel[0], ofdmPowerLevel[1])); + /* RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n", */ + /* channel, cckPowerLevel[0], cckPowerLevel[1], ofdmPowerLevel[0], ofdmPowerLevel[1])); */ - //ccxPowerIndexCheck(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]); + /* ccxPowerIndexCheck(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]); */ phy_PowerIndexCheck88E(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0],&BW20PowerLevel[0],&BW40PowerLevel[0]); rtl8188e_PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]); @@ -2200,14 +2144,14 @@ PHY_SetTxPowerLevel8188E( } -// -// Description: -// Update transmit power level of all channel supported. -// -// TODO: -// A mode. -// By Bruce, 2008-02-04. -// +/* */ +/* Description: */ +/* Update transmit power level of all channel supported. */ +/* */ +/* TODO: */ +/* A mode. */ +/* By Bruce, 2008-02-04. */ +/* */ BOOLEAN PHY_UpdateTxPowerDbm8188E( IN struct adapter *Adapter, @@ -2218,7 +2162,7 @@ PHY_UpdateTxPowerDbm8188E( u8 idx; u8 rf_path; - // TODO: A mode Tx power. + /* TODO: A mode Tx power. */ u8 CckTxPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, powerInDbm); u8 OfdmTxPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, powerInDbm); @@ -2227,7 +2171,7 @@ PHY_UpdateTxPowerDbm8188E( else OfdmTxPwrIdx = 0; - //RT_TRACE(COMP_TXAGC, DBG_LOUD, ("PHY_UpdateTxPowerDbm8192S(): %ld dBm , CckTxPwrIdx = %d, OfdmTxPwrIdx = %d\n", powerInDbm, CckTxPwrIdx, OfdmTxPwrIdx)); + /* RT_TRACE(COMP_TXAGC, DBG_LOUD, ("PHY_UpdateTxPowerDbm8192S(): %ld dBm , CckTxPwrIdx = %d, OfdmTxPwrIdx = %d\n", powerInDbm, CckTxPwrIdx, OfdmTxPwrIdx)); */ for(idx = 0; idx < 14; idx++) { @@ -2238,9 +2182,6 @@ PHY_UpdateTxPowerDbm8188E( pHalData->TxPwrLevelHT40_2S[rf_path][idx] = OfdmTxPwrIdx; } } - - //Adapter->HalFunc.SetTxPowerLevelHandler(Adapter, pHalData->CurrentChannel);//gtest:todo - return true; } @@ -2292,58 +2233,35 @@ _PHY_SetBWMode92C( IN struct adapter *Adapter ) { -// struct adapter * Adapter = (PADAPTER)pTimer->Adapter; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); u8 regBwOpMode; u8 regRRSR_RSC; - //return; - - // Added it for 20/40 mhz switch time evaluation by guangan 070531 - //u32 NowL, NowH; - //u64 BeginTime, EndTime; - - /*RT_TRACE(COMP_SCAN, DBG_LOUD, ("==>PHY_SetBWModeCallback8192C() Switch to %s bandwidth\n", \ - pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"))*/ - if(pHalData->rf_chip == RF_PSEUDO_11N) { - //pHalData->SetBWModeInProgress= false; return; } - // There is no 40MHz mode in RF_8225. + /* There is no 40MHz mode in RF_8225. */ if(pHalData->rf_chip==RF_8225) return; if(Adapter->bDriverStopped) return; - // Added it for 20/40 mhz switch time evaluation by guangan 070531 - //NowL = PlatformEFIORead4Byte(Adapter, TSFR); - //NowH = PlatformEFIORead4Byte(Adapter, TSFR+4); - //BeginTime = ((u64)NowH << 32) + NowL; - - //3// - //3//<1>Set MAC register - //3// - //Adapter->HalFunc.SetBWModeHandler(); - regBwOpMode = rtw_read8(Adapter, REG_BWOPMODE); regRRSR_RSC = rtw_read8(Adapter, REG_RRSR+2); - //regBwOpMode = rtw_hal_get_hwreg(Adapter,HW_VAR_BWMODE,(u8 *)®BwOpMode); - switch(pHalData->CurrentChannelBW) - { + switch(pHalData->CurrentChannelBW) { case HT_CHANNEL_WIDTH_20: regBwOpMode |= BW_OPMODE_20MHZ; - // 2007/02/07 Mark by Emily becasue we have not verify whether this register works + /* 2007/02/07 Mark by Emily becasue we have not verify whether this register works */ rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode); break; case HT_CHANNEL_WIDTH_40: regBwOpMode &= ~BW_OPMODE_20MHZ; - // 2007/02/07 Mark by Emily becasue we have not verify whether this register works + /* 2007/02/07 Mark by Emily becasue we have not verify whether this register works */ rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode); regRRSR_RSC = (regRRSR_RSC&0x90) |(pHalData->nCur40MhzPrimeSC<<5); @@ -2356,16 +2274,16 @@ _PHY_SetBWMode92C( break; } - //3// - //3//<2>Set PHY related register - //3// + /* 3 */ + /* 3<2>Set PHY related register */ + /* 3 */ switch(pHalData->CurrentChannelBW) { /* 20 MHz channel*/ case HT_CHANNEL_WIDTH_20: PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0); PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0); - //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1); + /* PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1); */ break; @@ -2375,10 +2293,10 @@ _PHY_SetBWMode92C( PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1); PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1); - // Set Control channel to upper or lower. These settings are required only for 40MHz + /* Set Control channel to upper or lower. These settings are required only for 40MHz */ PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1)); PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC); - //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 0); + /* PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 0); */ PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC==HAL_PRIME_CHNL_OFFSET_LOWER)?2:1); @@ -2392,33 +2310,33 @@ _PHY_SetBWMode92C( break; } - //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 + /* Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 */ - // Added it for 20/40 mhz switch time evaluation by guangan 070531 - //NowL = PlatformEFIORead4Byte(Adapter, TSFR); - //NowH = PlatformEFIORead4Byte(Adapter, TSFR+4); - //EndTime = ((u64)NowH << 32) + NowL; - //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime))); + /* Added it for 20/40 mhz switch time evaluation by guangan 070531 */ + /* NowL = PlatformEFIORead4Byte(Adapter, TSFR); */ + /* NowH = PlatformEFIORead4Byte(Adapter, TSFR+4); */ + /* EndTime = ((u64)NowH << 32) + NowL; */ + /* RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime))); */ - //3<3>Set RF related register + /* 3<3>Set RF related register */ switch(pHalData->rf_chip) { case RF_8225: - //PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW); + /* PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW); */ break; case RF_8256: - // Please implement this function in Hal8190PciPhy8256.c - //PHY_SetRF8256Bandwidth(Adapter, pHalData->CurrentChannelBW); + /* Please implement this function in Hal8190PciPhy8256.c */ + /* PHY_SetRF8256Bandwidth(Adapter, pHalData->CurrentChannelBW); */ break; case RF_8258: - // Please implement this function in Hal8190PciPhy8258.c - // PHY_SetRF8258Bandwidth(); + /* Please implement this function in Hal8190PciPhy8258.c */ + /* PHY_SetRF8258Bandwidth(); */ break; case RF_PSEUDO_11N: - // Do Nothing + /* Do Nothing */ break; case RF_6052: @@ -2426,13 +2344,13 @@ _PHY_SetBWMode92C( break; default: - //RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID)); + /* RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID)); */ break; } - //pHalData->SetBWModeInProgress= FALSE; + /* pHalData->SetBWModeInProgress= FALSE; */ - //RT_TRACE(COMP_SCAN, DBG_LOUD, ("<==PHY_SetBWModeCallback8192C() \n" )); + /* RT_TRACE(COMP_SCAN, DBG_LOUD, ("<==PHY_SetBWModeCallback8192C() \n" )); */ } @@ -2442,7 +2360,7 @@ _PHY_SetBWMode92C( * Overview: This function is export to "HalCommon" moudule * * Input: struct adapter * Adapter - * HT_CHANNEL_WIDTH Bandwidth //20M or 40M + * HT_CHANNEL_WIDTH Bandwidth 20M or 40M * * Output: NONE * @@ -2453,38 +2371,12 @@ _PHY_SetBWMode92C( void PHY_SetBWMode8188E( IN struct adapter * Adapter, - IN HT_CHANNEL_WIDTH Bandwidth, // 20M or 40M - IN unsigned char Offset // Upper, Lower, or Don't care + IN HT_CHANNEL_WIDTH Bandwidth, /* 20M or 40M */ + IN unsigned char Offset /* Upper, Lower, or Don't care */ ) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); HT_CHANNEL_WIDTH tmpBW= pHalData->CurrentChannelBW; - // Modified it for 20/40 mhz switch by guangan 070531 - //PMGNT_INFO pMgntInfo=&Adapter->MgntInfo; - - //return; - - //if(pHalData->SwChnlInProgress) -// if(pMgntInfo->bScanInProgress) -// { -// RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() %s Exit because bScanInProgress!\n", -// Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")); -// return; -// } - -// if(pHalData->SetBWModeInProgress) -// { -// // Modified it for 20/40 mhz switch by guangan 070531 -// RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() %s cancel last timer because SetBWModeInProgress!\n", -// Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")); -// PlatformCancelTimer(Adapter, &pHalData->SetBWModeTimer); -// //return; -// } - - //if(pHalData->SetBWModeInProgress) - // return; - - //pHalData->SetBWModeInProgress= TRUE; pHalData->CurrentChannelBW = Bandwidth; @@ -2509,10 +2401,10 @@ static void _PHY_SwChnl8192C(struct adapter *Adapter, u8 channel) DBG_871X( "[%s] ch = %d\n", __FUNCTION__, channel ); } - //s1. pre common command - CmdID_SetTxPowerLevel + /* s1. pre common command - CmdID_SetTxPowerLevel */ PHY_SetTxPowerLevel8188E(Adapter, channel); - //s2. RF dependent command - CmdID_RF_WriteReg, param1=RF_CHNLBW, param2=channel + /* s2. RF dependent command - CmdID_RF_WriteReg, param1=RF_CHNLBW, param2=channel */ param1 = RF_CHNLBW; param2 = channel; for(eRFPath = 0; eRFPath NumTotalRFPath; eRFPath++) @@ -2522,81 +2414,81 @@ static void _PHY_SwChnl8192C(struct adapter *Adapter, u8 channel) } - //s3. post common command - CmdID_End, None + /* s3. post common command - CmdID_End, None */ } -// <20130708, James> A workaround to eliminate the 2480MHz spur for 8188E I-Cut +/* <20130708, James> A workaround to eliminate the 2480MHz spur for 8188E I-Cut */ static void phy_SpurCalibration_8188E( IN struct adapter * Adapter ) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - //DbgPrint("===> phy_SpurCalibration_8188E CurrentChannelBW = %d, CurrentChannel = %d\n", pHalData->CurrentChannelBW, pHalData->CurrentChannel); + /* DbgPrint("===> phy_SpurCalibration_8188E CurrentChannelBW = %d, CurrentChannel = %d\n", pHalData->CurrentChannelBW, pHalData->CurrentChannel); */ if(pHalData->CurrentChannelBW == 0 && pHalData->CurrentChannel == 13){ - PHY_SetBBReg(Adapter, rOFDM1_CFOTracking, BIT(28), 0x1); //enable CSI Mask - PHY_SetBBReg(Adapter, rOFDM1_csi_fix_mask, BIT(26)|BIT(25), 0x3); //Fix CSI Mask Tone + PHY_SetBBReg(Adapter, rOFDM1_CFOTracking, BIT(28), 0x1); /* enable CSI Mask */ + PHY_SetBBReg(Adapter, rOFDM1_csi_fix_mask, BIT(26)|BIT(25), 0x3); /* Fix CSI Mask Tone */ } else{ - PHY_SetBBReg(Adapter, rOFDM1_CFOTracking, BIT(28), 0x0); //disable CSI Mask + PHY_SetBBReg(Adapter, rOFDM1_CFOTracking, BIT(28), 0x0); /* disable CSI Mask */ PHY_SetBBReg(Adapter, rOFDM1_csi_fix_mask, BIT(26)|BIT(25), 0x0); } } void -PHY_SwChnl8188E( // Call after initialization +PHY_SwChnl8188E( /* Call after initialization */ IN struct adapter *Adapter, IN u8 channel ) { - //struct adapter *Adapter = ADJUST_TO_ADAPTIVE_ADAPTER(pAdapter, true); + /* struct adapter *Adapter = ADJUST_TO_ADAPTIVE_ADAPTER(pAdapter, true); */ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); u8 tmpchannel = pHalData->CurrentChannel; BOOLEAN bResult = true; if(pHalData->rf_chip == RF_PSEUDO_11N) { - //pHalData->SwChnlInProgress=FALSE; - return; //return immediately if it is peudo-phy + /* pHalData->SwChnlInProgress=FALSE; */ + return; /* return immediately if it is peudo-phy */ } - //if(pHalData->SwChnlInProgress) - // return; + /* if(pHalData->SwChnlInProgress) */ + /* return; */ - //if(pHalData->SetBWModeInProgress) - // return; + /* if(pHalData->SetBWModeInProgress) */ + /* return; */ - //-------------------------------------------- + /* */ switch(pHalData->CurrentWirelessMode) { case WIRELESS_MODE_A: case WIRELESS_MODE_N_5G: - //RT_ASSERT((channel>14), ("WIRELESS_MODE_A but channel<=14")); + /* RT_ASSERT((channel>14), ("WIRELESS_MODE_A but channel<=14")); */ break; case WIRELESS_MODE_B: - //RT_ASSERT((channel<=14), ("WIRELESS_MODE_B but channel>14")); + /* RT_ASSERT((channel<=14), ("WIRELESS_MODE_B but channel>14")); */ break; case WIRELESS_MODE_G: case WIRELESS_MODE_N_24G: - //RT_ASSERT((channel<=14), ("WIRELESS_MODE_G but channel>14")); + /* RT_ASSERT((channel<=14), ("WIRELESS_MODE_G but channel>14")); */ break; default: - //RT_ASSERT(FALSE, ("Invalid WirelessMode(%#x)!!\n", pHalData->CurrentWirelessMode)); + /* RT_ASSERT(FALSE, ("Invalid WirelessMode(%#x)!!\n", pHalData->CurrentWirelessMode)); */ break; } - //-------------------------------------------- + /* */ - //pHalData->SwChnlInProgress = TRUE; + /* pHalData->SwChnlInProgress = TRUE; */ if(channel == 0) channel = 1; pHalData->CurrentChannel=channel; - //pHalData->SwChnlStage=0; - //pHalData->SwChnlStep=0; + /* pHalData->SwChnlStage=0; */ + /* pHalData->SwChnlStep=0; */ if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) { @@ -2605,27 +2497,27 @@ PHY_SwChnl8188E( // Call after initialization phy_SpurCalibration_8188E( Adapter); if(bResult) { - //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress TRUE schdule workitem done\n")); + /* RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress TRUE schdule workitem done\n")); */ } else { - //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE schdule workitem error\n")); - //if(IS_HARDWARE_TYPE_8192SU(Adapter)) - //{ - // pHalData->SwChnlInProgress = FALSE; + /* RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE schdule workitem error\n")); */ + /* if(IS_HARDWARE_TYPE_8192SU(Adapter)) */ + /* */ + /* pHalData->SwChnlInProgress = FALSE; */ pHalData->CurrentChannel = tmpchannel; - //} + /* */ } } else { - //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE driver sleep or unload\n")); - //if(IS_HARDWARE_TYPE_8192SU(Adapter)) - //{ - // pHalData->SwChnlInProgress = FALSE; + /* RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE driver sleep or unload\n")); */ + /* if(IS_HARDWARE_TYPE_8192SU(Adapter)) */ + /* */ + /* pHalData->SwChnlInProgress = FALSE; */ pHalData->CurrentChannel = tmpchannel; - //} + /* */ } } @@ -2658,14 +2550,14 @@ phy_SetSwChnlCmdArray( if(CmdTable == NULL) { - //RT_ASSERT(FALSE, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n")); + /* RT_ASSERT(FALSE, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n")); */ return false; } if(CmdTableIdx >= CmdTableSz) { - //RT_ASSERT(FALSE, - // ("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%ld, CmdTableSz:%ld\n", - // CmdTableIdx, CmdTableSz)); + /* RT_ASSERT(FALSE, */ + /* ("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%ld, CmdTableSz:%ld\n", */ + /* CmdTableIdx, CmdTableSz)); */ return false; } @@ -2680,68 +2572,68 @@ phy_SetSwChnlCmdArray( static void -phy_FinishSwChnlNow( // We should not call this function directly +phy_FinishSwChnlNow( /* We should not call this function directly */ IN struct adapter *Adapter, IN u8 channel ) { } -// -// Description: -// Switch channel synchronously. Called by SwChnlByDelayHandler. -// -// Implemented by Bruce, 2008-02-14. -// The following procedure is operted according to SwChanlCallback8190Pci(). -// However, this procedure is performed synchronously which should be running under -// passive level. -// +/* */ +/* Description: */ +/* Switch channel synchronously. Called by SwChnlByDelayHandler. */ +/* */ +/* Implemented by Bruce, 2008-02-14. */ +/* The following procedure is operted according to SwChanlCallback8190Pci(). */ +/* However, this procedure is performed synchronously which should be running under */ +/* passive level. */ +/* */ void -PHY_SwChnlPhy8192C( // Only called during initialize +PHY_SwChnlPhy8192C( /* Only called during initialize */ IN struct adapter *Adapter, IN u8 channel ) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - //RT_TRACE(COMP_SCAN | COMP_RM, DBG_LOUD, ("==>PHY_SwChnlPhy8192S(), switch from channel %d to channel %d.\n", pHalData->CurrentChannel, channel)); + /* RT_TRACE(COMP_SCAN | COMP_RM, DBG_LOUD, ("==>PHY_SwChnlPhy8192S(), switch from channel %d to channel %d.\n", pHalData->CurrentChannel, channel)); */ - // Cannot IO. - //if(RT_CANNOT_IO(Adapter)) - // return; + /* Cannot IO. */ + /* if(RT_CANNOT_IO(Adapter)) */ + /* return; */ - // Channel Switching is in progress. - //if(pHalData->SwChnlInProgress) - // return; + /* Channel Switching is in progress. */ + /* if(pHalData->SwChnlInProgress) */ + /* return; */ - //return immediately if it is peudo-phy + /* return immediately if it is peudo-phy */ if(pHalData->rf_chip == RF_PSEUDO_11N) { - //pHalData->SwChnlInProgress=FALSE; + /* pHalData->SwChnlInProgress=FALSE; */ return; } - //pHalData->SwChnlInProgress = TRUE; + /* pHalData->SwChnlInProgress = TRUE; */ if( channel == 0) channel = 1; pHalData->CurrentChannel=channel; - //pHalData->SwChnlStage = 0; - //pHalData->SwChnlStep = 0; + /* pHalData->SwChnlStage = 0; */ + /* pHalData->SwChnlStep = 0; */ phy_FinishSwChnlNow(Adapter,channel); - //pHalData->SwChnlInProgress = FALSE; + /* pHalData->SwChnlInProgress = FALSE; */ } -// -// Description: -// Configure H/W functionality to enable/disable Monitor mode. -// Note, because we possibly need to configure BB and RF in this function, -// so caller should in PASSIVE_LEVEL. 080118, by rcnjko. -// +/* */ +/* Description: */ +/* Configure H/W functionality to enable/disable Monitor mode. */ +/* Note, because we possibly need to configure BB and RF in this function, */ +/* so caller should in PASSIVE_LEVEL. 080118, by rcnjko. */ +/* */ void PHY_SetMonitorMode8192C( IN struct adapter * pAdapter, @@ -2775,7 +2667,7 @@ PHY_CheckIsLegalRfPath8192C( { BOOLEAN rtValue = true; - // NOt check RF Path now.! + /* NOt check RF Path now.! */ return rtValue; } /* PHY_CheckIsLegalRfPath8192C */ @@ -2792,37 +2684,37 @@ static void _PHY_SetRFPathSwitch( { u1bTmp = rtw_read8(pAdapter, REG_LEDCFG2) | BIT7; rtw_write8(pAdapter, REG_LEDCFG2, u1bTmp); - //PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01); + /* PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01); */ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01); } if(is2T) { if(bMain) - PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A + PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); /* 92C_Path_A */ else - PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT + PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); /* BT */ } else { if(bMain) - PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x2); //Main + PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x2); /* Main */ else - PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x1); //Aux + PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x1); /* Aux */ } } -//return value TRUE => Main; FALSE => Aux +/* return value TRUE => Main; FALSE => Aux */ static BOOLEAN _PHY_QueryRFPathSwitch( IN struct adapter *pAdapter, IN BOOLEAN is2T ) { -// if(is2T) -// return true; +/* if(is2T) */ +/* return true; */ if(!pAdapter->hw_init_completed) { @@ -2852,26 +2744,26 @@ _PHY_DumpRFReg(IN struct adapter *pAdapter) { u32 rfRegValue,rfRegOffset; - //RTPRINT(FINIT, INIT_RF, ("PHY_DumpRFReg()====>\n")); + /* RTPRINT(FINIT, INIT_RF, ("PHY_DumpRFReg()====>\n")); */ for(rfRegOffset = 0x00;rfRegOffset<=0x30;rfRegOffset++){ rfRegValue = PHY_QueryRFReg(pAdapter,RF_PATH_A, rfRegOffset, bMaskDWord); - //RTPRINT(FINIT, INIT_RF, (" 0x%02x = 0x%08x\n",rfRegOffset,rfRegValue)); + /* RTPRINT(FINIT, INIT_RF, (" 0x%02x = 0x%08x\n",rfRegOffset,rfRegValue)); */ } - //RTPRINT(FINIT, INIT_RF, ("<===== PHY_DumpRFReg()\n")); + /* RTPRINT(FINIT, INIT_RF, ("<===== PHY_DumpRFReg()\n")); */ } -// -// Move from phycfg.c to gen.c to be code independent later -// -//-------------------------Move to other DIR later----------------------------*/ +/* */ +/* Move from phycfg.c to gen.c to be code independent later */ +/* */ +/* Move to other DIR later----------------------------*/ -// -// Description: -// To dump all Tx FIFO LLT related link-list table. -// Added by Roger, 2009.03.10. -// +/* */ +/* Description: */ +/* To dump all Tx FIFO LLT related link-list table. */ +/* Added by Roger, 2009.03.10. */ +/* */ static void DumpBBDbgPort_92CU( IN struct adapter * Adapter ) diff --git a/hal/rtl8188e_rf6052.c b/hal/rtl8188e_rf6052.c index ef5b22c..70fa30c 100755 --- a/hal/rtl8188e_rf6052.c +++ b/hal/rtl8188e_rf6052.c @@ -48,17 +48,17 @@ #include /*---------------------------Define Local Constant---------------------------*/ -// Define local structure for debug!!!!! +/* Define local structure for debug!!!!! */ typedef struct RF_Shadow_Compare_Map { - // Shadow register value + /* Shadow register value */ u32 Value; - // Compare or not flag + /* Compare or not flag */ u8 Compare; - // Record If it had ever modified unpredicted + /* Record If it had ever modified unpredicted */ u8 ErrorOrNot; - // Recorver Flag + /* Recorver Flag */ u8 Recorver; - // + /* */ u8 Driver_Write; }RF_SHADOW_T; /*---------------------------Define Local Constant---------------------------*/ @@ -69,8 +69,8 @@ typedef struct RF_Shadow_Compare_Map { /*------------------------Define local variable------------------------------*/ -// 2008/11/20 MH For Debug only, RF -//static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG] = {0}; +/* 2008/11/20 MH For Debug only, RF */ +/* static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG] = {0}; */ static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG]; /*------------------------Define local variable------------------------------*/ @@ -80,7 +80,7 @@ static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG]; * * Overview: For RL6052, we must change some RF settign for 1T or 2T. * - * Input: u16 DataRate // 0x80-8f, 0x90-9f + * Input: u16 DataRate 0x80-8f, 0x90-9f * * Output: NONE * @@ -95,7 +95,7 @@ static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG]; void rtl8188e_RF_ChangeTxPath( IN struct adapter *Adapter, IN u16 DataRate) { -// We do not support gain table change inACUT now !!!! Delete later !!! +/* We do not support gain table change inACUT now !!!! Delete later !!! */ } /* RF_ChangeTxPath */ @@ -105,7 +105,7 @@ void rtl8188e_RF_ChangeTxPath( IN struct adapter *Adapter, * Overview: This function is called by SetBWModeCallback8190Pci() only * * Input: struct adapter * Adapter - * WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M + * WIRELESS_BANDWIDTH_E Bandwidth 20M or 40M * * Output: NONE * @@ -116,7 +116,7 @@ void rtl8188e_RF_ChangeTxPath( IN struct adapter *Adapter, void rtl8188e_PHY_RF6052SetBandwidth( IN struct adapter * Adapter, - IN HT_CHANNEL_WIDTH Bandwidth) //20M or 40M + IN HT_CHANNEL_WIDTH Bandwidth) /* 20M or 40M */ { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); @@ -133,7 +133,6 @@ rtl8188e_PHY_RF6052SetBandwidth( break; default: - //RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth )); break; } @@ -166,13 +165,11 @@ rtl8188e_PHY_RF6052SetCckTxPower( struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; struct dm_priv *pdmpriv = &pHalData->dmpriv; struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; - //PMGNT_INFO pMgntInfo=&Adapter->MgntInfo; u32 TxAGC[2]={0, 0}, tmpval=0,pwrtrac_value; BOOLEAN TurboScanOff = false; u8 idx1, idx2; u8* ptr; u8 direction; - //FOR CE ,must disable turbo scan TurboScanOff = true; @@ -181,7 +178,7 @@ rtl8188e_PHY_RF6052SetCckTxPower( TxAGC[RF_PATH_A] = 0x3f3f3f3f; TxAGC[RF_PATH_B] = 0x3f3f3f3f; - TurboScanOff = true;//disable turbo scan + TurboScanOff = true;/* disable turbo scan */ if(TurboScanOff) { @@ -190,7 +187,7 @@ rtl8188e_PHY_RF6052SetCckTxPower( TxAGC[idx1] = pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); - // 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20. + /* 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20. */ if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA) TxAGC[idx1] = 0x20; } @@ -198,9 +195,9 @@ rtl8188e_PHY_RF6052SetCckTxPower( } else { -// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. -// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. -// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. +/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */ +/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */ +/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */ if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) { TxAGC[RF_PATH_A] = 0x10101010; @@ -235,16 +232,16 @@ rtl8188e_PHY_RF6052SetCckTxPower( ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 1, &direction, &pwrtrac_value); - //printk("ODM_TxPwrTrackAdjust88E => direction:%02x, pwrtrac_value:%d \n", direction, pwrtrac_value); - //printk(" ==> TxAGC:0x%08x \n",TxAGC[0] ); + /* printk("ODM_TxPwrTrackAdjust88E => direction:%02x, pwrtrac_value:%d \n", direction, pwrtrac_value); */ + /* printk(" ==> TxAGC:0x%08x \n",TxAGC[0] ); */ - if (direction == 1) // Increase TX pwoer + if (direction == 1) /* Increase TX pwoer */ { TxAGC[0] += pwrtrac_value; TxAGC[1] += pwrtrac_value; } - else if (direction == 2) // Decrease TX pwoer + else if (direction == 2) /* Decrease TX pwoer */ { TxAGC[0] -= pwrtrac_value; TxAGC[1] -= pwrtrac_value; @@ -260,31 +257,22 @@ rtl8188e_PHY_RF6052SetCckTxPower( ptr++; } } - //printk(" ==> TxAGC:0x%08x \n",TxAGC[0] ); + /* printk(" ==> TxAGC:0x%08x \n",TxAGC[0] ); */ - // rf-A cck tx power + /* rf-A cck tx power */ tmpval = TxAGC[RF_PATH_A]&0xff; PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); - //printk("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_A_CCK1_Mcs32); + /* printk("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_A_CCK1_Mcs32); */ tmpval = TxAGC[RF_PATH_A]>>8; PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); - //printk("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11); + /* printk("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11); */ -/* - // rf-B cck tx power - tmpval = TxAGC[RF_PATH_B]>>24; - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval); - //printk("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11); - tmpval = TxAGC[RF_PATH_B]&0x00ffffff; - PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval); - //printk("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n",tmpval, rTxAGC_B_CCK1_55_Mcs32); -*/ } /* PHY_RF6052SetCckTxPower */ -// powerbase0 for OFDM rates -// powerbase1 for HT MCS rates +/* powerbase0 for OFDM rates */ +/* powerbase1 for HT MCS rates */ static void getPowerBase88E( IN struct adapter *Adapter, IN u8* pPowerLevelOFDM, @@ -307,12 +295,12 @@ static void getPowerBase88E( powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; *(OfdmBase+i) = powerBase0; - //DBG_871X(" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i)); + /* DBG_871X(" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i)); */ } for(i=0; iNumTotalRFPath; i++) { - //Check HT20 to HT40 diff + /* Check HT20 to HT40 diff */ if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) { powerlevel[i] = pPowerLevelBW20[i]; @@ -324,7 +312,7 @@ static void getPowerBase88E( powerBase1 = powerlevel[i]; powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; *(MCSBase+i) = powerBase1; - //DBG_871X(" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i)); + /* DBG_871X(" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i)); */ } } @@ -345,38 +333,38 @@ static void getTxPowerWriteValByRegulatory88E( u32 writeVal, customer_limit, rf; u8 Regulatory = pHalData->EEPROMRegulatory; - // - // Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate - // + /* */ + /* Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */ + /* */ for(rf=0; rf<2; rf++) { switch(Regulatory) { - case 0: // Realtek better performance - // increase power diff defined by Realtek for large power + case 0: /* Realtek better performance */ + /* increase power diff defined by Realtek for large power */ chnlGroup = 0; - //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", - // chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); + /* RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", */ + /* chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); */ writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + ((index<2)?powerBase0[rf]:powerBase1[rf]); - //RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); + /* RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); */ break; - case 1: // Realtek regulatory - // increase power diff defined by Realtek for regulatory + case 1: /* Realtek regulatory */ + /* increase power diff defined by Realtek for regulatory */ { if(pHalData->pwrGroupCnt == 1) chnlGroup = 0; - //if(pHalData->pwrGroupCnt >= pHalData->PGMaxGroup) + /* if(pHalData->pwrGroupCnt >= pHalData->PGMaxGroup) */ { - if (Channel < 3) // Chanel 1-2 + if (Channel < 3) /* Chanel 1-2 */ chnlGroup = 0; - else if (Channel < 6) // Channel 3-5 + else if (Channel < 6) /* Channel 3-5 */ chnlGroup = 1; - else if(Channel <9) // Channel 6-8 + else if(Channel <9) /* Channel 6-8 */ chnlGroup = 2; - else if(Channel <12) // Channel 9-11 + else if(Channel <12) /* Channel 9-11 */ chnlGroup = 3; - else if(Channel <14) // Channel 12-13 + else if(Channel <14) /* Channel 12-13 */ chnlGroup = 4; - else if(Channel ==14) // Channel 14 + else if(Channel ==14) /* Channel 14 */ chnlGroup = 4; if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) @@ -399,23 +387,23 @@ static void getTxPowerWriteValByRegulatory88E( chnlGroup+=4; */ } - //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", - //chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); + /* RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", */ + /* chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); */ writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + ((index<2)?powerBase0[rf]:powerBase1[rf]); - //RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); + /* RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); */ } break; - case 2: // Better regulatory - // don't increase any power diff + case 2: /* Better regulatory */ + /* don't increase any power diff */ writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]); - //RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); + /* RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); */ break; - case 3: // Customer defined power diff. - // increase power diff defined by customer. + case 3: /* Customer defined power diff. */ + /* increase power diff defined by customer. */ chnlGroup = 0; - //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", - // chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); + /* RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", */ + /* chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); */ /* if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) @@ -434,14 +422,14 @@ static void getTxPowerWriteValByRegulatory88E( else if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) pwr_diff = pHalData->TxPwrHt20Diff[rf][Channel-1]; - //RTPRINT(FPHY, PHY_TXPWR, ("power diff rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), pwr_diff)); + /* RTPRINT(FPHY, PHY_TXPWR, ("power diff rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), pwr_diff)); */ if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40) customer_pwr_limit = pHalData->PwrGroupHT40[rf][Channel-1]; else customer_pwr_limit = pHalData->PwrGroupHT20[rf][Channel-1]; - //RTPRINT(FPHY, PHY_TXPWR, ("customer pwr limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_pwr_limit)); + /* RTPRINT(FPHY, PHY_TXPWR, ("customer pwr limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_pwr_limit)); */ if(pwr_diff >= customer_pwr_limit) pwr_diff = 0; @@ -457,46 +445,39 @@ static void getTxPowerWriteValByRegulatory88E( } customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) | (pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]); - //RTPRINT(FPHY, PHY_TXPWR, ("Customer's limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_limit)); + /* RTPRINT(FPHY, PHY_TXPWR, ("Customer's limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_limit)); */ writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]); - //RTPRINT(FPHY, PHY_TXPWR, ("Customer, writeVal rf(%c)= 0x%x\n", ((rf==0)?'A':'B'), writeVal)); + /* RTPRINT(FPHY, PHY_TXPWR, ("Customer, writeVal rf(%c)= 0x%x\n", ((rf==0)?'A':'B'), writeVal)); */ break; default: chnlGroup = 0; writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + ((index<2)?powerBase0[rf]:powerBase1[rf]); - //RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); + /* RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); */ break; } -// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. -// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. -// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. - //92d do not need this +/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */ +/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */ +/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */ + /* 92d do not need this */ if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) writeVal = 0x14141414; else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) writeVal = 0x00000000; - // 20100628 Joseph: High power mode for BT-Coexist mechanism. - // This mechanism is only applied when Driver-Highpower-Mechanism is OFF. + /* 20100628 Joseph: High power mode for BT-Coexist mechanism. */ + /* This mechanism is only applied when Driver-Highpower-Mechanism is OFF. */ if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1) { - //RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n")); + /* RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n")); */ writeVal = writeVal - 0x06060606; } else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2) { - //RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n")); + /* RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n")); */ writeVal = writeVal ; } - /* - if(pMgntInfo->bDisableTXPowerByRate) - { - // add for OID_RT_11N_TX_POWER_BY_RATE ,disable tx powre change by rate - writeVal = 0x2c2c2c2c; - } - */ *(pOutWriteVal+rf) = writeVal; } } @@ -535,9 +516,9 @@ static void writeOFDMPowerReg88E( RegOffset = RegOffset_B[index]; PHY_SetBBReg(Adapter, RegOffset, bMaskDWord, writeVal); - //printk("Set OFDM tx pwr- 0x%x = %08x\n", RegOffset, writeVal); + /* printk("Set OFDM tx pwr- 0x%x = %08x\n", RegOffset, writeVal); */ - // 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. + /* 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */ if(((pHalData->rf_type == RF_2T2R) && (RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs15_Mcs12))|| ((pHalData->rf_type != RF_2T2R) && @@ -598,14 +579,14 @@ rtl8188e_PHY_RF6052SetOFDMTxPower( u8 index = 0; - //DBG_871X("PHY_RF6052SetOFDMTxPower, channel(%d) \n", Channel); + /* DBG_871X("PHY_RF6052SetOFDMTxPower, channel(%d) \n", Channel); */ getPowerBase88E(Adapter, pPowerLevelOFDM,pPowerLevelBW20,pPowerLevelBW40, Channel, &powerBase0[0], &powerBase1[0]); - // - // 2012/04/23 MH According to power tracking value, we need to revise OFDM tx power. - // This is ued to fix unstable power tracking mode. - // + /* */ + /* 2012/04/23 MH According to power tracking value, we need to revise OFDM tx power. */ + /* This is ued to fix unstable power tracking mode. */ + /* */ ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 0, &direction, &pwrtrac_value); for(index=0; index<6; index++) @@ -635,10 +616,10 @@ phy_RF6052_Config_HardCode( ) { - // Set Default Bandwidth to 20M - //Adapter->HalFunc .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20); + /* Set Default Bandwidth to 20M */ + /* Adapter->HalFunc .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20); */ - // TODO: Set Default Channel to channel one for RTL8225 + /* TODO: Set Default Channel to channel one for RTL8225 */ } @@ -664,10 +645,10 @@ phy_RF6052_Config_ParaFile( pszRadioBFile = sz88eRadioBFile; - //3//----------------------------------------------------------------- - //3// <2> Initialize RF - //3//----------------------------------------------------------------- - //for(eRFPath = RF_PATH_A; eRFPath NumTotalRFPath; eRFPath++) + /* 3----------------------------------------------------------------- */ + /* 3 <2> Initialize RF */ + /* 3----------------------------------------------------------------- */ + /* for(eRFPath = RF_PATH_A; eRFPath NumTotalRFPath; eRFPath++) */ for(eRFPath = 0; eRFPath NumTotalRFPath; eRFPath++) { @@ -688,18 +669,18 @@ phy_RF6052_Config_ParaFile( /*----Set RF_ENV enable----*/ PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); - rtw_udelay_os(1);//PlatformStallExecution(1); + rtw_udelay_os(1);/* PlatformStallExecution(1); */ /*----Set RF_ENV output high----*/ PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); - rtw_udelay_os(1);//PlatformStallExecution(1); + rtw_udelay_os(1);/* PlatformStallExecution(1); */ /* Set bit number of Address and Data for RF register */ - PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255 - rtw_udelay_os(1);//PlatformStallExecution(1); + PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */ + rtw_udelay_os(1);/* PlatformStallExecution(1); */ - PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255 - rtw_udelay_os(1);//PlatformStallExecution(1); + PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */ + rtw_udelay_os(1);/* PlatformStallExecution(1); */ /*----Initialize RF fom connfiguration file----*/ switch(eRFPath) @@ -711,10 +692,10 @@ phy_RF6052_Config_ParaFile( rtStatus= _FAIL; #else rtStatus= rtl8188e_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath); - #endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM + #endif/* ifdef CONFIG_PHY_SETTING_WITH_ODM */ #else rtStatus = rtl8188e_PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF_RADIO_PATH_E)eRFPath); -#endif//#ifdef CONFIG_EMBEDDED_FWIMG +#endif/* ifdef CONFIG_EMBEDDED_FWIMG */ break; case RF_PATH_B: #ifdef CONFIG_EMBEDDED_FWIMG @@ -723,7 +704,7 @@ phy_RF6052_Config_ParaFile( rtStatus= _FAIL; #else rtStatus = rtl8188e_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath); - #endif //#ifdef CONFIG_PHY_SETTING_WITH_ODM + #endif /* ifdef CONFIG_PHY_SETTING_WITH_ODM */ #else rtStatus =rtl8188e_PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF_RADIO_PATH_E)eRFPath); #endif @@ -748,13 +729,13 @@ phy_RF6052_Config_ParaFile( } if(rtStatus != _SUCCESS){ - //RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); + /* RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); */ goto phy_RF6052_Config_ParaFile_Fail; } } - //RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n")); + /* RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n")); */ return rtStatus; phy_RF6052_Config_ParaFile_Fail: @@ -769,26 +750,26 @@ PHY_RF6052_Config8188E( HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); int rtStatus = _SUCCESS; - // - // Initialize general global value - // - // TODO: Extend RF_PATH_C and RF_PATH_D in the future + /* */ + /* Initialize general global value */ + /* */ + /* TODO: Extend RF_PATH_C and RF_PATH_D in the future */ if(pHalData->rf_type == RF_1T1R) pHalData->NumTotalRFPath = 1; else pHalData->NumTotalRFPath = 2; - // - // Config BB and RF - // + /* */ + /* Config BB and RF */ + /* */ rtStatus = phy_RF6052_Config_ParaFile(Adapter); return rtStatus; } -// -// ==> RF shadow Operation API Code Section!!! -// +/* */ +/* ==> RF shadow Operation API Code Section!!! */ +/* */ /*----------------------------------------------------------------------------- * Function: PHY_RFShadowRead * PHY_RFShadowWrite @@ -845,18 +826,18 @@ PHY_RFShadowCompare( IN u32 Offset) { u32 reg; - // Check if we need to check the register + /* Check if we need to check the register */ if (RF_Shadow[eRFPath][Offset].Compare == true) { reg = PHY_QueryRFReg(Adapter, eRFPath, Offset, bRFRegOffsetMask); - // Compare shadow and real rf register for 20bits!! + /* Compare shadow and real rf register for 20bits!! */ if (RF_Shadow[eRFPath][Offset].Value != reg) { - // Locate error position. + /* Locate error position. */ RF_Shadow[eRFPath][Offset].ErrorOrNot = true; - //RT_TRACE(COMP_INIT, DBG_LOUD, - //("PHY_RFShadowCompare RF-%d Addr%02lx Err = %05lx\n", - //eRFPath, Offset, reg)); + /* RT_TRACE(COMP_INIT, DBG_LOUD, */ + /* PHY_RFShadowCompare RF-%d Addr%02lx Err = %05lx\n", */ + /* eRFPath, Offset, reg)); */ } return RF_Shadow[eRFPath][Offset].ErrorOrNot ; } @@ -870,17 +851,17 @@ PHY_RFShadowRecorver( IN RF_RADIO_PATH_E eRFPath, IN u32 Offset) { - // Check if the address is error + /* Check if the address is error */ if (RF_Shadow[eRFPath][Offset].ErrorOrNot == true) { - // Check if we need to recorver the register. + /* Check if we need to recorver the register. */ if (RF_Shadow[eRFPath][Offset].Recorver == true) { PHY_SetRFReg(Adapter, eRFPath, Offset, bRFRegOffsetMask, RF_Shadow[eRFPath][Offset].Value); - //RT_TRACE(COMP_INIT, DBG_LOUD, - //("PHY_RFShadowRecorver RF-%d Addr%02lx=%05lx", - //eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value)); + /* RT_TRACE(COMP_INIT, DBG_LOUD, */ + /* PHY_RFShadowRecorver RF-%d Addr%02lx=%05lx", */ + /* eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value)); */ } } @@ -930,7 +911,7 @@ PHY_RFShadowCompareFlagSet( IN u32 Offset, IN u8 Type) { - // Set True or False!!! + /* Set True or False!!! */ RF_Shadow[eRFPath][Offset].Compare = Type; } /* PHY_RFShadowCompareFlagSet */ @@ -943,7 +924,7 @@ PHY_RFShadowRecorverFlagSet( IN u32 Offset, IN u8 Type) { - // Set True or False!!! + /* Set True or False!!! */ RF_Shadow[eRFPath][Offset].Recorver= Type; } /* PHY_RFShadowRecorverFlagSet */ @@ -960,7 +941,7 @@ PHY_RFShadowCompareFlagSetAll( { for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) { - // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! + /* 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! */ if (Offset != 0x26 && Offset != 0x27) PHY_RFShadowCompareFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, false); else @@ -982,7 +963,7 @@ PHY_RFShadowRecorverFlagSetAll( { for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) { - // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! + /* 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! */ if (Offset != 0x26 && Offset != 0x27) PHY_RFShadowRecorverFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, false); else diff --git a/hal/rtl8188e_rxdesc.c b/hal/rtl8188e_rxdesc.c index 975da54..c9258a8 100755 --- a/hal/rtl8188e_rxdesc.c +++ b/hal/rtl8188e_rxdesc.c @@ -26,10 +26,10 @@ static s32 translate2dbm(u8 signal_strength_idx) { - s32 signal_power; // in dBm. + s32 signal_power; /* in dBm. */ - // Translate to dBm (x=0.5y-95). + /* Translate to dBm (x=0.5y-95). */ signal_power = (s32)((signal_strength_idx + 1) >> 1); signal_power -= 95; @@ -43,10 +43,10 @@ static void process_rssi(struct adapter *padapter,union recv_frame *prframe) struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS struct signal_stat * signal_stat = &padapter->recvpriv.signal_strength_data; -#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS +#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ - //DBG_8192C("process_rssi=> pattrib->rssil(%d) signal_strength(%d)\n ",pattrib->RecvSignalPower,pattrib->signal_strength); - //if(pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon) + /* DBG_8192C("process_rssi=> pattrib->rssil(%d) signal_strength(%d)\n ",pattrib->RecvSignalPower,pattrib->signal_strength); */ + /* if(pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon) */ { #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS @@ -59,9 +59,8 @@ static void process_rssi(struct adapter *padapter,union recv_frame *prframe) signal_stat->total_num++; signal_stat->total_val += pattrib->phy_info.SignalStrength; signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num; - #else //CONFIG_NEW_SIGNAL_STAT_PROCESS + #else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ - //Adapter->RxStats.RssiCalculateCnt++; //For antenna Test if(padapter->recvpriv.signal_strength_data.total_num++ >= PHY_RSSI_SLID_WIN_MAX) { padapter->recvpriv.signal_strength_data.total_num = PHY_RSSI_SLID_WIN_MAX; @@ -86,10 +85,10 @@ static void process_rssi(struct adapter *padapter,union recv_frame *prframe) } RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("UI RSSI = %d, ui_rssi.TotalVal = %d, ui_rssi.TotalNum = %d\n", tmp_val, padapter->recvpriv.signal_strength_data.total_val,padapter->recvpriv.signal_strength_data.total_num)); - #endif //CONFIG_NEW_SIGNAL_STAT_PROCESS + #endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ } -}// Process_UI_RSSI_8192C +}/* Process_UI_RSSI_8192C */ @@ -99,7 +98,7 @@ static void process_link_qual(struct adapter *padapter,union recv_frame *prframe struct rx_pkt_attrib *pattrib; #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS struct signal_stat * signal_stat; -#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS +#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ if(prframe == NULL || padapter==NULL){ return; @@ -108,9 +107,9 @@ static void process_link_qual(struct adapter *padapter,union recv_frame *prframe pattrib = &prframe->u.hdr.attrib; #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS signal_stat = &padapter->recvpriv.signal_qual_data; -#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS +#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ - //DBG_8192C("process_link_qual=> pattrib->signal_qual(%d)\n ",pattrib->signal_qual); + /* DBG_8192C("process_link_qual=> pattrib->signal_qual(%d)\n ",pattrib->signal_qual); */ #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS if(signal_stat->update_req) { @@ -123,12 +122,12 @@ static void process_link_qual(struct adapter *padapter,union recv_frame *prframe signal_stat->total_val += pattrib->phy_info.SignalQuality; signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num; -#else //CONFIG_NEW_SIGNAL_STAT_PROCESS +#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ if(pattrib->phy_info.SignalQuality != 0) { - // - // 1. Record the general EVM to the sliding window. - // + /* */ + /* 1. Record the general EVM to the sliding window. */ + /* */ if(padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX) { padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX; @@ -143,7 +142,7 @@ static void process_link_qual(struct adapter *padapter,union recv_frame *prframe RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("Total SQ=%d pattrib->signal_qual= %d\n", padapter->recvpriv.signal_qual_data.total_val, pattrib->phy_info.SignalQuality)); - // <1> Showed on UI for user, in percentage. + /* <1> Showed on UI for user, in percentage. */ tmpVal = padapter->recvpriv.signal_qual_data.total_val/padapter->recvpriv.signal_qual_data.total_num; padapter->recvpriv.signal_qual=(u8)tmpVal; @@ -152,28 +151,28 @@ static void process_link_qual(struct adapter *padapter,union recv_frame *prframe { RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" pattrib->signal_qual =%d\n", pattrib->phy_info.SignalQuality)); } -#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS +#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ } -//void rtl8188e_process_phy_info(struct adapter *padapter, union recv_frame *prframe) +/* void rtl8188e_process_phy_info(struct adapter *padapter, union recv_frame *prframe) */ void rtl8188e_process_phy_info(struct adapter *padapter, void *prframe) { union recv_frame *precvframe = (union recv_frame *)prframe; - // - // Check RSSI - // + /* */ + /* Check RSSI */ + /* */ process_rssi(padapter, precvframe); - // - // Check PWDB. - // - //process_PWDB(padapter, precvframe); + /* */ + /* Check PWDB. */ + /* */ + /* process_PWDB(padapter, precvframe); */ - //UpdateRxSignalStatistics8192C(Adapter, pRfd); - // - // Check EVM - // + /* UpdateRxSignalStatistics8192C(Adapter, pRfd); */ + /* */ + /* Check EVM */ + /* */ process_link_qual(padapter, precvframe); } @@ -186,9 +185,9 @@ void update_recvframe_attrib_88e( struct rx_pkt_attrib *pattrib; struct recv_stat report; PRXREPORT prxreport; - //struct recv_frame_hdr *phdr; + /* struct recv_frame_hdr *phdr; */ - //phdr = &precvframe->u.hdr; + /* phdr = &precvframe->u.hdr; */ report.rxdw0 = prxstat->rxdw0; report.rxdw1 = prxstat->rxdw1; @@ -202,54 +201,54 @@ void update_recvframe_attrib_88e( pattrib = &precvframe->u.hdr.attrib; memset(pattrib, 0, sizeof(struct rx_pkt_attrib)); - pattrib->crc_err = (u8)((le32_to_cpu(report.rxdw0) >> 14) & 0x1);;//(u8)prxreport->crc32; + pattrib->crc_err = (u8)((le32_to_cpu(report.rxdw0) >> 14) & 0x1);;/* u8)prxreport->crc32; */ - // update rx report to recv_frame attribute - pattrib->pkt_rpt_type = (u8)((le32_to_cpu(report.rxdw3) >> 14) & 0x3);//prxreport->rpt_sel; + /* update rx report to recv_frame attribute */ + pattrib->pkt_rpt_type = (u8)((le32_to_cpu(report.rxdw3) >> 14) & 0x3);/* prxreport->rpt_sel; */ - if(pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet + if(pattrib->pkt_rpt_type == NORMAL_RX)/* Normal rx packet */ { - pattrib->pkt_len = (u16)(le32_to_cpu(report.rxdw0) &0x00003fff);//(u16)prxreport->pktlen; - pattrib->drvinfo_sz = (u8)((le32_to_cpu(report.rxdw0) >> 16) & 0xf) * 8;//(u8)(prxreport->drvinfosize << 3); + pattrib->pkt_len = (u16)(le32_to_cpu(report.rxdw0) &0x00003fff);/* u16)prxreport->pktlen; */ + pattrib->drvinfo_sz = (u8)((le32_to_cpu(report.rxdw0) >> 16) & 0xf) * 8;/* u8)(prxreport->drvinfosize << 3); */ - pattrib->physt = (u8)((le32_to_cpu(report.rxdw0) >> 26) & 0x1);//(u8)prxreport->physt; + pattrib->physt = (u8)((le32_to_cpu(report.rxdw0) >> 26) & 0x1);/* u8)prxreport->physt; */ - pattrib->bdecrypted = (le32_to_cpu(report.rxdw0) & BIT(27))? 0:1;//(u8)(prxreport->swdec ? 0 : 1); - pattrib->encrypt = (u8)((le32_to_cpu(report.rxdw0) >> 20) & 0x7);//(u8)prxreport->security; + pattrib->bdecrypted = (le32_to_cpu(report.rxdw0) & BIT(27))? 0:1;/* u8)(prxreport->swdec ? 0 : 1); */ + pattrib->encrypt = (u8)((le32_to_cpu(report.rxdw0) >> 20) & 0x7);/* u8)prxreport->security; */ - pattrib->qos = (u8)((le32_to_cpu(report.rxdw0) >> 23) & 0x1);//(u8)prxreport->qos; - pattrib->priority = (u8)((le32_to_cpu(report.rxdw1) >> 8) & 0xf);//(u8)prxreport->tid; + pattrib->qos = (u8)((le32_to_cpu(report.rxdw0) >> 23) & 0x1);/* u8)prxreport->qos; */ + pattrib->priority = (u8)((le32_to_cpu(report.rxdw1) >> 8) & 0xf);/* u8)prxreport->tid; */ - pattrib->amsdu = (u8)((le32_to_cpu(report.rxdw1) >> 13) & 0x1);//(u8)prxreport->amsdu; + pattrib->amsdu = (u8)((le32_to_cpu(report.rxdw1) >> 13) & 0x1);/* u8)prxreport->amsdu; */ - pattrib->seq_num = (u16)(le32_to_cpu(report.rxdw2) & 0x00000fff);//(u16)prxreport->seq; - pattrib->frag_num = (u8)((le32_to_cpu(report.rxdw2) >> 12) & 0xf);//(u8)prxreport->frag; - pattrib->mfrag = (u8)((le32_to_cpu(report.rxdw1) >> 27) & 0x1);//(u8)prxreport->mf; - pattrib->mdata = (u8)((le32_to_cpu(report.rxdw1) >> 26) & 0x1);//(u8)prxreport->md; + pattrib->seq_num = (u16)(le32_to_cpu(report.rxdw2) & 0x00000fff);/* u16)prxreport->seq; */ + pattrib->frag_num = (u8)((le32_to_cpu(report.rxdw2) >> 12) & 0xf);/* u8)prxreport->frag; */ + pattrib->mfrag = (u8)((le32_to_cpu(report.rxdw1) >> 27) & 0x1);/* u8)prxreport->mf; */ + pattrib->mdata = (u8)((le32_to_cpu(report.rxdw1) >> 26) & 0x1);/* u8)prxreport->md; */ - pattrib->mcs_rate = (u8)(le32_to_cpu(report.rxdw3) & 0x3f);//(u8)prxreport->rxmcs; - pattrib->rxht = (u8)((le32_to_cpu(report.rxdw3) >> 6) & 0x1);//(u8)prxreport->rxht; + pattrib->mcs_rate = (u8)(le32_to_cpu(report.rxdw3) & 0x3f);/* u8)prxreport->rxmcs; */ + pattrib->rxht = (u8)((le32_to_cpu(report.rxdw3) >> 6) & 0x1);/* u8)prxreport->rxht; */ - pattrib->icv_err = (u8)((le32_to_cpu(report.rxdw0) >> 15) & 0x1);//(u8)prxreport->icverr; + pattrib->icv_err = (u8)((le32_to_cpu(report.rxdw0) >> 15) & 0x1);/* u8)prxreport->icverr; */ pattrib->shift_sz = (u8)((le32_to_cpu(report.rxdw0) >> 24) & 0x3); - } else if(pattrib->pkt_rpt_type == TX_REPORT1) {//CCX + } else if(pattrib->pkt_rpt_type == TX_REPORT1) {/* CCX */ pattrib->pkt_len = TX_RPT1_PKT_LEN; pattrib->drvinfo_sz = 0; - } else if(pattrib->pkt_rpt_type == TX_REPORT2) { // TX RPT - pattrib->pkt_len =(u16)(le32_to_cpu(report.rxdw0) & 0x3FF);//Rx length[9:0] + } else if(pattrib->pkt_rpt_type == TX_REPORT2) { /* TX RPT */ + pattrib->pkt_len =(u16)(le32_to_cpu(report.rxdw0) & 0x3FF);/* Rx length[9:0] */ pattrib->drvinfo_sz = 0; - // - // Get TX report MAC ID valid. - // + /* */ + /* Get TX report MAC ID valid. */ + /* */ pattrib->MacIDValidEntry[0] = le32_to_cpu(report.rxdw4); pattrib->MacIDValidEntry[1] = le32_to_cpu(report.rxdw5); } - else if(pattrib->pkt_rpt_type == HIS_REPORT)// USB HISR RPT + else if(pattrib->pkt_rpt_type == HIS_REPORT)/* USB HISR RPT */ { - pattrib->pkt_len = (u16)(le32_to_cpu(report.rxdw0) &0x00003fff);//(u16)prxreport->pktlen; + pattrib->pkt_len = (u16)(le32_to_cpu(report.rxdw0) &0x00003fff);/* u16)prxreport->pktlen; */ } } @@ -272,7 +271,7 @@ void update_recvframe_phyinfo_88e( u8 *sa; struct sta_priv *pstapriv; struct sta_info *psta; - //_irqL irqL; + /* _irqL irqL; */ pkt_info.bPacketMatchBSSID =false; pkt_info.bPacketToSelf = false; @@ -302,16 +301,10 @@ void update_recvframe_phyinfo_88e( pkt_info.StationID = 0xFF; psta = rtw_get_stainfo(pstapriv, sa); if (psta) - { pkt_info.StationID = psta->mac_id; - //DBG_8192C("%s ==> StationID(%d)\n",__FUNCTION__,pkt_info.StationID); - } pkt_info.Rate = pattrib->mcs_rate; - //rtl8188e_query_rx_phy_status(precvframe, pphy_status); - //_enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); ODM_PhyStatusQuery(&pHalData->odmpriv,pPHYInfo,(u8 *)pphy_status,&(pkt_info)); - //_exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); precvframe->u.hdr.psta = NULL; if (pkt_info.bPacketMatchBSSID && diff --git a/hal/rtl8188e_sreset.c b/hal/rtl8188e_sreset.c index f648b0a..3899236 100755 --- a/hal/rtl8188e_sreset.c +++ b/hal/rtl8188e_sreset.c @@ -38,9 +38,9 @@ void rtl8188e_sreset_xmit_status_check(struct adapter *padapter) DBG_871X("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status); rtw_hal_sreset_reset(padapter); } - //total xmit irp = 4 - //DBG_8192C("==>%s free_xmitbuf_cnt(%d),txirp_cnt(%d)\n",__FUNCTION__,pxmitpriv->free_xmitbuf_cnt,pxmitpriv->txirp_cnt); - //if(pxmitpriv->txirp_cnt == NR_XMITBUFF+1) + /* total xmit irp = 4 */ + /* DBG_8192C("==>%s free_xmitbuf_cnt(%d),txirp_cnt(%d)\n",__FUNCTION__,pxmitpriv->free_xmitbuf_cnt,pxmitpriv->txirp_cnt); */ + /* if(pxmitpriv->txirp_cnt == NR_XMITBUFF+1) */ current_time = rtw_get_current_time(); if(0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) { @@ -56,7 +56,7 @@ void rtl8188e_sreset_xmit_status_check(struct adapter *padapter) if (diff_time > 4000) { u32 ability; - //padapter->Wifi_Error_Status = WIFI_TX_HANG; + /* padapter->Wifi_Error_Status = WIFI_TX_HANG; */ rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DM_FUNC, &ability); DBG_871X("%s tx hang %s\n", __FUNCTION__, diff --git a/hal/rtl8188e_xmit.c b/hal/rtl8188e_xmit.c index f9bd078..985f0b7 100755 --- a/hal/rtl8188e_xmit.c +++ b/hal/rtl8188e_xmit.c @@ -61,7 +61,7 @@ void handle_txrpt_ccx_88e(struct adapter *adapter, u8 *buf) rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL); } } -#endif //CONFIG_XMIT_ACK +#endif /* CONFIG_XMIT_ACK */ void _dbg_dump_tx_info(struct adapter *padapter,int frame_tag,struct tx_desc *ptxdesc) { @@ -69,24 +69,22 @@ void _dbg_dump_tx_info(struct adapter *padapter,int frame_tag,struct tx_desc *pt u8 bDumpTxDesc = false; rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DUMP_TXPKT, &(bDumpTxPkt)); - if(bDumpTxPkt ==1){//dump txdesc for data frame + if(bDumpTxPkt ==1){/* dump txdesc for data frame */ DBG_871X("dump tx_desc for data frame\n"); if((frame_tag&0x0f) == DATA_FRAMETAG){ bDumpTxDesc = true; } } - else if(bDumpTxPkt ==2){//dump txdesc for mgnt frame + else if(bDumpTxPkt ==2){/* dump txdesc for mgnt frame */ DBG_871X("dump tx_desc for mgnt frame\n"); if((frame_tag&0x0f) == MGNT_FRAMETAG){ bDumpTxDesc = true; } } - else if(bDumpTxPkt ==3){//dump early info + else if(bDumpTxPkt ==3){/* dump early info */ } if(bDumpTxDesc){ - // ptxdesc->txdw4 = cpu_to_le32(0x00001006);//RTS Rate=24M - // ptxdesc->txdw6 = 0x6666f800; DBG_8192C("=====================================\n"); DBG_8192C("txdw0(0x%08x)\n",ptxdesc->txdw0); DBG_8192C("txdw1(0x%08x)\n",ptxdesc->txdw1); @@ -112,7 +110,7 @@ void _dbg_dump_tx_info(struct adapter *padapter,int frame_tag,struct tx_desc *pt */ #ifdef CONFIG_TX_EARLY_MODE -//#define DBG_EMINFO +/* define DBG_EMINFO */ #if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1 #define EARLY_MODE_MAX_PKT_NUM 10 @@ -206,7 +204,7 @@ InsertEMContent_8188E( SET_EARLYMODE_LEN3(VirtualAddress, pEMInfo->EMPktLen[3]); SET_EARLYMODE_LEN4(VirtualAddress, pEMInfo->EMPktLen[4]); #endif - //RT_PRINT_DATA(COMP_SEND, DBG_LOUD, "EMHdr:", VirtualAddress, 8); + /* RT_PRINT_DATA(COMP_SEND, DBG_LOUD, "EMHdr:", VirtualAddress, 8); */ } @@ -214,7 +212,7 @@ InsertEMContent_8188E( void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmitbuf ) { - //struct adapter *padapter, struct xmit_frame *pxmitframe,struct tx_servq *ptxservq + /* struct adapter *padapter, struct xmit_frame *pxmitframe,struct tx_servq *ptxservq */ int index,j; u16 offset,pktlen; PTXDESC ptxdesc; @@ -262,7 +260,7 @@ void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmit eminfo.EMPktNum = pframe->agg_num-(index+1); } for(j=0;j< eminfo.EMPktNum ;j++){ - eminfo.EMPktLen[j] = pxmitpriv->agg_pkt[index+1+j].pkt_len+4;// 4 bytes CRC + eminfo.EMPktLen[j] = pxmitpriv->agg_pkt[index+1+j].pkt_len+4;/* 4 bytes CRC */ } if(pmem){ diff --git a/hal/rtl8188eu_led.c b/hal/rtl8188eu_led.c index 8c12b93..56f8c6b 100755 --- a/hal/rtl8188eu_led.c +++ b/hal/rtl8188eu_led.c @@ -25,24 +25,24 @@ #include #include -//================================================================================ -// LED object. -//================================================================================ +/* */ +/* LED object. */ +/* */ -//================================================================================ -// Prototype of protected function. -//================================================================================ +/* */ +/* Prototype of protected function. */ +/* */ -//================================================================================ -// LED_819xUsb routines. -//================================================================================ +/* */ +/* LED_819xUsb routines. */ +/* */ -// -// Description: -// Turn on LED according to LedPin specified. -// +/* */ +/* Description: */ +/* Turn on LED according to LedPin specified. */ +/* */ void SwLedOn( struct adapter *padapter, @@ -50,7 +50,7 @@ SwLedOn( ) { u8 LedCfg; - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + /* HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); */ if( (padapter->bSurpriseRemoved == true) || ( padapter->bDriverStopped == true)) { @@ -61,11 +61,11 @@ SwLedOn( switch(pLed->LedPin) { case LED_PIN_LED0: - rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0xf0)|BIT5|BIT6); // SW control led0 on. + rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0xf0)|BIT5|BIT6); /* SW control led0 on. */ break; case LED_PIN_LED1: - rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0x0f)|BIT5); // SW control led1 on. + rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0x0f)|BIT5); /* SW control led1 on. */ break; default: @@ -76,10 +76,10 @@ SwLedOn( } -// -// Description: -// Turn off LED according to LedPin specified. -// +/* */ +/* Description: */ +/* Turn off LED according to LedPin specified. */ +/* */ void SwLedOff( struct adapter *padapter, @@ -95,14 +95,14 @@ SwLedOff( } - LedCfg = rtw_read8(padapter, REG_LEDCFG2);//0x4E + LedCfg = rtw_read8(padapter, REG_LEDCFG2);/* 0x4E */ switch(pLed->LedPin) { case LED_PIN_LED0: - if(pHalData->bLedOpenDrain == true) // Open-drain arrangement for controlling the LED) + if(pHalData->bLedOpenDrain == true) /* Open-drain arrangement for controlling the LED) */ { - LedCfg &= 0x90; // Set to software control. + LedCfg &= 0x90; /* Set to software control. */ rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3)); LedCfg = rtw_read8(padapter, REG_MAC_PINMUX_CFG); LedCfg &= 0xFE; @@ -115,7 +115,7 @@ SwLedOff( break; case LED_PIN_LED1: - LedCfg &= 0x0f; // Set to software control. + LedCfg &= 0x0f; /* Set to software control. */ rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3)); break; @@ -127,19 +127,19 @@ exit: } -//================================================================================ -// Interface to manipulate LED objects. -//================================================================================ +/* */ +/* Interface to manipulate LED objects. */ +/* */ -//================================================================================ -// Default LED behavior. -//================================================================================ +/* */ +/* Default LED behavior. */ +/* */ -// -// Description: -// Initialize all LED_871x objects. -// +/* */ +/* Description: */ +/* Initialize all LED_871x objects. */ +/* */ void rtl8188eu_InitSwLeds( struct adapter *padapter @@ -155,10 +155,10 @@ rtl8188eu_InitSwLeds( } -// -// Description: -// DeInitialize all LED_819xUsb objects. -// +/* */ +/* Description: */ +/* DeInitialize all LED_819xUsb objects. */ +/* */ void rtl8188eu_DeInitSwLeds( struct adapter *padapter diff --git a/hal/rtl8188eu_recv.c b/hal/rtl8188eu_recv.c index e31a489..ed7ce74 100755 --- a/hal/rtl8188eu_recv.c +++ b/hal/rtl8188eu_recv.c @@ -59,8 +59,8 @@ int rtl8188eu_init_recv_priv(struct adapter *padapter) struct recv_buf *precvbuf; #ifdef CONFIG_RECV_THREAD_MODE - _rtw_init_sema(&precvpriv->recv_sema, 0);//will be removed - _rtw_init_sema(&precvpriv->terminate_recvthread_sema, 0);//will be removed + _rtw_init_sema(&precvpriv->recv_sema, 0);/* will be removed */ + _rtw_init_sema(&precvpriv->terminate_recvthread_sema, 0);/* will be removed */ #endif tasklet_init(&precvpriv->recv_tasklet, @@ -82,12 +82,12 @@ int rtl8188eu_init_recv_priv(struct adapter *padapter) } #endif - //init recv_buf + /* init recv_buf */ _rtw_init_queue(&precvpriv->free_recv_buf_queue); #ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX _rtw_init_queue(&precvpriv->recv_buf_pending_queue); -#endif // CONFIG_USE_USB_BUFFER_ALLOC_RX +#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */ precvpriv->pallocated_recv_buf = rtw_zmalloc(NR_RECVBUFF *sizeof(struct recv_buf) + 4); if(precvpriv->pallocated_recv_buf==NULL){ @@ -98,8 +98,8 @@ int rtl8188eu_init_recv_priv(struct adapter *padapter) memset(precvpriv->pallocated_recv_buf, 0, NR_RECVBUFF *sizeof(struct recv_buf) + 4); precvpriv->precv_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_recv_buf), 4); - //precvpriv->precv_buf = precvpriv->pallocated_recv_buf + 4 - - // ((uint) (precvpriv->pallocated_recv_buf) &(4-1)); + /* precvpriv->precv_buf = precvpriv->pallocated_recv_buf + 4 - */ + /* ((uint) (precvpriv->pallocated_recv_buf) &(4-1)); */ precvbuf = (struct recv_buf*)precvpriv->precv_buf; @@ -120,7 +120,7 @@ int rtl8188eu_init_recv_priv(struct adapter *padapter) precvbuf->adapter =padapter; - //rtw_list_insert_tail(&precvbuf->list, &(precvpriv->free_recv_buf_queue.queue)); + /* rtw_list_insert_tail(&precvbuf->list, &(precvpriv->free_recv_buf_queue.queue)); */ precvbuf++; @@ -189,7 +189,7 @@ void rtl8188eu_free_recv_priv (struct adapter *padapter) if(precvpriv->int_in_buf) rtw_mfree(precvpriv->int_in_buf, INTERRUPT_MSG_FORMAT_LEN); -#endif//CONFIG_USB_INTERRUPT_IN_PIPE +#endif/* CONFIG_USB_INTERRUPT_IN_PIPE */ if (skb_queue_len(&precvpriv->rx_skb_queue)) { DBG_8192C(KERN_WARNING "rx_skb_queue not empty\n"); diff --git a/hal/rtl8188eu_xmit.c b/hal/rtl8188eu_xmit.c index 3572d27..ef80af1 100755 --- a/hal/rtl8188eu_xmit.c +++ b/hal/rtl8188eu_xmit.c @@ -58,11 +58,11 @@ static u8 urb_zero_packet_chk(struct adapter *padapter, int sz) static void rtl8188eu_cal_txdesc_chksum(struct tx_desc *ptxdesc) { u16 *usPtr = (u16*)ptxdesc; - u32 count = 16; // (32 bytes / 2 bytes per XOR) => 16 times + u32 count = 16; /* (32 bytes / 2 bytes per XOR) => 16 times */ u32 index; u16 checksum = 0; - //Clear first + /* Clear first */ ptxdesc->txdw7 &= cpu_to_le32(0xffff0000); for(index = 0 ; index < count ; index++){ @@ -72,11 +72,11 @@ static void rtl8188eu_cal_txdesc_chksum(struct tx_desc *ptxdesc) ptxdesc->txdw7 |= cpu_to_le32(0x0000ffff&checksum); } -// -// Description: In normal chip, we should send some packet to Hw which will be used by Fw -// in FW LPS mode. The function is to fill the Tx descriptor of this packets, then -// Fw can tell Hw to send these packet derectly. -// +/* */ +/* Description: In normal chip, we should send some packet to Hw which will be used by Fw */ +/* in FW LPS mode. The function is to fill the Tx descriptor of this packets, then */ +/* Fw can tell Hw to send these packet derectly. */ +/* */ void rtl8188e_fill_fake_txdesc( struct adapter *padapter, u8* pDesc, @@ -87,41 +87,41 @@ void rtl8188e_fill_fake_txdesc( struct tx_desc *ptxdesc; - // Clear all status + /* Clear all status */ ptxdesc = (struct tx_desc*)pDesc; memset(pDesc, 0, TXDESC_SIZE); - //offset 0 - ptxdesc->txdw0 |= cpu_to_le32( OWN | FSG | LSG); //own, bFirstSeg, bLastSeg; + /* offset 0 */ + ptxdesc->txdw0 |= cpu_to_le32( OWN | FSG | LSG); /* own, bFirstSeg, bLastSeg; */ - ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<txdw0 |= cpu_to_le32(BufferLen&0x0000ffff); // Buffer size + command header + ptxdesc->txdw0 |= cpu_to_le32(BufferLen&0x0000ffff); /* Buffer size + command header */ - //offset 4 - ptxdesc->txdw1 |= cpu_to_le32((QSLT_MGNT<txdw1 |= cpu_to_le32((QSLT_MGNT<txdw1 |= cpu_to_le32(NAVUSEHDR); } else { - ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number - ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29. + ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); /* Hw set sequence number */ + ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); /* set bit3 to 1. Suugested by TimChen. 2009.12.29. */ } if (true == IsBTQosNull) { - ptxdesc->txdw2 |= cpu_to_le32(BIT(23)); // BT NULL + ptxdesc->txdw2 |= cpu_to_le32(BIT(23)); /* BT NULL */ } - //offset 16 - ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate + /* offset 16 */ + ptxdesc->txdw4 |= cpu_to_le32(BIT(8));/* driver uses rate */ - // USB interface drop packet if the checksum of descriptor isn't correct. - // Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.). + /* USB interface drop packet if the checksum of descriptor isn't correct. */ + /* Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.). */ rtl8188eu_cal_txdesc_chksum(ptxdesc); } @@ -129,7 +129,7 @@ static void fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxd { if ((pattrib->encrypt > 0) && !pattrib->bswenc) { switch (pattrib->encrypt) { - //SEC_TYPE : 0:NO_ENC,1:WEP40/TKIP,2:WAPI,3:AES + /* SEC_TYPE : 0:NO_ENC,1:WEP40/TKIP,2:WAPI,3:AES */ case _WEP40_: case _WEP104_: ptxdesc->txdw1 |= cpu_to_le32((0x01<vcs_mode); + /* DBG_8192C("cvs_mode=%d\n", pattrib->vcs_mode); */ switch(pattrib->vcs_mode) { @@ -177,7 +177,7 @@ static void fill_txdesc_vcs(struct pkt_attrib *pattrib, __le32 *pdw) if(pattrib->vcs_mode) { *pdw |= cpu_to_le32(HW_RTS_EN); - // Set RTS BW + /* Set RTS BW */ if(pattrib->ht_en) { *pdw |= (pattrib->bwmode&HT_CHANNEL_WIDTH_40)? cpu_to_le32(BIT(27)):0; @@ -196,7 +196,7 @@ static void fill_txdesc_vcs(struct pkt_attrib *pattrib, __le32 *pdw) static void fill_txdesc_phy(struct pkt_attrib *pattrib, __le32 *pdw) { - //DBG_8192C("bwmode=%d, ch_off=%d\n", pattrib->bwmode, pattrib->ch_offset); + /* DBG_8192C("bwmode=%d, ch_off=%d\n", pattrib->bwmode, pattrib->ch_offset); */ if(pattrib->ht_en) { @@ -223,7 +223,7 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bag struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct pkt_attrib *pattrib = &pxmitframe->attrib; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - //struct dm_priv *pdmpriv = &pHalData->dmpriv; + /* struct dm_priv *pdmpriv = &pHalData->dmpriv; */ struct tx_desc *ptxdesc = (struct tx_desc *)pmem; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); @@ -231,37 +231,37 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bag #ifdef CONFIG_P2P struct wifidirect_info* pwdinfo = &padapter->wdinfo; -#endif //CONFIG_P2P +#endif /* CONFIG_P2P */ #ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX if (padapter->registrypriv.mp_mode == 0) { - if((!bagg_pkt) &&(urb_zero_packet_chk(padapter, sz)==0))//(sz %512) != 0 - //if((!bagg_pkt) &&(rtw_usb_bulk_size_boundary(padapter,TXDESC_SIZE+sz)==false)) + if((!bagg_pkt) &&(urb_zero_packet_chk(padapter, sz)==0))/* sz %512) != 0 */ + /* if((!bagg_pkt) &&(rtw_usb_bulk_size_boundary(padapter,TXDESC_SIZE+sz)==false)) */ { ptxdesc = (struct tx_desc *)(pmem+PACKET_OFFSET_SZ); - //DBG_8192C("==> non-agg-pkt,shift pointer...\n"); + /* DBG_8192C("==> non-agg-pkt,shift pointer...\n"); */ pull = 1; } } -#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX +#endif /* CONFIG_USE_USB_BUFFER_ALLOC_TX */ memset(ptxdesc, 0, sizeof(struct tx_desc)); - //4 offset 0 + /* 4 offset 0 */ ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG); - //DBG_8192C("%s==> pkt_len=%d,bagg_pkt=%02x\n",__FUNCTION__,sz,bagg_pkt); - ptxdesc->txdw0 |= cpu_to_le32(sz & 0x0000ffff);//update TXPKTSIZE + /* DBG_8192C("%s==> pkt_len=%d,bagg_pkt=%02x\n",__FUNCTION__,sz,bagg_pkt); */ + ptxdesc->txdw0 |= cpu_to_le32(sz & 0x0000ffff);/* update TXPKTSIZE */ offset = TXDESC_SIZE + OFFSET_SZ; #ifdef CONFIG_TX_EARLY_MODE if(bagg_pkt){ - offset += EARLY_MODE_INFO_SIZE ;//0x28 + offset += EARLY_MODE_INFO_SIZE ;/* 0x28 */ } #endif - //DBG_8192C("%s==>offset(0x%02x) \n",__FUNCTION__,offset); - ptxdesc->txdw0 |= cpu_to_le32(((offset) << OFFSET_SHT) & 0x00ff0000);//32 bytes for TX Desc + /* DBG_8192C("%s==>offset(0x%02x) \n",__FUNCTION__,offset); */ + ptxdesc->txdw0 |= cpu_to_le32(((offset) << OFFSET_SHT) & 0x00ff0000);/* 32 bytes for TX Desc */ if (bmcst) ptxdesc->txdw0 |= cpu_to_le32(BMC); @@ -275,24 +275,24 @@ if (padapter->registrypriv.mp_mode == 0) } } #endif - //DBG_8192C("%s, pkt_offset=0x%02x\n",__FUNCTION__,pxmitframe->pkt_offset); + /* DBG_8192C("%s, pkt_offset=0x%02x\n",__FUNCTION__,pxmitframe->pkt_offset); */ - // pkt_offset, unit:8 bytes padding + /* pkt_offset, unit:8 bytes padding */ if (pxmitframe->pkt_offset > 0) ptxdesc->txdw1 |= cpu_to_le32((pxmitframe->pkt_offset << 26) & 0x7c000000); - //driver uses rate - ptxdesc->txdw4 |= cpu_to_le32(USERATE);//rate control always by driver + /* driver uses rate */ + ptxdesc->txdw4 |= cpu_to_le32(USERATE);/* rate control always by driver */ if((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG) { - //DBG_8192C("pxmitframe->frame_tag == DATA_FRAMETAG\n"); + /* DBG_8192C("pxmitframe->frame_tag == DATA_FRAMETAG\n"); */ - //offset 4 + /* offset 4 */ ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id&0x3F); qsel = (uint)(pattrib->qsel & 0x0000001f); - //DBG_8192C("==> macid(%d) qsel:0x%02x \n",pattrib->mac_id,qsel); + /* DBG_8192C("==> macid(%d) qsel:0x%02x \n",pattrib->mac_id,qsel); */ ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00); ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid<< RATE_ID_SHT) & 0x000F0000); @@ -300,27 +300,27 @@ if (padapter->registrypriv.mp_mode == 0) fill_txdesc_sectype(pattrib, ptxdesc); if(pattrib->ampdu_en==true){ - ptxdesc->txdw2 |= cpu_to_le32(AGG_EN);//AGG EN + ptxdesc->txdw2 |= cpu_to_le32(AGG_EN);/* AGG EN */ ptxdesc->txdw6 = cpu_to_le32(0x6666f800); } else{ - ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);//AGG BK + ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);/* AGG BK */ } - //offset 8 + /* offset 8 */ - //offset 12 + /* offset 12 */ ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<< SEQ_SHT)&0x0FFF0000); - //offset 16 , offset 20 + /* offset 16 , offset 20 */ if (pattrib->qos_en) - ptxdesc->txdw4 |= cpu_to_le32(QOS);//QoS + ptxdesc->txdw4 |= cpu_to_le32(QOS);/* QoS */ - //offset 20 + /* offset 20 */ #ifdef CONFIG_USB_TX_AGGREGATION if (pxmitframe->agg_num > 1){ - //DBG_8192C("%s agg_num:%d\n",__FUNCTION__,pxmitframe->agg_num ); + /* DBG_8192C("%s agg_num:%d\n",__FUNCTION__,pxmitframe->agg_num ); */ ptxdesc->txdw5 |= cpu_to_le32((pxmitframe->agg_num << USB_TXAGG_NUM_SHT) & 0xFF000000); } #endif @@ -330,28 +330,28 @@ if (padapter->registrypriv.mp_mode == 0) (pattrib->ether_type != 0x88b4) && (pattrib->dhcp_pkt != 1)) { - //Non EAP & ARP & DHCP type data packet + /* Non EAP & ARP & DHCP type data packet */ fill_txdesc_vcs(pattrib, &ptxdesc->txdw4); fill_txdesc_phy(pattrib, &ptxdesc->txdw4); - ptxdesc->txdw4 |= cpu_to_le32(0x00000008);//RTS Rate=24M - ptxdesc->txdw5 |= cpu_to_le32(0x0001ff00);//DATA/RTS Rate FB LMT + ptxdesc->txdw4 |= cpu_to_le32(0x00000008);/* RTS Rate=24M */ + ptxdesc->txdw5 |= cpu_to_le32(0x0001ff00);/* DATA/RTS Rate FB LMT */ #if (RATE_ADAPTIVE_SUPPORT == 1) if(pattrib->ht_en){ if( ODM_RA_GetShortGI_8188E(&pHalData->odmpriv,pattrib->mac_id)) - ptxdesc->txdw5 |= cpu_to_le32(SGI);//SGI + ptxdesc->txdw5 |= cpu_to_le32(SGI);/* SGI */ } data_rate =ODM_RA_GetDecisionRate_8188E(&pHalData->odmpriv,pattrib->mac_id); - //for debug + /* for debug */ #if 1 if(padapter->fix_rate!= 0xFF){ data_rate = padapter->fix_rate; ptxdesc->txdw4 |= cpu_to_le32(DISDATAFB); - //printk("==> fix data_rate:0x%02x\n",data_rate); + /* printk("==> fix data_rate:0x%02x\n",data_rate); */ } #endif @@ -360,40 +360,39 @@ if (padapter->registrypriv.mp_mode == 0) #if (POWER_TRAINING_ACTIVE==1) pwr_status = ODM_RA_GetHwPwrStatus_8188E(&pHalData->odmpriv,pattrib->mac_id); ptxdesc->txdw4 |=cpu_to_le32( (pwr_status & 0x7)<< PWR_STATUS_SHT); - #endif //(POWER_TRAINING_ACTIVE==1) - #else//if (RATE_ADAPTIVE_SUPPORT == 1) + #endif /* POWER_TRAINING_ACTIVE==1) */ + #else/* if (RATE_ADAPTIVE_SUPPORT == 1) */ if(pattrib->ht_en) - ptxdesc->txdw5 |= cpu_to_le32(SGI);//SGI + ptxdesc->txdw5 |= cpu_to_le32(SGI);/* SGI */ - data_rate = 0x13; //default rate: MCS7 - if(padapter->fix_rate!= 0xFF){//rate control by iwpriv + data_rate = 0x13; /* default rate: MCS7 */ + if(padapter->fix_rate!= 0xFF){/* rate control by iwpriv */ data_rate = padapter->fix_rate; ptxdesc->txdw4 | cpu_to_le32(DISDATAFB); } ptxdesc->txdw5 |= cpu_to_le32(data_rate & 0x3F); - #endif//if (RATE_ADAPTIVE_SUPPORT == 1) + #endif/* if (RATE_ADAPTIVE_SUPPORT == 1) */ } else { - // EAP data packet and ARP packet and DHCP. - // Use the 1M data rate to send the EAP/ARP packet. - // This will maybe make the handshake smooth. + /* EAP data packet and ARP packet and DHCP. */ + /* Use the 1M data rate to send the EAP/ARP packet. */ + /* This will maybe make the handshake smooth. */ - ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);//AGG BK + ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);/* AGG BK */ if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT) - ptxdesc->txdw4 |= cpu_to_le32(BIT(24));// DATA_SHORT + ptxdesc->txdw4 |= cpu_to_le32(BIT(24));/* DATA_SHORT */ ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate)); } #ifdef CONFIG_TCP_CSUM_OFFLOAD_TX - //offset 24 + /* offset 24 */ if ( pattrib->hw_tcp_csum == 1 ) { - // ptxdesc->txdw6 = 0; // clear TCP_CHECKSUM and IP_CHECKSUM. It's zero already!! u8 ip_hdr_offset = 32 + pattrib->hdrlen + pattrib->iv_len + 8; ptxdesc->txdw7 = (1 << 31) | (ip_hdr_offset << 16); DBG_8192C("ptxdesc->txdw7 = %08x\n", ptxdesc->txdw7); @@ -402,9 +401,9 @@ if (padapter->registrypriv.mp_mode == 0) } else if((pxmitframe->frame_tag&0x0f)== MGNT_FRAMETAG) { - //DBG_8192C("pxmitframe->frame_tag == MGNT_FRAMETAG\n"); + /* DBG_8192C("pxmitframe->frame_tag == MGNT_FRAMETAG\n"); */ - //offset 4 + /* offset 4 */ ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id&0x3f); qsel = (uint)(pattrib->qsel&0x0000001f); @@ -412,11 +411,11 @@ if (padapter->registrypriv.mp_mode == 0) ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid<< RATE_ID_SHT) & 0x000f0000); - //fill_txdesc_sectype(pattrib, ptxdesc); + /* fill_txdesc_sectype(pattrib, ptxdesc); */ - //offset 8 + /* offset 8 */ #ifdef CONFIG_XMIT_ACK - //CCX-TXRPT ack for xmit mgmt frames. + /* CCX-TXRPT ack for xmit mgmt frames. */ if (pxmitframe->ack_report) { #ifdef DBG_CCX static u16 ccx_sw = 0x123; @@ -426,17 +425,17 @@ if (padapter->registrypriv.mp_mode == 0) #endif ptxdesc->txdw2 |= cpu_to_le32(BIT(19)); } -#endif //CONFIG_XMIT_ACK +#endif /* CONFIG_XMIT_ACK */ - //offset 12 + /* offset 12 */ ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<txdw5 |= cpu_to_le32(RTY_LMT_EN);//retry limit enable + /* offset 20 */ + ptxdesc->txdw5 |= cpu_to_le32(RTY_LMT_EN);/* retry limit enable */ if(pattrib->retry_ctrl == true) - ptxdesc->txdw5 |= cpu_to_le32(0x00180000);//retry limit = 6 + ptxdesc->txdw5 |= cpu_to_le32(0x00180000);/* retry limit = 6 */ else - ptxdesc->txdw5 |= cpu_to_le32(0x00300000);//retry limit = 12 + ptxdesc->txdw5 |= cpu_to_le32(0x00300000);/* retry limit = 12 */ #ifdef CONFIG_INTEL_PROXIM if((padapter->proximity.proxim_on==true)&&(pattrib->intel_proxim==true)){ @@ -457,39 +456,35 @@ if (padapter->registrypriv.mp_mode == 0) { DBG_8192C("pxmitframe->frame_tag = %d\n", pxmitframe->frame_tag); - //offset 4 - ptxdesc->txdw1 |= cpu_to_le32((4)&0x3f);//CAM_ID(MAC_ID) + /* offset 4 */ + ptxdesc->txdw1 |= cpu_to_le32((4)&0x3f);/* CAM_ID(MAC_ID) */ - ptxdesc->txdw1 |= cpu_to_le32((6<< RATE_ID_SHT) & 0x000f0000);//raid + ptxdesc->txdw1 |= cpu_to_le32((6<< RATE_ID_SHT) & 0x000f0000);/* raid */ - //offset 8 + /* offset 8 */ - //offset 12 + /* offset 12 */ ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate)); } - // 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS. - // (1) The sequence number of each non-Qos frame / broadcast / multicast / - // mgnt frame should be controled by Hw because Fw will also send null data - // which we cannot control when Fw LPS enable. - // --> default enable non-Qos data sequense number. 2010.06.23. by tynli. - // (2) Enable HW SEQ control for beacon packet, because we use Hw beacon. - // (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets. - // 2010.06.23. Added by tynli. + /* 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS. */ + /* (1) The sequence number of each non-Qos frame / broadcast / multicast / */ + /* mgnt frame should be controled by Hw because Fw will also send null data */ + /* which we cannot control when Fw LPS enable. */ + /* --> default enable non-Qos data sequense number. 2010.06.23. by tynli. */ + /* (2) Enable HW SEQ control for beacon packet, because we use Hw beacon. */ + /* (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets. */ + /* 2010.06.23. Added by tynli. */ if(!pattrib->qos_en) { - //ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number - //ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29. - - ptxdesc->txdw3 |= cpu_to_le32(EN_HWSEQ); // Hw set sequence number - ptxdesc->txdw4 |= cpu_to_le32(HW_SSN); // Hw set sequence number - + ptxdesc->txdw3 |= cpu_to_le32(EN_HWSEQ); /* Hw set sequence number */ + ptxdesc->txdw4 |= cpu_to_le32(HW_SSN); /* Hw set sequence number */ } -#ifdef CONFIG_HW_ANTENNA_DIVERSITY //CONFIG_ANTENNA_DIVERSITY +#ifdef CONFIG_HW_ANTENNA_DIVERSITY /* CONFIG_ANTENNA_DIVERSITY */ ODM_SetTxAntByTxInfo_88E(&pHalData->odmpriv, pmem, pattrib->mac_id); #endif @@ -511,13 +506,13 @@ if (padapter->registrypriv.mp_mode == 0) */ s32 rtl8188eu_xmit_buf_handler(struct adapter *padapter) { - //PHAL_DATA_TYPE phal; + /* PHAL_DATA_TYPE phal; */ struct xmit_priv *pxmitpriv; struct xmit_buf *pxmitbuf; s32 ret; - //phal = GET_HAL_DATA(padapter); + /* phal = GET_HAL_DATA(padapter); */ pxmitpriv = &padapter->xmitpriv; ret = _rtw_down_sema(&pxmitpriv->xmit_sema); @@ -566,7 +561,7 @@ s32 rtl8188eu_xmit_buf_handler(struct adapter *padapter) #ifdef CONFIG_IOL_IOREG_CFG_DBG #include #endif -//for non-agg data frame or management frame +/* for non-agg data frame or management frame */ static s32 rtw_dump_xframe(struct adapter *padapter, struct xmit_frame *pxmitframe) { s32 ret = _SUCCESS; @@ -587,7 +582,7 @@ static s32 rtw_dump_xframe(struct adapter *padapter, struct xmit_frame *pxmitfra { rtw_issue_addbareq_cmd(padapter, pxmitframe); } -#endif //CONFIG_80211N_HT +#endif /* CONFIG_80211N_HT */ mem_addr = pxmitframe->buf_addr; RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_dump_xframe()\n")); @@ -604,7 +599,7 @@ static s32 rtw_dump_xframe(struct adapter *padapter, struct xmit_frame *pxmitfra sz = pxmitpriv->frag_len; sz = sz - 4 - (psecuritypriv->sw_encrypt ? 0 : pattrib->icv_len); } - else //no frag + else /* no frag */ { sz = pattrib->last_txcmdsz; } @@ -613,9 +608,9 @@ static s32 rtw_dump_xframe(struct adapter *padapter, struct xmit_frame *pxmitfra if(pull) { - mem_addr += PACKET_OFFSET_SZ; //pull txdesc head + mem_addr += PACKET_OFFSET_SZ; /* pull txdesc head */ - //pxmitbuf ->pbuf = mem_addr; + /* pxmitbuf ->pbuf = mem_addr; */ pxmitframe->buf_addr = mem_addr; w_sz = sz + TXDESC_SIZE; @@ -640,7 +635,7 @@ static s32 rtw_dump_xframe(struct adapter *padapter, struct xmit_frame *pxmitfra rtw_count_tx_stats(padapter, pxmitframe, sz); RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_write_port, w_sz=%d\n", w_sz)); - //DBG_8192C("rtw_write_port, w_sz=%d, sz=%d, txdesc_sz=%d, tid=%d\n", w_sz, sz, w_sz-sz, pattrib->priority); + /* DBG_8192C("rtw_write_port, w_sz=%d, sz=%d, txdesc_sz=%d, tid=%d\n", w_sz, sz, w_sz-sz, pattrib->priority); */ mem_addr += w_sz; @@ -663,7 +658,7 @@ static u32 xmitframe_need_length(struct xmit_frame *pxmitframe) u32 len = 0; - // no consider fragement + /* no consider fragement */ len = pattrib->hdrlen + pattrib->iv_len + SNAP_SIZE + sizeof(u16) + pattrib->pktlen + @@ -675,14 +670,14 @@ static u32 xmitframe_need_length(struct xmit_frame *pxmitframe) return len; } -#define IDEA_CONDITION 1 // check all packets before enqueue +#define IDEA_CONDITION 1 /* check all packets before enqueue */ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); struct xmit_frame *pxmitframe = NULL; struct xmit_frame *pfirstframe = NULL; - // aggregate variable + /* aggregate variable */ struct hw_xmit *phwxmit; struct sta_info *psta = NULL; struct tx_servq *ptxservq = NULL; @@ -690,15 +685,15 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm _irqL irqL; _list *xmitframe_plist = NULL, *xmitframe_phead = NULL; - u32 pbuf; // next pkt address - u32 pbuf_tail; // last pkt tail - u32 len; // packet length, except TXDESC_SIZE and PKT_OFFSET + u32 pbuf; /* next pkt address */ + u32 pbuf_tail; /* last pkt tail */ + u32 len; /* packet length, except TXDESC_SIZE and PKT_OFFSET */ u32 bulkSize = pHalData->UsbBulkOutSize; u8 descCount; u32 bulkPtr; - // dump frame variable + /* dump frame variable */ u32 ff_hwaddr; #ifndef IDEA_CONDITION @@ -708,24 +703,24 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm RT_TRACE(_module_rtl8192c_xmit_c_, _drv_info_, ("+xmitframe_complete\n")); - // check xmitbuffer is ok + /* check xmitbuffer is ok */ if (pxmitbuf == NULL) { pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); if (pxmitbuf == NULL){ - //DBG_871X("%s #1, connot alloc xmitbuf!!!! \n",__FUNCTION__); + /* DBG_871X("%s #1, connot alloc xmitbuf!!!! \n",__FUNCTION__); */ return false; } } -//DBG_8192C("%s ===================================== \n",__FUNCTION__); - //3 1. pick up first frame +/* DBG_8192C("%s ===================================== \n",__FUNCTION__); */ + /* 3 1. pick up first frame */ do { rtw_free_xmitframe(pxmitpriv, pxmitframe); pxmitframe = rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry); if (pxmitframe == NULL) { - // no more xmit frame, release xmit buffer - //DBG_8192C("no more xmit frame ,return\n"); + /* no more xmit frame, release xmit buffer */ + /* DBG_8192C("no more xmit frame ,return\n"); */ rtw_free_xmitbuf(pxmitpriv, pxmitbuf); return false; } @@ -735,30 +730,30 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_, ("xmitframe_complete: frame tag(%d) is not DATA_FRAMETAG(%d)!\n", pxmitframe->frame_tag, DATA_FRAMETAG)); -// rtw_free_xmitframe(pxmitpriv, pxmitframe); +/* rtw_free_xmitframe(pxmitpriv, pxmitframe); */ continue; } - // TID 0~15 + /* TID 0~15 */ if ((pxmitframe->attrib.priority < 0) || (pxmitframe->attrib.priority > 15)) { RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_, ("xmitframe_complete: TID(%d) should be 0~15!\n", pxmitframe->attrib.priority)); -// rtw_free_xmitframe(pxmitpriv, pxmitframe); +/* rtw_free_xmitframe(pxmitpriv, pxmitframe); */ continue; } #endif - //DBG_8192C("==> pxmitframe->attrib.priority:%d\n",pxmitframe->attrib.priority); + /* DBG_8192C("==> pxmitframe->attrib.priority:%d\n",pxmitframe->attrib.priority); */ pxmitframe->pxmitbuf = pxmitbuf; pxmitframe->buf_addr = pxmitbuf->pbuf; pxmitbuf->priv_data = pxmitframe; - pxmitframe->agg_num = 1; // alloc xmitframe should assign to 1. + pxmitframe->agg_num = 1; /* alloc xmitframe should assign to 1. */ #ifdef CONFIG_TX_EARLY_MODE - pxmitframe->pkt_offset = 2; // first frame of aggregation, reserve one offset for EM info ,another for usb bulk-out block check + pxmitframe->pkt_offset = 2; /* first frame of aggregation, reserve one offset for EM info ,another for usb bulk-out block check */ #else - pxmitframe->pkt_offset = 1; // first frame of aggregation, reserve offset + pxmitframe->pkt_offset = 1; /* first frame of aggregation, reserve offset */ #endif if (rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe) == false) { @@ -766,30 +761,30 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm continue; } - // always return ndis_packet after rtw_xmitframe_coalesce + /* always return ndis_packet after rtw_xmitframe_coalesce */ rtw_os_xmit_complete(padapter, pxmitframe); break; } while (1); - //3 2. aggregate same priority and same DA(AP or STA) frames + /* 3 2. aggregate same priority and same DA(AP or STA) frames */ pfirstframe = pxmitframe; len = xmitframe_need_length(pfirstframe) + TXDESC_SIZE+(pfirstframe->pkt_offset*PACKET_OFFSET_SZ); pbuf_tail = len; pbuf = _RND8(pbuf_tail); - // check pkt amount in one bulk + /* check pkt amount in one bulk */ descCount = 0; bulkPtr = bulkSize; if (pbuf < bulkPtr) descCount++; else { descCount = 0; - bulkPtr = ((pbuf / bulkSize) + 1) * bulkSize; // round to next bulkSize + bulkPtr = ((pbuf / bulkSize) + 1) * bulkSize; /* round to next bulkSize */ } - // dequeue same priority packet from station tx queue - //psta = pfirstframe->attrib.psta; + /* dequeue same priority packet from station tx queue */ + /* psta = pfirstframe->attrib.psta; */ psta = rtw_get_stainfo(&padapter->stapriv, pfirstframe->attrib.ra); if(pfirstframe->attrib.psta != psta){ DBG_871X("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pfirstframe->attrib.psta, psta); @@ -827,8 +822,8 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm phwxmit = pxmitpriv->hwxmits + 2; break; } -//DBG_8192C("==> pkt_no=%d,pkt_len=%d,len=%d,RND8_LEN=%d,pkt_offset=0x%02x\n", - //pxmitframe->agg_num,pxmitframe->attrib.last_txcmdsz,len,pbuf,pxmitframe->pkt_offset ); +/* DBG_8192C("==> pkt_no=%d,pkt_len=%d,len=%d,RND8_LEN=%d,pkt_offset=0x%02x\n", */ + /* pxmitframe->agg_num,pxmitframe->attrib.last_txcmdsz,len,pbuf,pxmitframe->pkt_offset ); */ _enter_critical_bh(&pxmitpriv->lock, &irqL); @@ -840,19 +835,17 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); xmitframe_plist = get_next(xmitframe_plist); - pxmitframe->agg_num = 0; // not first frame of aggregation + pxmitframe->agg_num = 0; /* not first frame of aggregation */ #ifdef CONFIG_TX_EARLY_MODE - pxmitframe->pkt_offset = 1;// not first frame of aggregation,reserve offset for EM Info + pxmitframe->pkt_offset = 1;/* not first frame of aggregation,reserve offset for EM Info */ #else - pxmitframe->pkt_offset = 0; // not first frame of aggregation, no need to reserve offset + pxmitframe->pkt_offset = 0; /* not first frame of aggregation, no need to reserve offset */ #endif len = xmitframe_need_length(pxmitframe) + TXDESC_SIZE +(pxmitframe->pkt_offset*PACKET_OFFSET_SZ); if (_RND8(pbuf + len) > MAX_XMITBUF_SZ) - //if (_RND8(pbuf + len) > (MAX_XMITBUF_SZ/2))//to do : for TX TP finial tune , Georgia 2012-0323 { - //DBG_8192C("%s....len> MAX_XMITBUF_SZ\n",__FUNCTION__); pxmitframe->agg_num = 1; pxmitframe->pkt_offset = 1; break; @@ -862,7 +855,7 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm phwxmit->accnt--; #ifndef IDEA_CONDITION - // suppose only data frames would be in queue + /* suppose only data frames would be in queue */ if (pxmitframe->frame_tag != DATA_FRAMETAG) { RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_, ("xmitframe_complete: frame tag(%d) is not DATA_FRAMETAG(%d)!\n", @@ -871,7 +864,7 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm continue; } - // TID 0~15 + /* TID 0~15 */ if ((pxmitframe->attrib.priority < 0) || (pxmitframe->attrib.priority > 15)) { RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_, @@ -882,7 +875,7 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm } #endif -// pxmitframe->pxmitbuf = pxmitbuf; +/* pxmitframe->pxmitbuf = pxmitbuf; */ pxmitframe->buf_addr = pxmitbuf->pbuf + pbuf; if (rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe) == false) { @@ -891,17 +884,17 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm continue; } - //DBG_8192C("==> pxmitframe->attrib.priority:%d\n",pxmitframe->attrib.priority); - // always return ndis_packet after rtw_xmitframe_coalesce + /* DBG_8192C("==> pxmitframe->attrib.priority:%d\n",pxmitframe->attrib.priority); */ + /* always return ndis_packet after rtw_xmitframe_coalesce */ rtw_os_xmit_complete(padapter, pxmitframe); - // (len - TXDESC_SIZE) == pxmitframe->attrib.last_txcmdsz + /* (len - TXDESC_SIZE) == pxmitframe->attrib.last_txcmdsz */ update_txdesc(pxmitframe, pxmitframe->buf_addr, pxmitframe->attrib.last_txcmdsz,true); - // don't need xmitframe any more + /* don't need xmitframe any more */ rtw_free_xmitframe(pxmitpriv, pxmitframe); - // handle pointer and stop condition + /* handle pointer and stop condition */ pbuf_tail = pbuf + len; pbuf = _RND8(pbuf_tail); @@ -922,7 +915,7 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm descCount = 0; bulkPtr = ((pbuf / bulkSize) + 1) * bulkSize; } - }//end while( aggregate same priority and same DA(AP or STA) frames) + }/* end while( aggregate same priority and same DA(AP or STA) frames) */ if (_rtw_queue_empty(&ptxservq->sta_pending) == true) @@ -937,36 +930,36 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm { rtw_issue_addbareq_cmd(padapter, pfirstframe); } -#endif //CONFIG_80211N_HT +#endif /* CONFIG_80211N_HT */ #ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX - //3 3. update first frame txdesc + /* 3 3. update first frame txdesc */ if ((pbuf_tail % bulkSize) == 0) { - // remove pkt_offset + /* remove pkt_offset */ pbuf_tail -= PACKET_OFFSET_SZ; pfirstframe->buf_addr += PACKET_OFFSET_SZ; pfirstframe->pkt_offset--; - //DBG_8192C("$$$$$ buf size equal to USB block size $$$$$$\n"); + /* DBG_8192C("$$$$$ buf size equal to USB block size $$$$$$\n"); */ } -#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX +#endif /* CONFIG_USE_USB_BUFFER_ALLOC_TX */ update_txdesc(pfirstframe, pfirstframe->buf_addr, pfirstframe->attrib.last_txcmdsz,true); #ifdef CONFIG_TX_EARLY_MODE - //prepare EM info for first frame, agg_num value start from 1 + /* prepare EM info for first frame, agg_num value start from 1 */ pxmitpriv->agg_pkt[0].offset = _RND8(pfirstframe->attrib.last_txcmdsz +TXDESC_SIZE +(pfirstframe->pkt_offset*PACKET_OFFSET_SZ)); - pxmitpriv->agg_pkt[0].pkt_len = pfirstframe->attrib.last_txcmdsz;//get from rtw_xmitframe_coalesce + pxmitpriv->agg_pkt[0].pkt_len = pfirstframe->attrib.last_txcmdsz;/* get from rtw_xmitframe_coalesce */ UpdateEarlyModeInfo8188E(pxmitpriv,pxmitbuf ); #endif - //3 4. write xmit buffer to USB FIFO + /* 3 4. write xmit buffer to USB FIFO */ ff_hwaddr = rtw_get_ff_hwaddr(pfirstframe); -//DBG_8192C("%s ===================================== write port,buf_size(%d) \n",__FUNCTION__,pbuf_tail); - // xmit address == ((xmit_frame*)pxmitbuf->priv_data)->buf_addr +/* DBG_8192C("%s ===================================== write port,buf_size(%d) \n",__FUNCTION__,pbuf_tail); */ + /* xmit address == ((xmit_frame*)pxmitbuf->priv_data)->buf_addr */ rtw_write_port(padapter, ff_hwaddr, pbuf_tail, (u8*)pxmitbuf); - //3 5. update statisitc + /* 3 5. update statisitc */ pbuf_tail -= (pfirstframe->agg_num * TXDESC_SIZE); pbuf_tail -= (pfirstframe->pkt_offset * PACKET_OFFSET_SZ); @@ -1017,12 +1010,12 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm if((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG) { - if(pxmitframe->attrib.priority<=15)//TID0~15 + if(pxmitframe->attrib.priority<=15)/* TID0~15 */ { res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe); } - //DBG_8192C("==> pxmitframe->attrib.priority:%d\n",pxmitframe->attrib.priority); - rtw_os_xmit_complete(padapter, pxmitframe);//always return ndis_packet after rtw_xmitframe_coalesce + /* DBG_8192C("==> pxmitframe->attrib.priority:%d\n",pxmitframe->attrib.priority); */ + rtw_os_xmit_complete(padapter, pxmitframe);/* always return ndis_packet after rtw_xmitframe_coalesce */ } @@ -1062,7 +1055,7 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm static s32 xmitframe_direct(struct adapter *padapter, struct xmit_frame *pxmitframe) { s32 res = _SUCCESS; -//DBG_8192C("==> %s \n",__FUNCTION__); +/* DBG_8192C("==> %s \n",__FUNCTION__); */ res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe); if (res == _SUCCESS) { @@ -1122,7 +1115,7 @@ enqueue: RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("pre_xmitframe: enqueue xmitframe fail\n")); rtw_free_xmitframe(pxmitpriv, pxmitframe); - // Trick, make the statistics correct + /* Trick, make the statistics correct */ pxmitpriv->tx_pkts--; pxmitpriv->tx_drop++; return true; @@ -1155,7 +1148,7 @@ s32 rtl8188eu_hal_xmitframe_enqueue(struct adapter *padapter, struct xmit_frame { rtw_free_xmitframe(pxmitpriv, pxmitframe); - // Trick, make the statistics correct + /* Trick, make the statistics correct */ pxmitpriv->tx_pkts--; pxmitpriv->tx_drop++; } @@ -1175,7 +1168,7 @@ static void rtl8188eu_hostap_mgnt_xmit_cb(struct urb *urb) { struct sk_buff *skb = (struct sk_buff *)urb->context; - //DBG_8192C("%s\n", __FUNCTION__); + /* DBG_8192C("%s\n", __FUNCTION__); */ rtw_skb_free(skb); } @@ -1196,7 +1189,7 @@ s32 rtl8188eu_hostap_mgnt_xmit_entry(struct adapter *padapter, _pkt *pkt) struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); - //DBG_8192C("%s\n", __FUNCTION__); + /* DBG_8192C("%s\n", __FUNCTION__); */ skb = pkt; @@ -1220,13 +1213,13 @@ s32 rtl8188eu_hostap_mgnt_xmit_entry(struct adapter *padapter, _pkt *pkt) goto _exit; } - // ----- fill tx desc ----- + /* ----- fill tx desc ----- */ ptxdesc = (struct tx_desc *)pxmitbuf; memset(ptxdesc, 0, sizeof(*ptxdesc)); - //offset 0 + /* offset 0 */ ptxdesc->txdw0 |= cpu_to_le32(len&0x0000ffff); - ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<txdw0 |= cpu_to_le32(OWN | FSG | LSG); if(bmcst) @@ -1234,44 +1227,44 @@ s32 rtl8188eu_hostap_mgnt_xmit_entry(struct adapter *padapter, _pkt *pkt) ptxdesc->txdw0 |= cpu_to_le32(BIT(24)); } - //offset 4 - ptxdesc->txdw1 |= cpu_to_le32(0x00);//MAC_ID + /* offset 4 */ + ptxdesc->txdw1 |= cpu_to_le32(0x00);/* MAC_ID */ ptxdesc->txdw1 |= cpu_to_le32((0x12<txdw1 |= cpu_to_le32((0x06<< 16) & 0x000f0000);//b mode + ptxdesc->txdw1 |= cpu_to_le32((0x06<< 16) & 0x000f0000);/* b mode */ - //offset 8 + /* offset 8 */ - //offset 12 + /* offset 12 */ ptxdesc->txdw3 |= cpu_to_le32((le16_to_cpu(tx_hdr->seq_ctl)<<16)&0xffff0000); - //offset 16 - ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate + /* offset 16 */ + ptxdesc->txdw4 |= cpu_to_le32(BIT(8));/* driver uses rate */ - //offset 20 + /* offset 20 */ - //HW append seq - ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number - ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29. + /* HW append seq */ + ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); /* Hw set sequence number */ + ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); /* set bit3 to 1. Suugested by TimChen. 2009.12.29. */ rtl8188eu_cal_txdesc_chksum(ptxdesc); - // ----- end of fill tx desc ----- + /* ----- end of fill tx desc ----- */ - // + /* */ skb_put(pxmit_skb, len + TXDESC_SIZE); pxmitbuf = pxmitbuf + TXDESC_SIZE; memcpy(pxmitbuf, skb->data, len); - //DBG_8192C("mgnt_xmit, len=%x\n", pxmit_skb->len); + /* DBG_8192C("mgnt_xmit, len=%x\n", pxmit_skb->len); */ - // ----- prepare urb for submit ----- + /* ----- prepare urb for submit ----- */ - //translate DMA FIFO addr to pipehandle - //pipe = ffaddr2pipehdl(pdvobj, MGT_QUEUE_INX); + /* translate DMA FIFO addr to pipehandle */ + /* pipe = ffaddr2pipehdl(pdvobj, MGT_QUEUE_INX); */ pipe = usb_sndbulkpipe(pdvobj->pusbdev, pHalData->Queue2EPNum[(u8)MGT_QUEUE_INX]&0x0f); usb_fill_bulk_urb(urb, pdvobj->pusbdev, pipe, diff --git a/hal/usb_halinit.c b/hal/usb_halinit.c index 08218bf..989589b 100755 --- a/hal/usb_halinit.c +++ b/hal/usb_halinit.c @@ -38,7 +38,7 @@ #ifdef CONFIG_EFUSE_CONFIG_FILE #include #include -#endif //CONFIG_EFUSE_CONFIG_FILE +#endif /* CONFIG_EFUSE_CONFIG_FILE */ #if DISABLE_BB_RF #define HAL_MAC_ENABLE 0 @@ -91,17 +91,17 @@ static BOOLEAN HalUsbSetQueuePipeMapping8188EUsb( _ConfigNormalChipOutEP_8188E(pAdapter, NumOutPipe); - // Normal chip with one IN and one OUT doesn't have interrupt IN EP. + /* Normal chip with one IN and one OUT doesn't have interrupt IN EP. */ if(1 == pHalData->OutEpNumber){ if(1 != NumInPipe){ return result; } } - // All config other than above support one Bulk IN and one Interrupt IN. - //if(2 != NumInPipe){ - // return result; - //} + /* All config other than above support one Bulk IN and one Interrupt IN. */ + /* if(2 != NumInPipe){ */ + /* return result; */ + /* */ result = Hal_MappingOutPipe(pAdapter, NumOutPipe); @@ -116,26 +116,26 @@ static void rtl8188eu_interface_configure(struct adapter *padapter) if (pdvobjpriv->ishighspeed == true) { - pHalData->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;//512 bytes + pHalData->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;/* 512 bytes */ } else { - pHalData->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;//64 bytes + pHalData->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;/* 64 bytes */ } pHalData->interfaceIndex = pdvobjpriv->InterfaceNumber; #ifdef CONFIG_USB_TX_AGGREGATION pHalData->UsbTxAggMode = 1; - pHalData->UsbTxAggDescNum = 0x6; // only 4 bits + pHalData->UsbTxAggDescNum = 0x6; /* only 4 bits */ #endif #ifdef CONFIG_USB_RX_AGGREGATION - pHalData->UsbRxAggMode = USB_RX_AGG_DMA;// USB_RX_AGG_DMA; - pHalData->UsbRxAggBlockCount = 8; //unit : 512b + pHalData->UsbRxAggMode = USB_RX_AGG_DMA;/* USB_RX_AGG_DMA; */ + pHalData->UsbRxAggBlockCount = 8; /* unit : 512b */ pHalData->UsbRxAggBlockTimeout = 0x6; - pHalData->UsbRxAggPageCount = 48; //uint :128 b //0x0A; // 10 = MAX_RX_DMA_BUFFER_SIZE/2/pHalData->UsbBulkOutSize - pHalData->UsbRxAggPageTimeout = 0x4; //6, absolute time = 34ms/(2^6) + pHalData->UsbRxAggPageCount = 48; /* uint :128 b 0x0A; 10 = MAX_RX_DMA_BUFFER_SIZE/2/pHalData->UsbBulkOutSize */ + pHalData->UsbRxAggPageTimeout = 0x4; /* 6, absolute time = 34ms/(2^6) */ #endif HalUsbSetQueuePipeMapping8188EUsb(padapter, @@ -147,7 +147,7 @@ static u32 InitPowerOn_rtl8188eu(struct adapter *padapter) { u16 value16; u8 bMacPwrCtrlOn=false; - // HW Power on sequence + /* HW Power on sequence */ rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); if(bMacPwrCtrlOn == true) @@ -159,16 +159,16 @@ static u32 InitPowerOn_rtl8188eu(struct adapter *padapter) return _FAIL; } - // Enable MAC DMA/WMAC/SCHEDULE/SEC block - // Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. - rtw_write16(padapter, REG_CR, 0x00); //suggseted by zhouzhou, by page, 20111230 + /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */ + /* Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */ + rtw_write16(padapter, REG_CR, 0x00); /* suggseted by zhouzhou, by page, 20111230 */ - // Enable MAC DMA/WMAC/SCHEDULE/SEC block + /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */ value16 = rtw_read16(padapter, REG_CR); value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN); - // for SDIO - Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. + /* for SDIO - Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */ rtw_write16(padapter, REG_CR, value16); @@ -200,11 +200,11 @@ static void _InitPABias(struct adapter *padapter) u8 pa_setting; BOOLEAN is92C = IS_92C_SERIAL(pHalData->VersionID); - //FIXED PA current issue - //efuse_one_byte_read(padapter, 0x1FA, &pa_setting); + /* FIXED PA current issue */ + /* efuse_one_byte_read(padapter, 0x1FA, &pa_setting); */ pa_setting = EFUSE_Read1Byte(padapter, 0x1FA); - //RT_TRACE(COMP_INIT, DBG_LOUD, ("_InitPABias 0x1FA 0x%x \n",pa_setting)); + /* RT_TRACE(COMP_INIT, DBG_LOUD, ("_InitPABias 0x1FA 0x%x \n",pa_setting)); */ if(!(pa_setting & BIT0)) { @@ -212,7 +212,7 @@ static void _InitPABias(struct adapter *padapter) PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x4F406); PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x8F406); PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0xCF406); - //RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path A\n")); + /* RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path A\n")); */ } if(!(pa_setting & BIT1) && is92C) @@ -221,7 +221,7 @@ static void _InitPABias(struct adapter *padapter) PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x4F406); PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x8F406); PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0xCF406); - //RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path B\n")); + /* RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path B\n")); */ } if(!(pa_setting & BIT4)) @@ -242,7 +242,7 @@ static void _InitBTCoexist(struct adapter *padapter) if(pbtpriv->BT_Coexist && pbtpriv->BT_CoexistType == BT_CSR_BC4) { -//#if MP_DRIVER != 1 +/* if MP_DRIVER != 1 */ if (padapter->registrypriv.mp_mode == 0) { if(pbtpriv->BT_Ant_isolation) @@ -251,7 +251,7 @@ static void _InitBTCoexist(struct adapter *padapter) DBG_8192C("BT write 0x%x = 0x%x\n", REG_GPIO_MUXCFG, 0xa0); } } -//#endif +/* endif */ u1Tmp = rtw_read8(padapter, 0x4fd) & BIT0; u1Tmp = u1Tmp | @@ -270,7 +270,7 @@ static void _InitBTCoexist(struct adapter *padapter) rtw_write32(padapter, REG_BT_COEX_TABLE+0xc, 0x40000010); DBG_8192C("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+0xc, 0x40000010); - //Config to 1T1R + /* Config to 1T1R */ u1Tmp = rtw_read8(padapter,rOFDM0_TRxPathEnable); u1Tmp &= ~(BIT1); rtw_write8( padapter, rOFDM0_TRxPathEnable, u1Tmp); @@ -287,11 +287,11 @@ static void _InitBTCoexist(struct adapter *padapter) -//--------------------------------------------------------------- -// -// MAC init functions -// -//--------------------------------------------------------------- +/* */ +/* */ +/* MAC init functions */ +/* */ +/* */ static void _SetMacID( IN struct adapter *Adapter, u8* MacID @@ -315,7 +315,7 @@ _SetBSSID( } -// Shall USB interface init this? +/* Shall USB interface init this? */ static void _InitInterrupt( IN struct adapter *Adapter @@ -325,9 +325,9 @@ _InitInterrupt( u8 usb_opt; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - //HISR write one to clear + /* HISR write one to clear */ rtw_write32(Adapter, REG_HISR_88E, 0xFFFFFFFF); - // HIMR - + /* HIMR - */ imr = IMR_PSTIMEOUT_88E | IMR_TBDER_88E | IMR_CPWM_88E | IMR_CPWM2_88E ; rtw_write32(Adapter, REG_HIMR_88E, imr); pHalData->IntrMask[0]=imr; @@ -337,9 +337,9 @@ _InitInterrupt( pHalData->IntrMask[1]=imr_ex; #ifdef CONFIG_SUPPORT_USB_INT - // REG_USB_SPECIAL_OPTION - BIT(4) - // 0; Use interrupt endpoint to upload interrupt pkt - // 1; Use bulk endpoint to upload interrupt pkt, + /* REG_USB_SPECIAL_OPTION - BIT(4) */ + /* 0; Use interrupt endpoint to upload interrupt pkt */ + /* 1; Use bulk endpoint to upload interrupt pkt, */ usb_opt = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION); @@ -354,7 +354,7 @@ _InitInterrupt( rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, usb_opt ); -#endif//CONFIG_SUPPORT_USB_INT +#endif/* CONFIG_SUPPORT_USB_INT */ } @@ -387,7 +387,7 @@ _InitQueueReservedPage( numLQ = 0x1C; } - // NOTE: This step shall be proceed before writting REG_RQPN. + /* NOTE: This step shall be proceed before writting REG_RQPN. */ if (pHalData->OutEpQueueSel & TX_SELE_NQ) { numNQ = 0x1C; } @@ -396,15 +396,15 @@ _InitQueueReservedPage( numPubQ = 0xA8 - numHQ - numLQ - numNQ; - // TX DMA + /* TX DMA */ value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN; rtw_write32(Adapter, REG_RQPN, value32); } else { - rtw_write16(Adapter,REG_RQPN_NPQ, 0x0000);//Just follow MP Team,??? Georgia 03/28 + rtw_write16(Adapter,REG_RQPN_NPQ, 0x0000);/* Just follow MP Team,??? Georgia 03/28 */ rtw_write16(Adapter,REG_RQPN_NPQ, 0x0d); - rtw_write32(Adapter,REG_RQPN, 0x808E000d);//reserve 7 page for LPS + rtw_write32(Adapter,REG_RQPN, 0x808E000d);/* reserve 7 page for LPS */ } } @@ -415,9 +415,9 @@ _InitTxBufferBoundary( ) { struct registry_priv *pregistrypriv = &Adapter->registrypriv; - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + /* HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); */ - //u16 txdmactrl; + /* u16 txdmactrl; */ rtw_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); rtw_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); @@ -432,8 +432,8 @@ _InitPageBoundary( IN struct adapter *Adapter ) { - // RX Page Boundary - // + /* RX Page Boundary */ + /* */ u16 rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E-1; rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy); @@ -480,7 +480,7 @@ _InitNormalChipOneOutEpPriority( value = QUEUE_NORMAL; break; default: - //RT_ASSERT(FALSE,("Shall not reach here!\n")); + /* RT_ASSERT(FALSE,("Shall not reach here!\n")); */ break; } @@ -523,7 +523,7 @@ _InitNormalChipTwoOutEpPriority( valueLow = QUEUE_NORMAL; break; default: - //RT_ASSERT(FALSE,("Shall not reach here!\n")); + /* RT_ASSERT(FALSE,("Shall not reach here!\n")); */ break; } @@ -535,7 +535,7 @@ _InitNormalChipTwoOutEpPriority( mgtQ = valueHi; hiQ = valueHi; } - else{//for WMM ,CONFIG_OUT_EP_WIFI_MODE + else{/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */ beQ = valueLow; bkQ = valueHi; viQ = valueHi; @@ -556,7 +556,7 @@ _InitNormalChipThreeOutEpPriority( struct registry_priv *pregistrypriv = &Adapter->registrypriv; u16 beQ,bkQ,viQ,voQ,mgtQ,hiQ; - if(!pregistrypriv->wifi_spec ){// typical setting + if(!pregistrypriv->wifi_spec ){/* typical setting */ beQ = QUEUE_LOW; bkQ = QUEUE_LOW; viQ = QUEUE_NORMAL; @@ -564,7 +564,7 @@ _InitNormalChipThreeOutEpPriority( mgtQ = QUEUE_HIGH; hiQ = QUEUE_HIGH; } - else{// for WMM + else{/* for WMM */ beQ = QUEUE_LOW; bkQ = QUEUE_NORMAL; viQ = QUEUE_NORMAL; @@ -594,7 +594,7 @@ _InitQueuePriority( _InitNormalChipThreeOutEpPriority(Adapter); break; default: - //RT_ASSERT(FALSE,("Shall not reach here!\n")); + /* RT_ASSERT(FALSE,("Shall not reach here!\n")); */ break; } @@ -623,11 +623,11 @@ _InitNetworkType( u32 value32; value32 = rtw_read32(Adapter, REG_CR); - // TODO: use the other function to set network type + /* TODO: use the other function to set network type */ value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP); rtw_write32(Adapter, REG_CR, value32); -// RASSERT(pIoBase->rtw_read8(REG_CR + 2) == 0x2); +/* RASSERT(pIoBase->rtw_read8(REG_CR + 2) == 0x2); */ } static void @@ -635,7 +635,7 @@ _InitTransferPageSize( IN struct adapter *Adapter ) { - // Tx page size is always 128. + /* Tx page size is always 128. */ u8 value8; value8 = _PSRX(PBP_128) | _PSTX(PBP_128); @@ -656,44 +656,44 @@ _InitWMACSetting( IN struct adapter *Adapter ) { - //u32 value32; - //u16 value16; + /* u32 value32; */ + /* u16 value16; */ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - //pHalData->ReceiveConfig = AAP | APM | AM | AB | APP_ICV | ADF | AMF | APP_FCS | HTC_LOC_CTRL | APP_MIC | APP_PHYSTS; - //pHalData->ReceiveConfig = - //RCR_AAP | RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYSTS; - // don't turn on AAP, it will allow all packets to driver + /* pHalData->ReceiveConfig = AAP | APM | AM | AB | APP_ICV | ADF | AMF | APP_FCS | HTC_LOC_CTRL | APP_MIC | APP_PHYSTS; */ + /* pHalData->ReceiveConfig = */ + /* RCR_AAP | RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYSTS; */ + /* don't turn on AAP, it will allow all packets to driver */ pHalData->ReceiveConfig = RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYSTS; #if (1 == RTL8188E_RX_PACKET_INCLUDE_CRC) pHalData->ReceiveConfig |= ACRC32; #endif - // some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile() + /* some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile() */ rtw_write32(Adapter, REG_RCR, pHalData->ReceiveConfig); - // Accept all multicast address + /* Accept all multicast address */ rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF); rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF); - // Accept all data frames - //value16 = 0xFFFF; - //rtw_write16(Adapter, REG_RXFLTMAP2, value16); + /* Accept all data frames */ + /* value16 = 0xFFFF; */ + /* rtw_write16(Adapter, REG_RXFLTMAP2, value16); */ - // 2010.09.08 hpfan - // Since ADF is removed from RCR, ps-poll will not be indicate to driver, - // RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. - //value16 = 0x400; - //rtw_write16(Adapter, REG_RXFLTMAP1, value16); + /* 2010.09.08 hpfan */ + /* Since ADF is removed from RCR, ps-poll will not be indicate to driver, */ + /* RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. */ + /* value16 = 0x400; */ + /* rtw_write16(Adapter, REG_RXFLTMAP1, value16); */ - // Accept all management frames - //value16 = 0xFFFF; - //rtw_write16(Adapter, REG_RXFLTMAP0, value16); + /* Accept all management frames */ + /* value16 = 0xFFFF; */ + /* rtw_write16(Adapter, REG_RXFLTMAP0, value16); */ - //enable RX_SHIFT bits - //rtw_write8(Adapter, REG_TRXDMA_CTRL, rtw_read8(Adapter, REG_TRXDMA_CTRL)|BIT(1)); + /* enable RX_SHIFT bits */ + /* rtw_write8(Adapter, REG_TRXDMA_CTRL, rtw_read8(Adapter, REG_TRXDMA_CTRL)|BIT(1)); */ } @@ -705,20 +705,20 @@ _InitAdaptiveCtrl( u16 value16; u32 value32; - // Response Rate Set + /* Response Rate Set */ value32 = rtw_read32(Adapter, REG_RRSR); value32 &= ~RATE_BITMAP_ALL; value32 |= RATE_RRSR_CCK_ONLY_1M; rtw_write32(Adapter, REG_RRSR, value32); - // CF-END Threshold - //m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); + /* CF-END Threshold */ + /* m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); */ - // SIFS (used in NAV) + /* SIFS (used in NAV) */ value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10); rtw_write16(Adapter, REG_SPEC_SIFS, value16); - // Retry Limit + /* Retry Limit */ value16 = _LRL(0x30) | _SRL(0x30); rtw_write16(Adapter, REG_RL, value16); @@ -729,7 +729,7 @@ _InitRateFallback( IN struct adapter *Adapter ) { - // Set Data Auto Rate Fallback Retry Count register. + /* Set Data Auto Rate Fallback Retry Count register. */ rtw_write32(Adapter, REG_DARFRC, 0x00000000); rtw_write32(Adapter, REG_DARFRC+4, 0x10080404); rtw_write32(Adapter, REG_RARFRC, 0x04030201); @@ -743,17 +743,17 @@ _InitEDCA( IN struct adapter *Adapter ) { - // Set Spec SIFS (used in NAV) + /* Set Spec SIFS (used in NAV) */ rtw_write16(Adapter,REG_SPEC_SIFS, 0x100a); rtw_write16(Adapter,REG_MAC_SPEC_SIFS, 0x100a); - // Set SIFS for CCK + /* Set SIFS for CCK */ rtw_write16(Adapter,REG_SIFS_CTX, 0x100a); - // Set SIFS for OFDM + /* Set SIFS for OFDM */ rtw_write16(Adapter,REG_SIFS_TRX, 0x100a); - // TXOP + /* TXOP */ rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B); rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F); rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324); @@ -779,12 +779,12 @@ static void _InitHWLed(struct adapter *Adapter) if( pledpriv->LedStrategy != HW_LED) return; -// HW led control -// to do .... -//must consider cases of antenna diversity/ commbo card/solo card/mini card +/* HW led control */ +/* to do .... */ +/* must consider cases of antenna diversity/ commbo card/solo card/mini card */ } -#endif //CONFIG_LED +#endif /* CONFIG_LED */ static void _InitRDGSetting( @@ -814,7 +814,7 @@ _InitRetryFunction( value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL); value8 |= EN_AMPDU_RTY_NEW; rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8); - // Set ACK timeout + /* Set ACK timeout */ rtw_write8(Adapter, REG_ACKTO, 0x40); } @@ -840,7 +840,7 @@ usb_AggSettingTxUpdate( { #ifdef CONFIG_USB_TX_AGGREGATION HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + /* PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); */ u32 value32; if(Adapter->registrypriv.wifi_spec) @@ -855,7 +855,7 @@ usb_AggSettingTxUpdate( } #endif -} // usb_AggSettingTxUpdate +} /* usb_AggSettingTxUpdate */ /*----------------------------------------------------------------------------- @@ -880,7 +880,7 @@ usb_AggSettingRxUpdate( { #ifdef CONFIG_USB_RX_AGGREGATION HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + /* PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); */ u8 valueDMA; u8 valueUSB; @@ -923,7 +923,7 @@ usb_AggSettingRxUpdate( break; case USB_RX_AGG_MIX: rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, pHalData->UsbRxAggPageCount); - rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, (pHalData->UsbRxAggPageTimeout& 0x1F));//0x280[12:8] + rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, (pHalData->UsbRxAggPageTimeout& 0x1F));/* 0x280[12:8] */ rtw_write8(Adapter, REG_USB_AGG_TH, pHalData->UsbRxAggBlockCount); rtw_write8(Adapter, REG_USB_AGG_TO, pHalData->UsbRxAggBlockTimeout); @@ -931,7 +931,7 @@ usb_AggSettingRxUpdate( break; case USB_RX_AGG_DISABLE: default: - // TODO: + /* TODO: */ break; } @@ -953,11 +953,11 @@ usb_AggSettingRxUpdate( pHalData->HwRxPageSize = 1024; break; default: - //RT_ASSERT(FALSE, ("RX_PAGE_SIZE_REG_VALUE definition is incorrect!\n")); + /* RT_ASSERT(FALSE, ("RX_PAGE_SIZE_REG_VALUE definition is incorrect!\n")); */ break; } #endif -} // usb_AggSettingRxUpdate +} /* usb_AggSettingRxUpdate */ static void InitUsbAggregationSetting( @@ -966,13 +966,13 @@ InitUsbAggregationSetting( { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - // Tx aggregation setting + /* Tx aggregation setting */ usb_AggSettingTxUpdate(Adapter); - // Rx aggregation setting + /* Rx aggregation setting */ usb_AggSettingRxUpdate(Adapter); - // 201/12/10 MH Add for USB agg mode dynamic switch. + /* 201/12/10 MH Add for USB agg mode dynamic switch. */ pHalData->UsbRxHighSpeedMode = false; } static void HalRxAggr8188EUsb( @@ -1005,7 +1005,7 @@ static void USB_AggModeSwitch( IN struct adapter * Adapter ) { -} // USB_AggModeSwitch +} /* USB_AggModeSwitch */ static void _InitOperationMode( @@ -1024,13 +1024,13 @@ _InitBeaconParameters( rtw_write16(Adapter, REG_BCN_CTRL, 0x1010); - // TODO: Remove these magic number - rtw_write16(Adapter, REG_TBTT_PROHIBIT,0x6404);// ms - rtw_write8(Adapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);// 5ms - rtw_write8(Adapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME); // 2ms + /* TODO: Remove these magic number */ + rtw_write16(Adapter, REG_TBTT_PROHIBIT,0x6404);/* ms */ + rtw_write8(Adapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);/* 5ms */ + rtw_write8(Adapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME); /* 2ms */ - // Suggested by designer timchen. Change beacon AIFS to the largest number - // beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 + /* Suggested by designer timchen. Change beacon AIFS to the largest number */ + /* beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 */ rtw_write16(Adapter, REG_BCNTCFG, 0x660F); pHalData->RegBcnCtrlVal = rtw_read8(Adapter, REG_BCN_CTRL); @@ -1062,9 +1062,9 @@ _InitRFType( return; } - // TODO: Consider that EEPROM set 92CU to 1T1R later. - // Force to overwrite setting according to chip version. Ignore EEPROM setting. - //pHalData->RF_Type = is92CU ? RF_2T2R : RF_1T1R; + /* TODO: Consider that EEPROM set 92CU to 1T1R later. */ + /* Force to overwrite setting according to chip version. Ignore EEPROM setting. */ + /* pHalData->RF_Type = is92CU ? RF_2T2R : RF_1T1R; */ MSG_8192C("Set RF Chip ID to RF_6052 and RF type to %d.\n", pHalData->rf_type); } @@ -1078,14 +1078,14 @@ _BeaconFunctionEnable( ) { rtw_write8(Adapter, REG_BCN_CTRL, (BIT4 | BIT3 | BIT1)); - //SetBcnCtrlReg(Adapter, (BIT4 | BIT3 | BIT1), 0x00); - //RT_TRACE(COMP_BEACON, DBG_LOUD, ("_BeaconFunctionEnable 0x550 0x%x\n", PlatformEFIORead1Byte(Adapter, 0x550))); + /* SetBcnCtrlReg(Adapter, (BIT4 | BIT3 | BIT1), 0x00); */ + /* RT_TRACE(COMP_BEACON, DBG_LOUD, ("_BeaconFunctionEnable 0x550 0x%x\n", PlatformEFIORead1Byte(Adapter, 0x550))); */ rtw_write8(Adapter, REG_RD_CTRL+1, 0x6F); } -// Set CCK and OFDM Block "ON" +/* Set CCK and OFDM Block "ON" */ static void _BBTurnOnBlock( IN struct adapter * Adapter ) @@ -1131,17 +1131,17 @@ _InitAntenna_Selection(IN struct adapter *Adapter) } -// -// 2010/08/26 MH Add for selective suspend mode check. -// If Efuse 0x0e bit1 is not enabled, we can not support selective suspend for Minicard and -// slim card. -// +/* */ +/* 2010/08/26 MH Add for selective suspend mode check. */ +/* If Efuse 0x0e bit1 is not enabled, we can not support selective suspend for Minicard and */ +/* slim card. */ +/* */ static void HalDetectSelectiveSuspendMode( IN struct adapter * Adapter ) { -} // HalDetectSelectiveSuspendMode +} /* HalDetectSelectiveSuspendMode */ /*----------------------------------------------------------------------------- * Function: HwSuspendModeEnable92Cu() * @@ -1163,31 +1163,31 @@ HwSuspendModeEnable_88eu( IN u8 Type ) { - //PRT_USB_DEVICE pDevice = GET_RT_USB_DEVICE(pAdapter); + /* PRT_USB_DEVICE pDevice = GET_RT_USB_DEVICE(pAdapter); */ u16 reg = rtw_read16(pAdapter, REG_GPIO_MUXCFG); - //if (!pDevice->RegUsbSS) + /* if (!pDevice->RegUsbSS) */ { return; } - // - // 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW - // to enter suspend mode automatically. Otherwise, it will shut down major power - // domain and 8051 will stop. When we try to enter selective suspend mode, we - // need to prevent HW to enter D2 mode aumotmatically. Another way, Host will - // issue a S10 signal to power domain. Then it will cleat SIC setting(from Yngli). - // We need to enable HW suspend mode when enter S3/S4 or disable. We need - // to disable HW suspend mode for IPS/radio_off. - // - //RT_TRACE(COMP_RF, DBG_LOUD, ("HwSuspendModeEnable92Cu = %d\n", Type)); + /* */ + /* 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW */ + /* to enter suspend mode automatically. Otherwise, it will shut down major power */ + /* domain and 8051 will stop. When we try to enter selective suspend mode, we */ + /* need to prevent HW to enter D2 mode aumotmatically. Another way, Host will */ + /* issue a S10 signal to power domain. Then it will cleat SIC setting(from Yngli). */ + /* We need to enable HW suspend mode when enter S3/S4 or disable. We need */ + /* to disable HW suspend mode for IPS/radio_off. */ + /* */ + /* RT_TRACE(COMP_RF, DBG_LOUD, ("HwSuspendModeEnable92Cu = %d\n", Type)); */ if (Type == false) { reg |= BIT14; - //RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg)); + /* RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg)); */ rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg); reg |= BIT12; - //RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg)); + /* RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg)); */ rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg); } else @@ -1198,7 +1198,7 @@ HwSuspendModeEnable_88eu( rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg); } -} // HwSuspendModeEnable92Cu +} /* HwSuspendModeEnable92Cu */ rt_rf_power_state RfOnOffDetect(IN struct adapter *pAdapter ) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); @@ -1211,7 +1211,7 @@ rt_rf_power_state RfOnOffDetect(IN struct adapter *pAdapter ) DBG_8192C("pwrdown, 0x5c(BIT7)=%02x\n", val8); rfpowerstate = (val8 & BIT7) ? rf_off: rf_on; } - else // rf on/off + else /* rf on/off */ { rtw_write8( pAdapter, REG_MAC_PINMUX_CFG,rtw_read8(pAdapter, REG_MAC_PINMUX_CFG)&~(BIT3)); val8 = rtw_read8(pAdapter, REG_GPIO_IO_SEL); @@ -1219,7 +1219,7 @@ rt_rf_power_state RfOnOffDetect(IN struct adapter *pAdapter ) rfpowerstate = (val8 & BIT3) ? rf_on : rf_off; } return rfpowerstate; -} // HalDetectPwrDownMode +} /* HalDetectPwrDownMode */ void _ps_open_RF(struct adapter *padapter); @@ -1259,17 +1259,17 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter) HAL_INIT_STAGES_INIT_SECURITY, HAL_INIT_STAGES_MISC11, HAL_INIT_STAGES_INIT_HAL_DM, - //HAL_INIT_STAGES_RF_PS, + /* HAL_INIT_STAGES_RF_PS, */ HAL_INIT_STAGES_IQK, HAL_INIT_STAGES_PW_TRACK, HAL_INIT_STAGES_LCK, - //HAL_INIT_STAGES_MISC21, - //HAL_INIT_STAGES_INIT_PABIAS, + /* HAL_INIT_STAGES_MISC21, */ + /* HAL_INIT_STAGES_INIT_PABIAS, */ #ifdef CONFIG_BT_COEXIST HAL_INIT_STAGES_BT_COEXIST, #endif - //HAL_INIT_STAGES_ANTENNA_SEL, - //HAL_INIT_STAGES_MISC31, + /* HAL_INIT_STAGES_ANTENNA_SEL, */ + /* HAL_INIT_STAGES_MISC31, */ HAL_INIT_STAGES_END, HAL_INIT_STAGES_NUM }; @@ -1289,21 +1289,21 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter) "HAL_INIT_STAGES_INIT_SECURITY", "HAL_INIT_STAGES_MISC11", "HAL_INIT_STAGES_INIT_HAL_DM", - //"HAL_INIT_STAGES_RF_PS", + /* HAL_INIT_STAGES_RF_PS", */ "HAL_INIT_STAGES_IQK", "HAL_INIT_STAGES_PW_TRACK", "HAL_INIT_STAGES_LCK", - //"HAL_INIT_STAGES_MISC21", + /* HAL_INIT_STAGES_MISC21", */ #ifdef CONFIG_BT_COEXIST "HAL_INIT_STAGES_BT_COEXIST", #endif - //"HAL_INIT_STAGES_ANTENNA_SEL", - //"HAL_INIT_STAGES_MISC31", + /* HAL_INIT_STAGES_ANTENNA_SEL", */ + /* HAL_INIT_STAGES_MISC31", */ "HAL_INIT_STAGES_END", }; int hal_init_profiling_i; - u32 hal_init_stages_timestamp[HAL_INIT_STAGES_NUM]; //used to record the time of each stage's starting point + u32 hal_init_stages_timestamp[HAL_INIT_STAGES_NUM]; /* used to record the time of each stage's starting point */ for(hal_init_profiling_i=0;hal_init_profiling_ibkeepfwalive) { _ps_open_RF(Adapter); if(pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized){ -// PHY_IQCalibrate(padapter, true); +/* PHY_IQCalibrate(padapter, true); */ PHY_IQCalibrate_8188E(Adapter,true); } else { -// PHY_IQCalibrate(padapter, false); +/* PHY_IQCalibrate(padapter, false); */ PHY_IQCalibrate_8188E(Adapter,false); pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = true; } -// dm_CheckTXPowerTracking(padapter); -// PHY_LCCalibrate(padapter); +/* dm_CheckTXPowerTracking(padapter); */ +/* PHY_LCCalibrate(padapter); */ ODM_TXPowerTrackingCheck(&pHalData->odmpriv ); PHY_LCCalibrate_8188E(Adapter); @@ -1381,24 +1381,24 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON); goto exit; } - // Save target channel - pHalData->CurrentChannel = 6;//default set to 6 + /* Save target channel */ + pHalData->CurrentChannel = 6;/* default set to 6 */ if(pwrctrlpriv->reg_rfoff == true){ pwrctrlpriv->rf_pwrstate = rf_off; } - // 2010/08/09 MH We need to check if we need to turnon or off RF after detecting - // HW GPIO pin. Before PHY_RFConfig8192C. - //HalDetectPwrDownMode(Adapter); - // 2010/08/26 MH If Efuse does not support sective suspend then disable the function. - //HalDetectSelectiveSuspendMode(Adapter); + /* 2010/08/09 MH We need to check if we need to turnon or off RF after detecting */ + /* HW GPIO pin. Before PHY_RFConfig8192C. */ + /* HalDetectPwrDownMode(Adapter); */ + /* 2010/08/26 MH If Efuse does not support sective suspend then disable the function. */ + /* HalDetectSelectiveSuspendMode(Adapter); */ if (!pregistrypriv->wifi_spec) { txpktbuf_bndy = TX_PAGE_BOUNDARY_88E; } else { - // for WMM + /* for WMM */ txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_88E; } @@ -1420,14 +1420,14 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW); { _InitRxSetting(Adapter); } -#endif //MP_DRIVER == 1 +#endif /* MP_DRIVER == 1 */ { #ifdef CONFIG_WOWLAN status = rtl8188e_FirmwareDownload(Adapter, false); #else status = rtl8188e_FirmwareDownload(Adapter); -#endif //CONFIG_WOWLAN +#endif /* CONFIG_WOWLAN */ if (status != _SUCCESS) { DBG_871X("%s: Download Firmware failed!!\n", __FUNCTION__); @@ -1455,9 +1455,9 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC); } #endif - // - //d. Initialize BB related configurations. - // + /* */ + /* d. Initialize BB related configurations. */ + /* */ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB); #if (HAL_BB_ENABLE == 1) status = PHY_BBConfig8188E(Adapter); @@ -1498,27 +1498,26 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT); } HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02); - // Get Rx PHY status in order to report RSSI and others. + /* Get Rx PHY status in order to report RSSI and others. */ _InitDriverInfoSize(Adapter, DRVINFO_SZ); _InitInterrupt(Adapter); - hal_init_macaddr(Adapter);//set mac_address - _InitNetworkType(Adapter);//set msr + hal_init_macaddr(Adapter);/* set mac_address */ + _InitNetworkType(Adapter);/* set msr */ _InitWMACSetting(Adapter); _InitAdaptiveCtrl(Adapter); _InitEDCA(Adapter); - //_InitRateFallback(Adapter);//just follow MP Team ???Georgia _InitRetryFunction(Adapter); InitUsbAggregationSetting(Adapter); - _InitOperationMode(Adapter);//todo + _InitOperationMode(Adapter);/* todo */ _InitBeaconParameters(Adapter); _InitBeaconMaxError(Adapter, true); - // - // Init CR MACTXEN, MACRXEN after setting RxFF boundary REG_TRXFF_BNDY to patch - // Hw bug which Hw initials RxFF boundry size to a value which is larger than the real Rx buffer size in 88E. - // - // Enable MACTXEN/MACRXEN block + /* */ + /* Init CR MACTXEN, MACRXEN after setting RxFF boundary REG_TRXFF_BNDY to patch */ + /* Hw bug which Hw initials RxFF boundry size to a value which is larger than the real Rx buffer size in 88E. */ + /* */ + /* Enable MACTXEN/MACRXEN block */ value16 = rtw_read16(Adapter, REG_CR); value16 |= (MACTXEN | MACRXEN); rtw_write8(Adapter, REG_CR, value16); @@ -1532,13 +1531,13 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02); } #if (RATE_ADAPTIVE_SUPPORT==1) - {//Enable TX Report - //Enable Tx Report Timer + {/* Enable TX Report */ + /* Enable Tx Report Timer */ value8 = rtw_read8(Adapter, REG_TX_RPT_CTRL); rtw_write8(Adapter, REG_TX_RPT_CTRL, (value8|BIT1|BIT0)); - //Set MAX RPT MACID - rtw_write8(Adapter, REG_TX_RPT_CTRL+1, 2);//FOR sta mode ,0: bc/mc ,1:AP - //Tx RPT Timer. Unit: 32us + /* Set MAX RPT MACID */ + rtw_write8(Adapter, REG_TX_RPT_CTRL+1, 2);/* FOR sta mode ,0: bc/mc ,1:AP */ + /* Tx RPT Timer. Unit: 32us */ rtw_write16(Adapter, REG_TX_RPT_TIME, 0xCdf0); } #endif @@ -1574,61 +1573,61 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02); #if defined(CONFIG_TX_MCAST2UNI) #ifdef CONFIG_CHECK_AC_LIFETIME - // Enable lifetime check for the four ACs + /* Enable lifetime check for the four ACs */ rtw_write8(Adapter, REG_LIFETIME_EN, 0x0F); -#endif // CONFIG_CHECK_AC_LIFETIME +#endif /* CONFIG_CHECK_AC_LIFETIME */ #ifdef CONFIG_TX_MCAST2UNI - rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); // unit: 256us. 256ms - rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); // unit: 256us. 256ms -#else // CONFIG_TX_MCAST2UNI - rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x3000); // unit: 256us. 3s - rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x3000); // unit: 256us. 3s -#endif // CONFIG_TX_MCAST2UNI -#endif // CONFIG_TX_MCAST2UNI + rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ + rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ +#else /* CONFIG_TX_MCAST2UNI */ + rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x3000); /* unit: 256us. 3s */ + rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x3000); /* unit: 256us. 3s */ +#endif /* CONFIG_TX_MCAST2UNI */ +#endif /* CONFIG_TX_MCAST2UNI */ #ifdef CONFIG_LED _InitHWLed(Adapter); -#endif //CONFIG_LED +#endif /* CONFIG_LED */ - // - // Joseph Note: Keep RfRegChnlVal for later use. - // + /* */ + /* Joseph Note: Keep RfRegChnlVal for later use. */ + /* */ pHalData->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (RF_RADIO_PATH_E)0, RF_CHNLBW, bRFRegOffsetMask); pHalData->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (RF_RADIO_PATH_E)1, RF_CHNLBW, bRFRegOffsetMask); HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK); _BBTurnOnBlock(Adapter); - //NicIFSetMacAddress(padapter, padapter->PermanentAddress); + /* NicIFSetMacAddress(padapter, padapter->PermanentAddress); */ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY); invalidate_cam_all(Adapter); HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11); - // 2010/12/17 MH We need to set TX power according to EFUSE content at first. + /* 2010/12/17 MH We need to set TX power according to EFUSE content at first. */ PHY_SetTxPowerLevel8188E(Adapter, pHalData->CurrentChannel); -// Move by Neo for USB SS to below setp -//_RfPowerSave(Adapter); +/* Move by Neo for USB SS to below setp */ +/* _RfPowerSave(Adapter); */ _InitAntenna_Selection(Adapter); - // - // Disable BAR, suggested by Scott - // 2010.04.09 add by hpfan - // + /* */ + /* Disable BAR, suggested by Scott */ + /* 2010.04.09 add by hpfan */ + /* */ rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff); - // HW SEQ CTRL - //set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. + /* HW SEQ CTRL */ + /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */ rtw_write8(Adapter,REG_HWSEQ_CTRL, 0xFF); if(pregistrypriv->wifi_spec) rtw_write16(Adapter,REG_FAST_EDCA_CTRL ,0); - //Nav limit , suggest by scott + /* Nav limit , suggest by scott */ rtw_write8(Adapter, 0x652, 0x0); HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM); @@ -1641,34 +1640,34 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM); MPT_InitializeAdapter(Adapter, Adapter->mppriv.channel); } else -#endif //#if (MP_DRIVER == 1) +#endif /* if (MP_DRIVER == 1) */ { - // - // 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status - // and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not - // call init_adapter. May cause some problem?? - // - // Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed - // in MgntActSet_RF_State() after wake up, because the value of pHalData->eRFPowerState - // is the same as eRfOff, we should change it to eRfOn after we config RF parameters. - // Added by tynli. 2010.03.30. + /* */ + /* 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status */ + /* and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not */ + /* call init_adapter. May cause some problem?? */ + /* */ + /* Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed */ + /* in MgntActSet_RF_State() after wake up, because the value of pHalData->eRFPowerState */ + /* is the same as eRfOff, we should change it to eRfOn after we config RF parameters. */ + /* Added by tynli. 2010.03.30. */ pwrctrlpriv->rf_pwrstate = rf_on; - // enable Tx report. + /* enable Tx report. */ rtw_write8(Adapter, REG_FWHW_TXQ_CTRL+1, 0x0F); - // Suggested by SD1 pisa. Added by tynli. 2011.10.21. - rtw_write8(Adapter, REG_EARLY_MODE_CONTROL+3, 0x01);//Pretx_en, for WEP/TKIP SEC + /* Suggested by SD1 pisa. Added by tynli. 2011.10.21. */ + rtw_write8(Adapter, REG_EARLY_MODE_CONTROL+3, 0x01);/* Pretx_en, for WEP/TKIP SEC */ - //tynli_test_tx_report. + /* tynli_test_tx_report. */ rtw_write16(Adapter, REG_TX_RPT_TIME, 0x3DF0); - //RT_TRACE(COMP_INIT, DBG_TRACE, ("InitializeAdapter8188EUsb() <====\n")); + /* RT_TRACE(COMP_INIT, DBG_TRACE, ("InitializeAdapter8188EUsb() <====\n")); */ - //enable tx DMA to drop the redundate data of packet + /* enable tx DMA to drop the redundate data of packet */ rtw_write16(Adapter,REG_TXDMA_OFFSET_CHK, (rtw_read16(Adapter,REG_TXDMA_OFFSET_CHK) | DROP_DATA_EN)); HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK); - // 2010/08/26 MH Merge from 8192CE. + /* 2010/08/26 MH Merge from 8192CE. */ if(pwrctrlpriv->rf_pwrstate == rf_on) { if(pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized){ @@ -1690,14 +1689,14 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK); } } -//HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS); -// _InitPABias(Adapter); +/* HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS); */ +/* _InitPABias(Adapter); */ rtw_write8(Adapter, REG_USB_HRPWM, 0); #ifdef CONFIG_XMIT_ACK - //ack for xmit mgmt frames. + /* ack for xmit mgmt frames. */ rtw_write32(Adapter, REG_FWHW_TXQ_CTRL, rtw_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12)); -#endif //CONFIG_XMIT_ACK +#endif /* CONFIG_XMIT_ACK */ exit: HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END); @@ -1724,15 +1723,15 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END); } void _ps_open_RF(struct adapter *padapter) { - //here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified - //phy_SsPwrSwitch92CU(padapter, rf_on, 1); + /* here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified */ + /* phy_SsPwrSwitch92CU(padapter, rf_on, 1); */ } static void hal_poweroff_rtl8188eu( IN struct adapter * Adapter ) { -// PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); +/* PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); */ u8 val8; u16 val16; u32 val32; @@ -1744,65 +1743,58 @@ static void hal_poweroff_rtl8188eu( RT_TRACE(COMP_INIT, DBG_LOUD, ("%s\n",__FUNCTION__)); - //Stop Tx Report Timer. 0x4EC[Bit1]=b'0 + /* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */ val8 = rtw_read8(Adapter, REG_TX_RPT_CTRL); rtw_write8(Adapter, REG_TX_RPT_CTRL, val8&(~BIT1)); - // stop rx + /* stop rx */ rtw_write8(Adapter, REG_CR, 0x0); - // Run LPS WL RFOFF flow + /* Run LPS WL RFOFF flow */ HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_LPS_ENTER_FLOW); - // 2. 0x1F[7:0] = 0 // turn off RF - //rtw_write8(Adapter, REG_RF_CTRL, 0x00); - val8 = rtw_read8(Adapter, REG_MCUFWDL); - if ((val8 & RAM_DL_SEL) && Adapter->bFWReady) //8051 RAM code + if ((val8 & RAM_DL_SEL) && Adapter->bFWReady) /* 8051 RAM code */ { - //rtl8723a_FirmwareSelfReset(padapter); - //_8051Reset88E(padapter); + /* rtl8723a_FirmwareSelfReset(padapter); */ + /* _8051Reset88E(padapter); */ - // Reset MCU 0x2[10]=0. + /* Reset MCU 0x2[10]=0. */ val8 = rtw_read8(Adapter, REG_SYS_FUNC_EN+1); - val8 &= ~BIT(2); // 0x2[10], FEN_CPUEN + val8 &= ~BIT(2); /* 0x2[10], FEN_CPUEN */ rtw_write8(Adapter, REG_SYS_FUNC_EN+1, val8); } - //val8 = rtw_read8(Adapter, REG_SYS_FUNC_EN+1); - //val8 &= ~BIT(2); // 0x2[10], FEN_CPUEN - //rtw_write8(Adapter, REG_SYS_FUNC_EN+1, val8); - - // MCUFWDL 0x80[1:0]=0 - // reset MCU ready status + /* MCUFWDL 0x80[1:0]=0 */ + /* reset MCU ready status */ rtw_write8(Adapter, REG_MCUFWDL, 0); - //YJ,add,111212 - //Disable 32k + /* YJ,add,111212 */ + /* Disable 32k */ val8 = rtw_read8(Adapter, REG_32K_CTRL); rtw_write8(Adapter, REG_32K_CTRL, val8&(~BIT0)); - // Card disable power action flow + /* Card disable power action flow */ HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_DISABLE_FLOW); - // Reset MCU IO Wrapper + /* Reset MCU IO Wrapper */ val8 = rtw_read8(Adapter, REG_RSV_CTRL+1); rtw_write8(Adapter, REG_RSV_CTRL+1, (val8&(~BIT3))); val8 = rtw_read8(Adapter, REG_RSV_CTRL+1); rtw_write8(Adapter, REG_RSV_CTRL+1, val8|BIT3); - //YJ,test add, 111207. For Power Consumption. + /* YJ,test add, 111207. For Power Consumption. */ val8 = rtw_read8(Adapter, GPIO_IN); rtw_write8(Adapter, GPIO_OUT, val8); - rtw_write8(Adapter, GPIO_IO_SEL, 0xFF);//Reg0x46 + rtw_write8(Adapter, GPIO_IO_SEL, 0xFF);/* Reg0x46 */ val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL); - //rtw_write8(Adapter, REG_GPIO_IO_SEL, (val8<<4)|val8); + /* rtw_write8(Adapter, REG_GPIO_IO_SEL, (val8<<4)|val8); */ rtw_write8(Adapter, REG_GPIO_IO_SEL, (val8<<4)); val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL+1); - rtw_write8(Adapter, REG_GPIO_IO_SEL+1, val8|0x0F);//Reg0x43 - rtw_write32(Adapter, REG_BB_PAD_CTRL, 0x00080808);//set LNA ,TRSW,EX_PA Pin to output mode + rtw_write8(Adapter, REG_GPIO_IO_SEL+1, val8|0x0F);/* Reg0x43 */ + rtw_write32(Adapter, REG_BB_PAD_CTRL, 0x00080808);/* set LNA ,TRSW,EX_PA Pin to output mode */ bMacPwrCtrlOn = false; rtw_hal_set_hwreg(Adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); Adapter->bFWReady = false; @@ -1810,10 +1802,10 @@ static void hal_poweroff_rtl8188eu( static void rtl8188eu_hw_power_down(struct adapter *padapter) { - // 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c. - // Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1. + /* 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c. */ + /* Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1. */ - // Enable register area 0x0-0xc. + /* Enable register area 0x0-0xc. */ rtw_write8(padapter,REG_RSV_CTRL, 0x0); rtw_write16(padapter, REG_APS_FSMCO, 0x8812); } @@ -1875,7 +1867,7 @@ static unsigned int rtl8188eu_inirp_init(struct adapter *Adapter) precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR; - //issue Rx irp to receive data + /* issue Rx irp to receive data */ precvbuf = (struct recv_buf *)precvpriv->precv_buf; for(i=0; iLedStrategy = SW_LED_MODE1; break; } - pHalData->bLedOpenDrain = true;// Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. -#else // HW LED + pHalData->bLedOpenDrain = true;/* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */ +#else /* HW LED */ pledpriv->LedStrategy = HW_LED; -#endif //CONFIG_SW_LED +#endif /* CONFIG_SW_LED */ } static void @@ -2022,7 +2014,7 @@ readAntennaDiversity( HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); struct registry_priv *registry_par = &pAdapter->registrypriv; - pHalData->AntDivCfg = registry_par->antdiv_cfg ; // 0:OFF , 1:ON, + pHalData->AntDivCfg = registry_par->antdiv_cfg ; /* 0:OFF , 1:ON, */ } static void @@ -2044,18 +2036,18 @@ Hal_EfuseParsePIDVID_8188EU( if( !AutoLoadFail ) { - // VID, PID + /* VID, PID */ pHalData->EEPROMVID = EF2BYTE(*(__le16 *)&hwinfo[EEPROM_VID_88EU]); pHalData->EEPROMPID = EF2BYTE(*(__le16 *)&hwinfo[EEPROM_PID_88EU]); - // Customer ID, 0x00 and 0xff are reserved for Realtek. + /* Customer ID, 0x00 and 0xff are reserved for Realtek. */ pHalData->EEPROMCustomerID = *(u8 *)&hwinfo[EEPROM_CUSTOMERID_88E]; pHalData->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID; } else { pHalData->EEPROMVID = EEPROM_Default_VID; pHalData->EEPROMPID = EEPROM_Default_PID; - // Customer ID, 0x00 and 0xff are reserved for Realtek. + /* Customer ID, 0x00 and 0xff are reserved for Realtek. */ pHalData->EEPROMCustomerID = EEPROM_Default_CustomerID; pHalData->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID; } @@ -2077,17 +2069,17 @@ Hal_EfuseParseMACAddr_8188EU( if (AutoLoadFail) { -// sMacAddr[5] = (u8)GetRandomNumber(1, 254); +/* sMacAddr[5] = (u8)GetRandomNumber(1, 254); */ for (i=0; i<6; i++) pEEPROM->mac_addr[i] = sMacAddr[i]; } else { - //Read Permanent MAC address + /* Read Permanent MAC address */ memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_88EU], ETH_ALEN); } -// NicIFSetMacAddress(pAdapter, pAdapter->PermanentAddress); +/* NicIFSetMacAddress(pAdapter, pAdapter->PermanentAddress); */ RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("Hal_EfuseParseMACAddr_8188EU: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n", @@ -2104,7 +2096,7 @@ Hal_CustomizeByCustomerID_8188EU( { } -// Read HW power down mode selection +/* Read HW power down mode selection */ static void _ReadPSSetting(IN struct adapter *Adapter,IN u8*PROMContent,IN u8 AutoloadFail) { } @@ -2122,7 +2114,7 @@ static u32 Hal_readPGDataFromConfigFile( u8 *PROMContent = pEEPROM->efuse_eeprom_data; - temp[2] = 0; // add end of string '\0' + temp[2] = 0; /* add end of string '\0' */ fp = filp_open("/system/etc/wifi/wifi_efuse.map", O_RDWR, 0644); if (IS_ERR(fp)) { @@ -2138,7 +2130,7 @@ static u32 Hal_readPGDataFromConfigFile( for (i=0; imac_addr[2], pEEPROM->mac_addr[3], pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]); } -#endif //CONFIG_EFUSE_CONFIG_FILE +#endif /* CONFIG_EFUSE_CONFIG_FILE */ static void readAdapterInfo_8188EU( @@ -2234,9 +2226,9 @@ readAdapterInfo_8188EU( Hal_EfuseParsePIDVID_8188EU(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); #ifdef CONFIG_EFUSE_CONFIG_FILE Hal_ReadMACAddrFromFile_8188EU(padapter); -#else //CONFIG_EFUSE_CONFIG_FILE +#else /* CONFIG_EFUSE_CONFIG_FILE */ Hal_EfuseParseMACAddr_8188EU(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); -#endif //CONFIG_EFUSE_CONFIG_FILE +#endif /* CONFIG_EFUSE_CONFIG_FILE */ Hal_ReadPowerSavingMode88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); Hal_ReadTxPowerInfo88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); @@ -2248,9 +2240,9 @@ readAdapterInfo_8188EU( Hal_EfuseParseBoardType88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); Hal_ReadThermalMeter_88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag); - // - // The following part initialize some vars by PG info. - // + /* */ + /* The following part initialize some vars by PG info. */ + /* */ Hal_InitChannelPlan(padapter); Hal_CustomizeByCustomerID_8188EU(padapter); @@ -2273,12 +2265,12 @@ static void _ReadPROMContent( DBG_8192C("Boot from %s, Autoload %s !\n", (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"), (pEEPROM->bautoload_fail_flag ? "Fail" : "OK") ); - //pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE; + /* pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE; */ #ifdef CONFIG_EFUSE_CONFIG_FILE Hal_readPGDataFromConfigFile(Adapter); -#else //CONFIG_EFUSE_CONFIG_FILE +#else /* CONFIG_EFUSE_CONFIG_FILE */ Hal_InitPGData88E(Adapter); -#endif //CONFIG_EFUSE_CONFIG_FILE +#endif /* CONFIG_EFUSE_CONFIG_FILE */ readAdapterInfo_8188EU(Adapter); } @@ -2300,20 +2292,20 @@ _ReadRFType( static int _ReadAdapterInfo8188EU(struct adapter *Adapter) { - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + /* HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); */ u32 start=rtw_get_current_time(); MSG_8192C("====> %s\n", __FUNCTION__); - //Efuse_InitSomeVar(Adapter); + /* Efuse_InitSomeVar(Adapter); */ - //if(IS_HARDWARE_TYPE_8723A(Adapter)) - // _EfuseCellSel(Adapter); + /* if(IS_HARDWARE_TYPE_8723A(Adapter)) */ + /* _EfuseCellSel(Adapter); */ - _ReadRFType(Adapter);//rf_chip -> _InitRFType() + _ReadRFType(Adapter);/* rf_chip -> _InitRFType() */ _ReadPROMContent(Adapter); - //MSG_8192C("%s()(done), rf_chip=0x%x, rf_type=0x%x\n", __FUNCTION__, pHalData->rf_chip, pHalData->rf_type); + /* MSG_8192C("%s()(done), rf_chip=0x%x, rf_type=0x%x\n", __FUNCTION__, pHalData->rf_chip, pHalData->rf_type); */ MSG_8192C("<==== %s in %d ms\n", __FUNCTION__, rtw_get_passing_time_ms(start)); @@ -2323,7 +2315,7 @@ static int _ReadAdapterInfo8188EU(struct adapter *Adapter) static void ReadAdapterInfo8188EU(struct adapter *Adapter) { - // Read EEPROM size before call any EEPROM function + /* Read EEPROM size before call any EEPROM function */ Adapter->EepromAddressSize = GetEEPROMSize8188E(Adapter); _ReadAdapterInfo8188EU(Adapter); @@ -2350,8 +2342,8 @@ static void ResumeTxBeacon(struct adapter *padapter) { HAL_DATA_TYPE* pHalData = GET_HAL_DATA(padapter); - // 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value - // which should be read from register to a global variable. + /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */ + /* which should be read from register to a global variable. */ rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl) | BIT6); pHalData->RegFwHwTxQCtrl |= BIT6; @@ -2389,31 +2381,27 @@ static void StopTxBeacon(struct adapter *padapter) { HAL_DATA_TYPE* pHalData = GET_HAL_DATA(padapter); - // 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value - // which should be read from register to a global variable. + /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */ + /* which should be read from register to a global variable. */ rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl) & (~BIT6)); pHalData->RegFwHwTxQCtrl &= (~BIT6); rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0x64); pHalData->RegReg542 &= ~(BIT0); rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542); - - //todo: CheckFwRsvdPageContent(Adapter); // 2010.06.23. Added by tynli. - } - static void hw_var_set_opmode(struct adapter *Adapter, u8 variable, u8* val) { u8 val8; u8 mode = *((u8 *)val); - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + /* HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); */ { - // disable Port0 TSF update + /* disable Port0 TSF update */ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4)); - // set net_type + /* set net_type */ val8 = rtw_read8(Adapter, MSR)&0x0c; val8 |= mode; rtw_write8(Adapter, MSR, val8); @@ -2424,25 +2412,25 @@ static void hw_var_set_opmode(struct adapter *Adapter, u8 variable, u8* val) { #ifdef CONFIG_INTERRUPT_BASED_TXBCN #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT - rtw_write8(Adapter, REG_DRVERLYINT, 0x05);//restore early int time to 5ms + rtw_write8(Adapter, REG_DRVERLYINT, 0x05);/* restore early int time to 5ms */ UpdateInterruptMask8188EU(Adapter,true, 0, IMR_BCNDMAINT0_88E); - #endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT + #endif/* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */ #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR UpdateInterruptMask8188EU(Adapter,true ,0, (IMR_TBDER_88E|IMR_TBDOK_88E)); - #endif //CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR + #endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */ - #endif //CONFIG_INTERRUPT_BASED_TXBCN + #endif /* CONFIG_INTERRUPT_BASED_TXBCN */ StopTxBeacon(Adapter); - rtw_write8(Adapter,REG_BCN_CTRL, 0x19);//disable atim wnd - //rtw_write8(Adapter,REG_BCN_CTRL, 0x18); + rtw_write8(Adapter,REG_BCN_CTRL, 0x19);/* disable atim wnd */ + /* rtw_write8(Adapter,REG_BCN_CTRL, 0x18); */ } else if((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/) { ResumeTxBeacon(Adapter); rtw_write8(Adapter,REG_BCN_CTRL, 0x1a); - //BIT3 - If set 0, hw will clr bcnq when tx becon ok/fail or port 0 + /* BIT3 - If set 0, hw will clr bcnq when tx becon ok/fail or port 0 */ rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4)); } else if(mode == _HW_STATE_AP_) @@ -2451,61 +2439,59 @@ static void hw_var_set_opmode(struct adapter *Adapter, u8 variable, u8* val) #ifdef CONFIG_INTERRUPT_BASED_TXBCN #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT UpdateInterruptMask8188EU(Adapter,true ,IMR_BCNDMAINT0_88E, 0); - #endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT + #endif/* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */ #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR UpdateInterruptMask8188EU(Adapter,true ,(IMR_TBDER_88E|IMR_TBDOK_88E), 0); - #endif//CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR + #endif/* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */ -#endif //CONFIG_INTERRUPT_BASED_TXBCN +#endif /* CONFIG_INTERRUPT_BASED_TXBCN */ ResumeTxBeacon(Adapter); rtw_write8(Adapter, REG_BCN_CTRL, 0x12); - //Set RCR - //rtw_write32(padapter, REG_RCR, 0x70002a8e);//CBSSID_DATA must set to 0 - //rtw_write32(Adapter, REG_RCR, 0x7000228e);//CBSSID_DATA must set to 0 - rtw_write32(Adapter, REG_RCR, 0x7000208e);//CBSSID_DATA must set to 0,reject ICV_ERR packet - //enable to rx data frame + /* Set RCR */ + rtw_write32(Adapter, REG_RCR, 0x7000208e);/* CBSSID_DATA must set to 0,reject ICV_ERR packet */ + /* enable to rx data frame */ rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF); - //enable to rx ps-poll + /* enable to rx ps-poll */ rtw_write16(Adapter, REG_RXFLTMAP1, 0x0400); - //Beacon Control related register for first time - rtw_write8(Adapter, REG_BCNDMATIM, 0x02); // 2ms + /* Beacon Control related register for first time */ + rtw_write8(Adapter, REG_BCNDMATIM, 0x02); /* 2ms */ - //rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF); - rtw_write8(Adapter, REG_ATIMWND, 0x0a); // 10ms + /* rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF); */ + rtw_write8(Adapter, REG_ATIMWND, 0x0a); /* 10ms */ rtw_write16(Adapter, REG_BCNTCFG, 0x00); rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04); - rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);// +32767 (~32ms) + rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */ - //reset TSF + /* reset TSF */ rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0)); - //BIT3 - If set 0, hw will clr bcnq when tx becon ok/fail or port 0 + /* BIT3 - If set 0, hw will clr bcnq when tx becon ok/fail or port 0 */ rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4)); - //enable BCN0 Function for if1 - //don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) + /* enable BCN0 Function for if1 */ + /* don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) */ #if defined(CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR) rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | EN_TXBCN_RPT|BIT(1))); #else rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION |BIT(1))); #endif - //dis BCN1 ATIM WND if if2 is station + /* dis BCN1 ATIM WND if if2 is station */ rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(0)); #ifdef CONFIG_TSF_RESET_OFFLOAD - // Reset TSF for STA+AP concurrent mode + /* Reset TSF for STA+AP concurrent mode */ if ( check_buddy_fwstate(Adapter, (WIFI_STATION_STATE|WIFI_ASOC_STATE)) ) { if (reset_tsf(Adapter, IFACE_PORT0) == false) DBG_871X("ERROR! %s()-%d: Reset port0 TSF fail\n", __FUNCTION__, __LINE__); } -#endif // CONFIG_TSF_RESET_OFFLOAD +#endif /* CONFIG_TSF_RESET_OFFLOAD */ } } @@ -2602,33 +2588,33 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) u16 BrateCfg = 0; u8 RateIndex = 0; - // 2007.01.16, by Emily - // Select RRSR (in Legacy-OFDM and CCK) - // For 8190, we select only 24M, 12M, 6M, 11M, 5.5M, 2M, and 1M from the Basic rate. - // We do not use other rates. + /* 2007.01.16, by Emily */ + /* Select RRSR (in Legacy-OFDM and CCK) */ + /* For 8190, we select only 24M, 12M, 6M, 11M, 5.5M, 2M, and 1M from the Basic rate. */ + /* We do not use other rates. */ HalSetBrateCfg( Adapter, val, &BrateCfg ); DBG_8192C("HW_VAR_BASIC_RATE: BrateCfg(%#x)\n", BrateCfg); - //2011.03.30 add by Luke Lee - //CCK 2M ACK should be disabled for some BCM and Atheros AP IOT - //because CCK 2M has poor TXEVM - //CCK 5.5M & 11M ACK should be enabled for better performance + /* 2011.03.30 add by Luke Lee */ + /* CCK 2M ACK should be disabled for some BCM and Atheros AP IOT */ + /* because CCK 2M has poor TXEVM */ + /* CCK 5.5M & 11M ACK should be enabled for better performance */ pHalData->BasicRateSet = BrateCfg = (BrateCfg |0xd) & 0x15d; - BrateCfg |= 0x01; // default enable 1M ACK rate - // Set RRSR rate table. + BrateCfg |= 0x01; /* default enable 1M ACK rate */ + /* Set RRSR rate table. */ rtw_write8(Adapter, REG_RRSR, BrateCfg&0xff); rtw_write8(Adapter, REG_RRSR+1, (BrateCfg>>8)&0xff); rtw_write8(Adapter, REG_RRSR+2, rtw_read8(Adapter, REG_RRSR+2)&0xf0); - // Set RTS initial rate + /* Set RTS initial rate */ while(BrateCfg > 0x1) { BrateCfg = (BrateCfg>> 1); RateIndex++; } - // Ziv - Check + /* Ziv - Check */ rtw_write8(Adapter, REG_INIRTS_RATE_SEL, RateIndex); } break; @@ -2644,30 +2630,29 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - //tsf = pmlmeext->TSFValue - ((u32)pmlmeext->TSFValue % (pmlmeinfo->bcn_interval*1024)) -1024; //us - tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) -1024; //us + tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) -1024; /* us */ if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) { - //pHalData->RegTxPause |= STOP_BCNQ;BIT(6) - //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)|BIT(6))); + /* pHalData->RegTxPause |= STOP_BCNQ;BIT(6) */ + /* rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)|BIT(6))); */ StopTxBeacon(Adapter); } - //disable related TSF function + /* disable related TSF function */ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3))); rtw_write32(Adapter, REG_TSFTR, tsf); rtw_write32(Adapter, REG_TSFTR+4, tsf>>32); - //enable related TSF function + /* enable related TSF function */ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3)); if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) { - //pHalData->RegTxPause &= (~STOP_BCNQ); - //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)&(~BIT(6)))); + /* pHalData->RegTxPause &= (~STOP_BCNQ); */ + /* rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)&(~BIT(6)))); */ ResumeTxBeacon(Adapter); } } @@ -2690,32 +2675,32 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) break; case HW_VAR_MLME_DISCONNECT: { - //Set RCR to not to receive data frame when NO LINK state - //rtw_write32(Adapter, REG_RCR, rtw_read32(padapter, REG_RCR) & ~RCR_ADF); - //reject all data frames + /* Set RCR to not to receive data frame when NO LINK state */ + /* rtw_write32(Adapter, REG_RCR, rtw_read32(padapter, REG_RCR) & ~RCR_ADF); */ + /* reject all data frames */ rtw_write16(Adapter, REG_RXFLTMAP2,0x00); - //reset TSF + /* reset TSF */ rtw_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1))); - //disable update TSF + /* disable update TSF */ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4)); } break; case HW_VAR_MLME_SITESURVEY: - if(*((u8 *)val))//under sitesurvey + if(*((u8 *)val))/* under sitesurvey */ { - //config RCR to receive different BSSID & not to receive data frame + /* config RCR to receive different BSSID & not to receive data frame */ u32 v = rtw_read32(Adapter, REG_RCR); v &= ~(RCR_CBSSID_BCN); rtw_write32(Adapter, REG_RCR, v); - //reject all data frame + /* reject all data frame */ rtw_write16(Adapter, REG_RXFLTMAP2,0x00); - //disable update TSF + /* disable update TSF */ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4)); } - else//sitesurvey done + else/* sitesurvey done */ { struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); @@ -2723,19 +2708,19 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) if ((is_client_associated_to_ap(Adapter) == true) || ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ) { - //enable to rx data frame - //rtw_write32(Adapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF); + /* enable to rx data frame */ + /* rtw_write32(Adapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF); */ rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF); - //enable update TSF + /* enable update TSF */ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4))); } else if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) { - //rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_ADF); + /* rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_ADF); */ rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF); - //enable update TSF + /* enable update TSF */ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4))); } @@ -2746,7 +2731,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) if(Adapter->in_cta_test) { u32 v = rtw_read32(Adapter, REG_RCR); - v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN );//| RCR_ADF + v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN );/* RCR_ADF */ rtw_write32(Adapter, REG_RCR, v); } else @@ -2762,16 +2747,16 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) u8 type = *((u8 *)val); struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; - if(type == 0) // prepare to join + if(type == 0) /* prepare to join */ { - //enable to rx data frame.Accept all data frame - //rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF); + /* enable to rx data frame.Accept all data frame */ + /* rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF); */ rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF); if(Adapter->in_cta_test) { u32 v = rtw_read32(Adapter, REG_RCR); - v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN );//| RCR_ADF + v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN );/* RCR_ADF */ rtw_write32(Adapter, REG_RCR, v); } else @@ -2783,18 +2768,18 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) { RetryLimit = (pHalData->CustomerID == RT_CID_CCX) ? 7 : 48; } - else // Ad-hoc Mode + else /* Ad-hoc Mode */ { RetryLimit = 0x7; } } - else if(type == 1) //joinbss_event call back when join res < 0 + else if(type == 1) /* joinbss_event call back when join res < 0 */ { rtw_write16(Adapter, REG_RXFLTMAP2,0x00); } - else if(type == 2) //sta add event call back + else if(type == 2) /* sta add event call back */ { - //enable update TSF + /* enable update TSF */ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4))); if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE)) @@ -2823,10 +2808,10 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) u16 bcn_interval = *((u16 *)val); if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE){ DBG_8192C("%s==> bcn_interval:%d, eraly_int:%d \n",__FUNCTION__,bcn_interval,bcn_interval>>1); - rtw_write8(Adapter, REG_DRVERLYINT, bcn_interval>>1);// 50ms for sdio + rtw_write8(Adapter, REG_DRVERLYINT, bcn_interval>>1);/* 50ms for sdio */ } } -#endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT +#endif/* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */ break; case HW_VAR_SLOT_TIME: @@ -2846,7 +2831,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) u1bAIFS = aSifsTime + (2 * pmlmeinfo->slotTime); - // Temporary removed, 2008.06.20. + /* Temporary removed, 2008.06.20. */ rtw_write8(Adapter, REG_EDCA_VO_PARAM, u1bAIFS); rtw_write8(Adapter, REG_EDCA_VI_PARAM, u1bAIFS); rtw_write8(Adapter, REG_EDCA_BE_PARAM, u1bAIFS); @@ -2855,21 +2840,21 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) } break; case HW_VAR_RESP_SIFS: - //SIFS_Timer = 0x0a0a0808; - //RESP_SIFS for CCK - rtw_write8(Adapter, REG_R2T_SIFS, val[0]); // SIFS_T2T_CCK (0x08) - rtw_write8(Adapter, REG_R2T_SIFS+1, val[1]); //SIFS_R2T_CCK(0x08) - //RESP_SIFS for OFDM - rtw_write8(Adapter, REG_T2T_SIFS, val[2]); //SIFS_T2T_OFDM (0x0a) - rtw_write8(Adapter, REG_T2T_SIFS+1, val[3]); //SIFS_R2T_OFDM(0x0a) + /* SIFS_Timer = 0x0a0a0808; */ + /* RESP_SIFS for CCK */ + rtw_write8(Adapter, REG_R2T_SIFS, val[0]); /* SIFS_T2T_CCK (0x08) */ + rtw_write8(Adapter, REG_R2T_SIFS+1, val[1]); /* SIFS_R2T_CCK(0x08) */ + /* RESP_SIFS for OFDM */ + rtw_write8(Adapter, REG_T2T_SIFS, val[2]); /* SIFS_T2T_OFDM (0x0a) */ + rtw_write8(Adapter, REG_T2T_SIFS+1, val[3]); /* SIFS_R2T_OFDM(0x0a) */ break; case HW_VAR_ACK_PREAMBLE: { u8 regTmp; u8 bShortPreamble = *( (PBOOLEAN)val ); - // Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) + /* Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) */ regTmp = (pHalData->nCur40MhzPrimeSC)<<5; - //regTmp = 0; + /* regTmp = 0; */ if(bShortPreamble) regTmp |= 0x80; @@ -2881,21 +2866,21 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) break; case HW_VAR_DM_FLAG: podmpriv->SupportAbility = *((u8 *)val); - //DBG_871X("HW_VAR_DM_FLAG ==> SupportAbility:0x%08x \n",podmpriv->SupportAbility ); + /* DBG_871X("HW_VAR_DM_FLAG ==> SupportAbility:0x%08x \n",podmpriv->SupportAbility ); */ break; case HW_VAR_DM_FUNC_OP: if(val[0]) - {// save dm flag + {/* save dm flag */ podmpriv->BK_SupportAbility = podmpriv->SupportAbility; } else - {// restore dm flag + {/* restore dm flag */ podmpriv->SupportAbility = podmpriv->BK_SupportAbility; } - //DBG_871X("HW_VAR_DM_FUNC_OP ==> %s SupportAbility:0x%08x \n", - // (val[0]==1)?"Save":"Restore", - // podmpriv->SupportAbility - // ); + /* DBG_871X("HW_VAR_DM_FUNC_OP ==> %s SupportAbility:0x%08x \n", */ + /* (val[0]==1)?"Save":"Restore", */ + /* podmpriv->SupportAbility */ + /* ); */ break; case HW_VAR_DM_FUNC_SET: if(*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE){ @@ -2905,7 +2890,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) else{ podmpriv->SupportAbility |= *((u32 *)val); } - //DBG_871X("HW_VAR_DM_FUNC_SET ==> SupportAbility:0x%08x \n",podmpriv->SupportAbility ); + /* DBG_871X("HW_VAR_DM_FUNC_SET ==> SupportAbility:0x%08x \n",podmpriv->SupportAbility ); */ break; case HW_VAR_DM_FUNC_CLR: podmpriv->SupportAbility &= *((u32 *)val); @@ -2921,24 +2906,24 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) for(i=0;iMgntInfo.MinSpaceCfg)); + /* RT_TRACE(COMP_MLME, DBG_LOUD, ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", Adapter->MgntInfo.MinSpaceCfg)); */ rtw_write8(Adapter, REG_AMPDU_MIN_SPACE, (rtw_read8(Adapter, REG_AMPDU_MIN_SPACE) & 0xf8) | MinSpacingToSet); } } @@ -3041,10 +3026,10 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) #ifdef CONFIG_BT_COEXIST if( (pHalData->bt_coexist.BT_Coexist) && (pHalData->bt_coexist.BT_CoexistType == BT_CSR_BC4) ) - pRegToSet = RegToSet_BT; // 0x97427431; + pRegToSet = RegToSet_BT; /* 0x97427431; */ else #endif - pRegToSet = RegToSet_Normal; // 0xb972a841; + pRegToSet = RegToSet_Normal; /* 0xb972a841; */ FactorToSet = *((u8 *)val); if(FactorToSet <= 3) @@ -3064,7 +3049,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) rtw_write8(Adapter, (REG_AGGLEN_LMT+index), pRegToSet[index]); } - //RT_TRACE(COMP_MLME, DBG_LOUD, ("Set HW_VAR_AMPDU_FACTOR: %#x\n", FactorToSet)); + /* RT_TRACE(COMP_MLME, DBG_LOUD, ("Set HW_VAR_AMPDU_FACTOR: %#x\n", FactorToSet)); */ } } break; @@ -3084,13 +3069,13 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) #ifdef CONFIG_LPS_LCLK { u8 ps_state = *((u8 *)val); - //rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit) for 88e. - //BIT0 value - 1: 32k, 0:40MHz. - //BIT6 value - 1: report cpwm value after success set, 0:do not report. - //BIT7 value - Toggle bit change. - //modify by Thomas. 2012/4/2. + /* rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit) for 88e. */ + /* BIT0 value - 1: 32k, 0:40MHz. */ + /* BIT6 value - 1: report cpwm value after success set, 0:do not report. */ + /* BIT7 value - Toggle bit change. */ + /* modify by Thomas. 2012/4/2. */ ps_state = ps_state & 0xC1; - //DBG_871X("##### Change RPWM value to = %x for switch clk #####\n",ps_state); + /* DBG_871X("##### Change RPWM value to = %x for switch clk #####\n",ps_state); */ rtw_write8(Adapter, REG_USB_HRPWM, ps_state); } #endif @@ -3099,8 +3084,8 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) { u8 psmode = (*(u8 *)val); - // Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power - // saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang. + /* Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power */ + /* saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang. */ if( (psmode != PS_MODE_ACTIVE) && (!IS_92C_SERIAL(pHalData->VersionID))) { ODM_RF_Saving(podmpriv, true); @@ -3121,7 +3106,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) rtl8188e_set_p2p_ps_offload_cmd(Adapter, p2p_ps_state); } break; -#endif //CONFIG_P2P_PS +#endif /* CONFIG_P2P_PS */ #ifdef CONFIG_TDLS case HW_VAR_TDLS_WRCR: rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)&(~RCR_CBSSID_DATA )); @@ -3131,13 +3116,13 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)&(~ RCR_CBSSID_DATA )&(~RCR_CBSSID_BCN )); rtw_write16(Adapter, REG_RXFLTMAP2,0xffff); - //disable update TSF + /* disable update TSF */ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4)); } break; case HW_VAR_TDLS_DONE_CH_SEN: { - //enable update TSF + /* enable update TSF */ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~ BIT(4))); rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|(RCR_CBSSID_BCN )); } @@ -3145,13 +3130,13 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) case HW_VAR_TDLS_RS_RCR: rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|(RCR_CBSSID_DATA)); break; -#endif //CONFIG_TDLS +#endif /* CONFIG_TDLS */ case HW_VAR_INITIAL_GAIN: { DIG_T *pDigTable = &podmpriv->DM_DigTable; u32 rx_gain = ((u32 *)(val))[0]; - if(rx_gain == 0xff){//restore rx gain + if(rx_gain == 0xff){/* restore rx gain */ ODM_Write_DIG(podmpriv,pDigTable->BackupIGValue); } else{ @@ -3188,7 +3173,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) #ifdef CONFIG_SW_ANTENNA_DIVERSITY case HW_VAR_ANTENNA_DIVERSITY_LINK: - //odm_SwAntDivRestAfterLink8192C(Adapter); + /* odm_SwAntDivRestAfterLink8192C(Adapter); */ ODM_SwAntDivRestAfterLink(podmpriv); break; #endif @@ -3197,20 +3182,20 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) { u8 Optimum_antenna = (*(u8 *)val); u8 Ant ; - //switch antenna to Optimum_antenna - //DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B"); + /* switch antenna to Optimum_antenna */ + /* DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B"); */ if(pHalData->CurAntenna != Optimum_antenna) { Ant = (Optimum_antenna==2)?MAIN_ANT:AUX_ANT; ODM_UpdateRxIdleAnt_88E(&pHalData->odmpriv, Ant); pHalData->CurAntenna = Optimum_antenna ; - //DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B"); + /* DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B"); */ } } break; #endif - case HW_VAR_EFUSE_BYTES: // To set EFUE total used bytes, added by Roger, 2008.12.22. + case HW_VAR_EFUSE_BYTES: /* To set EFUE total used bytes, added by Roger, 2008.12.22. */ pHalData->EfuseUsedBytes = *((u16 *)val); break; case HW_VAR_FIFO_CLEARN_UP: @@ -3218,15 +3203,15 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter); u8 trycnt = 100; - //pause tx + /* pause tx */ rtw_write8(Adapter,REG_TXPAUSE,0xff); - //keep sn + /* keep sn */ Adapter->xmitpriv.nqos_ssn = rtw_read16(Adapter,REG_NQOS_SEQ); if(pwrpriv->bkeepfwalive != true) { - //RX DMA stop + /* RX DMA stop */ rtw_write32(Adapter,REG_RXPKT_NUM,(rtw_read32(Adapter,REG_RXPKT_NUM)|RW_RELEASE_EN)); do{ if(!(rtw_read32(Adapter,REG_RXPKT_NUM)&RXDMA_IDLE)) @@ -3235,7 +3220,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) if(trycnt ==0) DBG_8192C("Stop RX DMA failed...... \n"); - //RQPN Load 0 + /* RQPN Load 0 */ rtw_write16(Adapter,REG_RQPN_NPQ,0x0); rtw_write32(Adapter,REG_RQPN,0x80000000); rtw_mdelay_os(10); @@ -3269,11 +3254,11 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) SetFwRelatedForWoWLAN8188ES(Adapter, true); - //Set Pattern - //if(adapter_to_pwrctl(Adapter)->wowlan_pattern==true) - // rtw_wowlan_reload_pattern(Adapter); + /* Set Pattern */ + /* if(adapter_to_pwrctl(Adapter)->wowlan_pattern==true) */ + /* rtw_wowlan_reload_pattern(Adapter); */ - //RX DMA stop + /* RX DMA stop */ DBG_871X_LEVEL(_drv_always_, "Pause DMA\n"); rtw_write32(Adapter,REG_RXPKT_NUM,(rtw_read32(Adapter,REG_RXPKT_NUM)|RW_RELEASE_EN)); do{ @@ -3281,14 +3266,14 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is true\n"); break; } else { - // If RX_DMA is not idle, receive one pkt from DMA + /* If RX_DMA is not idle, receive one pkt from DMA */ DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is not true\n"); } }while(trycnt--); if(trycnt ==0) DBG_871X_LEVEL(_drv_always_, "Stop RX DMA failed...... \n"); - //Set WOWLAN H2C command. + /* Set WOWLAN H2C command. */ DBG_871X_LEVEL(_drv_always_, "Set WOWLan cmd\n"); rtl8188es_set_wowlan_cmd(Adapter, 1); @@ -3310,7 +3295,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) rtw_write8(Adapter, REG_RSV_CTRL, 0x20); rtw_write8(Adapter, REG_RSV_CTRL, 0x60); - //rtw_msleep_os(10); + /* rtw_msleep_os(10); */ break; case WOWLAN_DISABLE: DBG_871X_LEVEL(_drv_always_, "WOWLAN_DISABLE\n"); @@ -3334,14 +3319,14 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) rtw_msleep_os(2); if(!(adapter_to_pwrctl(Adapter)->wowlan_wake_reason & FWDecisionDisconnect)) rtl8188e_set_FwJoinBssReport_cmd(Adapter, 1); - //rtw_msleep_os(10); + /* rtw_msleep_os(10); */ break; default: break; } } break; -#endif //CONFIG_WOWLAN +#endif /* CONFIG_WOWLAN */ #if (RATE_ADAPTIVE_SUPPORT == 1) @@ -3359,7 +3344,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) } break; case HW_VAR_BCN_VALID: - //BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw + /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw */ rtw_write8(Adapter, REG_TDECTRL+2, rtw_read8(Adapter, REG_TDECTRL+2) | BIT0); break; default: @@ -3384,7 +3369,7 @@ static void GetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) val[0] = rtw_read8(Adapter, REG_TXPAUSE); break; case HW_VAR_BCN_VALID: - //BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2 + /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2 */ val[0] = (BIT0 & rtw_read8(Adapter, REG_TDECTRL+2))?true:false; break; case HW_VAR_DM_FLAG: @@ -3395,11 +3380,11 @@ static void GetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) break; case HW_VAR_FWLPS_RF_ON: { - //When we halt NIC, we should check if FW LPS is leave. + /* When we halt NIC, we should check if FW LPS is leave. */ if(adapter_to_pwrctl(Adapter)->rf_pwrstate == rf_off) { - // If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave, - // because Fw is unload. + /* If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave, */ + /* because Fw is unload. */ val[0] = true; } else @@ -3419,7 +3404,7 @@ static void GetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) val[0] = pHalData->CurAntenna; break; #endif - case HW_VAR_EFUSE_BYTES: // To get EFUE total used bytes, added by Roger, 2008.12.22. + case HW_VAR_EFUSE_BYTES: /* To get EFUE total used bytes, added by Roger, 2008.12.22. */ *((u16 *)(val)) = pHalData->EfuseUsedBytes; break; case HW_VAR_APFM_ON_MAC: @@ -3455,10 +3440,10 @@ static void GetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val) ; } -// -// Description: -// Query setting of specified variable. -// +/* */ +/* Description: */ +/* Query setting of specified variable. */ +/* */ static u8 GetHalDefVar8188EUsb( IN struct adapter * Adapter, IN HAL_DEF_VARIABLE eVariable, @@ -3473,7 +3458,7 @@ static u8 GetHalDefVar8188EUsb( switch(eVariable) { case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB: -#if 1 //trunk +#if 1 /* trunk */ { struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; struct sta_priv * pstapriv = &Adapter->stapriv; @@ -3484,7 +3469,7 @@ static u8 GetHalDefVar8188EUsb( *((int *)pValue) = psta->rssi_stat.UndecoratedSmoothedPWDB; } } -#else //V4 branch +#else /* V4 branch */ if(check_fwstate(&Adapter->mlmepriv, WIFI_STATION_STATE) == true){ *((int *)pValue) = pHalData->dmpriv.UndecoratedSmoothedPWDB; } @@ -3535,7 +3520,7 @@ static u8 GetHalDefVar8188EUsb( u8 MacID = *((u8*)pValue); *((u8*)pValue) = ODM_RA_GetHwPwrStatus_8188E(podmpriv, MacID); } -#endif//(POWER_TRAINING_ACTIVE==1) +#endif/* POWER_TRAINING_ACTIVE==1) */ break; case HW_VAR_MAX_RX_AMPDU_FACTOR: @@ -3549,7 +3534,7 @@ static u8 GetHalDefVar8188EUsb( u8 i; u8 bLinked = false; - //if(check_fwstate(&Adapter->mlmepriv, _FW_LINKED)== true) + /* if(check_fwstate(&Adapter->mlmepriv, _FW_LINKED)== true) */ if(rtw_linked_check(Adapter)) bLinked = true; @@ -3573,7 +3558,7 @@ static u8 GetHalDefVar8188EUsb( } } } -#endif //(RATE_ADAPTIVE_SUPPORT == 1) +#endif /* RATE_ADAPTIVE_SUPPORT == 1) */ break; case HAL_DEF_DBG_DUMP_RXPKT: *(( u8*)pValue) = pHalData->bDumpRxPkt; @@ -3593,10 +3578,10 @@ static u8 GetHalDefVar8188EUsb( -// -// Description: -// Change default setting of specified variable. -// +/* */ +/* Description: */ +/* Change default setting of specified variable. */ +/* */ static u8 SetHalDefVar8188EUsb( IN struct adapter * Adapter, IN HAL_DEF_VARIABLE eVariable, @@ -3614,34 +3599,30 @@ static u8 SetHalDefVar8188EUsb( { u8 dm_func = *(( u8*)pValue); - if(dm_func == 0){ //disable all dynamic func + if(dm_func == 0){ /* disable all dynamic func */ podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE; DBG_8192C("==> Disable all dynamic function...\n"); } - else if(dm_func == 1){//disable DIG + else if(dm_func == 1){/* disable DIG */ podmpriv->SupportAbility &= (~DYNAMIC_BB_DIG); DBG_8192C("==> Disable DIG...\n"); } - else if(dm_func == 2){//disable High power + else if(dm_func == 2){/* disable High power */ podmpriv->SupportAbility &= (~DYNAMIC_BB_DYNAMIC_TXPWR); } - else if(dm_func == 3){//disable tx power tracking + else if(dm_func == 3){/* disable tx power tracking */ podmpriv->SupportAbility &= (~DYNAMIC_RF_CALIBRATION); DBG_8192C("==> Disable tx power tracking...\n"); - } - //else if(dm_func == 4){//disable BT coexistence - // pdmpriv->DMFlag &= (~DYNAMIC_FUNC_BT); - //} - else if(dm_func == 5){//disable antenna diversity + } else if(dm_func == 5){/* disable antenna diversity */ podmpriv->SupportAbility &= (~DYNAMIC_BB_ANT_DIV); } - else if(dm_func == 6){//turn on all dynamic func + else if(dm_func == 6){/* turn on all dynamic func */ if(!(podmpriv->SupportAbility & DYNAMIC_BB_DIG)) { DIG_T *pDigTable = &podmpriv->DM_DigTable; pDigTable->CurIGValue= rtw_read8(Adapter,0xc50); } - //pdmpriv->DMFlag |= DYNAMIC_FUNC_BT; + /* pdmpriv->DMFlag |= DYNAMIC_FUNC_BT; */ podmpriv->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE; DBG_8192C("==> Turn on all dynamic function...\n"); } @@ -3660,43 +3641,15 @@ static u8 SetHalDefVar8188EUsb( return bResult; } -/* -u32 _update_92cu_basic_rate(struct adapter *padapter, unsigned int mask) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); -#ifdef CONFIG_BT_COEXIST - struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist); -#endif - unsigned int BrateCfg = 0; -#ifdef CONFIG_BT_COEXIST - if( (pbtpriv->BT_Coexist) && (pbtpriv->BT_CoexistType == BT_CSR_BC4) ) - { - BrateCfg = mask & 0x151; - //DBG_8192C("BT temp disable cck 2/5.5/11M, (0x%x = 0x%x)\n", REG_RRSR, BrateCfg & 0x151); - } - else -#endif - { - //if(pHalData->VersionID != VERSION_TEST_CHIP_88C) - BrateCfg = mask & 0x15F; - //else //for 88CU 46PING setting, Disable CCK 2M, 5.5M, Others must tuning - // BrateCfg = mask & 0x159; - } - - BrateCfg |= 0x01; // default enable 1M ACK rate - - return BrateCfg; -} -*/ static void _update_response_rate(struct adapter *padapter,unsigned int mask) { u8 RateIndex = 0; - // Set RRSR rate table. + /* Set RRSR rate table. */ rtw_write8(padapter, REG_RRSR, mask&0xff); rtw_write8(padapter,REG_RRSR+1, (mask>>8)&0xff); - // Set RTS initial rate + /* Set RTS initial rate */ while(mask > 0x1) { mask = (mask>> 1); @@ -3707,7 +3660,7 @@ static void _update_response_rate(struct adapter *padapter,unsigned int mask) static void UpdateHalRAMask8188EUsb(struct adapter *padapter, u32 mac_id, u8 rssi_level) { - //volatile unsigned int result; + /* volatile unsigned int result; */ u8 init_rate=0; u8 networkType, raid; u32 mask,rate_bitmap; @@ -3715,12 +3668,12 @@ static void UpdateHalRAMask8188EUsb(struct adapter *padapter, u32 mac_id, u8 rss int supportRateNum = 0; struct sta_info *psta; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - //struct dm_priv *pdmpriv = &pHalData->dmpriv; + /* struct dm_priv *pdmpriv = &pHalData->dmpriv; */ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); - if (mac_id >= NUM_STA) //CAM_SIZE + if (mac_id >= NUM_STA) /* CAM_SIZE */ { return; } @@ -3733,10 +3686,10 @@ static void UpdateHalRAMask8188EUsb(struct adapter *padapter, u32 mac_id, u8 rss switch (mac_id) { - case 0:// for infra mode + case 0:/* for infra mode */ supportRateNum = rtw_get_rateset_len(cur_network->SupportedRates); networkType = judge_network_type(padapter, cur_network->SupportedRates, supportRateNum) & 0xf; - //pmlmeext->cur_wireless_mode = networkType; + /* pmlmeext->cur_wireless_mode = networkType; */ raid = networktype_to_raid(networkType); mask = update_supported_rate(cur_network->SupportedRates, supportRateNum); @@ -3750,7 +3703,7 @@ static void UpdateHalRAMask8188EUsb(struct adapter *padapter, u32 mac_id, u8 rss break; - case 1://for broadcast/multicast + case 1:/* for broadcast/multicast */ supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates); if(pmlmeext->cur_wireless_mode & WIRELESS_11B) networkType = WIRELESS_11B; @@ -3762,19 +3715,19 @@ static void UpdateHalRAMask8188EUsb(struct adapter *padapter, u32 mac_id, u8 rss break; - default: //for each sta in IBSS + default: /* for each sta in IBSS */ supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates); networkType = judge_network_type(padapter, pmlmeinfo->FW_sta_info[mac_id].SupportedRates, supportRateNum) & 0xf; - //pmlmeext->cur_wireless_mode = networkType; + /* pmlmeext->cur_wireless_mode = networkType; */ raid = networktype_to_raid(networkType); mask = update_supported_rate(cur_network->SupportedRates, supportRateNum); - //todo: support HT in IBSS + /* todo: support HT in IBSS */ break; } - //mask &=0x0fffffff; + /* mask &=0x0fffffff; */ rate_bitmap = 0x0fffffff; #ifdef CONFIG_ODM_REFRESH_RAMASK { @@ -3792,8 +3745,7 @@ static void UpdateHalRAMask8188EUsb(struct adapter *padapter, u32 mac_id, u8 rss { u8 arg = 0; - //arg = (cam_idx-4)&0x1f;//MACID - arg = mac_id&0x1f;//MACID + arg = mac_id&0x1f;/* MACID */ arg |= BIT(7); @@ -3809,10 +3761,10 @@ static void UpdateHalRAMask8188EUsb(struct adapter *padapter, u32 mac_id, u8 rss else { arg |= BIT(6); } -#endif //CONFIG_INTEL_PROXIM +#endif /* CONFIG_INTEL_PROXIM */ mask |= ((raid<<28)&0xf0000000); - //to do + /* to do */ /* *(u32 *)&RateMask=EF4Byte((ratr_bitmap&0x0fffffff) | (ratr_index<<28)); RateMask[4] = macId | (bShortGI?0x20:0x00) | 0x80; @@ -3837,7 +3789,7 @@ static void UpdateHalRAMask8188EUsb(struct adapter *padapter, u32 mac_id, u8 rss } - //set ra_id + /* set ra_id */ psta->raid = raid; psta->init_rate = init_rate; @@ -3848,25 +3800,25 @@ static void UpdateHalRAMask8188EUsb(struct adapter *padapter, u32 mac_id, u8 rss static void SetBeaconRelatedRegisters8188EUsb(struct adapter *padapter) { u32 value32; - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + /* HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); */ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); u32 bcn_ctrl_reg = REG_BCN_CTRL; - //reset TSF, enable update TSF, correcting TSF On Beacon + /* reset TSF, enable update TSF, correcting TSF On Beacon */ - //REG_BCN_INTERVAL - //REG_BCNDMATIM - //REG_ATIMWND - //REG_TBTT_PROHIBIT - //REG_DRVERLYINT - //REG_BCN_MAX_ERR - //REG_BCNTCFG //(0x510) - //REG_DUAL_TSF_RST - //REG_BCN_CTRL //(0x550) + /* REG_BCN_INTERVAL */ + /* REG_BCNDMATIM */ + /* REG_ATIMWND */ + /* REG_TBTT_PROHIBIT */ + /* REG_DRVERLYINT */ + /* REG_BCN_MAX_ERR */ + /* REG_BCNTCFG (0x510) */ + /* REG_DUAL_TSF_RST */ + /* REG_BCN_CTRL (0x550) */ - //BCN interval + /* BCN interval */ rtw_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval); - rtw_write8(padapter, REG_ATIMWND, 0x02);// 2ms + rtw_write8(padapter, REG_ATIMWND, 0x02);/* 2ms */ _InitBeaconParameters(padapter); @@ -3879,7 +3831,7 @@ static void SetBeaconRelatedRegisters8188EUsb(struct adapter *padapter) value32 |= TSFRST; rtw_write32(padapter, REG_TCR, value32); - // NOTE: Fix test chip's bug (about contention windows's randomness) + /* NOTE: Fix test chip's bug (about contention windows's randomness) */ rtw_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50); rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50); @@ -3887,11 +3839,11 @@ static void SetBeaconRelatedRegisters8188EUsb(struct adapter *padapter) ResumeTxBeacon(padapter); - //rtw_write8(padapter, 0x422, rtw_read8(padapter, 0x422)|BIT(6)); + /* rtw_write8(padapter, 0x422, rtw_read8(padapter, 0x422)|BIT(6)); */ - //rtw_write8(padapter, 0x541, 0xff); + /* rtw_write8(padapter, 0x541, 0xff); */ - //rtw_write8(padapter, 0x542, rtw_read8(padapter, 0x541)|BIT(0)); + /* rtw_write8(padapter, 0x542, rtw_read8(padapter, 0x541)|BIT(0)); */ rtw_write8(padapter, bcn_ctrl_reg, rtw_read8(padapter, bcn_ctrl_reg)|BIT(1)); @@ -3909,17 +3861,17 @@ static void rtl8188eu_init_default_value(struct adapter * padapter) pdmpriv = &pHalData->dmpriv; - //init default value + /* init default value */ pHalData->fw_ractrl = false; if(!pwrctrlpriv->bkeepfwalive) pHalData->LastHMEBoxNum = 0; - //init dm default value + /* init dm default value */ pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = false; - pHalData->odmpriv.RFCalibrateInfo.TM_Trigger = 0;//for IQK - //pdmpriv->binitialized = false; -// pdmpriv->prv_traffic_idx = 3; -// pdmpriv->initialize = 0; + pHalData->odmpriv.RFCalibrateInfo.TM_Trigger = 0;/* for IQK */ + /* pdmpriv->binitialized = false; */ +/* pdmpriv->prv_traffic_idx = 3; */ +/* pdmpriv->initialize = 0; */ pHalData->pwrGroupCnt = 0; pHalData->PGMaxGroup= 13; pHalData->odmpriv.RFCalibrateInfo.ThermalValue_HP_index = 0; @@ -3934,12 +3886,9 @@ static u8 rtl8188eu_ps_func(struct adapter *Adapter,HAL_INTF_PS_FUNC efunc_id, u #if defined(CONFIG_AUTOSUSPEND) && defined(SUPPORT_HW_RFOFF_DETECTED) case HAL_USB_SELECT_SUSPEND: - { - u8 bfwpoll = *(( u8*)val); - //rtl8188e_set_FwSelectSuspend_cmd(Adapter,bfwpoll ,500);//note fw to support hw power down ping detect - } + u8 bfwpoll = *(( u8*)val); break; - #endif //CONFIG_AUTOSUSPEND && SUPPORT_HW_RFOFF_DETECTED + #endif /* CONFIG_AUTOSUSPEND && SUPPORT_HW_RFOFF_DETECTED */ default: break; @@ -3976,19 +3925,19 @@ void rtl8188eu_set_hal_ops(struct adapter * padapter) #ifdef CONFIG_SW_LED pHalFunc->InitSwLeds = &rtl8188eu_InitSwLeds; pHalFunc->DeInitSwLeds = &rtl8188eu_DeInitSwLeds; -#else //case of hw led or no led +#else /* case of hw led or no led */ pHalFunc->InitSwLeds = NULL; pHalFunc->DeInitSwLeds = NULL; -#endif//CONFIG_SW_LED +#endif/* CONFIG_SW_LED */ pHalFunc->init_default_value = &rtl8188eu_init_default_value; pHalFunc->intf_chip_configure = &rtl8188eu_interface_configure; pHalFunc->read_adapter_info = &ReadAdapterInfo8188EU; - //pHalFunc->set_bwmode_handler = &PHY_SetBWMode8192C; - //pHalFunc->set_channel_handler = &PHY_SwChnl8192C; + /* pHalFunc->set_bwmode_handler = &PHY_SetBWMode8192C; */ + /* pHalFunc->set_channel_handler = &PHY_SwChnl8192C; */ - //pHalFunc->hal_dm_watchdog = &rtl8192c_HalDmWatchDog; + /* pHalFunc->hal_dm_watchdog = &rtl8192c_HalDmWatchDog; */ pHalFunc->SetHwRegHandler = &SetHwReg8188EU; @@ -3999,8 +3948,6 @@ void rtl8188eu_set_hal_ops(struct adapter * padapter) pHalFunc->UpdateRAMaskHandler = &UpdateHalRAMask8188EUsb; pHalFunc->SetBeaconRelatedRegistersHandler = &SetBeaconRelatedRegisters8188EUsb; - //pHalFunc->Add_RateATid = &rtl8192c_Add_RateATid; - pHalFunc->hal_xmit = &rtl8188eu_hal_xmit; pHalFunc->mgnt_xmit = &rtl8188eu_mgnt_xmit; pHalFunc->hal_xmitframe_enqueue = &rtl8188eu_hal_xmitframe_enqueue; diff --git a/hal/usb_ops_linux.c b/hal/usb_ops_linux.c index b7b09d3..f63b146 100755 --- a/hal/usb_ops_linux.c +++ b/hal/usb_ops_linux.c @@ -43,7 +43,7 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE u8 *tmp_buf; - #else // use stack memory + #else /* use stack memory */ u8 tmp_buf[MAX_USB_IO_CTL_SIZE]; #endif @@ -64,20 +64,20 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u #endif - // Acquire IO memory for vendorreq + /* Acquire IO memory for vendorreq */ #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC pIo_buf = pdvobjpriv->usb_vendor_req_buf; #else #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE tmp_buf = rtw_malloc( (u32) len + ALIGNMENT_UNIT); tmp_buflen = (u32)len + ALIGNMENT_UNIT; - #else // use stack memory + #else /* use stack memory */ tmp_buflen = MAX_USB_IO_CTL_SIZE; #endif - // Added by Albert 2010/02/09 - // For mstar platform, mstar suggests the address for USB IO should be 16 bytes alignment. - // Trying to fix it here. + /* Added by Albert 2010/02/09 */ + /* For mstar platform, mstar suggests the address for USB IO should be 16 bytes alignment. */ + /* Trying to fix it here. */ pIo_buf = (tmp_buf==NULL)?NULL:tmp_buf + ALIGNMENT_UNIT -((SIZE_PTR)(tmp_buf) & 0x0f ); #endif @@ -93,27 +93,27 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u if (requesttype == 0x01) { - pipe = usb_rcvctrlpipe(udev, 0);//read_in + pipe = usb_rcvctrlpipe(udev, 0);/* read_in */ reqtype = REALTEK_USB_VENQT_READ; } else { - pipe = usb_sndctrlpipe(udev, 0);//write_out + pipe = usb_sndctrlpipe(udev, 0);/* write_out */ reqtype = REALTEK_USB_VENQT_WRITE; memcpy( pIo_buf, pdata, len); } status = rtw_usb_control_msg(udev, pipe, request, reqtype, value, index, pIo_buf, len, RTW_USB_CONTROL_MSG_TIMEOUT); - if ( status == len) // Success this control transfer. + if ( status == len) /* Success this control transfer. */ { rtw_reset_continual_io_error(pdvobjpriv); if ( requesttype == 0x01 ) - { // For Control read transfer, we have to copy the read data from pIo_buf to pdata. + { /* For Control read transfer, we have to copy the read data from pIo_buf to pdata. */ memcpy( pdata, pIo_buf, len ); } } - else { // error cases + else { /* error cases */ DBG_8192C("reg 0x%x, usb %s %u fail, status:%d value=0x%x, vendorreq_times:%d\n" , value,(requesttype == 0x01)?"read":"write" , len, status, *(u32*)pdata, vendorreq_times); @@ -130,11 +130,11 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u #endif } } - else // status != len && status >= 0 + else /* status != len && status >= 0 */ { if (status > 0) { if ( requesttype == 0x01 ) - { // For Control read transfer, we have to copy the read data from pIo_buf to pdata. + { /* For Control read transfer, we have to copy the read data from pIo_buf to pdata. */ memcpy( pdata, pIo_buf, len ); } } @@ -147,13 +147,13 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u } - // firmware download is checksumed, don't retry + /* firmware download is checksumed, don't retry */ if ( (value >= FW_8188E_START_ADDRESS && value <= FW_8188E_END_ADDRESS) || status == len ) break; } - // release IO memory used by vendorreq + /* release IO memory used by vendorreq */ #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE rtw_mfree(tmp_buf, tmp_buflen); #endif @@ -177,8 +177,8 @@ static u8 usb_read8(struct intf_hdl *pintfhdl, u32 addr) u8 data; request = 0x05; - requesttype = 0x01;//read_in - index = 0;//n/a + requesttype = 0x01;/* read_in */ + index = 0;/* n/a */ wvalue = (u16)(addr&0x0000ffff); len = 1; @@ -197,8 +197,8 @@ static u16 usb_read16(struct intf_hdl *pintfhdl, u32 addr) __le32 data; request = 0x05; - requesttype = 0x01;//read_in - index = 0;//n/a + requesttype = 0x01;/* read_in */ + index = 0;/* n/a */ wvalue = (u16)(addr&0x0000ffff); len = 2; @@ -217,8 +217,8 @@ static u32 usb_read32(struct intf_hdl *pintfhdl, u32 addr) __le32 data; request = 0x05; - requesttype = 0x01;//read_in - index = 0;//n/a + requesttype = 0x01;/* read_in */ + index = 0;/* n/a */ wvalue = (u16)(addr&0x0000ffff); len = 4; @@ -239,8 +239,8 @@ static int usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val) int ret; request = 0x05; - requesttype = 0x00;//write_out - index = 0;//n/a + requesttype = 0x00;/* write_out */ + index = 0;/* n/a */ wvalue = (u16)(addr&0x0000ffff); len = 1; @@ -263,8 +263,8 @@ static int usb_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val) int ret; request = 0x05; - requesttype = 0x00;//write_out - index = 0;//n/a + requesttype = 0x00;/* write_out */ + index = 0;/* n/a */ wvalue = (u16)(addr&0x0000ffff); len = 2; @@ -287,8 +287,8 @@ static int usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val) int ret; request = 0x05; - requesttype = 0x00;//write_out - index = 0;//n/a + requesttype = 0x00;/* write_out */ + index = 0;/* n/a */ wvalue = (u16)(addr&0x0000ffff); len = 4; @@ -309,8 +309,8 @@ static int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata u8 buf[VENDOR_CMD_MAX_DATA_LEN]={0}; request = 0x05; - requesttype = 0x00;//write_out - index = 0;//n/a + requesttype = 0x00;/* write_out */ + index = 0;/* n/a */ wvalue = (u16)(addr&0x0000ffff); len = length; @@ -330,7 +330,7 @@ static void interrupt_handler_8188eu(struct adapter *padapter,u16 pkt_len,u8 *pb return ; } - // HISR + /* HISR */ memcpy(&(pHalData->IntArray[0]), &(pbuf[USB_INTR_CONTENT_HISR_OFFSET]), 4); memcpy(&(pHalData->IntArray[1]), &(pbuf[USB_INTR_CONTENT_HISRE_OFFSET]), 4); @@ -338,11 +338,11 @@ static void interrupt_handler_8188eu(struct adapter *padapter,u16 pkt_len,u8 *pb if ( pHalData->IntArray[0] & IMR_CPWM_88E ) { memcpy(&pwr_rpt.state, &(pbuf[USB_INTR_CONTENT_CPWM1_OFFSET]), 1); - //88e's cpwm value only change BIT0, so driver need to add PS_STATE_S2 for LPS flow. + /* 88e's cpwm value only change BIT0, so driver need to add PS_STATE_S2 for LPS flow. */ pwr_rpt.state |= PS_STATE_S2; _set_workitem(&(adapter_to_pwrctl(padapter)->cpwm_event)); } -#endif//CONFIG_LPS_LCLK +#endif/* CONFIG_LPS_LCLK */ #ifdef CONFIG_INTERRUPT_BASED_TXBCN @@ -356,12 +356,12 @@ static void interrupt_handler_8188eu(struct adapter *padapter,u16 pkt_len,u8 *pb struct mlme_priv *pmlmepriv = &padapter->mlmepriv; if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { - //send_beacon(padapter); + /* send_beacon(padapter); */ if (pmlmepriv->update_bcn == true) set_tx_beacon_cmd(padapter); } } -#endif //CONFIG_INTERRUPT_BASED_TXBCN +#endif /* CONFIG_INTERRUPT_BASED_TXBCN */ #ifdef DBG_CONFIG_ERROR_DETECT_INT if ( pHalData->IntArray[1] & IMR_TXERR_88E ) @@ -372,12 +372,12 @@ static void interrupt_handler_8188eu(struct adapter *padapter,u16 pkt_len,u8 *pb DBG_871X("===> %s Transmit FIFO Overflow \n",__FUNCTION__); if ( pHalData->IntArray[1] & IMR_RXFOVW_88E ) DBG_871X("===> %s Receive FIFO Overflow \n",__FUNCTION__); -#endif//DBG_CONFIG_ERROR_DETECT_INT +#endif/* DBG_CONFIG_ERROR_DETECT_INT */ - // C2H Event + /* C2H Event */ if (pbuf[0]!= 0){ memcpy(&(pHalData->C2hArray[0]), &(pbuf[USB_INTR_CONTENT_C2H_OFFSET]), 16); - //rtw_c2h_wk_cmd(padapter); to do.. + /* rtw_c2h_wk_cmd(padapter); to do.. */ } } @@ -397,7 +397,7 @@ static void usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs) return; } - if (purb->status==0)//SUCCESS + if (purb->status==0)/* SUCCESS */ { if (purb->actual_length > INTERRUPT_MSG_FORMAT_LEN) { @@ -421,7 +421,7 @@ static void usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs) case -EPIPE: case -ENODEV: case -ESHUTDOWN: - //padapter->bSurpriseRemoved=true; + /* padapter->bSurpriseRemoved=true; */ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=TRUE\n")); case -ENOENT: padapter->bDriverStopped=true; @@ -451,7 +451,7 @@ static u32 usb_read_interrupt(struct intf_hdl *pintfhdl, u32 addr) ; - //translate DMA FIFO addr to pipehandle + /* translate DMA FIFO addr to pipehandle */ pipe = ffaddr2pipehdl(pdvobj, addr); usb_fill_int_urb(precvpriv->int_in_urb, pusbd, pipe, @@ -520,10 +520,10 @@ static int recvbuf2recvframe(struct adapter *padapter, struct recv_buf *precvbuf } _rtw_init_listhead(&precvframe->u.hdr.list); - precvframe->u.hdr.precvbuf = NULL; //can't access the precvbuf for new arch. + precvframe->u.hdr.precvbuf = NULL; /* can't access the precvbuf for new arch. */ precvframe->u.hdr.len=0; - //rtl8192c_query_rx_desc_status(precvframe, prxstat); + /* rtl8192c_query_rx_desc_status(precvframe, prxstat); */ update_recvframe_attrib_88e(precvframe, prxstat); pattrib = &precvframe->u.hdr.attrib; @@ -552,9 +552,9 @@ static int recvbuf2recvframe(struct adapter *padapter, struct recv_buf *precvbuf goto _exit_recvbuf2recvframe; } - // Modified by Albert 20101213 - // For 8 bytes IP header alignment. - if (pattrib->qos) // Qos data, wireless lan header length is 26 + /* Modified by Albert 20101213 */ + /* For 8 bytes IP header alignment. */ + if (pattrib->qos) /* Qos data, wireless lan header length is 26 */ { shift_sz = 6; } @@ -565,10 +565,9 @@ static int recvbuf2recvframe(struct adapter *padapter, struct recv_buf *precvbuf skb_len = pattrib->pkt_len; - // for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. - // modify alloc_sz for recvive crc error packet by thomas 2011-06-02 + /* for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. */ + /* modify alloc_sz for recvive crc error packet by thomas 2011-06-02 */ if ((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){ - //alloc_sz = 1664; //1664 is 128 alignment. if (skb_len <= 1650) alloc_sz = 1664; else @@ -576,8 +575,8 @@ static int recvbuf2recvframe(struct adapter *padapter, struct recv_buf *precvbuf } else { alloc_sz = skb_len; - // 6 is for IP header 8 bytes alignment in QoS packet case. - // 8 is for skb->data 4 bytes alignment. + /* 6 is for IP header 8 bytes alignment in QoS packet case. */ + /* 8 is for skb->data 4 bytes alignment. */ alloc_sz += 14; } @@ -589,17 +588,17 @@ static int recvbuf2recvframe(struct adapter *padapter, struct recv_buf *precvbuf precvframe->u.hdr.pkt = pkt_copy; precvframe->u.hdr.rx_head = pkt_copy->data; precvframe->u.hdr.rx_end = pkt_copy->data + alloc_sz; - skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));//force pkt_copy->data at 8-byte alignment address - skb_reserve( pkt_copy, shift_sz );//force ip_hdr at 8-byte alignment address according to shift_sz. + skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));/* force pkt_copy->data at 8-byte alignment address */ + skb_reserve( pkt_copy, shift_sz );/* force ip_hdr at 8-byte alignment address according to shift_sz. */ memcpy(pkt_copy->data, (pbuf + pattrib->drvinfo_sz + RXDESC_SIZE), skb_len); precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data; } else { DBG_8192C("recvbuf2recvframe:can not allocate memory for skb copy\n"); - //precvframe->u.hdr.pkt = rtw_skb_clone(pskb); - //precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pbuf; - //precvframe->u.hdr.rx_end = pbuf + (pkt_offset>1612?pkt_offset:1612); + /* precvframe->u.hdr.pkt = rtw_skb_clone(pskb); */ + /* precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pbuf; */ + /* precvframe->u.hdr.rx_end = pbuf + (pkt_offset>1612?pkt_offset:1612); */ precvframe->u.hdr.pkt = NULL; rtw_free_recvframe(precvframe, pfree_recv_queue); @@ -608,7 +607,7 @@ static int recvbuf2recvframe(struct adapter *padapter, struct recv_buf *precvbuf } recvframe_put(precvframe, skb_len); - //recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE); + /* recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE); */ #ifdef CONFIG_USB_RX_AGGREGATION switch(pHalData->UsbRxAggMode) @@ -626,7 +625,7 @@ static int recvbuf2recvframe(struct adapter *padapter, struct recv_buf *precvbuf } #endif - if (pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet + if (pattrib->pkt_rpt_type == NORMAL_RX)/* Normal rx packet */ { if (pattrib->physt) update_recvframe_phyinfo_88e(precvframe, (struct phy_stat*)pphy_status); @@ -636,17 +635,17 @@ static int recvbuf2recvframe(struct adapter *padapter, struct recv_buf *precvbuf ("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n")); } - } else{ // pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP + } else{ /* pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP */ - //enqueue recvframe to txrtp queue + /* enqueue recvframe to txrtp queue */ if (pattrib->pkt_rpt_type == TX_REPORT1){ - //DBG_8192C("rx CCX \n"); - //CCX-TXRPT ack for xmit mgmt frames. + /* DBG_8192C("rx CCX \n"); */ + /* CCX-TXRPT ack for xmit mgmt frames. */ handle_txrpt_ccx_88e(padapter, precvframe->u.hdr.rx_data); } else if (pattrib->pkt_rpt_type == TX_REPORT2){ - //DBG_8192C("rx TX RPT \n"); + /* DBG_8192C("rx TX RPT \n"); */ ODM_RA_TxRPT2Handle_8188E( &pHalData->odmpriv, precvframe->u.hdr.rx_data, @@ -658,7 +657,7 @@ static int recvbuf2recvframe(struct adapter *padapter, struct recv_buf *precvbuf } else if (pattrib->pkt_rpt_type == HIS_REPORT) { - //DBG_8192C("%s , rx USB HISR \n",__FUNCTION__); + /* DBG_8192C("%s , rx USB HISR \n",__FUNCTION__); */ #ifdef CONFIG_SUPPORT_USB_INT interrupt_handler_8188eu(padapter,pattrib->pkt_len,precvframe->u.hdr.rx_data); #endif @@ -724,7 +723,7 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) goto exit; } - if (purb->status==0)//SUCCESS + if (purb->status==0)/* SUCCESS */ { if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)) { @@ -738,7 +737,7 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) precvbuf->transfer_len = purb->actual_length; - //rtw_enqueue_rx_transfer_buffer(precvpriv, rx_transfer_buf); + /* rtw_enqueue_rx_transfer_buffer(precvpriv, rx_transfer_buf); */ rtw_enqueue_recvbuf(precvbuf, &precvpriv->recv_buf_pending_queue); tasklet_schedule(&precvpriv->recv_tasklet); @@ -759,7 +758,7 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) case -EPIPE: case -ENODEV: case -ESHUTDOWN: - //padapter->bSurpriseRemoved=true; + /* padapter->bSurpriseRemoved=true; */ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=TRUE\n")); case -ENOENT: padapter->bDriverStopped=true; @@ -823,14 +822,14 @@ static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) purb = precvbuf->purb; - //translate DMA FIFO addr to pipehandle + /* translate DMA FIFO addr to pipehandle */ pipe = ffaddr2pipehdl(pdvobj, addr); usb_fill_bulk_urb(purb, pusbd, pipe, precvbuf->pbuf, MAX_RECVBUF_SZ, usb_read_port_complete, - precvbuf);//context is precvbuf + precvbuf);/* context is precvbuf */ purb->transfer_dma = precvbuf->dma_transfer_addr; purb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; @@ -856,7 +855,7 @@ static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) return ret; } -#else // CONFIG_USE_USB_BUFFER_ALLOC_RX +#else /* CONFIG_USE_USB_BUFFER_ALLOC_RX */ static int recvbuf2recvframe(struct adapter *padapter, _pkt *pskb) { u8 *pbuf; @@ -896,10 +895,10 @@ static int recvbuf2recvframe(struct adapter *padapter, _pkt *pskb) } _rtw_init_listhead(&precvframe->u.hdr.list); - precvframe->u.hdr.precvbuf = NULL; //can't access the precvbuf for new arch. + precvframe->u.hdr.precvbuf = NULL; /* can't access the precvbuf for new arch. */ precvframe->u.hdr.len=0; - //rtl8192c_query_rx_desc_status(precvframe, prxstat); + /* rtl8192c_query_rx_desc_status(precvframe, prxstat); */ update_recvframe_attrib_88e(precvframe, prxstat); pattrib = &precvframe->u.hdr.attrib; @@ -927,9 +926,9 @@ static int recvbuf2recvframe(struct adapter *padapter, _pkt *pskb) goto _exit_recvbuf2recvframe; } - // Modified by Albert 20101213 - // For 8 bytes IP header alignment. - if (pattrib->qos) // Qos data, wireless lan header length is 26 + /* Modified by Albert 20101213 */ + /* For 8 bytes IP header alignment. */ + if (pattrib->qos) /* Qos data, wireless lan header length is 26 */ { shift_sz = 6; } @@ -940,10 +939,9 @@ static int recvbuf2recvframe(struct adapter *padapter, _pkt *pskb) skb_len = pattrib->pkt_len; - // for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. - // modify alloc_sz for recvive crc error packet by thomas 2011-06-02 + /* for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. */ + /* modify alloc_sz for recvive crc error packet by thomas 2011-06-02 */ if ((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){ - //alloc_sz = 1664; //1664 is 128 alignment. if (skb_len <= 1650) alloc_sz = 1664; else @@ -951,8 +949,8 @@ static int recvbuf2recvframe(struct adapter *padapter, _pkt *pskb) } else { alloc_sz = skb_len; - // 6 is for IP header 8 bytes alignment in QoS packet case. - // 8 is for skb->data 4 bytes alignment. + /* 6 is for IP header 8 bytes alignment in QoS packet case. */ + /* 8 is for skb->data 4 bytes alignment. */ alloc_sz += 14; } @@ -964,8 +962,8 @@ static int recvbuf2recvframe(struct adapter *padapter, _pkt *pskb) precvframe->u.hdr.pkt = pkt_copy; precvframe->u.hdr.rx_head = pkt_copy->data; precvframe->u.hdr.rx_end = pkt_copy->data + alloc_sz; - skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));//force pkt_copy->data at 8-byte alignment address - skb_reserve( pkt_copy, shift_sz );//force ip_hdr at 8-byte alignment address according to shift_sz. + skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));/* force pkt_copy->data at 8-byte alignment address */ + skb_reserve( pkt_copy, shift_sz );/* force ip_hdr at 8-byte alignment address according to shift_sz. */ memcpy(pkt_copy->data, (pbuf + pattrib->drvinfo_sz + RXDESC_SIZE), skb_len); precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data; } @@ -995,7 +993,7 @@ static int recvbuf2recvframe(struct adapter *padapter, _pkt *pskb) } recvframe_put(precvframe, skb_len); - //recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE); + /* recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE); */ #ifdef CONFIG_USB_RX_AGGREGATION switch(pHalData->UsbRxAggMode) @@ -1013,7 +1011,7 @@ static int recvbuf2recvframe(struct adapter *padapter, _pkt *pskb) } #endif - if (pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet + if (pattrib->pkt_rpt_type == NORMAL_RX)/* Normal rx packet */ { if (pattrib->physt) update_recvframe_phyinfo_88e(precvframe, (struct phy_stat*)pphy_status); @@ -1022,15 +1020,15 @@ static int recvbuf2recvframe(struct adapter *padapter, _pkt *pskb) RT_TRACE(_module_rtl871x_recv_c_,_drv_err_, ("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n")); } - } else{ // pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP - //enqueue recvframe to txrtp queue + } else{ /* pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP */ + /* enqueue recvframe to txrtp queue */ if (pattrib->pkt_rpt_type == TX_REPORT1){ - //DBG_8192C("rx CCX \n"); - //CCX-TXRPT ack for xmit mgmt frames. + /* DBG_8192C("rx CCX \n"); */ + /* CCX-TXRPT ack for xmit mgmt frames. */ handle_txrpt_ccx_88e(padapter, precvframe->u.hdr.rx_data); } else if (pattrib->pkt_rpt_type == TX_REPORT2){ - //DBG_8192C("rx TX RPT \n"); + /* DBG_8192C("rx TX RPT \n"); */ ODM_RA_TxRPT2Handle_8188E( &pHalData->odmpriv, precvframe->u.hdr.rx_data, @@ -1042,7 +1040,7 @@ static int recvbuf2recvframe(struct adapter *padapter, _pkt *pskb) } else if (pattrib->pkt_rpt_type == HIS_REPORT) { - //DBG_8192C("%s , rx USB HISR \n",__FUNCTION__); + /* DBG_8192C("%s , rx USB HISR \n",__FUNCTION__); */ #ifdef CONFIG_SUPPORT_USB_INT interrupt_handler_8188eu(padapter,pattrib->pkt_len,precvframe->u.hdr.rx_data); #endif @@ -1111,18 +1109,18 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete!!!\n")); - //_enter_critical(&precvpriv->lock, &irqL); - //precvbuf->irp_pending=false; - //precvpriv->rx_pending_cnt --; - //_exit_critical(&precvpriv->lock, &irqL); + /* _enter_critical(&precvpriv->lock, &irqL); */ + /* precvbuf->irp_pending=false; */ + /* precvpriv->rx_pending_cnt --; */ + /* _exit_critical(&precvpriv->lock, &irqL); */ precvpriv->rx_pending_cnt --; - //if (precvpriv->rx_pending_cnt== 0) - //{ - // RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: rx_pending_cnt== 0, set allrxreturnevt!\n")); - // _rtw_up_sema(&precvpriv->allrxreturnevt); - //} + /* if (precvpriv->rx_pending_cnt== 0) */ + /* */ + /* RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: rx_pending_cnt== 0, set allrxreturnevt!\n")); */ + /* _rtw_up_sema(&precvpriv->allrxreturnevt); */ + /* */ if (padapter->bSurpriseRemoved || padapter->bDriverStopped||padapter->bReadPortCancel) { @@ -1141,7 +1139,7 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) goto exit; } - if (purb->status==0)//SUCCESS + if (purb->status==0)/* SUCCESS */ { if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)) { @@ -1181,7 +1179,7 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) case -EPIPE: case -ENODEV: case -ESHUTDOWN: - //padapter->bSurpriseRemoved=true; + /* padapter->bSurpriseRemoved=true; */ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=TRUE\n")); case -ENOENT: padapter->bDriverStopped=true; @@ -1253,7 +1251,7 @@ static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) if (precvbuf != NULL) { rtl8188eu_init_recvbuf(adapter, precvbuf); - //re-assign for linux based on skb + /* re-assign for linux based on skb */ if ((precvbuf->reuse == false) || (precvbuf->pskb == NULL)) { precvbuf->pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ); @@ -1272,7 +1270,7 @@ static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) precvbuf->ptail = skb_tail_pointer(precvbuf->pskb); precvbuf->pend = skb_end_pointer(precvbuf->pskb); precvbuf->pbuf = precvbuf->pskb->data; - } else//reuse skb + } else/* reuse skb */ { precvbuf->phead = precvbuf->pskb->head; precvbuf->pdata = precvbuf->pskb->data; @@ -1287,12 +1285,12 @@ static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) purb = precvbuf->purb; - //translate DMA FIFO addr to pipehandle + /* translate DMA FIFO addr to pipehandle */ pipe = ffaddr2pipehdl(pdvobj, addr); usb_fill_bulk_urb(purb, pusbd, pipe, precvbuf->pbuf, MAX_RECVBUF_SZ, usb_read_port_complete, - precvbuf);//context is precvbuf + precvbuf);/* context is precvbuf */ err = usb_submit_urb(purb, GFP_ATOMIC); if ((err) && (err != (-EPERM))) { @@ -1309,7 +1307,7 @@ static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) } return ret; } -#endif // CONFIG_USE_USB_BUFFER_ALLOC_RX +#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */ void rtl8188eu_xmit_tasklet(void *priv) {