skyfall/rtl8188eu
1
0
Fork 0
mirror of https://github.com/lwfinger/rtl8188eu.git synced 2025-05-08 14:33:05 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

rtl8188eu: Change all "if(" to "if ("

Browse source 
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2015-08-15 13:02:34 -05:00
parent aa89a39a09
commit 6ead3e77dc
61 changed files with 3500 additions and 3500 deletions
Download patch file Download diff file Expand all files Collapse all files

76
hal/Hal8188ERateAdaptive.c
View file

@ -113,7 +113,7 @@ odm_SetTxRPTTiming_8188E(
u8 idx = 0;
for(idx=0; idx<5; idx++)
if(DynamicTxRPTTiming[idx] == pRaInfo->RptTime)
if (DynamicTxRPTTiming[idx] == pRaInfo->RptTime)
break;
if (extend==0) /* back to default timing */
@ -124,7 +124,7 @@ odm_SetTxRPTTiming_8188E(
idx=5;
}
else if (extend==2) {/* decrease the timing */
if(idx!=0)
if (idx!=0)
idx-=1;
}
pRaInfo->RptTime=DynamicTxRPTTiming[idx];
@ -142,7 +142,7 @@ odm_RateDown_8188E(
u8 i;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateDown_8188E()\n"));
if(NULL == pRaInfo)
if (NULL == pRaInfo)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateDown_8188E(): pRaInfo is NULL\n"));
return -1;
@ -158,7 +158,7 @@ odm_RateDown_8188E(
{
RateID=HighestRate;
}
else if(pRaInfo->RateSGI)
else if (pRaInfo->RateSGI)
{
pRaInfo->RateSGI=0;
}
@ -186,14 +186,14 @@ RateDownFinish:
pRaInfo->RAWaitingCounter+=1;
pRaInfo->RAPendingCounter+=1;
}
else if(pRaInfo->RAWaitingCounter==0){
else if (pRaInfo->RAWaitingCounter==0){
}
else{
pRaInfo->RAWaitingCounter=0;
pRaInfo->RAPendingCounter=0;
}
if(pRaInfo->RAPendingCounter>=4)
if (pRaInfo->RAPendingCounter>=4)
pRaInfo->RAPendingCounter=4;
pRaInfo->DecisionRate=RateID;
@ -215,7 +215,7 @@ odm_RateUp_8188E(
u8 i;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateUp_8188E()\n"));
if(NULL == pRaInfo)
if (NULL == pRaInfo)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateUp_8188E(): pRaInfo is NULL\n"));
return -1;
@ -247,21 +247,21 @@ odm_RateUp_8188E(
}
}
}
else if(RateID == HighestRate)
else if (RateID == HighestRate)
{
if (pRaInfo->SGIEnable && (pRaInfo->RateSGI != 1))
pRaInfo->RateSGI = 1;
else if((pRaInfo->SGIEnable) !=1 )
else if ((pRaInfo->SGIEnable) !=1 )
pRaInfo->RateSGI = 0;
}
else /* if((sta_info_ra->Decision_rate) > (sta_info_ra->Highest_rate)) */
else /* if ((sta_info_ra->Decision_rate) > (sta_info_ra->Highest_rate)) */
{
RateID = HighestRate;
}
RateUpfinish:
/* if(pRaInfo->RAWaitingCounter==10) */
if(pRaInfo->RAWaitingCounter==(4+PendingForRateUpFail[pRaInfo->RAPendingCounter]))
/* if (pRaInfo->RAWaitingCounter==10) */
if (pRaInfo->RAWaitingCounter==(4+PendingForRateUpFail[pRaInfo->RAPendingCounter]))
pRaInfo->RAWaitingCounter=0;
else
pRaInfo->RAWaitingCounter++;
@ -351,7 +351,7 @@ odm_RateDecision_8188E(
else if (pRaInfo->NscUp > N_THRESHOLD_HIGH[RateID])
odm_RateUp_8188E(pDM_Odm,pRaInfo);
if(pRaInfo->DecisionRate > pRaInfo->HighestRate)
if (pRaInfo->DecisionRate > pRaInfo->HighestRate)
pRaInfo->DecisionRate = pRaInfo->HighestRate;
if ((pRaInfo->DecisionRate)==(pRaInfo->PreRate))
@ -428,7 +428,7 @@ odm_ARFBRefresh_8188E(
if (pRaInfo->RAUseRate){
for (i=RATESIZE;i>=0;i--)
{
if((pRaInfo->RAUseRate)&BIT(i)){
if ((pRaInfo->RAUseRate)&BIT(i)){
pRaInfo->HighestRate=i;
break;
}
@ -441,7 +441,7 @@ odm_ARFBRefresh_8188E(
if (pRaInfo->RAUseRate){
for (i=0;i<RATESIZE;i++)
{
if((pRaInfo->RAUseRate)&BIT(i))
if ((pRaInfo->RAUseRate)&BIT(i))
{
pRaInfo->LowestRate=i;
break;
@ -455,9 +455,9 @@ odm_ARFBRefresh_8188E(
#if POWER_TRAINING_ACTIVE == 1
if (pRaInfo->HighestRate >0x13)
pRaInfo->PTModeSS=3;
else if(pRaInfo->HighestRate >0x0b)
else if (pRaInfo->HighestRate >0x0b)
pRaInfo->PTModeSS=2;
else if(pRaInfo->HighestRate >0x0b)
else if (pRaInfo->HighestRate >0x0b)
pRaInfo->PTModeSS=1;
else
pRaInfo->PTModeSS=0;
@ -466,7 +466,7 @@ odm_ARFBRefresh_8188E(
#endif
if(pRaInfo->DecisionRate > pRaInfo->HighestRate)
if (pRaInfo->DecisionRate > pRaInfo->HighestRate)
pRaInfo->DecisionRate = pRaInfo->HighestRate;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD,
@ -515,7 +515,7 @@ odm_PTTryState_8188E(
{
if (pRaInfo->PTStage==0)
pRaInfo->PTStage=1;
else if(pRaInfo->PTStage==1)
else if (pRaInfo->PTStage==1)
pRaInfo->PTStage=3;
else
pRaInfo->PTStage=5;
@ -554,7 +554,7 @@ odm_PTDecision_8188E(
for(j=0;j<=4;j++)
{
numsc += pRaInfo->RTY[j] * PT_PENALTY[j];
if(numsc>num_total)
if (numsc>num_total)
break;
}
@ -588,7 +588,7 @@ odm_RATxRPTTimerSetting(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,(" =====>odm_RATxRPTTimerSetting()\n"));
if(pDM_Odm->CurrminRptTime != minRptTime){
if (pDM_Odm->CurrminRptTime != minRptTime){
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD,
(" CurrminRptTime =0x%04x minRptTime=0x%04x\n", pDM_Odm->CurrminRptTime, minRptTime));
rtw_rpt_timer_cfg_cmd(pDM_Odm->Adapter,minRptTime);
@ -622,16 +622,16 @@ ODM_RAInfo_Init(
PODM_RA_INFO_T pRaInfo = &pDM_Odm->RAInfo[MacID];
u8 WirelessMode=0xFF; /* invalid value */
u8 max_rate_idx = 0x13; /* MCS7 */
if(pDM_Odm->pWirelessMode!=NULL){
if (pDM_Odm->pWirelessMode!=NULL){
WirelessMode=*(pDM_Odm->pWirelessMode);
}
if(WirelessMode != 0xFF ){
if(WirelessMode & ODM_WM_N24G)
if (WirelessMode != 0xFF ){
if (WirelessMode & ODM_WM_N24G)
max_rate_idx = 0x13;
else if(WirelessMode & ODM_WM_G)
else if (WirelessMode & ODM_WM_G)
max_rate_idx = 0x0b;
else if(WirelessMode & ODM_WM_B)
else if (WirelessMode & ODM_WM_B)
max_rate_idx = 0x03;
}
@ -702,7 +702,7 @@ ODM_RA_GetShortGI_8188E(
u8 MacID
)
{
if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM))
if ((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM))
return 0;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,
("MacID=%d SGI=%d\n", MacID, pDM_Odm->RAInfo[MacID].RateSGI));
@ -717,7 +717,7 @@ ODM_RA_GetDecisionRate_8188E(
{
u8 DecisionRate = 0;
if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM))
if ((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM))
return 0;
DecisionRate = (pDM_Odm->RAInfo[MacID].DecisionRate);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,
@ -732,7 +732,7 @@ ODM_RA_GetHwPwrStatus_8188E(
)
{
u8 PTStage = 5;
if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM))
if ((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM))
return 0;
PTStage = (pDM_Odm->RAInfo[MacID].PTStage);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,
@ -754,7 +754,7 @@ ODM_RA_UpdateRateInfo_8188E(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD,
("MacID=%d RateID=0x%x RateMask=0x%x SGIEnable=%d\n",
MacID, RateID, RateMask, SGIEnable));
if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM))
if ((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM))
return;
pRaInfo = &(pDM_Odm->RAInfo[MacID]);
@ -775,7 +775,7 @@ ODM_RA_SetRSSI_8188E(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,
(" MacID=%d Rssi=%d\n", MacID, Rssi));
if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM))
if ((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM))
return;
pRaInfo = &(pDM_Odm->RAInfo[MacID]);
@ -815,15 +815,15 @@ ODM_RA_TxRPT2Handle_8188E(
do
{
if(MacId >= ASSOCIATE_ENTRY_NUM)
if (MacId >= ASSOCIATE_ENTRY_NUM)
valid = 0;
else if(MacId >= 32)
else if (MacId >= 32)
valid = (1<<(MacId-32)) & MacIDValidEntry1;
else
valid = (1<<MacId) & MacIDValidEntry0;
pRAInfo = &(pDM_Odm->RAInfo[MacId]);
if(valid)
if (valid)
{
pRAInfo->RTY[0] = (u16)GET_TX_REPORT_TYPE1_RERTY_0(pBuffer);
@ -839,7 +839,7 @@ ODM_RA_TxRPT2Handle_8188E(
pRAInfo->RTY[3] + \
pRAInfo->RTY[4] + \
pRAInfo->DROP;
if(pRAInfo->TOTAL != 0)
if (pRAInfo->TOTAL != 0)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD,
("macid=%d Total=%d R0=%d R1=%d R2=%d R3=%d R4=%d D0=%d valid0=%x valid1=%x\n",
@ -855,10 +855,10 @@ ODM_RA_TxRPT2Handle_8188E(
MacIDValidEntry1));
#if POWER_TRAINING_ACTIVE == 1
if (pRAInfo->PTActive){
if(pRAInfo->RAstage<5){
if (pRAInfo->RAstage<5){
odm_RateDecision_8188E(pDM_Odm,pRAInfo);
}
else if(pRAInfo->RAstage==5){ /* Power training try state */
else if (pRAInfo->RAstage==5){ /* Power training try state */
odm_PTTryState_8188E(pRAInfo);
}
else {/* RAstage==6 */
@ -895,7 +895,7 @@ ODM_RA_TxRPT2Handle_8188E(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, (" TOTAL=0!!!!\n"));
}
if(minRptTime > pRAInfo->RptTime)
if (minRptTime > pRAInfo->RptTime)
minRptTime = pRAInfo->RptTime;
pBuffer += TX_RPT2_ITEM_SIZE;

4
hal/HalPhyRf.c
View file

@ -63,11 +63,11 @@ u8 ODM_GetRightChnlPlaceforIQK(u8 chnl)
u8 place = chnl;
if(chnl > 14)
if (chnl > 14)
{
for(place = 14; place<sizeof(channel_all); place++)
{
if(channel_all[place] == chnl)
if (channel_all[place] == chnl)
{
return place-13;
}

192
hal/HalPhyRf_8188e.c
View file

@ -31,14 +31,14 @@
do {\
for(_offset = 0; _offset < _size; _offset++)\
{\
if(_deltaThermal < thermalThreshold[_direction][_offset])\
if (_deltaThermal < thermalThreshold[_direction][_offset])\
{\
if(_offset != 0)\
if (_offset != 0)\
_offset--;\
break;\
}\
} \
if(_offset >= _size)\
if (_offset >= _size)\
_offset = _size-1;\
} while(0)
@ -57,14 +57,14 @@ static void setIqkMatrix(
/* printk("%s==> OFDM_index:%d\n",__FUNCTION__,OFDM_index); */
/* if(OFDM_index> OFDM_TABLE_SIZE_92D) */
/* if (OFDM_index> OFDM_TABLE_SIZE_92D) */
/* */
/* printk("%s==> OFDM_index> 43\n",__FUNCTION__); */
/* */
ele_D = (OFDMSwingTable[OFDM_index] & 0xFFC00000)>>22;
/* new element A = element D x X */
if((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G))
if ((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G))
{
if ((IqkResult_X & 0x00000200) != 0) /* consider minus */
IqkResult_X = IqkResult_X | 0xFFFFFC00;
@ -290,7 +290,7 @@ odm_TxPwrTrackSetPwr88E(
}
else if (Method == BBSWING)
{
if(* (pDM_Odm->pChannel) < 14)
if (* (pDM_Odm->pChannel) < 14)
{
ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13[pDM_Odm->BbSwingIdxCck][0]);
ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13[pDM_Odm->BbSwingIdxCck][1]);
@ -386,13 +386,13 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
/* 4 3. Initialize ThermalValues of RFCalibrateInfo */
if( ! pDM_Odm->RFCalibrateInfo.ThermalValue)
if ( ! pDM_Odm->RFCalibrateInfo.ThermalValue)
{
pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue;
pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue;
}
if(pDM_Odm->RFCalibrateInfo.bReloadtxpowerindex)
if (pDM_Odm->RFCalibrateInfo.bReloadtxpowerindex)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n"));
}
@ -401,19 +401,19 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue;
pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++;
if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == AVG_THERMAL_NUM_88E)
if (pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == AVG_THERMAL_NUM_88E)
pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0;
for(i = 0; i < AVG_THERMAL_NUM_88E; i++)
{
if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i])
if (pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i])
{
ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i];
ThermalValue_AVG_count++;
}
}
if(ThermalValue_AVG_count)
if (ThermalValue_AVG_count)
{
ThermalValue = (u8)(ThermalValue_AVG / ThermalValue_AVG_count);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("AVG Thermal Meter = 0x%x\n", ThermalValue));
@ -427,7 +427,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
/* 4 6. If necessary, do LCK. */
/* if((delta_LCK > pHalData->Delta_LCK) && (pHalData->Delta_LCK != 0)) */
/* if ((delta_LCK > pHalData->Delta_LCK) && (pHalData->Delta_LCK != 0)) */
if ((delta_LCK >= 8)) /* Delta temperature is equal to or larger than 20 centigrade. */
{
pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue;
@ -442,7 +442,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
/* 4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset */
if(ThermalValue > pHalData->EEPROMThermalMeter) {
if (ThermalValue > pHalData->EEPROMThermalMeter) {
CALCULATE_SWINGTALBE_OFFSET(offset, POWER_INC, index_mapping_NUM_88E, delta);
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex;
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex = -1 * deltaSwingTableIdx[POWER_INC][offset];
@ -473,7 +473,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
for(i = 0; i < rf; i++) {
if(pDM_Odm->RFCalibrateInfo.OFDM_index[i] > OFDM_TABLE_SIZE_92D-1)
if (pDM_Odm->RFCalibrateInfo.OFDM_index[i] > OFDM_TABLE_SIZE_92D-1)
{
pDM_Odm->RFCalibrateInfo.OFDM_index[i] = OFDM_TABLE_SIZE_92D-1;
}
@ -483,7 +483,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
}
}
if(pDM_Odm->RFCalibrateInfo.CCK_index > CCK_TABLE_SIZE-1)
if (pDM_Odm->RFCalibrateInfo.CCK_index > CCK_TABLE_SIZE-1)
pDM_Odm->RFCalibrateInfo.CCK_index = CCK_TABLE_SIZE-1;
} else {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
@ -528,7 +528,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Temperature(%d) lower than PG value(%d), increases the power by TxAGC\n", ThermalValue, pHalData->EEPROMThermalMeter));
odm_TxPwrTrackSetPwr88E(pDM_Odm, BBSWING, RF_PATH_A, Indexforchannel);
/* if(is2T) */
/* if (is2T) */
/* odm_TxPwrTrackSetPwr88E(pDM_Odm, BBSWING, RF_PATH_B, Indexforchannel); */
}
@ -538,7 +538,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
}
/* if((delta_IQK > pHalData->Delta_IQK) && (pHalData->Delta_IQK != 0)) */
/* if ((delta_IQK > pHalData->Delta_IQK) && (pHalData->Delta_IQK != 0)) */
if ((delta_IQK >= 8)){ /* Delta temperature is equal to or larger than 20 centigrade. */
/* printk("delta_IQK(%d) >=8 do_IQK\n",delta_IQK); */
doIQK(pDM_Odm, delta_IQK, ThermalValue, 8);
@ -602,7 +602,7 @@ phy_PathA_IQK_8188E(
regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4));
if(!(regEAC & BIT28) &&
if (!(regEAC & BIT28) &&
(((regE94 & 0x03FF0000)>>16) != 0x142) &&
(((regE9C & 0x03FF0000)>>16) != 0x42) )
result |= 0x01;
@ -671,7 +671,7 @@ phy_PathA_RxIQK(
regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C));
if(!(regEAC & BIT28) &&
if (!(regEAC & BIT28) &&
(((regE94 & 0x03FF0000)>>16) != 0x142) &&
(((regE9C & 0x03FF0000)>>16) != 0x42) )
{
@ -738,7 +738,7 @@ phy_PathA_RxIQK(
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180 );
if(!(regEAC & BIT27) && /* if Tx is OK, check whether Rx is OK */
if (!(regEAC & BIT27) && /* if Tx is OK, check whether Rx is OK */
(((regEA4 & 0x03FF0000)>>16) != 0x132) &&
(((regEAC & 0x03FF0000)>>16) != 0x36))
result |= 0x02;
@ -781,14 +781,14 @@ phy_PathB_IQK_8188E(
regECC= ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xecc = 0x%x\n", regECC));
if(!(regEAC & BIT31) &&
if (!(regEAC & BIT31) &&
(((regEB4 & 0x03FF0000)>>16) != 0x142) &&
(((regEBC & 0x03FF0000)>>16) != 0x42))
result |= 0x01;
else
return result;
if(!(regEAC & BIT30) &&
if (!(regEAC & BIT30) &&
(((regEC4 & 0x03FF0000)>>16) != 0x132) &&
(((regECC & 0x03FF0000)>>16) != 0x36))
result |= 0x02;
@ -815,10 +815,10 @@ _PHY_PathAFillIQKMatrix(
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed"));
if(final_candidate == 0xFF)
if (final_candidate == 0xFF)
return;
else if(bIQKOK)
else if (bIQKOK)
{
Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
@ -843,7 +843,7 @@ _PHY_PathAFillIQKMatrix(
ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1));
if(bTxOnly)
if (bTxOnly)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix only Tx OK\n"));
return;
@ -875,10 +875,10 @@ _PHY_PathBFillIQKMatrix(
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed"));
if(final_candidate == 0xFF)
if (final_candidate == 0xFF)
return;
else if(bIQKOK)
else if (bIQKOK)
{
Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
@ -902,7 +902,7 @@ _PHY_PathBFillIQKMatrix(
ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1));
if(bTxOnly)
if (bTxOnly)
return;
reg = result[final_candidate][6];
@ -1022,7 +1022,7 @@ _PHY_PathADDAOn(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n"));
pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4;
if(false == is2T){
if (false == is2T){
pathOn = 0x0bdb25a0;
ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0b1b25a0);
}
@ -1106,12 +1106,12 @@ phy_SimularityCompare_8188E(
bool is2T;
s32 tmp1 = 0,tmp2 = 0;
if( (pDM_Odm->RFType ==ODM_2T2R )||(pDM_Odm->RFType ==ODM_2T3R )||(pDM_Odm->RFType ==ODM_2T4R ))
if ( (pDM_Odm->RFType ==ODM_2T2R )||(pDM_Odm->RFType ==ODM_2T3R )||(pDM_Odm->RFType ==ODM_2T4R ))
is2T = true;
else
is2T = false;
if(is2T)
if (is2T)
bound = 8;
else
bound = 4;
@ -1126,14 +1126,14 @@ phy_SimularityCompare_8188E(
for( i = 0; i < bound; i++ )
{
/* diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); */
if((i==1) || (i==3) || (i==5) || (i==7))
if ((i==1) || (i==3) || (i==5) || (i==7))
{
if((result[c1][i]& 0x00000200) != 0)
if ((result[c1][i]& 0x00000200) != 0)
tmp1 = result[c1][i] | 0xFFFFFC00;
else
tmp1 = result[c1][i];
if((result[c2][i]& 0x00000200) != 0)
if ((result[c2][i]& 0x00000200) != 0)
tmp2 = result[c2][i] | 0xFFFFFC00;
else
tmp2 = result[c2][i];
@ -1150,9 +1150,9 @@ phy_SimularityCompare_8188E(
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8188E differnece overflow index %d compare1 0x%x compare2 0x%x!!!\n", i, result[c1][i], result[c2][i]));
if((i == 2 || i == 6) && !SimularityBitMap)
if ((i == 2 || i == 6) && !SimularityBitMap)
{
if(result[c1][i]+result[c1][i+1] == 0)
if (result[c1][i]+result[c1][i+1] == 0)
final_candidate[(i/4)] = c2;
else if (result[c2][i]+result[c2][i+1] == 0)
final_candidate[(i/4)] = c1;
@ -1170,7 +1170,7 @@ phy_SimularityCompare_8188E(
{
for( i = 0; i < (bound/4); i++ )
{
if(final_candidate[i] != 0xFF)
if (final_candidate[i] != 0xFF)
{
for( j = i*4; j < (i+1)*4-2; j++)
result[3][j] = result[final_candidate[i]][j];
@ -1256,7 +1256,7 @@ else
/* Note: IQ calibration must be performed after loading */
/* PHY_REG.txt , and radio_a, radio_b.txt */
if(t==0) {
if (t==0) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));
/* Save ADDA parameters, turn Path A ADDA on */
@ -1268,11 +1268,11 @@ else
_PHY_PathADDAOn(pAdapter, ADDA_REG, true, is2T);
if(t==0) {
if (t==0) {
pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u8)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8));
}
if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){
if (!pDM_Odm->RFCalibrateInfo.bRfPiEnable){
/* Switch BB to PI mode to do IQ Calibration. */
_PHY_PIModeSwitch(pAdapter, true);
}
@ -1290,7 +1290,7 @@ else
ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00);
if(is2T)
if (is2T)
{
ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000);
ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000);
@ -1303,7 +1303,7 @@ else
/* AP or IQK */
ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
if(is2T)
if (is2T)
{
ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000);
}
@ -1316,7 +1316,7 @@ else
for(i = 0 ; i < retryCount ; i++){
PathAOK = phy_PathA_IQK_8188E(pAdapter, is2T);
if(PathAOK == 0x01){
if (PathAOK == 0x01){
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n"));
result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
@ -1326,7 +1326,7 @@ else
for(i = 0 ; i < retryCount ; i++){
PathAOK = phy_PathA_RxIQK(pAdapter, is2T);
if(PathAOK == 0x03){
if (PathAOK == 0x03){
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n"));
result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
@ -1336,11 +1336,11 @@ else
}
}
if(0x00 == PathAOK){
if (0x00 == PathAOK){
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n"));
}
if(is2T){
if (is2T){
_PHY_PathAStandBy(pAdapter);
/* Turn Path B ADDA on */
@ -1348,7 +1348,7 @@ else
for(i = 0 ; i < retryCount ; i++){
PathBOK = phy_PathB_IQK_8188E(pAdapter);
if(PathBOK == 0x03){
if (PathBOK == 0x03){
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK Success!!\n"));
result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16;
result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16;
@ -1364,7 +1364,7 @@ else
}
}
if(0x00 == PathBOK){
if (0x00 == PathBOK){
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n"));
}
}
@ -1373,8 +1373,8 @@ else
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n"));
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0);
if(t!=0) {
if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){
if (t!=0) {
if (!pDM_Odm->RFCalibrateInfo.bRfPiEnable){
/* Switch back BB to SI mode after finish IQ Calibration. */
_PHY_PIModeSwitch(pAdapter, false);
}
@ -1390,7 +1390,7 @@ else
/* Restore RX initial gain */
ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3);
if(is2T){
if (is2T){
ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3);
}
@ -1418,19 +1418,19 @@ phy_LCCalibrate_8188E(
/* Check continuous TX and Packet TX */
tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03);
if((tmpReg&0x70) != 0) /* Deal with contisuous TX case */
if ((tmpReg&0x70) != 0) /* Deal with contisuous TX case */
ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); /* disable all continuous TX */
else /* Deal with Packet TX case */
ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); /* block all queues */
if((tmpReg&0x70) != 0)
if ((tmpReg&0x70) != 0)
{
/* 1. Read original RF mode */
/* Path-A */
RF_Amode = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits);
/* Path-B */
if(is2T)
if (is2T)
RF_Bmode = PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits);
/* 2. Set RF mode = standby mode */
@ -1438,7 +1438,7 @@ phy_LCCalibrate_8188E(
ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000);
/* Path-B */
if(is2T)
if (is2T)
ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000);
}
@ -1452,14 +1452,14 @@ phy_LCCalibrate_8188E(
/* Restore original situation */
if((tmpReg&0x70) != 0) /* Deal with contisuous TX case */
if ((tmpReg&0x70) != 0) /* Deal with contisuous TX case */
{
/* Path-A */
ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg);
ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);
/* Path-B */
if(is2T)
if (is2T)
ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
}
else /* Deal with Packet TX case */
@ -1586,7 +1586,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R")));
if(!is2T)
if (!is2T)
pathbound = 1;
/* 2 FOR NORMAL CHIP SETTINGS */
@ -1616,7 +1616,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
/* save BB default value */
for(index = 0; index < APK_BB_REG_NUM ; index++) {
if(index == 0) /* skip */
if (index == 0) /* skip */
continue;
BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord);
}
@ -1631,7 +1631,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
{
if(path == RF_PATH_A)
if (path == RF_PATH_A)
{
/* path A APK */
/* load APK setting */
@ -1670,7 +1670,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
}
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
}
else if(path == RF_PATH_B)
else if (path == RF_PATH_B)
{
/* path B APK */
/* load APK setting */
@ -1720,12 +1720,12 @@ if ( *(pDM_Odm->mp_mode) == 1)
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord)));
/* BB to AP mode */
if(path == 0)
if (path == 0)
{
for(index = 0; index < APK_BB_REG_NUM ; index++)
{
if(index == 0) /* skip */
if (index == 0) /* skip */
continue;
else if (index < 5)
ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]);
@ -1750,7 +1750,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
/* MAC settings */
_PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup);
if(path == RF_PATH_A) /* Path B to standby mode */
if (path == RF_PATH_A) /* Path B to standby mode */
{
ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x10000);
}
@ -1762,7 +1762,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
}
delta_offset = ((delta+14)/2);
if(delta_offset < 0)
if (delta_offset < 0)
delta_offset = 0;
else if (delta_offset > 12)
delta_offset = 12;
@ -1770,15 +1770,15 @@ if ( *(pDM_Odm->mp_mode) == 1)
/* AP calibration */
for(index = 0; index < APK_BB_REG_NUM; index++)
{
if(index != 1) /* only DO PA11+PAD01001, AP RF setting */
if (index != 1) /* only DO PA11+PAD01001, AP RF setting */
continue;
tmpReg = APK_RF_init_value[path][index];
if(!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore)
if (!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore)
{
BB_offset = (tmpReg & 0xF0000) >> 16;
if(!(tmpReg & BIT15)) /* sign bit 0 */
if (!(tmpReg & BIT15)) /* sign bit 0 */
{
BB_offset = -BB_offset;
}
@ -1789,7 +1789,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset));
if(BB_offset < 0)
if (BB_offset < 0)
{
tmpReg = tmpReg & (~BIT15);
BB_offset = -BB_offset;
@ -1824,7 +1824,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
}
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
if(path == RF_PATH_A)
if (path == RF_PATH_A)
tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000);
else
tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000);
@ -1846,7 +1846,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
for(index = 0; index < APK_BB_REG_NUM ; index++)
{
if(index == 0) /* skip */
if (index == 0) /* skip */
continue;
ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]);
}
@ -1858,7 +1858,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
for(path = 0; path < pathbound; path++)
{
ODM_SetRFReg(pDM_Odm, path, 0xd, bMaskDWord, regD[path]);
if(path == RF_PATH_B)
if (path == RF_PATH_B)
{
ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);
ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101);
@ -1877,13 +1877,13 @@ if ( *(pDM_Odm->mp_mode) == 1)
{
ODM_SetRFReg(pDM_Odm, path, 0x3, bMaskDWord,
((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1]));
if(path == RF_PATH_A)
if (path == RF_PATH_A)
ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord,
((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05));
else
ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord,
((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05));
if(!IS_HARDWARE_TYPE_8723A(pAdapter))
if (!IS_HARDWARE_TYPE_8723A(pAdapter))
ODM_SetRFReg(pDM_Odm, path, RF_BS_PA_APSET_G9_G11, bMaskDWord,
((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08));
}
@ -1939,7 +1939,7 @@ PHY_IQCalibrate_8188E(
if (ODM_CheckPowerStatus(pAdapter) == false)
return;
if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
{
return;
}
@ -1954,14 +1954,14 @@ if (*(pDM_Odm->mp_mode) == 1)
#endif
/* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */
if(bSingleTone || bCarrierSuppression)
if (bSingleTone || bCarrierSuppression)
return;
#if DISABLE_BB_RF
return;
#endif
if(bReCovery)
if (bReCovery)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8188E: Return due to bReCovery!\n"));
_PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
@ -1973,7 +1973,7 @@ if (*(pDM_Odm->mp_mode) == 1)
result[0][i] = 0;
result[1][i] = 0;
result[2][i] = 0;
if((i==0) ||(i==2) || (i==4) || (i==6))
if ((i==0) ||(i==2) || (i==4) || (i==6))
result[3][i] = 0x100;
else
result[3][i] = 0;
@ -1992,26 +1992,26 @@ if (*(pDM_Odm->mp_mode) == 1)
{
phy_IQCalibrate_8188E(pAdapter, result, i, is2T);
if(i == 1) {
if (i == 1) {
is12simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 1);
if(is12simular) {
if (is12simular) {
final_candidate = 0;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n",final_candidate));
break;
}
}
if(i == 2)
if (i == 2)
{
is13simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 2);
if(is13simular) {
if (is13simular) {
final_candidate = 0;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n",final_candidate));
break;
}
is23simular = phy_SimularityCompare_8188E(pAdapter, result, 1, 2);
if(is23simular) {
if (is23simular) {
final_candidate = 1;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n",final_candidate));
}
@ -2021,7 +2021,7 @@ if (*(pDM_Odm->mp_mode) == 1)
for(i = 0; i < 8; i++)
RegTmp += result[3][i];
if(RegTmp != 0)
if (RegTmp != 0)
final_candidate = 3;
else
final_candidate = 0xFF;
@ -2045,7 +2045,7 @@ if (*(pDM_Odm->mp_mode) == 1)
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));
}
if(final_candidate != 0xff)
if (final_candidate != 0xff)
{
pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0];
pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1];
@ -2065,11 +2065,11 @@ if (*(pDM_Odm->mp_mode) == 1)
pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; /* Y default value */
}
if((RegE94 != 0)/*&&(RegEA4 != 0)*/)
if ((RegE94 != 0)/*&&(RegEA4 != 0)*/)
_PHY_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0));
if (is2T) {
if((RegEB4 != 0)/*&&(RegEC4 != 0)*/)
if ((RegEB4 != 0)/*&&(RegEC4 != 0)*/)
_PHY_PathBFillIQKMatrix(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0));
}
@ -2077,7 +2077,7 @@ if (*(pDM_Odm->mp_mode) == 1)
/* To Fix BSOD when final_candidate is 0xff */
/* by sherry 20120321 */
if(final_candidate < 4)
if (final_candidate < 4)
{
for(i = 0; i < IQK_Matrix_REG_NUM; i++)
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i];
@ -2122,12 +2122,12 @@ if (*(pDM_Odm->mp_mode) == 1)
return;
#endif
if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
{
return;
}
/* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */
if(bSingleTone || bCarrierSuppression)
if (bSingleTone || bCarrierSuppression)
return;
while(*(pDM_Odm->pbScanInProcess) && timecount < timeout)
@ -2140,7 +2140,7 @@ if (*(pDM_Odm->mp_mode) == 1)
/* ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount)); */
if(pDM_Odm->RFType == ODM_2T2R)
if (pDM_Odm->RFType == ODM_2T2R)
{
phy_LCCalibrate_8188E(pAdapter, true);
}
@ -2173,7 +2173,7 @@ static void phy_SetRFPathSwitch_8188E(
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
if(pAdapter->hw_init_completed == false)
if (pAdapter->hw_init_completed == false)
{
u8 u1bTmp;
u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7;
@ -2181,9 +2181,9 @@ static void phy_SetRFPathSwitch_8188E(
/* ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01); */
ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01);
}
if(is2T) /* 92C */
if (is2T) /* 92C */
{
if(bMain)
if (bMain)
ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); /* 92C_Path_A */
else
ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); /* BT */
@ -2191,7 +2191,7 @@ static void phy_SetRFPathSwitch_8188E(
else /* 88C */
{
if(bMain)
if (bMain)
ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2); /* Main */
else
ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1); /* Aux */
@ -2209,7 +2209,7 @@ void PHY_SetRFPathSwitch_8188E(
return;
#endif
if(pDM_Odm->RFType == ODM_2T2R)
if (pDM_Odm->RFType == ODM_2T2R)
{
phy_SetRFPathSwitch_8188E(pAdapter, bMain, true);
}

38
hal/hal_com.c
View file

@ -33,34 +33,34 @@ void dump_chip_info(struct hal_version ChipVersion)
int cnt = 0;
u8 buf[128];
if(IS_81XXC(ChipVersion)){
if (IS_81XXC(ChipVersion)){
cnt += sprintf((buf+cnt), "Chip Version Info: %s_", IS_92C_SERIAL(ChipVersion)?"CHIP_8192C":"CHIP_8188C");
}
else if(IS_92D(ChipVersion)){
else if (IS_92D(ChipVersion)){
cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8192D_");
}
else if(IS_8723_SERIES(ChipVersion)){
else if (IS_8723_SERIES(ChipVersion)){
cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8723A_");
}
else if(IS_8188E(ChipVersion)){
else if (IS_8188E(ChipVersion)){
cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8188E_");
}
cnt += sprintf((buf+cnt), "%s_", IS_NORMAL_CHIP(ChipVersion)?"Normal_Chip":"Test_Chip");
cnt += sprintf((buf+cnt), "%s_", IS_CHIP_VENDOR_TSMC(ChipVersion)?"TSMC":"UMC");
if(IS_A_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "A_CUT_");
else if(IS_B_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "B_CUT_");
else if(IS_C_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "C_CUT_");
else if(IS_D_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "D_CUT_");
else if(IS_E_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "E_CUT_");
else if(IS_I_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "I_CUT_");
else if(IS_J_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "J_CUT_");
else if(IS_K_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "K_CUT_");
if (IS_A_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "A_CUT_");
else if (IS_B_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "B_CUT_");
else if (IS_C_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "C_CUT_");
else if (IS_D_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "D_CUT_");
else if (IS_E_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "E_CUT_");
else if (IS_I_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "I_CUT_");
else if (IS_J_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "J_CUT_");
else if (IS_K_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "K_CUT_");
else cnt += sprintf((buf+cnt), "UNKNOWN_CUT(%d)_", ChipVersion.CUTVersion);
if(IS_1T1R(ChipVersion)) cnt += sprintf((buf+cnt), "1T1R_");
else if(IS_1T2R(ChipVersion)) cnt += sprintf((buf+cnt), "1T2R_");
else if(IS_2T2R(ChipVersion)) cnt += sprintf((buf+cnt), "2T2R_");
if (IS_1T1R(ChipVersion)) cnt += sprintf((buf+cnt), "1T1R_");
else if (IS_1T2R(ChipVersion)) cnt += sprintf((buf+cnt), "1T2R_");
else if (IS_2T2R(ChipVersion)) cnt += sprintf((buf+cnt), "2T2R_");
else cnt += sprintf((buf+cnt), "UNKNOWN_RFTYPE(%d)_", ChipVersion.RFType);
cnt += sprintf((buf+cnt), "RomVer(%d)\n", ChipVersion.ROMVer);
@ -151,7 +151,7 @@ void HalSetBrateCfg(
is_brate = mBratesOS[i] & IEEE80211_BASIC_RATE_MASK;
brate = mBratesOS[i] & 0x7f;
if( is_brate )
if ( is_brate )
{
switch(brate)
{
@ -198,7 +198,7 @@ _TwoOutPipeMapping(
{
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
if(bWIFICfg){ /* WMM */
if (bWIFICfg){ /* WMM */
/* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */
/* 0, 1, 0, 1, 0, 0, 0, 0, 0 }; */
@ -243,7 +243,7 @@ static void _ThreeOutPipeMapping(
{
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
if(bWIFICfg){/* for WMM */
if (bWIFICfg){/* for WMM */
/* BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA */
/* 1, 2, 1, 0, 0, 0, 0, 0, 0 }; */
@ -389,7 +389,7 @@ SetHalDefVar(struct adapter *adapter, enum HAL_DEF_VARIABLE variable, void *valu
switch(variable) {
case HW_DEF_FA_CNT_DUMP:
if(*((u8*)value))
if (*((u8*)value))
pDM_Odm->DebugComponents |= (ODM_COMP_DIG |ODM_COMP_FA_CNT);
else
pDM_Odm->DebugComponents &= ~(ODM_COMP_DIG |ODM_COMP_FA_CNT);

114
hal/hal_intf.c
View file

@ -27,40 +27,40 @@
void rtw_hal_chip_configure(struct adapter *padapter)
{
if(padapter->HalFunc.intf_chip_configure)
if (padapter->HalFunc.intf_chip_configure)
padapter->HalFunc.intf_chip_configure(padapter);
}
void rtw_hal_read_chip_info(struct adapter *padapter)
{
if(padapter->HalFunc.read_adapter_info)
if (padapter->HalFunc.read_adapter_info)
padapter->HalFunc.read_adapter_info(padapter);
}
void rtw_hal_read_chip_version(struct adapter *padapter)
{
if(padapter->HalFunc.read_chip_version)
if (padapter->HalFunc.read_chip_version)
padapter->HalFunc.read_chip_version(padapter);
}
void rtw_hal_def_value_init(struct adapter *padapter)
{
if (is_primary_adapter(padapter))
if(padapter->HalFunc.init_default_value)
if (padapter->HalFunc.init_default_value)
padapter->HalFunc.init_default_value(padapter);
}
void rtw_hal_free_data(struct adapter *padapter)
{
if (is_primary_adapter(padapter))
if(padapter->HalFunc.free_hal_data)
if (padapter->HalFunc.free_hal_data)
padapter->HalFunc.free_hal_data(padapter);
}
void rtw_hal_dm_init(struct adapter *padapter)
{
if (is_primary_adapter(padapter))
if(padapter->HalFunc.dm_init)
if (padapter->HalFunc.dm_init)
padapter->HalFunc.dm_init(padapter);
}
@ -68,32 +68,32 @@ void rtw_hal_dm_deinit(struct adapter *padapter)
{
/* cancel dm timer */
if (is_primary_adapter(padapter))
if(padapter->HalFunc.dm_deinit)
if (padapter->HalFunc.dm_deinit)
padapter->HalFunc.dm_deinit(padapter);
}
void rtw_hal_sw_led_init(struct adapter *padapter)
{
if(padapter->HalFunc.InitSwLeds)
if (padapter->HalFunc.InitSwLeds)
padapter->HalFunc.InitSwLeds(padapter);
}
void rtw_hal_sw_led_deinit(struct adapter *padapter)
{
if(padapter->HalFunc.DeInitSwLeds)
if (padapter->HalFunc.DeInitSwLeds)
padapter->HalFunc.DeInitSwLeds(padapter);
}
u32 rtw_hal_power_on(struct adapter *padapter)
{
if(padapter->HalFunc.hal_power_on)
if (padapter->HalFunc.hal_power_on)
return padapter->HalFunc.hal_power_on(padapter);
return _FAIL;
}
void rtw_hal_power_off(struct adapter *padapter)
{
if(padapter->HalFunc.hal_power_off)
if (padapter->HalFunc.hal_power_off)
padapter->HalFunc.hal_power_off(padapter);
}
@ -105,7 +105,7 @@ uint rtw_hal_init(struct adapter *padapter)
status = padapter->HalFunc.hal_init(padapter);
if(status == _SUCCESS){
if (status == _SUCCESS){
for (i = 0; i<dvobj->iface_nums; i++) {
padapter = dvobj->padapters[i];
padapter->hw_init_completed = true;
@ -147,7 +147,7 @@ uint rtw_hal_deinit(struct adapter *padapter)
status = padapter->HalFunc.hal_deinit(padapter);
if(status == _SUCCESS){
if (status == _SUCCESS){
for (i = 0; i<dvobj->iface_nums; i++) {
padapter = dvobj->padapters[i];
padapter->hw_init_completed = false;
@ -174,27 +174,27 @@ void rtw_hal_get_hwreg(struct adapter *padapter, u8 variable, u8 *val)
u8 rtw_hal_set_def_var(struct adapter *padapter, enum HAL_DEF_VARIABLE eVariable, void * pValue)
{
if(padapter->HalFunc.SetHalDefVarHandler)
if (padapter->HalFunc.SetHalDefVarHandler)
return padapter->HalFunc.SetHalDefVarHandler(padapter,eVariable,pValue);
return _FAIL;
}
u8 rtw_hal_get_def_var(struct adapter *padapter, enum HAL_DEF_VARIABLE eVariable, void * pValue)
{
if(padapter->HalFunc.GetHalDefVarHandler)
if (padapter->HalFunc.GetHalDefVarHandler)
return padapter->HalFunc.GetHalDefVarHandler(padapter,eVariable,pValue);
return _FAIL;
}
void rtw_hal_set_odm_var(struct adapter *padapter, enum HAL_ODM_VARIABLE eVariable, void * pValue1,bool bSet)
{
if(padapter->HalFunc.SetHalODMVarHandler)
if (padapter->HalFunc.SetHalODMVarHandler)
padapter->HalFunc.SetHalODMVarHandler(padapter,eVariable,pValue1,bSet);
}
void rtw_hal_get_odm_var(struct adapter *padapter, enum HAL_ODM_VARIABLE eVariable, void * pValue1,bool bSet)
{
if(padapter->HalFunc.GetHalODMVarHandler)
if (padapter->HalFunc.GetHalODMVarHandler)
padapter->HalFunc.GetHalODMVarHandler(padapter,eVariable,pValue1,bSet);
}
@ -229,7 +229,7 @@ void rtw_hal_disable_interrupt(struct adapter *padapter)
u32 rtw_hal_inirp_init(struct adapter *padapter)
{
u32 rst = _FAIL;
if(padapter->HalFunc.inirp_init)
if (padapter->HalFunc.inirp_init)
rst = padapter->HalFunc.inirp_init(padapter);
else
DBG_871X(" %s HalFunc.inirp_init is NULL!!!\n",__FUNCTION__);
@ -239,7 +239,7 @@ u32 rtw_hal_inirp_init(struct adapter *padapter)
u32 rtw_hal_inirp_deinit(struct adapter *padapter)
{
if(padapter->HalFunc.inirp_deinit)
if (padapter->HalFunc.inirp_deinit)
return padapter->HalFunc.inirp_deinit(padapter);
return _FAIL;
@ -248,14 +248,14 @@ u32 rtw_hal_inirp_deinit(struct adapter *padapter)
u8 rtw_hal_intf_ps_func(struct adapter *padapter, enum HAL_INTF_PS_FUNC efunc_id, u8* val)
{
if(padapter->HalFunc.interface_ps_func)
if (padapter->HalFunc.interface_ps_func)
return padapter->HalFunc.interface_ps_func(padapter,efunc_id,val);
return _FAIL;
}
s32 rtw_hal_xmitframe_enqueue(struct adapter *padapter, struct xmit_frame *pxmitframe)
{
if(padapter->HalFunc.hal_xmitframe_enqueue)
if (padapter->HalFunc.hal_xmitframe_enqueue)
return padapter->HalFunc.hal_xmitframe_enqueue(padapter, pxmitframe);
return false;
@ -263,7 +263,7 @@ s32 rtw_hal_xmitframe_enqueue(struct adapter *padapter, struct xmit_frame *pxmit
s32 rtw_hal_xmit(struct adapter *padapter, struct xmit_frame *pxmitframe)
{
if(padapter->HalFunc.hal_xmit)
if (padapter->HalFunc.hal_xmit)
return padapter->HalFunc.hal_xmit(padapter, pxmitframe);
return false;
@ -280,9 +280,9 @@ s32 rtw_hal_mgnt_xmit(struct adapter *padapter, struct xmit_frame *pmgntframe)
memcpy(pmgntframe->attrib.ra, pwlanhdr->addr1, ETH_ALEN);
#ifdef CONFIG_IEEE80211W
if(padapter->securitypriv.binstallBIPkey == true)
if (padapter->securitypriv.binstallBIPkey == true)
{
if(IS_MCAST(pmgntframe->attrib.ra))
if (IS_MCAST(pmgntframe->attrib.ra))
{
pmgntframe->attrib.encrypt = _BIP_;
/* pmgntframe->attrib.bswenc = true; */
@ -296,27 +296,27 @@ s32 rtw_hal_mgnt_xmit(struct adapter *padapter, struct xmit_frame *pmgntframe)
}
#endif /* CONFIG_IEEE80211W */
if(padapter->HalFunc.mgnt_xmit)
if (padapter->HalFunc.mgnt_xmit)
ret = padapter->HalFunc.mgnt_xmit(padapter, pmgntframe);
return ret;
}
s32 rtw_hal_init_xmit_priv(struct adapter *padapter)
{
if(padapter->HalFunc.init_xmit_priv != NULL)
if (padapter->HalFunc.init_xmit_priv != NULL)
return padapter->HalFunc.init_xmit_priv(padapter);
return _FAIL;
}
void rtw_hal_free_xmit_priv(struct adapter *padapter)
{
if(padapter->HalFunc.free_xmit_priv != NULL)
if (padapter->HalFunc.free_xmit_priv != NULL)
padapter->HalFunc.free_xmit_priv(padapter);
}
s32 rtw_hal_init_recv_priv(struct adapter *padapter)
{
if(padapter->HalFunc.init_recv_priv)
if (padapter->HalFunc.init_recv_priv)
return padapter->HalFunc.init_recv_priv(padapter);
return _FAIL;
@ -324,7 +324,7 @@ s32 rtw_hal_init_recv_priv(struct adapter *padapter)
void rtw_hal_free_recv_priv(struct adapter *padapter)
{
if(padapter->HalFunc.free_recv_priv)
if (padapter->HalFunc.free_recv_priv)
padapter->HalFunc.free_recv_priv(padapter);
}
@ -333,119 +333,119 @@ void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level)
struct adapter *padapter;
struct mlme_priv *pmlmepriv;
if(!psta)
if (!psta)
return;
padapter = psta->padapter;
pmlmepriv = &(padapter->mlmepriv);
if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == true)
if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == true)
{
add_RATid(padapter, psta, rssi_level);
}
else
{
if(padapter->HalFunc.UpdateRAMaskHandler)
if (padapter->HalFunc.UpdateRAMaskHandler)
padapter->HalFunc.UpdateRAMaskHandler(padapter, psta->mac_id, rssi_level);
}
}
void rtw_hal_add_ra_tid(struct adapter *padapter, u32 bitmap, u8 arg, u8 rssi_level)
{
if(padapter->HalFunc.Add_RateATid)
if (padapter->HalFunc.Add_RateATid)
padapter->HalFunc.Add_RateATid(padapter, bitmap, arg, rssi_level);
}
/* Start specifical interface thread */
void rtw_hal_start_thread(struct adapter *padapter)
{
if(padapter->HalFunc.run_thread)
if (padapter->HalFunc.run_thread)
padapter->HalFunc.run_thread(padapter);
}
/* Start specifical interface thread */
void rtw_hal_stop_thread(struct adapter *padapter)
{
if(padapter->HalFunc.cancel_thread)
if (padapter->HalFunc.cancel_thread)
padapter->HalFunc.cancel_thread(padapter);
}
u32 rtw_hal_read_bbreg(struct adapter *padapter, u32 RegAddr, u32 BitMask)
{
u32 data = 0;
if(padapter->HalFunc.read_bbreg)
if (padapter->HalFunc.read_bbreg)
data = padapter->HalFunc.read_bbreg(padapter, RegAddr, BitMask);
return data;
}
void rtw_hal_write_bbreg(struct adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
{
if(padapter->HalFunc.write_bbreg)
if (padapter->HalFunc.write_bbreg)
padapter->HalFunc.write_bbreg(padapter, RegAddr, BitMask, Data);
}
u32 rtw_hal_read_rfreg(struct adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask)
{
u32 data = 0;
if( padapter->HalFunc.read_rfreg)
if ( padapter->HalFunc.read_rfreg)
data = padapter->HalFunc.read_rfreg(padapter, eRFPath, RegAddr, BitMask);
return data;
}
void rtw_hal_write_rfreg(struct adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
{
if(padapter->HalFunc.write_rfreg)
if (padapter->HalFunc.write_rfreg)
padapter->HalFunc.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data);
}
s32 rtw_hal_interrupt_handler(struct adapter *padapter)
{
if(padapter->HalFunc.interrupt_handler)
if (padapter->HalFunc.interrupt_handler)
return padapter->HalFunc.interrupt_handler(padapter);
return _FAIL;
}
void rtw_hal_set_bwmode(struct adapter *padapter, enum HT_CHANNEL_WIDTH Bandwidth, u8 Offset)
{
if(padapter->HalFunc.set_bwmode_handler)
if (padapter->HalFunc.set_bwmode_handler)
padapter->HalFunc.set_bwmode_handler(padapter, Bandwidth, Offset);
}
void rtw_hal_set_chan(struct adapter *padapter, u8 channel)
{
if(padapter->HalFunc.set_channel_handler)
if (padapter->HalFunc.set_channel_handler)
padapter->HalFunc.set_channel_handler(padapter, channel);
}
void rtw_hal_dm_watchdog(struct adapter *padapter)
{
if(padapter->HalFunc.hal_dm_watchdog)
if (padapter->HalFunc.hal_dm_watchdog)
padapter->HalFunc.hal_dm_watchdog(padapter);
}
void rtw_hal_bcn_related_reg_setting(struct adapter *padapter)
{
if(padapter->HalFunc.SetBeaconRelatedRegistersHandler)
if (padapter->HalFunc.SetBeaconRelatedRegistersHandler)
padapter->HalFunc.SetBeaconRelatedRegistersHandler(padapter);
}
u8 rtw_hal_antdiv_before_linked(struct adapter *padapter)
{
if(padapter->HalFunc.AntDivBeforeLinkHandler)
if (padapter->HalFunc.AntDivBeforeLinkHandler)
return padapter->HalFunc.AntDivBeforeLinkHandler(padapter);
return false;
}
void rtw_hal_antdiv_rssi_compared(struct adapter *padapter, struct wlan_bssid_ex *dst, struct wlan_bssid_ex *src)
{
if(padapter->HalFunc.AntDivCompareHandler)
if (padapter->HalFunc.AntDivCompareHandler)
padapter->HalFunc.AntDivCompareHandler(padapter, dst, src);
}
#ifdef CONFIG_HOSTAPD_MLME
s32 rtw_hal_hostap_mgnt_xmit_entry(struct adapter *padapter, _pkt *pkt)
{
if(padapter->HalFunc.hostap_mgnt_xmit_entry)
if (padapter->HalFunc.hostap_mgnt_xmit_entry)
return padapter->HalFunc.hostap_mgnt_xmit_entry(padapter, pkt);
return _FAIL;
}
@ -453,20 +453,20 @@ s32 rtw_hal_hostap_mgnt_xmit_entry(struct adapter *padapter, _pkt *pkt)
void rtw_hal_sreset_init(struct adapter *padapter)
{
if(padapter->HalFunc.sreset_init_value)
if (padapter->HalFunc.sreset_init_value)
padapter->HalFunc.sreset_init_value(padapter);
}
void rtw_hal_sreset_reset(struct adapter *padapter)
{
padapter = GET_PRIMARY_ADAPTER(padapter);
if(padapter->HalFunc.silentreset)
if (padapter->HalFunc.silentreset)
padapter->HalFunc.silentreset(padapter);
}
void rtw_hal_sreset_reset_value(struct adapter *padapter)
{
if(padapter->HalFunc.sreset_reset_value)
if (padapter->HalFunc.sreset_reset_value)
padapter->HalFunc.sreset_reset_value(padapter);
}
@ -475,7 +475,7 @@ void rtw_hal_sreset_xmit_status_check(struct adapter *padapter)
if (!is_primary_adapter(padapter))
return;
if(padapter->HalFunc.sreset_xmit_status_check)
if (padapter->HalFunc.sreset_xmit_status_check)
padapter->HalFunc.sreset_xmit_status_check(padapter);
}
@ -484,14 +484,14 @@ void rtw_hal_sreset_linked_status_check(struct adapter *padapter)
if (!is_primary_adapter(padapter))
return;
if(padapter->HalFunc.sreset_linked_status_check)
if (padapter->HalFunc.sreset_linked_status_check)
padapter->HalFunc.sreset_linked_status_check(padapter);
}
u8 rtw_hal_sreset_get_wifi_status(struct adapter *padapter)
{
u8 status = 0;
if(padapter->HalFunc.sreset_get_wifi_status)
if (padapter->HalFunc.sreset_get_wifi_status)
status = padapter->HalFunc.sreset_get_wifi_status(padapter);
return status;
}
@ -502,27 +502,27 @@ bool rtw_hal_sreset_inprogress(struct adapter *padapter)
padapter = GET_PRIMARY_ADAPTER(padapter);
if(padapter->HalFunc.sreset_inprogress)
if (padapter->HalFunc.sreset_inprogress)
inprogress = padapter->HalFunc.sreset_inprogress(padapter);
return inprogress;
}
int rtw_hal_iol_cmd(struct adapter *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt)
{
if(adapter->HalFunc.IOL_exec_cmds_sync)
if (adapter->HalFunc.IOL_exec_cmds_sync)
return adapter->HalFunc.IOL_exec_cmds_sync(adapter, xmit_frame, max_wating_ms,bndy_cnt);
return _FAIL;
}
void rtw_hal_notch_filter(struct adapter *adapter, bool enable)
{
if(adapter->HalFunc.hal_notch_filter)
if (adapter->HalFunc.hal_notch_filter)
adapter->HalFunc.hal_notch_filter(adapter,enable);
}
void rtw_hal_reset_security_engine(struct adapter * adapter)
{
if(adapter->HalFunc.hal_reset_security_engine)
if (adapter->HalFunc.hal_reset_security_engine)
adapter->HalFunc.hal_reset_security_engine(adapter);
}

492
hal/odm.c
View file

File diff suppressed because it is too large Load diff

176
hal/odm_HWConfig.c
View file

@ -82,42 +82,42 @@ odm_SignalScaleMapping_92CSeries(
{
s32 RetSig;
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
if(pDM_Odm->SupportInterface == ODM_ITRF_PCIE)
if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE)
{
/* Step 1. Scale mapping. */
if(CurrSig >= 61 && CurrSig <= 100)
if (CurrSig >= 61 && CurrSig <= 100)
{
RetSig = 90 + ((CurrSig - 60) / 4);
}
else if(CurrSig >= 41 && CurrSig <= 60)
else if (CurrSig >= 41 && CurrSig <= 60)
{
RetSig = 78 + ((CurrSig - 40) / 2);
}
else if(CurrSig >= 31 && CurrSig <= 40)
else if (CurrSig >= 31 && CurrSig <= 40)
{
RetSig = 66 + (CurrSig - 30);
}
else if(CurrSig >= 21 && CurrSig <= 30)
else if (CurrSig >= 21 && CurrSig <= 30)
{
RetSig = 54 + (CurrSig - 20);
}
else if(CurrSig >= 5 && CurrSig <= 20)
else if (CurrSig >= 5 && CurrSig <= 20)
{
RetSig = 42 + (((CurrSig - 5) * 2) / 3);
}
else if(CurrSig == 4)
else if (CurrSig == 4)
{
RetSig = 36;
}
else if(CurrSig == 3)
else if (CurrSig == 3)
{
RetSig = 27;
}
else if(CurrSig == 2)
else if (CurrSig == 2)
{
RetSig = 18;
}
else if(CurrSig == 1)
else if (CurrSig == 1)
{
RetSig = 9;
}
@ -129,33 +129,33 @@ odm_SignalScaleMapping_92CSeries(
#endif
#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) ||(DEV_BUS_TYPE == RT_SDIO_INTERFACE))
if((pDM_Odm->SupportInterface == ODM_ITRF_USB) || (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) )
if ((pDM_Odm->SupportInterface == ODM_ITRF_USB) || (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) )
{
if(CurrSig >= 51 && CurrSig <= 100)
if (CurrSig >= 51 && CurrSig <= 100)
{
RetSig = 100;
}
else if(CurrSig >= 41 && CurrSig <= 50)
else if (CurrSig >= 41 && CurrSig <= 50)
{
RetSig = 80 + ((CurrSig - 40)*2);
}
else if(CurrSig >= 31 && CurrSig <= 40)
else if (CurrSig >= 31 && CurrSig <= 40)
{
RetSig = 66 + (CurrSig - 30);
}
else if(CurrSig >= 21 && CurrSig <= 30)
else if (CurrSig >= 21 && CurrSig <= 30)
{
RetSig = 54 + (CurrSig - 20);
}
else if(CurrSig >= 10 && CurrSig <= 20)
else if (CurrSig >= 10 && CurrSig <= 20)
{
RetSig = 42 + (((CurrSig - 10) * 2) / 3);
}
else if(CurrSig >= 5 && CurrSig <= 9)
else if (CurrSig >= 5 && CurrSig <= 9)
{
RetSig = 22 + (((CurrSig - 5) * 3) / 2);
}
else if(CurrSig >= 1 && CurrSig <= 4)
else if (CurrSig >= 1 && CurrSig <= 4)
{
RetSig = 6 + (((CurrSig - 1) * 3) / 2);
}
@ -173,13 +173,13 @@ odm_SignalScaleMapping(
s32 CurrSig
)
{
if( (pDM_Odm->SupportPlatform == ODM_MP) &&
if ( (pDM_Odm->SupportPlatform == ODM_MP) &&
(pDM_Odm->SupportInterface != ODM_ITRF_PCIE) && /* USB & SDIO */
(pDM_Odm->PatchID==10))/* pMgntInfo->CustomerID == RT_CID_819x_Netcore */
{
return odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore(pDM_Odm,CurrSig);
}
else if( (pDM_Odm->SupportPlatform == ODM_MP) &&
else if ( (pDM_Odm->SupportPlatform == ODM_MP) &&
(pDM_Odm->SupportInterface == ODM_ITRF_PCIE) &&
(pDM_Odm->PatchID==19))/* pMgntInfo->CustomerID == RT_CID_819x_Lenovo) */
{
@ -219,15 +219,15 @@ odm_EVMdbToPercentage(
/* ODM_RTPRINT(FRX, RX_PHY_SQ, ("EVMdbToPercentage92C Value=%d / %x\n", ret_val, ret_val)); */
if(ret_val >= 0)
if (ret_val >= 0)
ret_val = 0;
if(ret_val <= -33)
if (ret_val <= -33)
ret_val = -33;
ret_val = 0 - ret_val;
ret_val*=3;
if(ret_val == 99)
if (ret_val == 99)
ret_val = 100;
return(ret_val);
@ -261,7 +261,7 @@ odm_RxPhyStatus92CSeries_Parsing(
pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1;
if(isCCKrate) {
if (isCCKrate) {
u8 report;
u8 cck_agc_rpt;
@ -276,12 +276,12 @@ odm_RxPhyStatus92CSeries_Parsing(
/* 2011.11.28 LukeLee: 88E use different LNA & VGA gain table */
/* The RSSI formula should be modified according to the gain table */
/* In 88E, cck_highpwr is always set to 1 */
if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8812)) {
if (pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8812)) {
LNA_idx = ((cck_agc_rpt & 0xE0) >>5);
VGA_idx = (cck_agc_rpt & 0x1F);
switch(LNA_idx) {
case 7:
if(VGA_idx <= 27)
if (VGA_idx <= 27)
rx_pwr_all = -100 + 2*(27-VGA_idx); /* VGA_idx = 27~2 */
else
rx_pwr_all = -100;
@ -299,7 +299,7 @@ odm_RxPhyStatus92CSeries_Parsing(
rx_pwr_all = -24 + 2*(7-VGA_idx); /* VGA_idx = 7~0 */
break;
case 2:
if(cck_highpwr)
if (cck_highpwr)
rx_pwr_all = -12 + 2*(5-VGA_idx); /* VGA_idx = 5~0 */
else
rx_pwr_all = -6+ 2*(5-VGA_idx);
@ -315,19 +315,19 @@ odm_RxPhyStatus92CSeries_Parsing(
}
rx_pwr_all += 6;
PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all);
if(cck_highpwr == false)
if (cck_highpwr == false)
{
if(PWDB_ALL >= 80)
if (PWDB_ALL >= 80)
PWDB_ALL = ((PWDB_ALL-80)<<1)+((PWDB_ALL-80)>>1)+80;
else if((PWDB_ALL <= 78) && (PWDB_ALL >= 20))
else if ((PWDB_ALL <= 78) && (PWDB_ALL >= 20))
PWDB_ALL += 3;
if(PWDB_ALL>100)
if (PWDB_ALL>100)
PWDB_ALL = 100;
}
}
else
{
if(!cck_highpwr)
if (!cck_highpwr)
{
report =( cck_agc_rpt & 0xc0 )>>6;
switch(report)
@ -375,30 +375,30 @@ odm_RxPhyStatus92CSeries_Parsing(
PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all);
/* Modification for ext-LNA board */
if(pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA))
if (pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA))
{
if((cck_agc_rpt>>7) == 0){
if ((cck_agc_rpt>>7) == 0){
PWDB_ALL = (PWDB_ALL>94)?100:(PWDB_ALL +6);
}
else
{
if(PWDB_ALL > 38)
if (PWDB_ALL > 38)
PWDB_ALL -= 16;
else
PWDB_ALL = (PWDB_ALL<=16)?(PWDB_ALL>>2):(PWDB_ALL -12);
}
/* CCK modification */
if(PWDB_ALL > 25 && PWDB_ALL <= 60)
if (PWDB_ALL > 25 && PWDB_ALL <= 60)
PWDB_ALL += 6;
/* else if (PWDB_ALL <= 25) */
/* PWDB_ALL += 8; */
}
else/* Modification for int-LNA board */
{
if(PWDB_ALL > 99)
if (PWDB_ALL > 99)
PWDB_ALL -= 8;
else if(PWDB_ALL > 50 && PWDB_ALL <= 68)
else if (PWDB_ALL > 50 && PWDB_ALL <= 68)
PWDB_ALL += 4;
}
}
@ -409,20 +409,20 @@ odm_RxPhyStatus92CSeries_Parsing(
/* */
/* (3) Get Signal Quality (EVM) */
/* */
if(pPktinfo->bPacketMatchBSSID)
if (pPktinfo->bPacketMatchBSSID)
{
u8 SQ,SQ_rpt;
if((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)){/* pMgntInfo->CustomerID == RT_CID_819x_Lenovo */
if ((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)){/* pMgntInfo->CustomerID == RT_CID_819x_Lenovo */
SQ = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm,isCCKrate,PWDB_ALL,0,0);
}
else if(pPhyInfo->RxPWDBAll > 40 && !pDM_Odm->bInHctTest){
else if (pPhyInfo->RxPWDBAll > 40 && !pDM_Odm->bInHctTest){
SQ = 100;
}
else{
SQ_rpt = pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all;
if(SQ_rpt > 64)
if (SQ_rpt > 64)
SQ = 0;
else if (SQ_rpt < 20)
SQ = 100;
@ -460,14 +460,14 @@ odm_RxPhyStatus92CSeries_Parsing(
/* RTPRINT(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI)); */
/* Modification for ext-LNA board */
if(pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA))
if (pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA))
{
if((pPhyStaRpt->path_agc[i].trsw) == 1)
if ((pPhyStaRpt->path_agc[i].trsw) == 1)
RSSI = (RSSI>94)?100:(RSSI +6);
else
RSSI = (RSSI<=16)?(RSSI>>3):(RSSI -16);
if((RSSI <= 34) && (RSSI >=4))
if ((RSSI <= 34) && (RSSI >=4))
RSSI -= 4;
}
@ -477,11 +477,11 @@ odm_RxPhyStatus92CSeries_Parsing(
pPhyInfo->RxSNR[i] = pDM_Odm->PhyDbgInfo.RxSNRdB[i] = (s32)(pPhyStaRpt->path_rxsnr[i]/2);
/* Record Signal Strength for next packet */
if(pPktinfo->bPacketMatchBSSID)
if (pPktinfo->bPacketMatchBSSID)
{
if((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19))
if ((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19))
{
if(i==ODM_RF_PATH_A)
if (i==ODM_RF_PATH_A)
pPhyInfo->SignalQuality = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm,isCCKrate,PWDB_ALL,i,RSSI);
}
@ -502,13 +502,13 @@ odm_RxPhyStatus92CSeries_Parsing(
pPhyInfo->RxPower = rx_pwr_all;
pPhyInfo->RecvSignalPower = rx_pwr_all;
if((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)){
if ((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)){
/* do nothing */
} else{/* pMgntInfo->CustomerID != RT_CID_819x_Lenovo */
/* */
/* (3)EVM of HT rate */
/* */
if(pPktinfo->Rate >=DESC92C_RATEMCS8 && pPktinfo->Rate <=DESC92C_RATEMCS15)
if (pPktinfo->Rate >=DESC92C_RATEMCS8 && pPktinfo->Rate <=DESC92C_RATEMCS15)
Max_spatial_stream = 2; /* both spatial stream make sense */
else
Max_spatial_stream = 1; /* only spatial stream 1 makes sense */
@ -522,9 +522,9 @@ odm_RxPhyStatus92CSeries_Parsing(
/* RTPRINT(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n", */
/* GET_RX_STATUS_DESC_RX_MCS(pDesc), pDrvInfo->rxevm[i], "%", EVM)); */
if(pPktinfo->bPacketMatchBSSID)
if (pPktinfo->bPacketMatchBSSID)
{
if(i==ODM_RF_PATH_A) /* Fill value in RFD, Get the first spatial stream only */
if (i==ODM_RF_PATH_A) /* Fill value in RFD, Get the first spatial stream only */
{
pPhyInfo->SignalQuality = (u8)(EVM & 0xff);
}
@ -536,7 +536,7 @@ odm_RxPhyStatus92CSeries_Parsing(
}
/* UI BSS List signal strength(in percentage), make it good looking, from 0~100. */
/* It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). */
if(isCCKrate)
if (isCCKrate)
{
pPhyInfo->SignalStrength = (u8)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));/* PWDB_ALL; */
}
@ -580,7 +580,7 @@ odm_Process_RSSIForDM(
PSTA_INFO_T pEntry;
if(pPktinfo->StationID == 0xFF)
if (pPktinfo->StationID == 0xFF)
return;
/* 2011/11/17 MH Need to debug */
@ -590,35 +590,35 @@ odm_Process_RSSIForDM(
}
pEntry = pDM_Odm->pODM_StaInfo[pPktinfo->StationID];
if(!IS_STA_VALID(pEntry))
if (!IS_STA_VALID(pEntry))
return;
if((!pPktinfo->bPacketMatchBSSID) )
if ((!pPktinfo->bPacketMatchBSSID) )
return;
isCCKrate = (pPktinfo->Rate <= DESC92C_RATE11M) ? true : false;
if(pPktinfo->bPacketBeacon)
if (pPktinfo->bPacketBeacon)
pDM_Odm->PhyDbgInfo.NumQryBeaconPkt++;
pDM_Odm->RxRate = pPktinfo->Rate;
/* Smart Antenna Debug Message------------------ */
if(pDM_Odm->SupportICType == ODM_RTL8188E)
if (pDM_Odm->SupportICType == ODM_RTL8188E)
{
u8 antsel_tr_mux;
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)
if (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)
{
if(pDM_FatTable->FAT_State == FAT_TRAINING_STATE)
if (pDM_FatTable->FAT_State == FAT_TRAINING_STATE)
{
if(pPktinfo->bPacketToSelf) /* pPktinfo->bPacketMatchBSSID && (!pPktinfo->bPacketBeacon)) */
if (pPktinfo->bPacketToSelf) /* pPktinfo->bPacketMatchBSSID && (!pPktinfo->bPacketBeacon)) */
{
antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2<<2) |(pDM_FatTable->antsel_rx_keep_1 <<1) |pDM_FatTable->antsel_rx_keep_0;
pDM_FatTable->antSumRSSI[antsel_tr_mux] += pPhyInfo->RxPWDBAll;
pDM_FatTable->antRSSIcnt[antsel_tr_mux]++;
}
}
} else if((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)) {
if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) {
} else if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)) {
if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) {
antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2<<2) |(pDM_FatTable->antsel_rx_keep_1 <<1) |pDM_FatTable->antsel_rx_keep_0;
ODM_AntselStatistics_88E(pDM_Odm, antsel_tr_mux, pPktinfo->StationID, pPhyInfo->RxPWDBAll);
}
@ -631,12 +631,12 @@ odm_Process_RSSIForDM(
UndecoratedSmoothedOFDM = pEntry->rssi_stat.UndecoratedSmoothedOFDM;
UndecoratedSmoothedPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB;
if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon)
if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon)
{
if(!isCCKrate)/* ofdm rate */
if (!isCCKrate)/* ofdm rate */
{
if(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B] == 0){
if (pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B] == 0){
RSSI_Ave = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A];
pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A];
pDM_Odm->RSSI_B = 0;
@ -648,7 +648,7 @@ odm_Process_RSSIForDM(
pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A];
pDM_Odm->RSSI_B = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B];
if(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A] > pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B])
if (pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A] > pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B])
{
RSSI_max = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A];
RSSI_min = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B];
@ -658,24 +658,24 @@ odm_Process_RSSIForDM(
RSSI_max = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B];
RSSI_min = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A];
}
if((RSSI_max -RSSI_min) < 3)
if ((RSSI_max -RSSI_min) < 3)
RSSI_Ave = RSSI_max;
else if((RSSI_max -RSSI_min) < 6)
else if ((RSSI_max -RSSI_min) < 6)
RSSI_Ave = RSSI_max - 1;
else if((RSSI_max -RSSI_min) < 10)
else if ((RSSI_max -RSSI_min) < 10)
RSSI_Ave = RSSI_max - 2;
else
RSSI_Ave = RSSI_max - 3;
}
/* 1 Process OFDM RSSI */
if(UndecoratedSmoothedOFDM <= 0) /* initialize */
if (UndecoratedSmoothedOFDM <= 0) /* initialize */
{
UndecoratedSmoothedOFDM = pPhyInfo->RxPWDBAll;
}
else
{
if(pPhyInfo->RxPWDBAll > (u32)UndecoratedSmoothedOFDM)
if (pPhyInfo->RxPWDBAll > (u32)UndecoratedSmoothedOFDM)
{
UndecoratedSmoothedOFDM =
( ((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) +
@ -700,13 +700,13 @@ odm_Process_RSSIForDM(
pDM_Odm->RSSI_B = 0xFF;
/* 1 Process CCK RSSI */
if(UndecoratedSmoothedCCK <= 0) /* initialize */
if (UndecoratedSmoothedCCK <= 0) /* initialize */
{
UndecoratedSmoothedCCK = pPhyInfo->RxPWDBAll;
}
else
{
if(pPhyInfo->RxPWDBAll > (u32)UndecoratedSmoothedCCK)
if (pPhyInfo->RxPWDBAll > (u32)UndecoratedSmoothedCCK)
{
UndecoratedSmoothedCCK =
( ((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) +
@ -723,10 +723,10 @@ odm_Process_RSSIForDM(
pEntry->rssi_stat.PacketMap = pEntry->rssi_stat.PacketMap<<1;
}
/* if(pEntry) */
/* if (pEntry) */
{
/* 2011.07.28 LukeLee: modified to prevent unstable CCK RSSI */
if(pEntry->rssi_stat.ValidBit >= 64)
if (pEntry->rssi_stat.ValidBit >= 64)
pEntry->rssi_stat.ValidBit = 64;
else
pEntry->rssi_stat.ValidBit++;
@ -734,14 +734,14 @@ odm_Process_RSSIForDM(
for(i=0; i<pEntry->rssi_stat.ValidBit; i++)
OFDM_pkt += (u8)(pEntry->rssi_stat.PacketMap>>i)&BIT0;
if(pEntry->rssi_stat.ValidBit == 64)
if (pEntry->rssi_stat.ValidBit == 64)
{
Weighting = ((OFDM_pkt<<4) > 64)?64:(OFDM_pkt<<4);
UndecoratedSmoothedPWDB = (Weighting*UndecoratedSmoothedOFDM+(64-Weighting)*UndecoratedSmoothedCCK)>>6;
}
else
{
if(pEntry->rssi_stat.ValidBit != 0)
if (pEntry->rssi_stat.ValidBit != 0)
UndecoratedSmoothedPWDB = (OFDM_pkt*UndecoratedSmoothedOFDM+(pEntry->rssi_stat.ValidBit-OFDM_pkt)*UndecoratedSmoothedCCK)/pEntry->rssi_stat.ValidBit;
else
UndecoratedSmoothedPWDB = 0;
@ -778,9 +778,9 @@ ODM_PhyStatusQuery_92CSeries(
pPhyStatus,
pPktinfo);
if( pDM_Odm->RSSI_test == true) {
if ( pDM_Odm->RSSI_test == true) {
/* Select the packets to do RSSI checking for antenna switching. */
if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon )
if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon )
ODM_SwAntDivChkPerPktRssi(pDM_Odm,pPktinfo->StationID,pPhyInfo);
} else {
odm_Process_RSSIForDM(pDM_Odm,pPhyInfo,pPktinfo);
@ -842,7 +842,7 @@ ODM_ConfigRFWithHeaderFile(
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===>ODM_ConfigRFWithHeaderFile\n"));
if (pDM_Odm->SupportICType == ODM_RTL8188E)
{
if(IS_VENDOR_8188E_I_CUT_SERIES(pDM_Odm->Adapter))
if (IS_VENDOR_8188E_I_CUT_SERIES(pDM_Odm->Adapter))
READ_AND_CONFIG(8188E,_RadioA_1T_ICUT_);
else
READ_AND_CONFIG(8188E,_RadioA_1T_);
@ -863,18 +863,18 @@ ODM_ConfigBBWithHeaderFile(
ODM_BB_Config_Type ConfigType
)
{
if(pDM_Odm->SupportICType == ODM_RTL8188E) {
if(ConfigType == CONFIG_BB_PHY_REG) {
if(IS_VENDOR_8188E_I_CUT_SERIES(pDM_Odm->Adapter))
if (pDM_Odm->SupportICType == ODM_RTL8188E) {
if (ConfigType == CONFIG_BB_PHY_REG) {
if (IS_VENDOR_8188E_I_CUT_SERIES(pDM_Odm->Adapter))
READ_AND_CONFIG(8188E,_PHY_REG_1T_ICUT_);
else
READ_AND_CONFIG(8188E,_PHY_REG_1T_);
} else if(ConfigType == CONFIG_BB_AGC_TAB) {
if(IS_VENDOR_8188E_I_CUT_SERIES(pDM_Odm->Adapter))
} else if (ConfigType == CONFIG_BB_AGC_TAB) {
if (IS_VENDOR_8188E_I_CUT_SERIES(pDM_Odm->Adapter))
READ_AND_CONFIG(8188E,_AGC_TAB_1T_ICUT_);
else
READ_AND_CONFIG(8188E,_AGC_TAB_1T_);
} else if(ConfigType == CONFIG_BB_PHY_REG_PG) {
} else if (ConfigType == CONFIG_BB_PHY_REG_PG) {
READ_AND_CONFIG(8188E,_PHY_REG_PG_);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8188EPHY_REG_PGArray\n"));
}
@ -889,7 +889,7 @@ ODM_ConfigMACWithHeaderFile(
{
u8 result = HAL_STATUS_SUCCESS;
if (pDM_Odm->SupportICType == ODM_RTL8188E) {
if(IS_VENDOR_8188E_I_CUT_SERIES(pDM_Odm->Adapter))
if (IS_VENDOR_8188E_I_CUT_SERIES(pDM_Odm->Adapter))
READ_AND_CONFIG(8188E,_MAC_REG_ICUT_);
else
result =READ_AND_CONFIG(8188E,_MAC_REG_);

68
hal/odm_RTL8188E.c
View file

@ -31,7 +31,7 @@ ODM_DIG_LowerBound_88E(
{
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
{
pDM_DigTable->rx_gain_range_min = (u8) pDM_DigTable->AntDiv_RSSI_max;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_DIG_LowerBound_88E(): pDM_DigTable->AntDiv_RSSI_max=%d\n",pDM_DigTable->AntDiv_RSSI_max));
@ -119,7 +119,7 @@ odm_TRX_HWAntDivInit(
ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT);
/* antenna mapping table */
if(!pDM_Odm->bIsMPChip) /* testchip */
if (!pDM_Odm->bIsMPChip) /* testchip */
{
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); /* Reg858[10:8]=3'b001 */
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); /* Reg858[13:11]=3'b010 */
@ -179,9 +179,9 @@ odm_FastAntTrainingInit(
ODM_SetBBReg(pDM_Odm, 0xca4 , bMaskDWord, 0x000000a0);
/* antenna mapping table */
if(AntCombination == 2)
if (AntCombination == 2)
{
if(!pDM_Odm->bIsMPChip) /* testchip */
if (!pDM_Odm->bIsMPChip) /* testchip */
{
ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1); /* Reg858[10:8]=3'b001 */
ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 2); /* Reg858[13:11]=3'b010 */
@ -192,9 +192,9 @@ odm_FastAntTrainingInit(
ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2);
}
}
else if(AntCombination == 7)
else if (AntCombination == 7)
{
if(!pDM_Odm->bIsMPChip) /* testchip */
if (!pDM_Odm->bIsMPChip) /* testchip */
{
ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); /* Reg858[10:8]=3'b000 */
ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 1); /* Reg858[13:11]=3'b001 */
@ -242,7 +242,7 @@ ODM_AntennaDiversityInit_88E(
PDM_ODM_T pDM_Odm
)
{
if(pDM_Odm->SupportICType != ODM_RTL8188E)
if (pDM_Odm->SupportICType != ODM_RTL8188E)
return;
/* ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d, pHalData->AntDivCfg=%d\n", */
@ -250,11 +250,11 @@ ODM_AntennaDiversityInit_88E(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d\n",pDM_Odm->AntDivType));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->bIsMPChip=%s\n",(pDM_Odm->bIsMPChip?"true":"false")));
if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)
if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)
odm_RX_HWAntDivInit(pDM_Odm);
else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
else if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
odm_TRX_HWAntDivInit(pDM_Odm);
else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)
else if (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)
odm_FastAntTrainingInit(pDM_Odm);
}
@ -265,10 +265,10 @@ ODM_UpdateRxIdleAnt_88E(PDM_ODM_T pDM_Odm, u8 Ant)
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
u32 DefaultAnt, OptionalAnt;
if(pDM_FatTable->RxIdleAnt != Ant)
if (pDM_FatTable->RxIdleAnt != Ant)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Update Rx Idle Ant\n"));
if(Ant == MAIN_ANT)
if (Ant == MAIN_ANT)
{
DefaultAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?MAIN_ANT_CG_TRX:MAIN_ANT_CGCS_RX;
OptionalAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?AUX_ANT_CG_TRX:AUX_ANT_CGCS_RX;
@ -279,7 +279,7 @@ ODM_UpdateRxIdleAnt_88E(PDM_ODM_T pDM_Odm, u8 Ant)
OptionalAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?MAIN_ANT_CG_TRX:MAIN_ANT_CGCS_RX;
}
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
{
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); /* Default RX */
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); /* Optional RX */
@ -287,7 +287,7 @@ ODM_UpdateRxIdleAnt_88E(PDM_ODM_T pDM_Odm, u8 Ant)
ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11N , BIT6|BIT7, DefaultAnt); /* Resp Tx */
}
else if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)
else if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)
{
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); /* Default RX */
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); /* Optional RX */
@ -305,7 +305,7 @@ odm_UpdateTxAnt_88E(PDM_ODM_T pDM_Odm, u8 Ant, u32 MacId)
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
u8 TargetAnt;
if(Ant == MAIN_ANT)
if (Ant == MAIN_ANT)
TargetAnt = MAIN_ANT_CG_TRX;
else
TargetAnt = AUX_ANT_CG_TRX;
@ -329,7 +329,7 @@ ODM_SetTxAntByTxInfo_88E(
{
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
if((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
{
SET_TX_DESC_ANTSEL_A_88E(pDesc, pDM_FatTable->antsel_a[macId]);
SET_TX_DESC_ANTSEL_B_88E(pDesc, pDM_FatTable->antsel_b[macId]);
@ -348,9 +348,9 @@ ODM_AntselStatistics_88E(
)
{
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
{
if(antsel_tr_mux == MAIN_ANT_CG_TRX)
if (antsel_tr_mux == MAIN_ANT_CG_TRX)
{
pDM_FatTable->MainAnt_Sum[MacId]+=RxPWDBAll;
@ -363,9 +363,9 @@ ODM_AntselStatistics_88E(
}
}
else if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)
else if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)
{
if(antsel_tr_mux == MAIN_ANT_CGCS_RX)
if (antsel_tr_mux == MAIN_ANT_CGCS_RX)
{
pDM_FatTable->MainAnt_Sum[MacId]+=RxPWDBAll;
@ -398,7 +398,7 @@ odm_HWAntDiv(
for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
{
pEntry = pDM_Odm->pODM_StaInfo[i];
if(IS_STA_VALID(pEntry))
if (IS_STA_VALID(pEntry))
{
/* 2 Caculate RSSI per Antenna */
Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0;
@ -410,19 +410,19 @@ odm_HWAntDiv(
/* 2 Select MaxRSSI for DIG */
LocalMaxRSSI = (Main_RSSI>Aux_RSSI)?Main_RSSI:Aux_RSSI;
if((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40))
if ((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40))
AntDivMaxRSSI = LocalMaxRSSI;
if(LocalMaxRSSI > MaxRSSI)
if (LocalMaxRSSI > MaxRSSI)
MaxRSSI = LocalMaxRSSI;
/* 2 Select RX Idle Antenna */
if((pDM_FatTable->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0))
if ((pDM_FatTable->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0))
Main_RSSI = Aux_RSSI;
else if((pDM_FatTable->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0))
else if ((pDM_FatTable->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0))
Aux_RSSI = Main_RSSI;
LocalMinRSSI = (Main_RSSI>Aux_RSSI)?Aux_RSSI:Main_RSSI;
if(LocalMinRSSI < MinRSSI)
if (LocalMinRSSI < MinRSSI)
{
MinRSSI = LocalMinRSSI;
RxIdleAnt = TargetAnt;
@ -431,7 +431,7 @@ odm_HWAntDiv(
#else
/* 2 Select TRX Antenna */
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
odm_UpdateTxAnt_88E(pDM_Odm, TargetAnt, i);
#endif
}
@ -454,32 +454,32 @@ ODM_AntennaDiversity_88E(
)
{
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
if((pDM_Odm->SupportICType != ODM_RTL8188E) || (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)))
if ((pDM_Odm->SupportICType != ODM_RTL8188E) || (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)))
{
/* ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E: Not Support 88E AntDiv\n")); */
return;
}
if(!pDM_Odm->bLinked)
if (!pDM_Odm->bLinked)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E(): No Link.\n"));
if(pDM_FatTable->bBecomeLinked == true)
if (pDM_FatTable->bBecomeLinked == true)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn off HW AntDiv\n"));
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); /* RegC50[7]=1'b1 enable HW AntDiv */
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 0); /* Enable CCK AntDiv */
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); /* Reg80c[21]=1'b0 from TX Reg */
pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;
}
return;
} else {
if(pDM_FatTable->bBecomeLinked ==false) {
if (pDM_FatTable->bBecomeLinked ==false) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn on HW AntDiv\n"));
/* Because HW AntDiv is disabled before Link, we enable HW AntDiv after link */
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 1); /* RegC50[7]=1'b1 enable HW AntDiv */
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 1); /* Enable CCK AntDiv */
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) {
if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) {
#if TX_BY_REG
ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); /* Reg80c[21]=1'b0 from Reg */
#else
@ -492,7 +492,7 @@ ODM_AntennaDiversity_88E(
if((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV))
if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV))
odm_HWAntDiv(pDM_Odm);
}

2
hal/odm_RegConfig8188E.c
View file

@ -29,7 +29,7 @@ odm_ConfigRFReg_8188E(
u32 RegAddr
)
{
if(Addr == 0xffe)
if (Addr == 0xffe)
{
ODM_sleep_ms(50);
}

20
hal/odm_debug.h
View file

@ -104,31 +104,31 @@
#if DBG
#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \
if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
if (((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
{ \
if(pDM_Odm->SupportICType == ODM_RTL8192C) \
if (pDM_Odm->SupportICType == ODM_RTL8192C) \
DbgPrint("[ODM-92C] "); \
else if(pDM_Odm->SupportICType == ODM_RTL8192D) \
else if (pDM_Odm->SupportICType == ODM_RTL8192D) \
DbgPrint("[ODM-92D] "); \
else if(pDM_Odm->SupportICType == ODM_RTL8723A) \
else if (pDM_Odm->SupportICType == ODM_RTL8723A) \
DbgPrint("[ODM-8723A] "); \
else if(pDM_Odm->SupportICType == ODM_RTL8188E) \
else if (pDM_Odm->SupportICType == ODM_RTL8188E) \
DbgPrint("[ODM-8188E] "); \
else if(pDM_Odm->SupportICType == ODM_RTL8812) \
else if (pDM_Odm->SupportICType == ODM_RTL8812) \
DbgPrint("[ODM-8812] "); \
else if(pDM_Odm->SupportICType == ODM_RTL8821) \
else if (pDM_Odm->SupportICType == ODM_RTL8821) \
DbgPrint("[ODM-8821] "); \
RT_PRINTK fmt; \
}
#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) \
if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
if (((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
{ \
RT_PRINTK fmt; \
}
#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \
if(!(expr)) { \
if (!(expr)) { \
DbgPrint( "Assertion failed! %s at ......\n", #expr); \
DbgPrint( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \
RT_PRINTK fmt; \
@ -139,7 +139,7 @@
#define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __FUNCTION__, str); }
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) \
if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
if (((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
{ \
int __i; \
u8 * __ptr = (u8 *)ptr; \

60
hal/rtl8188e_cmd.c
View file

@ -50,7 +50,7 @@ static u8 _is_fw_read_cmd_down(struct adapter* padapter, u8 msgbox_num)
do{
valid = rtw_read8(padapter,REG_HMETFR) & BIT(msgbox_num);
if(0 == valid ){
if (0 == valid ){
read_down = true;
}
}while( (!read_down) && (retry_cnts--));
@ -88,7 +88,7 @@ static s32 FillH2CCmd_88E(struct adapter *padapter, u8 ElementID, u32 CmdLen, u8
padapter = GET_PRIMARY_ADAPTER(padapter);
pHalData = GET_HAL_DATA(padapter);
if(padapter->bFWReady == false)
if (padapter->bFWReady == false)
{
DBG_8192C("FillH2CCmd_88E(): return H2C cmd because fw is not ready\n");
return ret;
@ -109,14 +109,14 @@ static s32 FillH2CCmd_88E(struct adapter *padapter, u8 ElementID, u32 CmdLen, u8
do{
h2c_box_num = pHalData->LastHMEBoxNum;
if(!_is_fw_read_cmd_down(padapter, h2c_box_num)){
if (!_is_fw_read_cmd_down(padapter, h2c_box_num)){
DBG_8192C(" fw read cmd failed...\n");
goto exit;
}
*(u8*)(&h2c_cmd) = ElementID;
if(CmdLen<=3)
if (CmdLen<=3)
{
memcpy((u8*)(&h2c_cmd)+1, pCmdBuffer, CmdLen );
}
@ -169,7 +169,7 @@ u8 rtl8188e_set_rssi_cmd(struct adapter*padapter, u8 *param)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
;
if(pHalData->fw_ractrl == true){
if (pHalData->fw_ractrl == true){
}else{
DBG_8192C("==>%s fw dont support RA\n",__FUNCTION__);
res=_FAIL;
@ -183,7 +183,7 @@ u8 rtl8188e_set_raid_cmd(struct adapter*padapter, u32 mask)
u8 res=_SUCCESS;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
;
if(pHalData->fw_ractrl == true){
if (pHalData->fw_ractrl == true){
__le32 lmask;
memset(buf, 0, 3);
@ -212,7 +212,7 @@ void rtl8188e_Add_RateATid(struct adapter *pAdapter, u32 bitmap, u8 arg, u8 rssi
raid = (bitmap>>28) & 0x0f;
bitmap &=0x0fffffff;
if(rssi_level != DM_RATR_STA_INIT)
if (rssi_level != DM_RATR_STA_INIT)
bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv, macid, bitmap, rssi_level);
bitmap |= ((raid<<28)&0xf0000000);
@ -232,7 +232,7 @@ void rtl8188e_Add_RateATid(struct adapter *pAdapter, u32 bitmap, u8 arg, u8 rssi
__FUNCTION__,macid ,raid ,bitmap, shortGIrate);
#if(RATE_ADAPTIVE_SUPPORT == 1)
#if (RATE_ADAPTIVE_SUPPORT == 1)
ODM_RA_UpdateRateInfo_8188E(
&(pHalData->odmpriv),
macid,
@ -286,7 +286,7 @@ void rtl8188e_set_FwPwrMode_cmd(struct adapter *padapter, u8 Mode)
H2CSetPwrMode.bAllQueueUAPSD = padapter->registrypriv.uapsd_enable;
if(Mode > 0)
if (Mode > 0)
{
H2CSetPwrMode.PwrState = 0x00;/* AllON(0x0C), RFON(0x04), RFOFF(0x00) */
#ifdef CONFIG_EXT_CLK
@ -312,13 +312,13 @@ void rtl8188e_set_FwMediaStatus_cmd(struct adapter *padapter, __le16 mstatus_rpt
DBG_871X("### %s: MStatus=%x MACID=%d\n", __FUNCTION__,opmode,macid);
FillH2CCmd_88E(padapter, H2C_COM_MEDIA_STATUS_RPT, sizeof(mst_rpt), (u8 *)&mst_rpt);
if(macid > 31){
if (macid > 31){
macid = macid-32;
reg_macid_no_link = REG_MACID_NO_LINK_1;
}
/* Delete select macid (MACID 0~63) from queue list. */
if(opmode == 1)/* 1:connect */
if (opmode == 1)/* 1:connect */
{
rtw_write32(padapter,reg_macid_no_link, (rtw_read32(padapter,reg_macid_no_link) & (~BIT(macid))));
}
@ -376,7 +376,7 @@ static void ConstructBeacon(struct adapter *padapter, u8 *pframe, u32 *pLength)
pframe += 2;
pktlen += 2;
if( (pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
if ( (pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
{
/* DBG_871X("ie len=%d\n", cur_network->IELength); */
pktlen += cur_network->IELength - sizeof(struct ndis_802_11_fixed_ies);
@ -397,7 +397,7 @@ static void ConstructBeacon(struct adapter *padapter, u8 *pframe, u32 *pLength)
/* DS parameter set */
pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen);
if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)
if ( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)
{
u32 ATIMWindow;
/* IBSS Parameter Set... */
@ -561,7 +561,7 @@ CheckFwRsvdPageContent(
HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter);
u32 MaxBcnPageNum;
if(pHalData->FwRsvdPageStartOffset != 0)
if (pHalData->FwRsvdPageStartOffset != 0)
{
/*MaxBcnPageNum = PageNum_128(pMgntInfo->MaxBeaconSize);
RT_ASSERT((MaxBcnPageNum <= pHalData->FwRsvdPageStartOffset),
@ -708,7 +708,7 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus)
DBG_871X("%s mstatus(%x)\n", __FUNCTION__,mstatus);
if(mstatus == 1) {
if (mstatus == 1) {
/* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. */
/* Suggested by filen. Added by tynli. */
rtw_write16(padapter, REG_BCN_PSR_RPT, (0xC000|pmlmeinfo->aid));
@ -730,7 +730,7 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus)
rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)&(~BIT(3)));
rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(4));
if(pHalData->RegFwHwTxQCtrl&BIT6)
if (pHalData->RegFwHwTxQCtrl&BIT6)
{
DBG_871X("HalDownloadRSVDPage(): There is an Adapter is sending beacon.\n");
bSendBeacon = true;
@ -761,10 +761,10 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus)
}while(!bcn_valid && DLBcnCount<=100 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped);
/* RT_ASSERT(bcn_valid, ("HalDownloadRSVDPage88ES(): 1 Download RSVD page failed!\n")); */
if(padapter->bSurpriseRemoved || padapter->bDriverStopped)
if (padapter->bSurpriseRemoved || padapter->bDriverStopped)
{
}
else if(!bcn_valid)
else if (!bcn_valid)
DBG_871X("%s: 1 Download RSVD page failed! DLBcnCount:%u, poll:%u\n", __FUNCTION__ ,DLBcnCount, poll);
else
DBG_871X("%s: 1 Download RSVD success! DLBcnCount:%u, poll:%u\n", __FUNCTION__, DLBcnCount, poll);
@ -774,10 +774,10 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus)
/* At run time, we cannot get the Tx Desc until it is released in TxHandleInterrupt() so we will return */
/* the beacon TCB in the following code. 2011.11.23. by tynli. */
/* */
/* if(bcn_valid && padapter->bEnterPnpSleep) */
if(0)
/* if (bcn_valid && padapter->bEnterPnpSleep) */
if (0)
{
if(bSendBeacon)
if (bSendBeacon)
{
rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
DLBcnCount = 0;
@ -798,10 +798,10 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus)
}while(!bcn_valid && DLBcnCount<=100 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped);
/* RT_ASSERT(bcn_valid, ("HalDownloadRSVDPage(): 2 Download RSVD page failed!\n")); */
if(padapter->bSurpriseRemoved || padapter->bDriverStopped)
if (padapter->bSurpriseRemoved || padapter->bDriverStopped)
{
}
else if(!bcn_valid)
else if (!bcn_valid)
DBG_871X("%s: 2 Download RSVD page failed! DLBcnCount:%u, poll:%u\n", __FUNCTION__ ,DLBcnCount, poll);
else
DBG_871X("%s: 2 Download RSVD success! DLBcnCount:%u, poll:%u\n", __FUNCTION__, DLBcnCount, poll);
@ -819,7 +819,7 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus)
/* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
/* the beacon cannot be sent by HW. */
/* 2010.06.23. Added by tynli. */
if(bSendBeacon)
if (bSendBeacon)
{
rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl|BIT6));
pHalData->RegFwHwTxQCtrl |= BIT6;
@ -828,7 +828,7 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus)
/* */
/* Update RSVD page location H2C to Fw. */
/* */
if(bcn_valid)
if (bcn_valid)
{
rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
DBG_871X("Set RSVD page location to Fw.\n");
@ -836,7 +836,7 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus)
}
/* Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli. */
/* if(!padapter->bEnterPnpSleep) */
/* if (!padapter->bEnterPnpSleep) */
{
/* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */
pHalData->RegCR_1 &= (~BIT0);
@ -863,7 +863,7 @@ void rtl8188e_set_p2p_ps_offload_cmd(struct adapter* padapter, u8 p2p_ps_state)
case P2P_PS_ENABLE:
DBG_8192C("P2P_PS_ENABLE\n");
/* update CTWindow value. */
if( pwdinfo->ctwindow > 0 )
if ( pwdinfo->ctwindow > 0 )
{
p2p_ps_offload->CTWindow_En = 1;
rtw_write8(padapter, REG_P2P_CTWIN, pwdinfo->ctwindow);
@ -874,7 +874,7 @@ void rtl8188e_set_p2p_ps_offload_cmd(struct adapter* padapter, u8 p2p_ps_state)
{
/* To control the register setting for which NOA */
rtw_write8(padapter, REG_NOA_DESC_SEL, (i << 4));
if(i == 0)
if (i == 0)
p2p_ps_offload->NoA0_En = 1;
else
p2p_ps_offload->NoA1_En = 1;
@ -893,14 +893,14 @@ void rtl8188e_set_p2p_ps_offload_cmd(struct adapter* padapter, u8 p2p_ps_state)
rtw_write8(padapter, REG_NOA_DESC_COUNT, pwdinfo->noa_count[i]);
}
if( (pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0) )
if ( (pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0) )
{
/* rst p2p circuit */
rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(4));
p2p_ps_offload->Offload_En = 1;
if(pwdinfo->role == P2P_ROLE_GO)
if (pwdinfo->role == P2P_ROLE_GO)
{
p2p_ps_offload->role= 1;
p2p_ps_offload->AllStaSleep = 0;

30
hal/rtl8188e_dm.c
View file

@ -59,7 +59,7 @@ static void dm_CheckPbcGPIO(struct adapter *padapter)
u8 tmp1byte;
u8 bPbcPressed = false;
if(!padapter->registrypriv.hw_wps_pbc)
if (!padapter->registrypriv.hw_wps_pbc)
return;
tmp1byte = rtw_read8(padapter, GPIO_IO_SEL);
@ -82,7 +82,7 @@ static void dm_CheckPbcGPIO(struct adapter *padapter)
{
bPbcPressed = true;
}
if( true == bPbcPressed)
if ( true == bPbcPressed)
{
/* Here we only set bPbcPressed to true */
/* After trigger PBC, the variable will be set to false */
@ -141,7 +141,7 @@ static void Init_ODM_ComInfo_88E(struct adapter *Adapter)
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_PLATFORM,ODM_CE);
if(Adapter->interface_type == RTW_GSPI )
if (Adapter->interface_type == RTW_GSPI )
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,ODM_ITRF_SDIO);
else
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,Adapter->interface_type);/* RTL871X_HCI_TYPE */
@ -161,13 +161,13 @@ static void Init_ODM_ComInfo_88E(struct adapter *Adapter)
ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_BWIFI_TEST,Adapter->registrypriv.wifi_spec);
if(pHalData->rf_type == RF_1T1R){
if (pHalData->rf_type == RF_1T1R){
ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_1T1R);
}
else if(pHalData->rf_type == RF_2T2R){
else if (pHalData->rf_type == RF_2T2R){
ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_2T2R);
}
else if(pHalData->rf_type == RF_1T2R){
else if (pHalData->rf_type == RF_1T2R){
ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_1T2R);
}
@ -204,7 +204,7 @@ static void Update_ODM_ComInfo_88E(struct adapter *Adapter)
pdmpriv->InitODMFlag |= ODM_MAC_EDCA_TURBO;
}
if(pHalData->AntDivCfg)
if (pHalData->AntDivCfg)
pdmpriv->InitODMFlag |= ODM_BB_ANT_DIV;
#if (MP_DRIVER==1)
@ -288,11 +288,11 @@ rtl8188e_HalDmWatchDog(
#ifdef CONFIG_P2P
/* Fw is under p2p powersaving mode, driver should stop dynamic mechanism. */
/* modifed by thomas. 2011.06.11. */
if(Adapter->wdinfo.p2p_ps_mode)
if (Adapter->wdinfo.p2p_ps_mode)
bFwPSAwake = false;
#endif /* CONFIG_P2P */
if( (hw_init_completed == true)
if ( (hw_init_completed == true)
&& ((!bFwCurrentInPSMode) && bFwPSAwake))
{
/* */
@ -308,7 +308,7 @@ rtl8188e_HalDmWatchDog(
u8 bLinked=false;
u8 bsta_state = false;
if(rtw_linked_check(Adapter))
if (rtw_linked_check(Adapter))
bLinked = true;
ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_LINK, bLinked);
@ -355,12 +355,12 @@ void AntDivCompare8188E(struct adapter *Adapter, struct wlan_bssid_ex *dst, stru
/* struct adapter *Adapter = pDM_Odm->Adapter ; */
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
if(0 != pHalData->AntDivCfg )
if (0 != pHalData->AntDivCfg )
{
/* DBG_8192C("update_network=> orgRSSI(%d)(%d),newRSSI(%d)(%d)\n",dst->Rssi,query_rx_pwr_percentage(dst->Rssi), */
/* src->Rssi,query_rx_pwr_percentage(src->Rssi)); */
/* select optimum_antenna for before linked =>For antenna diversity */
if(dst->Rssi >= src->Rssi )/* keep org parameter */
if (dst->Rssi >= src->Rssi )/* keep org parameter */
{
src->Rssi = dst->Rssi;
src->PhyInfo.Optimum_antenna = dst->PhyInfo.Optimum_antenna;
@ -378,19 +378,19 @@ u8 AntDivBeforeLink8188E(struct adapter *Adapter )
struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
/* Condition that does not need to use antenna diversity. */
if(pHalData->AntDivCfg==0)
if (pHalData->AntDivCfg==0)
{
/* DBG_8192C("odm_AntDivBeforeLink8192C(): No AntDiv Mechanism.\n"); */
return false;
}
if(check_fwstate(pmlmepriv, _FW_LINKED) == true)
if (check_fwstate(pmlmepriv, _FW_LINKED) == true)
{
return false;
}
if(pDM_SWAT_Table->SWAS_NoLink_State == 0){
if (pDM_SWAT_Table->SWAS_NoLink_State == 0){
/* switch channel */
pDM_SWAT_Table->SWAS_NoLink_State = 1;
pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A;

386
hal/rtl8188e_hal_init.c
View file

File diff suppressed because it is too large Load diff

170
hal/rtl8188e_phycfg.c
View file

@ -77,7 +77,7 @@ phy_CalculateBitShift(
return (i);
}
#if(SIC_ENABLE == 1)
#if (SIC_ENABLE == 1)
static bool
sic_IsSICReady(
struct adapter *Adapter
@ -89,22 +89,22 @@ sic_IsSICReady(
while(1)
{
if(retryCnt++ >= SIC_MAX_POLL_CNT)
if (retryCnt++ >= SIC_MAX_POLL_CNT)
{
/* RTPRINT(FPHY, (PHY_SICR|PHY_SICW), ("[SIC], sic_IsSICReady() return false\n")); */
return false;
}
/* if(RT_SDIO_CANNOT_IO(Adapter)) */
/* if (RT_SDIO_CANNOT_IO(Adapter)) */
/* return false; */
sic_cmd = rtw_read8(Adapter, SIC_CMD_REG);
/* sic_cmd = PlatformEFIORead1Byte(Adapter, SIC_CMD_REG); */
#if(SIC_HW_SUPPORT == 1)
#if (SIC_HW_SUPPORT == 1)
sic_cmd &= 0xf0; /* [7:4] */
#endif
/* RTPRINT(FPHY, (PHY_SICR|PHY_SICW), ("[SIC], sic_IsSICReady(), readback 0x%x=0x%x\n", SIC_CMD_REG, sic_cmd)); */
if(sic_cmd == SIC_CMD_READY)
if (sic_cmd == SIC_CMD_READY)
return true;
else
{
@ -127,9 +127,9 @@ sic_Read4Byte(
/* RTPRINT(FPHY, PHY_SICR, ("[SIC], sic_Read4Byte(): read offset(%#x)\n", offset)); */
if(sic_IsSICReady(Adapter))
if (sic_IsSICReady(Adapter))
{
#if(SIC_HW_SUPPORT == 1)
#if (SIC_HW_SUPPORT == 1)
rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_PREREAD);
/* PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_PREREAD); */
/* RTPRINT(FPHY, PHY_SICR, ("write cmdreg 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_PREREAD)); */
@ -149,7 +149,7 @@ sic_Read4Byte(
rtw_udelay_os(50);
/* PlatformStallExecution(50); */
}
if(sic_IsSICReady(Adapter))
if (sic_IsSICReady(Adapter))
{
u4ret = rtw_read32(Adapter, SIC_DATA_REG);
/* u4ret = PlatformEFIORead4Byte(Adapter, SIC_DATA_REG); */
@ -170,9 +170,9 @@ sic_Write4Byte(
{
u8 retry = 6;
if(sic_IsSICReady(Adapter))
if (sic_IsSICReady(Adapter))
{
#if(SIC_HW_SUPPORT == 1)
#if (SIC_HW_SUPPORT == 1)
rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_PREWRITE);
#endif
rtw_write8(Adapter, SIC_ADDR_REG, (u8)(offset&0xff));
@ -205,7 +205,7 @@ SIC_SetBBReg(
/* RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg(), mask=0x%x, addr[0x%x]=0x%x\n", BitMask, RegAddr, Data)); */
if(BitMask!= bMaskDWord){/* if not "double word" write */
if (BitMask!= bMaskDWord){/* if not "double word" write */
OriginalValue = sic_Read4Byte(Adapter, RegAddr);
/* BitShift = sic_CalculateBitShift(BitMask); */
BitShift = phy_CalculateBitShift(BitMask);
@ -251,7 +251,7 @@ SIC_Init(
/* Here we need to write 0x1b8~0x1bf = 0 after fw is downloaded */
/* because for 8723E at beginning 0x1b8=0x1e, that will cause */
/* sic always not be ready */
#if(SIC_HW_SUPPORT == 1)
#if (SIC_HW_SUPPORT == 1)
/* RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_Init(), write 0x%x = 0x%x\n", */
/* SIC_INIT_REG, SIC_INIT_VAL)); */
rtw_write8(Adapter, SIC_INIT_REG, SIC_INIT_VAL);
@ -308,7 +308,7 @@ rtl8188e_PHY_QueryBBReg(
return 0;
#endif
#if(SIC_ENABLE == 1)
#if (SIC_ENABLE == 1)
return SIC_QueryBBReg(Adapter, RegAddr, BitMask);
#endif
@ -355,12 +355,12 @@ rtl8188e_PHY_SetBBReg(
return;
#endif
#if(SIC_ENABLE == 1)
#if (SIC_ENABLE == 1)
SIC_SetBBReg(Adapter, RegAddr, BitMask, Data);
return;
#endif
if(BitMask!= bMaskDWord){/* if not "double word" write */
if (BitMask!= bMaskDWord){/* if not "double word" write */
OriginalValue = rtw_read32(Adapter, RegAddr);
BitShift = phy_CalculateBitShift(BitMask);
Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask));
@ -417,7 +417,7 @@ phy_RFSerialRead(
NewOffset = Offset;
/* 2009/06/17 MH We can not execute IO for power save or other accident mode. */
/* if(RT_CANNOT_IO(Adapter)) */
/* if (RT_CANNOT_IO(Adapter)) */
/* */
/* RTPRINT(FPHY, PHY_RFR, ("phy_RFSerialRead return all one\n")); */
/* return 0xFFFFFFFF; */
@ -427,7 +427,7 @@ phy_RFSerialRead(
/* For RF A/B write 0x824/82c(does not work in the future) */
/* We must use 0x824 for RF A and B to execute read trigger */
tmplong = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord);
if(eRFPath == RF_PATH_A)
if (eRFPath == RF_PATH_A)
tmplong2 = tmplong;
else
tmplong2 = PHY_QueryBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord);
@ -443,12 +443,12 @@ phy_RFSerialRead(
/* PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge); */
rtw_udelay_os(10);/* PlatformStallExecution(10); */
if(eRFPath == RF_PATH_A)
if (eRFPath == RF_PATH_A)
RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT8);
else if(eRFPath == RF_PATH_B)
else if (eRFPath == RF_PATH_B)
RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1, BIT8);
if(RfPiEnable)
if (RfPiEnable)
{ /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);
/* DBG_8192C("Readback from RF-PI : 0x%x\n", retValue); */
@ -680,7 +680,7 @@ s32 PHY_MACConfig8188E(struct adapter *Adapter)
pszMACRegFile = sz8188EMACRegFile;
/* Config MAC */
if(HAL_STATUS_FAILURE == ODM_ConfigMACWithHeaderFile(&pHalData->odmpriv))
if (HAL_STATUS_FAILURE == ODM_ConfigMACWithHeaderFile(&pHalData->odmpriv))
rtStatus = _FAIL;
/* 2010.07.13 AMPDU aggregation number B */
@ -863,107 +863,107 @@ storePwrIndexDiffRateOffset(
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
if(RegAddr == rTxAGC_A_Rate18_06)
if (RegAddr == rTxAGC_A_Rate18_06)
{
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0] = Data;
/* printk("MCSTxPowerLevelOriginalOffset[%d][0]-TxAGC_A_Rate18_06 = 0x%x\n", pHalData->pwrGroupCnt, */
/* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0]); */
}
if(RegAddr == rTxAGC_A_Rate54_24)
if (RegAddr == rTxAGC_A_Rate54_24)
{
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1] = Data;
/* printk("MCSTxPowerLevelOriginalOffset[%d][1]-TxAGC_A_Rate54_24 = 0x%x\n", pHalData->pwrGroupCnt, */
/* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1]); */
}
if(RegAddr == rTxAGC_A_CCK1_Mcs32)
if (RegAddr == rTxAGC_A_CCK1_Mcs32)
{
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6] = Data;
/* printk("MCSTxPowerLevelOriginalOffset[%d][6]-TxAGC_A_CCK1_Mcs32 = 0x%x\n", pHalData->pwrGroupCnt, */
/* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6]); */
}
if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0xffffff00)
if (RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0xffffff00)
{
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7] = Data;
/* printk("MCSTxPowerLevelOriginalOffset[%d][7]-TxAGC_B_CCK11_A_CCK2_11 = 0x%x\n", pHalData->pwrGroupCnt, */
/* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7]); */
}
if(RegAddr == rTxAGC_A_Mcs03_Mcs00)
if (RegAddr == rTxAGC_A_Mcs03_Mcs00)
{
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2] = Data;
/* printk("MCSTxPowerLevelOriginalOffset[%d][2]-TxAGC_A_Mcs03_Mcs00 = 0x%x\n", pHalData->pwrGroupCnt, */
/* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2]); */
}
if(RegAddr == rTxAGC_A_Mcs07_Mcs04)
if (RegAddr == rTxAGC_A_Mcs07_Mcs04)
{
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3] = Data;
/* printk("MCSTxPowerLevelOriginalOffset[%d][3]-TxAGC_A_Mcs07_Mcs04 = 0x%x\n", pHalData->pwrGroupCnt, */
/* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3]); */
}
if(RegAddr == rTxAGC_A_Mcs11_Mcs08)
if (RegAddr == rTxAGC_A_Mcs11_Mcs08)
{
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4] = Data;
/* printk("MCSTxPowerLevelOriginalOffset[%d][4]-TxAGC_A_Mcs11_Mcs08 = 0x%x\n", pHalData->pwrGroupCnt, */
/* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4]); */
}
if(RegAddr == rTxAGC_A_Mcs15_Mcs12)
if (RegAddr == rTxAGC_A_Mcs15_Mcs12)
{
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5] = Data;
/* printk("MCSTxPowerLevelOriginalOffset[%d][5]-TxAGC_A_Mcs15_Mcs12 = 0x%x\n", pHalData->pwrGroupCnt,pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5]); */
if(pHalData->rf_type== RF_1T1R)
if (pHalData->rf_type== RF_1T1R)
{
/* printk("pwrGroupCnt = %d\n", pHalData->pwrGroupCnt); */
pHalData->pwrGroupCnt++;
}
}
if(RegAddr == rTxAGC_B_Rate18_06)
if (RegAddr == rTxAGC_B_Rate18_06)
{
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8] = Data;
/* printk("MCSTxPowerLevelOriginalOffset[%d][8]-TxAGC_B_Rate18_06 = 0x%x\n", pHalData->pwrGroupCnt, */
/* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8]); */
}
if(RegAddr == rTxAGC_B_Rate54_24)
if (RegAddr == rTxAGC_B_Rate54_24)
{
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9] = Data;
/* printk("MCSTxPowerLevelOriginalOffset[%d][9]-TxAGC_B_Rate54_24 = 0x%x\n", pHalData->pwrGroupCnt, */
/* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9]); */
}
if(RegAddr == rTxAGC_B_CCK1_55_Mcs32)
if (RegAddr == rTxAGC_B_CCK1_55_Mcs32)
{
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14] = Data;
/* printk("MCSTxPowerLevelOriginalOffset[%d][14]-TxAGC_B_CCK1_55_Mcs32 = 0x%x\n", pHalData->pwrGroupCnt, */
/* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14]); */
}
if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0x000000ff)
if (RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0x000000ff)
{
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15] = Data;
/* printk("MCSTxPowerLevelOriginalOffset[%d][15]-TxAGC_B_CCK11_A_CCK2_11 = 0x%x\n", pHalData->pwrGroupCnt, */
/* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15]); */
}
if(RegAddr == rTxAGC_B_Mcs03_Mcs00)
if (RegAddr == rTxAGC_B_Mcs03_Mcs00)
{
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10] = Data;
/* printk("MCSTxPowerLevelOriginalOffset[%d][10]-TxAGC_B_Mcs03_Mcs00 = 0x%x\n", pHalData->pwrGroupCnt, */
/* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10]); */
}
if(RegAddr == rTxAGC_B_Mcs07_Mcs04)
if (RegAddr == rTxAGC_B_Mcs07_Mcs04)
{
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11] = Data;
/* printk("MCSTxPowerLevelOriginalOffset[%d][11]-TxAGC_B_Mcs07_Mcs04 = 0x%x\n", pHalData->pwrGroupCnt, */
/* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11]); */
}
if(RegAddr == rTxAGC_B_Mcs11_Mcs08)
if (RegAddr == rTxAGC_B_Mcs11_Mcs08)
{
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12] = Data;
/* printk("MCSTxPowerLevelOriginalOffset[%d][12]-TxAGC_B_Mcs11_Mcs08 = 0x%x\n", pHalData->pwrGroupCnt, */
/* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12]); */
}
if(RegAddr == rTxAGC_B_Mcs15_Mcs12)
if (RegAddr == rTxAGC_B_Mcs15_Mcs12)
{
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13] = Data;
/* printk("MCSTxPowerLevelOriginalOffset[%d][13]-TxAGC_B_Mcs15_Mcs12 = 0x%x\n", pHalData->pwrGroupCnt, */
/* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13]); */
if(pHalData->rf_type != RF_1T1R)
if (pHalData->rf_type != RF_1T1R)
{
/* printk("pwrGroupCnt = %d\n", pHalData->pwrGroupCnt); */
pHalData->pwrGroupCnt++;
@ -1063,10 +1063,10 @@ phy_BB8188E_Config_ParaFile(
/* 1. Read PHY_REG.TXT BB INIT!! */
/* We will seperate as 88C / 92C according to chip version */
/* */
if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
if (HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
rtStatus = _FAIL;
if(rtStatus != _SUCCESS){
if (rtStatus != _SUCCESS){
/* RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!")); */
goto phy_BB8190_Config_ParaFile_Fail;
}
@ -1074,7 +1074,7 @@ phy_BB8188E_Config_ParaFile(
/* */
/* 20100318 Joseph: Config 2T2R to 1T2R if necessary. */
/* */
/* if(pHalData->rf_type == RF_1T2R) */
/* if (pHalData->rf_type == RF_1T2R) */
/* */
/* phy_BB8192C_Config_1T(Adapter); */
/* DBG_8192C("phy_BB8188E_Config_ParaFile():Config to 1T!!\n"); */
@ -1086,19 +1086,19 @@ phy_BB8188E_Config_ParaFile(
if (pEEPROM->bautoload_fail_flag == false) {
pHalData->pwrGroupCnt = 0;
if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_PG))
if (HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_PG))
rtStatus = _FAIL;
}
if(rtStatus != _SUCCESS){
if (rtStatus != _SUCCESS){
/* RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!")); */
goto phy_BB8190_Config_ParaFile_Fail;
}
/* 3. BB AGC table Initialization */
if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
if (HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
rtStatus = _FAIL;
if(rtStatus != _SUCCESS){
if (rtStatus != _SUCCESS){
/* RT_TRACE(COMP_FPGA, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():AGC Table Fail\n")); */
goto phy_BB8190_Config_ParaFile_Fail;
}
@ -1226,7 +1226,7 @@ PHY_ConfigRFExternalPA(
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u16 i=0;
if(!pHalData->ExternalPA)
if (!pHalData->ExternalPA)
return rtStatus;
return rtStatus;
}
@ -1310,7 +1310,7 @@ PHY_CheckBBAndRFOK(
/* */
/* Check whether readback data is correct */
/* */
if(ulRegRead != WriteData[i])
if (ulRegRead != WriteData[i])
{
/* RT_TRACE(COMP_FPGA, DBG_LOUD, ("ulRegRead: %lx, WriteData: %lx\n", ulRegRead, WriteData[i])); */
rtStatus = _FAIL;
@ -1387,7 +1387,7 @@ phy_DbmToTxPwrIdx(
break;
}
if((PowerInDbm - Offset) > 0)
if ((PowerInDbm - Offset) > 0)
{
TxPwrIdx = (u8)((PowerInDbm - Offset) * 2);
}
@ -1397,7 +1397,7 @@ phy_DbmToTxPwrIdx(
}
/* Tx Power Index is too large. */
if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S)
if (TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S)
TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S;
return TxPwrIdx;
@ -1479,14 +1479,14 @@ PHY_GetTxPowerLevel8188E(
TxPwrLevel = pHalData->CurrentOfdm24GTxPwrIdx + pHalData->LegacyHTTxPowerDiff;
/* Compare with Legacy OFDM Tx power. */
if(phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm)
if (phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm)
TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel);
/* HT OFDM */
TxPwrLevel = pHalData->CurrentOfdm24GTxPwrIdx;
/* Compare with HT OFDM Tx power. */
if(phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm)
if (phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm)
TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel);
*powerlevel = TxPwrDbm;
@ -1507,14 +1507,14 @@ static void getTxPowerIndex88E(
u8 TxCount=0,path_nums;
if((RF_1T2R == pHalData->rf_type) ||(RF_1T1R ==pHalData->rf_type ))
if ((RF_1T2R == pHalData->rf_type) ||(RF_1T1R ==pHalData->rf_type ))
path_nums = 1;
else
path_nums = 2;
for(TxCount=0;TxCount< path_nums ;TxCount++)
{
if(TxCount==RF_PATH_A)
if (TxCount==RF_PATH_A)
{
/* 1. CCK */
cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index];
@ -1531,7 +1531,7 @@ static void getTxPowerIndex88E(
/* pHalData->BW20_24G_Diff[TxCount][RF_PATH_A], */
/* BW20PowerLevel[TxCount])); */
}
else if(TxCount==RF_PATH_B)
else if (TxCount==RF_PATH_B)
{
/* 1. CCK */
cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index];
@ -1596,7 +1596,7 @@ PHY_SetTxPowerLevel8188E(
u8 BW20PowerLevel[MAX_TX_COUNT], BW40PowerLevel[MAX_TX_COUNT];
u8 i=0;
/*
#if(MP_DRIVER == 1)
#if (MP_DRIVER == 1)
if (Adapter->registrypriv.mp_mode == 1)
return;
#endif
@ -1640,7 +1640,7 @@ PHY_UpdateTxPowerDbm8188E(
u8 CckTxPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, powerInDbm);
u8 OfdmTxPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, powerInDbm);
if(OfdmTxPwrIdx - pHalData->LegacyHTTxPowerDiff > 0)
if (OfdmTxPwrIdx - pHalData->LegacyHTTxPowerDiff > 0)
OfdmTxPwrIdx -= pHalData->LegacyHTTxPowerDiff;
else
OfdmTxPwrIdx = 0;
@ -1711,16 +1711,16 @@ _PHY_SetBWMode92C(
u8 regBwOpMode;
u8 regRRSR_RSC;
if(pHalData->rf_chip == RF_PSEUDO_11N)
if (pHalData->rf_chip == RF_PSEUDO_11N)
{
return;
}
/* There is no 40MHz mode in RF_8225. */
if(pHalData->rf_chip==RF_8225)
if (pHalData->rf_chip==RF_8225)
return;
if(Adapter->bDriverStopped)
if (Adapter->bDriverStopped)
return;
regBwOpMode = rtw_read8(Adapter, REG_BWOPMODE);
@ -1856,7 +1856,7 @@ PHY_SetBWMode8188E(
pHalData->nCur40MhzPrimeSC = Offset;
if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
_PHY_SetBWMode92C(Adapter);
else
pHalData->CurrentChannelBW = tmpBW;
@ -1899,7 +1899,7 @@ static void phy_SpurCalibration_8188E(
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
/* DbgPrint("===> phy_SpurCalibration_8188E CurrentChannelBW = %d, CurrentChannel = %d\n", pHalData->CurrentChannelBW, pHalData->CurrentChannel); */
if(pHalData->CurrentChannelBW == 0 && pHalData->CurrentChannel == 13){
if (pHalData->CurrentChannelBW == 0 && pHalData->CurrentChannel == 13){
PHY_SetBBReg(Adapter, rOFDM1_CFOTracking, BIT(28), 0x1); /* enable CSI Mask */
PHY_SetBBReg(Adapter, rOFDM1_csi_fix_mask, BIT(26)|BIT(25), 0x3); /* Fix CSI Mask Tone */
}
@ -1920,16 +1920,16 @@ PHY_SwChnl8188E( /* Call after initialization */
u8 tmpchannel = pHalData->CurrentChannel;
bool bResult = true;
if(pHalData->rf_chip == RF_PSEUDO_11N)
if (pHalData->rf_chip == RF_PSEUDO_11N)
{
/* pHalData->SwChnlInProgress=false; */
return; /* return immediately if it is peudo-phy */
}
/* if(pHalData->SwChnlInProgress) */
/* if (pHalData->SwChnlInProgress) */
/* return; */
/* if(pHalData->SetBWModeInProgress) */
/* if (pHalData->SetBWModeInProgress) */
/* return; */
/* */
@ -1956,7 +1956,7 @@ PHY_SwChnl8188E( /* Call after initialization */
/* */
/* pHalData->SwChnlInProgress = true; */
if(channel == 0)
if (channel == 0)
channel = 1;
pHalData->CurrentChannel=channel;
@ -1964,19 +1964,19 @@ PHY_SwChnl8188E( /* Call after initialization */
/* pHalData->SwChnlStage=0; */
/* pHalData->SwChnlStep=0; */
if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
{
_PHY_SwChnl8192C(Adapter, channel);
if (IS_VENDOR_8188E_I_CUT_SERIES(Adapter))
phy_SpurCalibration_8188E( Adapter);
if(bResult)
if (bResult)
{
/* RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress true schdule workitem done\n")); */
}
else
{
/* RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress false schdule workitem error\n")); */
/* if(IS_HARDWARE_TYPE_8192SU(Adapter)) */
/* if (IS_HARDWARE_TYPE_8192SU(Adapter)) */
/* */
/* pHalData->SwChnlInProgress = false; */
pHalData->CurrentChannel = tmpchannel;
@ -1987,7 +1987,7 @@ PHY_SwChnl8188E( /* Call after initialization */
else
{
/* RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress false driver sleep or unload\n")); */
/* if(IS_HARDWARE_TYPE_8192SU(Adapter)) */
/* if (IS_HARDWARE_TYPE_8192SU(Adapter)) */
/* */
/* pHalData->SwChnlInProgress = false; */
pHalData->CurrentChannel = tmpchannel;
@ -2022,12 +2022,12 @@ phy_SetSwChnlCmdArray(
{
SwChnlCmd* pCmd;
if(CmdTable == NULL)
if (CmdTable == NULL)
{
/* RT_ASSERT(false, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n")); */
return false;
}
if(CmdTableIdx >= CmdTableSz)
if (CmdTableIdx >= CmdTableSz)
{
/* RT_ASSERT(false, */
/* ("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%ld, CmdTableSz:%ld\n", */
@ -2073,22 +2073,22 @@ PHY_SwChnlPhy8192C( /* Only called during initialize */
/* RT_TRACE(COMP_SCAN | COMP_RM, DBG_LOUD, ("==>PHY_SwChnlPhy8192S(), switch from channel %d to channel %d.\n", pHalData->CurrentChannel, channel)); */
/* Cannot IO. */
/* if(RT_CANNOT_IO(Adapter)) */
/* if (RT_CANNOT_IO(Adapter)) */
/* return; */
/* Channel Switching is in progress. */
/* if(pHalData->SwChnlInProgress) */
/* if (pHalData->SwChnlInProgress) */
/* return; */
/* return immediately if it is peudo-phy */
if(pHalData->rf_chip == RF_PSEUDO_11N)
if (pHalData->rf_chip == RF_PSEUDO_11N)
{
/* pHalData->SwChnlInProgress=false; */
return;
}
/* pHalData->SwChnlInProgress = true; */
if( channel == 0)
if ( channel == 0)
channel = 1;
pHalData->CurrentChannel=channel;
@ -2154,7 +2154,7 @@ static void _PHY_SetRFPathSwitch(
{
u8 u1bTmp;
if(!pAdapter->hw_init_completed)
if (!pAdapter->hw_init_completed)
{
u1bTmp = rtw_read8(pAdapter, REG_LEDCFG2) | BIT7;
rtw_write8(pAdapter, REG_LEDCFG2, u1bTmp);
@ -2162,9 +2162,9 @@ static void _PHY_SetRFPathSwitch(
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
}
if(is2T)
if (is2T)
{
if(bMain)
if (bMain)
PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); /* 92C_Path_A */
else
PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); /* BT */
@ -2172,7 +2172,7 @@ static void _PHY_SetRFPathSwitch(
else
{
if(bMain)
if (bMain)
PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x2); /* Main */
else
PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x1); /* Aux */
@ -2187,25 +2187,25 @@ static bool _PHY_QueryRFPathSwitch(
bool is2T
)
{
/* if(is2T) */
/* if (is2T) */
/* return true; */
if(!pAdapter->hw_init_completed)
if (!pAdapter->hw_init_completed)
{
PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
}
if(is2T)
if (is2T)
{
if(PHY_QueryBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01)
if (PHY_QueryBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01)
return true;
else
return false;
}
else
{
if(PHY_QueryBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300) == 0x02)
if (PHY_QueryBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300) == 0x02)
return true;
else
return false;

60
hal/rtl8188e_rf6052.c
View file

@ -173,14 +173,14 @@ rtl8188e_PHY_RF6052SetCckTxPower(
TurboScanOff = true;
if(pmlmeext->sitesurvey_res.state == SCAN_PROCESS)
if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS)
{
TxAGC[RF_PATH_A] = 0x3f3f3f3f;
TxAGC[RF_PATH_B] = 0x3f3f3f3f;
TurboScanOff = true;/* disable turbo scan */
if(TurboScanOff)
if (TurboScanOff)
{
for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
{
@ -198,12 +198,12 @@ rtl8188e_PHY_RF6052SetCckTxPower(
/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */
if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
{
TxAGC[RF_PATH_A] = 0x10101010;
TxAGC[RF_PATH_B] = 0x10101010;
}
else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
{
TxAGC[RF_PATH_A] = 0x00000000;
TxAGC[RF_PATH_B] = 0x00000000;
@ -217,7 +217,7 @@ rtl8188e_PHY_RF6052SetCckTxPower(
(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
}
if(pHalData->EEPROMRegulatory==0)
if (pHalData->EEPROMRegulatory==0)
{
tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) +
(pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8);
@ -252,7 +252,7 @@ rtl8188e_PHY_RF6052SetCckTxPower(
ptr = (u8*)(&(TxAGC[idx1]));
for(idx2=0; idx2<4; idx2++)
{
if(*ptr > RF6052_MAX_TX_PWR)
if (*ptr > RF6052_MAX_TX_PWR)
*ptr = RF6052_MAX_TX_PWR;
ptr++;
}
@ -301,7 +301,7 @@ static void getPowerBase88E(
for(i=0; i<pHalData->NumTotalRFPath; i++)
{
/* Check HT20 to HT40 diff */
if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
{
powerlevel[i] = pPowerLevelBW20[i];
}
@ -350,24 +350,24 @@ static void getTxPowerWriteValByRegulatory88E(
case 1: /* Realtek regulatory */
/* increase power diff defined by Realtek for regulatory */
{
if(pHalData->pwrGroupCnt == 1)
if (pHalData->pwrGroupCnt == 1)
chnlGroup = 0;
/* if(pHalData->pwrGroupCnt >= pHalData->PGMaxGroup) */
/* if (pHalData->pwrGroupCnt >= pHalData->PGMaxGroup) */
{
if (Channel < 3) /* Chanel 1-2 */
chnlGroup = 0;
else if (Channel < 6) /* Channel 3-5 */
chnlGroup = 1;
else if(Channel <9) /* Channel 6-8 */
else if (Channel <9) /* Channel 6-8 */
chnlGroup = 2;
else if(Channel <12) /* Channel 9-11 */
else if (Channel <12) /* Channel 9-11 */
chnlGroup = 3;
else if(Channel <14) /* Channel 12-13 */
else if (Channel <14) /* Channel 12-13 */
chnlGroup = 4;
else if(Channel ==14) /* Channel 14 */
else if (Channel ==14) /* Channel 14 */
chnlGroup = 4;
if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
chnlGroup++;
else
chnlGroup+=6;
@ -383,7 +383,7 @@ static void getTxPowerWriteValByRegulatory88E(
case 3: /* Customer defined power diff. */
/* increase power diff defined by customer. */
chnlGroup = 0;
if(index < 2)
if (index < 2)
pwr_diff = pHalData->TxPwrLegacyHtDiff[rf][Channel-1];
else if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
pwr_diff = pHalData->TxPwrHt20Diff[rf][Channel-1];
@ -393,7 +393,7 @@ static void getTxPowerWriteValByRegulatory88E(
else
customer_pwr_limit = pHalData->PwrGroupHT20[rf][Channel-1];
if(pwr_diff >= customer_pwr_limit)
if (pwr_diff >= customer_pwr_limit)
pwr_diff = 0;
else
pwr_diff = customer_pwr_limit - pwr_diff;
@ -402,7 +402,7 @@ static void getTxPowerWriteValByRegulatory88E(
{
pwr_diff_limit[i] = (u8)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]&(0x7f<<(i*8)))>>(i*8));
if(pwr_diff_limit[i] > pwr_diff)
if (pwr_diff_limit[i] > pwr_diff)
pwr_diff_limit[i] = pwr_diff;
}
customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
@ -423,19 +423,19 @@ static void getTxPowerWriteValByRegulatory88E(
/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */
/* 92d do not need this */
if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
writeVal = 0x14141414;
else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
writeVal = 0x00000000;
/* 20100628 Joseph: High power mode for BT-Coexist mechanism. */
/* This mechanism is only applied when Driver-Highpower-Mechanism is OFF. */
if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
{
/* RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n")); */
writeVal = writeVal - 0x06060606;
}
else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
{
/* RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n")); */
writeVal = writeVal ;
@ -472,7 +472,7 @@ static void writeOFDMPowerReg88E(
}
writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) |(pwr_val[1]<<8) |pwr_val[0];
if(rf == 0)
if (rf == 0)
RegOffset = RegOffset_A[index];
else
RegOffset = RegOffset_B[index];
@ -481,19 +481,19 @@ static void writeOFDMPowerReg88E(
/* printk("Set OFDM tx pwr- 0x%x = %08x\n", RegOffset, writeVal); */
/* 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */
if(((pHalData->rf_type == RF_2T2R) &&
if (((pHalData->rf_type == RF_2T2R) &&
(RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs15_Mcs12))||
((pHalData->rf_type != RF_2T2R) &&
(RegOffset == rTxAGC_A_Mcs07_Mcs04 || RegOffset == rTxAGC_B_Mcs07_Mcs04)) )
{
writeVal = pwr_val[3];
if(RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_A_Mcs07_Mcs04)
if (RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_A_Mcs07_Mcs04)
RegOffset = 0xc90;
if(RegOffset == rTxAGC_B_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs07_Mcs04)
if (RegOffset == rTxAGC_B_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs07_Mcs04)
RegOffset = 0xc98;
for(i=0; i<3; i++)
{
if(i!=2)
if (i!=2)
writeVal = (writeVal>8)?(writeVal-8):0;
else
writeVal = (writeVal>6)?(writeVal-6):0;
@ -648,11 +648,11 @@ phy_RF6052_Config_ParaFile(
switch(eRFPath)
{
case RF_PATH_A:
if(HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(ODM_RF_RADIO_PATH_E)eRFPath, (ODM_RF_RADIO_PATH_E)eRFPath))
if (HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(ODM_RF_RADIO_PATH_E)eRFPath, (ODM_RF_RADIO_PATH_E)eRFPath))
rtStatus= _FAIL;
break;
case RF_PATH_B:
if(HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(ODM_RF_RADIO_PATH_E)eRFPath, (ODM_RF_RADIO_PATH_E)eRFPath))
if (HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(ODM_RF_RADIO_PATH_E)eRFPath, (ODM_RF_RADIO_PATH_E)eRFPath))
rtStatus= _FAIL;
break;
case RF_PATH_C:
@ -674,7 +674,7 @@ phy_RF6052_Config_ParaFile(
break;
}
if(rtStatus != _SUCCESS){
if (rtStatus != _SUCCESS){
/* RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); */
goto phy_RF6052_Config_ParaFile_Fail;
}
@ -700,7 +700,7 @@ PHY_RF6052_Config8188E(
/* Initialize general global value */
/* */
/* TODO: Extend RF_PATH_C and RF_PATH_D in the future */
if(pHalData->rf_type == RF_1T1R)
if (pHalData->rf_type == RF_1T1R)
pHalData->NumTotalRFPath = 1;
else
pHalData->NumTotalRFPath = 2;

18
hal/rtl8188e_rxdesc.c
View file

@ -44,7 +44,7 @@ static void process_rssi(struct adapter *padapter,union recv_frame *prframe)
struct signal_stat * signal_stat = &padapter->recvpriv.signal_strength_data;
if(signal_stat->update_req) {
if (signal_stat->update_req) {
signal_stat->total_num = 0;
signal_stat->total_val = 0;
signal_stat->update_req = 0;
@ -61,14 +61,14 @@ static void process_link_qual(struct adapter *padapter,union recv_frame *prframe
struct rx_pkt_attrib *pattrib;
struct signal_stat * signal_stat;
if(prframe == NULL || padapter==NULL){
if (prframe == NULL || padapter==NULL){
return;
}
pattrib = &prframe->u.hdr.attrib;
signal_stat = &padapter->recvpriv.signal_qual_data;
if(signal_stat->update_req) {
if (signal_stat->update_req) {
signal_stat->total_num = 0;
signal_stat->total_val = 0;
signal_stat->update_req = 0;
@ -130,7 +130,7 @@ void update_recvframe_attrib_88e(
/* update rx report to recv_frame attribute */
pattrib->pkt_rpt_type = (u8)((le32_to_cpu(report.rxdw3) >> 14) & 0x3);/* prxreport->rpt_sel; */
if(pattrib->pkt_rpt_type == NORMAL_RX)/* Normal rx packet */
if (pattrib->pkt_rpt_type == NORMAL_RX)/* Normal rx packet */
{
pattrib->pkt_len = (u16)(le32_to_cpu(report.rxdw0) &0x00003fff);/* u16)prxreport->pktlen; */
pattrib->drvinfo_sz = (u8)((le32_to_cpu(report.rxdw0) >> 16) & 0xf) * 8;/* u8)(prxreport->drvinfosize << 3); */
@ -156,10 +156,10 @@ void update_recvframe_attrib_88e(
pattrib->icv_err = (u8)((le32_to_cpu(report.rxdw0) >> 15) & 0x1);/* u8)prxreport->icverr; */
pattrib->shift_sz = (u8)((le32_to_cpu(report.rxdw0) >> 24) & 0x3);
} else if(pattrib->pkt_rpt_type == TX_REPORT1) {/* CCX */
} else if (pattrib->pkt_rpt_type == TX_REPORT1) {/* CCX */
pattrib->pkt_len = TX_RPT1_PKT_LEN;
pattrib->drvinfo_sz = 0;
} else if(pattrib->pkt_rpt_type == TX_REPORT2) { /* TX RPT */
} else if (pattrib->pkt_rpt_type == TX_REPORT2) { /* TX RPT */
pattrib->pkt_len =(u16)(le32_to_cpu(report.rxdw0) & 0x3FF);/* Rx length[9:0] */
pattrib->drvinfo_sz = 0;
@ -170,7 +170,7 @@ void update_recvframe_attrib_88e(
pattrib->MacIDValidEntry[1] = le32_to_cpu(report.rxdw5);
}
else if(pattrib->pkt_rpt_type == HIS_REPORT)/* USB HISR RPT */
else if (pattrib->pkt_rpt_type == HIS_REPORT)/* USB HISR RPT */
{
pattrib->pkt_len = (u16)(le32_to_cpu(report.rxdw0) &0x00003fff);/* u16)prxreport->pktlen; */
}
@ -211,8 +211,8 @@ void update_recvframe_phyinfo_88e(
pkt_info.bPacketBeacon = pkt_info.bPacketMatchBSSID && (GetFrameSubType(wlanhdr) == WIFI_BEACON);
if(pkt_info.bPacketBeacon){
if(check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == true){
if (pkt_info.bPacketBeacon){
if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == true){
sa = padapter->mlmepriv.cur_network.network.MacAddress;
}
else

12
hal/rtl8188e_sreset.c
View file

@ -32,13 +32,13 @@ void rtl8188e_sreset_xmit_status_check(struct adapter *padapter)
unsigned int diff_time;
u32 txdma_status;
if( (txdma_status=rtw_read32(padapter, REG_TXDMA_STATUS)) !=0x00){
if ( (txdma_status=rtw_read32(padapter, REG_TXDMA_STATUS)) !=0x00){
DBG_871X("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status);
rtw_hal_sreset_reset(padapter);
}
current_time = rtw_get_current_time();
if(0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) {
if (0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) {
diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_time);
@ -77,16 +77,16 @@ void rtl8188e_sreset_linked_status_check(struct adapter *padapter)
u32 rx_dma_status = 0;
u8 fw_status=0;
rx_dma_status = rtw_read32(padapter,REG_RXDMA_STATUS);
if(rx_dma_status!= 0x00){
if (rx_dma_status!= 0x00){
DBG_8192C("%s REG_RXDMA_STATUS:0x%08x\n",__FUNCTION__,rx_dma_status);
rtw_write32(padapter,REG_RXDMA_STATUS,rx_dma_status);
}
fw_status = rtw_read8(padapter,REG_FMETHR);
if(fw_status != 0x00)
if (fw_status != 0x00)
{
if(fw_status == 1)
if (fw_status == 1)
DBG_8192C("%s REG_FW_STATUS (0x%02x), Read_Efuse_Fail !! \n",__FUNCTION__,fw_status);
else if(fw_status == 2)
else if (fw_status == 2)
DBG_8192C("%s REG_FW_STATUS (0x%02x), Condition_No_Match !! \n",__FUNCTION__,fw_status);
}
if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) {

12
hal/rtl8188e_xmit.c
View file

@ -67,22 +67,22 @@ void _dbg_dump_tx_info(struct adapter *padapter,int frame_tag,struct tx_desc *pt
u8 bDumpTxDesc = false;
rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DUMP_TXPKT, &(bDumpTxPkt));
if(bDumpTxPkt ==1){/* dump txdesc for data frame */
if (bDumpTxPkt ==1){/* dump txdesc for data frame */
DBG_871X("dump tx_desc for data frame\n");
if((frame_tag&0x0f) == DATA_FRAMETAG){
if ((frame_tag&0x0f) == DATA_FRAMETAG){
bDumpTxDesc = true;
}
}
else if(bDumpTxPkt ==2){/* dump txdesc for mgnt frame */
else if (bDumpTxPkt ==2){/* dump txdesc for mgnt frame */
DBG_871X("dump tx_desc for mgnt frame\n");
if((frame_tag&0x0f) == MGNT_FRAMETAG){
if ((frame_tag&0x0f) == MGNT_FRAMETAG){
bDumpTxDesc = true;
}
}
else if(bDumpTxPkt ==3){/* dump early info */
else if (bDumpTxPkt ==3){/* dump early info */
}
if(bDumpTxDesc){
if (bDumpTxDesc){
DBG_8192C("=====================================\n");
DBG_8192C("txdw0(0x%08x)\n",ptxdesc->txdw0);
DBG_8192C("txdw1(0x%08x)\n",ptxdesc->txdw1);

6
hal/rtl8188eu_led.c
View file

@ -52,7 +52,7 @@ SwLedOn(
u8 LedCfg;
/* HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); */
if( (padapter->bSurpriseRemoved == true) || ( padapter->bDriverStopped == true))
if ( (padapter->bSurpriseRemoved == true) || ( padapter->bDriverStopped == true))
{
return;
}
@ -89,7 +89,7 @@ SwLedOff(
u8 LedCfg;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
if((padapter->bSurpriseRemoved == true) || ( padapter->bDriverStopped == true))
if ((padapter->bSurpriseRemoved == true) || ( padapter->bDriverStopped == true))
{
goto exit;
}
@ -100,7 +100,7 @@ SwLedOff(
switch(pLed->LedPin)
{
case LED_PIN_LED0:
if(pHalData->bLedOpenDrain == true) /* Open-drain arrangement for controlling the LED) */
if (pHalData->bLedOpenDrain == true) /* Open-drain arrangement for controlling the LED) */
{
LedCfg &= 0x90; /* Set to software control. */
rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3));

18
hal/rtl8188eu_recv.c
View file

@ -44,7 +44,7 @@ void rtl8188eu_init_recvbuf(struct adapter *padapter, struct recv_buf *precvbuf)
precvbuf->ref_cnt = 0;
if(precvbuf->pbuf)
if (precvbuf->pbuf)
{
precvbuf->pdata = precvbuf->phead = precvbuf->ptail = precvbuf->pbuf;
precvbuf->pend = precvbuf->pdata + MAX_RECVBUF_SZ;
@ -64,13 +64,13 @@ int rtl8188eu_init_recv_priv(struct adapter *padapter)
#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
precvpriv->int_in_urb = usb_alloc_urb(0, GFP_KERNEL);
if(precvpriv->int_in_urb == NULL){
if (precvpriv->int_in_urb == NULL){
res= _FAIL;
DBG_8192C("alloc_urb for interrupt in endpoint fail !!!!\n");
goto exit;
}
precvpriv->int_in_buf = rtw_zmalloc(INTERRUPT_MSG_FORMAT_LEN);
if(precvpriv->int_in_buf == NULL){
if (precvpriv->int_in_buf == NULL){
res= _FAIL;
DBG_8192C("alloc_mem for interrupt in endpoint fail !!!!\n");
goto exit;
@ -81,7 +81,7 @@ int rtl8188eu_init_recv_priv(struct adapter *padapter)
_rtw_init_queue(&precvpriv->free_recv_buf_queue);
precvpriv->pallocated_recv_buf = rtw_zmalloc(NR_RECVBUFF *sizeof(struct recv_buf) + 4);
if(precvpriv->pallocated_recv_buf==NULL){
if (precvpriv->pallocated_recv_buf==NULL){
res= _FAIL;
RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("alloc recv_buf fail!\n"));
goto exit;
@ -100,7 +100,7 @@ int rtl8188eu_init_recv_priv(struct adapter *padapter)
precvbuf->alloc_sz = MAX_RECVBUF_SZ;
res = rtw_os_recvbuf_resource_alloc(padapter, precvbuf);
if(res==_FAIL)
if (res==_FAIL)
break;
precvbuf->ref_cnt = 0;
@ -130,7 +130,7 @@ int rtl8188eu_init_recv_priv(struct adapter *padapter)
{
pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
if(pskb)
if (pskb)
{
pskb->dev = padapter->pnetdev;
@ -164,14 +164,14 @@ void rtl8188eu_free_recv_priv (struct adapter *padapter)
precvbuf++;
}
if(precvpriv->pallocated_recv_buf)
if (precvpriv->pallocated_recv_buf)
rtw_mfree(precvpriv->pallocated_recv_buf, NR_RECVBUFF *sizeof(struct recv_buf) + 4);
#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
if(precvpriv->int_in_urb)
if (precvpriv->int_in_urb)
usb_free_urb(precvpriv->int_in_urb);
if(precvpriv->int_in_buf)
if (precvpriv->int_in_buf)
rtw_mfree(precvpriv->int_in_buf, INTERRUPT_MSG_FORMAT_LEN);
#endif/* CONFIG_USB_INTERRUPT_IN_PIPE */

60
hal/rtl8188eu_xmit.c
View file

@ -163,19 +163,19 @@ static void fill_txdesc_vcs(struct pkt_attrib *pattrib, __le32 *pdw)
break;
}
if(pattrib->vcs_mode) {
if (pattrib->vcs_mode) {
*pdw |= cpu_to_le32(HW_RTS_EN);
/* Set RTS BW */
if(pattrib->ht_en)
if (pattrib->ht_en)
{
*pdw |= (pattrib->bwmode&HT_CHANNEL_WIDTH_40)? cpu_to_le32(BIT(27)):0;
if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
*pdw |= cpu_to_le32((0x01<<28)&0x30000000);
else if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
*pdw |= cpu_to_le32((0x02<<28)&0x30000000);
else if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)
else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)
*pdw |= 0;
else
*pdw |= cpu_to_le32((0x03<<28)&0x30000000);
@ -187,15 +187,15 @@ static void fill_txdesc_phy(struct pkt_attrib *pattrib, __le32 *pdw)
{
/* DBG_8192C("bwmode=%d, ch_off=%d\n", pattrib->bwmode, pattrib->ch_offset); */
if(pattrib->ht_en)
if (pattrib->ht_en)
{
*pdw |= (pattrib->bwmode&HT_CHANNEL_WIDTH_40)? cpu_to_le32(BIT(25)):0;
if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
*pdw |= cpu_to_le32((0x01<<DATA_SC_SHT)&0x003f0000);
else if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
*pdw |= cpu_to_le32((0x02<<DATA_SC_SHT)&0x003f0000);
else if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)
else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)
*pdw |= 0;
else
*pdw |= cpu_to_le32((0x03<<DATA_SC_SHT)&0x003f0000);
@ -221,7 +221,7 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bag
#endif /* CONFIG_P2P */
if (padapter->registrypriv.mp_mode == 0) {
if((!bagg_pkt) &&(urb_zero_packet_chk(padapter, sz)==0)) {
if ((!bagg_pkt) &&(urb_zero_packet_chk(padapter, sz)==0)) {
ptxdesc = (struct tx_desc *)(pmem+PACKET_OFFSET_SZ);
pull = 1;
}
@ -240,8 +240,8 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bag
if (bmcst) ptxdesc->txdw0 |= cpu_to_le32(BMC);
if (padapter->registrypriv.mp_mode == 0) {
if(!bagg_pkt) {
if((pull) && (pxmitframe->pkt_offset>0))
if (!bagg_pkt) {
if ((pull) && (pxmitframe->pkt_offset>0))
pxmitframe->pkt_offset = pxmitframe->pkt_offset -1;
}
}
@ -252,7 +252,7 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bag
/* driver uses rate */
ptxdesc->txdw4 |= cpu_to_le32(USERATE);/* rate control always by driver */
if((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG)
if ((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG)
{
/* DBG_8192C("pxmitframe->frame_tag == DATA_FRAMETAG\n"); */
@ -267,7 +267,7 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bag
fill_txdesc_sectype(pattrib, ptxdesc);
if(pattrib->ampdu_en==true){
if (pattrib->ampdu_en==true){
ptxdesc->txdw2 |= cpu_to_le32(AGG_EN);/* AGG EN */
ptxdesc->txdw6 = cpu_to_le32(0x6666f800);
} else{
@ -305,14 +305,14 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bag
ptxdesc->txdw5 |= cpu_to_le32(0x0001ff00);/* DATA/RTS Rate FB LMT */
#if (RATE_ADAPTIVE_SUPPORT == 1)
if(pattrib->ht_en){
if( ODM_RA_GetShortGI_8188E(&pHalData->odmpriv,pattrib->mac_id))
if (pattrib->ht_en){
if ( ODM_RA_GetShortGI_8188E(&pHalData->odmpriv,pattrib->mac_id))
ptxdesc->txdw5 |= cpu_to_le32(SGI);/* SGI */
}
data_rate =ODM_RA_GetDecisionRate_8188E(&pHalData->odmpriv,pattrib->mac_id);
/* for debug */
if(padapter->fix_rate!= 0xFF){
if (padapter->fix_rate!= 0xFF){
data_rate = padapter->fix_rate;
ptxdesc->txdw4 |= cpu_to_le32(DISDATAFB);
@ -326,11 +326,11 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bag
#endif /* POWER_TRAINING_ACTIVE==1) */
#else/* if (RATE_ADAPTIVE_SUPPORT == 1) */
if(pattrib->ht_en)
if (pattrib->ht_en)
ptxdesc->txdw5 |= cpu_to_le32(SGI);/* SGI */
data_rate = 0x13; /* default rate: MCS7 */
if(padapter->fix_rate!= 0xFF){/* rate control by iwpriv */
if (padapter->fix_rate!= 0xFF){/* rate control by iwpriv */
data_rate = padapter->fix_rate;
ptxdesc->txdw4 | cpu_to_le32(DISDATAFB);
}
@ -352,7 +352,7 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bag
ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
}
} else if((pxmitframe->frame_tag&0x0f)== MGNT_FRAMETAG) {
} else if ((pxmitframe->frame_tag&0x0f)== MGNT_FRAMETAG) {
/* offset 4 */
ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id&0x3f);
@ -378,13 +378,13 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bag
/* offset 20 */
ptxdesc->txdw5 |= cpu_to_le32(RTY_LMT_EN);/* retry limit enable */
if(pattrib->retry_ctrl == true)
if (pattrib->retry_ctrl == true)
ptxdesc->txdw5 |= cpu_to_le32(0x00180000);/* retry limit = 6 */
else
ptxdesc->txdw5 |= cpu_to_le32(0x00300000);/* retry limit = 12 */
#ifdef CONFIG_INTEL_PROXIM
if((padapter->proximity.proxim_on==true)&&(pattrib->intel_proxim==true)){
if ((padapter->proximity.proxim_on==true)&&(pattrib->intel_proxim==true)){
DBG_871X("\n %s pattrib->rate=%d\n",__FUNCTION__,pattrib->rate);
ptxdesc->txdw5 |= cpu_to_le32( pattrib->rate);
}
@ -394,7 +394,7 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bag
ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
}
}
else if((pxmitframe->frame_tag&0x0f) == TXAGG_FRAMETAG)
else if ((pxmitframe->frame_tag&0x0f) == TXAGG_FRAMETAG)
{
DBG_8192C("pxmitframe->frame_tag == TXAGG_FRAMETAG\n");
}
@ -424,7 +424,7 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bag
/* (2) Enable HW SEQ control for beacon packet, because we use Hw beacon. */
/* (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets. */
/* 2010.06.23. Added by tynli. */
if(!pattrib->qos_en)
if (!pattrib->qos_en)
{
ptxdesc->txdw3 |= cpu_to_le32(EN_HWSEQ); /* Hw set sequence number */
ptxdesc->txdw4 |= cpu_to_le32(HW_SSN); /* Hw set sequence number */
@ -478,7 +478,7 @@ static s32 rtw_dump_xframe(struct adapter *padapter, struct xmit_frame *pxmitfra
pull = update_txdesc(pxmitframe, mem_addr, sz, false);
if(pull)
if (pull)
{
mem_addr += PACKET_OFFSET_SZ; /* pull txdesc head */
@ -525,7 +525,7 @@ static u32 xmitframe_need_length(struct xmit_frame *pxmitframe)
pattrib->pktlen +
((pattrib->bswenc) ? pattrib->icv_len : 0);
if(pattrib->encrypt ==_TKIP_)
if (pattrib->encrypt ==_TKIP_)
len += 8;
return len;
@ -643,13 +643,13 @@ s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxm
/* dequeue same priority packet from station tx queue */
/* psta = pfirstframe->attrib.psta; */
psta = rtw_get_stainfo(&padapter->stapriv, pfirstframe->attrib.ra);
if(pfirstframe->attrib.psta != psta){
if (pfirstframe->attrib.psta != psta){
DBG_871X("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pfirstframe->attrib.psta, psta);
}
if (psta == NULL) {
DBG_8192C("rtw_xmit_classifier: psta == NULL\n");
}
if(!(psta->state &_FW_LINKED)){
if (!(psta->state &_FW_LINKED)){
DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state);
}
@ -956,7 +956,7 @@ s32 rtl8188eu_hostap_mgnt_xmit_entry(struct adapter *padapter, _pkt *pkt)
pxmit_skb = rtw_skb_alloc(len + TXDESC_SIZE);
if(!pxmit_skb)
if (!pxmit_skb)
goto _exit;
pxmitbuf = pxmit_skb->data;
@ -975,7 +975,7 @@ s32 rtl8188eu_hostap_mgnt_xmit_entry(struct adapter *padapter, _pkt *pkt)
ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<<OFFSET_SHT)&0x00ff0000);/* default = 32 bytes for TX Desc */
ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
if(bmcst)
if (bmcst)
{
ptxdesc->txdw0 |= cpu_to_le32(BIT(24));
}

216
hal/usb_halinit.c
View file

@ -83,14 +83,14 @@ static bool HalUsbSetQueuePipeMapping8188EUsb(
_ConfigNormalChipOutEP_8188E(pAdapter, NumOutPipe);
/* Normal chip with one IN and one OUT doesn't have interrupt IN EP. */
if(1 == pHalData->OutEpNumber){
if(1 != NumInPipe){
if (1 == pHalData->OutEpNumber){
if (1 != NumInPipe){
return result;
}
}
/* All config other than above support one Bulk IN and one Interrupt IN. */
/* if(2 != NumInPipe){ */
/* if (2 != NumInPipe){ */
/* return result; */
/* */
@ -137,10 +137,10 @@ static u32 InitPowerOn_rtl8188eu(struct adapter *padapter)
/* HW Power on sequence */
rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
if(bMacPwrCtrlOn == true)
if (bMacPwrCtrlOn == true)
return _SUCCESS;
if(!HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_PWR_ON_FLOW))
if (!HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_PWR_ON_FLOW))
{
DBG_871X(KERN_ERR "%s: run power on flow fail\n", __func__);
return _FAIL;
@ -193,7 +193,7 @@ static void _InitPABias(struct adapter *padapter)
/* RT_TRACE(COMP_INIT, DBG_LOUD, ("_InitPABias 0x1FA 0x%x\n",pa_setting)); */
if(!(pa_setting & BIT0))
if (!(pa_setting & BIT0))
{
PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
@ -202,7 +202,7 @@ static void _InitPABias(struct adapter *padapter)
/* RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path A\n")); */
}
if(!(pa_setting & BIT1) && is92C)
if (!(pa_setting & BIT1) && is92C)
{
PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
@ -211,7 +211,7 @@ static void _InitPABias(struct adapter *padapter)
/* RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path B\n")); */
}
if(!(pa_setting & BIT4))
if (!(pa_setting & BIT4))
{
pa_setting = rtw_read8(padapter, 0x16);
pa_setting &= 0x0F;
@ -226,13 +226,13 @@ static void _InitBTCoexist(struct adapter *padapter)
struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist);
u8 u1Tmp;
if(pbtpriv->BT_Coexist && pbtpriv->BT_CoexistType == BT_CSR_BC4)
if (pbtpriv->BT_Coexist && pbtpriv->BT_CoexistType == BT_CSR_BC4)
{
/* if MP_DRIVER != 1 */
if (padapter->registrypriv.mp_mode == 0)
{
if(pbtpriv->BT_Ant_isolation)
if (pbtpriv->BT_Ant_isolation)
{
rtw_write8( padapter,REG_GPIO_MUXCFG, 0xa0);
DBG_8192C("BT write 0x%x = 0x%x\n", REG_GPIO_MUXCFG, 0xa0);
@ -329,7 +329,7 @@ _InitInterrupt(
usb_opt = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
if(!adapter_to_dvobj(Adapter)->ishighspeed
if (!adapter_to_dvobj(Adapter)->ishighspeed
#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
|| pHalData->RtIntInPipe == 0x05
#endif
@ -357,7 +357,7 @@ _InitQueueReservedPage(
u8 value8;
bool bWiFiConfig = pregistrypriv->wifi_spec;
if((bWiFiConfig)|| (pregistrypriv->qos_opt_enable))
if ((bWiFiConfig)|| (pregistrypriv->qos_opt_enable))
{
if (pHalData->OutEpQueueSel & TX_SELE_HQ)
{
@ -509,7 +509,7 @@ _InitNormalChipTwoOutEpPriority(
break;
}
if(!pregistrypriv->wifi_spec ){
if (!pregistrypriv->wifi_spec ){
beQ = valueLow;
bkQ = valueLow;
viQ = valueHi;
@ -538,7 +538,7 @@ _InitNormalChipThreeOutEpPriority(
struct registry_priv *pregistrypriv = &Adapter->registrypriv;
u16 beQ,bkQ,viQ,voQ,mgtQ,hiQ;
if(!pregistrypriv->wifi_spec ){/* typical setting */
if (!pregistrypriv->wifi_spec ){/* typical setting */
beQ = QUEUE_LOW;
bkQ = QUEUE_LOW;
viQ = QUEUE_NORMAL;
@ -803,10 +803,10 @@ usb_AggSettingTxUpdate(
/* PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); */
u32 value32;
if(Adapter->registrypriv.wifi_spec)
if (Adapter->registrypriv.wifi_spec)
pHalData->UsbTxAggMode = false;
if(pHalData->UsbTxAggMode){
if (pHalData->UsbTxAggMode){
value32 = rtw_read32(Adapter, REG_TDECTRL);
value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
value32 |= ((pHalData->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
@ -1012,7 +1012,7 @@ _InitRFType(
pHalData->rf_chip = RF_6052;
if(false == is92CU){
if (false == is92CU){
pHalData->rf_type = RF_1T1R;
DBG_8192C("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n");
return;
@ -1071,14 +1071,14 @@ _InitAntenna_Selection(struct adapter *Adapter)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
if(pHalData->AntDivCfg==0)
if (pHalData->AntDivCfg==0)
return;
DBG_8192C("==> %s ....\n",__FUNCTION__);
rtw_write32(Adapter, REG_LEDCFG0, rtw_read32(Adapter, REG_LEDCFG0)|BIT23);
PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
if(PHY_QueryBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A)
if (PHY_QueryBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A)
pHalData->CurAntenna = Antenna_A;
else
pHalData->CurAntenna = Antenna_B;
@ -1128,7 +1128,7 @@ rt_rf_power_state RfOnOffDetect(struct adapter *pAdapter )
u8 val8;
rt_rf_power_state rfpowerstate = rf_off;
if(adapter_to_pwrctl(pAdapter)->bHWPowerdown)
if (adapter_to_pwrctl(pAdapter)->bHWPowerdown)
{
val8 = rtw_read8(pAdapter, REG_HSISR);
DBG_8192C("pwrdown, 0x5c(BIT7)=%02x\n", val8);
@ -1238,11 +1238,11 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter)
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
if(pwrctrlpriv->bkeepfwalive)
if (pwrctrlpriv->bkeepfwalive)
{
_ps_open_RF(Adapter);
if(pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized){
if (pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized){
PHY_IQCalibrate_8188E(Adapter,true);
}
else
@ -1260,7 +1260,7 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter)
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
status = InitPowerOn_rtl8188eu(Adapter);
if(status == _FAIL){
if (status == _FAIL){
RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n"));
goto exit;
}
@ -1269,7 +1269,7 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter)
pHalData->CurrentChannel = 6;/* default set to 6 */
if(pwrctrlpriv->reg_rfoff == true){
if (pwrctrlpriv->reg_rfoff == true){
pwrctrlpriv->rf_pwrstate = rf_off;
}
@ -1315,7 +1315,7 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter)
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
#if (HAL_MAC_ENABLE == 1)
status = PHY_MACConfig8188E(Adapter);
if(status == _FAIL)
if (status == _FAIL)
{
DBG_871X(" ### Failed to init MAC ......\n ");
goto exit;
@ -1328,7 +1328,7 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter)
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
#if (HAL_BB_ENABLE == 1)
status = PHY_BBConfig8188E(Adapter);
if(status == _FAIL)
if (status == _FAIL)
{
DBG_871X(" ### Failed to init BB ......\n ");
goto exit;
@ -1339,7 +1339,7 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter)
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
#if (HAL_RF_ENABLE == 1)
status = PHY_RFConfig8188E(Adapter);
if(status == _FAIL)
if (status == _FAIL)
{
DBG_871X(" ### Failed to init RF ......\n ");
goto exit;
@ -1348,7 +1348,7 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter)
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_EFUSE_PATCH);
status = rtl8188e_iol_efuse_patch(Adapter);
if(status == _FAIL){
if (status == _FAIL){
DBG_871X("%s rtl8188e_iol_efuse_patch failed\n",__FUNCTION__);
goto exit;
}
@ -1357,7 +1357,7 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter)
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
status = InitLLTTable(Adapter, txpktbuf_bndy);
if(status == _FAIL){
if (status == _FAIL){
RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n"));
goto exit;
}
@ -1391,7 +1391,7 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter)
_InitHardwareDropIncorrectBulkOut(Adapter);
if(pHalData->bRDGEnable){
if (pHalData->bRDGEnable){
_InitRDGSetting(Adapter);
}
@ -1449,7 +1449,7 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter)
/* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
rtw_write8(Adapter,REG_HWSEQ_CTRL, 0xFF);
if(pregistrypriv->wifi_spec)
if (pregistrypriv->wifi_spec)
rtw_write16(Adapter,REG_FAST_EDCA_CTRL ,0);
/* Nav limit , suggest by scott */
@ -1493,9 +1493,9 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter)
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
/* 2010/08/26 MH Merge from 8192CE. */
if(pwrctrlpriv->rf_pwrstate == rf_on)
if (pwrctrlpriv->rf_pwrstate == rf_on)
{
if(pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized){
if (pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized){
PHY_IQCalibrate_8188E(Adapter,true);
} else {
PHY_IQCalibrate_8188E(Adapter,false);
@ -1554,7 +1554,7 @@ static void hal_poweroff_rtl8188eu(
u8 bMacPwrCtrlOn=false;
rtw_hal_get_hwreg(Adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
if(bMacPwrCtrlOn == false)
if (bMacPwrCtrlOn == false)
return ;
RT_TRACE(COMP_INIT, DBG_LOUD, ("%s\n",__FUNCTION__));
@ -1636,14 +1636,14 @@ static u32 rtl8188eu_hal_deinit(struct adapter *Adapter)
rtw_write32(Adapter, REG_HIMRE_88E, IMR_DISABLED_88E);
DBG_8192C("bkeepfwalive(%x)\n", pwrctl->bkeepfwalive);
if(pwrctl->bkeepfwalive) {
if((pwrctl->bHWPwrPindetect) && (pwrctl->bHWPowerdown))
if (pwrctl->bkeepfwalive) {
if ((pwrctl->bHWPwrPindetect) && (pwrctl->bHWPowerdown))
rtl8188eu_hw_power_down(Adapter);
} else {
if(Adapter->hw_init_completed == true){
if (Adapter->hw_init_completed == true){
hal_poweroff_rtl8188eu(Adapter);
if((pwrctl->bHWPwrPindetect ) && (pwrctl->bHWPowerdown))
if ((pwrctl->bHWPwrPindetect ) && (pwrctl->bHWPowerdown))
rtl8188eu_hw_power_down(Adapter);
}
@ -1680,7 +1680,7 @@ static unsigned int rtl8188eu_inirp_init(struct adapter *Adapter)
precvbuf = (struct recv_buf *)precvpriv->precv_buf;
for(i=0; i<NR_RECVBUFF; i++)
{
if(_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == false )
if (_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == false )
{
RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_port error\n"));
status = _FAIL;
@ -1692,14 +1692,14 @@ static unsigned int rtl8188eu_inirp_init(struct adapter *Adapter)
}
#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
if(pHalData->RtIntInPipe != 0x05)
if (pHalData->RtIntInPipe != 0x05)
{
status = _FAIL;
DBG_871X("%s =>Warning !! Have not USB Int-IN pipe, pHalData->RtIntInPipe(%d)!!!\n",__FUNCTION__,pHalData->RtIntInPipe);
goto exit;
}
_read_interrupt = pintfhdl->io_ops._read_interrupt;
if(_read_interrupt(pintfhdl, RECV_INT_IN_ADDR) == false )
if (_read_interrupt(pintfhdl, RECV_INT_IN_ADDR) == false )
{
RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_interrupt error\n"));
status = _FAIL;
@ -1839,7 +1839,7 @@ Hal_EfuseParsePIDVID_8188EU(
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
if( !AutoLoadFail )
if ( !AutoLoadFail )
{
/* VID, PID */
pHalData->EEPROMVID = EF2BYTE(*(__le16 *)&hwinfo[EEPROM_VID_88EU]);
@ -1981,7 +1981,7 @@ static int _ReadAdapterInfo8188EU(struct adapter *Adapter)
/* Efuse_InitSomeVar(Adapter); */
/* if(IS_HARDWARE_TYPE_8723A(Adapter)) */
/* if (IS_HARDWARE_TYPE_8723A(Adapter)) */
/* _EfuseCellSel(Adapter); */
_ReadRFType(Adapter);/* rf_chip -> _InitRFType() */
@ -2041,7 +2041,7 @@ static void UpdateInterruptMask8188EU(struct adapter *padapter,u8 bHIMR0 ,u32 Ad
u32 *himr;
pHalData = GET_HAL_DATA(padapter);
if(bHIMR0)
if (bHIMR0)
himr = &(pHalData->IntrMask[0]);
else
himr = &(pHalData->IntrMask[1]);
@ -2052,7 +2052,7 @@ static void UpdateInterruptMask8188EU(struct adapter *padapter,u8 bHIMR0 ,u32 Ad
if (RemoveMSR)
*himr &= (~RemoveMSR);
if(bHIMR0)
if (bHIMR0)
rtw_write32(padapter, REG_HIMR_88E, *himr);
else
rtw_write32(padapter, REG_HIMRE_88E, *himr);
@ -2090,20 +2090,20 @@ static void hw_var_set_opmode(struct adapter *Adapter, u8 variable, u8* val)
DBG_871X("%s()-%d mode = %d\n", __FUNCTION__, __LINE__, mode);
if((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_))
if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_))
{
StopTxBeacon(Adapter);
rtw_write8(Adapter,REG_BCN_CTRL, 0x19);/* disable atim wnd */
}
else if((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/)
else if ((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/)
{
ResumeTxBeacon(Adapter);
rtw_write8(Adapter,REG_BCN_CTRL, 0x1a);
/* BIT3 - If set 0, hw will clr bcnq when tx becon ok/fail or port 0 */
rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4));
}
else if(mode == _HW_STATE_AP_)
else if (mode == _HW_STATE_AP_)
{
ResumeTxBeacon(Adapter);
@ -2178,7 +2178,7 @@ static void hw_var_set_bcn_func(struct adapter *Adapter, u8 variable, u8* val)
bcn_ctrl_reg = REG_BCN_CTRL;
if(*((u8 *)val))
if (*((u8 *)val))
rtw_write8(Adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
else
rtw_write8(Adapter, bcn_ctrl_reg, rtw_read8(Adapter, bcn_ctrl_reg)&(~(EN_BCN_FUNCTION | EN_TXBCN_RPT)));
@ -2285,7 +2285,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) -1024; /* us */
if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
{
/* pHalData->RegTxPause |= STOP_BCNQ;BIT(6) */
/* rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)|BIT(6))); */
@ -2302,7 +2302,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3));
if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
{
/* pHalData->RegTxPause &= (~STOP_BCNQ); */
/* rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)&(~BIT(6)))); */
@ -2311,7 +2311,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
}
break;
case HW_VAR_CHECK_BSSID:
if(*((u8 *)val))
if (*((u8 *)val))
{
rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
}
@ -2341,7 +2341,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
}
break;
case HW_VAR_MLME_SITESURVEY:
if(*((u8 *)val))/* under sitesurvey */
if (*((u8 *)val))/* under sitesurvey */
{
/* config RCR to receive different BSSID & not to receive data frame */
u32 v = rtw_read32(Adapter, REG_RCR);
@ -2368,7 +2368,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
/* enable update TSF */
rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
}
else if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
else if ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
{
/* rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_ADF); */
rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF);
@ -2377,11 +2377,11 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
}
if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
if ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
else
{
if(Adapter->in_cta_test)
if (Adapter->in_cta_test)
{
u32 v = rtw_read32(Adapter, REG_RCR);
v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN );/* RCR_ADF */
@ -2400,13 +2400,13 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
u8 type = *((u8 *)val);
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
if(type == 0) /* prepare to join */
if (type == 0) /* prepare to join */
{
/* enable to rx data frame.Accept all data frame */
/* rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF); */
rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF);
if(Adapter->in_cta_test)
if (Adapter->in_cta_test)
{
u32 v = rtw_read32(Adapter, REG_RCR);
v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN );/* RCR_ADF */
@ -2417,7 +2417,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
}
if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == true)
if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == true)
{
RetryLimit = (pHalData->CustomerID == RT_CID_CCX) ? 7 : 48;
}
@ -2426,16 +2426,16 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
RetryLimit = 0x7;
}
}
else if(type == 1) /* joinbss_event call back when join res < 0 */
else if (type == 1) /* joinbss_event call back when join res < 0 */
{
rtw_write16(Adapter, REG_RXFLTMAP2,0x00);
}
else if(type == 2) /* sta add event call back */
else if (type == 2) /* sta add event call back */
{
/* enable update TSF */
rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
{
RetryLimit = 0x7;
}
@ -2463,9 +2463,9 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
rtw_write8(Adapter, REG_SLOT, val[0]);
if(pmlmeinfo->WMM_enable == 0)
if (pmlmeinfo->WMM_enable == 0)
{
if( pmlmeext->cur_wireless_mode == WIRELESS_11B)
if ( pmlmeext->cur_wireless_mode == WIRELESS_11B)
aSifsTime = 10;
else
aSifsTime = 16;
@ -2496,7 +2496,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
/* Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) */
regTmp = (pHalData->nCur40MhzPrimeSC)<<5;
/* regTmp = 0; */
if(bShortPreamble)
if (bShortPreamble)
regTmp |= 0x80;
rtw_write8(Adapter, REG_RRSR+2, regTmp);
@ -2510,7 +2510,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
/* DBG_871X("HW_VAR_DM_FLAG ==> SupportAbility:0x%08x\n",podmpriv->SupportAbility ); */
break;
case HW_VAR_DM_FUNC_OP:
if(val[0])
if (val[0])
{/* save dm flag */
podmpriv->BK_SupportAbility = podmpriv->SupportAbility;
}
@ -2524,7 +2524,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
/* ); */
break;
case HW_VAR_DM_FUNC_SET:
if(*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE){
if (*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE){
pdmpriv->DMFlag = pdmpriv->InitDMFlag;
podmpriv->SupportAbility = pdmpriv->InitODMFlag;
}
@ -2548,7 +2548,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
for(i=0;i<CAM_CONTENT_COUNT;i++)
{
/* filled id in CAM config 2 byte */
if( i == 0)
if ( i == 0)
{
ulContent |=(ucIndex & 0x03) | ((u16)(ulEncAlgo)<<2);
/* ulContent |= CAM_VALID; */
@ -2599,20 +2599,20 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
u8 acm_ctrl = *((u8 *)val);
u8 AcmCtrl = rtw_read8( Adapter, REG_ACMHWCTRL);
if(acm_ctrl > 1)
if (acm_ctrl > 1)
AcmCtrl = AcmCtrl | 0x1;
if(acm_ctrl & BIT(3))
if (acm_ctrl & BIT(3))
AcmCtrl |= AcmHw_VoqEn;
else
AcmCtrl &= (~AcmHw_VoqEn);
if(acm_ctrl & BIT(2))
if (acm_ctrl & BIT(2))
AcmCtrl |= AcmHw_ViqEn;
else
AcmCtrl &= (~AcmHw_ViqEn);
if(acm_ctrl & BIT(1))
if (acm_ctrl & BIT(1))
AcmCtrl |= AcmHw_BeqEn;
else
AcmCtrl &= (~AcmHw_BeqEn);
@ -2627,7 +2627,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
u8 SecMinSpace;
MinSpacingToSet = *((u8 *)val);
if(MinSpacingToSet <= 7)
if (MinSpacingToSet <= 7)
{
switch(Adapter->securitypriv.dot11PrivacyAlgrthm)
{
@ -2647,7 +2647,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
break;
}
if(MinSpacingToSet < SecMinSpace){
if (MinSpacingToSet < SecMinSpace){
MinSpacingToSet = SecMinSpace;
}
@ -2665,7 +2665,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
u8 index = 0;
#ifdef CONFIG_BT_COEXIST
if( (pHalData->bt_coexist.BT_Coexist) &&
if ( (pHalData->bt_coexist.BT_Coexist) &&
(pHalData->bt_coexist.BT_CoexistType == BT_CSR_BC4) )
pRegToSet = RegToSet_BT; /* 0x97427431; */
else
@ -2673,18 +2673,18 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
pRegToSet = RegToSet_Normal; /* 0xb972a841; */
FactorToSet = *((u8 *)val);
if(FactorToSet <= 3)
if (FactorToSet <= 3)
{
FactorToSet = (1<<(FactorToSet + 2));
if(FactorToSet>0xf)
if (FactorToSet>0xf)
FactorToSet = 0xf;
for(index=0; index<4; index++)
{
if((pRegToSet[index] & 0xf0) > (FactorToSet<<4))
if ((pRegToSet[index] & 0xf0) > (FactorToSet<<4))
pRegToSet[index] = (pRegToSet[index] & 0x0f) | (FactorToSet<<4);
if((pRegToSet[index] & 0x0f) > FactorToSet)
if ((pRegToSet[index] & 0x0f) > FactorToSet)
pRegToSet[index] = (pRegToSet[index] & 0xf0) | (FactorToSet);
rtw_write8(Adapter, (REG_AGGLEN_LMT+index), pRegToSet[index]);
@ -2697,7 +2697,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
case HW_VAR_RXDMA_AGG_PG_TH:
{
u8 threshold = *((u8 *)val);
if( threshold == 0)
if ( threshold == 0)
{
threshold = pHalData->UsbRxAggPageCount;
}
@ -2712,7 +2712,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
/* Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power */
/* saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang. */
if( (psmode != PS_MODE_ACTIVE) && (!IS_92C_SERIAL(pHalData->VersionID)))
if ( (psmode != PS_MODE_ACTIVE) && (!IS_92C_SERIAL(pHalData->VersionID)))
{
ODM_RF_Saving(podmpriv, true);
}
@ -2738,7 +2738,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
DIG_T *pDigTable = &podmpriv->DM_DigTable;
u32 rx_gain = ((u32 *)(val))[0];
if(rx_gain == 0xff){/* restore rx gain */
if (rx_gain == 0xff){/* restore rx gain */
ODM_Write_DIG(podmpriv,pDigTable->BackupIGValue);
}
else{
@ -2778,7 +2778,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
u8 Ant ;
/* switch antenna to Optimum_antenna */
/* DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B"); */
if(pHalData->CurAntenna != Optimum_antenna)
if (pHalData->CurAntenna != Optimum_antenna)
{
Ant = (Optimum_antenna==2)?MAIN_ANT:AUX_ANT;
ODM_UpdateRxIdleAnt_88E(&pHalData->odmpriv, Ant);
@ -2802,15 +2802,15 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
/* keep sn */
Adapter->xmitpriv.nqos_ssn = rtw_read16(Adapter,REG_NQOS_SEQ);
if(pwrpriv->bkeepfwalive != true)
if (pwrpriv->bkeepfwalive != true)
{
/* RX DMA stop */
rtw_write32(Adapter,REG_RXPKT_NUM,(rtw_read32(Adapter,REG_RXPKT_NUM)|RW_RELEASE_EN));
do{
if(!(rtw_read32(Adapter,REG_RXPKT_NUM)&RXDMA_IDLE))
if (!(rtw_read32(Adapter,REG_RXPKT_NUM)&RXDMA_IDLE))
break;
}while(trycnt--);
if(trycnt ==0)
if (trycnt ==0)
DBG_8192C("Stop RX DMA failed......\n");
/* RQPN Load 0 */
@ -2879,7 +2879,7 @@ static void GetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
case HW_VAR_FWLPS_RF_ON:
{
/* When we halt NIC, we should check if FW LPS is leave. */
if(adapter_to_pwrctl(Adapter)->rf_pwrstate == rf_off)
if (adapter_to_pwrctl(Adapter)->rf_pwrstate == rf_off)
{
/* If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave, */
/* because Fw is unload. */
@ -2890,7 +2890,7 @@ static void GetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
u32 valRCR;
valRCR = rtw_read32(Adapter, REG_RCR);
valRCR &= 0x00070000;
if(valRCR)
if (valRCR)
val[0] = false;
else
val[0] = true;
@ -2951,7 +2951,7 @@ static u8 GetHalDefVar8188EUsb(
struct sta_priv * pstapriv = &Adapter->stapriv;
struct sta_info * psta;
psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
if(psta)
if (psta)
{
*((int *)pValue) = psta->rssi_stat.UndecoratedSmoothedPWDB;
}
@ -2990,7 +2990,7 @@ static u8 GetHalDefVar8188EUsb(
case HAL_DEF_PT_PWR_STATUS:
#if(POWER_TRAINING_ACTIVE==1)
#if (POWER_TRAINING_ACTIVE==1)
{
u8 MacID = *((u8*)pValue);
*((u8*)pValue) = ODM_RA_GetHwPwrStatus_8188E(podmpriv, MacID);
@ -3009,14 +3009,14 @@ static u8 GetHalDefVar8188EUsb(
u8 i;
u8 bLinked = false;
/* if(check_fwstate(&Adapter->mlmepriv, _FW_LINKED)== true) */
/* if (check_fwstate(&Adapter->mlmepriv, _FW_LINKED)== true) */
if(rtw_linked_check(Adapter))
if (rtw_linked_check(Adapter))
bLinked = true;
if(bLinked){
if (bLinked){
DBG_871X("============ RA status check ===================\n");
if(Adapter->bRxRSSIDisplay >30)
if (Adapter->bRxRSSIDisplay >30)
Adapter->bRxRSSIDisplay = 1;
for(i=0;i< Adapter->bRxRSSIDisplay;i++){
DBG_8192C("Mac_id:%d ,RSSI:%d,RateID = %d,RAUseRate = 0x%08x,RateSGI = %d, DecisionRate = 0x%02x ,PTStage = %d, RetryOver drop:%d, LifeTimeOver drop:%d\n",
@ -3074,25 +3074,25 @@ static u8 SetHalDefVar8188EUsb(
{
u8 dm_func = *(( u8*)pValue);
if(dm_func == 0){ /* disable all dynamic func */
if (dm_func == 0){ /* disable all dynamic func */
podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE;
DBG_8192C("==> Disable all dynamic function...\n");
}
else if(dm_func == 1){/* disable DIG */
else if (dm_func == 1){/* disable DIG */
podmpriv->SupportAbility &= (~DYNAMIC_BB_DIG);
DBG_8192C("==> Disable DIG...\n");
}
else if(dm_func == 2){/* disable High power */
else if (dm_func == 2){/* disable High power */
podmpriv->SupportAbility &= (~DYNAMIC_BB_DYNAMIC_TXPWR);
}
else if(dm_func == 3){/* disable tx power tracking */
else if (dm_func == 3){/* disable tx power tracking */
podmpriv->SupportAbility &= (~DYNAMIC_RF_CALIBRATION);
DBG_8192C("==> Disable tx power tracking...\n");
} else if(dm_func == 5){/* disable antenna diversity */
} else if (dm_func == 5){/* disable antenna diversity */
podmpriv->SupportAbility &= (~DYNAMIC_BB_ANT_DIV);
}
else if(dm_func == 6){/* turn on all dynamic func */
if(!(podmpriv->SupportAbility & DYNAMIC_BB_DIG))
else if (dm_func == 6){/* turn on all dynamic func */
if (!(podmpriv->SupportAbility & DYNAMIC_BB_DIG))
{
DIG_T *pDigTable = &podmpriv->DM_DigTable;
pDigTable->CurIGValue= rtw_read8(Adapter,0xc50);
@ -3154,7 +3154,7 @@ static void UpdateHalRAMask8188EUsb(struct adapter *padapter, u32 mac_id, u8 rss
}
psta = pmlmeinfo->FW_sta_info[mac_id].psta;
if(psta == NULL)
if (psta == NULL)
{
return;
}
@ -3180,7 +3180,7 @@ static void UpdateHalRAMask8188EUsb(struct adapter *padapter, u32 mac_id, u8 rss
case 1:/* for broadcast/multicast */
supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
if(pmlmeext->cur_wireless_mode & WIRELESS_11B)
if (pmlmeext->cur_wireless_mode & WIRELESS_11B)
networkType = WIRELESS_11B;
else
networkType = WIRELESS_11G;
@ -3210,7 +3210,7 @@ static void UpdateHalRAMask8188EUsb(struct adapter *padapter, u32 mac_id, u8 rss
init_rate = get_highest_rate_idx(mask)&0x3f;
if(pHalData->fw_ractrl == true)
if (pHalData->fw_ractrl == true)
{
u8 arg = 0;
@ -3224,7 +3224,7 @@ static void UpdateHalRAMask8188EUsb(struct adapter *padapter, u32 mac_id, u8 rss
DBG_871X("update raid entry, mask=0x%x, arg=0x%x\n", mask, arg);
psta->ra_mask=mask;
#ifdef CONFIG_INTEL_PROXIM
if(padapter->proximity.proxim_on ==true){
if (padapter->proximity.proxim_on ==true){
arg &= ~BIT(6);
}
else {
@ -3244,7 +3244,7 @@ static void UpdateHalRAMask8188EUsb(struct adapter *padapter, u32 mac_id, u8 rss
else
{
#if(RATE_ADAPTIVE_SUPPORT == 1)
#if (RATE_ADAPTIVE_SUPPORT == 1)
ODM_RA_UpdateRateInfo_8188E(
&(pHalData->odmpriv),
@ -3331,7 +3331,7 @@ static void rtl8188eu_init_default_value(struct adapter * padapter)
/* init default value */
pHalData->fw_ractrl = false;
if(!pwrctrlpriv->bkeepfwalive)
if (!pwrctrlpriv->bkeepfwalive)
pHalData->LastHMEBoxNum = 0;
/* init dm default value */
@ -3370,7 +3370,7 @@ void rtl8188eu_set_hal_ops(struct adapter * padapter)
padapter->HalData = rtw_zmalloc(sizeof(HAL_DATA_TYPE));
if(padapter->HalData == NULL){
if (padapter->HalData == NULL){
DBG_8192C("cant not alloc memory for HAL DATA\n");
}