mirror of
https://github.com/lwfinger/rtl8188eu.git
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rtl8188EUS: Initial addition of files in branch v5.2.2.4
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
parent
77471b4361
commit
6fa9ed423c
541 changed files with 393757 additions and 85553 deletions
571
core/rtw_odm.c
571
core/rtw_odm.c
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@ -19,187 +19,428 @@
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******************************************************************************/
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#include <rtw_odm.h>
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#include <rtl8188e_hal.h>
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#include <hal_data.h>
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static const char *odm_comp_str[] = {
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"ODM_COMP_DIG",
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"ODM_COMP_RA_MASK",
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"ODM_COMP_DYNAMIC_TXPWR",
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"ODM_COMP_FA_CNT",
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"ODM_COMP_RSSI_MONITOR",
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"ODM_COMP_CCK_PD",
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"ODM_COMP_ANT_DIV",
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"ODM_COMP_PWR_SAVE",
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"ODM_COMP_PWR_TRAIN",
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"ODM_COMP_RATE_ADAPTIVE",
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"ODM_COMP_PATH_DIV",
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"ODM_COMP_PSD",
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"ODM_COMP_DYNAMIC_PRICCA",
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"ODM_COMP_RXHP",
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NULL,
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NULL,
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"ODM_COMP_EDCA_TURBO",
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"ODM_COMP_EARLY_MODE",
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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"ODM_COMP_TX_PWR_TRACK",
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"ODM_COMP_RX_GAIN_TRACK",
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"ODM_COMP_CALIBRATION",
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NULL,
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NULL,
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NULL,
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"ODM_COMP_COMMON",
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"ODM_COMP_INIT",
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};
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#define RTW_ODM_COMP_MAX 32
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static const char *odm_ability_str[] = {
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"ODM_BB_DIG",
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"ODM_BB_RA_MASK",
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"ODM_BB_DYNAMIC_TXPWR",
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"ODM_BB_FA_CNT",
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"ODM_BB_RSSI_MONITOR",
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"ODM_BB_CCK_PD ",
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"ODM_BB_ANT_DIV",
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"ODM_BB_PWR_SAVE",
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"ODM_BB_PWR_TRAIN",
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"ODM_BB_RATE_ADAPTIVE",
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"ODM_BB_PATH_DIV",
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"ODM_BB_PSD",
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"ODM_BB_RXHP",
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"ODM_BB_ADAPTIVITY",
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"ODM_BB_DYNAMIC_ATC",
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NULL,
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"ODM_MAC_EDCA_TURBO",
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"ODM_MAC_EARLY_MODE",
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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"ODM_RF_TX_PWR_TRACK",
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"ODM_RF_RX_GAIN_TRACK",
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"ODM_RF_CALIBRATION",
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};
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/* set ODM_CMNINFO_IC_TYPE based on chip_type */
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void rtw_odm_init_ic_type(_adapter *adapter)
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{
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HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
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struct PHY_DM_STRUCT *odm = &hal_data->odmpriv;
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u4Byte ic_type = chip_type_to_odm_ic_type(rtw_get_chip_type(adapter));
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#define RTW_ODM_ABILITY_MAX 27
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rtw_warn_on(!ic_type);
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static const char *odm_dbg_level_str[] = {
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NULL,
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"ODM_DBG_OFF",
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"ODM_DBG_SERIOUS",
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"ODM_DBG_WARNING",
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"ODM_DBG_LOUD",
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"ODM_DBG_TRACE ",
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};
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odm_cmn_info_init(odm, ODM_CMNINFO_IC_TYPE, ic_type);
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}
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#define RTW_ODM_DBG_LEVEL_NUM 6
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inline void rtw_odm_set_force_igi_lb(_adapter *adapter, u8 lb)
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{
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HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
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int _rtw_odm_dbg_comp_msg(struct adapter *adapter, char *buf, int len)
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hal_data->u1ForcedIgiLb = lb;
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}
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inline u8 rtw_odm_get_force_igi_lb(_adapter *adapter)
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{
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HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
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return hal_data->u1ForcedIgiLb;
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}
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void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter)
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{
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RTW_PRINT_SEL(sel, "ADAPTIVITY_VERSION "ADAPTIVITY_VERSION"\n");
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}
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#define RTW_ADAPTIVITY_EN_DISABLE 0
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#define RTW_ADAPTIVITY_EN_ENABLE 1
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void rtw_odm_adaptivity_en_msg(void *sel, _adapter *adapter)
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{
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struct registry_priv *regsty = &adapter->registrypriv;
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struct mlme_priv *mlme = &adapter->mlmepriv;
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HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
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struct PHY_DM_STRUCT *odm = &hal_data->odmpriv;
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RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_EN_");
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if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_DISABLE)
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_RTW_PRINT_SEL(sel, "DISABLE\n");
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else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE)
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_RTW_PRINT_SEL(sel, "ENABLE\n");
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else
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_RTW_PRINT_SEL(sel, "INVALID\n");
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}
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#define RTW_ADAPTIVITY_MODE_NORMAL 0
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#define RTW_ADAPTIVITY_MODE_CARRIER_SENSE 1
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void rtw_odm_adaptivity_mode_msg(void *sel, _adapter *adapter)
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{
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struct registry_priv *regsty = &adapter->registrypriv;
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RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_MODE_");
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if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_NORMAL)
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_RTW_PRINT_SEL(sel, "NORMAL\n");
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else if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_CARRIER_SENSE)
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_RTW_PRINT_SEL(sel, "CARRIER_SENSE\n");
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else
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_RTW_PRINT_SEL(sel, "INVALID\n");
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}
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#define RTW_ADAPTIVITY_DML_DISABLE 0
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#define RTW_ADAPTIVITY_DML_ENABLE 1
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void rtw_odm_adaptivity_dml_msg(void *sel, _adapter *adapter)
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{
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struct registry_priv *regsty = &adapter->registrypriv;
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RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_DML_");
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if (regsty->adaptivity_dml == RTW_ADAPTIVITY_DML_DISABLE)
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_RTW_PRINT_SEL(sel, "DISABLE\n");
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else if (regsty->adaptivity_dml == RTW_ADAPTIVITY_DML_ENABLE)
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_RTW_PRINT_SEL(sel, "ENABLE\n");
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else
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_RTW_PRINT_SEL(sel, "INVALID\n");
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}
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void rtw_odm_adaptivity_dc_backoff_msg(void *sel, _adapter *adapter)
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{
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struct registry_priv *regsty = &adapter->registrypriv;
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RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_DC_BACKOFF:%u\n", regsty->adaptivity_dc_backoff);
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}
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void rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter)
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{
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rtw_odm_adaptivity_ver_msg(sel, adapter);
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rtw_odm_adaptivity_en_msg(sel, adapter);
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rtw_odm_adaptivity_mode_msg(sel, adapter);
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rtw_odm_adaptivity_dml_msg(sel, adapter);
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rtw_odm_adaptivity_dc_backoff_msg(sel, adapter);
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}
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bool rtw_odm_adaptivity_needed(_adapter *adapter)
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{
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struct registry_priv *regsty = &adapter->registrypriv;
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struct mlme_priv *mlme = &adapter->mlmepriv;
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bool ret = _FALSE;
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if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE)
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ret = _TRUE;
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return ret;
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}
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void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter)
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{
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
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DM_ODM_T *odm = &pHalData->odmpriv;
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int cnt = 0;
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u64 dbg_comp;
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int i;
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struct PHY_DM_STRUCT *odm = &pHalData->odmpriv;
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rtw_hal_get_def_var(adapter, HW_DEF_ODM_DBG_FLAG, &dbg_comp);
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cnt += snprintf(buf+cnt, len-cnt, "odm.DebugComponents = 0x%016llx\n", dbg_comp);
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for (i =0;i<RTW_ODM_COMP_MAX;i++) {
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if (odm_comp_str[i])
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cnt += snprintf(buf+cnt, len-cnt, "%cBIT%-2d %s\n",
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(BIT0 << i) & dbg_comp ? '+' : ' ', i, odm_comp_str[i]);
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}
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rtw_odm_adaptivity_config_msg(sel, adapter);
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return cnt;
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}
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RTW_PRINT_SEL(sel, "%10s %16s %16s %22s %12s\n"
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, "th_l2h_ini", "th_edcca_hl_diff", "th_l2h_ini_mode2", "th_edcca_hl_diff_mode2", "edcca_enable");
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RTW_PRINT_SEL(sel, "0x%-8x %-16d 0x%-14x %-22d %-12d\n"
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, (u8)odm->th_l2h_ini
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, odm->th_edcca_hl_diff
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, (u8)odm->th_l2h_ini_mode2
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, odm->th_edcca_hl_diff_mode2
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, odm->edcca_enable
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);
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void rtw_odm_dbg_comp_msg(struct adapter *adapter)
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{
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char buf[768] = {0};
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_rtw_odm_dbg_comp_msg(adapter, buf, 768);
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DBG_88E_LEVEL(_drv_always_, "\n%s", buf);
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}
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inline void rtw_odm_dbg_comp_set(struct adapter *adapter, u64 comps)
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{
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rtw_hal_set_def_var(adapter, HW_DEF_ODM_DBG_FLAG, &comps);
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}
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int _rtw_odm_dbg_level_msg(struct adapter *adapter, char *buf, int len)
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{
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
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DM_ODM_T *odm = &pHalData->odmpriv;
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int cnt = 0;
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u32 dbg_level;
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int i;
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rtw_hal_get_def_var(adapter, HW_DEF_ODM_DBG_LEVEL, &dbg_level);
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cnt += snprintf(buf+cnt, len-cnt, "odm.DebugDebugLevel = %u\n", dbg_level);
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for (i =0;i<RTW_ODM_DBG_LEVEL_NUM;i++) {
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if (odm_dbg_level_str[i])
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cnt += snprintf(buf+cnt, len-cnt, "%u %s\n", i, odm_dbg_level_str[i]);
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}
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return cnt;
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}
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void rtw_odm_dbg_level_msg(struct adapter *adapter)
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{
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char buf[100] = {0};
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_rtw_odm_dbg_comp_msg(adapter, buf, 100);
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DBG_88E_LEVEL(_drv_always_, "\n%s", buf);
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}
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inline void rtw_odm_dbg_level_set(struct adapter *adapter, u32 level)
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{
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rtw_hal_set_def_var(adapter, HW_DEF_ODM_DBG_LEVEL, &level);
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}
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int _rtw_odm_adaptivity_parm_msg(struct adapter *adapter, char *buf, int len)
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{
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
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DM_ODM_T *odm = &pHalData->odmpriv;
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return snprintf(buf, len,
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"%10s %16s %8s %10s %11s %14s\n"
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"0x%-8x %-16d 0x%-6x %-10d %-11u %-14u\n",
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"TH_L2H_ini", "TH_EDCCA_HL_diff", "IGI_Base", "ForceEDCCA", "AdapEn_RSSI", "IGI_LowerBound",
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(u8)odm->TH_L2H_ini,
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odm->TH_EDCCA_HL_diff,
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odm->IGI_Base,
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odm->ForceEDCCA,
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odm->AdapEn_RSSI,
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odm->IGI_LowerBound
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RTW_PRINT_SEL(sel, "%15s %9s\n", "AdapEnableState", "Adap_Flag");
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RTW_PRINT_SEL(sel, "%-15x %-9x\n"
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, odm->adaptivity_enable
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, odm->adaptivity_flag
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);
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}
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void rtw_odm_adaptivity_parm_msg(struct adapter *adapter)
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{
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char buf[256] = {0};
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_rtw_odm_dbg_comp_msg(adapter, buf, 256);
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DBG_88E_LEVEL(_drv_always_, "\n%s", buf);
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}
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void rtw_odm_adaptivity_parm_set(struct adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff,
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s8 IGI_Base, bool ForceEDCCA, u8 AdapEn_RSSI, u8 IGI_LowerBound)
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void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff, s8 th_l2h_ini_mode2, s8 th_edcca_hl_diff_mode2, u8 edcca_enable)
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{
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
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DM_ODM_T *odm = &pHalData->odmpriv;
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struct PHY_DM_STRUCT *odm = &pHalData->odmpriv;
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odm->TH_L2H_ini = TH_L2H_ini;
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odm->TH_EDCCA_HL_diff = TH_EDCCA_HL_diff;
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odm->IGI_Base = IGI_Base;
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odm->ForceEDCCA = ForceEDCCA;
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odm->AdapEn_RSSI = AdapEn_RSSI;
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odm->IGI_LowerBound = IGI_LowerBound;
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odm->th_l2h_ini = th_l2h_ini;
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odm->th_edcca_hl_diff = th_edcca_hl_diff;
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odm->th_l2h_ini_mode2 = th_l2h_ini_mode2;
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odm->th_edcca_hl_diff_mode2 = th_edcca_hl_diff_mode2;
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odm->edcca_enable = edcca_enable;
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}
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void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter)
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{
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HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
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struct PHY_DM_STRUCT *odm = &(hal_data->odmpriv);
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RTW_PRINT_SEL(sel, "rx_rate = %s, RSSI_A = %d(%%), RSSI_B = %d(%%)\n",
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HDATA_RATE(odm->rx_rate), odm->RSSI_A, odm->RSSI_B);
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}
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void rtw_odm_acquirespinlock(_adapter *adapter, enum rt_spinlock_type type)
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{
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PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
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_irqL irqL;
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switch (type) {
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case RT_IQK_SPINLOCK:
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_enter_critical_bh(&pHalData->IQKSpinLock, &irqL);
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default:
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break;
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}
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}
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void rtw_odm_releasespinlock(_adapter *adapter, enum rt_spinlock_type type)
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{
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PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
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_irqL irqL;
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switch (type) {
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case RT_IQK_SPINLOCK:
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_exit_critical_bh(&pHalData->IQKSpinLock, &irqL);
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default:
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break;
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}
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}
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inline u8 rtw_odm_get_dfs_domain(_adapter *adapter)
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{
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#ifdef CONFIG_DFS_MASTER
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HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
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struct PHY_DM_STRUCT *pDM_Odm = &(hal_data->odmpriv);
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return pDM_Odm->dfs_region_domain;
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#else
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return PHYDM_DFS_DOMAIN_UNKNOWN;
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#endif
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}
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inline u8 rtw_odm_dfs_domain_unknown(_adapter *adapter)
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{
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#ifdef CONFIG_DFS_MASTER
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return rtw_odm_get_dfs_domain(adapter) == PHYDM_DFS_DOMAIN_UNKNOWN;
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#else
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return 1;
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#endif
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}
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#ifdef CONFIG_DFS_MASTER
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inline VOID rtw_odm_radar_detect_reset(_adapter *adapter)
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{
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phydm_radar_detect_reset(GET_ODM(adapter));
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}
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inline VOID rtw_odm_radar_detect_disable(_adapter *adapter)
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{
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phydm_radar_detect_disable(GET_ODM(adapter));
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}
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/* called after ch, bw is set */
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inline VOID rtw_odm_radar_detect_enable(_adapter *adapter)
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{
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phydm_radar_detect_enable(GET_ODM(adapter));
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}
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inline BOOLEAN rtw_odm_radar_detect(_adapter *adapter)
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{
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return phydm_radar_detect(GET_ODM(adapter));
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}
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#endif /* CONFIG_DFS_MASTER */
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void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys)
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{
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#ifndef DBG_RX_PHYSTATUS_CHINFO
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#define DBG_RX_PHYSTATUS_CHINFO 0
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#endif
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#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
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_adapter *adapter = rframe->u.hdr.adapter;
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struct PHY_DM_STRUCT *phydm = GET_ODM(adapter);
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struct rx_pkt_attrib *attrib = &rframe->u.hdr.attrib;
|
||||
u8 *wlanhdr = get_recvframe_data(rframe);
|
||||
|
||||
if (phydm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) {
|
||||
/*
|
||||
* 8723D:
|
||||
* type_0(CCK)
|
||||
* l_rxsc
|
||||
* is filled with primary channel SC, not real rxsc.
|
||||
* 0:LSC, 1:USC
|
||||
* type_1(OFDM)
|
||||
* rf_mode
|
||||
* RF bandwidth when RX
|
||||
* l_rxsc(legacy), ht_rxsc
|
||||
* see below RXSC N-series
|
||||
* type_2(Not used)
|
||||
*/
|
||||
/*
|
||||
* 8821C, 8822B:
|
||||
* type_0(CCK)
|
||||
* l_rxsc
|
||||
* is filled with primary channel SC, not real rxsc.
|
||||
* 0:LSC, 1:USC
|
||||
* type_1(OFDM)
|
||||
* rf_mode
|
||||
* RF bandwidth when RX
|
||||
* l_rxsc(legacy), ht_rxsc
|
||||
* see below RXSC AC-series
|
||||
* type_2(Not used)
|
||||
*/
|
||||
|
||||
if ((*phys & 0xf) == 0) {
|
||||
struct _phy_status_rpt_jaguar2_type0 *phys_t0 = (struct _phy_status_rpt_jaguar2_type0 *)phys;
|
||||
|
||||
if (DBG_RX_PHYSTATUS_CHINFO) {
|
||||
RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u)\n"
|
||||
, *phys & 0xf
|
||||
, MAC_ARG(get_ta(wlanhdr))
|
||||
, is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
|
||||
, HDATA_RATE(attrib->data_rate)
|
||||
, phys_t0->band, phys_t0->channel, phys_t0->rxsc
|
||||
);
|
||||
}
|
||||
|
||||
} else if ((*phys & 0xf) == 1) {
|
||||
struct _phy_status_rpt_jaguar2_type1 *phys_t1 = (struct _phy_status_rpt_jaguar2_type1 *)phys;
|
||||
u8 rxsc = (attrib->data_rate > DESC_RATE11M && attrib->data_rate < DESC_RATEMCS0) ? phys_t1->l_rxsc : phys_t1->ht_rxsc;
|
||||
u8 pkt_cch = 0;
|
||||
u8 pkt_bw = CHANNEL_WIDTH_20;
|
||||
|
||||
#if ODM_IC_11N_SERIES_SUPPORT
|
||||
if (phydm->support_ic_type & ODM_IC_11N_SERIES) {
|
||||
/* RXSC N-series */
|
||||
#define RXSC_DUP 0
|
||||
#define RXSC_LSC 1
|
||||
#define RXSC_USC 2
|
||||
#define RXSC_40M 3
|
||||
|
||||
static const s8 cch_offset_by_rxsc[4] = {0, -2, 2, 0};
|
||||
|
||||
if (phys_t1->rf_mode == 0) {
|
||||
pkt_cch = phys_t1->channel;
|
||||
pkt_bw = CHANNEL_WIDTH_20;
|
||||
} else if (phys_t1->rf_mode == 1) {
|
||||
if (rxsc == RXSC_LSC || rxsc == RXSC_USC) {
|
||||
pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
|
||||
pkt_bw = CHANNEL_WIDTH_20;
|
||||
} else if (rxsc == RXSC_40M) {
|
||||
pkt_cch = phys_t1->channel;
|
||||
pkt_bw = CHANNEL_WIDTH_40;
|
||||
}
|
||||
} else
|
||||
rtw_warn_on(1);
|
||||
|
||||
goto type1_end;
|
||||
}
|
||||
#endif /* ODM_IC_11N_SERIES_SUPPORT */
|
||||
|
||||
#if ODM_IC_11AC_SERIES_SUPPORT
|
||||
if (phydm->support_ic_type & ODM_IC_11AC_SERIES) {
|
||||
/* RXSC AC-series */
|
||||
#define RXSC_DUP 0 /* 0: RX from all SC of current rf_mode */
|
||||
|
||||
#define RXSC_LL20M_OF_160M 8 /* 1~8: RX from 20MHz SC */
|
||||
#define RXSC_L20M_OF_160M 6
|
||||
#define RXSC_L20M_OF_80M 4
|
||||
#define RXSC_L20M_OF_40M 2
|
||||
#define RXSC_U20M_OF_40M 1
|
||||
#define RXSC_U20M_OF_80M 3
|
||||
#define RXSC_U20M_OF_160M 5
|
||||
#define RXSC_UU20M_OF_160M 7
|
||||
|
||||
#define RXSC_L40M_OF_160M 12 /* 9~12: RX from 40MHz SC */
|
||||
#define RXSC_L40M_OF_80M 10
|
||||
#define RXSC_U40M_OF_80M 9
|
||||
#define RXSC_U40M_OF_160M 11
|
||||
|
||||
#define RXSC_L80M_OF_160M 14 /* 13~14: RX from 80MHz SC */
|
||||
#define RXSC_U80M_OF_160M 13
|
||||
|
||||
static const s8 cch_offset_by_rxsc[15] = {0, 2, -2, 6, -6, 10, -10, 14, -14, 4, -4, 12, -12, 8, -8};
|
||||
|
||||
if (phys_t1->rf_mode > 3) {
|
||||
/* invalid rf_mode */
|
||||
rtw_warn_on(1);
|
||||
goto type1_end;
|
||||
}
|
||||
|
||||
if (phys_t1->rf_mode == 0) {
|
||||
/* RF 20MHz */
|
||||
pkt_cch = phys_t1->channel;
|
||||
pkt_bw = CHANNEL_WIDTH_20;
|
||||
goto type1_end;
|
||||
}
|
||||
|
||||
if (rxsc == 0) {
|
||||
/* RF and RX with same BW */
|
||||
if (attrib->data_rate >= DESC_RATEMCS0) {
|
||||
pkt_cch = phys_t1->channel;
|
||||
pkt_bw = phys_t1->rf_mode;
|
||||
}
|
||||
goto type1_end;
|
||||
}
|
||||
|
||||
if ((phys_t1->rf_mode == 1 && rxsc >= 1 && rxsc <= 2) /* RF 40MHz, RX 20MHz */
|
||||
|| (phys_t1->rf_mode == 2 && rxsc >= 1 && rxsc <= 4) /* RF 80MHz, RX 20MHz */
|
||||
|| (phys_t1->rf_mode == 3 && rxsc >= 1 && rxsc <= 8) /* RF 160MHz, RX 20MHz */
|
||||
) {
|
||||
pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
|
||||
pkt_bw = CHANNEL_WIDTH_20;
|
||||
} else if ((phys_t1->rf_mode == 2 && rxsc >= 9 && rxsc <= 10) /* RF 80MHz, RX 40MHz */
|
||||
|| (phys_t1->rf_mode == 3 && rxsc >= 9 && rxsc <= 12) /* RF 160MHz, RX 40MHz */
|
||||
) {
|
||||
if (attrib->data_rate >= DESC_RATEMCS0) {
|
||||
pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
|
||||
pkt_bw = CHANNEL_WIDTH_40;
|
||||
}
|
||||
} else if ((phys_t1->rf_mode == 3 && rxsc >= 13 && rxsc <= 14) /* RF 160MHz, RX 80MHz */
|
||||
) {
|
||||
if (attrib->data_rate >= DESC_RATEMCS0) {
|
||||
pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
|
||||
pkt_bw = CHANNEL_WIDTH_80;
|
||||
}
|
||||
} else
|
||||
rtw_warn_on(1);
|
||||
|
||||
}
|
||||
#endif /* ODM_IC_11AC_SERIES_SUPPORT */
|
||||
|
||||
type1_end:
|
||||
if (DBG_RX_PHYSTATUS_CHINFO) {
|
||||
RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, rf_mode:%u, l_rxsc:%u, ht_rxsc:%u) => %u,%u\n"
|
||||
, *phys & 0xf
|
||||
, MAC_ARG(get_ta(wlanhdr))
|
||||
, is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
|
||||
, HDATA_RATE(attrib->data_rate)
|
||||
, phys_t1->band, phys_t1->channel, phys_t1->rf_mode, phys_t1->l_rxsc, phys_t1->ht_rxsc
|
||||
, pkt_cch, pkt_bw
|
||||
);
|
||||
}
|
||||
|
||||
/* for now, only return cneter channel of 20MHz packet */
|
||||
if (pkt_cch && pkt_bw == CHANNEL_WIDTH_20)
|
||||
attrib->ch = pkt_cch;
|
||||
|
||||
} else {
|
||||
struct _phy_status_rpt_jaguar2_type2 *phys_t2 = (struct _phy_status_rpt_jaguar2_type2 *)phys;
|
||||
|
||||
if (DBG_RX_PHYSTATUS_CHINFO) {
|
||||
RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u, ht_rxsc:%u)\n"
|
||||
, *phys & 0xf
|
||||
, MAC_ARG(get_ta(wlanhdr))
|
||||
, is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
|
||||
, HDATA_RATE(attrib->data_rate)
|
||||
, phys_t2->band, phys_t2->channel, phys_t2->l_rxsc, phys_t2->ht_rxsc
|
||||
);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) */
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue