mirror of
https://github.com/lwfinger/rtl8188eu.git
synced 2025-05-09 06:43:06 +00:00
rtl8188EUS: Initial addition of files in branch v5.2.2.4
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
parent
77471b4361
commit
6fa9ed423c
541 changed files with 393757 additions and 85553 deletions
123
hal/phydm/halhwimg.h
Normal file
123
hal/phydm/halhwimg.h
Normal file
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@ -0,0 +1,123 @@
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#pragma once
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#ifndef __INC_HW_IMG_H
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#define __INC_HW_IMG_H
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/*
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* 2011/03/15 MH Add for different IC HW image file selection. code size consideration.
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* */
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#if RT_PLATFORM == PLATFORM_LINUX
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#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
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/* For 92C */
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#define RTL8192CE_HWIMG_SUPPORT 1
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#define RTL8192CE_TEST_HWIMG_SUPPORT 0
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#define RTL8192CU_HWIMG_SUPPORT 0
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#define RTL8192CU_TEST_HWIMG_SUPPORT 0
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/* For 92D */
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#define RTL8192DE_HWIMG_SUPPORT 1
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#define RTL8192DE_TEST_HWIMG_SUPPORT 0
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#define RTL8192DU_HWIMG_SUPPORT 0
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#define RTL8192DU_TEST_HWIMG_SUPPORT 0
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/* For 8723 */
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#define RTL8723E_HWIMG_SUPPORT 1
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#define RTL8723U_HWIMG_SUPPORT 0
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#define RTL8723S_HWIMG_SUPPORT 0
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/* For 88E */
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#define RTL8188EE_HWIMG_SUPPORT 0
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#define RTL8188EU_HWIMG_SUPPORT 0
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#define RTL8188ES_HWIMG_SUPPORT 0
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#elif (DEV_BUS_TYPE == RT_USB_INTERFACE)
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/* For 92C */
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#define RTL8192CE_HWIMG_SUPPORT 0
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#define RTL8192CE_TEST_HWIMG_SUPPORT 0
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#define RTL8192CU_HWIMG_SUPPORT 1
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#define RTL8192CU_TEST_HWIMG_SUPPORT 0
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/* For 92D */
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#define RTL8192DE_HWIMG_SUPPORT 0
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#define RTL8192DE_TEST_HWIMG_SUPPORT 0
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#define RTL8192DU_HWIMG_SUPPORT 1
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#define RTL8192DU_TEST_HWIMG_SUPPORT 0
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/* For 8723 */
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#define RTL8723E_HWIMG_SUPPORT 0
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#define RTL8723U_HWIMG_SUPPORT 1
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#define RTL8723S_HWIMG_SUPPORT 0
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/* For 88E */
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#define RTL8188EE_HWIMG_SUPPORT 0
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#define RTL8188EU_HWIMG_SUPPORT 0
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#define RTL8188ES_HWIMG_SUPPORT 0
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#elif (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
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/* For 92C */
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#define RTL8192CE_HWIMG_SUPPORT 0
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#define RTL8192CE_TEST_HWIMG_SUPPORT 0
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#define RTL8192CU_HWIMG_SUPPORT 1
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#define RTL8192CU_TEST_HWIMG_SUPPORT 0
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/* For 92D */
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#define RTL8192DE_HWIMG_SUPPORT 0
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#define RTL8192DE_TEST_HWIMG_SUPPORT 0
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#define RTL8192DU_HWIMG_SUPPORT 1
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#define RTL8192DU_TEST_HWIMG_SUPPORT 0
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/* For 8723 */
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#define RTL8723E_HWIMG_SUPPORT 0
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#define RTL8723U_HWIMG_SUPPORT 0
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#define RTL8723S_HWIMG_SUPPORT 1
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/* For 88E */
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#define RTL8188EE_HWIMG_SUPPORT 0
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#define RTL8188EU_HWIMG_SUPPORT 0
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#define RTL8188ES_HWIMG_SUPPORT 0
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#endif
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#else /* PLATFORM_WINDOWS & MacOSX */
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/* For 92C */
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#define RTL8192CE_HWIMG_SUPPORT 1
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#define RTL8192CE_TEST_HWIMG_SUPPORT 1
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#define RTL8192CU_HWIMG_SUPPORT 1
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#define RTL8192CU_TEST_HWIMG_SUPPORT 1
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/* For 92D */
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#define RTL8192DE_HWIMG_SUPPORT 1
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#define RTL8192DE_TEST_HWIMG_SUPPORT 1
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#define RTL8192DU_HWIMG_SUPPORT 1
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#define RTL8192DU_TEST_HWIMG_SUPPORT 1
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#if defined(UNDER_CE)
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/* For 8723 */
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#define RTL8723E_HWIMG_SUPPORT 0
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#define RTL8723U_HWIMG_SUPPORT 0
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#define RTL8723S_HWIMG_SUPPORT 1
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/* For 88E */
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#define RTL8188EE_HWIMG_SUPPORT 0
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#define RTL8188EU_HWIMG_SUPPORT 0
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#define RTL8188ES_HWIMG_SUPPORT 0
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#else
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/* For 8723 */
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#define RTL8723E_HWIMG_SUPPORT 1
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/* #define RTL_8723E_TEST_HWIMG_SUPPORT 1 */
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#define RTL8723U_HWIMG_SUPPORT 1
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/* #define RTL_8723U_TEST_HWIMG_SUPPORT 1 */
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#define RTL8723S_HWIMG_SUPPORT 1
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/* #define RTL_8723S_TEST_HWIMG_SUPPORT 1 */
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/* For 88E */
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#define RTL8188EE_HWIMG_SUPPORT 1
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#define RTL8188EU_HWIMG_SUPPORT 1
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#define RTL8188ES_HWIMG_SUPPORT 1
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#endif
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#endif
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#endif /* __INC_HW_IMG_H */
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2665
hal/phydm/halphyrf_ap.c
Normal file
2665
hal/phydm/halphyrf_ap.c
Normal file
File diff suppressed because it is too large
Load diff
178
hal/phydm/halphyrf_ap.h
Normal file
178
hal/phydm/halphyrf_ap.h
Normal file
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@ -0,0 +1,178 @@
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __HAL_PHY_RF_H__
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#define __HAL_PHY_RF_H__
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#include "phydm_powertracking_ap.h"
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#if (RTL8814A_SUPPORT == 1)
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#include "rtl8814a/phydm_iqk_8814a.h"
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#endif
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#if (RTL8822B_SUPPORT == 1)
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#include "rtl8822b/phydm_iqk_8822b.h"
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#endif
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#if (RTL8821C_SUPPORT == 1)
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#include "rtl8822b/phydm_iqk_8821c.h"
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#endif
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enum pwrtrack_method {
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BBSWING,
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TXAGC,
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MIX_MODE,
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TSSI_MODE
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};
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typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
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typedef void(*func_iqk)(void *, u8, u8, u8);
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typedef void (*func_lck)(void *);
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/* refine by YuChen for 8814A */
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typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
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typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
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typedef void (*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
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struct _TXPWRTRACK_CFG {
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u8 swing_table_size_cck;
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u8 swing_table_size_ofdm;
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u8 threshold_iqk;
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u8 threshold_dpk;
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u8 average_thermal_num;
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u8 rf_path_count;
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u32 thermal_reg_addr;
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func_set_pwr odm_tx_pwr_track_set_pwr;
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func_iqk do_iqk;
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func_lck phy_lc_calibrate;
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func_swing get_delta_swing_table;
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func_swing8814only get_delta_swing_table8814only;
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func_all_swing get_delta_all_swing_table;
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};
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void
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configure_txpower_track(
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void *p_dm_void,
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struct _TXPWRTRACK_CFG *p_config
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);
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void
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odm_txpowertracking_callback_thermal_meter(
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#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
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void *p_dm_void
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#else
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struct _ADAPTER *adapter
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#endif
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);
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#if (RTL8192E_SUPPORT == 1)
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void
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odm_txpowertracking_callback_thermal_meter_92e(
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#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
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void *p_dm_void
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#else
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struct _ADAPTER *adapter
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#endif
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);
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#endif
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#if (RTL8814A_SUPPORT == 1)
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void
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odm_txpowertracking_callback_thermal_meter_jaguar_series2(
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#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
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void *p_dm_void
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#else
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struct _ADAPTER *adapter
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#endif
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);
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#elif ODM_IC_11AC_SERIES_SUPPORT
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void
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odm_txpowertracking_callback_thermal_meter_jaguar_series(
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#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
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void *p_dm_void
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#else
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struct _ADAPTER *adapter
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#endif
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);
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#elif (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
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void
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odm_txpowertracking_callback_thermal_meter_jaguar_series3(
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#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
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void *p_dm_void
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#else
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struct _ADAPTER *adapter
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#endif
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);
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#endif
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#define IS_CCK_RATE(_rate) (ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M)
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#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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#define MAX_TOLERANCE 5
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#define IQK_DELAY_TIME 1 /* ms */
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/*
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* BB/MAC/RF other monitor API
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* */
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void phy_set_monitor_mode8192c(struct _ADAPTER *p_adapter,
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bool is_enable_monitor_mode);
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/*
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* IQ calibrate
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* */
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void
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phy_iq_calibrate_8192c(struct _ADAPTER *p_adapter,
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bool is_recovery);
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/*
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* LC calibrate
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* */
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void
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phy_lc_calibrate_8192c(struct _ADAPTER *p_adapter);
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/*
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* AP calibrate
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* */
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void
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phy_ap_calibrate_8192c(struct _ADAPTER *p_adapter,
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s8 delta);
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#endif
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#define ODM_TARGET_CHNL_NUM_2G_5G 59
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void
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odm_reset_iqk_result(
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void *p_dm_void
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);
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u8
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odm_get_right_chnl_place_for_iqk(
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u8 chnl
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);
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void phydm_rf_init(void *p_dm_void);
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void phydm_rf_watchdog(void *p_dm_void);
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#endif /* #ifndef __HAL_PHY_RF_H__ */
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799
hal/phydm/halphyrf_ce.c
Normal file
799
hal/phydm/halphyrf_ce.c
Normal file
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@ -0,0 +1,799 @@
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/******************************************************************************
|
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*
|
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
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*
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* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
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* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
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*
|
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*
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******************************************************************************/
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#include "mp_precomp.h"
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#include "phydm_precomp.h"
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#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \
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do {\
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for (_offset = 0; _offset < _size; _offset++) { \
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\
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if (_delta_thermal < thermal_threshold[_direction][_offset]) { \
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\
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if (_offset != 0)\
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_offset--;\
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break;\
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} \
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} \
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if (_offset >= _size)\
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_offset = _size-1;\
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} while (0)
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void configure_txpower_track(
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void *p_dm_void,
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struct _TXPWRTRACK_CFG *p_config
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)
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{
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struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
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|
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#if RTL8192E_SUPPORT
|
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if (p_dm_odm->support_ic_type == ODM_RTL8192E)
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configure_txpower_track_8192e(p_config);
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#endif
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#if RTL8821A_SUPPORT
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if (p_dm_odm->support_ic_type == ODM_RTL8821)
|
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configure_txpower_track_8821a(p_config);
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#endif
|
||||
#if RTL8812A_SUPPORT
|
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if (p_dm_odm->support_ic_type == ODM_RTL8812)
|
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configure_txpower_track_8812a(p_config);
|
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#endif
|
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#if RTL8188E_SUPPORT
|
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if (p_dm_odm->support_ic_type == ODM_RTL8188E)
|
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configure_txpower_track_8188e(p_config);
|
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#endif
|
||||
|
||||
#if RTL8723B_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8723B)
|
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configure_txpower_track_8723b(p_config);
|
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#endif
|
||||
|
||||
#if RTL8814A_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8814A)
|
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configure_txpower_track_8814a(p_config);
|
||||
#endif
|
||||
|
||||
#if RTL8703B_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8703B)
|
||||
configure_txpower_track_8703b(p_config);
|
||||
#endif
|
||||
|
||||
#if RTL8188F_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8188F)
|
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configure_txpower_track_8188f(p_config);
|
||||
#endif
|
||||
#if RTL8723D_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8723D)
|
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configure_txpower_track_8723d(p_config);
|
||||
#endif
|
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#if RTL8822B_SUPPORT
|
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if (p_dm_odm->support_ic_type == ODM_RTL8822B)
|
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configure_txpower_track_8822b(p_config);
|
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#endif
|
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#if RTL8821C_SUPPORT
|
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if (p_dm_odm->support_ic_type == ODM_RTL8821C)
|
||||
configure_txpower_track_8821c(p_config);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/* **********************************************************************
|
||||
* <20121113, Kordan> This function should be called when tx_agc changed.
|
||||
* Otherwise the previous compensation is gone, because we record the
|
||||
* delta of temperature between two TxPowerTracking watch dogs.
|
||||
*
|
||||
* NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
|
||||
* need to call this function.
|
||||
* ********************************************************************** */
|
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void
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odm_clear_txpowertracking_state(
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void *p_dm_void
|
||||
)
|
||||
{
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struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
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PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(p_dm_odm->adapter);
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u8 p = 0;
|
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struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
|
||||
|
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p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index;
|
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p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->default_cck_index;
|
||||
p_dm_odm->rf_calibrate_info.CCK_index = 0;
|
||||
|
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for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) {
|
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p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->default_ofdm_index;
|
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p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->default_ofdm_index;
|
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p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index;
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|
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p_rf_calibrate_info->power_index_offset[p] = 0;
|
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p_rf_calibrate_info->delta_power_index[p] = 0;
|
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p_rf_calibrate_info->delta_power_index_last[p] = 0;
|
||||
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = 0; /* Initial Mix mode power tracking*/
|
||||
p_rf_calibrate_info->remnant_ofdm_swing_idx[p] = 0;
|
||||
p_rf_calibrate_info->kfree_offset[p] = 0;
|
||||
}
|
||||
|
||||
p_rf_calibrate_info->modify_tx_agc_flag_path_a = false; /*Initial at Modify Tx Scaling mode*/
|
||||
p_rf_calibrate_info->modify_tx_agc_flag_path_b = false; /*Initial at Modify Tx Scaling mode*/
|
||||
p_rf_calibrate_info->modify_tx_agc_flag_path_c = false; /*Initial at Modify Tx Scaling mode*/
|
||||
p_rf_calibrate_info->modify_tx_agc_flag_path_d = false; /*Initial at Modify Tx Scaling mode*/
|
||||
p_rf_calibrate_info->remnant_cck_swing_idx = 0;
|
||||
p_rf_calibrate_info->thermal_value = p_hal_data->eeprom_thermal_meter;
|
||||
|
||||
p_rf_calibrate_info->modify_tx_agc_value_cck = 0; /* modify by Mingzhi.Guo */
|
||||
p_rf_calibrate_info->modify_tx_agc_value_ofdm = 0; /* modify by Mingzhi.Guo */
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
#else
|
||||
struct _ADAPTER *adapter
|
||||
#endif
|
||||
)
|
||||
{
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
|
||||
|
||||
u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
|
||||
s8 diff_DPK[4] = {0};
|
||||
u8 thermal_value_avg_count = 0;
|
||||
u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
|
||||
|
||||
u8 OFDM_min_index = 0; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
|
||||
u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(p_hal_data->current_channel) */
|
||||
u8 power_tracking_type = p_hal_data->rf_power_tracking_type;
|
||||
u8 xtal_offset_eanble = 0;
|
||||
|
||||
struct _TXPWRTRACK_CFG c;
|
||||
|
||||
/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
|
||||
u8 *delta_swing_table_idx_tup_a = NULL;
|
||||
u8 *delta_swing_table_idx_tdown_a = NULL;
|
||||
u8 *delta_swing_table_idx_tup_b = NULL;
|
||||
u8 *delta_swing_table_idx_tdown_b = NULL;
|
||||
/*for 8814 add by Yu Chen*/
|
||||
u8 *delta_swing_table_idx_tup_c = NULL;
|
||||
u8 *delta_swing_table_idx_tdown_c = NULL;
|
||||
u8 *delta_swing_table_idx_tup_d = NULL;
|
||||
u8 *delta_swing_table_idx_tdown_d = NULL;
|
||||
/*for Xtal Offset by James.Tung*/
|
||||
s8 *delta_swing_table_xtal_up = NULL;
|
||||
s8 *delta_swing_table_xtal_down = NULL;
|
||||
|
||||
/* 4 2. Initilization ( 7 steps in total ) */
|
||||
|
||||
configure_txpower_track(p_dm_odm, &c);
|
||||
|
||||
(*c.get_delta_swing_table)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
|
||||
(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/
|
||||
(*c.get_delta_swing_table8814only)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
|
||||
(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D)) /*for Xtal Offset*/
|
||||
(*c.get_delta_swing_xtal_table)(p_dm_odm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down);
|
||||
|
||||
p_rf_calibrate_info->txpowertracking_callback_cnt++; /*cosa add for debug*/
|
||||
p_rf_calibrate_info->is_txpowertracking_init = true;
|
||||
|
||||
/*p_rf_calibrate_info->txpowertrack_control = p_hal_data->txpowertrack_control;
|
||||
<Kordan> We should keep updating the control variable according to HalData.
|
||||
<Kordan> rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
#if (MP_DRIVER == 1)
|
||||
p_rf_calibrate_info->rega24 = 0x090e1317;
|
||||
#endif
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
if (p_dm_odm->mp_mode == true)
|
||||
p_rf_calibrate_info->rega24 = 0x090e1317;
|
||||
#endif
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("===>odm_txpowertracking_callback_thermal_meter\n p_rf_calibrate_info->bb_swing_idx_cck_base: %d, p_rf_calibrate_info->bb_swing_idx_ofdm_base[A]: %d, p_rf_calibrate_info->default_ofdm_index: %d\n",
|
||||
p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->bb_swing_idx_ofdm_base[ODM_RF_PATH_A], p_rf_calibrate_info->default_ofdm_index));
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("p_rf_calibrate_info->txpowertrack_control=%d, p_hal_data->eeprom_thermal_meter %d\n", p_rf_calibrate_info->txpowertrack_control, p_hal_data->eeprom_thermal_meter));
|
||||
thermal_value = (u8)odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
|
||||
|
||||
/*add log by zhao he, check c80/c94/c14/ca0 value*/
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8723D) {
|
||||
regc80 = odm_get_bb_reg(p_dm_odm, 0xc80, MASKDWORD);
|
||||
regcd0 = odm_get_bb_reg(p_dm_odm, 0xcd0, MASKDWORD);
|
||||
regcd4 = odm_get_bb_reg(p_dm_odm, 0xcd4, MASKDWORD);
|
||||
regab4 = odm_get_bb_reg(p_dm_odm, 0xab4, 0x000007FF);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4));
|
||||
}
|
||||
|
||||
if (!p_rf_calibrate_info->txpowertrack_control)
|
||||
return;
|
||||
|
||||
|
||||
/*4 3. Initialize ThermalValues of rf_calibrate_info*/
|
||||
|
||||
if (p_rf_calibrate_info->is_reloadtxpowerindex)
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("reload ofdm index for band switch\n"));
|
||||
|
||||
/*4 4. Calculate average thermal meter*/
|
||||
|
||||
p_rf_calibrate_info->thermal_value_avg[p_rf_calibrate_info->thermal_value_avg_index] = thermal_value;
|
||||
p_rf_calibrate_info->thermal_value_avg_index++;
|
||||
if (p_rf_calibrate_info->thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/
|
||||
p_rf_calibrate_info->thermal_value_avg_index = 0;
|
||||
|
||||
for (i = 0; i < c.average_thermal_num; i++) {
|
||||
if (p_rf_calibrate_info->thermal_value_avg[i]) {
|
||||
thermal_value_avg += p_rf_calibrate_info->thermal_value_avg[i];
|
||||
thermal_value_avg_count++;
|
||||
}
|
||||
}
|
||||
|
||||
if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */
|
||||
thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
|
||||
p_rf_calibrate_info->thermal_value_delta = thermal_value - p_hal_data->eeprom_thermal_meter;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, p_hal_data->eeprom_thermal_meter));
|
||||
}
|
||||
|
||||
/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
|
||||
|
||||
/* "delta" here is used to determine whether thermal value changes or not. */
|
||||
delta = (thermal_value > p_rf_calibrate_info->thermal_value) ? (thermal_value - p_rf_calibrate_info->thermal_value) : (p_rf_calibrate_info->thermal_value - thermal_value);
|
||||
delta_LCK = (thermal_value > p_rf_calibrate_info->thermal_value_lck) ? (thermal_value - p_rf_calibrate_info->thermal_value_lck) : (p_rf_calibrate_info->thermal_value_lck - thermal_value);
|
||||
delta_IQK = (thermal_value > p_rf_calibrate_info->thermal_value_iqk) ? (thermal_value - p_rf_calibrate_info->thermal_value_iqk) : (p_rf_calibrate_info->thermal_value_iqk - thermal_value);
|
||||
|
||||
if (p_rf_calibrate_info->thermal_value_iqk == 0xff) { /*no PG, use thermal value for IQK*/
|
||||
p_rf_calibrate_info->thermal_value_iqk = thermal_value;
|
||||
delta_IQK = (thermal_value > p_rf_calibrate_info->thermal_value_iqk) ? (thermal_value - p_rf_calibrate_info->thermal_value_iqk) : (p_rf_calibrate_info->thermal_value_iqk - thermal_value);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, use thermal_value for IQK\n"));
|
||||
}
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
diff_DPK[p] = (s8)thermal_value - (s8)p_rf_calibrate_info->dpk_thermal[p];
|
||||
|
||||
/*4 6. If necessary, do LCK.*/
|
||||
|
||||
if (!(p_dm_odm->support_ic_type & ODM_RTL8821)) { /*no PG, do LCK at initial status*/
|
||||
if (p_rf_calibrate_info->thermal_value_lck == 0xff) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, do LCK\n"));
|
||||
p_rf_calibrate_info->thermal_value_lck = thermal_value;
|
||||
|
||||
/*Use RTLCK, so close power tracking driver LCK*/
|
||||
if (!(p_dm_odm->support_ic_type & ODM_RTL8814A)) {
|
||||
if (c.phy_lc_calibrate)
|
||||
(*c.phy_lc_calibrate)(p_dm_odm);
|
||||
}
|
||||
|
||||
delta_LCK = (thermal_value > p_rf_calibrate_info->thermal_value_lck) ? (thermal_value - p_rf_calibrate_info->thermal_value_lck) : (p_rf_calibrate_info->thermal_value_lck - thermal_value);
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK));
|
||||
|
||||
/* Delta temperature is equal to or larger than 20 centigrade.*/
|
||||
if (delta_LCK >= c.threshold_iqk) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk));
|
||||
p_rf_calibrate_info->thermal_value_lck = thermal_value;
|
||||
|
||||
/*Use RTLCK, so close power tracking driver LCK*/
|
||||
if (!(p_dm_odm->support_ic_type & ODM_RTL8814A)) {
|
||||
if (c.phy_lc_calibrate)
|
||||
(*c.phy_lc_calibrate)(p_dm_odm);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
|
||||
|
||||
if (delta > 0 && p_rf_calibrate_info->txpowertrack_control) {
|
||||
/* "delta" here is used to record the absolute value of differrence. */
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
delta = thermal_value > p_hal_data->eeprom_thermal_meter ? (thermal_value - p_hal_data->eeprom_thermal_meter) : (p_hal_data->eeprom_thermal_meter - thermal_value);
|
||||
#else
|
||||
delta = (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - p_dm_odm->priv->pmib->dot11RFEntry.ther) : (p_dm_odm->priv->pmib->dot11RFEntry.ther - thermal_value);
|
||||
#endif
|
||||
if (delta >= TXPWR_TRACK_TABLE_SIZE)
|
||||
delta = TXPWR_TRACK_TABLE_SIZE - 1;
|
||||
|
||||
/*4 7.1 The Final Power index = BaseIndex + power_index_offset*/
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
if (thermal_value > p_hal_data->eeprom_thermal_meter) {
|
||||
#else
|
||||
if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) {
|
||||
#endif
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
p_rf_calibrate_info->delta_power_index_last[p] = p_rf_calibrate_info->delta_power_index[p]; /*recording poer index offset*/
|
||||
switch (p) {
|
||||
case ODM_RF_PATH_B:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]));
|
||||
|
||||
p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
|
||||
case ODM_RF_PATH_C:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]));
|
||||
|
||||
p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
|
||||
case ODM_RF_PATH_D:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]));
|
||||
|
||||
p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
|
||||
default:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]));
|
||||
|
||||
p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D)) {
|
||||
/*Save xtal_offset from Xtal table*/
|
||||
p_rf_calibrate_info->xtal_offset_last = p_rf_calibrate_info->xtal_offset; /*recording last Xtal offset*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]));
|
||||
p_rf_calibrate_info->xtal_offset = delta_swing_table_xtal_up[delta];
|
||||
|
||||
if (p_rf_calibrate_info->xtal_offset_last == p_rf_calibrate_info->xtal_offset)
|
||||
xtal_offset_eanble = 0;
|
||||
else
|
||||
xtal_offset_eanble = 1;
|
||||
}
|
||||
|
||||
} else {
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
p_rf_calibrate_info->delta_power_index_last[p] = p_rf_calibrate_info->delta_power_index[p]; /*recording poer index offset*/
|
||||
|
||||
switch (p) {
|
||||
case ODM_RF_PATH_B:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]));
|
||||
p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
|
||||
case ODM_RF_PATH_C:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]));
|
||||
p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
|
||||
case ODM_RF_PATH_D:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]));
|
||||
p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
|
||||
default:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]));
|
||||
p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D)) {
|
||||
/*Save xtal_offset from Xtal table*/
|
||||
p_rf_calibrate_info->xtal_offset_last = p_rf_calibrate_info->xtal_offset; /*recording last Xtal offset*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]));
|
||||
p_rf_calibrate_info->xtal_offset = delta_swing_table_xtal_down[delta];
|
||||
|
||||
if (p_rf_calibrate_info->xtal_offset_last == p_rf_calibrate_info->xtal_offset)
|
||||
xtal_offset_eanble = 0;
|
||||
else
|
||||
xtal_offset_eanble = 1;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p));
|
||||
|
||||
if (p_rf_calibrate_info->delta_power_index[p] == p_rf_calibrate_info->delta_power_index_last[p]) /*If Thermal value changes but lookup table value still the same*/
|
||||
p_rf_calibrate_info->power_index_offset[p] = 0;
|
||||
else
|
||||
p_rf_calibrate_info->power_index_offset[p] = p_rf_calibrate_info->delta_power_index[p] - p_rf_calibrate_info->delta_power_index_last[p]; /*Power index diff between 2 times Power Tracking*/
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, p_rf_calibrate_info->power_index_offset[p], p_rf_calibrate_info->delta_power_index[p], p_rf_calibrate_info->delta_power_index_last[p]));
|
||||
|
||||
p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] + p_rf_calibrate_info->power_index_offset[p];
|
||||
p_rf_calibrate_info->CCK_index = p_rf_calibrate_info->bb_swing_idx_cck_base + p_rf_calibrate_info->power_index_offset[p];
|
||||
|
||||
p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->CCK_index;
|
||||
p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->OFDM_index[p];
|
||||
|
||||
/*************Print BB Swing base and index Offset*************/
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_cck, p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->power_index_offset[p]));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_ofdm[p], p, p_rf_calibrate_info->bb_swing_idx_ofdm_base[p], p_rf_calibrate_info->power_index_offset[p]));
|
||||
|
||||
/*4 7.1 Handle boundary conditions of index.*/
|
||||
|
||||
if (p_rf_calibrate_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)
|
||||
p_rf_calibrate_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;
|
||||
else if (p_rf_calibrate_info->OFDM_index[p] <= OFDM_min_index)
|
||||
p_rf_calibrate_info->OFDM_index[p] = OFDM_min_index;
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("\n\n========================================================================================================\n"));
|
||||
|
||||
if (p_rf_calibrate_info->CCK_index > c.swing_table_size_cck - 1)
|
||||
p_rf_calibrate_info->CCK_index = c.swing_table_size_cck - 1;
|
||||
else if (p_rf_calibrate_info->CCK_index <= 0)
|
||||
p_rf_calibrate_info->CCK_index = 0;
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, p_rf_calibrate_info->thermal_value: %d\n",
|
||||
p_rf_calibrate_info->txpowertrack_control, thermal_value, p_rf_calibrate_info->thermal_value));
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
p_rf_calibrate_info->power_index_offset[p] = 0;
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
|
||||
p_rf_calibrate_info->CCK_index, p_rf_calibrate_info->bb_swing_idx_cck_base)); /*Print Swing base & current*/
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
|
||||
p_rf_calibrate_info->OFDM_index[p], p, p_rf_calibrate_info->bb_swing_idx_ofdm_base[p]));
|
||||
}
|
||||
|
||||
if ((p_dm_odm->support_ic_type & ODM_RTL8814A)) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("power_tracking_type=%d\n", power_tracking_type));
|
||||
|
||||
if (power_tracking_type == 0) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0);
|
||||
} else if (power_tracking_type == 1) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_2G_TSSI_5G_MODE, p, 0);
|
||||
} else if (power_tracking_type == 2) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_5G_TSSI_2G_MODE, p, 0);
|
||||
} else if (power_tracking_type == 3) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking TSSI MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, TSSI_MODE, p, 0);
|
||||
}
|
||||
p_rf_calibrate_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/
|
||||
|
||||
} else if ((p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_A] != 0 ||
|
||||
p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_B] != 0 ||
|
||||
p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_C] != 0 ||
|
||||
p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_D] != 0) &&
|
||||
p_rf_calibrate_info->txpowertrack_control && (p_hal_data->eeprom_thermal_meter != 0xff)) {
|
||||
/* 4 7.2 Configure the Swing Table to adjust Tx Power. */
|
||||
|
||||
p_rf_calibrate_info->is_tx_power_changed = true; /*Always true after Tx Power is adjusted by power tracking.*/
|
||||
/* */
|
||||
/* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */
|
||||
/* to increase TX power. Otherwise, EVM will be bad. */
|
||||
/* */
|
||||
/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
|
||||
if (thermal_value > p_rf_calibrate_info->thermal_value) {
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
|
||||
p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_rf_calibrate_info->thermal_value));
|
||||
}
|
||||
} else if (thermal_value < p_rf_calibrate_info->thermal_value) { /*Low temperature*/
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
|
||||
p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_rf_calibrate_info->thermal_value));
|
||||
}
|
||||
}
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
if (thermal_value > p_hal_data->eeprom_thermal_meter)
|
||||
#else
|
||||
if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther)
|
||||
#endif
|
||||
{
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature(%d) higher than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter));
|
||||
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8821 ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8814A ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8822B ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8821C) {
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0);
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, indexforchannel);
|
||||
}
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature(%d) lower than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter));
|
||||
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8821 ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8814A ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8822B ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8821C) {
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, indexforchannel);
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, indexforchannel);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->bb_swing_idx_cck; /*Record last time Power Tracking result as base.*/
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->bb_swing_idx_ofdm[p];
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("p_rf_calibrate_info->thermal_value = %d thermal_value= %d\n", p_rf_calibrate_info->thermal_value, thermal_value));
|
||||
|
||||
p_rf_calibrate_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/
|
||||
|
||||
}
|
||||
|
||||
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8723D) {
|
||||
|
||||
if (xtal_offset_eanble != 0 && p_rf_calibrate_info->txpowertrack_control && (p_hal_data->eeprom_thermal_meter != 0xff)) {
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter Xtal Tracking**********\n"));
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
if (thermal_value > p_hal_data->eeprom_thermal_meter) {
|
||||
#else
|
||||
if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) {
|
||||
#endif
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature(%d) higher than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter));
|
||||
(*c.odm_txxtaltrack_set_xtal)(p_dm_odm);
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature(%d) lower than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter));
|
||||
(*c.odm_txxtaltrack_set_xtal)(p_dm_odm);
|
||||
}
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********End Xtal Tracking**********\n"));
|
||||
}
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
|
||||
if (!IS_HARDWARE_TYPE_8723B(adapter)) {
|
||||
/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
|
||||
if (delta_IQK >= c.threshold_iqk) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk));
|
||||
if (!p_rf_calibrate_info->is_iqk_in_progress)
|
||||
(*c.do_iqk)(p_dm_odm, delta_IQK, thermal_value, 8);
|
||||
}
|
||||
}
|
||||
if (p_rf_calibrate_info->dpk_thermal[ODM_RF_PATH_A] != 0) {
|
||||
if (diff_DPK[ODM_RF_PATH_A] >= c.threshold_dpk) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk));
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
|
||||
} else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.threshold_dpk)) {
|
||||
s32 value = 0x20 + (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk);
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
|
||||
} else {
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
|
||||
}
|
||||
}
|
||||
if (p_rf_calibrate_info->dpk_thermal[ODM_RF_PATH_B] != 0) {
|
||||
if (diff_DPK[ODM_RF_PATH_B] >= c.threshold_dpk) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk));
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
|
||||
} else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.threshold_dpk)) {
|
||||
s32 value = 0x20 + (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk);
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
|
||||
} else {
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===odm_txpowertracking_callback_thermal_meter\n"));
|
||||
|
||||
p_rf_calibrate_info->tx_powercount = 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* 3============================================================
|
||||
* 3 IQ Calibration
|
||||
* 3============================================================ */
|
||||
|
||||
void
|
||||
odm_reset_iqk_result(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
|
||||
{
|
||||
u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
|
||||
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165
|
||||
};
|
||||
u8 place = chnl;
|
||||
|
||||
|
||||
if (chnl > 14) {
|
||||
for (place = 14; place < sizeof(channel_all); place++) {
|
||||
if (channel_all[place] == chnl)
|
||||
return place - 13;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
void
|
||||
odm_iq_calibrate(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
)
|
||||
{
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
if (*p_dm_odm->p_is_fcs_mode_enable)
|
||||
return;
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
|
||||
if (IS_HARDWARE_TYPE_8812AU(adapter))
|
||||
return;
|
||||
#endif
|
||||
|
||||
if (p_dm_odm->is_linked) {
|
||||
if ((*p_dm_odm->p_channel != p_dm_odm->pre_channel) && (!*p_dm_odm->p_is_scan_in_process)) {
|
||||
p_dm_odm->pre_channel = *p_dm_odm->p_channel;
|
||||
p_dm_odm->linked_interval = 0;
|
||||
}
|
||||
|
||||
if (p_dm_odm->linked_interval < 3)
|
||||
p_dm_odm->linked_interval++;
|
||||
|
||||
if (p_dm_odm->linked_interval == 2) {
|
||||
if (IS_HARDWARE_TYPE_8814A(adapter)) {
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
phy_iq_calibrate_8814a(p_dm_odm, false);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
else if (IS_HARDWARE_TYPE_8822B(adapter))
|
||||
phy_iq_calibrate_8822b(p_dm_odm, false);
|
||||
#endif
|
||||
|
||||
#if (RTL8821C_SUPPORT == 1)
|
||||
else if (IS_HARDWARE_TYPE_8821C(adapter))
|
||||
phy_iq_calibrate_8821c(p_dm_odm, false);
|
||||
#endif
|
||||
|
||||
#if (RTL8821A_SUPPORT == 1)
|
||||
else if (IS_HARDWARE_TYPE_8821(adapter))
|
||||
phy_iq_calibrate_8821a(p_dm_odm, false);
|
||||
#endif
|
||||
}
|
||||
} else
|
||||
p_dm_odm->linked_interval = 0;
|
||||
}
|
||||
|
||||
void phydm_rf_init(void *p_dm_void)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
odm_txpowertracking_init(p_dm_odm);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
odm_clear_txpowertracking_state(p_dm_odm);
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
phy_iq_calibrate_8814a_init(p_dm_odm);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
void phydm_rf_watchdog(void *p_dm_void)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
odm_txpowertracking_check(p_dm_odm);
|
||||
if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)
|
||||
odm_iq_calibrate(p_dm_odm);
|
||||
#endif
|
||||
}
|
||||
117
hal/phydm/halphyrf_ce.h
Normal file
117
hal/phydm/halphyrf_ce.h
Normal file
|
|
@ -0,0 +1,117 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HAL_PHY_RF_H__
|
||||
#define __HAL_PHY_RF_H__
|
||||
|
||||
#include "phydm_kfree.h"
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
#include "rtl8814a/phydm_iqk_8814a.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
#include "rtl8822b/phydm_iqk_8822b.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8821C_SUPPORT == 1)
|
||||
#include "rtl8821c/phydm_iqk_8821c.h"
|
||||
#endif
|
||||
|
||||
#include "phydm_powertracking_ce.h"
|
||||
|
||||
|
||||
enum spur_cal_method {
|
||||
PLL_RESET,
|
||||
AFE_PHASE_SEL
|
||||
};
|
||||
|
||||
enum pwrtrack_method {
|
||||
BBSWING,
|
||||
TXAGC,
|
||||
MIX_MODE,
|
||||
TSSI_MODE,
|
||||
MIX_2G_TSSI_5G_MODE,
|
||||
MIX_5G_TSSI_2G_MODE
|
||||
};
|
||||
|
||||
typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
|
||||
typedef void(*func_iqk)(void *, u8, u8, u8);
|
||||
typedef void (*func_lck)(void *);
|
||||
typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
|
||||
typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
|
||||
typedef void(*func_swing_xtal)(void *, s8 **, s8 **);
|
||||
typedef void(*func_set_xtal)(void *);
|
||||
|
||||
struct _TXPWRTRACK_CFG {
|
||||
u8 swing_table_size_cck;
|
||||
u8 swing_table_size_ofdm;
|
||||
u8 threshold_iqk;
|
||||
u8 threshold_dpk;
|
||||
u8 average_thermal_num;
|
||||
u8 rf_path_count;
|
||||
u32 thermal_reg_addr;
|
||||
func_set_pwr odm_tx_pwr_track_set_pwr;
|
||||
func_iqk do_iqk;
|
||||
func_lck phy_lc_calibrate;
|
||||
func_swing get_delta_swing_table;
|
||||
func_swing8814only get_delta_swing_table8814only;
|
||||
func_swing_xtal get_delta_swing_xtal_table;
|
||||
func_set_xtal odm_txxtaltrack_set_xtal;
|
||||
};
|
||||
|
||||
void
|
||||
configure_txpower_track(
|
||||
void *p_dm_void,
|
||||
struct _TXPWRTRACK_CFG *p_config
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
odm_clear_txpowertracking_state(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
void *p_dm_void
|
||||
#else
|
||||
struct _ADAPTER *adapter
|
||||
#endif
|
||||
);
|
||||
|
||||
|
||||
|
||||
#define ODM_TARGET_CHNL_NUM_2G_5G 59
|
||||
|
||||
|
||||
void
|
||||
odm_reset_iqk_result(
|
||||
void *p_dm_void
|
||||
);
|
||||
u8
|
||||
odm_get_right_chnl_place_for_iqk(
|
||||
u8 chnl
|
||||
);
|
||||
|
||||
void phydm_rf_init(void *p_dm_void);
|
||||
void phydm_rf_watchdog(void *p_dm_void);
|
||||
|
||||
#endif /* #ifndef __HAL_PHY_RF_H__ */
|
||||
784
hal/phydm/halphyrf_win.c
Normal file
784
hal/phydm/halphyrf_win.c
Normal file
|
|
@ -0,0 +1,784 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \
|
||||
do {\
|
||||
for (_offset = 0; _offset < _size; _offset++) { \
|
||||
\
|
||||
if (_delta_thermal < thermal_threshold[_direction][_offset]) { \
|
||||
\
|
||||
if (_offset != 0)\
|
||||
_offset--;\
|
||||
break;\
|
||||
} \
|
||||
} \
|
||||
if (_offset >= _size)\
|
||||
_offset = _size-1;\
|
||||
} while (0)
|
||||
|
||||
void configure_txpower_track(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
struct _TXPWRTRACK_CFG *p_config
|
||||
)
|
||||
{
|
||||
#if RTL8192E_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8192E)
|
||||
configure_txpower_track_8192e(p_config);
|
||||
#endif
|
||||
#if RTL8821A_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8821)
|
||||
configure_txpower_track_8821a(p_config);
|
||||
#endif
|
||||
#if RTL8812A_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8812)
|
||||
configure_txpower_track_8812a(p_config);
|
||||
#endif
|
||||
#if RTL8188E_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8188E)
|
||||
configure_txpower_track_8188e(p_config);
|
||||
#endif
|
||||
|
||||
#if RTL8188F_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8188F)
|
||||
configure_txpower_track_8188f(p_config);
|
||||
#endif
|
||||
|
||||
#if RTL8723B_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8723B)
|
||||
configure_txpower_track_8723b(p_config);
|
||||
#endif
|
||||
|
||||
#if RTL8814A_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8814A)
|
||||
configure_txpower_track_8814a(p_config);
|
||||
#endif
|
||||
|
||||
#if RTL8703B_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8703B)
|
||||
configure_txpower_track_8703b(p_config);
|
||||
#endif
|
||||
|
||||
#if RTL8822B_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8822B)
|
||||
configure_txpower_track_8822b(p_config);
|
||||
#endif
|
||||
|
||||
#if RTL8723D_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8723D)
|
||||
configure_txpower_track_8723d(p_config);
|
||||
#endif
|
||||
|
||||
#if RTL8821C_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8821C)
|
||||
configure_txpower_track_8821c(p_config);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/* **********************************************************************
|
||||
* <20121113, Kordan> This function should be called when tx_agc changed.
|
||||
* Otherwise the previous compensation is gone, because we record the
|
||||
* delta of temperature between two TxPowerTracking watch dogs.
|
||||
*
|
||||
* NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
|
||||
* need to call this function.
|
||||
* ********************************************************************** */
|
||||
void
|
||||
odm_clear_txpowertracking_state(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
)
|
||||
{
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(p_dm_odm->adapter);
|
||||
u8 p = 0;
|
||||
struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
|
||||
|
||||
p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index;
|
||||
p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->default_cck_index;
|
||||
p_rf_calibrate_info->CCK_index = 0;
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) {
|
||||
p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->default_ofdm_index;
|
||||
p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->default_ofdm_index;
|
||||
p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index;
|
||||
|
||||
p_rf_calibrate_info->power_index_offset[p] = 0;
|
||||
p_rf_calibrate_info->delta_power_index[p] = 0;
|
||||
p_rf_calibrate_info->delta_power_index_last[p] = 0;
|
||||
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = 0; /* Initial Mix mode power tracking*/
|
||||
p_rf_calibrate_info->remnant_ofdm_swing_idx[p] = 0;
|
||||
p_rf_calibrate_info->kfree_offset[p] = 0;
|
||||
}
|
||||
|
||||
p_rf_calibrate_info->modify_tx_agc_flag_path_a = false; /*Initial at Modify Tx Scaling mode*/
|
||||
p_rf_calibrate_info->modify_tx_agc_flag_path_b = false; /*Initial at Modify Tx Scaling mode*/
|
||||
p_rf_calibrate_info->modify_tx_agc_flag_path_c = false; /*Initial at Modify Tx Scaling mode*/
|
||||
p_rf_calibrate_info->modify_tx_agc_flag_path_d = false; /*Initial at Modify Tx Scaling mode*/
|
||||
p_rf_calibrate_info->remnant_cck_swing_idx = 0;
|
||||
p_rf_calibrate_info->thermal_value = p_hal_data->eeprom_thermal_meter;
|
||||
|
||||
p_rf_calibrate_info->modify_tx_agc_value_cck = 0; /* modify by Mingzhi.Guo */
|
||||
p_rf_calibrate_info->modify_tx_agc_value_ofdm = 0; /* modify by Mingzhi.Guo */
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
#else
|
||||
struct _ADAPTER *adapter
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
|
||||
|
||||
u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
|
||||
s8 diff_DPK[4] = {0};
|
||||
u8 thermal_value_avg_count = 0;
|
||||
u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
|
||||
|
||||
u8 OFDM_min_index = 0; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
|
||||
u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(p_hal_data->current_channel) */
|
||||
u8 power_tracking_type = p_hal_data->RfPowerTrackingType;
|
||||
u8 xtal_offset_eanble = 0;
|
||||
|
||||
struct _TXPWRTRACK_CFG c;
|
||||
|
||||
/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
|
||||
u8 *delta_swing_table_idx_tup_a = NULL;
|
||||
u8 *delta_swing_table_idx_tdown_a = NULL;
|
||||
u8 *delta_swing_table_idx_tup_b = NULL;
|
||||
u8 *delta_swing_table_idx_tdown_b = NULL;
|
||||
/*for 8814 add by Yu Chen*/
|
||||
u8 *delta_swing_table_idx_tup_c = NULL;
|
||||
u8 *delta_swing_table_idx_tdown_c = NULL;
|
||||
u8 *delta_swing_table_idx_tup_d = NULL;
|
||||
u8 *delta_swing_table_idx_tdown_d = NULL;
|
||||
/*for Xtal Offset by James.Tung*/
|
||||
s8 *delta_swing_table_xtal_up = NULL;
|
||||
s8 *delta_swing_table_xtal_down = NULL;
|
||||
|
||||
/* 4 2. Initilization ( 7 steps in total ) */
|
||||
|
||||
configure_txpower_track(p_dm_odm, &c);
|
||||
|
||||
(*c.get_delta_swing_table)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
|
||||
(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/
|
||||
(*c.get_delta_swing_table8814only)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
|
||||
(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D)) /*for Xtal Offset*/
|
||||
(*c.get_delta_swing_xtal_table)(p_dm_odm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down);
|
||||
|
||||
|
||||
p_rf_calibrate_info->txpowertracking_callback_cnt++; /*cosa add for debug*/
|
||||
p_rf_calibrate_info->is_txpowertracking_init = true;
|
||||
|
||||
/*p_rf_calibrate_info->txpowertrack_control = p_hal_data->txpowertrack_control;
|
||||
<Kordan> We should keep updating the control variable according to HalData.
|
||||
<Kordan> rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
#if (MP_DRIVER == 1)
|
||||
p_rf_calibrate_info->rega24 = 0x090e1317;
|
||||
#endif
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
if (p_dm_odm->mp_mode == true)
|
||||
p_rf_calibrate_info->rega24 = 0x090e1317;
|
||||
#endif
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("===>odm_txpowertracking_callback_thermal_meter\n p_rf_calibrate_info->bb_swing_idx_cck_base: %d, p_rf_calibrate_info->bb_swing_idx_ofdm_base[A]: %d, p_rf_calibrate_info->default_ofdm_index: %d\n",
|
||||
p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->bb_swing_idx_ofdm_base[ODM_RF_PATH_A], p_rf_calibrate_info->default_ofdm_index));
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("p_rf_calibrate_info->txpowertrack_control=%d, p_hal_data->eeprom_thermal_meter %d\n", p_rf_calibrate_info->txpowertrack_control, p_hal_data->eeprom_thermal_meter));
|
||||
thermal_value = (u8)odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
|
||||
|
||||
/*add log by zhao he, check c80/c94/c14/ca0 value*/
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8723D) {
|
||||
regc80 = odm_get_bb_reg(p_dm_odm, 0xc80, MASKDWORD);
|
||||
regcd0 = odm_get_bb_reg(p_dm_odm, 0xcd0, MASKDWORD);
|
||||
regcd4 = odm_get_bb_reg(p_dm_odm, 0xcd4, MASKDWORD);
|
||||
regab4 = odm_get_bb_reg(p_dm_odm, 0xab4, 0x000007FF);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4));
|
||||
}
|
||||
|
||||
if (!p_rf_calibrate_info->txpowertrack_control)
|
||||
return;
|
||||
|
||||
|
||||
/*4 3. Initialize ThermalValues of rf_calibrate_info*/
|
||||
|
||||
if (p_rf_calibrate_info->is_reloadtxpowerindex)
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("reload ofdm index for band switch\n"));
|
||||
|
||||
/*4 4. Calculate average thermal meter*/
|
||||
|
||||
p_rf_calibrate_info->thermal_value_avg[p_rf_calibrate_info->thermal_value_avg_index] = thermal_value;
|
||||
p_rf_calibrate_info->thermal_value_avg_index++;
|
||||
if (p_rf_calibrate_info->thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/
|
||||
p_rf_calibrate_info->thermal_value_avg_index = 0;
|
||||
|
||||
for (i = 0; i < c.average_thermal_num; i++) {
|
||||
if (p_rf_calibrate_info->thermal_value_avg[i]) {
|
||||
thermal_value_avg += p_rf_calibrate_info->thermal_value_avg[i];
|
||||
thermal_value_avg_count++;
|
||||
}
|
||||
}
|
||||
|
||||
if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */
|
||||
thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
|
||||
p_rf_calibrate_info->thermal_value_delta = thermal_value - p_hal_data->eeprom_thermal_meter;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, p_hal_data->eeprom_thermal_meter));
|
||||
}
|
||||
|
||||
/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
|
||||
|
||||
/* "delta" here is used to determine whether thermal value changes or not. */
|
||||
delta = (thermal_value > p_rf_calibrate_info->thermal_value) ? (thermal_value - p_rf_calibrate_info->thermal_value) : (p_rf_calibrate_info->thermal_value - thermal_value);
|
||||
delta_LCK = (thermal_value > p_rf_calibrate_info->thermal_value_lck) ? (thermal_value - p_rf_calibrate_info->thermal_value_lck) : (p_rf_calibrate_info->thermal_value_lck - thermal_value);
|
||||
delta_IQK = (thermal_value > p_rf_calibrate_info->thermal_value_iqk) ? (thermal_value - p_rf_calibrate_info->thermal_value_iqk) : (p_rf_calibrate_info->thermal_value_iqk - thermal_value);
|
||||
|
||||
if (p_rf_calibrate_info->thermal_value_iqk == 0xff) { /*no PG, use thermal value for IQK*/
|
||||
p_rf_calibrate_info->thermal_value_iqk = thermal_value;
|
||||
delta_IQK = (thermal_value > p_rf_calibrate_info->thermal_value_iqk) ? (thermal_value - p_rf_calibrate_info->thermal_value_iqk) : (p_rf_calibrate_info->thermal_value_iqk - thermal_value);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, use thermal_value for IQK\n"));
|
||||
}
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
diff_DPK[p] = (s8)thermal_value - (s8)p_rf_calibrate_info->dpk_thermal[p];
|
||||
|
||||
/*4 6. If necessary, do LCK.*/
|
||||
|
||||
if (!(p_dm_odm->support_ic_type & ODM_RTL8821)) { /*no PG, do LCK at initial status*/
|
||||
if (p_rf_calibrate_info->thermal_value_lck == 0xff) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, do LCK\n"));
|
||||
p_rf_calibrate_info->thermal_value_lck = thermal_value;
|
||||
|
||||
/*Use RTLCK, so close power tracking driver LCK*/
|
||||
if (!(p_dm_odm->support_ic_type & ODM_RTL8814A)) {
|
||||
if (c.phy_lc_calibrate)
|
||||
(*c.phy_lc_calibrate)(p_dm_odm);
|
||||
}
|
||||
|
||||
delta_LCK = (thermal_value > p_rf_calibrate_info->thermal_value_lck) ? (thermal_value - p_rf_calibrate_info->thermal_value_lck) : (p_rf_calibrate_info->thermal_value_lck - thermal_value);
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK));
|
||||
|
||||
/* Delta temperature is equal to or larger than 20 centigrade.*/
|
||||
if (delta_LCK >= c.threshold_iqk) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk));
|
||||
p_rf_calibrate_info->thermal_value_lck = thermal_value;
|
||||
|
||||
/*Use RTLCK, so close power tracking driver LCK*/
|
||||
if (!(p_dm_odm->support_ic_type & ODM_RTL8814A)) {
|
||||
if (c.phy_lc_calibrate)
|
||||
(*c.phy_lc_calibrate)(p_dm_odm);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
|
||||
|
||||
if (delta > 0 && p_rf_calibrate_info->txpowertrack_control) {
|
||||
/* "delta" here is used to record the absolute value of differrence. */
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
delta = thermal_value > p_hal_data->eeprom_thermal_meter ? (thermal_value - p_hal_data->eeprom_thermal_meter) : (p_hal_data->eeprom_thermal_meter - thermal_value);
|
||||
#else
|
||||
delta = (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - p_dm_odm->priv->pmib->dot11RFEntry.ther) : (p_dm_odm->priv->pmib->dot11RFEntry.ther - thermal_value);
|
||||
#endif
|
||||
if (delta >= TXPWR_TRACK_TABLE_SIZE)
|
||||
delta = TXPWR_TRACK_TABLE_SIZE - 1;
|
||||
|
||||
/*4 7.1 The Final Power index = BaseIndex + power_index_offset*/
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
if (thermal_value > p_hal_data->eeprom_thermal_meter) {
|
||||
#else
|
||||
if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) {
|
||||
#endif
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
p_rf_calibrate_info->delta_power_index_last[p] = p_rf_calibrate_info->delta_power_index[p]; /*recording poer index offset*/
|
||||
switch (p) {
|
||||
case ODM_RF_PATH_B:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]));
|
||||
|
||||
p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
|
||||
case ODM_RF_PATH_C:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]));
|
||||
|
||||
p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
|
||||
case ODM_RF_PATH_D:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]));
|
||||
|
||||
p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
|
||||
default:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]));
|
||||
|
||||
p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D)) {
|
||||
/*Save xtal_offset from Xtal table*/
|
||||
p_rf_calibrate_info->xtal_offset_last = p_rf_calibrate_info->xtal_offset; /*recording last Xtal offset*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]));
|
||||
p_rf_calibrate_info->xtal_offset = delta_swing_table_xtal_up[delta];
|
||||
|
||||
if (p_rf_calibrate_info->xtal_offset_last == p_rf_calibrate_info->xtal_offset)
|
||||
xtal_offset_eanble = 0;
|
||||
else
|
||||
xtal_offset_eanble = 1;
|
||||
}
|
||||
|
||||
} else {
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
p_rf_calibrate_info->delta_power_index_last[p] = p_rf_calibrate_info->delta_power_index[p]; /*recording poer index offset*/
|
||||
|
||||
switch (p) {
|
||||
case ODM_RF_PATH_B:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]));
|
||||
p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
|
||||
case ODM_RF_PATH_C:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]));
|
||||
p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
|
||||
case ODM_RF_PATH_D:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]));
|
||||
p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
|
||||
default:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]));
|
||||
p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D)) {
|
||||
/*Save xtal_offset from Xtal table*/
|
||||
p_rf_calibrate_info->xtal_offset_last = p_rf_calibrate_info->xtal_offset; /*recording last Xtal offset*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]));
|
||||
p_rf_calibrate_info->xtal_offset = delta_swing_table_xtal_down[delta];
|
||||
|
||||
if (p_rf_calibrate_info->xtal_offset_last == p_rf_calibrate_info->xtal_offset)
|
||||
xtal_offset_eanble = 0;
|
||||
else
|
||||
xtal_offset_eanble = 1;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p));
|
||||
|
||||
if (p_rf_calibrate_info->delta_power_index[p] == p_rf_calibrate_info->delta_power_index_last[p]) /*If Thermal value changes but lookup table value still the same*/
|
||||
p_rf_calibrate_info->power_index_offset[p] = 0;
|
||||
else
|
||||
p_rf_calibrate_info->power_index_offset[p] = p_rf_calibrate_info->delta_power_index[p] - p_rf_calibrate_info->delta_power_index_last[p]; /*Power index diff between 2 times Power Tracking*/
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, p_rf_calibrate_info->power_index_offset[p], p_rf_calibrate_info->delta_power_index[p], p_rf_calibrate_info->delta_power_index_last[p]));
|
||||
|
||||
p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] + p_rf_calibrate_info->power_index_offset[p];
|
||||
p_rf_calibrate_info->CCK_index = p_rf_calibrate_info->bb_swing_idx_cck_base + p_rf_calibrate_info->power_index_offset[p];
|
||||
|
||||
p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->CCK_index;
|
||||
p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->OFDM_index[p];
|
||||
|
||||
/*************Print BB Swing base and index Offset*************/
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_cck, p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->power_index_offset[p]));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_ofdm[p], p, p_rf_calibrate_info->bb_swing_idx_ofdm_base[p], p_rf_calibrate_info->power_index_offset[p]));
|
||||
|
||||
/*4 7.1 Handle boundary conditions of index.*/
|
||||
|
||||
if (p_rf_calibrate_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)
|
||||
p_rf_calibrate_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;
|
||||
else if (p_rf_calibrate_info->OFDM_index[p] <= OFDM_min_index)
|
||||
p_rf_calibrate_info->OFDM_index[p] = OFDM_min_index;
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("\n\n========================================================================================================\n"));
|
||||
|
||||
if (p_rf_calibrate_info->CCK_index > c.swing_table_size_cck - 1)
|
||||
p_rf_calibrate_info->CCK_index = c.swing_table_size_cck - 1;
|
||||
else if (p_rf_calibrate_info->CCK_index <= 0)
|
||||
p_rf_calibrate_info->CCK_index = 0;
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, p_rf_calibrate_info->thermal_value: %d\n",
|
||||
p_rf_calibrate_info->txpowertrack_control, thermal_value, p_rf_calibrate_info->thermal_value));
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
p_rf_calibrate_info->power_index_offset[p] = 0;
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
|
||||
p_rf_calibrate_info->CCK_index, p_rf_calibrate_info->bb_swing_idx_cck_base)); /*Print Swing base & current*/
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
|
||||
p_rf_calibrate_info->OFDM_index[p], p, p_rf_calibrate_info->bb_swing_idx_ofdm_base[p]));
|
||||
}
|
||||
|
||||
if ((p_dm_odm->support_ic_type & ODM_RTL8814A)) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("power_tracking_type=%d\n", power_tracking_type));
|
||||
|
||||
if (power_tracking_type == 0) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0);
|
||||
} else if (power_tracking_type == 1) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_2G_TSSI_5G_MODE, p, 0);
|
||||
} else if (power_tracking_type == 2) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_5G_TSSI_2G_MODE, p, 0);
|
||||
} else if (power_tracking_type == 3) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking TSSI MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, TSSI_MODE, p, 0);
|
||||
}
|
||||
p_rf_calibrate_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/
|
||||
|
||||
} else if ((p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_A] != 0 ||
|
||||
p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_B] != 0 ||
|
||||
p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_C] != 0 ||
|
||||
p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_D] != 0) &&
|
||||
p_rf_calibrate_info->txpowertrack_control && (p_hal_data->eeprom_thermal_meter != 0xff)) {
|
||||
/* 4 7.2 Configure the Swing Table to adjust Tx Power. */
|
||||
|
||||
p_rf_calibrate_info->is_tx_power_changed = true; /*Always true after Tx Power is adjusted by power tracking.*/
|
||||
/* */
|
||||
/* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */
|
||||
/* to increase TX power. Otherwise, EVM will be bad. */
|
||||
/* */
|
||||
/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
|
||||
if (thermal_value > p_rf_calibrate_info->thermal_value) {
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
|
||||
p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_rf_calibrate_info->thermal_value));
|
||||
}
|
||||
} else if (thermal_value < p_rf_calibrate_info->thermal_value) { /*Low temperature*/
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
|
||||
p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_rf_calibrate_info->thermal_value));
|
||||
}
|
||||
}
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
if (thermal_value > p_hal_data->eeprom_thermal_meter)
|
||||
#else
|
||||
if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther)
|
||||
#endif
|
||||
{
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature(%d) higher than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter));
|
||||
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8821 ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8814A ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8822B ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8821C) {
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0);
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, indexforchannel);
|
||||
}
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature(%d) lower than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter));
|
||||
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8821 ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8814A ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8822B ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8821C) {
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, indexforchannel);
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, indexforchannel);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->bb_swing_idx_cck; /*Record last time Power Tracking result as base.*/
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->bb_swing_idx_ofdm[p];
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("p_rf_calibrate_info->thermal_value = %d thermal_value= %d\n", p_rf_calibrate_info->thermal_value, thermal_value));
|
||||
|
||||
p_rf_calibrate_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/
|
||||
|
||||
}
|
||||
|
||||
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8723D) {
|
||||
|
||||
if (xtal_offset_eanble != 0 && p_rf_calibrate_info->txpowertrack_control && (p_hal_data->eeprom_thermal_meter != 0xff)) {
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter Xtal Tracking**********\n"));
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
if (thermal_value > p_hal_data->eeprom_thermal_meter) {
|
||||
#else
|
||||
if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) {
|
||||
#endif
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature(%d) higher than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter));
|
||||
(*c.odm_txxtaltrack_set_xtal)(p_dm_odm);
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature(%d) lower than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter));
|
||||
(*c.odm_txxtaltrack_set_xtal)(p_dm_odm);
|
||||
}
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********End Xtal Tracking**********\n"));
|
||||
}
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
|
||||
if (!IS_HARDWARE_TYPE_8723B(adapter)) {
|
||||
/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
|
||||
if (delta_IQK >= c.threshold_iqk) {
|
||||
p_rf_calibrate_info->thermal_value_iqk = thermal_value;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk));
|
||||
if (!p_rf_calibrate_info->is_iqk_in_progress)
|
||||
(*c.do_iqk)(p_dm_odm, delta_IQK, thermal_value, 8);
|
||||
}
|
||||
}
|
||||
if (p_rf_calibrate_info->dpk_thermal[ODM_RF_PATH_A] != 0) {
|
||||
if (diff_DPK[ODM_RF_PATH_A] >= c.threshold_dpk) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk));
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
|
||||
} else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.threshold_dpk)) {
|
||||
s32 value = 0x20 + (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk);
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
|
||||
} else {
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
|
||||
}
|
||||
}
|
||||
if (p_rf_calibrate_info->dpk_thermal[ODM_RF_PATH_B] != 0) {
|
||||
if (diff_DPK[ODM_RF_PATH_B] >= c.threshold_dpk) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk));
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
|
||||
} else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.threshold_dpk)) {
|
||||
s32 value = 0x20 + (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk);
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
|
||||
} else {
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===odm_txpowertracking_callback_thermal_meter\n"));
|
||||
|
||||
p_rf_calibrate_info->tx_powercount = 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* 3============================================================
|
||||
* 3 IQ Calibration
|
||||
* 3============================================================ */
|
||||
|
||||
void
|
||||
odm_reset_iqk_result(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
|
||||
{
|
||||
u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
|
||||
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165
|
||||
};
|
||||
u8 place = chnl;
|
||||
|
||||
|
||||
if (chnl > 14) {
|
||||
for (place = 14; place < sizeof(channel_all); place++) {
|
||||
if (channel_all[place] == chnl)
|
||||
return place - 13;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
void
|
||||
odm_iq_calibrate(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
)
|
||||
{
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
|
||||
|
||||
RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("=>%s\n" , __FUNCTION__));
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
if (*p_dm_odm->p_is_fcs_mode_enable)
|
||||
return;
|
||||
#endif
|
||||
|
||||
if (p_dm_odm->is_linked) {
|
||||
RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("interval=%d ch=%d prech=%d scan=%s\n", p_dm_odm->linked_interval,
|
||||
*p_dm_odm->p_channel, p_dm_odm->pre_channel, *p_dm_odm->p_is_scan_in_process == TRUE ? "TRUE":"FALSE"));
|
||||
|
||||
if (*p_dm_odm->p_channel != p_dm_odm->pre_channel) {
|
||||
p_dm_odm->pre_channel = *p_dm_odm->p_channel;
|
||||
p_dm_odm->linked_interval = 0;
|
||||
}
|
||||
|
||||
if ((p_dm_odm->linked_interval < 3) && (!*p_dm_odm->p_is_scan_in_process))
|
||||
p_dm_odm->linked_interval++;
|
||||
|
||||
if (p_dm_odm->linked_interval == 2)
|
||||
PHY_IQCalibrate(adapter, false);
|
||||
} else
|
||||
p_dm_odm->linked_interval = 0;
|
||||
|
||||
RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("<=%s interval=%d ch=%d prech=%d scan=%s\n", __FUNCTION__, p_dm_odm->linked_interval,
|
||||
*p_dm_odm->p_channel, p_dm_odm->pre_channel, *p_dm_odm->p_is_scan_in_process == TRUE?"TRUE":"FALSE"));
|
||||
}
|
||||
|
||||
void phydm_rf_init(struct PHY_DM_STRUCT *p_dm_odm)
|
||||
{
|
||||
|
||||
odm_txpowertracking_init(p_dm_odm);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
odm_clear_txpowertracking_state(p_dm_odm);
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
phy_iq_calibrate_8814a_init(p_dm_odm);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
void phydm_rf_watchdog(struct PHY_DM_STRUCT *p_dm_odm)
|
||||
{
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
odm_txpowertracking_check(p_dm_odm);
|
||||
if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)
|
||||
odm_iq_calibrate(p_dm_odm);
|
||||
#endif
|
||||
}
|
||||
119
hal/phydm/halphyrf_win.h
Normal file
119
hal/phydm/halphyrf_win.h
Normal file
|
|
@ -0,0 +1,119 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HAL_PHY_RF_H__
|
||||
#define __HAL_PHY_RF_H__
|
||||
|
||||
#include "phydm_kfree.h"
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
#include "rtl8814a/phydm_iqk_8814a.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
#include "rtl8822b/phydm_iqk_8822b.h"
|
||||
#include "../mac/Halmac_type.h"
|
||||
#endif
|
||||
#include "phydm_powertracking_win.h"
|
||||
|
||||
#if (RTL8821C_SUPPORT == 1)
|
||||
#include "rtl8821c/phydm_iqk_8821c.h"
|
||||
#endif
|
||||
|
||||
enum spur_cal_method {
|
||||
PLL_RESET,
|
||||
AFE_PHASE_SEL
|
||||
};
|
||||
|
||||
enum pwrtrack_method {
|
||||
BBSWING,
|
||||
TXAGC,
|
||||
MIX_MODE,
|
||||
TSSI_MODE,
|
||||
MIX_2G_TSSI_5G_MODE,
|
||||
MIX_5G_TSSI_2G_MODE
|
||||
};
|
||||
|
||||
typedef void(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
|
||||
typedef void(*func_iqk)(void *, u8, u8, u8);
|
||||
typedef void(*func_lck)(void *);
|
||||
typedef void(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
|
||||
typedef void(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
|
||||
typedef void (*func_swing_xtal)(void *, s8 **, s8 **);
|
||||
typedef void (*func_set_xtal)(void *);
|
||||
typedef void(*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
|
||||
|
||||
struct _TXPWRTRACK_CFG {
|
||||
u8 swing_table_size_cck;
|
||||
u8 swing_table_size_ofdm;
|
||||
u8 threshold_iqk;
|
||||
u8 threshold_dpk;
|
||||
u8 average_thermal_num;
|
||||
u8 rf_path_count;
|
||||
u32 thermal_reg_addr;
|
||||
func_set_pwr odm_tx_pwr_track_set_pwr;
|
||||
func_iqk do_iqk;
|
||||
func_lck phy_lc_calibrate;
|
||||
func_swing get_delta_swing_table;
|
||||
func_swing8814only get_delta_swing_table8814only;
|
||||
func_swing_xtal get_delta_swing_xtal_table;
|
||||
func_set_xtal odm_txxtaltrack_set_xtal;
|
||||
func_all_swing get_delta_all_swing_table;
|
||||
};
|
||||
|
||||
void
|
||||
configure_txpower_track(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
struct _TXPWRTRACK_CFG *p_config
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
odm_clear_txpowertracking_state(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
#else
|
||||
struct _ADAPTER *adapter
|
||||
#endif
|
||||
);
|
||||
|
||||
|
||||
|
||||
#define ODM_TARGET_CHNL_NUM_2G_5G 59
|
||||
|
||||
|
||||
void
|
||||
odm_reset_iqk_result(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
u8
|
||||
odm_get_right_chnl_place_for_iqk(
|
||||
u8 chnl
|
||||
);
|
||||
|
||||
void odm_iq_calibrate(struct PHY_DM_STRUCT *p_dm_odm);
|
||||
void phydm_rf_init(struct PHY_DM_STRUCT *p_dm_odm);
|
||||
void phydm_rf_watchdog(struct PHY_DM_STRUCT *p_dm_odm);
|
||||
|
||||
#endif /* #ifndef __HAL_PHY_RF_H__ */
|
||||
19
hal/phydm/mp_precomp.h
Normal file
19
hal/phydm/mp_precomp.h
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
3425
hal/phydm/phydm.c
Normal file
3425
hal/phydm/phydm.c
Normal file
File diff suppressed because it is too large
Load diff
1336
hal/phydm/phydm.h
Normal file
1336
hal/phydm/phydm.h
Normal file
File diff suppressed because it is too large
Load diff
1154
hal/phydm/phydm_acs.c
Normal file
1154
hal/phydm/phydm_acs.c
Normal file
File diff suppressed because it is too large
Load diff
105
hal/phydm/phydm_acs.h
Normal file
105
hal/phydm/phydm_acs.h
Normal file
|
|
@ -0,0 +1,105 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMACS_H__
|
||||
#define __PHYDMACS_H__
|
||||
|
||||
#define ACS_VERSION "1.1" /*20150729 by YuChen*/
|
||||
#define CLM_VERSION "1.0"
|
||||
|
||||
#define ODM_MAX_CHANNEL_2G 14
|
||||
#define ODM_MAX_CHANNEL_5G 24
|
||||
|
||||
/* For phydm_auto_channel_select_setting_ap() */
|
||||
#define STORE_DEFAULT_NHM_SETTING 0
|
||||
#define RESTORE_DEFAULT_NHM_SETTING 1
|
||||
#define ACS_NHM_SETTING 2
|
||||
|
||||
struct _ACS_ {
|
||||
bool is_force_acs_result;
|
||||
u8 clean_channel_2g;
|
||||
u8 clean_channel_5g;
|
||||
u16 channel_info_2g[2][ODM_MAX_CHANNEL_2G]; /* Channel_Info[1]: channel score, Channel_Info[2]:Channel_Scan_Times */
|
||||
u16 channel_info_5g[2][ODM_MAX_CHANNEL_5G];
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
u8 acs_step;
|
||||
/* NHM count 0-11 */
|
||||
u8 nhm_cnt[14][11];
|
||||
|
||||
/* AC-Series, for storing previous setting */
|
||||
u32 reg0x990;
|
||||
u32 reg0x994;
|
||||
u32 reg0x998;
|
||||
u32 reg0x99c;
|
||||
u8 reg0x9a0; /* u8 */
|
||||
|
||||
/* N-Series, for storing previous setting */
|
||||
u32 reg0x890;
|
||||
u32 reg0x894;
|
||||
u32 reg0x898;
|
||||
u32 reg0x89c;
|
||||
u8 reg0xe28; /* u8 */
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
|
||||
void
|
||||
odm_auto_channel_select_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_auto_channel_select_reset(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_auto_channel_select(
|
||||
void *p_dm_void,
|
||||
u8 channel
|
||||
);
|
||||
|
||||
u8
|
||||
odm_get_auto_channel_select_result(
|
||||
void *p_dm_void,
|
||||
u8 band
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
|
||||
void
|
||||
phydm_auto_channel_select_setting_ap(
|
||||
void *p_dm_void,
|
||||
u32 setting, /* 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING */
|
||||
u32 acs_step
|
||||
);
|
||||
|
||||
void
|
||||
phydm_get_nhm_statistics_ap(
|
||||
void *p_dm_void,
|
||||
u32 idx, /* @ 2G, Real channel number = idx+1 */
|
||||
u32 acs_step
|
||||
);
|
||||
|
||||
#endif /* #if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) */
|
||||
|
||||
#endif /* #ifndef __PHYDMACS_H__ */
|
||||
1130
hal/phydm/phydm_adaptivity.c
Normal file
1130
hal/phydm/phydm_adaptivity.c
Normal file
File diff suppressed because it is too large
Load diff
219
hal/phydm/phydm_adaptivity.h
Normal file
219
hal/phydm/phydm_adaptivity.h
Normal file
|
|
@ -0,0 +1,219 @@
|
|||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMADAPTIVITY_H__
|
||||
#define __PHYDMADAPTIVITY_H__
|
||||
|
||||
#define ADAPTIVITY_VERSION "9.3.5" /*20160902 changed by Kevin, refine method for searching pwdb lower bound*/
|
||||
|
||||
#define pwdb_upper_bound 7
|
||||
#define dfir_loss 5
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
|
||||
enum phydm_regulation_type {
|
||||
REGULATION_FCC = 0,
|
||||
REGULATION_MKK = 1,
|
||||
REGULATION_ETSI = 2,
|
||||
REGULATION_WW = 3,
|
||||
|
||||
MAX_REGULATION_NUM = 4
|
||||
};
|
||||
#endif
|
||||
|
||||
enum phydm_adapinfo_e {
|
||||
PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0,
|
||||
PHYDM_ADAPINFO_DCBACKOFF,
|
||||
PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY,
|
||||
PHYDM_ADAPINFO_TH_L2H_INI,
|
||||
PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF,
|
||||
PHYDM_ADAPINFO_AP_NUM_TH
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
enum phydm_set_lna {
|
||||
phydm_disable_lna = 0,
|
||||
phydm_enable_lna = 1,
|
||||
};
|
||||
|
||||
|
||||
enum phydm_trx_mux_type {
|
||||
phydm_shutdown = 0,
|
||||
phydm_standby_mode = 1,
|
||||
phydm_tx_mode = 2,
|
||||
phydm_rx_mode = 3
|
||||
};
|
||||
|
||||
enum phydm_mac_edcca_type {
|
||||
phydm_ignore_edcca = 0,
|
||||
phydm_dont_ignore_edcca = 1
|
||||
};
|
||||
|
||||
struct _ADAPTIVITY_STATISTICS {
|
||||
s8 th_l2h_ini_backup;
|
||||
s8 th_edcca_hl_diff_backup;
|
||||
s8 igi_base;
|
||||
u8 igi_target;
|
||||
u8 nhm_wait;
|
||||
s8 h2l_lb;
|
||||
s8 l2h_lb;
|
||||
bool is_first_link;
|
||||
bool is_check;
|
||||
bool dynamic_link_adaptivity;
|
||||
u8 ap_num_th;
|
||||
u8 adajust_igi_level;
|
||||
bool acs_for_adaptivity;
|
||||
s8 backup_l2h;
|
||||
s8 backup_h2l;
|
||||
bool is_stop_edcca;
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
RT_WORK_ITEM phydm_pause_edcca_work_item;
|
||||
RT_WORK_ITEM phydm_resume_edcca_work_item;
|
||||
#endif
|
||||
};
|
||||
|
||||
void
|
||||
phydm_pause_edcca(
|
||||
void *p_dm_void,
|
||||
bool is_pasue_edcca
|
||||
);
|
||||
|
||||
void
|
||||
phydm_check_adaptivity(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_check_environment(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_nhm_counter_statistics_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_nhm_counter_statistics(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_nhm_counter_statistics_reset(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_get_nhm_counter_statistics(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_mac_edcca_state(
|
||||
void *p_dm_void,
|
||||
enum phydm_mac_edcca_type state
|
||||
);
|
||||
|
||||
void
|
||||
phydm_set_edcca_threshold(
|
||||
void *p_dm_void,
|
||||
s8 H2L,
|
||||
s8 L2H
|
||||
);
|
||||
|
||||
void
|
||||
phydm_set_trx_mux(
|
||||
void *p_dm_void,
|
||||
enum phydm_trx_mux_type tx_mode,
|
||||
enum phydm_trx_mux_type rx_mode
|
||||
);
|
||||
|
||||
bool
|
||||
phydm_cal_nhm_cnt(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_search_pwdb_lower_bound(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_adaptivity_info_init(
|
||||
void *p_dm_void,
|
||||
enum phydm_adapinfo_e cmn_info,
|
||||
u32 value
|
||||
);
|
||||
|
||||
void
|
||||
phydm_adaptivity_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_adaptivity(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_set_edcca_threshold_api(
|
||||
void *p_dm_void,
|
||||
u8 IGI
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void
|
||||
phydm_disable_edcca(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_dynamic_edcca(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_adaptivity_bsod(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
void
|
||||
phydm_pause_edcca_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
);
|
||||
|
||||
void
|
||||
phydm_resume_edcca_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
);
|
||||
|
||||
#endif
|
||||
764
hal/phydm/phydm_adc_sampling.c
Normal file
764
hal/phydm/phydm_adc_sampling.c
Normal file
|
|
@ -0,0 +1,764 @@
|
|||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
#if ((RTL8197F_SUPPORT == 1) || (RTL8822B_SUPPORT == 1))
|
||||
#include "rtl8197f/Hal8197FPhyReg.h"
|
||||
#include "WlanHAL/HalMac88XX/halmac_reg2.h"
|
||||
#else
|
||||
#include "WlanHAL/HalHeader/HalComReg.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (PHYDM_LA_MODE_SUPPORT == 1)
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
|
||||
#if WPP_SOFTWARE_TRACE
|
||||
#include "phydm_adc_sampling.tmh"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
bool
|
||||
phydm_la_buffer_allocate(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp);
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf);
|
||||
bool ret = false;
|
||||
|
||||
dbg_print("[LA mode BufferAllocate]\n");
|
||||
|
||||
if (adc_smp_buf->length == 0) {
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
if (PlatformAllocateMemoryWithZero(adapter, (void **)&(adc_smp_buf->octet), adc_smp_buf->buffer_size) != RT_STATUS_SUCCESS) {
|
||||
#else
|
||||
odm_allocate_memory(p_dm_odm, (void **)&adc_smp_buf->octet, adc_smp_buf->buffer_size);
|
||||
if (!adc_smp_buf->octet) {
|
||||
#endif
|
||||
ret = false;
|
||||
} else
|
||||
adc_smp_buf->length = adc_smp_buf->buffer_size;
|
||||
ret = true;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
void
|
||||
phydm_la_get_tx_pkt_buf(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp);
|
||||
struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf);
|
||||
u32 i = 0, value32, data_l = 0, data_h = 0;
|
||||
u32 addr, finish_addr;
|
||||
u32 end_addr = (adc_smp_buf->start_pos + adc_smp_buf->buffer_size) - 1; /*end_addr = 0x3ffff;*/
|
||||
bool is_round_up;
|
||||
static u32 page = 0xFF;
|
||||
u32 smp_cnt = 0, smp_number = 0, addr_8byte = 0;
|
||||
|
||||
odm_memory_set(p_dm_odm, adc_smp_buf->octet, 0, adc_smp_buf->length);
|
||||
odm_write_1byte(p_dm_odm, 0x0106, 0x69);
|
||||
|
||||
dbg_print("GetTxPktBuf\n");
|
||||
|
||||
value32 = odm_read_4byte(p_dm_odm, 0x7c0);
|
||||
is_round_up = (bool)((value32 & BIT(31)) >> 31);
|
||||
finish_addr = (value32 & 0x7FFF0000) >> 16; /*Reg7C0[30:16]: finish addr (unit: 8byte)*/
|
||||
|
||||
if (is_round_up) {
|
||||
addr = (finish_addr + 1) << 3;
|
||||
dbg_print("is_round_up = ((%d)), finish_addr=((0x%x)), 0x7c0=((0x%x))\n", is_round_up, finish_addr, value32);
|
||||
smp_number = ((adc_smp_buf->buffer_size) >> 3); /*Byte to 64Byte*/
|
||||
} else {
|
||||
addr = adc_smp_buf->start_pos;
|
||||
|
||||
addr_8byte = addr >> 3;
|
||||
if (addr_8byte > finish_addr)
|
||||
smp_number = addr_8byte - finish_addr;
|
||||
else
|
||||
smp_number = finish_addr - addr_8byte;
|
||||
|
||||
dbg_print("is_round_up = ((%d)), finish_addr=((0x%x * 8Byte)), Start_Addr = ((0x%x * 8Byte)), smp_number = ((%d))\n", is_round_up, finish_addr, addr_8byte, smp_number);
|
||||
|
||||
}
|
||||
/*
|
||||
dbg_print("is_round_up = %d, finish_addr=0x%x, value32=0x%x\n", is_round_up, finish_addr, value32);
|
||||
dbg_print("end_addr = %x, adc_smp_buf->start_pos = 0x%x, adc_smp_buf->buffer_size = 0x%x\n", end_addr, adc_smp_buf->start_pos, adc_smp_buf->buffer_size);
|
||||
*/
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
watchdog_stop(p_dm_odm->priv);
|
||||
#endif
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8197F) {
|
||||
for (addr = 0x0, i = 0; addr < end_addr; addr += 8, i += 2) { /*64K byte*/
|
||||
if ((addr & 0xfff) == 0)
|
||||
odm_set_bb_reg(p_dm_odm, 0x0140, MASKLWORD, 0x780 + (addr >> 12));
|
||||
data_l = odm_get_bb_reg(p_dm_odm, 0x8000 + (addr & 0xfff), MASKDWORD);
|
||||
data_h = odm_get_bb_reg(p_dm_odm, 0x8000 + (addr & 0xfff) + 4, MASKDWORD);
|
||||
|
||||
dbg_print("%08x%08x\n", data_h, data_l);
|
||||
}
|
||||
} else {
|
||||
while (addr != (finish_addr << 3)) {
|
||||
if (page != (addr >> 12)) {
|
||||
/*Reg140=0x780+(addr>>12), addr=0x30~0x3F, total 16 pages*/
|
||||
page = (addr >> 12);
|
||||
}
|
||||
odm_set_bb_reg(p_dm_odm, 0x0140, MASKLWORD, 0x780 + page);
|
||||
|
||||
/*pDataL = 0x8000+(addr&0xfff);*/
|
||||
data_l = odm_get_bb_reg(p_dm_odm, 0x8000 + (addr & 0xfff), MASKDWORD);
|
||||
data_h = odm_get_bb_reg(p_dm_odm, 0x8000 + (addr & 0xfff) + 4, MASKDWORD);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
adc_smp_buf->octet[i] = data_h;
|
||||
adc_smp_buf->octet[i + 1] = data_l;
|
||||
#endif
|
||||
|
||||
#if DBG
|
||||
dbg_print("%08x%08x\n", data_h, data_l);
|
||||
#else
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("%08x%08x\n", adc_smp_buf->octet[i], adc_smp_buf->octet[i + 1]));
|
||||
#endif
|
||||
#endif
|
||||
|
||||
i = i + 2;
|
||||
|
||||
if ((addr + 8) >= end_addr)
|
||||
addr = adc_smp_buf->start_pos;
|
||||
else
|
||||
addr = addr + 8;
|
||||
|
||||
smp_cnt++;
|
||||
if (smp_cnt >= (smp_number - 1))
|
||||
break;
|
||||
}
|
||||
dbg_print("smp_cnt = ((%d))\n", smp_cnt);
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("smp_cnt = ((%d))\n", smp_cnt));
|
||||
#endif
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
watchdog_resume(p_dm_odm->priv);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
phydm_la_mode_set_mac_iq_dump(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp);
|
||||
u32 reg_value;
|
||||
|
||||
odm_write_1byte(p_dm_odm, 0x7c0, 0); /*clear all 0x7c0*/
|
||||
odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(0), 1); /*Enable LA mode HW block*/
|
||||
|
||||
if (adc_smp->la_trig_mode == PHYDM_MAC_TRIG) {
|
||||
|
||||
adc_smp->is_bb_trigger = 0;
|
||||
odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(2), 1); /*polling bit for MAC mode*/
|
||||
odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(4) | BIT3, adc_smp->la_trigger_edge); /*trigger mode for MAC*/
|
||||
|
||||
dbg_print("[MAC_trig] ref_mask = ((0x%x)), ref_value = ((0x%x)), dbg_port = ((0x%x))\n", adc_smp->la_mac_ref_mask, adc_smp->la_trig_sig_sel, adc_smp->la_dbg_port);
|
||||
/*[Set MAC Debug Port]*/
|
||||
odm_set_mac_reg(p_dm_odm, 0xF4, BIT(16), 1);
|
||||
odm_set_mac_reg(p_dm_odm, 0x38, 0xff0000, adc_smp->la_dbg_port);
|
||||
odm_set_mac_reg(p_dm_odm, 0x7c4, MASKDWORD, adc_smp->la_mac_ref_mask);
|
||||
odm_set_mac_reg(p_dm_odm, 0x7c8, MASKDWORD, adc_smp->la_trig_sig_sel);
|
||||
|
||||
} else {
|
||||
|
||||
adc_smp->is_bb_trigger = 1;
|
||||
odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(1), 1); /*polling bit for BB ADC mode*/
|
||||
|
||||
if (adc_smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
|
||||
|
||||
odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(3), 1); /*polling bit for MAC trigger event*/
|
||||
odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(7) | BIT(6), adc_smp->la_trig_sig_sel);
|
||||
|
||||
if (adc_smp->la_trig_sig_sel == ADCSMP_TRIG_REG)
|
||||
odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(5), 1); /* manual trigger 0x7C0[5] = 0->1*/
|
||||
}
|
||||
}
|
||||
|
||||
reg_value = odm_get_bb_reg(p_dm_odm, 0x7c0, 0xff);
|
||||
dbg_print("4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value);
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value));
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
phydm_la_mode_set_dma_type(
|
||||
void *p_dm_void,
|
||||
u8 la_dma_type
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
|
||||
dbg_print("2. [LA mode DMA setting] Dma_type = ((%d))\n", la_dma_type);
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("2. [LA mode DMA setting] Dma_type = ((%d))\n", la_dma_type));
|
||||
#endif
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_N_ANTDIV_SUPPORT)
|
||||
odm_set_bb_reg(p_dm_odm, 0x9a0, 0xf00, la_dma_type); /*0x9A0[11:8]*/
|
||||
else
|
||||
odm_set_bb_reg(p_dm_odm, odm_adc_trigger_jaguar2, 0xf00, la_dma_type); /*0x95C[11:8]*/
|
||||
}
|
||||
|
||||
void
|
||||
phydm_adc_smp_start(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp);
|
||||
u8 tmp_u1b;
|
||||
u8 backup_DMA, while_cnt = 0;
|
||||
u8 polling_ok = false, target_polling_bit;
|
||||
|
||||
phydm_la_mode_bb_setting(p_dm_odm);
|
||||
phydm_la_mode_set_dma_type(p_dm_odm, adc_smp->la_dma_type);
|
||||
phydm_la_mode_set_trigger_time(p_dm_odm, adc_smp->la_trigger_time);
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8197F)
|
||||
odm_set_bb_reg(p_dm_odm, 0xd00, BIT(26), 0x1);
|
||||
else { /*for 8814A and 8822B?*/
|
||||
odm_write_1byte(p_dm_odm, 0x198c, 0x7);
|
||||
odm_write_1byte(p_dm_odm, 0x8b4, 0x80);
|
||||
/* odm_set_bb_reg(p_dm_odm, 0x8b4, BIT7, 1); */
|
||||
}
|
||||
|
||||
phydm_la_mode_set_mac_iq_dump(p_dm_odm);
|
||||
/* return; */
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
watchdog_stop(p_dm_odm->priv);
|
||||
#endif
|
||||
|
||||
target_polling_bit = (adc_smp->is_bb_trigger) ? BIT(1) : BIT(2);
|
||||
do { /*Polling time always use 100ms, when it exceed 2s, break while loop*/
|
||||
tmp_u1b = odm_read_1byte(p_dm_odm, 0x7c0);
|
||||
|
||||
if (adc_smp->adc_smp_state != ADCSMP_STATE_SET) {
|
||||
dbg_print("[state Error] adc_smp_state != ADCSMP_STATE_SET\n");
|
||||
break;
|
||||
|
||||
} else if (tmp_u1b & target_polling_bit) {
|
||||
ODM_delay_ms(100);
|
||||
while_cnt = while_cnt + 1;
|
||||
continue;
|
||||
} else {
|
||||
dbg_print("[LA Query OK] polling_bit=((0x%x))\n", target_polling_bit);
|
||||
polling_ok = true;
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8197F)
|
||||
odm_set_bb_reg(p_dm_odm, 0x7c0, BIT(0), 0x0);
|
||||
break;
|
||||
}
|
||||
} while (while_cnt < 20);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
watchdog_resume(p_dm_odm->priv);
|
||||
#if (RTL8197F_SUPPORT)
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8197F) {
|
||||
/*Stop DMA*/
|
||||
backup_DMA = odm_get_mac_reg(p_dm_odm, 0x300, MASKLWORD);
|
||||
odm_set_mac_reg(p_dm_odm, 0x300, 0x7fff, backup_DMA | 0x7fff);
|
||||
|
||||
/*move LA mode content from IMEM to TxPktBuffer
|
||||
Src : OCPBASE_IMEM 0x00000000
|
||||
Dest : OCPBASE_TXBUF 0x18780000
|
||||
Len : 64K*/
|
||||
GET_HAL_INTERFACE(p_dm_odm->priv)->init_ddma_handler(p_dm_odm->priv, OCPBASE_IMEM, OCPBASE_TXBUF, 0x10000);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
if (adc_smp->adc_smp_state == ADCSMP_STATE_SET) {
|
||||
|
||||
if (polling_ok)
|
||||
phydm_la_get_tx_pkt_buf(p_dm_odm);
|
||||
else
|
||||
dbg_print("[Polling timeout]\n");
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8197F)
|
||||
odm_set_mac_reg(p_dm_odm, 0x300, 0x7fff, backup_DMA); /*Resume DMA*/
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
if (adc_smp->adc_smp_state == ADCSMP_STATE_SET)
|
||||
adc_smp->adc_smp_state = ADCSMP_STATE_QUERY;
|
||||
#endif
|
||||
|
||||
dbg_print("[LA mode] LA_pattern_count = ((%d))\n", adc_smp->la_count);
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("[LA mode] la_count = ((%d))\n", adc_smp->la_count));
|
||||
#endif
|
||||
|
||||
|
||||
adc_smp_stop(p_dm_odm);
|
||||
|
||||
if (adc_smp->la_count == 0) {
|
||||
dbg_print("LA Dump finished ---------->\n\n\n");
|
||||
/**/
|
||||
} else {
|
||||
adc_smp->la_count--;
|
||||
dbg_print("LA Dump more ---------->\n\n\n");
|
||||
adc_smp_set(p_dm_odm, adc_smp->la_trig_mode, adc_smp->la_trig_sig_sel, adc_smp->la_dma_type, adc_smp->la_trigger_time, 0);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
void
|
||||
adc_smp_work_item_callback(
|
||||
void *p_context
|
||||
)
|
||||
{
|
||||
struct _ADAPTER *adapter = (struct _ADAPTER *)p_context;
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp);
|
||||
|
||||
dbg_print("[WorkItem Call back] LA_State=((%d))\n", adc_smp->adc_smp_state);
|
||||
phydm_adc_smp_start(p_dm_odm);
|
||||
}
|
||||
#endif
|
||||
|
||||
void
|
||||
adc_smp_set(
|
||||
void *p_dm_void,
|
||||
u8 trig_mode,
|
||||
u32 trig_sig_sel,
|
||||
u8 dma_data_sig_sel,
|
||||
u32 trigger_time,
|
||||
u16 polling_time
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
bool is_set_success = true;
|
||||
struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp);
|
||||
|
||||
adc_smp->la_trig_mode = trig_mode;
|
||||
adc_smp->la_trig_sig_sel = trig_sig_sel;
|
||||
adc_smp->la_dma_type = dma_data_sig_sel;
|
||||
adc_smp->la_trigger_time = trigger_time;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
if (adc_smp->adc_smp_state != ADCSMP_STATE_IDLE)
|
||||
is_set_success = false;
|
||||
else if (adc_smp->adc_smp_buf.length == 0)
|
||||
is_set_success = phydm_la_buffer_allocate(p_dm_odm);
|
||||
#endif
|
||||
|
||||
if (is_set_success) {
|
||||
adc_smp->adc_smp_state = ADCSMP_STATE_SET;
|
||||
|
||||
dbg_print("[LA Set Success] LA_State=((%d))\n", adc_smp->adc_smp_state);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
|
||||
dbg_print("ADCSmp_work_item_index = ((%d))\n", adc_smp->la_work_item_index);
|
||||
if (adc_smp->la_work_item_index != 0) {
|
||||
odm_schedule_work_item(&(adc_smp->adc_smp_work_item_1));
|
||||
adc_smp->la_work_item_index = 0;
|
||||
} else {
|
||||
odm_schedule_work_item(&(adc_smp->adc_smp_work_item));
|
||||
adc_smp->la_work_item_index = 1;
|
||||
}
|
||||
#else
|
||||
phydm_adc_smp_start(p_dm_odm);
|
||||
#endif
|
||||
} else
|
||||
dbg_print("[LA Set Fail] LA_State=((%d))\n", adc_smp->adc_smp_state);
|
||||
|
||||
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
enum rt_status
|
||||
adc_smp_query(
|
||||
void *p_dm_void,
|
||||
ULONG information_buffer_length,
|
||||
void *information_buffer,
|
||||
PULONG bytes_written
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp);
|
||||
enum rt_status ret_status = RT_STATUS_SUCCESS;
|
||||
struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf);
|
||||
|
||||
dbg_print("[%s] LA_State=((%d))", __func__, adc_smp->adc_smp_state);
|
||||
|
||||
if (information_buffer_length != adc_smp_buf->buffer_size) {
|
||||
*bytes_written = 0;
|
||||
ret_status = RT_STATUS_RESOURCE;
|
||||
} else if (adc_smp_buf->length != adc_smp_buf->buffer_size) {
|
||||
*bytes_written = 0;
|
||||
ret_status = RT_STATUS_RESOURCE;
|
||||
} else if (adc_smp->adc_smp_state != ADCSMP_STATE_QUERY) {
|
||||
*bytes_written = 0;
|
||||
ret_status = RT_STATUS_PENDING;
|
||||
} else {
|
||||
odm_move_memory(p_dm_odm, information_buffer, adc_smp_buf->octet, adc_smp_buf->buffer_size);
|
||||
*bytes_written = adc_smp_buf->buffer_size;
|
||||
|
||||
adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
|
||||
}
|
||||
|
||||
dbg_print("Return status %d\n", ret_status);
|
||||
|
||||
return ret_status;
|
||||
}
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
|
||||
void
|
||||
adc_smp_query(
|
||||
void *p_dm_void,
|
||||
void *output,
|
||||
u32 out_len,
|
||||
u32 *pused
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp);
|
||||
struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf);
|
||||
u32 used = *pused;
|
||||
u32 i;
|
||||
/* struct timespec t; */
|
||||
/* rtw_get_current_timespec(&t); */
|
||||
|
||||
dbg_print("%s adc_smp_state %d", __func__, adc_smp->adc_smp_state);
|
||||
|
||||
for (i = 0; i < (adc_smp_buf->length >> 2) - 2; i += 2) {
|
||||
PHYDM_SNPRINTF((output + used, out_len - used,
|
||||
"%08x%08x\n", adc_smp_buf->octet[i], adc_smp_buf->octet[i + 1]));
|
||||
}
|
||||
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "\n"));
|
||||
/* PHYDM_SNPRINTF((output+used, out_len-used, "\n[%lu.%06lu]\n", t.tv_sec, t.tv_nsec)); */
|
||||
*pused = used;
|
||||
}
|
||||
|
||||
s32
|
||||
adc_smp_get_sample_counts(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp);
|
||||
struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf);
|
||||
|
||||
return (adc_smp_buf->length >> 2) - 2;
|
||||
}
|
||||
|
||||
s32
|
||||
adc_smp_query_single_data(
|
||||
void *p_dm_void,
|
||||
void *output,
|
||||
u32 out_len,
|
||||
u32 index
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp);
|
||||
struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf);
|
||||
u32 used = 0;
|
||||
|
||||
/* dbg_print("%s adc_smp_state %d\n", __func__, adc_smp->adc_smp_state); */
|
||||
if (adc_smp->adc_smp_state != ADCSMP_STATE_QUERY) {
|
||||
PHYDM_SNPRINTF((output + used, out_len - used,
|
||||
"Error: la data is not ready yet ...\n"));
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (index < ((adc_smp_buf->length >> 2) - 2)) {
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "%08x%08x\n",
|
||||
adc_smp_buf->octet[index], adc_smp_buf->octet[index + 1]));
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
void
|
||||
adc_smp_stop(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp);
|
||||
|
||||
adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
|
||||
dbg_print("[LA_Stop] LA_state = ((%d))\n", adc_smp->adc_smp_state);
|
||||
}
|
||||
|
||||
void
|
||||
adc_smp_init(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp);
|
||||
struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf);
|
||||
|
||||
adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8814A) {
|
||||
adc_smp_buf->start_pos = 0x30000;
|
||||
adc_smp_buf->buffer_size = 0x10000;
|
||||
} else if (p_dm_odm->support_ic_type & ODM_RTL8822B) {
|
||||
adc_smp_buf->start_pos = 0x20000;
|
||||
adc_smp_buf->buffer_size = 0x20000;
|
||||
} else if (p_dm_odm->support_ic_type & ODM_RTL8197F) {
|
||||
adc_smp_buf->start_pos = 0x00000;
|
||||
adc_smp_buf->buffer_size = 0x10000;
|
||||
} else if (p_dm_odm->support_ic_type & ODM_RTL8821C) {
|
||||
adc_smp_buf->start_pos = 0x8000;
|
||||
adc_smp_buf->buffer_size = 0x8000;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
void
|
||||
adc_smp_de_init(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp);
|
||||
struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf);
|
||||
|
||||
adc_smp_stop(p_dm_odm);
|
||||
|
||||
if (adc_smp_buf->length != 0x0) {
|
||||
odm_free_memory(p_dm_odm, adc_smp_buf->octet, adc_smp_buf->length);
|
||||
adc_smp_buf->length = 0x0;
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
void
|
||||
phydm_la_mode_bb_setting(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp);
|
||||
|
||||
u8 trig_mode = adc_smp->la_trig_mode;
|
||||
u32 trig_sig_sel = adc_smp->la_trig_sig_sel;
|
||||
u32 dbg_port = adc_smp->la_dbg_port;
|
||||
u8 is_trigger_edge = adc_smp->la_trigger_edge;
|
||||
u8 sampling_rate = adc_smp->la_smp_rate;
|
||||
|
||||
dbg_print("1. [LA mode bb_setting] trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x))\n",
|
||||
trig_mode, dbg_port, is_trigger_edge, sampling_rate, trig_sig_sel);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("1. [LA mode bb_setting]trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x))\n",
|
||||
trig_mode, dbg_port, is_trigger_edge, sampling_rate, trig_sig_sel));
|
||||
#endif
|
||||
|
||||
if (trig_mode == PHYDM_MAC_TRIG)
|
||||
trig_sig_sel = 0; /*ignore this setting*/
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
|
||||
|
||||
if (trig_mode == PHYDM_ADC_RF0_TRIG) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x8f8, BIT(25) | BIT24 | BIT23 | BIT22, 9); /*DBGOUT_RFC_a[31:0]*/
|
||||
} else if (trig_mode == PHYDM_ADC_RF1_TRIG) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x8f8, BIT(25) | BIT24 | BIT23 | BIT22, 8); /*DBGOUT_RFC_b[31:0]*/
|
||||
} else
|
||||
odm_set_bb_reg(p_dm_odm, 0x8f8, BIT(25) | BIT(24) | BIT(23) | BIT(22), 0);
|
||||
/*
|
||||
(0:) '{ofdm_dbg[31:0]}'
|
||||
(1:) '{cca,crc32_fail,dbg_ofdm[29:0]}'
|
||||
(2:) '{vbon,crc32_fail,dbg_ofdm[29:0]}'
|
||||
(3:) '{cca,crc32_ok,dbg_ofdm[29:0]}'
|
||||
(4:) '{vbon,crc32_ok,dbg_ofdm[29:0]}'
|
||||
(5:) '{dbg_iqk_anta}'
|
||||
(6:) '{cca,ofdm_crc_ok,dbg_dp_anta[29:0]}'
|
||||
(7:) '{dbg_iqk_antb}'
|
||||
(8:) '{DBGOUT_RFC_b[31:0]}'
|
||||
(9:) '{DBGOUT_RFC_a[31:0]}'
|
||||
(a:) '{dbg_ofdm}'
|
||||
(b:) '{dbg_cck}'
|
||||
*/
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, 0x198C, BIT(2) | BIT1 | BIT0, 7); /*disable dbg clk gating*/
|
||||
|
||||
/*dword= odm_get_bb_reg(p_dm_odm, 0x8FC, MASKDWORD);*/
|
||||
/*dbg_print("dbg_port = ((0x%x))\n", dword);*/
|
||||
odm_set_bb_reg(p_dm_odm, 0x95C, 0x1f, trig_sig_sel); /*0x95C[4:0], BB debug port bit*/
|
||||
odm_set_bb_reg(p_dm_odm, 0x8FC, MASKDWORD, dbg_port);
|
||||
odm_set_bb_reg(p_dm_odm, 0x95C, BIT(31), is_trigger_edge); /*0: posedge, 1: negedge*/
|
||||
odm_set_bb_reg(p_dm_odm, 0x95c, 0xe0, sampling_rate);
|
||||
/* (0:) '80MHz'
|
||||
(1:) '40MHz'
|
||||
(2:) '20MHz'
|
||||
(3:) '10MHz'
|
||||
(4:) '5MHz'
|
||||
(5:) '2.5MHz'
|
||||
(6:) '1.25MHz'
|
||||
(7:) '160MHz (for BW160 ic)'
|
||||
*/
|
||||
} else {
|
||||
odm_set_bb_reg(p_dm_odm, 0x9a0, 0x1f, trig_sig_sel); /*0x9A0[4:0], BB debug port bit*/
|
||||
odm_set_bb_reg(p_dm_odm, 0x908, MASKDWORD, dbg_port);
|
||||
odm_set_bb_reg(p_dm_odm, 0x9A0, BIT(31), is_trigger_edge); /*0: posedge, 1: negedge*/
|
||||
odm_set_bb_reg(p_dm_odm, 0x9A0, 0xe0, sampling_rate);
|
||||
/* (0:) '80MHz'
|
||||
(1:) '40MHz'
|
||||
(2:) '20MHz'
|
||||
(3:) '10MHz'
|
||||
(4:) '5MHz'
|
||||
(5:) '2.5MHz'
|
||||
(6:) '1.25MHz'
|
||||
(7:) '160MHz (for BW160 ic)'
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
phydm_la_mode_set_trigger_time(
|
||||
void *p_dm_void,
|
||||
u32 trigger_time_mu_sec
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u8 trigger_time_unit_num;
|
||||
u32 time_unit = 0;
|
||||
|
||||
if (trigger_time_mu_sec < 128) {
|
||||
time_unit = 0; /*unit: 1mu sec*/
|
||||
} else if (trigger_time_mu_sec < 256) {
|
||||
time_unit = 1; /*unit: 2mu sec*/
|
||||
} else if (trigger_time_mu_sec < 512) {
|
||||
time_unit = 2; /*unit: 4mu sec*/
|
||||
} else if (trigger_time_mu_sec < 1024) {
|
||||
time_unit = 3; /*unit: 8mu sec*/
|
||||
} else if (trigger_time_mu_sec < 2048) {
|
||||
time_unit = 4; /*unit: 16mu sec*/
|
||||
} else if (trigger_time_mu_sec < 4096) {
|
||||
time_unit = 5; /*unit: 32mu sec*/
|
||||
} else if (trigger_time_mu_sec < 8192) {
|
||||
time_unit = 6; /*unit: 64mu sec*/
|
||||
}
|
||||
|
||||
trigger_time_unit_num = (u8)(trigger_time_mu_sec >> time_unit);
|
||||
|
||||
dbg_print("3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", trigger_time_unit_num, time_unit);
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", trigger_time_unit_num, time_unit));
|
||||
#endif
|
||||
|
||||
odm_set_mac_reg(p_dm_odm, 0x7cc, BIT(20) | BIT(19) | BIT(18), time_unit);
|
||||
odm_set_mac_reg(p_dm_odm, 0x7c0, 0x7f00, (trigger_time_unit_num & 0x7f));
|
||||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
phydm_lamode_trigger_setting(
|
||||
void *p_dm_void,
|
||||
char input[][16],
|
||||
u32 *_used,
|
||||
char *output,
|
||||
u32 *_out_len,
|
||||
u32 input_num
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp);
|
||||
u8 trig_mode, dma_data_sig_sel;
|
||||
u32 trig_sig_sel;
|
||||
bool is_enable_la_mode, is_trigger_edge;
|
||||
u32 dbg_port, trigger_time_mu_sec;
|
||||
u32 mac_ref_signal_mask;
|
||||
u8 sampling_rate = 0, i;
|
||||
char help[] = "-h";
|
||||
u32 var1[10] = {0};
|
||||
u32 used = *_used;
|
||||
u32 out_len = *_out_len;
|
||||
|
||||
if (p_dm_odm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE) {
|
||||
|
||||
PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
|
||||
is_enable_la_mode = (bool)var1[0];
|
||||
/*dbg_print("echo cmd input_num = %d\n", input_num);*/
|
||||
|
||||
if ((strcmp(input[1], help) == 0)) {
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "{En} {0:BB,1:BB_MAC,2:RF0,3:RF1,4:MAC} \n {BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA type} {TrigTime} \n {polling_time/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n"));
|
||||
/**/
|
||||
} else if ((is_enable_la_mode == 1)) {
|
||||
|
||||
PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
|
||||
|
||||
trig_mode = (u8)var1[1];
|
||||
|
||||
if (trig_mode == PHYDM_MAC_TRIG)
|
||||
PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);
|
||||
else
|
||||
PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
|
||||
trig_sig_sel = var1[2];
|
||||
|
||||
PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
|
||||
PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]);
|
||||
PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]);
|
||||
PHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]);
|
||||
PHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]);
|
||||
PHYDM_SSCANF(input[9], DCMD_DECIMAL, &var1[8]);
|
||||
PHYDM_SSCANF(input[10], DCMD_DECIMAL, &var1[9]);
|
||||
|
||||
dma_data_sig_sel = (u8)var1[3];
|
||||
trigger_time_mu_sec = var1[4]; /*unit: us*/
|
||||
|
||||
adc_smp->la_mac_ref_mask = var1[5];
|
||||
adc_smp->la_dbg_port = var1[6];
|
||||
adc_smp->la_trigger_edge = (u8) var1[7];
|
||||
adc_smp->la_smp_rate = (u8)(var1[8] & 0x7);
|
||||
adc_smp->la_count = var1[9];
|
||||
|
||||
|
||||
dbg_print("echo lamode %d %d %d %d %d %d %x %d %d %d\n", var1[0], var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], var1[7], var1[8], var1[9]);
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("echo lamode %d %d %d %d %d %d %x %d %d %d\n", var1[0], var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], var1[7], var1[8], var1[9]));
|
||||
#endif
|
||||
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "a.En= ((1)), b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n", trig_mode, trig_sig_sel, dma_data_sig_sel));
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "e.Trig_Time = ((%dus)), f.mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n", trigger_time_mu_sec, adc_smp->la_mac_ref_mask, adc_smp->la_dbg_port));
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n", adc_smp->la_trigger_edge, (80 >> adc_smp->la_smp_rate), adc_smp->la_count));
|
||||
|
||||
adc_smp_set(p_dm_odm, trig_mode, trig_sig_sel, dma_data_sig_sel, trigger_time_mu_sec, 0);
|
||||
|
||||
} else {
|
||||
adc_smp_stop(p_dm_odm);
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "Disable LA mode\n"));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif /*endif PHYDM_LA_MODE_SUPPORT == 1*/
|
||||
147
hal/phydm/phydm_adc_sampling.h
Normal file
147
hal/phydm/phydm_adc_sampling.h
Normal file
|
|
@ -0,0 +1,147 @@
|
|||
#ifndef __INC_ADCSMP_H
|
||||
#define __INC_ADCSMP_H
|
||||
|
||||
#define DYNAMIC_LA_MODE "1.0" /*2016.07.15 Dino */
|
||||
|
||||
#if (PHYDM_LA_MODE_SUPPORT == 1)
|
||||
|
||||
struct _RT_ADCSMP_STRING {
|
||||
u32 *octet;
|
||||
u32 length;
|
||||
u32 buffer_size;
|
||||
u32 start_pos;
|
||||
};
|
||||
|
||||
|
||||
enum rt_adcsmp_trig_sel {
|
||||
PHYDM_ADC_BB_TRIG = 0,
|
||||
PHYDM_ADC_MAC_TRIG = 1,
|
||||
PHYDM_ADC_RF0_TRIG = 2,
|
||||
PHYDM_ADC_RF1_TRIG = 3,
|
||||
PHYDM_MAC_TRIG = 4
|
||||
};
|
||||
|
||||
|
||||
enum rt_adcsmp_trig_sig_sel {
|
||||
ADCSMP_TRIG_CRCOK = 0,
|
||||
ADCSMP_TRIG_CRCFAIL = 1,
|
||||
ADCSMP_TRIG_CCA = 2,
|
||||
ADCSMP_TRIG_REG = 3
|
||||
};
|
||||
|
||||
|
||||
enum rt_adcsmp_state {
|
||||
ADCSMP_STATE_IDLE = 0,
|
||||
ADCSMP_STATE_SET = 1,
|
||||
ADCSMP_STATE_QUERY = 2
|
||||
};
|
||||
|
||||
|
||||
struct _RT_ADCSMP {
|
||||
struct _RT_ADCSMP_STRING adc_smp_buf;
|
||||
enum rt_adcsmp_state adc_smp_state;
|
||||
u8 la_trig_mode;
|
||||
u32 la_trig_sig_sel;
|
||||
u8 la_dma_type;
|
||||
u32 la_trigger_time;
|
||||
u32 la_mac_ref_mask;
|
||||
u32 la_dbg_port;
|
||||
u8 la_trigger_edge;
|
||||
u8 la_smp_rate;
|
||||
u32 la_count;
|
||||
u8 is_bb_trigger;
|
||||
u8 la_work_item_index;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
RT_WORK_ITEM adc_smp_work_item;
|
||||
RT_WORK_ITEM adc_smp_work_item_1;
|
||||
#endif
|
||||
};
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
void
|
||||
adc_smp_work_item_callback(
|
||||
void *p_context
|
||||
);
|
||||
#endif
|
||||
|
||||
void
|
||||
adc_smp_set(
|
||||
void *p_dm_void,
|
||||
u8 trig_mode,
|
||||
u32 trig_sig_sel,
|
||||
u8 dma_data_sig_sel,
|
||||
u32 trigger_time,
|
||||
u16 polling_time
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
enum rt_status
|
||||
adc_smp_query(
|
||||
void *p_dm_void,
|
||||
ULONG information_buffer_length,
|
||||
void *information_buffer,
|
||||
PULONG bytes_written
|
||||
);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
void
|
||||
adc_smp_query(
|
||||
void *p_dm_void,
|
||||
void *output,
|
||||
u32 out_len,
|
||||
u32 *pused
|
||||
);
|
||||
|
||||
s32
|
||||
adc_smp_get_sample_counts(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
s32
|
||||
adc_smp_query_single_data(
|
||||
void *p_dm_void,
|
||||
void *output,
|
||||
u32 out_len,
|
||||
u32 index
|
||||
);
|
||||
|
||||
#endif
|
||||
void
|
||||
adc_smp_stop(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
adc_smp_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
void
|
||||
adc_smp_de_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
#endif
|
||||
|
||||
void
|
||||
phydm_la_mode_bb_setting(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_la_mode_set_trigger_time(
|
||||
void *p_dm_void,
|
||||
u32 trigger_time_mu_sec
|
||||
);
|
||||
|
||||
void
|
||||
phydm_lamode_trigger_setting(
|
||||
void *p_dm_void,
|
||||
char input[][16],
|
||||
u32 *_used,
|
||||
char *output,
|
||||
u32 *_out_len,
|
||||
u32 input_num
|
||||
);
|
||||
#endif
|
||||
#endif
|
||||
864
hal/phydm/phydm_antdect.c
Normal file
864
hal/phydm/phydm_antdect.c
Normal file
|
|
@ -0,0 +1,864 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* ************************************************************
|
||||
* include files
|
||||
* ************************************************************ */
|
||||
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
/* #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */
|
||||
#if (defined(CONFIG_ANT_DETECTION))
|
||||
|
||||
/* IS_ANT_DETECT_SUPPORT_SINGLE_TONE(adapter)
|
||||
* IS_ANT_DETECT_SUPPORT_RSSI(adapter)
|
||||
* IS_ANT_DETECT_SUPPORT_PSD(adapter) */
|
||||
|
||||
/* 1 [1. Single Tone method] =================================================== */
|
||||
|
||||
/*
|
||||
* Description:
|
||||
* Set Single/Dual Antenna default setting for products that do not do detection in advance.
|
||||
*
|
||||
* Added by Joseph, 2012.03.22
|
||||
* */
|
||||
void
|
||||
odm_single_dual_antenna_default_setting(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table;
|
||||
struct _ADAPTER *p_adapter = p_dm_odm->adapter;
|
||||
|
||||
u8 bt_ant_num = BT_GetPgAntNum(p_adapter);
|
||||
/* Set default antenna A and B status */
|
||||
if (bt_ant_num == 2) {
|
||||
p_dm_swat_table->ANTA_ON = true;
|
||||
p_dm_swat_table->ANTB_ON = true;
|
||||
|
||||
} else if (bt_ant_num == 1) {
|
||||
/* Set antenna A as default */
|
||||
p_dm_swat_table->ANTA_ON = true;
|
||||
p_dm_swat_table->ANTB_ON = false;
|
||||
|
||||
} else
|
||||
RT_ASSERT(false, ("Incorrect antenna number!!\n"));
|
||||
}
|
||||
|
||||
|
||||
/* 2 8723A ANT DETECT
|
||||
*
|
||||
* Description:
|
||||
* Implement IQK single tone for RF DPK loopback and BB PSD scanning.
|
||||
* This function is cooperated with BB team Neil.
|
||||
*
|
||||
* Added by Roger, 2011.12.15
|
||||
* */
|
||||
bool
|
||||
odm_single_dual_antenna_detection(
|
||||
void *p_dm_void,
|
||||
u8 mode
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ADAPTER *p_adapter = p_dm_odm->adapter;
|
||||
struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table;
|
||||
u32 current_channel, rf_loop_reg;
|
||||
u8 n;
|
||||
u32 reg88c, regc08, reg874, regc50, reg948, regb2c, reg92c, reg930, reg064, afe_rrx_wait_cca;
|
||||
u8 initial_gain = 0x5a;
|
||||
u32 PSD_report_tmp;
|
||||
u32 ant_a_report = 0x0, ant_b_report = 0x0, ant_0_report = 0x0;
|
||||
bool is_result = true;
|
||||
u32 afe_backup[16];
|
||||
u32 AFE_REG_8723A[16] = {
|
||||
REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
|
||||
REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
|
||||
REG_TX_OFDM_BBON, REG_TX_TO_RX,
|
||||
REG_TX_TO_TX, REG_RX_CCK,
|
||||
REG_RX_OFDM, REG_RX_WAIT_RIFS,
|
||||
REG_RX_TO_RX, REG_STANDBY,
|
||||
REG_SLEEP, REG_PMPD_ANAEN,
|
||||
REG_FPGA0_XCD_SWITCH_CONTROL, REG_BLUE_TOOTH
|
||||
};
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection()============>\n"));
|
||||
|
||||
|
||||
if (!(p_dm_odm->support_ic_type & ODM_RTL8723B))
|
||||
return is_result;
|
||||
|
||||
/* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */
|
||||
if (!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(p_adapter))
|
||||
return is_result;
|
||||
|
||||
/* 1 Backup Current RF/BB Settings */
|
||||
|
||||
current_channel = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK);
|
||||
rf_loop_reg = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x00, RFREGOFFSETMASK);
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8723B) {
|
||||
reg92c = odm_get_bb_reg(p_dm_odm, REG_DPDT_CONTROL, MASKDWORD);
|
||||
reg930 = odm_get_bb_reg(p_dm_odm, rfe_ctrl_anta_src, MASKDWORD);
|
||||
reg948 = odm_get_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, MASKDWORD);
|
||||
regb2c = odm_get_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, MASKDWORD);
|
||||
reg064 = odm_get_mac_reg(p_dm_odm, REG_SYM_WLBT_PAPE_SEL, BIT(29));
|
||||
odm_set_bb_reg(p_dm_odm, REG_DPDT_CONTROL, 0x3, 0x1);
|
||||
odm_set_bb_reg(p_dm_odm, rfe_ctrl_anta_src, 0xff, 0x77);
|
||||
odm_set_mac_reg(p_dm_odm, REG_SYM_WLBT_PAPE_SEL, BIT(29), 0x1); /* dbg 7 */
|
||||
odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, 0x3c0, 0x0);/* dbg 8 */
|
||||
odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, BIT(31), 0x0);
|
||||
}
|
||||
|
||||
odm_stall_execution(10);
|
||||
|
||||
/* Store A path Register 88c, c08, 874, c50 */
|
||||
reg88c = odm_get_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD);
|
||||
regc08 = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD);
|
||||
reg874 = odm_get_bb_reg(p_dm_odm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD);
|
||||
regc50 = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD);
|
||||
|
||||
/* Store AFE Registers */
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8723B)
|
||||
afe_rrx_wait_cca = odm_get_bb_reg(p_dm_odm, REG_RX_WAIT_CCA, MASKDWORD);
|
||||
|
||||
/* Set PSD 128 pts */
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pts */
|
||||
|
||||
/* To SET CH1 to do */
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK, 0x7401); /* channel 1 */
|
||||
|
||||
/* AFE all on step */
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8723B)
|
||||
odm_set_bb_reg(p_dm_odm, REG_RX_WAIT_CCA, MASKDWORD, 0x01c00016);
|
||||
|
||||
/* 3 wire Disable */
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, 0xCCF000C0);
|
||||
|
||||
/* BB IQK setting */
|
||||
odm_set_bb_reg(p_dm_odm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800E4);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x22208000);
|
||||
|
||||
/* IQK setting tone@ 4.34Mhz */
|
||||
odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_A, MASKDWORD, 0x10008C1C);
|
||||
odm_set_bb_reg(p_dm_odm, REG_TX_IQK, MASKDWORD, 0x01007c00);
|
||||
|
||||
/* Page B init */
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00080000);
|
||||
odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x0f600000);
|
||||
odm_set_bb_reg(p_dm_odm, REG_RX_IQK, MASKDWORD, 0x01004800);
|
||||
odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_A, MASKDWORD, 0x10008c1f);
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8723B) {
|
||||
odm_set_bb_reg(p_dm_odm, REG_TX_IQK_PI_A, MASKDWORD, 0x82150016);
|
||||
odm_set_bb_reg(p_dm_odm, REG_RX_IQK_PI_A, MASKDWORD, 0x28150016);
|
||||
}
|
||||
odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_RSP, MASKDWORD, 0x001028d0);
|
||||
odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, 0x7f, initial_gain);
|
||||
|
||||
/* IQK Single tone start */
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x808000);
|
||||
odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
|
||||
odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
|
||||
|
||||
odm_stall_execution(10000);
|
||||
|
||||
/* PSD report of antenna A */
|
||||
PSD_report_tmp = 0x0;
|
||||
for (n = 0; n < 2; n++) {
|
||||
PSD_report_tmp = get_psd_data(p_dm_odm, 14, initial_gain);
|
||||
if (PSD_report_tmp > ant_a_report)
|
||||
ant_a_report = PSD_report_tmp;
|
||||
}
|
||||
|
||||
/* change to Antenna B */
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8723B) {
|
||||
/* odm_set_bb_reg(p_dm_odm, REG_DPDT_CONTROL, 0x3, 0x2); */
|
||||
odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);
|
||||
odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);
|
||||
}
|
||||
|
||||
odm_stall_execution(10);
|
||||
|
||||
/* PSD report of antenna B */
|
||||
PSD_report_tmp = 0x0;
|
||||
for (n = 0; n < 2; n++) {
|
||||
PSD_report_tmp = get_psd_data(p_dm_odm, 14, initial_gain);
|
||||
if (PSD_report_tmp > ant_b_report)
|
||||
ant_b_report = PSD_report_tmp;
|
||||
}
|
||||
|
||||
/* Close IQK Single Tone function */
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
|
||||
|
||||
/* 1 Return to antanna A */
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8723B) {
|
||||
/* external DPDT */
|
||||
odm_set_bb_reg(p_dm_odm, REG_DPDT_CONTROL, MASKDWORD, reg92c);
|
||||
|
||||
/* internal S0/S1 */
|
||||
odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948);
|
||||
odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c);
|
||||
odm_set_bb_reg(p_dm_odm, rfe_ctrl_anta_src, MASKDWORD, reg930);
|
||||
odm_set_mac_reg(p_dm_odm, REG_SYM_WLBT_PAPE_SEL, BIT(29), reg064);
|
||||
}
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, reg88c);
|
||||
odm_set_bb_reg(p_dm_odm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, regc08);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, reg874);
|
||||
odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, 0x7F, 0x40);
|
||||
odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD, regc50);
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, current_channel);
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x00, RFREGOFFSETMASK, rf_loop_reg);
|
||||
|
||||
/* Reload AFE Registers */
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8723B)
|
||||
odm_set_bb_reg(p_dm_odm, REG_RX_WAIT_CCA, MASKDWORD, afe_rrx_wait_cca);
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8723B) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d\n", 2416, ant_a_report));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d\n", 2416, ant_b_report));
|
||||
|
||||
/* 2 Test ant B based on ant A is ON */
|
||||
if ((ant_a_report >= 100) && (ant_b_report >= 100) && (ant_a_report <= 135) && (ant_b_report <= 135)) {
|
||||
u8 TH1 = 2, TH2 = 6;
|
||||
|
||||
if ((ant_a_report - ant_b_report < TH1) || (ant_b_report - ant_a_report < TH1)) {
|
||||
p_dm_swat_table->ANTA_ON = true;
|
||||
p_dm_swat_table->ANTB_ON = true;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection(): Dual Antenna\n"));
|
||||
} else if (((ant_a_report - ant_b_report >= TH1) && (ant_a_report - ant_b_report <= TH2)) ||
|
||||
((ant_b_report - ant_a_report >= TH1) && (ant_b_report - ant_a_report <= TH2))) {
|
||||
p_dm_swat_table->ANTA_ON = false;
|
||||
p_dm_swat_table->ANTB_ON = false;
|
||||
is_result = false;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection(): Need to check again\n"));
|
||||
} else {
|
||||
p_dm_swat_table->ANTA_ON = true;
|
||||
p_dm_swat_table->ANTB_ON = false;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection(): Single Antenna\n"));
|
||||
}
|
||||
p_dm_odm->ant_detected_info.is_ant_detected = true;
|
||||
p_dm_odm->ant_detected_info.db_for_ant_a = ant_a_report;
|
||||
p_dm_odm->ant_detected_info.db_for_ant_b = ant_b_report;
|
||||
p_dm_odm->ant_detected_info.db_for_ant_o = ant_0_report;
|
||||
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("return false!!\n"));
|
||||
is_result = false;
|
||||
}
|
||||
}
|
||||
return is_result;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* 1 [2. Scan AP RSSI method] ================================================== */
|
||||
|
||||
|
||||
|
||||
|
||||
bool
|
||||
odm_sw_ant_div_check_before_link(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
|
||||
#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
|
||||
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
PMGNT_INFO p_mgnt_info = &adapter->MgntInfo;
|
||||
struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table;
|
||||
struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table;
|
||||
s8 score = 0;
|
||||
PRT_WLAN_BSS p_tmp_bss_desc, p_test_bss_desc;
|
||||
u8 power_target_L = 9, power_target_H = 16;
|
||||
u8 tmp_power_diff = 0, power_diff = 0, avg_power_diff = 0, max_power_diff = 0, min_power_diff = 0xff;
|
||||
u16 index, counter = 0;
|
||||
static u8 scan_channel;
|
||||
u32 tmp_swas_no_link_bk_reg948;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n", p_dm_odm->dm_swat_table.ANTA_ON, p_dm_odm->dm_swat_table.ANTB_ON));
|
||||
|
||||
/* if(HP id) */
|
||||
{
|
||||
if (p_dm_odm->dm_swat_table.rssi_ant_dect_result == true && p_dm_odm->support_ic_type == ODM_RTL8723B) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("8723B RSSI-based Antenna Detection is done\n"));
|
||||
return false;
|
||||
}
|
||||
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8723B) {
|
||||
if (p_dm_swat_table->swas_no_link_bk_reg948 == 0xff)
|
||||
p_dm_swat_table->swas_no_link_bk_reg948 = odm_read_4byte(p_dm_odm, REG_S0_S1_PATH_SWITCH);
|
||||
}
|
||||
}
|
||||
|
||||
if (p_dm_odm->adapter == NULL) { /* For BSOD when plug/unplug fast. //By YJ,120413 */
|
||||
/* The ODM structure is not initialized. */
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */
|
||||
if (!IS_ANT_DETECT_SUPPORT_RSSI(adapter))
|
||||
return false;
|
||||
else
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Antenna Detection: RSSI method\n"));
|
||||
|
||||
/* Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. */
|
||||
odm_acquire_spin_lock(p_dm_odm, RT_RF_STATE_SPINLOCK);
|
||||
if (p_hal_data->eRFPowerState != eRfOn || p_mgnt_info->RFChangeInProgress || p_mgnt_info->bMediaConnect) {
|
||||
odm_release_spin_lock(p_dm_odm, RT_RF_STATE_SPINLOCK);
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
|
||||
("odm_sw_ant_div_check_before_link(): rf_change_in_progress(%x), e_rf_power_state(%x)\n",
|
||||
p_mgnt_info->RFChangeInProgress, p_hal_data->eRFPowerState));
|
||||
|
||||
p_dm_swat_table->swas_no_link_state = 0;
|
||||
|
||||
return false;
|
||||
} else
|
||||
odm_release_spin_lock(p_dm_odm, RT_RF_STATE_SPINLOCK);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->swas_no_link_state = %d\n", p_dm_swat_table->swas_no_link_state));
|
||||
/* 1 Run AntDiv mechanism "Before Link" part. */
|
||||
if (p_dm_swat_table->swas_no_link_state == 0) {
|
||||
/* 1 Prepare to do Scan again to check current antenna state. */
|
||||
|
||||
/* Set check state to next step. */
|
||||
p_dm_swat_table->swas_no_link_state = 1;
|
||||
|
||||
/* Copy Current Scan list. */
|
||||
p_mgnt_info->tmpNumBssDesc = p_mgnt_info->NumBssDesc;
|
||||
PlatformMoveMemory((void *)adapter->MgntInfo.tmpbssDesc, (void *)p_mgnt_info->bssDesc, sizeof(RT_WLAN_BSS) * MAX_BSS_DESC);
|
||||
|
||||
/* Go back to scan function again. */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link: Scan one more time\n"));
|
||||
p_mgnt_info->ScanStep = 0;
|
||||
p_mgnt_info->bScanAntDetect = true;
|
||||
scan_channel = odm_sw_ant_div_select_scan_chnl(adapter);
|
||||
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) {
|
||||
if (p_dm_fat_table->rx_idle_ant == MAIN_ANT)
|
||||
odm_update_rx_idle_ant(p_dm_odm, AUX_ANT);
|
||||
else
|
||||
odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT);
|
||||
if (scan_channel == 0) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
|
||||
("odm_sw_ant_div_check_before_link(): No AP List Avaiable, Using ant(%s)\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "AUX_ANT" : "MAIN_ANT"));
|
||||
|
||||
if (IS_5G_WIRELESS_MODE(p_mgnt_info->dot11CurrentWirelessMode)) {
|
||||
p_dm_swat_table->ant_5g = p_dm_fat_table->rx_idle_ant;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->ant_5g=%s\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
|
||||
} else {
|
||||
p_dm_swat_table->ant_2g = p_dm_fat_table->rx_idle_ant;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->ant_2g=%s\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
|
||||
("odm_sw_ant_div_check_before_link: Change to %s for testing.\n", ((p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")));
|
||||
} else if (p_dm_odm->support_ic_type & (ODM_RTL8723B)) {
|
||||
/*Switch Antenna to another one.*/
|
||||
|
||||
tmp_swas_no_link_bk_reg948 = odm_read_4byte(p_dm_odm, REG_S0_S1_PATH_SWITCH);
|
||||
|
||||
if ((p_dm_swat_table->cur_antenna == MAIN_ANT) && (tmp_swas_no_link_bk_reg948 == 0x200)) {
|
||||
odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);
|
||||
odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);
|
||||
p_dm_swat_table->cur_antenna = AUX_ANT;
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Reg[948]= (( %x )) was in wrong state\n", tmp_swas_no_link_bk_reg948));
|
||||
return false;
|
||||
}
|
||||
odm_stall_execution(10);
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link: Change to (( %s-ant)) for testing.\n", (p_dm_swat_table->cur_antenna == MAIN_ANT) ? "MAIN" : "AUX"));
|
||||
}
|
||||
|
||||
odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
|
||||
PlatformSetTimer(adapter, &p_mgnt_info->ScanTimer, 5);
|
||||
|
||||
return true;
|
||||
} else { /* p_dm_swat_table->swas_no_link_state == 1 */
|
||||
/* 1 ScanComple() is called after antenna swiched. */
|
||||
/* 1 Check scan result and determine which antenna is going */
|
||||
/* 1 to be used. */
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" tmp_num_bss_desc= (( %d ))\n", p_mgnt_info->tmpNumBssDesc)); /* debug for Dino */
|
||||
|
||||
for (index = 0; index < p_mgnt_info->tmpNumBssDesc; index++) {
|
||||
p_tmp_bss_desc = &(p_mgnt_info->tmpbssDesc[index]); /* Antenna 1 */
|
||||
p_test_bss_desc = &(p_mgnt_info->bssDesc[index]); /* Antenna 2 */
|
||||
|
||||
if (PlatformCompareMemory(p_test_bss_desc->bdBssIdBuf, p_tmp_bss_desc->bdBssIdBuf, 6) != 0) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): ERROR!! This shall not happen.\n"));
|
||||
continue;
|
||||
}
|
||||
|
||||
if (p_dm_odm->support_ic_type != ODM_RTL8723B) {
|
||||
if (p_tmp_bss_desc->ChannelNumber == scan_channel) {
|
||||
if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link: Compare scan entry: score++\n"));
|
||||
RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower));
|
||||
|
||||
score++;
|
||||
PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS));
|
||||
} else if (p_tmp_bss_desc->RecvSignalPower < p_test_bss_desc->RecvSignalPower) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link: Compare scan entry: score--\n"));
|
||||
RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower));
|
||||
score--;
|
||||
} else {
|
||||
if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp < 5000) {
|
||||
RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("The 2nd Antenna didn't get this AP\n\n"));
|
||||
}
|
||||
}
|
||||
}
|
||||
} else { /* 8723B */
|
||||
if (p_tmp_bss_desc->ChannelNumber == scan_channel) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("channel_number == scan_channel->(( %d ))\n", p_tmp_bss_desc->ChannelNumber));
|
||||
|
||||
if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) { /* Pow(Ant1) > Pow(Ant2) */
|
||||
counter++;
|
||||
tmp_power_diff = (u8)(p_tmp_bss_desc->RecvSignalPower - p_test_bss_desc->RecvSignalPower);
|
||||
power_diff = power_diff + tmp_power_diff;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower));
|
||||
ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), p_tmp_bss_desc->bdSsIdBuf);
|
||||
ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), p_tmp_bss_desc->bdSsIdBuf);
|
||||
|
||||
/* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d))\n", tmp_power_diff,max_power_diff,min_power_diff)); */
|
||||
if (tmp_power_diff > max_power_diff)
|
||||
max_power_diff = tmp_power_diff;
|
||||
if (tmp_power_diff < min_power_diff)
|
||||
min_power_diff = tmp_power_diff;
|
||||
/* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("max_power_diff: (( %d)),min_power_diff: (( %d))\n",max_power_diff,min_power_diff)); */
|
||||
|
||||
PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS));
|
||||
} else if (p_test_bss_desc->RecvSignalPower > p_tmp_bss_desc->RecvSignalPower) { /* Pow(Ant1) < Pow(Ant2) */
|
||||
counter++;
|
||||
tmp_power_diff = (u8)(p_test_bss_desc->RecvSignalPower - p_tmp_bss_desc->RecvSignalPower);
|
||||
power_diff = power_diff + tmp_power_diff;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower));
|
||||
ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), p_tmp_bss_desc->bdSsIdBuf);
|
||||
ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), p_tmp_bss_desc->bdSsIdBuf);
|
||||
if (tmp_power_diff > max_power_diff)
|
||||
max_power_diff = tmp_power_diff;
|
||||
if (tmp_power_diff < min_power_diff)
|
||||
min_power_diff = tmp_power_diff;
|
||||
} else { /* Pow(Ant1) = Pow(Ant2) */
|
||||
if (p_test_bss_desc->bdTstamp > p_tmp_bss_desc->bdTstamp) { /* Stamp(Ant1) < Stamp(Ant2) */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000));
|
||||
if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp > 5000) {
|
||||
counter++;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower));
|
||||
ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), p_tmp_bss_desc->bdSsIdBuf);
|
||||
ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), p_tmp_bss_desc->bdSsIdBuf);
|
||||
min_power_diff = 0;
|
||||
}
|
||||
} else
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Error !!!]: Time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) {
|
||||
if (p_mgnt_info->NumBssDesc != 0 && score < 0) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
|
||||
("odm_sw_ant_div_check_before_link(): Using ant(%s)\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
|
||||
("odm_sw_ant_div_check_before_link(): Remain ant(%s)\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "AUX_ANT" : "MAIN_ANT"));
|
||||
|
||||
if (p_dm_fat_table->rx_idle_ant == MAIN_ANT)
|
||||
odm_update_rx_idle_ant(p_dm_odm, AUX_ANT);
|
||||
else
|
||||
odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT);
|
||||
}
|
||||
|
||||
if (IS_5G_WIRELESS_MODE(p_mgnt_info->dot11CurrentWirelessMode)) {
|
||||
p_dm_swat_table->ant_5g = p_dm_fat_table->rx_idle_ant;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->ant_5g=%s\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
|
||||
} else {
|
||||
p_dm_swat_table->ant_2g = p_dm_fat_table->rx_idle_ant;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->ant_2g=%s\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
|
||||
}
|
||||
} else if (p_dm_odm->support_ic_type == ODM_RTL8723B) {
|
||||
if (counter == 0) {
|
||||
if (p_dm_odm->dm_swat_table.pre_aux_fail_detec == false) {
|
||||
p_dm_odm->dm_swat_table.pre_aux_fail_detec = true;
|
||||
p_dm_odm->dm_swat_table.rssi_ant_dect_result = false;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] -> Scan Target-channel again\n"));
|
||||
|
||||
/* 3 [ Scan again ] */
|
||||
odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
|
||||
PlatformSetTimer(adapter, &p_mgnt_info->ScanTimer, 5);
|
||||
return true;
|
||||
} else { /* pre_aux_fail_detec == true */
|
||||
/* 2 [ Single Antenna ] */
|
||||
p_dm_odm->dm_swat_table.pre_aux_fail_detec = false;
|
||||
p_dm_odm->dm_swat_table.rssi_ant_dect_result = true;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter=(( 0 )) , [[ Still cannot find any AP ]]\n"));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Single antenna\n"));
|
||||
}
|
||||
p_dm_odm->dm_swat_table.aux_fail_detec_counter++;
|
||||
} else {
|
||||
p_dm_odm->dm_swat_table.pre_aux_fail_detec = false;
|
||||
|
||||
if (counter == 3) {
|
||||
avg_power_diff = ((power_diff - max_power_diff - min_power_diff) >> 1) + ((max_power_diff + min_power_diff) >> 2);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff));
|
||||
} else if (counter >= 4) {
|
||||
avg_power_diff = (power_diff - max_power_diff - min_power_diff) / (counter - 2);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff));
|
||||
|
||||
} else { /* counter==1,2 */
|
||||
avg_power_diff = power_diff / counter;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("avg_power_diff: (( %d )) , counter: (( %d )) , power_diff: (( %d ))\n", avg_power_diff, counter, power_diff));
|
||||
}
|
||||
|
||||
/* 2 [ Retry ] */
|
||||
if ((avg_power_diff >= power_target_L) && (avg_power_diff <= power_target_H)) {
|
||||
p_dm_odm->dm_swat_table.retry_counter++;
|
||||
|
||||
if (p_dm_odm->dm_swat_table.retry_counter <= 3) {
|
||||
p_dm_odm->dm_swat_table.rssi_ant_dect_result = false;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Low confidence result ]] avg_power_diff= (( %d )) -> Scan Target-channel again ]]\n", avg_power_diff));
|
||||
|
||||
/* 3 [ Scan again ] */
|
||||
odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
|
||||
PlatformSetTimer(adapter, &p_mgnt_info->ScanTimer, 5);
|
||||
return true;
|
||||
} else {
|
||||
p_dm_odm->dm_swat_table.rssi_ant_dect_result = true;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Still Low confidence result ]] (( retry_counter > 3 ))\n"));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Single antenna\n"));
|
||||
}
|
||||
|
||||
}
|
||||
/* 2 [ Dual Antenna ] */
|
||||
else if ((p_mgnt_info->NumBssDesc != 0) && (avg_power_diff < power_target_L)) {
|
||||
p_dm_odm->dm_swat_table.rssi_ant_dect_result = true;
|
||||
if (p_dm_odm->dm_swat_table.ANTB_ON == false) {
|
||||
p_dm_odm->dm_swat_table.ANTA_ON = true;
|
||||
p_dm_odm->dm_swat_table.ANTB_ON = true;
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Dual antenna\n"));
|
||||
p_dm_odm->dm_swat_table.dual_ant_counter++;
|
||||
|
||||
/* set bt coexDM from 1ant coexDM to 2ant coexDM */
|
||||
BT_SetBtCoexAntNum(adapter, BT_COEX_ANT_TYPE_DETECTED, 2);
|
||||
|
||||
/* 3 [ Init antenna diversity ] */
|
||||
p_dm_odm->support_ability |= ODM_BB_ANT_DIV;
|
||||
odm_ant_div_init(p_dm_odm);
|
||||
}
|
||||
/* 2 [ Single Antenna ] */
|
||||
else if (avg_power_diff > power_target_H) {
|
||||
p_dm_odm->dm_swat_table.rssi_ant_dect_result = true;
|
||||
if (p_dm_odm->dm_swat_table.ANTB_ON == true) {
|
||||
p_dm_odm->dm_swat_table.ANTA_ON = true;
|
||||
p_dm_odm->dm_swat_table.ANTB_ON = false;
|
||||
/* bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 1); */
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Single antenna\n"));
|
||||
p_dm_odm->dm_swat_table.single_ant_counter++;
|
||||
}
|
||||
}
|
||||
/* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("is_result=(( %d ))\n",p_dm_odm->dm_swat_table.rssi_ant_dect_result)); */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dual_ant_counter = (( %d )), single_ant_counter = (( %d )) , retry_counter = (( %d )) , aux_fail_detec_counter = (( %d ))\n\n\n",
|
||||
p_dm_odm->dm_swat_table.dual_ant_counter, p_dm_odm->dm_swat_table.single_ant_counter, p_dm_odm->dm_swat_table.retry_counter, p_dm_odm->dm_swat_table.aux_fail_detec_counter));
|
||||
|
||||
/* 2 recover the antenna setting */
|
||||
|
||||
if (p_dm_odm->dm_swat_table.ANTB_ON == false)
|
||||
odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, 0xfff, (p_dm_swat_table->swas_no_link_bk_reg948));
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("is_result=(( %d )), Recover Reg[948]= (( %x )) \n\n", p_dm_odm->dm_swat_table.rssi_ant_dect_result, p_dm_swat_table->swas_no_link_bk_reg948));
|
||||
|
||||
|
||||
}
|
||||
|
||||
/* Check state reset to default and wait for next time. */
|
||||
p_dm_swat_table->swas_no_link_state = 0;
|
||||
p_mgnt_info->bScanAntDetect = false;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* 1 [3. PSD method] ========================================================== */
|
||||
|
||||
|
||||
|
||||
|
||||
u32
|
||||
odm_get_psd_data(
|
||||
void *p_dm_void,
|
||||
u16 point,
|
||||
u8 initial_gain)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u32 psd_report;
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, 0x808, 0x3FF, point);
|
||||
odm_set_bb_reg(p_dm_odm, 0x808, BIT(22), 1); /* Start PSD calculation, Reg808[22]=0->1 */
|
||||
odm_stall_execution(150);/* Wait for HW PSD report */
|
||||
odm_set_bb_reg(p_dm_odm, 0x808, BIT(22), 0);/* Stop PSD calculation, Reg808[22]=1->0 */
|
||||
psd_report = odm_get_bb_reg(p_dm_odm, 0x8B4, MASKDWORD) & 0x0000FFFF; /* Read PSD report, Reg8B4[15:0] */
|
||||
|
||||
psd_report = (u32)(odm_convert_to_db(psd_report)); /* +(u32)(initial_gain); */
|
||||
return psd_report;
|
||||
}
|
||||
|
||||
|
||||
|
||||
void
|
||||
odm_single_dual_antenna_detection_psd(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u32 channel_ori;
|
||||
u8 initial_gain = 0x36;
|
||||
u8 tone_idx;
|
||||
u8 tone_lenth_1 = 7, tone_lenth_2 = 4;
|
||||
u16 tone_idx_1[7] = {88, 104, 120, 8, 24, 40, 56};
|
||||
u16 tone_idx_2[4] = {8, 24, 40, 56};
|
||||
u32 psd_report_main[11] = {0}, psd_report_aux[11] = {0};
|
||||
/* u8 tone_lenth_1=4, tone_lenth_2=2; */
|
||||
/* u16 tone_idx_1[4]={88, 120, 24, 56}; */
|
||||
/* u16 tone_idx_2[2]={ 24, 56}; */
|
||||
/* u32 psd_report_main[6]={0}, psd_report_aux[6]={0}; */
|
||||
|
||||
u32 PSD_report_temp, max_psd_report_main = 0, max_psd_report_aux = 0;
|
||||
u32 PSD_power_threshold;
|
||||
u32 main_psd_result = 0, aux_psd_result = 0;
|
||||
u32 regc50, reg948, regb2c, regc14, reg908;
|
||||
u32 i = 0, test_num = 8;
|
||||
|
||||
|
||||
if (p_dm_odm->support_ic_type != ODM_RTL8723B)
|
||||
return;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection_psd()============>\n"));
|
||||
|
||||
/* 2 [ Backup Current RF/BB Settings ] */
|
||||
|
||||
channel_ori = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK);
|
||||
reg948 = odm_get_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, MASKDWORD);
|
||||
regb2c = odm_get_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, MASKDWORD);
|
||||
regc50 = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD);
|
||||
regc14 = odm_get_bb_reg(p_dm_odm, 0xc14, MASKDWORD);
|
||||
reg908 = odm_get_bb_reg(p_dm_odm, 0x908, MASKDWORD);
|
||||
|
||||
/* 2 [ setting for doing PSD function (CH4)] */
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_RFMOD, BIT(24), 0); /* disable whole CCK block */
|
||||
odm_write_1byte(p_dm_odm, REG_TXPAUSE, 0xFF); /* Turn off TX -> Pause TX Queue */
|
||||
odm_set_bb_reg(p_dm_odm, 0xC14, MASKDWORD, 0x0); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */
|
||||
|
||||
/* PHYTXON while loop */
|
||||
odm_set_bb_reg(p_dm_odm, 0x908, MASKDWORD, 0x803);
|
||||
while (odm_get_bb_reg(p_dm_odm, 0xdf4, BIT(6))) {
|
||||
i++;
|
||||
if (i > 1000000) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Wait in %s() more than %d times!\n", __FUNCTION__, i));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, 0xc50, 0x7f, initial_gain);
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH4 & 40M */
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pt */ /* Set PSD 128 ptss */
|
||||
odm_stall_execution(3000);
|
||||
|
||||
|
||||
/* 2 [ Doing PSD Function in (CH4)] */
|
||||
|
||||
/* Antenna A */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH4)\n"));
|
||||
odm_set_bb_reg(p_dm_odm, 0x948, 0xfff, 0x200);
|
||||
odm_stall_execution(10);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dbg\n"));
|
||||
for (i = 0; i < test_num; i++) {
|
||||
for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) {
|
||||
PSD_report_temp = odm_get_psd_data(p_dm_odm, tone_idx_1[tone_idx], initial_gain);
|
||||
/* if( PSD_report_temp>psd_report_main[tone_idx] ) */
|
||||
psd_report_main[tone_idx] += PSD_report_temp;
|
||||
}
|
||||
}
|
||||
/* Antenna B */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH4)\n"));
|
||||
odm_set_bb_reg(p_dm_odm, 0x948, 0xfff, 0x280);
|
||||
odm_stall_execution(10);
|
||||
for (i = 0; i < test_num; i++) {
|
||||
for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) {
|
||||
PSD_report_temp = odm_get_psd_data(p_dm_odm, tone_idx_1[tone_idx], initial_gain);
|
||||
/* if( PSD_report_temp>psd_report_aux[tone_idx] ) */
|
||||
psd_report_aux[tone_idx] += PSD_report_temp;
|
||||
}
|
||||
}
|
||||
/* 2 [ Doing PSD Function in (CH8)] */
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */
|
||||
odm_stall_execution(3000);
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, 0xc50, 0x7f, initial_gain);
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH8 & 40M */
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */
|
||||
odm_stall_execution(3000);
|
||||
|
||||
/* Antenna A */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH8)\n"));
|
||||
odm_set_bb_reg(p_dm_odm, 0x948, 0xfff, 0x200);
|
||||
odm_stall_execution(10);
|
||||
|
||||
for (i = 0; i < test_num; i++) {
|
||||
for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) {
|
||||
PSD_report_temp = odm_get_psd_data(p_dm_odm, tone_idx_2[tone_idx], initial_gain);
|
||||
/* if( PSD_report_temp>psd_report_main[tone_idx] ) */
|
||||
psd_report_main[tone_lenth_1 + tone_idx] += PSD_report_temp;
|
||||
}
|
||||
}
|
||||
|
||||
/* Antenna B */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH8)\n"));
|
||||
odm_set_bb_reg(p_dm_odm, 0x948, 0xfff, 0x280);
|
||||
odm_stall_execution(10);
|
||||
|
||||
for (i = 0; i < test_num; i++) {
|
||||
for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) {
|
||||
PSD_report_temp = odm_get_psd_data(p_dm_odm, tone_idx_2[tone_idx], initial_gain);
|
||||
/* if( PSD_report_temp>psd_report_aux[tone_idx] ) */
|
||||
psd_report_aux[tone_lenth_1 + tone_idx] += PSD_report_temp;
|
||||
}
|
||||
}
|
||||
|
||||
/* 2 [ Calculate Result ] */
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nMain PSD Result: (ALL)\n"));
|
||||
for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d,\n", (tone_idx + 1), psd_report_main[tone_idx]));
|
||||
main_psd_result += psd_report_main[tone_idx];
|
||||
if (psd_report_main[tone_idx] > max_psd_report_main)
|
||||
max_psd_report_main = psd_report_main[tone_idx];
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Main= (( %d ))\n", main_psd_result));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Main = (( %d ))\n", max_psd_report_main));
|
||||
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nAux PSD Result: (ALL)\n"));
|
||||
for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d,\n", (tone_idx + 1), psd_report_aux[tone_idx]));
|
||||
aux_psd_result += psd_report_aux[tone_idx];
|
||||
if (psd_report_aux[tone_idx] > max_psd_report_aux)
|
||||
max_psd_report_aux = psd_report_aux[tone_idx];
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Aux= (( %d ))\n", aux_psd_result));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Aux = (( %d ))\n\n", max_psd_report_aux));
|
||||
|
||||
/* main_psd_result=main_psd_result-max_psd_report_main; */
|
||||
/* aux_psd_result=aux_psd_result-max_psd_report_aux; */
|
||||
PSD_power_threshold = (main_psd_result * 7) >> 3;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Main_result, Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n", main_psd_result, aux_psd_result, PSD_power_threshold));
|
||||
|
||||
/* 3 [ Dual Antenna ] */
|
||||
if (aux_psd_result >= PSD_power_threshold) {
|
||||
if (p_dm_odm->dm_swat_table.ANTB_ON == false) {
|
||||
p_dm_odm->dm_swat_table.ANTA_ON = true;
|
||||
p_dm_odm->dm_swat_table.ANTB_ON = true;
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Dual antenna\n"));
|
||||
|
||||
/* set bt coexDM from 1ant coexDM to 2ant coexDM */
|
||||
/* bt_set_bt_coex_ant_num(p_adapter, BT_COEX_ANT_TYPE_DETECTED, 2); */
|
||||
|
||||
/* Init antenna diversity */
|
||||
p_dm_odm->support_ability |= ODM_BB_ANT_DIV;
|
||||
odm_ant_div_init(p_dm_odm);
|
||||
}
|
||||
/* 3 [ Single Antenna ] */
|
||||
else {
|
||||
if (p_dm_odm->dm_swat_table.ANTB_ON == true) {
|
||||
p_dm_odm->dm_swat_table.ANTA_ON = true;
|
||||
p_dm_odm->dm_swat_table.ANTB_ON = false;
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Single antenna\n"));
|
||||
}
|
||||
|
||||
/* 2 [ Recover all parameters ] */
|
||||
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, channel_ori);
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */
|
||||
odm_set_bb_reg(p_dm_odm, 0xc50, 0x7f, regc50);
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948);
|
||||
odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c);
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_RFMOD, BIT(24), 1); /* enable whole CCK block */
|
||||
odm_write_1byte(p_dm_odm, REG_TXPAUSE, 0x0); /* Turn on TX */ /* Resume TX Queue */
|
||||
odm_set_bb_reg(p_dm_odm, 0xC14, MASKDWORD, regc14); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA] */
|
||||
odm_set_bb_reg(p_dm_odm, 0x908, MASKDWORD, reg908);
|
||||
|
||||
return;
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
void
|
||||
odm_sw_ant_detect_init(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
#if (defined(CONFIG_ANT_DETECTION))
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table;
|
||||
|
||||
/* p_dm_swat_table->pre_antenna = MAIN_ANT; */
|
||||
/* p_dm_swat_table->cur_antenna = MAIN_ANT; */
|
||||
p_dm_swat_table->swas_no_link_state = 0;
|
||||
p_dm_swat_table->pre_aux_fail_detec = false;
|
||||
p_dm_swat_table->swas_no_link_bk_reg948 = 0xff;
|
||||
#endif
|
||||
}
|
||||
95
hal/phydm/phydm_antdect.h
Normal file
95
hal/phydm/phydm_antdect.h
Normal file
|
|
@ -0,0 +1,95 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMANTDECT_H__
|
||||
#define __PHYDMANTDECT_H__
|
||||
|
||||
#define ANTDECT_VERSION "2.1" /*2015.07.29 by YuChen*/
|
||||
|
||||
#if (defined(CONFIG_ANT_DETECTION))
|
||||
/* #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */
|
||||
/* ANT Test */
|
||||
#define ANTTESTALL 0x00 /*ant A or B will be Testing*/
|
||||
#define ANTTESTA 0x01 /*ant A will be Testing*/
|
||||
#define ANTTESTB 0x02 /*ant B will be testing*/
|
||||
|
||||
#define MAX_ANTENNA_DETECTION_CNT 10
|
||||
|
||||
|
||||
struct _ANT_DETECTED_INFO {
|
||||
bool is_ant_detected;
|
||||
u32 db_for_ant_a;
|
||||
u32 db_for_ant_b;
|
||||
u32 db_for_ant_o;
|
||||
};
|
||||
|
||||
|
||||
enum dm_swas_e {
|
||||
antenna_a = 1,
|
||||
antenna_b = 2,
|
||||
antenna_max = 3,
|
||||
};
|
||||
|
||||
|
||||
|
||||
/* 1 [1. Single Tone method] =================================================== */
|
||||
|
||||
|
||||
|
||||
void
|
||||
odm_single_dual_antenna_default_setting(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
bool
|
||||
odm_single_dual_antenna_detection(
|
||||
void *p_dm_void,
|
||||
u8 mode
|
||||
);
|
||||
|
||||
/* 1 [2. Scan AP RSSI method] ================================================== */
|
||||
|
||||
#define sw_ant_div_check_before_link odm_sw_ant_div_check_before_link
|
||||
|
||||
bool
|
||||
odm_sw_ant_div_check_before_link(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
/* 1 [3. PSD method] ========================================================== */
|
||||
|
||||
|
||||
void
|
||||
odm_single_dual_antenna_detection_psd(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
void
|
||||
odm_sw_ant_detect_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
|
||||
#endif
|
||||
5234
hal/phydm/phydm_antdiv.c
Normal file
5234
hal/phydm/phydm_antdiv.c
Normal file
File diff suppressed because it is too large
Load diff
632
hal/phydm/phydm_antdiv.h
Normal file
632
hal/phydm/phydm_antdiv.h
Normal file
|
|
@ -0,0 +1,632 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMANTDIV_H__
|
||||
#define __PHYDMANTDIV_H__
|
||||
|
||||
/*#define ANTDIV_VERSION "2.0" //2014.11.04*/
|
||||
/*#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/
|
||||
/*#define ANTDIV_VERSION "2.2" 2015.01.16 Dino*/
|
||||
/*#define ANTDIV_VERSION "3.1" 2015.07.29 YuChen, remove 92c 92d 8723a*/
|
||||
/*#define ANTDIV_VERSION "3.2" 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B*/
|
||||
/*#define ANTDIV_VERSION "3.3" 2015.08.12 Stanley. 8723B does not need to check the antenna is control by BT,
|
||||
because antenna diversity only works when BT is disable or radio off*/
|
||||
/*#define ANTDIV_VERSION "3.4" 2015.08.28 Dino 1.Add 8821A Smart Antenna 2. Add 8188F SW S0S1 Antenna Diversity*/
|
||||
/*#define ANTDIV_VERSION "3.5" 2015.10.07 Stanley Always check antenna detection result from BT-coex. for 8723B, not from PHYDM*/
|
||||
/*#define ANTDIV_VERSION "3.6"*/ /*2015.11.16 Stanley */
|
||||
/*#define ANTDIV_VERSION "3.7"*/ /*2015.11.20 Dino Add SmartAnt FAT Patch */
|
||||
/*#define ANTDIV_VERSION "3.8" 2015.12.21 Dino, Add SmartAnt dynamic training packet num */
|
||||
#define ANTDIV_VERSION "3.9" /*2016.01.05 Dino, Add SmartAnt cmd for converting single & two smtant, and add cmd for adjust truth table */
|
||||
|
||||
/* 1 ============================================================
|
||||
* 1 Definition
|
||||
* 1 ============================================================ */
|
||||
|
||||
#define ANTDIV_INIT 0xff
|
||||
#define MAIN_ANT 1 /*ant A or ant Main or S1*/
|
||||
#define AUX_ANT 2 /*AntB or ant Aux or S0*/
|
||||
#define MAX_ANT 3 /* 3 for AP using*/
|
||||
|
||||
#define ANT1_2G 0 /* = ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */
|
||||
#define ANT2_2G 1 /* = ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */
|
||||
/*smart antenna*/
|
||||
#define SUPPORT_RF_PATH_NUM 4
|
||||
#define SUPPORT_BEAM_PATTERN_NUM 4
|
||||
#define NUM_ANTENNA_8821A 2
|
||||
|
||||
#define NO_FIX_TX_ANT 0
|
||||
#define FIX_TX_AT_MAIN 1
|
||||
#define FIX_AUX_AT_MAIN 2
|
||||
|
||||
/* Antenna Diversty Control type */
|
||||
#define ODM_AUTO_ANT 0
|
||||
#define ODM_FIX_MAIN_ANT 1
|
||||
#define ODM_FIX_AUX_ANT 2
|
||||
|
||||
#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8195A)
|
||||
#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814B)
|
||||
#define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT)
|
||||
#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E | ODM_RTL8192E)
|
||||
#define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821 | ODM_RTL8822B)
|
||||
|
||||
#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8881A | ODM_RTL8188F | ODM_RTL8723D)
|
||||
#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C)
|
||||
|
||||
#define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E)
|
||||
|
||||
#define ODM_ANTDIV_2G BIT(0)
|
||||
#define ODM_ANTDIV_5G BIT(1)
|
||||
|
||||
#define ANTDIV_ON 1
|
||||
#define ANTDIV_OFF 0
|
||||
|
||||
#define FAT_ON 1
|
||||
#define FAT_OFF 0
|
||||
|
||||
#define TX_BY_DESC 1
|
||||
#define TX_BY_REG 0
|
||||
|
||||
#define RSSI_METHOD 0
|
||||
#define EVM_METHOD 1
|
||||
#define CRC32_METHOD 2
|
||||
|
||||
#define INIT_ANTDIV_TIMMER 0
|
||||
#define CANCEL_ANTDIV_TIMMER 1
|
||||
#define RELEASE_ANTDIV_TIMMER 2
|
||||
|
||||
#define CRC32_FAIL 1
|
||||
#define CRC32_OK 0
|
||||
|
||||
#define evm_rssi_th_high 25
|
||||
#define evm_rssi_th_low 20
|
||||
|
||||
#define NORMAL_STATE_MIAN 1
|
||||
#define NORMAL_STATE_AUX 2
|
||||
#define TRAINING_STATE 3
|
||||
|
||||
#define FORCE_RSSI_DIFF 10
|
||||
|
||||
#define CSI_ON 1
|
||||
#define CSI_OFF 0
|
||||
|
||||
#define DIVON_CSIOFF 1
|
||||
#define DIVOFF_CSION 2
|
||||
|
||||
#define BDC_DIV_TRAIN_STATE 0
|
||||
#define bdc_bfer_train_state 1
|
||||
#define BDC_DECISION_STATE 2
|
||||
#define BDC_BF_HOLD_STATE 3
|
||||
#define BDC_DIV_HOLD_STATE 4
|
||||
|
||||
#define BDC_MODE_1 1
|
||||
#define BDC_MODE_2 2
|
||||
#define BDC_MODE_3 3
|
||||
#define BDC_MODE_4 4
|
||||
#define BDC_MODE_NULL 0xff
|
||||
|
||||
/*SW S0S1 antenna diversity*/
|
||||
#define SWAW_STEP_INIT 0xff
|
||||
#define SWAW_STEP_PEEK 0
|
||||
#define SWAW_STEP_DETERMINE 1
|
||||
|
||||
#define RSSI_CHECK_RESET_PERIOD 10
|
||||
#define RSSI_CHECK_THRESHOLD 50
|
||||
|
||||
/*Hong Lin Smart antenna*/
|
||||
#define HL_SMTANT_2WIRE_DATA_LEN 24
|
||||
|
||||
/* 1 ============================================================
|
||||
* 1 structure
|
||||
* 1 ============================================================ */
|
||||
|
||||
|
||||
struct _sw_antenna_switch_ {
|
||||
u8 double_chk_flag; /*If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than check this antenna again*/
|
||||
u8 try_flag;
|
||||
s32 pre_rssi;
|
||||
u8 cur_antenna;
|
||||
u8 pre_antenna;
|
||||
u8 rssi_trying;
|
||||
u8 reset_idx;
|
||||
u8 train_time;
|
||||
u8 train_time_flag; /*base on RSSI difference between two antennas*/
|
||||
struct timer_list phydm_sw_antenna_switch_timer;
|
||||
u32 pkt_cnt_sw_ant_div_by_ctrl_frame;
|
||||
bool is_sw_ant_div_by_ctrl_frame;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#if USE_WORKITEM
|
||||
RT_WORK_ITEM phydm_sw_antenna_switch_workitem;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* AntDect (Before link Antenna Switch check) need to be moved*/
|
||||
u16 single_ant_counter;
|
||||
u16 dual_ant_counter;
|
||||
u16 aux_fail_detec_counter;
|
||||
u16 retry_counter;
|
||||
u8 swas_no_link_state;
|
||||
u32 swas_no_link_bk_reg948;
|
||||
bool ANTA_ON; /*To indicate ant A is or not*/
|
||||
bool ANTB_ON; /*To indicate ant B is on or not*/
|
||||
bool pre_aux_fail_detec;
|
||||
bool rssi_ant_dect_result;
|
||||
u8 ant_5g;
|
||||
u8 ant_2g;
|
||||
|
||||
|
||||
};
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
|
||||
struct _BF_DIV_COEX_ {
|
||||
bool w_bfer_client[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
bool w_bfee_client[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u32 MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u32 MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
|
||||
u8 bd_ccoex_type_wbfer;
|
||||
u8 num_txbfee_client;
|
||||
u8 num_txbfer_client;
|
||||
u8 bdc_try_counter;
|
||||
u8 bdc_hold_counter;
|
||||
u8 bdc_mode;
|
||||
u8 bdc_active_mode;
|
||||
u8 BDC_state;
|
||||
u8 bdc_rx_idle_update_counter;
|
||||
u8 num_client;
|
||||
u8 pre_num_client;
|
||||
u8 num_bf_tar;
|
||||
u8 num_div_tar;
|
||||
|
||||
bool is_all_div_sta_idle;
|
||||
bool is_all_bf_sta_idle;
|
||||
bool bdc_try_flag;
|
||||
bool BF_pass;
|
||||
bool DIV_pass;
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
|
||||
struct _SMART_ANTENNA_TRAINNING_ {
|
||||
u32 latch_time;
|
||||
bool pkt_skip_statistic_en;
|
||||
u32 fix_beam_pattern_en;
|
||||
u32 fix_training_num_en;
|
||||
u32 fix_beam_pattern_codeword;
|
||||
u32 update_beam_codeword;
|
||||
u32 ant_num; /*number of used smart beam antenna*/
|
||||
u32 ant_num_total;/*number of total smart beam antenna*/
|
||||
u32 first_train_ant; /*decide witch antenna to train first*/
|
||||
u32 rfu_codeword_table[4]; /*2G beam truth table*/
|
||||
u32 rfu_codeword_table_5g[4]; /*5G beam truth table*/
|
||||
u32 beam_patten_num_each_ant;/*number of beam can be switched in each antenna*/
|
||||
u32 data_codeword_bit_num;
|
||||
u8 per_beam_training_pkt_num;
|
||||
u8 decision_holding_period;
|
||||
u8 pkt_counter;
|
||||
u32 fast_training_beam_num;
|
||||
u32 pre_fast_training_beam_num;
|
||||
u32 pkt_rssi_pre[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];
|
||||
u8 beam_train_cnt[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];
|
||||
u8 beam_train_rssi_diff[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];
|
||||
u32 pkt_rssi_sum[8][SUPPORT_BEAM_PATTERN_NUM];
|
||||
u32 pkt_rssi_cnt[8][SUPPORT_BEAM_PATTERN_NUM];
|
||||
u32 rx_idle_beam[SUPPORT_RF_PATH_NUM];
|
||||
u32 pre_codeword;
|
||||
bool force_update_beam_en;
|
||||
u32 beacon_counter;
|
||||
u32 pre_beacon_counter;
|
||||
u8 update_beam_idx;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
RT_WORK_ITEM hl_smart_antenna_workitem;
|
||||
RT_WORK_ITEM hl_smart_antenna_decision_workitem;
|
||||
#endif
|
||||
|
||||
};
|
||||
#endif
|
||||
|
||||
struct _FAST_ANTENNA_TRAINNING_ {
|
||||
u8 bssid[6];
|
||||
u8 antsel_rx_keep_0;
|
||||
u8 antsel_rx_keep_1;
|
||||
u8 antsel_rx_keep_2;
|
||||
u8 antsel_rx_keep_3;
|
||||
u32 ant_sum_rssi[7];
|
||||
u32 ant_rssi_cnt[7];
|
||||
u32 ant_ave_rssi[7];
|
||||
u8 fat_state;
|
||||
u32 train_idx;
|
||||
u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u16 main_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u16 aux_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u16 main_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u16 aux_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u16 main_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u16 aux_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u16 main_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u16 aux_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u8 rx_idle_ant;
|
||||
u8 ant_div_on_off;
|
||||
bool is_become_linked;
|
||||
u32 min_max_rssi;
|
||||
u8 idx_ant_div_counter_2g;
|
||||
u8 idx_ant_div_counter_5g;
|
||||
u8 ant_div_2g_5g;
|
||||
|
||||
#ifdef ODM_EVM_ENHANCE_ANTDIV
|
||||
u32 main_ant_evm_sum[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u32 aux_ant_evm_sum[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u32 main_ant_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u32 aux_ant_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
bool EVM_method_enable;
|
||||
u8 target_ant_evm;
|
||||
u8 target_ant_crc32;
|
||||
u8 target_ant_enhance;
|
||||
u8 pre_target_ant_enhance;
|
||||
u16 main_mpdu_ok_cnt;
|
||||
u16 aux_mpdu_ok_cnt;
|
||||
|
||||
u32 crc32_ok_cnt;
|
||||
u32 crc32_fail_cnt;
|
||||
u32 main_crc32_ok_cnt;
|
||||
u32 aux_crc32_ok_cnt;
|
||||
u32 main_crc32_fail_cnt;
|
||||
u32 aux_crc32_fail_cnt;
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
u32 cck_ctrl_frame_cnt_main;
|
||||
u32 cck_ctrl_frame_cnt_aux;
|
||||
u32 ofdm_ctrl_frame_cnt_main;
|
||||
u32 ofdm_ctrl_frame_cnt_aux;
|
||||
u32 main_ant_ctrl_frame_sum;
|
||||
u32 aux_ant_ctrl_frame_sum;
|
||||
u32 main_ant_ctrl_frame_cnt;
|
||||
u32 aux_ant_ctrl_frame_cnt;
|
||||
#endif
|
||||
u8 b_fix_tx_ant;
|
||||
bool fix_ant_bfee;
|
||||
bool enable_ctrl_frame_antdiv;
|
||||
bool use_ctrl_frame_antdiv;
|
||||
u8 hw_antsw_occur;
|
||||
u8 *p_force_tx_ant_by_desc;
|
||||
u8 force_tx_ant_by_desc; /*A temp value, will hook to driver team's outer parameter later*/
|
||||
u8 *p_default_s0_s1;
|
||||
u8 default_s0_s1;
|
||||
};
|
||||
|
||||
|
||||
/* 1 ============================================================
|
||||
* 1 enumeration
|
||||
* 1 ============================================================ */
|
||||
|
||||
|
||||
|
||||
enum fat_state_e /*Fast antenna training*/
|
||||
{
|
||||
FAT_BEFORE_LINK_STATE = 0,
|
||||
FAT_PREPARE_STATE = 1,
|
||||
FAT_TRAINING_STATE = 2,
|
||||
FAT_DECISION_STATE = 3
|
||||
};
|
||||
|
||||
enum ant_div_type_e {
|
||||
NO_ANTDIV = 0xFF,
|
||||
CG_TRX_HW_ANTDIV = 0x01,
|
||||
CGCS_RX_HW_ANTDIV = 0x02,
|
||||
FIXED_HW_ANTDIV = 0x03,
|
||||
CG_TRX_SMART_ANTDIV = 0x04,
|
||||
CGCS_RX_SW_ANTDIV = 0x05,
|
||||
S0S1_SW_ANTDIV = 0x06, /*8723B intrnal switch S0 S1*/
|
||||
S0S1_TRX_HW_ANTDIV = 0x07, /*TRX S0S1 diversity for 8723D*/
|
||||
HL_SW_SMART_ANT_TYPE1 = 0x10 /*Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys, and each ant. is equipped with 4 antenna patterns*/
|
||||
};
|
||||
|
||||
|
||||
/* 1 ============================================================
|
||||
* 1 function prototype
|
||||
* 1 ============================================================ */
|
||||
|
||||
|
||||
void
|
||||
odm_stop_antenna_switch_dm(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_enable_antenna_diversity(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_set_ant_config(
|
||||
void *p_dm_void,
|
||||
u8 ant_setting /* 0=A, 1=B, 2=C, .... */
|
||||
);
|
||||
|
||||
|
||||
#define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link
|
||||
|
||||
void odm_sw_ant_div_rest_after_link(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
|
||||
|
||||
void
|
||||
phydm_antdiv_reset_statistic(
|
||||
void *p_dm_void,
|
||||
u32 macid
|
||||
);
|
||||
|
||||
void
|
||||
odm_update_rx_idle_ant(
|
||||
void *p_dm_void,
|
||||
u8 ant
|
||||
);
|
||||
|
||||
#if (RTL8723B_SUPPORT == 1)
|
||||
void
|
||||
odm_update_rx_idle_ant_8723b(
|
||||
void *p_dm_void,
|
||||
u8 ant,
|
||||
u32 default_ant,
|
||||
u32 optional_ant
|
||||
);
|
||||
#endif
|
||||
|
||||
#if (RTL8188F_SUPPORT == 1)
|
||||
void
|
||||
phydm_update_rx_idle_antenna_8188F(
|
||||
void *p_dm_void,
|
||||
u32 default_ant
|
||||
);
|
||||
#endif
|
||||
|
||||
#if (RTL8723D_SUPPORT == 1)
|
||||
|
||||
void
|
||||
phydm_set_tx_ant_pwr_8723d(
|
||||
void *p_dm_void,
|
||||
u8 ant
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void
|
||||
odm_sw_antdiv_callback(
|
||||
struct timer_list *p_timer
|
||||
);
|
||||
|
||||
void
|
||||
odm_sw_antdiv_workitem_callback(
|
||||
void *p_context
|
||||
);
|
||||
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
|
||||
void
|
||||
odm_sw_antdiv_workitem_callback(
|
||||
void *p_context
|
||||
);
|
||||
|
||||
void
|
||||
odm_sw_antdiv_callback(
|
||||
void *function_context
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
void
|
||||
odm_s0s1_sw_ant_div_by_ctrl_frame(
|
||||
void *p_dm_void,
|
||||
u8 step
|
||||
);
|
||||
|
||||
void
|
||||
odm_antsel_statistics_of_ctrl_frame(
|
||||
void *p_dm_void,
|
||||
u8 antsel_tr_mux,
|
||||
u32 rx_pwdb_all
|
||||
);
|
||||
|
||||
void
|
||||
odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(
|
||||
void *p_dm_void,
|
||||
void *p_phy_info_void,
|
||||
void *p_pkt_info_void
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef ODM_EVM_ENHANCE_ANTDIV
|
||||
void
|
||||
odm_evm_fast_ant_training_callback(
|
||||
void *p_dm_void
|
||||
);
|
||||
#endif
|
||||
|
||||
void
|
||||
odm_hw_ant_div(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
|
||||
void
|
||||
odm_fast_ant_training(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_fast_ant_training_callback(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_fast_ant_training_work_item_callback(
|
||||
void *p_dm_void
|
||||
);
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void
|
||||
phydm_beam_switch_workitem_callback(
|
||||
void *p_context
|
||||
);
|
||||
|
||||
void
|
||||
phydm_beam_decision_workitem_callback(
|
||||
void *p_context
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
void
|
||||
phydm_update_beam_pattern(
|
||||
void *p_dm_void,
|
||||
u32 codeword,
|
||||
u32 codeword_length
|
||||
);
|
||||
|
||||
void
|
||||
phydm_set_all_ant_same_beam_num(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_hl_smart_ant_debug(
|
||||
void *p_dm_void,
|
||||
u32 *const dm_value,
|
||||
u32 *_used,
|
||||
char *output,
|
||||
u32 *_out_len
|
||||
);
|
||||
|
||||
#endif/*#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/
|
||||
|
||||
void
|
||||
odm_ant_div_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_ant_div(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_antsel_statistics(
|
||||
void *p_dm_void,
|
||||
u8 antsel_tr_mux,
|
||||
u32 mac_id,
|
||||
u32 utility,
|
||||
u8 method,
|
||||
u8 is_cck_rate
|
||||
);
|
||||
|
||||
void
|
||||
odm_process_rssi_for_ant_div(
|
||||
void *p_dm_void,
|
||||
void *p_phy_info_void,
|
||||
void *p_pkt_info_void
|
||||
);
|
||||
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
void
|
||||
odm_set_tx_ant_by_tx_info(
|
||||
void *p_dm_void,
|
||||
u8 *p_desc,
|
||||
u8 mac_id
|
||||
);
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
|
||||
struct tx_desc; /*declared tx_desc here or compile error happened when enabled 8822B*/
|
||||
|
||||
void
|
||||
odm_set_tx_ant_by_tx_info(
|
||||
struct rtl8192cd_priv *priv,
|
||||
struct tx_desc *pdesc,
|
||||
unsigned short aid
|
||||
);
|
||||
|
||||
#if 1/*def def CONFIG_WLAN_HAL*/
|
||||
void
|
||||
odm_set_tx_ant_by_tx_info_hal(
|
||||
struct rtl8192cd_priv *priv,
|
||||
void *pdesc_data,
|
||||
u16 aid
|
||||
);
|
||||
#endif /*#ifdef CONFIG_WLAN_HAL*/
|
||||
#endif
|
||||
|
||||
|
||||
void
|
||||
odm_ant_div_config(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_ant_div_timers(
|
||||
void *p_dm_void,
|
||||
u8 state
|
||||
);
|
||||
|
||||
void
|
||||
phydm_antdiv_debug(
|
||||
void *p_dm_void,
|
||||
u32 *const dm_value,
|
||||
u32 *_used,
|
||||
char *output,
|
||||
u32 *_out_len
|
||||
);
|
||||
|
||||
#endif /*#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))*/
|
||||
|
||||
void
|
||||
odm_ant_div_reset(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_antenna_diversity_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_antenna_diversity(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
#endif /*#ifndef __ODMANTDIV_H__*/
|
||||
1880
hal/phydm/phydm_beamforming.c
Normal file
1880
hal/phydm/phydm_beamforming.c
Normal file
File diff suppressed because it is too large
Load diff
374
hal/phydm/phydm_beamforming.h
Normal file
374
hal/phydm/phydm_beamforming.h
Normal file
|
|
@ -0,0 +1,374 @@
|
|||
#ifndef __INC_PHYDM_BEAMFORMING_H
|
||||
#define __INC_PHYDM_BEAMFORMING_H
|
||||
|
||||
#ifndef BEAMFORMING_SUPPORT
|
||||
#define BEAMFORMING_SUPPORT 0
|
||||
#endif
|
||||
|
||||
/*Beamforming Related*/
|
||||
#include "txbf/halcomtxbf.h"
|
||||
#include "txbf/haltxbfjaguar.h"
|
||||
#include "txbf/haltxbf8192e.h"
|
||||
#include "txbf/haltxbf8814a.h"
|
||||
#include "txbf/haltxbf8822b.h"
|
||||
#include "txbf/haltxbfinterface.h"
|
||||
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
|
||||
#define eq_mac_addr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 )
|
||||
#define cp_mac_addr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5])
|
||||
|
||||
#endif
|
||||
|
||||
#define MAX_BEAMFORMEE_SU 2
|
||||
#define MAX_BEAMFORMER_SU 2
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
#define MAX_BEAMFORMEE_MU 6
|
||||
#define MAX_BEAMFORMER_MU 1
|
||||
#else
|
||||
#define MAX_BEAMFORMEE_MU 0
|
||||
#define MAX_BEAMFORMER_MU 0
|
||||
#endif
|
||||
|
||||
#define BEAMFORMEE_ENTRY_NUM (MAX_BEAMFORMEE_SU + MAX_BEAMFORMEE_MU)
|
||||
#define BEAMFORMER_ENTRY_NUM (MAX_BEAMFORMER_SU + MAX_BEAMFORMER_MU)
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
/*for different naming between WIN and CE*/
|
||||
#define BEACON_QUEUE BCN_QUEUE_INX
|
||||
#define NORMAL_QUEUE MGT_QUEUE_INX
|
||||
#define RT_DISABLE_FUNC RTW_DISABLE_FUNC
|
||||
#define RT_ENABLE_FUNC RTW_ENABLE_FUNC
|
||||
#endif
|
||||
|
||||
enum beamforming_entry_state {
|
||||
BEAMFORMING_ENTRY_STATE_UNINITIALIZE,
|
||||
BEAMFORMING_ENTRY_STATE_INITIALIZEING,
|
||||
BEAMFORMING_ENTRY_STATE_INITIALIZED,
|
||||
BEAMFORMING_ENTRY_STATE_PROGRESSING,
|
||||
BEAMFORMING_ENTRY_STATE_PROGRESSED
|
||||
};
|
||||
|
||||
|
||||
enum beamforming_notify_state {
|
||||
BEAMFORMING_NOTIFY_NONE,
|
||||
BEAMFORMING_NOTIFY_ADD,
|
||||
BEAMFORMING_NOTIFY_DELETE,
|
||||
BEAMFORMEE_NOTIFY_ADD_SU,
|
||||
BEAMFORMEE_NOTIFY_DELETE_SU,
|
||||
BEAMFORMEE_NOTIFY_ADD_MU,
|
||||
BEAMFORMEE_NOTIFY_DELETE_MU,
|
||||
BEAMFORMING_NOTIFY_RESET
|
||||
};
|
||||
|
||||
enum beamforming_cap {
|
||||
BEAMFORMING_CAP_NONE = 0x0,
|
||||
BEAMFORMER_CAP_HT_EXPLICIT = BIT(1),
|
||||
BEAMFORMEE_CAP_HT_EXPLICIT = BIT(2),
|
||||
BEAMFORMER_CAP_VHT_SU = BIT(5), /* Self has er Cap, because Reg er & peer ee */
|
||||
BEAMFORMEE_CAP_VHT_SU = BIT(6), /* Self has ee Cap, because Reg ee & peer er */
|
||||
BEAMFORMER_CAP_VHT_MU = BIT(7), /* Self has er Cap, because Reg er & peer ee */
|
||||
BEAMFORMEE_CAP_VHT_MU = BIT(8), /* Self has ee Cap, because Reg ee & peer er */
|
||||
BEAMFORMER_CAP = BIT(9),
|
||||
BEAMFORMEE_CAP = BIT(10),
|
||||
};
|
||||
|
||||
|
||||
enum sounding_mode {
|
||||
SOUNDING_SW_VHT_TIMER = 0x0,
|
||||
SOUNDING_SW_HT_TIMER = 0x1,
|
||||
sounding_stop_all_timer = 0x2,
|
||||
SOUNDING_HW_VHT_TIMER = 0x3,
|
||||
SOUNDING_HW_HT_TIMER = 0x4,
|
||||
SOUNDING_STOP_OID_TIMER = 0x5,
|
||||
SOUNDING_AUTO_VHT_TIMER = 0x6,
|
||||
SOUNDING_AUTO_HT_TIMER = 0x7,
|
||||
SOUNDING_FW_VHT_TIMER = 0x8,
|
||||
SOUNDING_FW_HT_TIMER = 0x9,
|
||||
};
|
||||
|
||||
struct _RT_BEAMFORM_STAINFO {
|
||||
u8 *ra;
|
||||
u16 aid;
|
||||
u16 mac_id;
|
||||
u8 my_mac_addr[6];
|
||||
WIRELESS_MODE wireless_mode;
|
||||
CHANNEL_WIDTH bw;
|
||||
enum beamforming_cap beamform_cap;
|
||||
u8 ht_beamform_cap;
|
||||
u16 vht_beamform_cap;
|
||||
u8 cur_beamform;
|
||||
u16 cur_beamform_vht;
|
||||
};
|
||||
|
||||
|
||||
struct _RT_BEAMFORMEE_ENTRY {
|
||||
bool is_used;
|
||||
bool is_txbf;
|
||||
bool is_sound;
|
||||
u16 aid; /*Used to construct AID field of NDPA packet.*/
|
||||
u16 mac_id; /*Used to Set Reg42C in IBSS mode. */
|
||||
u16 p_aid; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
|
||||
u16 g_id; /*Used to fill Tx DESC*/
|
||||
u8 my_mac_addr[6];
|
||||
u8 mac_addr[6]; /*Used to fill Reg6E4 to fill Mac address of CSI report frame.*/
|
||||
CHANNEL_WIDTH sound_bw; /*Sounding band_width*/
|
||||
u16 sound_period;
|
||||
enum beamforming_cap beamform_entry_cap;
|
||||
enum beamforming_entry_state beamform_entry_state;
|
||||
bool is_beamforming_in_progress;
|
||||
/*u8 log_seq; // Move to _RT_BEAMFORMER_ENTRY*/
|
||||
/*u16 log_retry_cnt:3; // 0~4 // Move to _RT_BEAMFORMER_ENTRY*/
|
||||
/*u16 LogSuccessCnt:2; // 0~2 // Move to _RT_BEAMFORMER_ENTRY*/
|
||||
u16 log_status_fail_cnt:5; /* 0~21 */
|
||||
u16 default_csi_cnt:5; /* 0~21 */
|
||||
u8 csi_matrix[327];
|
||||
u16 csi_matrix_len;
|
||||
u8 num_of_sounding_dim;
|
||||
u8 comp_steering_num_of_bfer;
|
||||
u8 su_reg_index;
|
||||
/*For MU-MIMO*/
|
||||
bool is_mu_sta;
|
||||
u8 mu_reg_index;
|
||||
u8 gid_valid[8];
|
||||
u8 user_position[16];
|
||||
};
|
||||
|
||||
struct _RT_BEAMFORMER_ENTRY {
|
||||
bool is_used;
|
||||
/*P_AID of BFer entry is probably not used*/
|
||||
u16 p_aid; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
|
||||
u16 g_id;
|
||||
u8 my_mac_addr[6];
|
||||
u8 mac_addr[6];
|
||||
enum beamforming_cap beamform_entry_cap;
|
||||
u8 num_of_sounding_dim;
|
||||
u8 clock_reset_times; /*Modified by Jeffery @2015-04-10*/
|
||||
u8 pre_log_seq; /*Modified by Jeffery @2015-03-30*/
|
||||
u8 log_seq; /*Modified by Jeffery @2014-10-29*/
|
||||
u16 log_retry_cnt:3; /*Modified by Jeffery @2014-10-29*/
|
||||
u16 log_success:2; /*Modified by Jeffery @2014-10-29*/
|
||||
u8 su_reg_index;
|
||||
/*For MU-MIMO*/
|
||||
bool is_mu_ap;
|
||||
u8 gid_valid[8];
|
||||
u8 user_position[16];
|
||||
u16 aid;
|
||||
};
|
||||
|
||||
struct _RT_SOUNDING_INFO {
|
||||
u8 sound_idx;
|
||||
CHANNEL_WIDTH sound_bw;
|
||||
enum sounding_mode sound_mode;
|
||||
u16 sound_period;
|
||||
};
|
||||
|
||||
|
||||
|
||||
struct _RT_BEAMFORMING_OID_INFO {
|
||||
u8 sound_oid_idx;
|
||||
CHANNEL_WIDTH sound_oid_bw;
|
||||
enum sounding_mode sound_oid_mode;
|
||||
u16 sound_oid_period;
|
||||
};
|
||||
|
||||
|
||||
struct _RT_BEAMFORMING_INFO {
|
||||
enum beamforming_cap beamform_cap;
|
||||
struct _RT_BEAMFORMEE_ENTRY beamformee_entry[BEAMFORMEE_ENTRY_NUM];
|
||||
struct _RT_BEAMFORMER_ENTRY beamformer_entry[BEAMFORMER_ENTRY_NUM];
|
||||
struct _RT_BEAMFORM_STAINFO beamform_sta_info;
|
||||
u8 beamformee_cur_idx;
|
||||
struct timer_list beamforming_timer;
|
||||
struct timer_list mu_timer;
|
||||
struct _RT_SOUNDING_INFO sounding_info;
|
||||
struct _RT_BEAMFORMING_OID_INFO beamforming_oid_info;
|
||||
struct _HAL_TXBF_INFO txbf_info;
|
||||
u8 sounding_sequence;
|
||||
u8 beamformee_su_cnt;
|
||||
u8 beamformer_su_cnt;
|
||||
u32 beamformee_su_reg_maping;
|
||||
u32 beamformer_su_reg_maping;
|
||||
/*For MU-MINO*/
|
||||
u8 beamformee_mu_cnt;
|
||||
u8 beamformer_mu_cnt;
|
||||
u32 beamformee_mu_reg_maping;
|
||||
u8 mu_ap_index;
|
||||
bool is_mu_sounding;
|
||||
u8 first_mu_bfee_index;
|
||||
bool is_mu_sounding_in_progress;
|
||||
bool dbg_disable_mu_tx;
|
||||
bool apply_v_matrix;
|
||||
bool snding3ss;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *source_adapter;
|
||||
#endif
|
||||
/* Control register */
|
||||
u32 reg_mu_tx_ctrl; /* For USB/SDIO interfaces aync I/O */
|
||||
};
|
||||
|
||||
|
||||
struct _RT_NDPA_STA_INFO {
|
||||
u16 aid:12;
|
||||
u16 feedback_type:1;
|
||||
u16 nc_index:3;
|
||||
};
|
||||
|
||||
enum phydm_acting_type {
|
||||
phydm_acting_as_ibss = 0,
|
||||
phydm_acting_as_ap = 1
|
||||
};
|
||||
|
||||
|
||||
enum beamforming_cap
|
||||
phydm_beamforming_get_entry_beam_cap_by_mac_id(
|
||||
void *p_dm_void,
|
||||
u8 mac_id
|
||||
);
|
||||
|
||||
struct _RT_BEAMFORMEE_ENTRY *
|
||||
phydm_beamforming_get_bfee_entry_by_addr(
|
||||
void *p_dm_void,
|
||||
u8 *RA,
|
||||
u8 *idx
|
||||
);
|
||||
|
||||
struct _RT_BEAMFORMER_ENTRY *
|
||||
phydm_beamforming_get_bfer_entry_by_addr(
|
||||
void *p_dm_void,
|
||||
u8 *TA,
|
||||
u8 *idx
|
||||
);
|
||||
|
||||
void
|
||||
phydm_beamforming_notify(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
bool
|
||||
phydm_acting_determine(
|
||||
void *p_dm_void,
|
||||
enum phydm_acting_type type
|
||||
);
|
||||
|
||||
void
|
||||
beamforming_enter(
|
||||
void *p_dm_void,
|
||||
u16 sta_idx
|
||||
);
|
||||
|
||||
void
|
||||
beamforming_leave(
|
||||
void *p_dm_void,
|
||||
u8 *RA
|
||||
);
|
||||
|
||||
bool
|
||||
beamforming_start_fw(
|
||||
void *p_dm_void,
|
||||
u8 idx
|
||||
);
|
||||
|
||||
void
|
||||
beamforming_check_sounding_success(
|
||||
void *p_dm_void,
|
||||
bool status
|
||||
);
|
||||
|
||||
void
|
||||
phydm_beamforming_end_sw(
|
||||
void *p_dm_void,
|
||||
bool status
|
||||
);
|
||||
|
||||
void
|
||||
beamforming_timer_callback(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_beamforming_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
|
||||
|
||||
enum beamforming_cap
|
||||
phydm_beamforming_get_beam_cap(
|
||||
void *p_dm_void,
|
||||
struct _RT_BEAMFORMING_INFO *p_beam_info
|
||||
);
|
||||
|
||||
|
||||
bool
|
||||
beamforming_control_v1(
|
||||
void *p_dm_void,
|
||||
u8 *RA,
|
||||
u8 AID,
|
||||
u8 mode,
|
||||
CHANNEL_WIDTH BW,
|
||||
u8 rate
|
||||
);
|
||||
|
||||
|
||||
bool
|
||||
phydm_beamforming_control_v2(
|
||||
void *p_dm_void,
|
||||
u8 idx,
|
||||
u8 mode,
|
||||
CHANNEL_WIDTH BW,
|
||||
u16 period
|
||||
);
|
||||
|
||||
void
|
||||
phydm_beamforming_watchdog(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
beamforming_sw_timer_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct timer_list *p_timer
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
void *function_context
|
||||
#endif
|
||||
);
|
||||
|
||||
bool
|
||||
beamforming_send_ht_ndpa_packet(
|
||||
void *p_dm_void,
|
||||
u8 *RA,
|
||||
CHANNEL_WIDTH BW,
|
||||
u8 q_idx
|
||||
);
|
||||
|
||||
|
||||
bool
|
||||
beamforming_send_vht_ndpa_packet(
|
||||
void *p_dm_void,
|
||||
u8 *RA,
|
||||
u16 AID,
|
||||
CHANNEL_WIDTH BW,
|
||||
u8 q_idx
|
||||
);
|
||||
|
||||
#else
|
||||
#define beamforming_gid_paid(adapter, p_tcb)
|
||||
#define phydm_acting_determine(p_dm_odm, type) false
|
||||
#define beamforming_enter(p_dm_odm, sta_idx)
|
||||
#define beamforming_leave(p_dm_odm, RA)
|
||||
#define beamforming_end_fw(p_dm_odm)
|
||||
#define beamforming_control_v1(p_dm_odm, RA, AID, mode, BW, rate) true
|
||||
#define beamforming_control_v2(p_dm_odm, idx, mode, BW, period) true
|
||||
#define phydm_beamforming_end_sw(p_dm_odm, _status)
|
||||
#define beamforming_timer_callback(p_dm_odm)
|
||||
#define phydm_beamforming_init(p_dm_odm)
|
||||
#define phydm_beamforming_control_v2(p_dm_odm, _idx, _mode, _BW, _period) false
|
||||
#define beamforming_watchdog(p_dm_odm)
|
||||
#define phydm_beamforming_watchdog(p_dm_odm)
|
||||
|
||||
|
||||
#endif
|
||||
#endif
|
||||
392
hal/phydm/phydm_ccx.c
Normal file
392
hal/phydm/phydm_ccx.c
Normal file
|
|
@ -0,0 +1,392 @@
|
|||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
/*Set NHM period, threshold, disable ignore cca or not, disable ignore txon or not*/
|
||||
void
|
||||
phydm_nhm_setting(
|
||||
void *p_dm_void,
|
||||
u8 nhm_setting
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info;
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
|
||||
|
||||
if (nhm_setting == SET_NHM_SETTING) {
|
||||
|
||||
/*Set inexclude_cca, inexclude_txon*/
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9), ccx_info->nhm_inexclude_cca);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10), ccx_info->nhm_inexclude_txon);
|
||||
|
||||
/*Set NHM period*/
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD, ccx_info->NHM_period);
|
||||
|
||||
/*Set NHM threshold*/
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0, ccx_info->NHM_th[0]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1, ccx_info->NHM_th[1]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2, ccx_info->NHM_th[2]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3, ccx_info->NHM_th[3]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0, ccx_info->NHM_th[4]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1, ccx_info->NHM_th[5]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2, ccx_info->NHM_th[6]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3, ccx_info->NHM_th[7]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, ccx_info->NHM_th[8]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2, ccx_info->NHM_th[9]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3, ccx_info->NHM_th[10]);
|
||||
|
||||
/*CCX EN*/
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8), CCX_EN);
|
||||
|
||||
} else if (nhm_setting == STORE_NHM_SETTING) {
|
||||
|
||||
/*Store pervious disable_ignore_cca, disable_ignore_txon*/
|
||||
ccx_info->NHM_inexclude_cca_restore = (enum nhm_inexclude_cca)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9));
|
||||
ccx_info->NHM_inexclude_txon_restore = (enum nhm_inexclude_txon)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10));
|
||||
|
||||
/*Store pervious NHM period*/
|
||||
ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD);
|
||||
|
||||
/*Store NHM threshold*/
|
||||
ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0);
|
||||
ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1);
|
||||
ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2);
|
||||
ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3);
|
||||
ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0);
|
||||
ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1);
|
||||
ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2);
|
||||
ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3);
|
||||
ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0);
|
||||
ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2);
|
||||
ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3);
|
||||
} else if (nhm_setting == RESTORE_NHM_SETTING) {
|
||||
|
||||
/*Set disable_ignore_cca, disable_ignore_txon*/
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9), ccx_info->NHM_inexclude_cca_restore);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10), ccx_info->NHM_inexclude_txon_restore);
|
||||
|
||||
/*Set NHM period*/
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD, ccx_info->NHM_period);
|
||||
|
||||
/*Set NHM threshold*/
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0, ccx_info->NHM_th_restore[0]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1, ccx_info->NHM_th_restore[1]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2, ccx_info->NHM_th_restore[2]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3, ccx_info->NHM_th_restore[3]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0, ccx_info->NHM_th_restore[4]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1, ccx_info->NHM_th_restore[5]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2, ccx_info->NHM_th_restore[6]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3, ccx_info->NHM_th_restore[7]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, ccx_info->NHM_th_restore[8]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2, ccx_info->NHM_th_restore[9]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3, ccx_info->NHM_th_restore[10]);
|
||||
} else
|
||||
return;
|
||||
}
|
||||
|
||||
else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
|
||||
|
||||
if (nhm_setting == SET_NHM_SETTING) {
|
||||
|
||||
/*Set disable_ignore_cca, disable_ignore_txon*/
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(9), ccx_info->nhm_inexclude_cca);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10), ccx_info->nhm_inexclude_txon);
|
||||
|
||||
/*Set NHM period*/
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKHWORD, ccx_info->NHM_period);
|
||||
|
||||
/*Set NHM threshold*/
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0, ccx_info->NHM_th[0]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1, ccx_info->NHM_th[1]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2, ccx_info->NHM_th[2]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3, ccx_info->NHM_th[3]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0, ccx_info->NHM_th[4]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1, ccx_info->NHM_th[5]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2, ccx_info->NHM_th[6]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3, ccx_info->NHM_th[7]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11N, MASKBYTE0, ccx_info->NHM_th[8]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2, ccx_info->NHM_th[9]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3, ccx_info->NHM_th[10]);
|
||||
|
||||
/*CCX EN*/
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(8), CCX_EN);
|
||||
} else if (nhm_setting == STORE_NHM_SETTING) {
|
||||
|
||||
/*Store pervious disable_ignore_cca, disable_ignore_txon*/
|
||||
ccx_info->NHM_inexclude_cca_restore = (enum nhm_inexclude_cca)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(9));
|
||||
ccx_info->NHM_inexclude_txon_restore = (enum nhm_inexclude_txon)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10));
|
||||
|
||||
/*Store pervious NHM period*/
|
||||
ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKHWORD);
|
||||
|
||||
/*Store NHM threshold*/
|
||||
ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0);
|
||||
ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1);
|
||||
ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2);
|
||||
ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3);
|
||||
ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0);
|
||||
ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1);
|
||||
ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2);
|
||||
ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3);
|
||||
ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11N, MASKBYTE0);
|
||||
ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2);
|
||||
ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3);
|
||||
|
||||
} else if (nhm_setting == RESTORE_NHM_SETTING) {
|
||||
|
||||
/*Set disable_ignore_cca, disable_ignore_txon*/
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(9), ccx_info->NHM_inexclude_cca_restore);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10), ccx_info->NHM_inexclude_txon_restore);
|
||||
|
||||
/*Set NHM period*/
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKHWORD, ccx_info->NHM_period_restore);
|
||||
|
||||
/*Set NHM threshold*/
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0, ccx_info->NHM_th_restore[0]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1, ccx_info->NHM_th_restore[1]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2, ccx_info->NHM_th_restore[2]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3, ccx_info->NHM_th_restore[3]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0, ccx_info->NHM_th_restore[4]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1, ccx_info->NHM_th_restore[5]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2, ccx_info->NHM_th_restore[6]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3, ccx_info->NHM_th_restore[7]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11N, MASKBYTE0, ccx_info->NHM_th_restore[8]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2, ccx_info->NHM_th_restore[9]);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3, ccx_info->NHM_th_restore[10]);
|
||||
} else
|
||||
return;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
phydm_nhm_trigger(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info;
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
|
||||
|
||||
/*Trigger NHM*/
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 0);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 1);
|
||||
} else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
|
||||
|
||||
/*Trigger NHM*/
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 0);
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 1);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
phydm_get_nhm_result(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u32 value32;
|
||||
struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info;
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
|
||||
|
||||
value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11AC);
|
||||
ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0);
|
||||
ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8);
|
||||
ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16);
|
||||
ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24);
|
||||
|
||||
value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11AC);
|
||||
ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0);
|
||||
ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8);
|
||||
ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16);
|
||||
ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24);
|
||||
|
||||
value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT11_TO_CNT8_11AC);
|
||||
ccx_info->NHM_result[8] = (u8)(value32 & MASKBYTE0);
|
||||
ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE1) >> 8);
|
||||
ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16);
|
||||
ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24);
|
||||
|
||||
/*Get NHM duration*/
|
||||
value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_DUR_READY_11AC);
|
||||
ccx_info->NHM_duration = (u16)(value32 & MASKLWORD);
|
||||
|
||||
}
|
||||
|
||||
else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
|
||||
|
||||
value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11N);
|
||||
ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0);
|
||||
ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8);
|
||||
ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16);
|
||||
ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24);
|
||||
|
||||
value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11N);
|
||||
ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0);
|
||||
ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8);
|
||||
ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16);
|
||||
ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24);
|
||||
|
||||
value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT9_TO_CNT8_11N);
|
||||
ccx_info->NHM_result[8] = (u8)((value32 & MASKBYTE2) >> 16);
|
||||
ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE3) >> 24);
|
||||
|
||||
value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT10_TO_CNT11_11N);
|
||||
ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16);
|
||||
ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24);
|
||||
|
||||
/*Get NHM duration*/
|
||||
value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT10_TO_CNT11_11N);
|
||||
ccx_info->NHM_duration = (u16)(value32 & MASKLWORD);
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
bool
|
||||
phydm_check_nhm_ready(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u32 value32 = 0;
|
||||
u8 i;
|
||||
bool ret = false;
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
|
||||
|
||||
value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11AC, MASKDWORD);
|
||||
|
||||
for (i = 0; i < 200; i++) {
|
||||
|
||||
ODM_delay_ms(1);
|
||||
if (odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_DUR_READY_11AC, BIT(17))) {
|
||||
ret = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
|
||||
|
||||
value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_READY_11N, MASKDWORD);
|
||||
|
||||
for (i = 0; i < 200; i++) {
|
||||
|
||||
ODM_delay_ms(1);
|
||||
if (odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_DUR_READY_11AC, BIT(17))) {
|
||||
ret = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
void
|
||||
phydm_store_nhm_setting(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info;
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
|
||||
|
||||
|
||||
} else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
|
||||
|
||||
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
phydm_clm_setting(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info;
|
||||
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKLWORD, ccx_info->CLM_period); /*4us sample 1 time*/
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11AC, BIT(8), 0x1); /*Enable CCX for CLM*/
|
||||
|
||||
} else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKLWORD, ccx_info->CLM_period); /*4us sample 1 time*/
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11N, BIT(8), 0x1); /*Enable CCX for CLM*/
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM period = %dus\n", __func__, ccx_info->CLM_period * 4));
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
phydm_clm_trigger(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) {
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11AC, BIT(0), 0x0); /*Trigger CLM*/
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11AC, BIT(0), 0x1);
|
||||
} else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11N, BIT(0), 0x0); /*Trigger CLM*/
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11N, BIT(0), 0x1);
|
||||
}
|
||||
}
|
||||
|
||||
bool
|
||||
phydm_check_cl_mready(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u32 value32 = 0;
|
||||
bool ret = false;
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)
|
||||
value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11AC, MASKDWORD); /*make sure CLM calc is ready*/
|
||||
else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)
|
||||
value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_READY_11N, MASKDWORD); /*make sure CLM calc is ready*/
|
||||
|
||||
if ((p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) && (value32 & BIT(16)))
|
||||
ret = true;
|
||||
else if ((p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) && (value32 & BIT(16)))
|
||||
ret = true;
|
||||
else
|
||||
ret = false;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM ready = %d\n", __func__, ret));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void
|
||||
phydm_get_cl_mresult(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info;
|
||||
|
||||
u32 value32 = 0;
|
||||
u16 results = 0;
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)
|
||||
value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11AC, MASKDWORD); /*read CLM calc result*/
|
||||
else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)
|
||||
value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11N, MASKDWORD); /*read CLM calc result*/
|
||||
|
||||
ccx_info->CLM_result = (u16)(value32 & MASKLWORD);
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM result = %dus\n", __func__, ccx_info->CLM_result * 4));
|
||||
|
||||
}
|
||||
102
hal/phydm/phydm_ccx.h
Normal file
102
hal/phydm/phydm_ccx.h
Normal file
|
|
@ -0,0 +1,102 @@
|
|||
#ifndef __PHYDMCCX_H__
|
||||
#define __PHYDMCCX_H__
|
||||
|
||||
#define CCX_EN 1
|
||||
|
||||
#define SET_NHM_SETTING 0
|
||||
#define STORE_NHM_SETTING 1
|
||||
#define RESTORE_NHM_SETTING 2
|
||||
|
||||
/*
|
||||
#define NHM_EXCLUDE_CCA 0
|
||||
#define NHM_INCLUDE_CCA 1
|
||||
#define NHM_EXCLUDE_TXON 0
|
||||
#define NHM_INCLUDE_TXON 1
|
||||
*/
|
||||
|
||||
enum nhm_inexclude_cca {
|
||||
NHM_EXCLUDE_CCA,
|
||||
NHM_INCLUDE_CCA
|
||||
};
|
||||
|
||||
enum nhm_inexclude_txon {
|
||||
NHM_EXCLUDE_TXON,
|
||||
NHM_INCLUDE_TXON
|
||||
};
|
||||
|
||||
|
||||
struct _CCX_INFO {
|
||||
|
||||
/*Settings*/
|
||||
u8 NHM_th[11];
|
||||
u16 NHM_period; /* 4us per unit */
|
||||
u16 CLM_period; /* 4us per unit */
|
||||
enum nhm_inexclude_txon nhm_inexclude_txon;
|
||||
enum nhm_inexclude_cca nhm_inexclude_cca;
|
||||
|
||||
/*Previous Settings*/
|
||||
u8 NHM_th_restore[11];
|
||||
u16 NHM_period_restore; /* 4us per unit */
|
||||
u16 CLM_period_restore; /* 4us per unit */
|
||||
enum nhm_inexclude_txon NHM_inexclude_txon_restore;
|
||||
enum nhm_inexclude_cca NHM_inexclude_cca_restore;
|
||||
|
||||
/*Report*/
|
||||
u8 NHM_result[12];
|
||||
u16 NHM_duration;
|
||||
u16 CLM_result;
|
||||
|
||||
|
||||
bool echo_NHM_en;
|
||||
bool echo_CLM_en;
|
||||
u8 echo_IGI;
|
||||
|
||||
};
|
||||
|
||||
/*NHM*/
|
||||
|
||||
void
|
||||
phydm_nhm_setting(
|
||||
void *p_dm_void,
|
||||
u8 nhm_setting
|
||||
);
|
||||
|
||||
void
|
||||
phydm_nhm_trigger(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_get_nhm_result(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
bool
|
||||
phydm_check_nhm_ready(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
/*CLM*/
|
||||
|
||||
void
|
||||
phydm_clm_setting(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_clm_trigger(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
bool
|
||||
phydm_check_cl_mready(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_get_cl_mresult(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
|
||||
#endif
|
||||
360
hal/phydm/phydm_cfotracking.c
Normal file
360
hal/phydm/phydm_cfotracking.c
Normal file
|
|
@ -0,0 +1,360 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
void
|
||||
odm_set_crystal_cap(
|
||||
void *p_dm_void,
|
||||
u8 crystal_cap
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK);
|
||||
|
||||
if (p_cfo_track->crystal_cap == crystal_cap)
|
||||
return;
|
||||
|
||||
p_cfo_track->crystal_cap = crystal_cap;
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8188F)) {
|
||||
/* write 0x24[22:17] = 0x24[16:11] = crystal_cap */
|
||||
crystal_cap = crystal_cap & 0x3F;
|
||||
odm_set_bb_reg(p_dm_odm, REG_AFE_XTAL_CTRL, 0x007ff800, (crystal_cap | (crystal_cap << 6)));
|
||||
} else if (p_dm_odm->support_ic_type & ODM_RTL8812) {
|
||||
/* write 0x2C[30:25] = 0x2C[24:19] = crystal_cap */
|
||||
crystal_cap = crystal_cap & 0x3F;
|
||||
odm_set_bb_reg(p_dm_odm, REG_MAC_PHY_CTRL, 0x7FF80000, (crystal_cap | (crystal_cap << 6)));
|
||||
} else if ((p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8192E | ODM_RTL8821))) {
|
||||
/* 0x2C[23:18] = 0x2C[17:12] = crystal_cap */
|
||||
crystal_cap = crystal_cap & 0x3F;
|
||||
odm_set_bb_reg(p_dm_odm, REG_MAC_PHY_CTRL, 0x00FFF000, (crystal_cap | (crystal_cap << 6)));
|
||||
} else if (p_dm_odm->support_ic_type & ODM_RTL8814A) {
|
||||
/* write 0x2C[26:21] = 0x2C[20:15] = crystal_cap */
|
||||
crystal_cap = crystal_cap & 0x3F;
|
||||
odm_set_bb_reg(p_dm_odm, REG_MAC_PHY_CTRL, 0x07FF8000, (crystal_cap | (crystal_cap << 6)));
|
||||
} else if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
|
||||
/* write 0x24[30:25] = 0x28[6:1] = crystal_cap */
|
||||
crystal_cap = crystal_cap & 0x3F;
|
||||
odm_set_bb_reg(p_dm_odm, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap);
|
||||
odm_set_bb_reg(p_dm_odm, REG_AFE_PLL_CTRL, 0x7e, crystal_cap);
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_set_crystal_cap(): Use default setting.\n"));
|
||||
odm_set_bb_reg(p_dm_odm, REG_MAC_PHY_CTRL, 0xFFF000, (crystal_cap | (crystal_cap << 6)));
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_set_crystal_cap(): crystal_cap = 0x%x\n", crystal_cap));
|
||||
#endif
|
||||
}
|
||||
|
||||
u8
|
||||
odm_get_default_crytaltal_cap(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u8 crystal_cap = 0x20;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
|
||||
crystal_cap = p_hal_data->crystal_cap;
|
||||
#else
|
||||
struct rtl8192cd_priv *priv = p_dm_odm->priv;
|
||||
|
||||
if (priv->pmib->dot11RFEntry.xcap > 0)
|
||||
crystal_cap = priv->pmib->dot11RFEntry.xcap;
|
||||
#endif
|
||||
|
||||
crystal_cap = crystal_cap & 0x3f;
|
||||
|
||||
return crystal_cap;
|
||||
}
|
||||
|
||||
void
|
||||
odm_set_atc_status(
|
||||
void *p_dm_void,
|
||||
bool atc_status
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK);
|
||||
|
||||
if (p_cfo_track->is_atc_status == atc_status)
|
||||
return;
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG(BB_ATC, p_dm_odm), ODM_BIT(BB_ATC, p_dm_odm), atc_status);
|
||||
p_cfo_track->is_atc_status = atc_status;
|
||||
}
|
||||
|
||||
bool
|
||||
odm_get_atc_status(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
bool atc_status;
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
|
||||
atc_status = (bool)odm_get_bb_reg(p_dm_odm, ODM_REG(BB_ATC, p_dm_odm), ODM_BIT(BB_ATC, p_dm_odm));
|
||||
return atc_status;
|
||||
}
|
||||
|
||||
void
|
||||
odm_cfo_tracking_reset(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK);
|
||||
|
||||
p_cfo_track->def_x_cap = odm_get_default_crytaltal_cap(p_dm_odm);
|
||||
p_cfo_track->is_adjust = true;
|
||||
|
||||
if (p_cfo_track->crystal_cap > p_cfo_track->def_x_cap) {
|
||||
odm_set_crystal_cap(p_dm_odm, p_cfo_track->crystal_cap - 1);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD,
|
||||
("odm_cfo_tracking_reset(): approch default value (0x%x)\n", p_cfo_track->crystal_cap));
|
||||
} else if (p_cfo_track->crystal_cap < p_cfo_track->def_x_cap) {
|
||||
odm_set_crystal_cap(p_dm_odm, p_cfo_track->crystal_cap + 1);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD,
|
||||
("odm_cfo_tracking_reset(): approch default value (0x%x)\n", p_cfo_track->crystal_cap));
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
odm_set_atc_status(p_dm_odm, true);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
odm_cfo_tracking_init(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK);
|
||||
|
||||
p_cfo_track->def_x_cap = p_cfo_track->crystal_cap = odm_get_default_crytaltal_cap(p_dm_odm);
|
||||
p_cfo_track->is_atc_status = odm_get_atc_status(p_dm_odm);
|
||||
p_cfo_track->is_adjust = true;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init()=========>\n"));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init(): is_atc_status = %d, crystal_cap = 0x%x\n", p_cfo_track->is_atc_status, p_cfo_track->def_x_cap));
|
||||
|
||||
#if RTL8822B_SUPPORT
|
||||
/* Crystal cap. control by WiFi */
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8822B)
|
||||
odm_set_bb_reg(p_dm_odm, 0x10, 0x40, 0x1);
|
||||
#endif
|
||||
|
||||
#if RTL8821C_SUPPORT
|
||||
/* Crystal cap. control by WiFi */
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8821C)
|
||||
odm_set_bb_reg(p_dm_odm, 0x10, 0x40, 0x1);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
odm_cfo_tracking(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK);
|
||||
s32 CFO_ave = 0;
|
||||
u32 CFO_rpt_sum, cfo_khz_avg[4] = {0};
|
||||
s32 CFO_ave_diff;
|
||||
s8 crystal_cap = p_cfo_track->crystal_cap;
|
||||
u8 adjust_xtal = 1, i, valid_path_cnt = 0;
|
||||
|
||||
/* 4 Support ability */
|
||||
if (!(p_dm_odm->support_ability & ODM_BB_CFO_TRACKING)) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Return: support_ability ODM_BB_CFO_TRACKING is disabled\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking()=========>\n"));
|
||||
|
||||
if (!p_dm_odm->is_linked || !p_dm_odm->is_one_entry_only) {
|
||||
/* 4 No link or more than one entry */
|
||||
odm_cfo_tracking_reset(p_dm_odm);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Reset: is_linked = %d, is_one_entry_only = %d\n",
|
||||
p_dm_odm->is_linked, p_dm_odm->is_one_entry_only));
|
||||
} else {
|
||||
/* 3 1. CFO Tracking */
|
||||
/* 4 1.1 No new packet */
|
||||
if (p_cfo_track->packet_count == p_cfo_track->packet_count_pre) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): packet counter doesn't change\n"));
|
||||
return;
|
||||
}
|
||||
p_cfo_track->packet_count_pre = p_cfo_track->packet_count;
|
||||
|
||||
/* 4 1.2 Calculate CFO */
|
||||
for (i = 0; i < p_dm_odm->num_rf_path; i++) {
|
||||
|
||||
if (p_cfo_track->CFO_cnt[i] == 0)
|
||||
continue;
|
||||
|
||||
valid_path_cnt++;
|
||||
CFO_rpt_sum = (u32)((p_cfo_track->CFO_tail[i] < 0) ? (0 - p_cfo_track->CFO_tail[i]) : p_cfo_track->CFO_tail[i]);
|
||||
cfo_khz_avg[i] = CFO_HW_RPT_2_MHZ(CFO_rpt_sum) / p_cfo_track->CFO_cnt[i];
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("[path %d] CFO_rpt_sum = (( %d )), CFO_cnt = (( %d )) , CFO_avg= (( %s%d )) kHz\n",
|
||||
i, CFO_rpt_sum, p_cfo_track->CFO_cnt[i], ((p_cfo_track->CFO_tail[i] < 0) ? "-" : " "), cfo_khz_avg[i]));
|
||||
}
|
||||
|
||||
for (i = 0; i < valid_path_cnt; i++) {
|
||||
|
||||
/* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("path [%d], p_cfo_track->CFO_tail = %d\n", i, p_cfo_track->CFO_tail[i])); */
|
||||
if (p_cfo_track->CFO_tail[i] < 0) {
|
||||
CFO_ave += (0 - (s32)cfo_khz_avg[i]);
|
||||
/* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("CFO_ave = %d\n", CFO_ave)); */
|
||||
} else
|
||||
CFO_ave += (s32)cfo_khz_avg[i];
|
||||
}
|
||||
|
||||
if (valid_path_cnt >= 2)
|
||||
CFO_ave = CFO_ave / valid_path_cnt;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("valid_path_cnt = ((%d)), CFO_ave = ((%d kHz))\n", valid_path_cnt, CFO_ave));
|
||||
|
||||
/*reset counter*/
|
||||
for (i = 0; i < p_dm_odm->num_rf_path; i++) {
|
||||
p_cfo_track->CFO_tail[i] = 0;
|
||||
p_cfo_track->CFO_cnt[i] = 0;
|
||||
}
|
||||
|
||||
/* 4 1.3 Avoid abnormal large CFO */
|
||||
CFO_ave_diff = (p_cfo_track->CFO_ave_pre >= CFO_ave) ? (p_cfo_track->CFO_ave_pre - CFO_ave) : (CFO_ave - p_cfo_track->CFO_ave_pre);
|
||||
if (CFO_ave_diff > 20 && p_cfo_track->large_cfo_hit == 0 && !p_cfo_track->is_adjust) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): first large CFO hit\n"));
|
||||
p_cfo_track->large_cfo_hit = 1;
|
||||
return;
|
||||
} else
|
||||
p_cfo_track->large_cfo_hit = 0;
|
||||
p_cfo_track->CFO_ave_pre = CFO_ave;
|
||||
|
||||
/* 4 1.4 Dynamic Xtal threshold */
|
||||
if (p_cfo_track->is_adjust == false) {
|
||||
if (CFO_ave > CFO_TH_XTAL_HIGH || CFO_ave < (-CFO_TH_XTAL_HIGH))
|
||||
p_cfo_track->is_adjust = true;
|
||||
} else {
|
||||
if (CFO_ave < CFO_TH_XTAL_LOW && CFO_ave > (-CFO_TH_XTAL_LOW))
|
||||
p_cfo_track->is_adjust = false;
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
/* 4 1.5 BT case: Disable CFO tracking */
|
||||
if (p_dm_odm->is_bt_enabled) {
|
||||
p_cfo_track->is_adjust = false;
|
||||
odm_set_crystal_cap(p_dm_odm, p_cfo_track->def_x_cap);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Disable CFO tracking for BT!!\n"));
|
||||
}
|
||||
#if 0
|
||||
/* 4 1.6 Big jump */
|
||||
if (p_cfo_track->is_adjust) {
|
||||
if (CFO_ave > CFO_TH_XTAL_LOW)
|
||||
adjust_xtal = adjust_xtal + ((CFO_ave - CFO_TH_XTAL_LOW) >> 2);
|
||||
else if (CFO_ave < (-CFO_TH_XTAL_LOW))
|
||||
adjust_xtal = adjust_xtal + ((CFO_TH_XTAL_LOW - CFO_ave) >> 2);
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Crystal cap offset = %d\n", adjust_xtal));
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* 4 1.7 Adjust Crystal Cap. */
|
||||
if (p_cfo_track->is_adjust) {
|
||||
if (CFO_ave > CFO_TH_XTAL_LOW)
|
||||
crystal_cap = crystal_cap + adjust_xtal;
|
||||
else if (CFO_ave < (-CFO_TH_XTAL_LOW))
|
||||
crystal_cap = crystal_cap - adjust_xtal;
|
||||
|
||||
if (crystal_cap > 0x3f)
|
||||
crystal_cap = 0x3f;
|
||||
else if (crystal_cap < 0)
|
||||
crystal_cap = 0;
|
||||
|
||||
odm_set_crystal_cap(p_dm_odm, (u8)crystal_cap);
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Crystal cap = 0x%x, Default Crystal cap = 0x%x\n",
|
||||
p_cfo_track->crystal_cap, p_cfo_track->def_x_cap));
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)
|
||||
return;
|
||||
|
||||
/* 3 2. Dynamic ATC switch */
|
||||
if (CFO_ave < CFO_TH_ATC && CFO_ave > -CFO_TH_ATC) {
|
||||
odm_set_atc_status(p_dm_odm, false);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Disable ATC!!\n"));
|
||||
} else {
|
||||
odm_set_atc_status(p_dm_odm, true);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Enable ATC!!\n"));
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
odm_parsing_cfo(
|
||||
void *p_dm_void,
|
||||
void *p_pktinfo_void,
|
||||
s8 *pcfotail,
|
||||
u8 num_ss
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pktinfo_void;
|
||||
struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK);
|
||||
u8 i;
|
||||
|
||||
if (!(p_dm_odm->support_ability & ODM_BB_CFO_TRACKING))
|
||||
return;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
if (p_pktinfo->is_packet_match_bssid)
|
||||
#else
|
||||
if (p_pktinfo->station_id != 0)
|
||||
#endif
|
||||
{
|
||||
if (num_ss > p_dm_odm->num_rf_path) /*For fool proof*/
|
||||
num_ss = p_dm_odm->num_rf_path;
|
||||
|
||||
/*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("num_ss = ((%d)), p_dm_odm->num_rf_path = ((%d))\n", num_ss, p_dm_odm->num_rf_path));*/
|
||||
|
||||
|
||||
/* 3 Update CFO report for path-A & path-B */
|
||||
/* Only paht-A and path-B have CFO tail and short CFO */
|
||||
for (i = 0; i < num_ss; i++) {
|
||||
p_cfo_track->CFO_tail[i] += pcfotail[i];
|
||||
p_cfo_track->CFO_cnt[i]++;
|
||||
/*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("[ID %d][path %d][rate 0x%x] CFO_tail = ((%d)), CFO_tail_sum = ((%d)), CFO_cnt = ((%d))\n",
|
||||
p_pktinfo->station_id, i, p_pktinfo->data_rate, pcfotail[i], p_cfo_track->CFO_tail[i], p_cfo_track->CFO_cnt[i]));
|
||||
*/
|
||||
}
|
||||
|
||||
/* 3 Update packet counter */
|
||||
if (p_cfo_track->packet_count == 0xffffffff)
|
||||
p_cfo_track->packet_count = 0;
|
||||
else
|
||||
p_cfo_track->packet_count++;
|
||||
}
|
||||
}
|
||||
69
hal/phydm/phydm_cfotracking.h
Normal file
69
hal/phydm/phydm_cfotracking.h
Normal file
|
|
@ -0,0 +1,69 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMCFOTRACK_H__
|
||||
#define __PHYDMCFOTRACK_H__
|
||||
|
||||
#define CFO_TRACKING_VERSION "1.4" /*2015.10.01 Stanley, Modify for 8822B*/
|
||||
|
||||
#define CFO_TH_XTAL_HIGH 20 /* kHz */
|
||||
#define CFO_TH_XTAL_LOW 10 /* kHz */
|
||||
#define CFO_TH_ATC 80 /* kHz */
|
||||
|
||||
struct _CFO_TRACKING_ {
|
||||
bool is_atc_status;
|
||||
bool large_cfo_hit;
|
||||
bool is_adjust;
|
||||
u8 crystal_cap;
|
||||
u8 def_x_cap;
|
||||
s32 CFO_tail[4];
|
||||
u32 CFO_cnt[4];
|
||||
s32 CFO_ave_pre;
|
||||
u32 packet_count;
|
||||
u32 packet_count_pre;
|
||||
|
||||
bool is_force_xtal_cap;
|
||||
bool is_reset;
|
||||
};
|
||||
|
||||
void
|
||||
odm_cfo_tracking_reset(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_cfo_tracking_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_cfo_tracking(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_parsing_cfo(
|
||||
void *p_dm_void,
|
||||
void *p_pktinfo_void,
|
||||
s8 *pcfotail,
|
||||
u8 num_ss
|
||||
);
|
||||
|
||||
#endif
|
||||
3061
hal/phydm/phydm_debug.c
Normal file
3061
hal/phydm/phydm_debug.c
Normal file
File diff suppressed because it is too large
Load diff
359
hal/phydm/phydm_debug.h
Normal file
359
hal/phydm/phydm_debug.h
Normal file
|
|
@ -0,0 +1,359 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __ODM_DBG_H__
|
||||
#define __ODM_DBG_H__
|
||||
|
||||
/*#define DEBUG_VERSION "1.1"*/ /*2015.07.29 YuChen*/
|
||||
/*#define DEBUG_VERSION "1.2"*/ /*2015.08.28 Dino*/
|
||||
#define DEBUG_VERSION "1.3" /*2016.04.28 YuChen*/
|
||||
/* -----------------------------------------------------------------------------
|
||||
* Define the debug levels
|
||||
*
|
||||
* 1. DBG_TRACE and DBG_LOUD are used for normal cases.
|
||||
* So that, they can help SW engineer to develope or trace states changed
|
||||
* and also help HW enginner to trace every operation to and from HW,
|
||||
* e.g IO, Tx, Rx.
|
||||
*
|
||||
* 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases,
|
||||
* which help us to debug SW or HW.
|
||||
*
|
||||
* -----------------------------------------------------------------------------
|
||||
*
|
||||
* Never used in a call to ODM_RT_TRACE()!
|
||||
* */
|
||||
#define ODM_DBG_OFF 1
|
||||
|
||||
/*
|
||||
* Fatal bug.
|
||||
* For example, Tx/Rx/IO locked up, OS hangs, memory access violation,
|
||||
* resource allocation failed, unexpected HW behavior, HW BUG and so on.
|
||||
* */
|
||||
#define ODM_DBG_SERIOUS 2
|
||||
|
||||
/*
|
||||
* Abnormal, rare, or unexpeted cases.
|
||||
* For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
|
||||
* */
|
||||
#define ODM_DBG_WARNING 3
|
||||
|
||||
/*
|
||||
* Normal case with useful information about current SW or HW state.
|
||||
* For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status,
|
||||
* SW protocol state change, dynamic mechanism state change and so on.
|
||||
* */
|
||||
#define ODM_DBG_LOUD 4
|
||||
|
||||
/*
|
||||
* Normal case with detail execution flow or information.
|
||||
* */
|
||||
#define ODM_DBG_TRACE 5
|
||||
|
||||
/*FW DBG MSG*/
|
||||
#define RATE_DECISION BIT(0)
|
||||
#define INIT_RA_TABLE BIT(1)
|
||||
#define RATE_UP BIT(2)
|
||||
#define RATE_DOWN BIT(3)
|
||||
#define TRY_DONE BIT(4)
|
||||
#define RA_H2C BIT(5)
|
||||
#define F_RATE_AP_RPT BIT(7)
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
* Define the tracing components
|
||||
*
|
||||
* -----------------------------------------------------------------------------
|
||||
*BB FW Functions*/
|
||||
#define PHYDM_FW_COMP_RA BIT(0)
|
||||
#define PHYDM_FW_COMP_MU BIT(1)
|
||||
#define PHYDM_FW_COMP_PATH_DIV BIT(2)
|
||||
#define PHYDM_FW_COMP_PHY_CONFIG BIT(3)
|
||||
|
||||
|
||||
/*BB Driver Functions*/
|
||||
#define ODM_COMP_DIG BIT(0)
|
||||
#define ODM_COMP_RA_MASK BIT(1)
|
||||
#define ODM_COMP_DYNAMIC_TXPWR BIT(2)
|
||||
#define ODM_COMP_FA_CNT BIT(3)
|
||||
#define ODM_COMP_RSSI_MONITOR BIT(4)
|
||||
#define ODM_COMP_SNIFFER BIT(5)
|
||||
#define ODM_COMP_ANT_DIV BIT(6)
|
||||
#define ODM_COMP_DFS BIT(7)
|
||||
#define ODM_COMP_NOISY_DETECT BIT(8)
|
||||
#define ODM_COMP_RATE_ADAPTIVE BIT(9)
|
||||
#define ODM_COMP_PATH_DIV BIT(10)
|
||||
#define ODM_COMP_CCX BIT(11)
|
||||
|
||||
#define ODM_COMP_DYNAMIC_PRICCA BIT(12)
|
||||
/*BIT13 TBD*/
|
||||
#define ODM_COMP_MP BIT(14)
|
||||
#define ODM_COMP_CFO_TRACKING BIT(15)
|
||||
#define ODM_COMP_ACS BIT(16)
|
||||
#define PHYDM_COMP_ADAPTIVITY BIT(17)
|
||||
#define PHYDM_COMP_RA_DBG BIT(18)
|
||||
#define PHYDM_COMP_TXBF BIT(19)
|
||||
/* MAC Functions */
|
||||
#define ODM_COMP_EDCA_TURBO BIT(20)
|
||||
#define ODM_COMP_DYNAMIC_RX_PATH BIT(21)
|
||||
#define ODM_FW_DEBUG_TRACE BIT(22)
|
||||
/* RF Functions */
|
||||
/*BIT23 TBD*/
|
||||
#define ODM_COMP_TX_PWR_TRACK BIT(24)
|
||||
/*BIT25 TBD*/
|
||||
#define ODM_COMP_CALIBRATION BIT(26)
|
||||
/* Common Functions */
|
||||
/*BIT27 TBD*/
|
||||
#define ODM_PHY_CONFIG BIT(28)
|
||||
#define ODM_COMP_INIT BIT(29)
|
||||
#define ODM_COMP_COMMON BIT(30)
|
||||
#define ODM_COMP_API BIT(31)
|
||||
|
||||
|
||||
/*------------------------Export Marco Definition---------------------------*/
|
||||
|
||||
#define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA)
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define dbg_print DbgPrint
|
||||
#define dcmd_printf DCMD_Printf
|
||||
#define dcmd_scanf DCMD_Scanf
|
||||
#define RT_PRINTK dbg_print
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#define dbg_print printk
|
||||
#define RT_PRINTK(fmt, args...) dbg_print("%s(): " fmt, __FUNCTION__, ## args);
|
||||
#define RT_DISP(dbgtype, dbgflag, printstr)
|
||||
#else
|
||||
#define dbg_print panic_printk
|
||||
#define RT_PRINTK(fmt, args...) dbg_print("%s(): " fmt, __FUNCTION__, ## args);
|
||||
#endif
|
||||
|
||||
#ifndef ASSERT
|
||||
#define ASSERT(expr)
|
||||
#endif
|
||||
|
||||
#if DBG
|
||||
#define ODM_RT_TRACE(p_dm_odm, comp, level, fmt) \
|
||||
do { \
|
||||
if (((comp) & p_dm_odm->debug_components) && (level <= p_dm_odm->debug_level || level == ODM_DBG_SERIOUS)) { \
|
||||
\
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8188E) \
|
||||
dbg_print("[PhyDM-8188E] "); \
|
||||
else if (p_dm_odm->support_ic_type == ODM_RTL8192E) \
|
||||
dbg_print("[PhyDM-8192E] "); \
|
||||
else if (p_dm_odm->support_ic_type == ODM_RTL8812) \
|
||||
dbg_print("[PhyDM-8812A] "); \
|
||||
else if (p_dm_odm->support_ic_type == ODM_RTL8821) \
|
||||
dbg_print("[PhyDM-8821A] "); \
|
||||
else if (p_dm_odm->support_ic_type == ODM_RTL8814A) \
|
||||
dbg_print("[PhyDM-8814A] "); \
|
||||
else if (p_dm_odm->support_ic_type == ODM_RTL8703B) \
|
||||
dbg_print("[PhyDM-8703B] "); \
|
||||
else if (p_dm_odm->support_ic_type == ODM_RTL8822B) \
|
||||
dbg_print("[PhyDM-8822B] "); \
|
||||
else if (p_dm_odm->support_ic_type == ODM_RTL8188F) \
|
||||
dbg_print("[PhyDM-8188F] "); \
|
||||
RT_PRINTK fmt; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define ODM_RT_TRACE_F(p_dm_odm, comp, level, fmt) do {\
|
||||
if (((comp) & p_dm_odm->debug_components) && (level <= p_dm_odm->debug_level)) { \
|
||||
\
|
||||
RT_PRINTK fmt; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
|
||||
#define ODM_RT_ASSERT(p_dm_odm, expr, fmt) do {\
|
||||
if (!(expr)) { \
|
||||
dbg_print("Assertion failed! %s at ......\n", #expr); \
|
||||
dbg_print(" ......%s,%s, line=%d\n", __FILE__, __FUNCTION__, __LINE__); \
|
||||
RT_PRINTK fmt; \
|
||||
ASSERT(false); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define ODM_dbg_enter() { dbg_print(" == > %s\n", __FUNCTION__); }
|
||||
#define ODM_dbg_exit() { dbg_print("< == %s\n", __FUNCTION__); }
|
||||
#define ODM_dbg_trace(str) { dbg_print("%s:%s\n", __FUNCTION__, str); }
|
||||
|
||||
#define ODM_PRINT_ADDR(p_dm_odm, comp, level, title_str, ptr) do {\
|
||||
if (((comp) & p_dm_odm->debug_components) && (level <= p_dm_odm->debug_level)) { \
|
||||
\
|
||||
int __i; \
|
||||
u8 *__ptr = (u8 *)ptr; \
|
||||
dbg_print("[ODM] "); \
|
||||
dbg_print(title_str); \
|
||||
dbg_print(" "); \
|
||||
for (__i = 0; __i < 6; __i++) \
|
||||
dbg_print("%02X%s", __ptr[__i], (__i == 5) ? "" : "-"); \
|
||||
dbg_print("\n"); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#else
|
||||
#define ODM_RT_TRACE(p_dm_odm, comp, level, fmt)
|
||||
#define ODM_RT_TRACE_F(p_dm_odm, comp, level, fmt)
|
||||
#define ODM_RT_ASSERT(p_dm_odm, expr, fmt)
|
||||
#define ODM_dbg_enter()
|
||||
#define ODM_dbg_exit()
|
||||
#define ODM_dbg_trace(str)
|
||||
#define ODM_PRINT_ADDR(p_dm_odm, comp, level, title_str, ptr)
|
||||
#endif
|
||||
|
||||
|
||||
void
|
||||
phydm_init_debug_setting(struct PHY_DM_STRUCT *p_dm_odm);
|
||||
|
||||
void phydm_basic_dbg_message(void *p_dm_void);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define PHYDM_DBGPRINT 0
|
||||
#define PHYDM_SSCANF(x, y, z) dcmd_scanf(x, y, z)
|
||||
#define PHYDM_VAST_INFO_SNPRINTF PHYDM_SNPRINTF
|
||||
#if (PHYDM_DBGPRINT == 1)
|
||||
#define PHYDM_SNPRINTF(msg) \
|
||||
do {\
|
||||
rsprintf msg;\
|
||||
dbg_print(output);\
|
||||
} while (0)
|
||||
#else
|
||||
#define PHYDM_SNPRINTF(msg) \
|
||||
do {\
|
||||
rsprintf msg;\
|
||||
dcmd_printf(output);\
|
||||
} while (0)
|
||||
#endif
|
||||
#else
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) || defined(__OSK__)
|
||||
#define PHYDM_DBGPRINT 0
|
||||
#else
|
||||
#define PHYDM_DBGPRINT 1
|
||||
#endif
|
||||
#define MAX_ARGC 20
|
||||
#define MAX_ARGV 16
|
||||
#define DCMD_DECIMAL "%d"
|
||||
#define DCMD_CHAR "%c"
|
||||
#define DCMD_HEX "%x"
|
||||
|
||||
#define PHYDM_SSCANF(x, y, z) sscanf(x, y, z)
|
||||
|
||||
#define PHYDM_VAST_INFO_SNPRINTF(msg)\
|
||||
do {\
|
||||
snprintf msg;\
|
||||
dbg_print(output);\
|
||||
} while (0)
|
||||
|
||||
#if (PHYDM_DBGPRINT == 1)
|
||||
#define PHYDM_SNPRINTF(msg)\
|
||||
do {\
|
||||
snprintf msg;\
|
||||
dbg_print(output);\
|
||||
} while (0)
|
||||
#else
|
||||
#define PHYDM_SNPRINTF(msg)\
|
||||
do {\
|
||||
if (out_len > used)\
|
||||
used += snprintf msg;\
|
||||
} while (0)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
void phydm_basic_profile(
|
||||
void *p_dm_void,
|
||||
u32 *_used,
|
||||
char *output,
|
||||
u32 *_out_len
|
||||
);
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
|
||||
s32
|
||||
phydm_cmd(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
char *input,
|
||||
u32 in_len,
|
||||
u8 flag,
|
||||
char *output,
|
||||
u32 out_len
|
||||
);
|
||||
#endif
|
||||
void
|
||||
phydm_cmd_parser(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
char input[][16],
|
||||
u32 input_num,
|
||||
u8 flag,
|
||||
char *output,
|
||||
u32 out_len
|
||||
);
|
||||
|
||||
bool
|
||||
phydm_api_trx_mode(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
enum odm_rf_path_e tx_path,
|
||||
enum odm_rf_path_e rx_path,
|
||||
bool is_tx2_path
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void phydm_sbd_check(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
void phydm_sbd_callback(
|
||||
struct timer_list *p_timer
|
||||
);
|
||||
|
||||
void phydm_sbd_workitem_callback(
|
||||
void *p_context
|
||||
);
|
||||
#endif
|
||||
|
||||
void
|
||||
phydm_fw_trace_en_h2c(
|
||||
void *p_dm_void,
|
||||
bool enable,
|
||||
u32 fw_debug_component,
|
||||
u32 monitor_mode,
|
||||
u32 macid
|
||||
);
|
||||
|
||||
void
|
||||
phydm_fw_trace_handler(
|
||||
void *p_dm_void,
|
||||
u8 *cmd_buf,
|
||||
u8 cmd_len
|
||||
);
|
||||
|
||||
void
|
||||
phydm_fw_trace_handler_code(
|
||||
void *p_dm_void,
|
||||
u8 *buffer,
|
||||
u8 cmd_len
|
||||
);
|
||||
|
||||
void
|
||||
phydm_fw_trace_handler_8051(
|
||||
void *p_dm_void,
|
||||
u8 *cmd_buf,
|
||||
u8 cmd_len
|
||||
);
|
||||
|
||||
#endif /* __ODM_DBG_H__ */
|
||||
257
hal/phydm/phydm_dfs.c
Normal file
257
hal/phydm/phydm_dfs.c
Normal file
|
|
@ -0,0 +1,257 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
============================================================
|
||||
include files
|
||||
============================================================
|
||||
*/
|
||||
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
#if defined(CONFIG_PHYDM_DFS_MASTER)
|
||||
void phydm_radar_detect_reset(void *p_dm_void)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, 0x924, BIT(15), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x924, BIT(15), 1);
|
||||
}
|
||||
|
||||
void phydm_radar_detect_disable(void *p_dm_void)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, 0x924, BIT(15), 0);
|
||||
}
|
||||
|
||||
static void phydm_radar_detect_with_dbg_parm(void *p_dm_void)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, p_dm_odm->radar_detect_reg_918);
|
||||
odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, p_dm_odm->radar_detect_reg_91c);
|
||||
odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, p_dm_odm->radar_detect_reg_920);
|
||||
odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, p_dm_odm->radar_detect_reg_924);
|
||||
}
|
||||
|
||||
/* Init radar detection parameters, called after ch, bw is set */
|
||||
void phydm_radar_detect_enable(void *p_dm_void)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u8 region_domain = p_dm_odm->dfs_region_domain;
|
||||
u8 c_channel = *(p_dm_odm->p_channel);
|
||||
|
||||
if (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("PHYDM_DFS_DOMAIN_UNKNOWN\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812 | ODM_RTL8881A)) {
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, 0x814, 0x3fffffff, 0x04cc4d10);
|
||||
odm_set_bb_reg(p_dm_odm, 0x834, MASKBYTE0, 0x06);
|
||||
|
||||
if (p_dm_odm->radar_detect_dbg_parm_en) {
|
||||
phydm_radar_detect_with_dbg_parm(p_dm_odm);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c17ecdf);
|
||||
odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x01528500);
|
||||
odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x0fa21a20);
|
||||
odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0f69204);
|
||||
|
||||
} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x01528500);
|
||||
odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0d67234);
|
||||
|
||||
if (c_channel >= 52 && c_channel <= 64) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c16ecdf);
|
||||
odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x0f141a20);
|
||||
} else {
|
||||
odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c16acdf);
|
||||
if (p_dm_odm->p_band_width == ODM_BW20M)
|
||||
odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x64721a20);
|
||||
else
|
||||
odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x68721a20);
|
||||
}
|
||||
|
||||
} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c16acdf);
|
||||
odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x01528500);
|
||||
odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0d67231);
|
||||
if (p_dm_odm->p_band_width == ODM_BW20M)
|
||||
odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x64741a20);
|
||||
else
|
||||
odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x68741a20);
|
||||
} else {
|
||||
/* not supported */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported dfs_region_domain:%d\n", region_domain));
|
||||
}
|
||||
|
||||
} else if (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)) {
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, 0x814, 0x3fffffff, 0x04cc4d10);
|
||||
odm_set_bb_reg(p_dm_odm, 0x834, MASKBYTE0, 0x06);
|
||||
|
||||
/* 8822B only, when BW = 20M, DFIR output is 40Mhz, but DFS input is 80MMHz, so it need to upgrade to 80MHz */
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8822B) {
|
||||
if (p_dm_odm->p_band_width == ODM_BW20M)
|
||||
odm_set_bb_reg(p_dm_odm, 0x1984, BIT(26), 1);
|
||||
else
|
||||
odm_set_bb_reg(p_dm_odm, 0x1984, BIT(26), 0);
|
||||
}
|
||||
|
||||
if (p_dm_odm->radar_detect_dbg_parm_en) {
|
||||
phydm_radar_detect_with_dbg_parm(p_dm_odm);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c16acdf);
|
||||
odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x095a8500);
|
||||
odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x0fa21a20);
|
||||
odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0f57204);
|
||||
|
||||
} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x095a8500);
|
||||
odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0d67234);
|
||||
|
||||
if (c_channel >= 52 && c_channel <= 64) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c16ecdf);
|
||||
odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x0f141a20);
|
||||
} else {
|
||||
odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c166cdf);
|
||||
if (p_dm_odm->p_band_width == ODM_BW20M)
|
||||
odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x64721a20);
|
||||
else
|
||||
odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x68721a20);
|
||||
}
|
||||
} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c166cdf);
|
||||
odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x095a8500);
|
||||
odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0d67231);
|
||||
if (p_dm_odm->p_band_width == ODM_BW20M)
|
||||
odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x64741a20);
|
||||
else
|
||||
odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x68741a20);
|
||||
} else {
|
||||
/* not supported */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported dfs_region_domain:%d\n", region_domain));
|
||||
}
|
||||
} else {
|
||||
/* not supported IC type*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported IC type:%d\n", p_dm_odm->support_ic_type));
|
||||
}
|
||||
|
||||
exit:
|
||||
phydm_radar_detect_reset(p_dm_odm);
|
||||
}
|
||||
|
||||
bool phydm_radar_detect(void *p_dm_void)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
bool enable_DFS = false;
|
||||
bool radar_detected = false;
|
||||
u8 region_domain = p_dm_odm->dfs_region_domain;
|
||||
|
||||
if (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("PHYDM_DFS_DOMAIN_UNKNOWN\n"));
|
||||
return false;
|
||||
}
|
||||
|
||||
if (odm_get_bb_reg(p_dm_odm, 0x924, BIT(15)))
|
||||
enable_DFS = true;
|
||||
|
||||
if ((odm_get_bb_reg(p_dm_odm, 0xf98, BIT(17)))
|
||||
|| (!(region_domain == PHYDM_DFS_DOMAIN_ETSI) && (odm_get_bb_reg(p_dm_odm, 0xf98, BIT(19)))))
|
||||
radar_detected = true;
|
||||
|
||||
if (enable_DFS && radar_detected) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD
|
||||
, ("Radar detect: enable_DFS:%d, radar_detected:%d\n"
|
||||
, enable_DFS, radar_detected));
|
||||
|
||||
phydm_radar_detect_reset(p_dm_odm);
|
||||
}
|
||||
|
||||
exit:
|
||||
return enable_DFS && radar_detected;
|
||||
}
|
||||
#endif /* defined(CONFIG_PHYDM_DFS_MASTER) */
|
||||
|
||||
bool
|
||||
phydm_dfs_master_enabled(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
#ifdef CONFIG_PHYDM_DFS_MASTER
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
|
||||
return *p_dm_odm->dfs_master_enabled ? true : false;
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
phydm_dfs_debug(
|
||||
void *p_dm_void,
|
||||
u32 *const argv,
|
||||
u32 *_used,
|
||||
char *output,
|
||||
u32 *_out_len
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u32 used = *_used;
|
||||
u32 out_len = *_out_len;
|
||||
|
||||
switch (argv[0]) {
|
||||
case 1:
|
||||
#if defined(CONFIG_PHYDM_DFS_MASTER)
|
||||
/* set dbg parameters for radar detection instead of the default value */
|
||||
if (argv[1] == 1) {
|
||||
p_dm_odm->radar_detect_reg_918 = argv[2];
|
||||
p_dm_odm->radar_detect_reg_91c = argv[3];
|
||||
p_dm_odm->radar_detect_reg_920 = argv[4];
|
||||
p_dm_odm->radar_detect_reg_924 = argv[5];
|
||||
p_dm_odm->radar_detect_dbg_parm_en = 1;
|
||||
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "Radar detection with dbg parameter\n"));
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "reg918:0x%08X\n", p_dm_odm->radar_detect_reg_918));
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "reg91c:0x%08X\n", p_dm_odm->radar_detect_reg_91c));
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "reg920:0x%08X\n", p_dm_odm->radar_detect_reg_920));
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "reg924:0x%08X\n", p_dm_odm->radar_detect_reg_924));
|
||||
} else {
|
||||
p_dm_odm->radar_detect_dbg_parm_en = 0;
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "Radar detection with default parameter\n"));
|
||||
}
|
||||
phydm_radar_detect_enable(p_dm_odm);
|
||||
#endif /* defined(CONFIG_PHYDM_DFS_MASTER) */
|
||||
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
75
hal/phydm/phydm_dfs.h
Normal file
75
hal/phydm/phydm_dfs.h
Normal file
|
|
@ -0,0 +1,75 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDM_DFS_H__
|
||||
#define __PHYDM_DFS_H__
|
||||
|
||||
#define DFS_VERSION "0.0"
|
||||
|
||||
/* ============================================================
|
||||
Definition
|
||||
============================================================
|
||||
*/
|
||||
|
||||
/*
|
||||
============================================================
|
||||
1 structure
|
||||
============================================================
|
||||
*/
|
||||
|
||||
/* ============================================================
|
||||
enumeration
|
||||
============================================================
|
||||
*/
|
||||
|
||||
enum phydm_dfs_region_domain {
|
||||
PHYDM_DFS_DOMAIN_UNKNOWN = 0,
|
||||
PHYDM_DFS_DOMAIN_FCC = 1,
|
||||
PHYDM_DFS_DOMAIN_MKK = 2,
|
||||
PHYDM_DFS_DOMAIN_ETSI = 3,
|
||||
};
|
||||
|
||||
/*
|
||||
============================================================
|
||||
function prototype
|
||||
============================================================
|
||||
*/
|
||||
#if defined(CONFIG_PHYDM_DFS_MASTER)
|
||||
void phydm_radar_detect_reset(void *p_dm_void);
|
||||
void phydm_radar_detect_disable(void *p_dm_void);
|
||||
void phydm_radar_detect_enable(void *p_dm_void);
|
||||
bool phydm_radar_detect(void *p_dm_void);
|
||||
#endif /* defined(CONFIG_PHYDM_DFS_MASTER) */
|
||||
|
||||
bool
|
||||
phydm_dfs_master_enabled(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_dfs_debug(
|
||||
void *p_dm_void,
|
||||
u32 *const argv,
|
||||
u32 *_used,
|
||||
char *output,
|
||||
u32 *_out_len
|
||||
);
|
||||
|
||||
#endif /*#ifndef __PHYDM_DFS_H__ */
|
||||
2142
hal/phydm/phydm_dig.c
Normal file
2142
hal/phydm/phydm_dig.c
Normal file
File diff suppressed because it is too large
Load diff
368
hal/phydm/phydm_dig.h
Normal file
368
hal/phydm/phydm_dig.h
Normal file
|
|
@ -0,0 +1,368 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMDIG_H__
|
||||
#define __PHYDMDIG_H__
|
||||
|
||||
#define DIG_VERSION "1.3" /* 2016.08.16 YuChen. Modify IGI lower bound to 0x1e for 8197F asked by RF Arthur*/
|
||||
|
||||
/* Pause DIG & CCKPD */
|
||||
#define DM_DIG_MAX_PAUSE_TYPE 0x7
|
||||
|
||||
enum dig_goupcheck_level {
|
||||
|
||||
DIG_GOUPCHECK_LEVEL_0,
|
||||
DIG_GOUPCHECK_LEVEL_1,
|
||||
DIG_GOUPCHECK_LEVEL_2
|
||||
|
||||
};
|
||||
|
||||
struct _dynamic_initial_gain_threshold_ {
|
||||
bool is_stop_dig; /* for debug */
|
||||
bool is_ignore_dig;
|
||||
bool is_psd_in_progress;
|
||||
|
||||
u8 dig_enable_flag;
|
||||
u8 dig_ext_port_stage;
|
||||
|
||||
int rssi_low_thresh;
|
||||
int rssi_high_thresh;
|
||||
|
||||
u32 fa_low_thresh;
|
||||
u32 fa_high_thresh;
|
||||
|
||||
u8 cur_sta_connect_state;
|
||||
u8 pre_sta_connect_state;
|
||||
u8 cur_multi_sta_connect_state;
|
||||
|
||||
u8 pre_ig_value;
|
||||
u8 cur_ig_value;
|
||||
u8 backup_ig_value; /* MP DIG */
|
||||
u8 bt30_cur_igi;
|
||||
u8 igi_backup;
|
||||
|
||||
s8 backoff_val;
|
||||
s8 backoff_val_range_max;
|
||||
s8 backoff_val_range_min;
|
||||
u8 rx_gain_range_max;
|
||||
u8 rx_gain_range_min;
|
||||
u8 rssi_val_min;
|
||||
|
||||
u8 pre_cck_cca_thres;
|
||||
u8 cur_cck_cca_thres;
|
||||
u8 pre_cck_pd_state;
|
||||
u8 cur_cck_pd_state;
|
||||
u8 cck_pd_backup;
|
||||
u8 pause_cckpd_level;
|
||||
u8 pause_cckpd_value[DM_DIG_MAX_PAUSE_TYPE + 1];
|
||||
|
||||
u8 large_fa_hit;
|
||||
u8 large_fa_timeout; /*if (large_fa_hit), monitor "large_fa_timeout" sec, if timeout, large_fa_hit=0*/
|
||||
u8 forbidden_igi;
|
||||
u32 recover_cnt;
|
||||
|
||||
u8 dig_dynamic_min_0;
|
||||
u8 dig_dynamic_min_1;
|
||||
bool is_media_connect_0;
|
||||
bool is_media_connect_1;
|
||||
|
||||
u32 ant_div_rssi_max;
|
||||
u32 RSSI_max;
|
||||
|
||||
u8 *is_p2p_in_process;
|
||||
|
||||
u8 pause_dig_level;
|
||||
u8 pause_dig_value[DM_DIG_MAX_PAUSE_TYPE + 1];
|
||||
|
||||
u32 cck_fa_ma;
|
||||
enum dig_goupcheck_level dig_go_up_check_level;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
bool is_tp_target;
|
||||
bool is_noise_est;
|
||||
u32 tp_train_th_min;
|
||||
u8 igi_offset_a;
|
||||
u8 igi_offset_b;
|
||||
#endif
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
|
||||
u8 rf_gain_idx;
|
||||
u8 agc_table_idx;
|
||||
u8 big_jump_lmt[16];
|
||||
u8 enable_adjust_big_jump:1;
|
||||
u8 big_jump_step1:3;
|
||||
u8 big_jump_step2:2;
|
||||
u8 big_jump_step3:2;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct _FALSE_ALARM_STATISTICS {
|
||||
u32 cnt_parity_fail;
|
||||
u32 cnt_rate_illegal;
|
||||
u32 cnt_crc8_fail;
|
||||
u32 cnt_mcs_fail;
|
||||
u32 cnt_ofdm_fail;
|
||||
u32 cnt_ofdm_fail_pre; /* For RTL8881A */
|
||||
u32 cnt_cck_fail;
|
||||
u32 cnt_all;
|
||||
u32 cnt_all_pre;
|
||||
u32 cnt_fast_fsync;
|
||||
u32 cnt_sb_search_fail;
|
||||
u32 cnt_ofdm_cca;
|
||||
u32 cnt_cck_cca;
|
||||
u32 cnt_cca_all;
|
||||
u32 cnt_bw_usc; /* Gary */
|
||||
u32 cnt_bw_lsc; /* Gary */
|
||||
u32 cnt_cck_crc32_error;
|
||||
u32 cnt_cck_crc32_ok;
|
||||
u32 cnt_ofdm_crc32_error;
|
||||
u32 cnt_ofdm_crc32_ok;
|
||||
u32 cnt_ht_crc32_error;
|
||||
u32 cnt_ht_crc32_ok;
|
||||
u32 cnt_vht_crc32_error;
|
||||
u32 cnt_vht_crc32_ok;
|
||||
u32 cnt_crc32_error_all;
|
||||
u32 cnt_crc32_ok_all;
|
||||
bool cck_block_enable;
|
||||
bool ofdm_block_enable;
|
||||
u32 dbg_port0;
|
||||
bool edcca_flag;
|
||||
};
|
||||
|
||||
enum dm_dig_op_e {
|
||||
DIG_TYPE_THRESH_HIGH = 0,
|
||||
DIG_TYPE_THRESH_LOW = 1,
|
||||
DIG_TYPE_BACKOFF = 2,
|
||||
DIG_TYPE_RX_GAIN_MIN = 3,
|
||||
DIG_TYPE_RX_GAIN_MAX = 4,
|
||||
DIG_TYPE_ENABLE = 5,
|
||||
DIG_TYPE_DISABLE = 6,
|
||||
DIG_OP_TYPE_MAX
|
||||
};
|
||||
|
||||
/*
|
||||
enum dm_cck_pdth_e
|
||||
{
|
||||
CCK_PD_STAGE_LowRssi = 0,
|
||||
CCK_PD_STAGE_HighRssi = 1,
|
||||
CCK_PD_STAGE_MAX = 3,
|
||||
};
|
||||
|
||||
enum dm_dig_ext_port_alg_e
|
||||
{
|
||||
DIG_EXT_PORT_STAGE_0 = 0,
|
||||
DIG_EXT_PORT_STAGE_1 = 1,
|
||||
DIG_EXT_PORT_STAGE_2 = 2,
|
||||
DIG_EXT_PORT_STAGE_3 = 3,
|
||||
DIG_EXT_PORT_STAGE_MAX = 4,
|
||||
};
|
||||
|
||||
enum dm_dig_connect_e
|
||||
{
|
||||
DIG_STA_DISCONNECT = 0,
|
||||
DIG_STA_CONNECT = 1,
|
||||
DIG_STA_BEFORE_CONNECT = 2,
|
||||
dig_multi_sta_disconnect = 3,
|
||||
dig_multi_sta_connect = 4,
|
||||
DIG_CONNECT_MAX
|
||||
};
|
||||
|
||||
|
||||
#define DM_MultiSTA_InitGainChangeNotify(Event) {dm_dig_table.cur_multi_sta_connect_state = Event;}
|
||||
|
||||
#define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER) \
|
||||
DM_MultiSTA_InitGainChangeNotify(dig_multi_sta_connect)
|
||||
|
||||
#define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER) \
|
||||
DM_MultiSTA_InitGainChangeNotify(dig_multi_sta_disconnect)
|
||||
*/
|
||||
|
||||
enum phydm_pause_type {
|
||||
PHYDM_PAUSE = BIT(0),
|
||||
PHYDM_RESUME = BIT(1)
|
||||
};
|
||||
|
||||
enum phydm_pause_level {
|
||||
/* number of pause level can't exceed DM_DIG_MAX_PAUSE_TYPE */
|
||||
PHYDM_PAUSE_LEVEL_0 = 0,
|
||||
PHYDM_PAUSE_LEVEL_1 = 1,
|
||||
PHYDM_PAUSE_LEVEL_2 = 2,
|
||||
PHYDM_PAUSE_LEVEL_3 = 3,
|
||||
PHYDM_PAUSE_LEVEL_4 = 4,
|
||||
PHYDM_PAUSE_LEVEL_5 = 5,
|
||||
PHYDM_PAUSE_LEVEL_6 = 6,
|
||||
PHYDM_PAUSE_LEVEL_7 = DM_DIG_MAX_PAUSE_TYPE /* maximum level */
|
||||
};
|
||||
|
||||
#define DM_DIG_THRESH_HIGH 40
|
||||
#define DM_DIG_THRESH_LOW 35
|
||||
|
||||
#define DM_FALSEALARM_THRESH_LOW 400
|
||||
#define DM_FALSEALARM_THRESH_HIGH 1000
|
||||
|
||||
#define DM_DIG_MAX_NIC 0x3e
|
||||
#define DM_DIG_MIN_NIC 0x20
|
||||
#define DM_DIG_MAX_OF_MIN_NIC 0x3e
|
||||
|
||||
#define DM_DIG_MAX_AP 0x3e
|
||||
#define DM_DIG_MIN_AP 0x20
|
||||
#define DM_DIG_MAX_OF_MIN 0x2A /* 0x32 */
|
||||
#define DM_DIG_MIN_AP_DFS 0x20
|
||||
|
||||
#define DM_DIG_MAX_NIC_HP 0x46
|
||||
#define DM_DIG_MIN_NIC_HP 0x2e
|
||||
|
||||
#define DM_DIG_MAX_AP_HP 0x42
|
||||
#define DM_DIG_MIN_AP_HP 0x30
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
#define DM_DIG_MAX_AP_COVERAGR 0x26
|
||||
#define DM_DIG_MIN_AP_COVERAGE 0x1c
|
||||
#define DM_DIG_MAX_OF_MIN_COVERAGE 0x22
|
||||
|
||||
#define dm_dig_tp_target_th0 500
|
||||
#define dm_dig_tp_target_th1 1000
|
||||
#define dm_dig_tp_training_period 10
|
||||
#endif
|
||||
|
||||
/* vivi 92c&92d has different definition, 20110504
|
||||
* this is for 92c */
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
|
||||
#define DM_DIG_FA_TH0 0x80/* 0x20 */
|
||||
#else
|
||||
#define DM_DIG_FA_TH0 0x200/* 0x20 */
|
||||
#endif
|
||||
#else
|
||||
#define DM_DIG_FA_TH0 0x200/* 0x20 */
|
||||
#endif
|
||||
|
||||
#define DM_DIG_FA_TH1 0x300
|
||||
#define DM_DIG_FA_TH2 0x400
|
||||
/* this is for 92d */
|
||||
#define DM_DIG_FA_TH0_92D 0x100
|
||||
#define DM_DIG_FA_TH1_92D 0x400
|
||||
#define DM_DIG_FA_TH2_92D 0x600
|
||||
|
||||
#define DM_DIG_BACKOFF_MAX 12
|
||||
#define DM_DIG_BACKOFF_MIN -4
|
||||
#define DM_DIG_BACKOFF_DEFAULT 10
|
||||
|
||||
#define DM_DIG_FA_TH0_LPS 4 /* -> 4 in lps */
|
||||
#define DM_DIG_FA_TH1_LPS 15 /* -> 15 lps */
|
||||
#define DM_DIG_FA_TH2_LPS 30 /* -> 30 lps */
|
||||
#define RSSI_OFFSET_DIG 0x05
|
||||
#define LARGE_FA_TIMEOUT 60
|
||||
|
||||
|
||||
void
|
||||
odm_change_dynamic_init_gain_thresh(
|
||||
void *p_dm_void,
|
||||
u32 dm_type,
|
||||
u32 dm_value
|
||||
);
|
||||
|
||||
void
|
||||
odm_write_dig(
|
||||
void *p_dm_void,
|
||||
u8 current_igi
|
||||
);
|
||||
|
||||
void
|
||||
odm_pause_dig(
|
||||
void *p_dm_void,
|
||||
enum phydm_pause_type pause_type,
|
||||
enum phydm_pause_level pause_level,
|
||||
u8 igi_value
|
||||
);
|
||||
|
||||
void
|
||||
odm_dig_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_DIG(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_dig_by_rssi_lps(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_false_alarm_counter_statistics(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_pause_cck_packet_detection(
|
||||
void *p_dm_void,
|
||||
enum phydm_pause_type pause_type,
|
||||
enum phydm_pause_level pause_level,
|
||||
u8 cck_pd_threshold
|
||||
);
|
||||
|
||||
void
|
||||
odm_cck_packet_detection_thresh(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_write_cck_cca_thres(
|
||||
void *p_dm_void,
|
||||
u8 cur_cck_cca_thres
|
||||
);
|
||||
|
||||
bool
|
||||
phydm_dig_go_up_check(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void
|
||||
odm_mpt_dig_callback(
|
||||
struct timer_list *p_timer
|
||||
);
|
||||
|
||||
void
|
||||
odm_mpt_dig_work_item_callback(
|
||||
void *p_context
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
void
|
||||
odm_mpt_dig_callback(
|
||||
void *p_dm_void
|
||||
);
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_CE)
|
||||
void
|
||||
ODM_MPT_DIG(
|
||||
void *p_dm_void
|
||||
);
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
357
hal/phydm/phydm_dynamic_rx_path.c
Normal file
357
hal/phydm/phydm_dynamic_rx_path.c
Normal file
|
|
@ -0,0 +1,357 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* ************************************************************
|
||||
* include files
|
||||
* ************************************************************ */
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
#if (CONFIG_DYNAMIC_RX_PATH == 1)
|
||||
|
||||
void
|
||||
phydm_process_phy_status_for_dynamic_rx_path(
|
||||
void *p_dm_void,
|
||||
void *p_phy_info_void,
|
||||
void *p_pkt_info_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)p_phy_info_void;
|
||||
struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pkt_info_void;
|
||||
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table);
|
||||
/*u8 is_cck_rate=0;*/
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
phydm_drp_get_statistic(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table);
|
||||
struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT);
|
||||
|
||||
odm_false_alarm_counter_statistics(p_dm_odm);
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
|
||||
false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca, false_alm_cnt->cnt_cca_all));
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
|
||||
false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all));
|
||||
}
|
||||
|
||||
void
|
||||
phydm_dynamic_rx_path(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table);
|
||||
u8 training_set_timmer_en;
|
||||
u8 curr_drp_state;
|
||||
u32 rx_ok_cal;
|
||||
u32 RSSI = 0;
|
||||
struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT);
|
||||
|
||||
if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_RX_PATH)) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Return Init] Not Support Dynamic RX PAth\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("Current drp_state = ((%d))\n", p_dm_drp_table->drp_state));
|
||||
|
||||
curr_drp_state = p_dm_drp_table->drp_state;
|
||||
|
||||
if (p_dm_drp_table->drp_state == DRP_INIT_STATE) {
|
||||
|
||||
phydm_drp_get_statistic(p_dm_odm);
|
||||
|
||||
if (false_alm_cnt->cnt_crc32_ok_all > 20) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Stop DRP Training] cnt_crc32_ok_all = ((%d))\n", false_alm_cnt->cnt_crc32_ok_all));
|
||||
p_dm_drp_table->drp_state = DRP_INIT_STATE;
|
||||
training_set_timmer_en = false;
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Start DRP Training] cnt_crc32_ok_all = ((%d))\n", false_alm_cnt->cnt_crc32_ok_all));
|
||||
p_dm_drp_table->drp_state = DRP_TRAINING_STATE_0;
|
||||
p_dm_drp_table->curr_rx_path = PHYDM_AB;
|
||||
training_set_timmer_en = true;
|
||||
}
|
||||
|
||||
} else if (p_dm_drp_table->drp_state == DRP_TRAINING_STATE_0) {
|
||||
|
||||
phydm_drp_get_statistic(p_dm_odm);
|
||||
|
||||
p_dm_drp_table->curr_cca_all_cnt_0 = false_alm_cnt->cnt_cca_all;
|
||||
p_dm_drp_table->curr_fa_all_cnt_0 = false_alm_cnt->cnt_all;
|
||||
|
||||
p_dm_drp_table->drp_state = DRP_TRAINING_STATE_1;
|
||||
p_dm_drp_table->curr_rx_path = PHYDM_B;
|
||||
training_set_timmer_en = true;
|
||||
|
||||
} else if (p_dm_drp_table->drp_state == DRP_TRAINING_STATE_1) {
|
||||
|
||||
phydm_drp_get_statistic(p_dm_odm);
|
||||
|
||||
p_dm_drp_table->curr_cca_all_cnt_1 = false_alm_cnt->cnt_cca_all;
|
||||
p_dm_drp_table->curr_fa_all_cnt_1 = false_alm_cnt->cnt_all;
|
||||
|
||||
#if 1
|
||||
p_dm_drp_table->drp_state = DRP_DECISION_STATE;
|
||||
#else
|
||||
|
||||
if (p_dm_odm->mp_mode) {
|
||||
rx_ok_cal = p_dm_odm->phy_dbg_info.num_qry_phy_status_cck + p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm;
|
||||
RSSI = (rx_ok_cal != 0) ? p_dm_odm->rx_pwdb_ave / rx_ok_cal : 0;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("MP RSSI = ((%d))\n", RSSI));
|
||||
}
|
||||
|
||||
if (RSSI > p_dm_drp_table->rssi_threshold)
|
||||
|
||||
p_dm_drp_table->drp_state = DRP_DECISION_STATE;
|
||||
|
||||
else {
|
||||
|
||||
p_dm_drp_table->drp_state = DRP_TRAINING_STATE_2;
|
||||
p_dm_drp_table->curr_rx_path = PHYDM_A;
|
||||
training_set_timmer_en = true;
|
||||
}
|
||||
#endif
|
||||
} else if (p_dm_drp_table->drp_state == DRP_TRAINING_STATE_2) {
|
||||
|
||||
phydm_drp_get_statistic(p_dm_odm);
|
||||
|
||||
p_dm_drp_table->curr_cca_all_cnt_2 = false_alm_cnt->cnt_cca_all;
|
||||
p_dm_drp_table->curr_fa_all_cnt_2 = false_alm_cnt->cnt_all;
|
||||
p_dm_drp_table->drp_state = DRP_DECISION_STATE;
|
||||
}
|
||||
|
||||
if (p_dm_drp_table->drp_state == DRP_DECISION_STATE) {
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("Current drp_state = ((%d))\n", p_dm_drp_table->drp_state));
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[0] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_0, p_dm_drp_table->curr_fa_all_cnt_0));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[1] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_1, p_dm_drp_table->curr_fa_all_cnt_1));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[2] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_2, p_dm_drp_table->curr_fa_all_cnt_2));
|
||||
|
||||
if (p_dm_drp_table->curr_fa_all_cnt_1 < p_dm_drp_table->curr_fa_all_cnt_0) {
|
||||
|
||||
if ((p_dm_drp_table->curr_fa_all_cnt_0 - p_dm_drp_table->curr_fa_all_cnt_1) > p_dm_drp_table->fa_diff_threshold)
|
||||
p_dm_drp_table->curr_rx_path = PHYDM_B;
|
||||
else
|
||||
p_dm_drp_table->curr_rx_path = PHYDM_AB;
|
||||
} else
|
||||
p_dm_drp_table->curr_rx_path = PHYDM_AB;
|
||||
|
||||
phydm_config_ofdm_rx_path(p_dm_odm, p_dm_drp_table->curr_rx_path);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Training Result] curr_rx_path = ((%s%s)),\n",
|
||||
((p_dm_drp_table->curr_rx_path & PHYDM_A) ? "A" : " "), ((p_dm_drp_table->curr_rx_path & PHYDM_B) ? "B" : " ")));
|
||||
|
||||
p_dm_drp_table->drp_state = DRP_INIT_STATE;
|
||||
training_set_timmer_en = false;
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("DRP_state: ((%d)) -> ((%d))\n", curr_drp_state, p_dm_drp_table->drp_state));
|
||||
|
||||
if (training_set_timmer_en) {
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Training en] curr_rx_path = ((%s%s)), training_time = ((%d ms))\n",
|
||||
((p_dm_drp_table->curr_rx_path & PHYDM_A) ? "A" : " "), ((p_dm_drp_table->curr_rx_path & PHYDM_B) ? "B" : " "), p_dm_drp_table->training_time));
|
||||
|
||||
phydm_config_ofdm_rx_path(p_dm_odm, p_dm_drp_table->curr_rx_path);
|
||||
odm_set_timer(p_dm_odm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer), p_dm_drp_table->training_time); /*ms*/
|
||||
} else
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("DRP period end\n\n", curr_drp_state, p_dm_drp_table->drp_state));
|
||||
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void
|
||||
phydm_dynamic_rx_path_callback(
|
||||
struct timer_list *p_timer
|
||||
)
|
||||
{
|
||||
struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->adapter;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &(p_hal_data->DM_OutSrc);
|
||||
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table);
|
||||
|
||||
#if DEV_BUS_TYPE == RT_PCI_INTERFACE
|
||||
#if USE_WORKITEM
|
||||
odm_schedule_work_item(&(p_dm_drp_table->phydm_dynamic_rx_path_workitem));
|
||||
#else
|
||||
{
|
||||
/* dbg_print("phydm_dynamic_rx_path\n"); */
|
||||
phydm_dynamic_rx_path(p_dm_odm);
|
||||
}
|
||||
#endif
|
||||
#else
|
||||
odm_schedule_work_item(&(p_dm_drp_table->phydm_dynamic_rx_path_workitem));
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
phydm_dynamic_rx_path_workitem_callback(
|
||||
void *p_context
|
||||
)
|
||||
{
|
||||
struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &(p_hal_data->DM_OutSrc);
|
||||
|
||||
/* dbg_print("phydm_dynamic_rx_path\n"); */
|
||||
phydm_dynamic_rx_path(p_dm_odm);
|
||||
}
|
||||
#else if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
|
||||
void
|
||||
phydm_dynamic_rx_path_callback(
|
||||
void *function_context
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)function_context;
|
||||
struct _ADAPTER *padapter = p_dm_odm->adapter;
|
||||
|
||||
if (padapter->net_closed == _TRUE)
|
||||
return;
|
||||
|
||||
#if 0 /* Can't do I/O in timer callback*/
|
||||
odm_s0s1_sw_ant_div(p_dm_odm, SWAW_STEP_DETERMINE);
|
||||
#else
|
||||
/*rtw_run_in_thread_cmd(padapter, odm_sw_antdiv_workitem_callback, padapter);*/
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
void
|
||||
phydm_dynamic_rx_path_timers(
|
||||
void *p_dm_void,
|
||||
u8 state
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table);
|
||||
|
||||
if (state == INIT_DRP_TIMMER) {
|
||||
|
||||
odm_initialize_timer(p_dm_odm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer),
|
||||
(void *)phydm_dynamic_rx_path_callback, NULL, "phydm_sw_antenna_switch_timer");
|
||||
} else if (state == CANCEL_DRP_TIMMER)
|
||||
|
||||
odm_cancel_timer(p_dm_odm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer));
|
||||
|
||||
else if (state == RELEASE_DRP_TIMMER)
|
||||
|
||||
odm_release_timer(p_dm_odm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer));
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
phydm_dynamic_rx_path_init(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table);
|
||||
bool ret_value;
|
||||
|
||||
if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_RX_PATH)) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Return] Not Support Dynamic RX PAth\n"));
|
||||
return;
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("phydm_dynamic_rx_path_init\n"));
|
||||
|
||||
p_dm_drp_table->drp_state = DRP_INIT_STATE;
|
||||
p_dm_drp_table->rssi_threshold = DRP_RSSI_TH;
|
||||
p_dm_drp_table->fa_count_thresold = 50;
|
||||
p_dm_drp_table->fa_diff_threshold = 50;
|
||||
p_dm_drp_table->training_time = 100; /*ms*/
|
||||
p_dm_drp_table->drp_skip_counter = 0;
|
||||
p_dm_drp_table->drp_period = 0;
|
||||
p_dm_drp_table->drp_init_finished = true;
|
||||
|
||||
ret_value = phydm_api_trx_mode(p_dm_odm, (enum odm_rf_path_e)(ODM_RF_A | ODM_RF_B), (enum odm_rf_path_e)(ODM_RF_A | ODM_RF_B), true);
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
phydm_drp_debug(
|
||||
void *p_dm_void,
|
||||
u32 *const dm_value,
|
||||
u32 *_used,
|
||||
char *output,
|
||||
u32 *_out_len
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u32 used = *_used;
|
||||
u32 out_len = *_out_len;
|
||||
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table);
|
||||
|
||||
switch (dm_value[0]) {
|
||||
|
||||
case DRP_TRAINING_TIME:
|
||||
p_dm_drp_table->training_time = (u16)dm_value[1];
|
||||
break;
|
||||
case DRP_TRAINING_PERIOD:
|
||||
p_dm_drp_table->drp_period = (u8)dm_value[1];
|
||||
break;
|
||||
case DRP_RSSI_THRESHOLD:
|
||||
p_dm_drp_table->rssi_threshold = (u8)dm_value[1];
|
||||
break;
|
||||
case DRP_FA_THRESHOLD:
|
||||
p_dm_drp_table->fa_count_thresold = dm_value[1];
|
||||
break;
|
||||
case DRP_FA_DIFF_THRESHOLD:
|
||||
p_dm_drp_table->fa_diff_threshold = dm_value[1];
|
||||
break;
|
||||
default:
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "[DRP] unknown command\n"));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
phydm_dynamic_rx_path_caller(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table);
|
||||
|
||||
if (p_dm_drp_table->drp_skip_counter < p_dm_drp_table->drp_period)
|
||||
p_dm_drp_table->drp_skip_counter++;
|
||||
else
|
||||
p_dm_drp_table->drp_skip_counter = 0;
|
||||
|
||||
if (p_dm_drp_table->drp_skip_counter != 0)
|
||||
return;
|
||||
|
||||
if (p_dm_drp_table->drp_init_finished != true)
|
||||
return;
|
||||
|
||||
phydm_dynamic_rx_path(p_dm_odm);
|
||||
|
||||
}
|
||||
#endif
|
||||
137
hal/phydm/phydm_dynamic_rx_path.h
Normal file
137
hal/phydm/phydm_dynamic_rx_path.h
Normal file
|
|
@ -0,0 +1,137 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMDYMICRXPATH_H__
|
||||
#define __PHYDMDYMICRXPATH_H__
|
||||
|
||||
#define DYNAMIC_RX_PATH_VERSION "1.0" /*2016.07.15 Dino */
|
||||
|
||||
|
||||
#define DRP_RSSI_TH 35
|
||||
|
||||
#define INIT_DRP_TIMMER 0
|
||||
#define CANCEL_DRP_TIMMER 1
|
||||
#define RELEASE_DRP_TIMMER 2
|
||||
|
||||
#if (CONFIG_DYNAMIC_RX_PATH == 1)
|
||||
|
||||
enum drp_state_e {
|
||||
DRP_INIT_STATE = 0,
|
||||
DRP_TRAINING_STATE_0 = 1,
|
||||
DRP_TRAINING_STATE_1 = 2,
|
||||
DRP_TRAINING_STATE_2 = 3,
|
||||
DRP_DECISION_STATE = 4
|
||||
};
|
||||
|
||||
enum adjustable_value_e {
|
||||
DRP_TRAINING_TIME = 0,
|
||||
DRP_TRAINING_PERIOD = 1,
|
||||
DRP_RSSI_THRESHOLD = 2,
|
||||
DRP_FA_THRESHOLD = 3,
|
||||
DRP_FA_DIFF_THRESHOLD = 4
|
||||
};
|
||||
|
||||
struct _DYNAMIC_RX_PATH_ {
|
||||
u8 curr_rx_path;
|
||||
u8 drp_state;
|
||||
u16 training_time;
|
||||
u8 rssi_threshold;
|
||||
u32 fa_count_thresold;
|
||||
u32 fa_diff_threshold;
|
||||
u32 curr_cca_all_cnt_0;
|
||||
u32 curr_fa_all_cnt_0;
|
||||
u32 curr_cca_all_cnt_1;
|
||||
u32 curr_fa_all_cnt_1;
|
||||
u32 curr_cca_all_cnt_2;
|
||||
u32 curr_fa_all_cnt_2;
|
||||
u8 drp_skip_counter;
|
||||
u8 drp_period;
|
||||
u8 drp_init_finished;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#if USE_WORKITEM
|
||||
RT_WORK_ITEM phydm_dynamic_rx_path_workitem;
|
||||
#endif
|
||||
#endif
|
||||
struct timer_list phydm_dynamic_rx_path_timer;
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
void
|
||||
phydm_process_phy_status_for_dynamic_rx_path(
|
||||
void *p_dm_void,
|
||||
void *p_phy_info_void,
|
||||
void *p_pkt_info_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_dynamic_rx_path(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void
|
||||
phydm_dynamic_rx_path_callback(
|
||||
struct timer_list *p_timer
|
||||
);
|
||||
|
||||
void
|
||||
phydm_dynamic_rx_path_workitem_callback(
|
||||
void *p_context
|
||||
);
|
||||
|
||||
#else if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
|
||||
void
|
||||
phydm_dynamic_rx_path_callback(
|
||||
void *function_context
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
void
|
||||
phydm_dynamic_rx_path_timers(
|
||||
void *p_dm_void,
|
||||
u8 state
|
||||
);
|
||||
|
||||
void
|
||||
phydm_dynamic_rx_path_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_drp_debug(
|
||||
void *p_dm_void,
|
||||
u32 *const dm_value,
|
||||
u32 *_used,
|
||||
char *output,
|
||||
u32 *_out_len
|
||||
);
|
||||
|
||||
void
|
||||
phydm_dynamic_rx_path_caller(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
111
hal/phydm/phydm_dynamicbbpowersaving.c
Normal file
111
hal/phydm/phydm_dynamicbbpowersaving.c
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* ************************************************************
|
||||
* include files
|
||||
* ************************************************************ */
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
#if (defined(CONFIG_BB_POWER_SAVING))
|
||||
|
||||
void
|
||||
odm_dynamic_bb_power_saving_init(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _dynamic_power_saving *p_dm_ps_table = &p_dm_odm->dm_ps_table;
|
||||
|
||||
p_dm_ps_table->pre_cca_state = CCA_MAX;
|
||||
p_dm_ps_table->cur_cca_state = CCA_MAX;
|
||||
p_dm_ps_table->pre_rf_state = RF_MAX;
|
||||
p_dm_ps_table->cur_rf_state = RF_MAX;
|
||||
p_dm_ps_table->rssi_val_min = 0;
|
||||
p_dm_ps_table->initialize = 0;
|
||||
}
|
||||
|
||||
void
|
||||
odm_rf_saving(
|
||||
void *p_dm_void,
|
||||
u8 is_force_in_normal
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
|
||||
struct _dynamic_power_saving *p_dm_ps_table = &p_dm_odm->dm_ps_table;
|
||||
u8 rssi_up_bound = 30 ;
|
||||
u8 rssi_low_bound = 25;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
if (p_dm_odm->patch_id == 40) { /* RT_CID_819x_FUNAI_TV */
|
||||
rssi_up_bound = 50 ;
|
||||
rssi_low_bound = 45;
|
||||
}
|
||||
#endif
|
||||
if (p_dm_ps_table->initialize == 0) {
|
||||
|
||||
p_dm_ps_table->reg874 = (odm_get_bb_reg(p_dm_odm, 0x874, MASKDWORD) & 0x1CC000) >> 14;
|
||||
p_dm_ps_table->regc70 = (odm_get_bb_reg(p_dm_odm, 0xc70, MASKDWORD) & BIT(3)) >> 3;
|
||||
p_dm_ps_table->reg85c = (odm_get_bb_reg(p_dm_odm, 0x85c, MASKDWORD) & 0xFF000000) >> 24;
|
||||
p_dm_ps_table->rega74 = (odm_get_bb_reg(p_dm_odm, 0xa74, MASKDWORD) & 0xF000) >> 12;
|
||||
/* Reg818 = phy_query_bb_reg(p_adapter, 0x818, MASKDWORD); */
|
||||
p_dm_ps_table->initialize = 1;
|
||||
}
|
||||
|
||||
if (!is_force_in_normal) {
|
||||
if (p_dm_odm->rssi_min != 0xFF) {
|
||||
if (p_dm_ps_table->pre_rf_state == rf_normal) {
|
||||
if (p_dm_odm->rssi_min >= rssi_up_bound)
|
||||
p_dm_ps_table->cur_rf_state = rf_save;
|
||||
else
|
||||
p_dm_ps_table->cur_rf_state = rf_normal;
|
||||
} else {
|
||||
if (p_dm_odm->rssi_min <= rssi_low_bound)
|
||||
p_dm_ps_table->cur_rf_state = rf_normal;
|
||||
else
|
||||
p_dm_ps_table->cur_rf_state = rf_save;
|
||||
}
|
||||
} else
|
||||
p_dm_ps_table->cur_rf_state = RF_MAX;
|
||||
} else
|
||||
p_dm_ps_table->cur_rf_state = rf_normal;
|
||||
|
||||
if (p_dm_ps_table->pre_rf_state != p_dm_ps_table->cur_rf_state) {
|
||||
if (p_dm_ps_table->cur_rf_state == rf_save) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x874, 0x1C0000, 0x2); /* reg874[20:18]=3'b010 */
|
||||
odm_set_bb_reg(p_dm_odm, 0xc70, BIT(3), 0); /* regc70[3]=1'b0 */
|
||||
odm_set_bb_reg(p_dm_odm, 0x85c, 0xFF000000, 0x63); /* reg85c[31:24]=0x63 */
|
||||
odm_set_bb_reg(p_dm_odm, 0x874, 0xC000, 0x2); /* reg874[15:14]=2'b10 */
|
||||
odm_set_bb_reg(p_dm_odm, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */
|
||||
odm_set_bb_reg(p_dm_odm, 0x818, BIT(28), 0x0); /* Reg818[28]=1'b0 */
|
||||
odm_set_bb_reg(p_dm_odm, 0x818, BIT(28), 0x1); /* Reg818[28]=1'b1 */
|
||||
} else {
|
||||
odm_set_bb_reg(p_dm_odm, 0x874, 0x1CC000, p_dm_ps_table->reg874);
|
||||
odm_set_bb_reg(p_dm_odm, 0xc70, BIT(3), p_dm_ps_table->regc70);
|
||||
odm_set_bb_reg(p_dm_odm, 0x85c, 0xFF000000, p_dm_ps_table->reg85c);
|
||||
odm_set_bb_reg(p_dm_odm, 0xa74, 0xF000, p_dm_ps_table->rega74);
|
||||
odm_set_bb_reg(p_dm_odm, 0x818, BIT(28), 0x0);
|
||||
}
|
||||
p_dm_ps_table->pre_rf_state = p_dm_ps_table->cur_rf_state;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
57
hal/phydm/phydm_dynamicbbpowersaving.h
Normal file
57
hal/phydm/phydm_dynamicbbpowersaving.h
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMDYNAMICBBPOWERSAVING_H__
|
||||
#define __PHYDMDYNAMICBBPOWERSAVING_H__
|
||||
|
||||
#define DYNAMIC_BBPWRSAV_VERSION "1.1"
|
||||
|
||||
#if (defined(CONFIG_BB_POWER_SAVING))
|
||||
|
||||
struct _dynamic_power_saving {
|
||||
u8 pre_cca_state;
|
||||
u8 cur_cca_state;
|
||||
|
||||
u8 pre_rf_state;
|
||||
u8 cur_rf_state;
|
||||
|
||||
int rssi_val_min;
|
||||
|
||||
u8 initialize;
|
||||
u32 reg874, regc70, reg85c, rega74;
|
||||
|
||||
};
|
||||
|
||||
#define dm_rf_saving odm_rf_saving
|
||||
|
||||
void odm_rf_saving(
|
||||
void *p_dm_void,
|
||||
u8 is_force_in_normal
|
||||
);
|
||||
|
||||
void
|
||||
odm_dynamic_bb_power_saving_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
#else
|
||||
#define dm_rf_saving(p_dm_void, is_force_in_normal)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
535
hal/phydm/phydm_dynamictxpower.c
Normal file
535
hal/phydm/phydm_dynamictxpower.c
Normal file
|
|
@ -0,0 +1,535 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* ************************************************************
|
||||
* include files
|
||||
* ************************************************************ */
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
void
|
||||
odm_dynamic_tx_power_init(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
PMGNT_INFO p_mgnt_info = &adapter->MgntInfo;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
|
||||
/*if (!IS_HARDWARE_TYPE_8814A(adapter)) {*/
|
||||
/* ODM_RT_TRACE(p_dm_odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, */
|
||||
/* ("odm_dynamic_tx_power_init DynamicTxPowerEnable=%d\n", p_mgnt_info->is_dynamic_tx_power_enable));*/
|
||||
/* return;*/
|
||||
/*} else*/
|
||||
{
|
||||
p_mgnt_info->bDynamicTxPowerEnable = true;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD,
|
||||
("odm_dynamic_tx_power_init DynamicTxPowerEnable=%d\n", p_mgnt_info->bDynamicTxPowerEnable));
|
||||
}
|
||||
|
||||
#if DEV_BUS_TYPE == RT_USB_INTERFACE
|
||||
if (RT_GetInterfaceSelection(adapter) == INTF_SEL1_USB_High_Power) {
|
||||
odm_dynamic_tx_power_save_power_index(p_dm_odm);
|
||||
p_mgnt_info->bDynamicTxPowerEnable = true;
|
||||
} else
|
||||
#else
|
||||
/* so 92c pci do not need dynamic tx power? vivi check it later */
|
||||
p_mgnt_info->bDynamicTxPowerEnable = false;
|
||||
#endif
|
||||
|
||||
|
||||
p_hal_data->LastDTPLvl = tx_high_pwr_level_normal;
|
||||
p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
|
||||
p_dm_odm->last_dtp_lvl = tx_high_pwr_level_normal;
|
||||
p_dm_odm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal;
|
||||
p_dm_odm->tx_agc_ofdm_18_6 = odm_get_bb_reg(p_dm_odm, 0xC24, MASKDWORD); /*TXAGC {18M 12M 9M 6M}*/
|
||||
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
odm_dynamic_tx_power_save_power_index(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
|
||||
u8 index;
|
||||
u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
for (index = 0; index < 6; index++)
|
||||
p_hal_data->PowerIndex_backup[index] = PlatformEFIORead1Byte(adapter, power_index_reg[index]);
|
||||
|
||||
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
odm_dynamic_tx_power_restore_power_index(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
|
||||
u8 index;
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
for (index = 0; index < 6; index++)
|
||||
PlatformEFIOWrite1Byte(adapter, power_index_reg[index], p_hal_data->PowerIndex_backup[index]);
|
||||
|
||||
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
odm_dynamic_tx_power_write_power_index(
|
||||
void *p_dm_void,
|
||||
u8 value)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u8 index;
|
||||
u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
|
||||
|
||||
for (index = 0; index < 6; index++)
|
||||
/* platform_efio_write_1byte(adapter, power_index_reg[index], value); */
|
||||
odm_write_1byte(p_dm_odm, power_index_reg[index], value);
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
odm_dynamic_tx_power_nic_ce(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
|
||||
#if (RTL8821A_SUPPORT == 1)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u8 val;
|
||||
u8 rssi_tmp = p_dm_odm->rssi_min;
|
||||
|
||||
if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_TXPWR))
|
||||
return;
|
||||
|
||||
if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
|
||||
p_dm_odm->dynamic_tx_high_power_lvl = tx_high_pwr_level_level2;
|
||||
/**/
|
||||
} else if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL1) {
|
||||
p_dm_odm->dynamic_tx_high_power_lvl = tx_high_pwr_level_level1;
|
||||
/**/
|
||||
} else if (rssi_tmp < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
|
||||
p_dm_odm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal;
|
||||
/**/
|
||||
}
|
||||
|
||||
if (p_dm_odm->last_dtp_lvl != p_dm_odm->dynamic_tx_high_power_lvl) {
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("update_DTP_lv: ((%d)) -> ((%d))\n", p_dm_odm->last_dtp_lvl, p_dm_odm->dynamic_tx_high_power_lvl));
|
||||
|
||||
p_dm_odm->last_dtp_lvl = p_dm_odm->dynamic_tx_high_power_lvl;
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8821)) {
|
||||
|
||||
if (p_dm_odm->dynamic_tx_high_power_lvl == tx_high_pwr_level_level2) {
|
||||
|
||||
odm_set_mac_reg(p_dm_odm, 0x6D8, BIT(20) | BIT19 | BIT18, 1); /* Resp TXAGC offset = -3dB*/
|
||||
|
||||
val = p_dm_odm->tx_agc_ofdm_18_6 & 0xff;
|
||||
if (val >= 0x20)
|
||||
val -= 0x16;
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, 0xC24, 0xff, val);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: level 2\n"));
|
||||
} else if (p_dm_odm->dynamic_tx_high_power_lvl == tx_high_pwr_level_level1) {
|
||||
|
||||
odm_set_mac_reg(p_dm_odm, 0x6D8, BIT(20) | BIT19 | BIT18, 1); /* Resp TXAGC offset = -3dB*/
|
||||
|
||||
val = p_dm_odm->tx_agc_ofdm_18_6 & 0xff;
|
||||
if (val >= 0x20)
|
||||
val -= 0x10;
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, 0xC24, 0xff, val);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: level 1\n"));
|
||||
} else if (p_dm_odm->dynamic_tx_high_power_lvl == tx_high_pwr_level_normal) {
|
||||
|
||||
odm_set_mac_reg(p_dm_odm, 0x6D8, BIT(20) | BIT19 | BIT18, 0); /* Resp TXAGC offset = 0dB*/
|
||||
odm_set_bb_reg(p_dm_odm, 0xC24, MASKDWORD, p_dm_odm->tx_agc_ofdm_18_6);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: normal\n"));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_dynamic_tx_power(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
/* */
|
||||
/* For AP/ADSL use struct rtl8192cd_priv* */
|
||||
/* For CE/NIC use struct _ADAPTER* */
|
||||
/* */
|
||||
/* struct _ADAPTER* p_adapter = p_dm_odm->adapter;
|
||||
* struct rtl8192cd_priv* priv = p_dm_odm->priv; */
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_TXPWR))
|
||||
return;
|
||||
/* */
|
||||
/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
|
||||
/* at the same time. In the stage2/3, we need to prive universal interface and merge all */
|
||||
/* HW dynamic mechanism. */
|
||||
/* */
|
||||
switch (p_dm_odm->support_platform) {
|
||||
case ODM_WIN:
|
||||
odm_dynamic_tx_power_nic(p_dm_odm);
|
||||
break;
|
||||
case ODM_CE:
|
||||
odm_dynamic_tx_power_nic_ce(p_dm_odm);
|
||||
break;
|
||||
case ODM_AP:
|
||||
odm_dynamic_tx_power_ap(p_dm_odm);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_dynamic_tx_power_nic(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
|
||||
if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_TXPWR))
|
||||
return;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8814A)
|
||||
odm_dynamic_tx_power_8814a(p_dm_odm);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8821) {
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
PMGNT_INFO p_mgnt_info = GetDefaultMgntInfo(adapter);
|
||||
|
||||
if (p_mgnt_info->RegRspPwr == 1) {
|
||||
if (p_dm_odm->rssi_min > 60)
|
||||
odm_set_mac_reg(p_dm_odm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT19 | BIT18, 1); /*Resp TXAGC offset = -3dB*/
|
||||
else if (p_dm_odm->rssi_min < 55)
|
||||
odm_set_mac_reg(p_dm_odm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT19 | BIT18, 0); /*Resp TXAGC offset = 0dB*/
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
odm_dynamic_tx_power_ap(
|
||||
void *p_dm_void
|
||||
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
|
||||
/* #if ((RTL8192C_SUPPORT==1) || (RTL8192D_SUPPORT==1) || (RTL8188E_SUPPORT==1) || (RTL8812E_SUPPORT==1)) */
|
||||
|
||||
|
||||
struct rtl8192cd_priv *priv = p_dm_odm->priv;
|
||||
s32 i;
|
||||
s16 pwr_thd = 63;
|
||||
|
||||
if (!priv->pshare->rf_ft_var.tx_pwr_ctrl)
|
||||
return;
|
||||
|
||||
#if ((RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1))
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A))
|
||||
pwr_thd = TX_POWER_NEAR_FIELD_THRESH_LVL1;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Check if station is near by to use lower tx power
|
||||
*/
|
||||
|
||||
if ((priv->up_time % 3) == 0) {
|
||||
int disable_pwr_ctrl = ((p_dm_odm->false_alm_cnt.cnt_all > 1000) || ((p_dm_odm->false_alm_cnt.cnt_all > 300) && ((RTL_R8(0xc50) & 0x7f) >= 0x32))) ? 1 : 0;
|
||||
|
||||
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
|
||||
struct sta_info *pstat = p_dm_odm->p_odm_sta_info[i];
|
||||
if (IS_STA_VALID(pstat)) {
|
||||
if (disable_pwr_ctrl)
|
||||
pstat->hp_level = 0;
|
||||
else if ((pstat->hp_level == 0) && (pstat->rssi > pwr_thd))
|
||||
pstat->hp_level = 1;
|
||||
else if ((pstat->hp_level == 1) && (pstat->rssi < (pwr_thd - 8)))
|
||||
pstat->hp_level = 0;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_WLAN_HAL_8192EE)
|
||||
if (GET_CHIP_VER(priv) == VERSION_8192E) {
|
||||
if (!disable_pwr_ctrl && (p_dm_odm->rssi_min != 0xff)) {
|
||||
if (p_dm_odm->rssi_min > pwr_thd)
|
||||
RRSR_power_control_11n(priv, 1);
|
||||
else if (p_dm_odm->rssi_min < (pwr_thd - 8))
|
||||
RRSR_power_control_11n(priv, 0);
|
||||
} else
|
||||
RRSR_power_control_11n(priv, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_WLAN_HAL_8814AE
|
||||
if (GET_CHIP_VER(priv) == VERSION_8814A) {
|
||||
if (!disable_pwr_ctrl && (p_dm_odm->rssi_min != 0xff)) {
|
||||
if (p_dm_odm->rssi_min > pwr_thd)
|
||||
RRSR_power_control_14(priv, 1);
|
||||
else if (p_dm_odm->rssi_min < (pwr_thd - 8))
|
||||
RRSR_power_control_14(priv, 0);
|
||||
} else
|
||||
RRSR_power_control_14(priv, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
}
|
||||
/* #endif */
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
odm_dynamic_tx_power_8821(
|
||||
void *p_dm_void,
|
||||
u8 *p_desc,
|
||||
u8 mac_id
|
||||
)
|
||||
{
|
||||
#if (RTL8821A_SUPPORT == 1)
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct sta_info *p_entry;
|
||||
u8 reg0xc56_byte;
|
||||
u8 txpwr_offset = 0;
|
||||
|
||||
p_entry = p_dm_odm->p_odm_sta_info[mac_id];
|
||||
|
||||
reg0xc56_byte = odm_read_1byte(p_dm_odm, 0xc56);
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("reg0xc56_byte=%d\n", reg0xc56_byte));
|
||||
|
||||
if (p_entry[mac_id].rssi_stat.undecorated_smoothed_pwdb > 85) {
|
||||
|
||||
/* Avoid TXAGC error after TX power offset is applied.
|
||||
For example: Reg0xc56=0x6, if txpwr_offset=3( reduce 11dB )
|
||||
Total power = 6-11= -5( overflow!! ), PA may be burned !
|
||||
so txpwr_offset should be adjusted by Reg0xc56*/
|
||||
|
||||
if (reg0xc56_byte < 7)
|
||||
txpwr_offset = 1;
|
||||
else if (reg0xc56_byte < 11)
|
||||
txpwr_offset = 2;
|
||||
else
|
||||
txpwr_offset = 3;
|
||||
|
||||
SET_TX_DESC_TX_POWER_OFFSET_8812(p_desc, txpwr_offset);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_dynamic_tx_power_8821: RSSI=%d, txpwr_offset=%d\n", p_entry[mac_id].rssi_stat.undecorated_smoothed_pwdb, txpwr_offset));
|
||||
|
||||
} else {
|
||||
SET_TX_DESC_TX_POWER_OFFSET_8812(p_desc, txpwr_offset);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_dynamic_tx_power_8821: RSSI=%d, txpwr_offset=%d\n", p_entry[mac_id].rssi_stat.undecorated_smoothed_pwdb, txpwr_offset));
|
||||
|
||||
}
|
||||
#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
|
||||
#endif /*#if (RTL8821A_SUPPORT==1)*/
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void
|
||||
odm_dynamic_tx_power_8814a(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
PMGNT_INFO p_mgnt_info = &adapter->MgntInfo;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
s32 undecorated_smoothed_pwdb;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD,
|
||||
("TxLevel=%d p_mgnt_info->iot_action=%x p_mgnt_info->is_dynamic_tx_power_enable=%d\n",
|
||||
p_hal_data->DynamicTxHighPowerLvl, p_mgnt_info->IOTAction, p_mgnt_info->bDynamicTxPowerEnable));
|
||||
|
||||
/*STA not connected and AP not connected*/
|
||||
if ((!p_mgnt_info->bMediaConnect) && (p_hal_data->EntryMinUndecoratedSmoothedPWDB == 0)) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("Not connected to any reset power lvl\n"));
|
||||
p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
if ((p_mgnt_info->bDynamicTxPowerEnable != true) || p_mgnt_info->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)
|
||||
p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
|
||||
else {
|
||||
if (p_mgnt_info->bMediaConnect) { /*Default port*/
|
||||
if (ACTING_AS_AP(adapter) || ACTING_AS_IBSS(adapter)) {
|
||||
undecorated_smoothed_pwdb = p_hal_data->EntryMinUndecoratedSmoothedPWDB;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Client PWDB = 0x%x\n", undecorated_smoothed_pwdb));
|
||||
} else {
|
||||
undecorated_smoothed_pwdb = p_hal_data->UndecoratedSmoothedPWDB;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x\n", undecorated_smoothed_pwdb));
|
||||
}
|
||||
} else {/*associated entry pwdb*/
|
||||
undecorated_smoothed_pwdb = p_hal_data->EntryMinUndecoratedSmoothedPWDB;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x\n", undecorated_smoothed_pwdb));
|
||||
}
|
||||
|
||||
/*Should we separate as 2.4G/5G band?*/
|
||||
|
||||
if (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
|
||||
p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_level2;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("tx_high_pwr_level_level1 (TxPwr=0x0)\n"));
|
||||
} else if ((undecorated_smoothed_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
|
||||
(undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
|
||||
p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_level1;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("tx_high_pwr_level_level1 (TxPwr=0x10)\n"));
|
||||
} else if (undecorated_smoothed_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
|
||||
p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("tx_high_pwr_level_normal\n"));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if (p_hal_data->DynamicTxHighPowerLvl != p_hal_data->LastDTPLvl) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_dynamic_tx_power_8814a() channel = %d\n", p_hal_data->CurrentChannel));
|
||||
odm_set_tx_power_level8814(adapter, p_hal_data->CurrentChannel, p_hal_data->DynamicTxHighPowerLvl);
|
||||
}
|
||||
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD,
|
||||
("odm_dynamic_tx_power_8814a() channel = %d TXpower lvl=%d/%d\n",
|
||||
p_hal_data->CurrentChannel, p_hal_data->LastDTPLvl, p_hal_data->DynamicTxHighPowerLvl));
|
||||
|
||||
p_hal_data->LastDTPLvl = p_hal_data->DynamicTxHighPowerLvl;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**/
|
||||
/*For normal driver we always use the FW method to configure TX power index to reduce I/O transaction.*/
|
||||
/**/
|
||||
/**/
|
||||
void
|
||||
odm_set_tx_power_level8814(
|
||||
struct _ADAPTER *adapter,
|
||||
u8 channel,
|
||||
u8 pwr_lvl
|
||||
)
|
||||
{
|
||||
#if (DEV_BUS_TYPE == RT_USB_INTERFACE)
|
||||
u32 i, j, k = 0;
|
||||
u32 value[264] = {0};
|
||||
u32 path = 0, power_index, txagc_table_wd = 0x00801000;
|
||||
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
|
||||
u8 jaguar2_rates[][4] = { {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M},
|
||||
{MGN_6M, MGN_9M, MGN_12M, MGN_18M},
|
||||
{MGN_24M, MGN_36M, MGN_48M, MGN_54M},
|
||||
{MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3},
|
||||
{MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7},
|
||||
{MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11},
|
||||
{MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15},
|
||||
{MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19},
|
||||
{MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23},
|
||||
{MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3},
|
||||
{MGN_VHT1SS_MCS4, MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7},
|
||||
{MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9, MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1},
|
||||
{MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4, MGN_VHT2SS_MCS5},
|
||||
{MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9},
|
||||
{MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3},
|
||||
{MGN_VHT3SS_MCS4, MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7},
|
||||
{MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9, 0, 0}
|
||||
};
|
||||
|
||||
for (path = ODM_RF_PATH_A; path <= ODM_RF_PATH_D; ++path) {
|
||||
|
||||
u8 usb_host = UsbModeQueryHubUsbType(adapter);
|
||||
u8 usb_rfset = UsbModeQueryRfSet(adapter);
|
||||
u8 usb_rf_type = RT_GetRFType(adapter);
|
||||
|
||||
for (i = 0; i <= 16; i++) {
|
||||
for (j = 0; j <= 3; j++) {
|
||||
if (jaguar2_rates[i][j] == 0)
|
||||
continue;
|
||||
|
||||
txagc_table_wd = 0x00801000;
|
||||
power_index = (u32) PHY_GetTxPowerIndex(adapter, (u8)path, jaguar2_rates[i][j], p_hal_data->CurrentChannelBW, channel);
|
||||
|
||||
/*for Query bus type to recude tx power.*/
|
||||
if (usb_host != USB_MODE_U3 && usb_rfset == 1 && IS_HARDWARE_TYPE_8814AU(adapter) && usb_rf_type == RF_3T3R) {
|
||||
if (channel <= 14) {
|
||||
if (power_index >= 16)
|
||||
power_index -= 16;
|
||||
else
|
||||
power_index = 0;
|
||||
} else
|
||||
power_index = 0;
|
||||
}
|
||||
|
||||
if (pwr_lvl == tx_high_pwr_level_level1) {
|
||||
if (power_index >= 0x10)
|
||||
power_index -= 0x10;
|
||||
else
|
||||
power_index = 0;
|
||||
} else if (pwr_lvl == tx_high_pwr_level_level2)
|
||||
power_index = 0;
|
||||
|
||||
txagc_table_wd |= (path << 8) | MRateToHwRate(jaguar2_rates[i][j]) | (power_index << 24);
|
||||
|
||||
PHY_SetTxPowerIndexShadow(adapter, (u8)power_index, (u8)path, jaguar2_rates[i][j]);
|
||||
|
||||
value[k++] = txagc_table_wd;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (adapter->MgntInfo.bScanInProgress == false && adapter->MgntInfo.RegFWOffload == 2)
|
||||
HalDownloadTxPowerLevel8814(adapter, value);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
110
hal/phydm/phydm_dynamictxpower.h
Normal file
110
hal/phydm/phydm_dynamictxpower.h
Normal file
|
|
@ -0,0 +1,110 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMDYNAMICTXPOWER_H__
|
||||
#define __PHYDMDYNAMICTXPOWER_H__
|
||||
|
||||
/*#define DYNAMIC_TXPWR_VERSION "1.0"*/
|
||||
/*#define DYNAMIC_TXPWR_VERSION "1.3" */ /*2015.08.26, Add 8814 Dynamic TX power*/
|
||||
#define DYNAMIC_TXPWR_VERSION "1.4" /*2015.11.06, Add CE 8821A Dynamic TX power*/
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
|
||||
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60
|
||||
#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
|
||||
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
|
||||
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60
|
||||
#endif
|
||||
|
||||
#define tx_high_pwr_level_normal 0
|
||||
#define tx_high_pwr_level_level1 1
|
||||
#define tx_high_pwr_level_level2 2
|
||||
|
||||
#define tx_high_pwr_level_bt1 3
|
||||
#define tx_high_pwr_level_bt2 4
|
||||
#define tx_high_pwr_level_15 5
|
||||
#define tx_high_pwr_level_35 6
|
||||
#define tx_high_pwr_level_50 7
|
||||
#define tx_high_pwr_level_70 8
|
||||
#define tx_high_pwr_level_100 9
|
||||
|
||||
void
|
||||
odm_dynamic_tx_power_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_dynamic_tx_power_restore_power_index(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_dynamic_tx_power_nic(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
void
|
||||
odm_dynamic_tx_power_save_power_index(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_dynamic_tx_power_write_power_index(
|
||||
void *p_dm_void,
|
||||
u8 value);
|
||||
|
||||
void
|
||||
odm_dynamic_tx_power_8821(
|
||||
void *p_dm_void,
|
||||
u8 *p_desc,
|
||||
u8 mac_id
|
||||
);
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void
|
||||
odm_dynamic_tx_power_8814a(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
odm_set_tx_power_level8814(
|
||||
struct _ADAPTER *adapter,
|
||||
u8 channel,
|
||||
u8 pwr_lvl
|
||||
);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
void
|
||||
odm_dynamic_tx_power(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_dynamic_tx_power_ap(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
#endif
|
||||
698
hal/phydm/phydm_edcaturbocheck.c
Normal file
698
hal/phydm/phydm_edcaturbocheck.c
Normal file
|
|
@ -0,0 +1,698 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* ************************************************************
|
||||
* include files
|
||||
* ************************************************************ */
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
#if PHYDM_SUPPORT_EDCA
|
||||
|
||||
void
|
||||
odm_edca_turbo_init(
|
||||
void *p_dm_void)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter = NULL;
|
||||
HAL_DATA_TYPE *p_hal_data = NULL;
|
||||
|
||||
if (p_dm_odm->adapter == NULL) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("EdcaTurboInit fail!!!\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
adapter = p_dm_odm->adapter;
|
||||
p_hal_data = GET_HAL_DATA(adapter);
|
||||
|
||||
p_dm_odm->dm_edca_table.is_current_turbo_edca = false;
|
||||
p_dm_odm->dm_edca_table.is_cur_rdl_state = false;
|
||||
p_hal_data->is_any_non_be_pkts = false;
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
p_dm_odm->dm_edca_table.is_current_turbo_edca = false;
|
||||
p_dm_odm->dm_edca_table.is_cur_rdl_state = false;
|
||||
adapter->recvpriv.is_any_non_be_pkts = false;
|
||||
|
||||
#endif
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_VO_PARAM)));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_VI_PARAM)));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_BE_PARAM)));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_BK_PARAM)));
|
||||
|
||||
|
||||
} /* ODM_InitEdcaTurbo */
|
||||
|
||||
void
|
||||
odm_edca_turbo_check(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
/* */
|
||||
/* For AP/ADSL use struct rtl8192cd_priv* */
|
||||
/* For CE/NIC use struct _ADAPTER* */
|
||||
/* */
|
||||
|
||||
/* */
|
||||
/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
|
||||
/* at the same time. In the stage2/3, we need to prive universal interface and merge all */
|
||||
/* HW dynamic mechanism. */
|
||||
/* */
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_edca_turbo_check========================>\n"));
|
||||
|
||||
if (!(p_dm_odm->support_ability & ODM_MAC_EDCA_TURBO))
|
||||
return;
|
||||
|
||||
switch (p_dm_odm->support_platform) {
|
||||
case ODM_WIN:
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
odm_edca_turbo_check_mp(p_dm_odm);
|
||||
#endif
|
||||
break;
|
||||
|
||||
case ODM_CE:
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
odm_edca_turbo_check_ce(p_dm_odm);
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("<========================odm_edca_turbo_check\n"));
|
||||
|
||||
} /* odm_CheckEdcaTurbo */
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
|
||||
|
||||
void
|
||||
odm_edca_turbo_check_ce(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
u32 EDCA_BE_UL = 0x5ea42b;/* Parameter suggested by Scott */ /* edca_setting_UL[p_mgnt_info->iot_peer]; */
|
||||
u32 EDCA_BE_DL = 0x00a42b;/* Parameter suggested by Scott */ /* edca_setting_DL[p_mgnt_info->iot_peer]; */
|
||||
u32 ic_type = p_dm_odm->support_ic_type;
|
||||
u32 iot_peer = 0;
|
||||
u8 wireless_mode = 0xFF; /* invalid value */
|
||||
u32 traffic_index;
|
||||
u32 edca_param;
|
||||
u64 cur_tx_bytes = 0;
|
||||
u64 cur_rx_bytes = 0;
|
||||
u8 bbtchange = _TRUE;
|
||||
u8 is_bias_on_rx = _FALSE;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter);
|
||||
struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
|
||||
struct recv_priv *precvpriv = &(adapter->recvpriv);
|
||||
struct registry_priv *pregpriv = &adapter->registrypriv;
|
||||
struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
|
||||
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
|
||||
|
||||
if (p_dm_odm->is_linked != _TRUE) {
|
||||
precvpriv->is_any_non_be_pkts = _FALSE;
|
||||
return;
|
||||
}
|
||||
|
||||
if ((pregpriv->wifi_spec == 1)) { /* || (pmlmeinfo->HT_enable == 0)) */
|
||||
precvpriv->is_any_non_be_pkts = _FALSE;
|
||||
return;
|
||||
}
|
||||
|
||||
if (p_dm_odm->p_wireless_mode != NULL)
|
||||
wireless_mode = *(p_dm_odm->p_wireless_mode);
|
||||
|
||||
iot_peer = pmlmeinfo->assoc_AP_vendor;
|
||||
|
||||
if (iot_peer >= HT_IOT_PEER_MAX) {
|
||||
precvpriv->is_any_non_be_pkts = _FALSE;
|
||||
return;
|
||||
}
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8188E) {
|
||||
if ((iot_peer == HT_IOT_PEER_RALINK) || (iot_peer == HT_IOT_PEER_ATHEROS))
|
||||
is_bias_on_rx = _TRUE;
|
||||
}
|
||||
|
||||
/* Check if the status needs to be changed. */
|
||||
if ((bbtchange) || (!precvpriv->is_any_non_be_pkts)) {
|
||||
cur_tx_bytes = pdvobjpriv->traffic_stat.cur_tx_bytes;
|
||||
cur_rx_bytes = pdvobjpriv->traffic_stat.cur_rx_bytes;
|
||||
|
||||
/* traffic, TX or RX */
|
||||
if (is_bias_on_rx) {
|
||||
if (cur_tx_bytes > (cur_rx_bytes << 2)) {
|
||||
/* Uplink TP is present. */
|
||||
traffic_index = UP_LINK;
|
||||
} else {
|
||||
/* Balance TP is present. */
|
||||
traffic_index = DOWN_LINK;
|
||||
}
|
||||
} else {
|
||||
if (cur_rx_bytes > (cur_tx_bytes << 2)) {
|
||||
/* Downlink TP is present. */
|
||||
traffic_index = DOWN_LINK;
|
||||
} else {
|
||||
/* Balance TP is present. */
|
||||
traffic_index = UP_LINK;
|
||||
}
|
||||
}
|
||||
|
||||
/* if ((p_dm_odm->dm_edca_table.prv_traffic_idx != traffic_index) || (!p_dm_odm->dm_edca_table.is_current_turbo_edca)) */
|
||||
{
|
||||
if (p_dm_odm->support_interface == ODM_ITRF_PCIE) {
|
||||
EDCA_BE_UL = 0x6ea42b;
|
||||
EDCA_BE_DL = 0x6ea42b;
|
||||
}
|
||||
|
||||
/* 92D txop can't be set to 0x3e for cisco1250 */
|
||||
if ((iot_peer == HT_IOT_PEER_CISCO) && (wireless_mode == ODM_WM_N24G)) {
|
||||
EDCA_BE_DL = edca_setting_DL[iot_peer];
|
||||
EDCA_BE_UL = edca_setting_UL[iot_peer];
|
||||
}
|
||||
/* merge from 92s_92c_merge temp brunch v2445 20120215 */
|
||||
else if ((iot_peer == HT_IOT_PEER_CISCO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == (ODM_WM_B | ODM_WM_G)) || (wireless_mode == ODM_WM_A) || (wireless_mode == ODM_WM_B)))
|
||||
EDCA_BE_DL = edca_setting_dl_g_mode[iot_peer];
|
||||
else if ((iot_peer == HT_IOT_PEER_AIRGO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == ODM_WM_A)))
|
||||
EDCA_BE_DL = 0xa630;
|
||||
else if (iot_peer == HT_IOT_PEER_MARVELL) {
|
||||
EDCA_BE_DL = edca_setting_DL[iot_peer];
|
||||
EDCA_BE_UL = edca_setting_UL[iot_peer];
|
||||
} else if (iot_peer == HT_IOT_PEER_ATHEROS) {
|
||||
/* Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue. */
|
||||
EDCA_BE_DL = edca_setting_DL[iot_peer];
|
||||
}
|
||||
|
||||
if ((ic_type == ODM_RTL8812) || (ic_type == ODM_RTL8821) || (ic_type == ODM_RTL8192E)) { /* add 8812AU/8812AE */
|
||||
EDCA_BE_UL = 0x5ea42b;
|
||||
EDCA_BE_DL = 0x5ea42b;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x", EDCA_BE_UL, EDCA_BE_DL));
|
||||
}
|
||||
|
||||
if (traffic_index == DOWN_LINK)
|
||||
edca_param = EDCA_BE_DL;
|
||||
else
|
||||
edca_param = EDCA_BE_UL;
|
||||
|
||||
rtw_write32(adapter, REG_EDCA_BE_PARAM, edca_param);
|
||||
|
||||
p_dm_odm->dm_edca_table.prv_traffic_idx = traffic_index;
|
||||
}
|
||||
|
||||
p_dm_odm->dm_edca_table.is_current_turbo_edca = _TRUE;
|
||||
} else {
|
||||
/* */
|
||||
/* Turn Off EDCA turbo here. */
|
||||
/* Restore original EDCA according to the declaration of AP. */
|
||||
/* */
|
||||
if (p_dm_odm->dm_edca_table.is_current_turbo_edca) {
|
||||
rtw_write32(adapter, REG_EDCA_BE_PARAM, p_hal_data->ac_param_be);
|
||||
p_dm_odm->dm_edca_table.is_current_turbo_edca = _FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void
|
||||
odm_edca_turbo_check_mp(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
|
||||
struct _ADAPTER *p_default_adapter = get_default_adapter(adapter);
|
||||
struct _ADAPTER *p_ext_adapter = get_first_ext_adapter(adapter); /* NULL; */
|
||||
PMGNT_INFO p_mgnt_info = &adapter->MgntInfo;
|
||||
PSTA_QOS p_sta_qos = adapter->MgntInfo.p_sta_qos;
|
||||
/* [Win7 count Tx/Rx statistic for Extension Port] odm_CheckEdcaTurbo's adapter is always Default. 2009.08.20, by Bohn */
|
||||
u64 ext_cur_tx_ok_cnt = 0;
|
||||
u64 ext_cur_rx_ok_cnt = 0;
|
||||
/* For future Win7 Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn. */
|
||||
u8 two_port_status = (u8)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE;
|
||||
|
||||
/* Keep past Tx/Rx packet count for RT-to-RT EDCA turbo. */
|
||||
u64 cur_tx_ok_cnt = 0;
|
||||
u64 cur_rx_ok_cnt = 0;
|
||||
u32 EDCA_BE_UL = 0x5ea42b;/* Parameter suggested by Scott */ /* edca_setting_UL[p_mgnt_info->iot_peer]; */
|
||||
u32 EDCA_BE_DL = 0x5ea42b;/* Parameter suggested by Scott */ /* edca_setting_DL[p_mgnt_info->iot_peer]; */
|
||||
u32 EDCA_BE = 0x5ea42b;
|
||||
u8 iot_peer = 0;
|
||||
bool *p_is_cur_rdl_state = NULL;
|
||||
bool is_last_is_cur_rdl_state = false;
|
||||
bool is_bias_on_rx = false;
|
||||
bool is_edca_turbo_on = false;
|
||||
u8 tx_rate = 0xFF;
|
||||
u64 value64;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_edca_turbo_check_mp========================>"));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_BE_PARAM)));
|
||||
|
||||
/* *******************************
|
||||
* list paramter for different platform
|
||||
* ******************************* */
|
||||
is_last_is_cur_rdl_state = p_dm_odm->dm_edca_table.is_cur_rdl_state;
|
||||
p_is_cur_rdl_state = &(p_dm_odm->dm_edca_table.is_cur_rdl_state);
|
||||
|
||||
/* 2012/09/14 MH Add */
|
||||
if (p_mgnt_info->num_non_be_pkt > p_mgnt_info->reg_edca_thresh && !(adapter->MgntInfo.wifi_confg & RT_WIFI_LOGO))
|
||||
p_hal_data->is_any_non_be_pkts = true;
|
||||
|
||||
p_mgnt_info->num_non_be_pkt = 0;
|
||||
|
||||
/* Caculate TX/RX TP: */
|
||||
cur_tx_ok_cnt = p_dm_odm->cur_tx_ok_cnt;
|
||||
cur_rx_ok_cnt = p_dm_odm->cur_rx_ok_cnt;
|
||||
|
||||
|
||||
if (p_ext_adapter == NULL)
|
||||
p_ext_adapter = p_default_adapter;
|
||||
|
||||
ext_cur_tx_ok_cnt = p_ext_adapter->tx_stats.num_tx_bytes_unicast - p_mgnt_info->ext_last_tx_ok_cnt;
|
||||
ext_cur_rx_ok_cnt = p_ext_adapter->rx_stats.num_rx_bytes_unicast - p_mgnt_info->ext_last_rx_ok_cnt;
|
||||
get_two_port_shared_resource(adapter, TWO_PORT_SHARED_OBJECT__STATUS, NULL, &two_port_status);
|
||||
/* For future Win7 Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn. */
|
||||
if (two_port_status == TWO_PORT_STATUS__EXTENSION_ONLY) {
|
||||
cur_tx_ok_cnt = ext_cur_tx_ok_cnt ;
|
||||
cur_rx_ok_cnt = ext_cur_rx_ok_cnt ;
|
||||
}
|
||||
/* */
|
||||
iot_peer = p_mgnt_info->iot_peer;
|
||||
is_bias_on_rx = (p_mgnt_info->iot_action & HT_IOT_ACT_EDCA_BIAS_ON_RX) ? true : false;
|
||||
is_edca_turbo_on = ((!p_hal_data->is_any_non_be_pkts)) ? true : false;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("is_any_non_be_pkts : 0x%lx\n", p_hal_data->is_any_non_be_pkts));
|
||||
|
||||
|
||||
/* *******************************
|
||||
* check if edca turbo is disabled
|
||||
* ******************************* */
|
||||
if (odm_is_edca_turbo_disable(p_dm_odm)) {
|
||||
p_hal_data->is_any_non_be_pkts = false;
|
||||
p_mgnt_info->last_tx_ok_cnt = adapter->tx_stats.num_tx_bytes_unicast;
|
||||
p_mgnt_info->last_rx_ok_cnt = adapter->rx_stats.num_rx_bytes_unicast;
|
||||
p_mgnt_info->ext_last_tx_ok_cnt = p_ext_adapter->tx_stats.num_tx_bytes_unicast;
|
||||
p_mgnt_info->ext_last_rx_ok_cnt = p_ext_adapter->rx_stats.num_rx_bytes_unicast;
|
||||
|
||||
}
|
||||
|
||||
/* *******************************
|
||||
* remove iot case out
|
||||
* ******************************* */
|
||||
odm_edca_para_sel_by_iot(p_dm_odm, &EDCA_BE_UL, &EDCA_BE_DL);
|
||||
|
||||
|
||||
/* *******************************
|
||||
* Check if the status needs to be changed.
|
||||
* ******************************* */
|
||||
if (is_edca_turbo_on) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("is_edca_turbo_on : 0x%x is_bias_on_rx : 0x%x\n", is_edca_turbo_on, is_bias_on_rx));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("cur_tx_ok_cnt : 0x%lx\n", cur_tx_ok_cnt));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("cur_rx_ok_cnt : 0x%lx\n", cur_rx_ok_cnt));
|
||||
if (is_bias_on_rx)
|
||||
odm_edca_choose_traffic_idx(p_dm_odm, cur_tx_ok_cnt, cur_rx_ok_cnt, true, p_is_cur_rdl_state);
|
||||
else
|
||||
odm_edca_choose_traffic_idx(p_dm_odm, cur_tx_ok_cnt, cur_rx_ok_cnt, false, p_is_cur_rdl_state);
|
||||
|
||||
/* modify by Guo.Mingzhi 2011-12-29 */
|
||||
if (adapter->AP_EDCA_PARAM[0] != EDCA_BE)
|
||||
EDCA_BE = adapter->AP_EDCA_PARAM[0];
|
||||
else
|
||||
EDCA_BE = ((*p_is_cur_rdl_state) == true) ? EDCA_BE_DL : EDCA_BE_UL;
|
||||
|
||||
/*For TPLINK 8188EU test*/
|
||||
if ((IS_HARDWARE_TYPE_8188EU(adapter)) && (p_hal_data->UndecoratedSmoothedPWDB < 28)) { /* Set to origimal EDCA 0x5EA42B now need to update.*/
|
||||
|
||||
} else { /*Use TPLINK preferred EDCA parameters.*/
|
||||
EDCA_BE = p_mgnt_info->EDCABEPara;
|
||||
}
|
||||
|
||||
if (IS_HARDWARE_TYPE_8821U(adapter)) {
|
||||
if (p_mgnt_info->reg_tx_duty_enable) {
|
||||
/* 2013.01.23 LukeLee: debug for 8811AU thermal issue (reduce Tx duty cycle) */
|
||||
if (!p_mgnt_info->forced_data_rate) { /* auto rate */
|
||||
if (p_dm_odm->tx_rate != 0xFF)
|
||||
tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(p_dm_odm->tx_rate);
|
||||
} else /* force rate */
|
||||
tx_rate = (u8) p_mgnt_info->forced_data_rate;
|
||||
|
||||
value64 = (cur_rx_ok_cnt << 2);
|
||||
if (cur_tx_ok_cnt < value64) /* Downlink */
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
|
||||
else { /* Uplink */
|
||||
/*dbg_print("p_rf_calibrate_info->thermal_value = 0x%X\n", p_rf_calibrate_info->thermal_value);*/
|
||||
/*if(p_rf_calibrate_info->thermal_value < p_hal_data->eeprom_thermal_meter)*/
|
||||
if ((p_dm_odm->rf_calibrate_info.thermal_value < 0x2c) || (*p_dm_odm->p_band_type == BAND_ON_2_4G))
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
|
||||
else {
|
||||
switch (tx_rate) {
|
||||
case MGN_VHT1SS_MCS6:
|
||||
case MGN_VHT1SS_MCS5:
|
||||
case MGN_MCS6:
|
||||
case MGN_MCS5:
|
||||
case MGN_48M:
|
||||
case MGN_54M:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0x1ea42b);
|
||||
break;
|
||||
case MGN_VHT1SS_MCS4:
|
||||
case MGN_MCS4:
|
||||
case MGN_36M:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa42b);
|
||||
break;
|
||||
case MGN_VHT1SS_MCS3:
|
||||
case MGN_MCS3:
|
||||
case MGN_24M:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa47f);
|
||||
break;
|
||||
case MGN_VHT1SS_MCS2:
|
||||
case MGN_MCS2:
|
||||
case MGN_18M:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa57f);
|
||||
break;
|
||||
case MGN_VHT1SS_MCS1:
|
||||
case MGN_MCS1:
|
||||
case MGN_9M:
|
||||
case MGN_12M:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa77f);
|
||||
break;
|
||||
case MGN_VHT1SS_MCS0:
|
||||
case MGN_MCS0:
|
||||
case MGN_6M:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa87f);
|
||||
break;
|
||||
default:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
} else
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
|
||||
|
||||
} else if (IS_HARDWARE_TYPE_8812AU(adapter)) {
|
||||
if (p_mgnt_info->reg_tx_duty_enable) {
|
||||
/* 2013.07.26 Wilson: debug for 8812AU thermal issue (reduce Tx duty cycle) */
|
||||
/* it;s the same issue as 8811AU */
|
||||
if (!p_mgnt_info->forced_data_rate) { /* auto rate */
|
||||
if (p_dm_odm->tx_rate != 0xFF)
|
||||
tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(p_dm_odm->tx_rate);
|
||||
} else /* force rate */
|
||||
tx_rate = (u8) p_mgnt_info->forced_data_rate;
|
||||
|
||||
value64 = (cur_rx_ok_cnt << 2);
|
||||
if (cur_tx_ok_cnt < value64) /* Downlink */
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
|
||||
else { /* Uplink */
|
||||
/*dbg_print("p_rf_calibrate_info->thermal_value = 0x%X\n", p_rf_calibrate_info->thermal_value);*/
|
||||
/*if(p_rf_calibrate_info->thermal_value < p_hal_data->eeprom_thermal_meter)*/
|
||||
if ((p_dm_odm->rf_calibrate_info.thermal_value < 0x2c) || (*p_dm_odm->p_band_type == BAND_ON_2_4G))
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
|
||||
else {
|
||||
switch (tx_rate) {
|
||||
case MGN_VHT2SS_MCS9:
|
||||
case MGN_VHT1SS_MCS9:
|
||||
case MGN_VHT1SS_MCS8:
|
||||
case MGN_MCS15:
|
||||
case MGN_MCS7:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0x1ea44f);
|
||||
case MGN_VHT2SS_MCS8:
|
||||
case MGN_VHT1SS_MCS7:
|
||||
case MGN_MCS14:
|
||||
case MGN_MCS6:
|
||||
case MGN_54M:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa44f);
|
||||
case MGN_VHT2SS_MCS7:
|
||||
case MGN_VHT2SS_MCS6:
|
||||
case MGN_VHT1SS_MCS6:
|
||||
case MGN_VHT1SS_MCS5:
|
||||
case MGN_MCS13:
|
||||
case MGN_MCS5:
|
||||
case MGN_48M:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa630);
|
||||
break;
|
||||
case MGN_VHT2SS_MCS5:
|
||||
case MGN_VHT2SS_MCS4:
|
||||
case MGN_VHT1SS_MCS4:
|
||||
case MGN_VHT1SS_MCS3:
|
||||
case MGN_MCS12:
|
||||
case MGN_MCS4:
|
||||
case MGN_MCS3:
|
||||
case MGN_36M:
|
||||
case MGN_24M:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa730);
|
||||
break;
|
||||
case MGN_VHT2SS_MCS3:
|
||||
case MGN_VHT2SS_MCS2:
|
||||
case MGN_VHT2SS_MCS1:
|
||||
case MGN_VHT1SS_MCS2:
|
||||
case MGN_VHT1SS_MCS1:
|
||||
case MGN_MCS11:
|
||||
case MGN_MCS10:
|
||||
case MGN_MCS9:
|
||||
case MGN_MCS2:
|
||||
case MGN_MCS1:
|
||||
case MGN_18M:
|
||||
case MGN_12M:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa830);
|
||||
break;
|
||||
case MGN_VHT2SS_MCS0:
|
||||
case MGN_VHT1SS_MCS0:
|
||||
case MGN_MCS0:
|
||||
case MGN_MCS8:
|
||||
case MGN_9M:
|
||||
case MGN_6M:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa87f);
|
||||
break;
|
||||
default:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
} else
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
|
||||
} else
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("EDCA Turbo on: EDCA_BE:0x%lx\n", EDCA_BE));
|
||||
|
||||
p_dm_odm->dm_edca_table.is_current_turbo_edca = true;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("EDCA_BE_DL : 0x%lx EDCA_BE_UL : 0x%lx EDCA_BE : 0x%lx\n", EDCA_BE_DL, EDCA_BE_UL, EDCA_BE));
|
||||
|
||||
} else {
|
||||
/* Turn Off EDCA turbo here. */
|
||||
/* Restore original EDCA according to the declaration of AP. */
|
||||
if (p_dm_odm->dm_edca_table.is_current_turbo_edca) {
|
||||
phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_AC_PARAM, GET_WMM_PARAM_ELE_SINGLE_AC_PARAM(p_sta_qos->wmm_param_ele, AC0_BE));
|
||||
|
||||
p_dm_odm->dm_edca_table.is_current_turbo_edca = false;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Restore EDCA BE: 0x%lx\n", p_dm_odm->WMMEDCA_BE));
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/* check if edca turbo is disabled */
|
||||
bool
|
||||
odm_is_edca_turbo_disable(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
PMGNT_INFO p_mgnt_info = &adapter->MgntInfo;
|
||||
u32 iot_peer = p_mgnt_info->iot_peer;
|
||||
|
||||
if (p_dm_odm->is_bt_disable_edca_turbo) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("EdcaTurboDisable for BT!!\n"));
|
||||
return true;
|
||||
}
|
||||
|
||||
if ((!(p_dm_odm->support_ability & ODM_MAC_EDCA_TURBO)) ||
|
||||
(p_dm_odm->wifi_test & RT_WIFI_LOGO) ||
|
||||
(iot_peer >= HT_IOT_PEER_MAX)) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("EdcaTurboDisable\n"));
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
/* 1. We do not turn on EDCA turbo mode for some AP that has IOT issue */
|
||||
/* 2. User may disable EDCA Turbo mode with OID settings. */
|
||||
if (p_mgnt_info->iot_action & HT_IOT_ACT_DISABLE_EDCA_TURBO) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("iot_action:EdcaTurboDisable\n"));
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
|
||||
|
||||
}
|
||||
|
||||
/* add iot case here: for MP/CE */
|
||||
void
|
||||
odm_edca_para_sel_by_iot(
|
||||
void *p_dm_void,
|
||||
u32 *EDCA_BE_UL,
|
||||
u32 *EDCA_BE_DL
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
u32 iot_peer = 0;
|
||||
u32 ic_type = p_dm_odm->support_ic_type;
|
||||
u8 wireless_mode = 0xFF; /* invalid value */
|
||||
u32 iot_peer_sub_type = 0;
|
||||
|
||||
PMGNT_INFO p_mgnt_info = &adapter->MgntInfo;
|
||||
u8 two_port_status = (u8)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE;
|
||||
|
||||
if (p_dm_odm->p_wireless_mode != NULL)
|
||||
wireless_mode = *(p_dm_odm->p_wireless_mode);
|
||||
|
||||
/* ========================================================= */
|
||||
/* list paramter for different platform */
|
||||
|
||||
iot_peer = p_mgnt_info->iot_peer;
|
||||
iot_peer_sub_type = p_mgnt_info->iot_peer_subtype;
|
||||
get_two_port_shared_resource(adapter, TWO_PORT_SHARED_OBJECT__STATUS, NULL, &two_port_status);
|
||||
|
||||
/* ****************************
|
||||
* / IOT case for MP
|
||||
* **************************** */
|
||||
if (p_dm_odm->support_interface == ODM_ITRF_PCIE) {
|
||||
(*EDCA_BE_UL) = 0x6ea42b;
|
||||
(*EDCA_BE_DL) = 0x6ea42b;
|
||||
}
|
||||
|
||||
if (two_port_status == TWO_PORT_STATUS__EXTENSION_ONLY) {
|
||||
(*EDCA_BE_UL) = 0x5ea42b;/* Parameter suggested by Scott */ /* edca_setting_UL[ExtAdapter->mgnt_info.iot_peer]; */
|
||||
(*EDCA_BE_DL) = 0x5ea42b;/* Parameter suggested by Scott */ /* edca_setting_DL[ExtAdapter->mgnt_info.iot_peer]; */
|
||||
}
|
||||
|
||||
#if (INTEL_PROXIMITY_SUPPORT == 1)
|
||||
if (p_mgnt_info->intel_class_mode_info.is_enable_ca == true)
|
||||
(*EDCA_BE_UL) = (*EDCA_BE_DL) = 0xa44f;
|
||||
else
|
||||
#endif
|
||||
{
|
||||
if ((p_mgnt_info->iot_action & (HT_IOT_ACT_FORCED_ENABLE_BE_TXOP | HT_IOT_ACT_AMSDU_ENABLE))) {
|
||||
/* To check whether we shall force turn on TXOP configuration. */
|
||||
if (!((*EDCA_BE_UL) & 0xffff0000))
|
||||
(*EDCA_BE_UL) |= 0x005e0000; /* Force TxOP limit to 0x005e for UL. */
|
||||
if (!((*EDCA_BE_DL) & 0xffff0000))
|
||||
(*EDCA_BE_DL) |= 0x005e0000; /* Force TxOP limit to 0x005e for DL. */
|
||||
}
|
||||
|
||||
/* 92D txop can't be set to 0x3e for cisco1250 */
|
||||
if ((iot_peer == HT_IOT_PEER_CISCO) && (wireless_mode == ODM_WM_N24G)) {
|
||||
(*EDCA_BE_DL) = edca_setting_DL[iot_peer];
|
||||
(*EDCA_BE_UL) = edca_setting_UL[iot_peer];
|
||||
}
|
||||
/* merge from 92s_92c_merge temp brunch v2445 20120215 */
|
||||
else if ((iot_peer == HT_IOT_PEER_CISCO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == (ODM_WM_B | ODM_WM_G)) || (wireless_mode == ODM_WM_A) || (wireless_mode == ODM_WM_B)))
|
||||
(*EDCA_BE_DL) = edca_setting_dl_g_mode[iot_peer];
|
||||
else if ((iot_peer == HT_IOT_PEER_AIRGO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == ODM_WM_A)))
|
||||
(*EDCA_BE_DL) = 0xa630;
|
||||
|
||||
else if (iot_peer == HT_IOT_PEER_MARVELL) {
|
||||
(*EDCA_BE_DL) = edca_setting_DL[iot_peer];
|
||||
(*EDCA_BE_UL) = edca_setting_UL[iot_peer];
|
||||
} else if (iot_peer == HT_IOT_PEER_ATHEROS && iot_peer_sub_type != HT_IOT_PEER_TPLINK_AC1750) {
|
||||
/* Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue. */
|
||||
if (wireless_mode == ODM_WM_G)
|
||||
(*EDCA_BE_DL) = edca_setting_dl_g_mode[iot_peer];
|
||||
else
|
||||
(*EDCA_BE_DL) = edca_setting_DL[iot_peer];
|
||||
|
||||
if (ic_type == ODM_RTL8821)
|
||||
(*EDCA_BE_DL) = 0x5ea630;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
if ((ic_type == ODM_RTL8812) || (ic_type == ODM_RTL8192E)) { /* add 8812AU/8812AE */
|
||||
(*EDCA_BE_UL) = 0x5ea42b;
|
||||
(*EDCA_BE_DL) = 0x5ea42b;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("8812A: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx\n", (*EDCA_BE_UL), (*EDCA_BE_DL)));
|
||||
}
|
||||
|
||||
if ((ic_type == ODM_RTL8814A) && (iot_peer == HT_IOT_PEER_REALTEK)) { /*8814AU and 8814AR*/
|
||||
(*EDCA_BE_UL) = 0x5ea42b;
|
||||
(*EDCA_BE_DL) = 0xa42b;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("8814A: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx\n", (*EDCA_BE_UL), (*EDCA_BE_DL)));
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Special: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx, iot_peer = %d\n", (*EDCA_BE_UL), (*EDCA_BE_DL), iot_peer));
|
||||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_edca_choose_traffic_idx(
|
||||
void *p_dm_void,
|
||||
u64 cur_tx_bytes,
|
||||
u64 cur_rx_bytes,
|
||||
bool is_bias_on_rx,
|
||||
bool *p_is_cur_rdl_state
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
|
||||
if (is_bias_on_rx) {
|
||||
|
||||
if (cur_tx_bytes > (cur_rx_bytes * 4)) {
|
||||
*p_is_cur_rdl_state = false;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Uplink Traffic\n "));
|
||||
|
||||
} else {
|
||||
*p_is_cur_rdl_state = true;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Balance Traffic\n"));
|
||||
|
||||
}
|
||||
} else {
|
||||
if (cur_rx_bytes > (cur_tx_bytes * 4)) {
|
||||
*p_is_cur_rdl_state = true;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Downlink Traffic\n"));
|
||||
|
||||
} else {
|
||||
*p_is_cur_rdl_state = false;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Balance Traffic\n"));
|
||||
}
|
||||
}
|
||||
|
||||
return ;
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif /*PHYDM_SUPPORT_EDCA*/
|
||||
102
hal/phydm/phydm_edcaturbocheck.h
Normal file
102
hal/phydm/phydm_edcaturbocheck.h
Normal file
|
|
@ -0,0 +1,102 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMEDCATURBOCHECK_H__
|
||||
#define __PHYDMEDCATURBOCHECK_H__
|
||||
|
||||
#if PHYDM_SUPPORT_EDCA
|
||||
/*#define EDCATURBO_VERSION "2.1"*/
|
||||
#define EDCATURBO_VERSION "2.3" /*2015.07.29 by YuChen*/
|
||||
|
||||
struct _EDCA_TURBO_ {
|
||||
bool is_current_turbo_edca;
|
||||
bool is_cur_rdl_state;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
u32 prv_traffic_idx; /* edca turbo */
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
|
||||
/* UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU MARVELL 92U_AP SELF_AP(DownLink/Tx) */
|
||||
{ 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322};
|
||||
|
||||
|
||||
static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
|
||||
/* UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP(UpLink/Rx) */
|
||||
{ 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b};
|
||||
|
||||
static u32 edca_setting_dl_g_mode[HT_IOT_PEER_MAX] =
|
||||
/* UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP */
|
||||
{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b};
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
void
|
||||
odm_edca_turbo_check(
|
||||
void *p_dm_void
|
||||
);
|
||||
void
|
||||
odm_edca_turbo_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void
|
||||
odm_edca_turbo_check_mp(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
/* check if edca turbo is disabled */
|
||||
bool
|
||||
odm_is_edca_turbo_disable(
|
||||
void *p_dm_void
|
||||
);
|
||||
/* choose edca paramter for special IOT case */
|
||||
void
|
||||
odm_edca_para_sel_by_iot(
|
||||
void *p_dm_void,
|
||||
u32 *EDCA_BE_UL,
|
||||
u32 *EDCA_BE_DL
|
||||
);
|
||||
/* check if it is UL or DL */
|
||||
void
|
||||
odm_edca_choose_traffic_idx(
|
||||
void *p_dm_void,
|
||||
u64 cur_tx_bytes,
|
||||
u64 cur_rx_bytes,
|
||||
bool is_bias_on_rx,
|
||||
bool *p_is_cur_rdl_state
|
||||
);
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
void
|
||||
odm_edca_turbo_check_ce(
|
||||
void *p_dm_void
|
||||
);
|
||||
#endif
|
||||
|
||||
#endif /*PHYDM_SUPPORT_EDCA*/
|
||||
|
||||
#endif
|
||||
189
hal/phydm/phydm_features.h
Normal file
189
hal/phydm/phydm_features.h
Normal file
|
|
@ -0,0 +1,189 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDM_FEATURES_H__
|
||||
#define __PHYDM_FEATURES
|
||||
|
||||
#define ODM_RECEIVER_BLOCKING_SUPPORT (ODM_RTL8188E | ODM_RTL8192E)
|
||||
#if ((RTL8814A_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
|
||||
#define PHYDM_LA_MODE_SUPPORT 1
|
||||
#else
|
||||
#define PHYDM_LA_MODE_SUPPORT 0
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
|
||||
/*phydm debyg report & tools*/
|
||||
#define CONFIG_PHYDM_DEBUG_FUNCTION 1
|
||||
|
||||
/*Antenna Diversity*/
|
||||
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
|
||||
#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
|
||||
|
||||
#if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1)
|
||||
#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY
|
||||
#endif
|
||||
|
||||
#if (RTL8821A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1)
|
||||
/*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
|
||||
#define CONFIG_FAT_PATCH
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
#define CONFIG_DYNAMIC_RX_PATH 0
|
||||
#else
|
||||
#define CONFIG_DYNAMIC_RX_PATH 0
|
||||
#endif
|
||||
|
||||
#if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1)
|
||||
#define CONFIG_RECEIVER_BLOCKING
|
||||
#endif
|
||||
#define PHYDM_SUPPORT_EDCA 0
|
||||
#define SUPPORTABLITY_PHYDMLIZE 1
|
||||
#define RA_MASK_PHYDMLIZE_WIN 1
|
||||
/*#define CONFIG_PATH_DIVERSITY*/
|
||||
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
|
||||
#define CONFIG_ANT_DETECTION
|
||||
/*#define CONFIG_RA_DBG_CMD*/
|
||||
#define CONFIG_RA_FW_DBG_CODE 1
|
||||
/*#define CONFIG_PHYDM_RX_SNIFFER_PARSING*/
|
||||
#define CONFIG_BB_POWER_SAVING
|
||||
#define CONFIG_BB_TXBF_API
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
|
||||
/*phydm debyg report & tools*/
|
||||
#if defined(CONFIG_DISABLE_PHYDM_DEBUG_FUNCTION)
|
||||
#define CONFIG_PHYDM_DEBUG_FUNCTION 0
|
||||
#else
|
||||
#define CONFIG_PHYDM_DEBUG_FUNCTION 1
|
||||
#endif
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
#define CONFIG_DYNAMIC_RX_PATH 0
|
||||
#else
|
||||
#define CONFIG_DYNAMIC_RX_PATH 0
|
||||
#endif
|
||||
|
||||
#define PHYDM_SUPPORT_EDCA 1
|
||||
#define SUPPORTABLITY_PHYDMLIZE 0
|
||||
#define RA_MASK_PHYDMLIZE_AP 1
|
||||
|
||||
/* #define CONFIG_RA_DBG_CMD*/
|
||||
#define CONFIG_RA_FW_DBG_CODE 0
|
||||
|
||||
/*#define CONFIG_PATH_DIVERSITY*/
|
||||
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
|
||||
#define CONFIG_RA_DYNAMIC_RATE_ID
|
||||
/*#define CONFIG_BB_POWER_SAVING*/
|
||||
#define CONFIG_BB_TXBF_API
|
||||
|
||||
/* [ Configure Antenna Diversity ] */
|
||||
#if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH)
|
||||
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
|
||||
#define ODM_EVM_ENHANCE_ANTDIV
|
||||
|
||||
/*----------*/
|
||||
|
||||
#if (!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
|
||||
#define CONFIG_NO_2G_DIVERSITY
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NO_5G_DIVERSITY_8881A
|
||||
#define CONFIG_NO_5G_DIVERSITY
|
||||
#elif defined(CONFIG_5G_CGCS_RX_DIVERSITY_8881A)
|
||||
#define CONFIG_5G_CGCS_RX_DIVERSITY
|
||||
#elif defined(CONFIG_5G_CG_TRX_DIVERSITY_8881A)
|
||||
#define CONFIG_5G_CG_TRX_DIVERSITY
|
||||
#elif defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)
|
||||
#define CONFIG_2G5G_CG_TRX_DIVERSITY
|
||||
#endif
|
||||
#if (!defined(CONFIG_NO_5G_DIVERSITY) && !defined(CONFIG_5G_CGCS_RX_DIVERSITY) && !defined(CONFIG_5G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY) && !defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
|
||||
#define CONFIG_NO_5G_DIVERSITY
|
||||
#endif
|
||||
/*----------*/
|
||||
#if (defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY))
|
||||
#define CONFIG_NOT_SUPPORT_ANTDIV
|
||||
#elif (!defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY))
|
||||
#define CONFIG_2G_SUPPORT_ANTDIV
|
||||
#elif (defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY))
|
||||
#define CONFIG_5G_SUPPORT_ANTDIV
|
||||
#elif ((!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY))
|
||||
#define CONFIG_2G5G_SUPPORT_ANTDIV
|
||||
#endif
|
||||
/*----------*/
|
||||
#endif
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
|
||||
/*phydm debyg report & tools*/
|
||||
#define CONFIG_PHYDM_DEBUG_FUNCTION 1
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
#define CONFIG_DYNAMIC_RX_PATH 0
|
||||
#else
|
||||
#define CONFIG_DYNAMIC_RX_PATH 0
|
||||
#endif
|
||||
|
||||
#define PHYDM_SUPPORT_EDCA 1
|
||||
#define SUPPORTABLITY_PHYDMLIZE 1
|
||||
#define RA_MASK_PHYDMLIZE_CE 1
|
||||
|
||||
/*Antenna Diversity*/
|
||||
#ifdef CONFIG_ANTENNA_DIVERSITY
|
||||
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
|
||||
|
||||
#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
|
||||
|
||||
#if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1)
|
||||
#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY
|
||||
#endif
|
||||
|
||||
#if (RTL8821A_SUPPORT == 1)
|
||||
/*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DFS_MASTER
|
||||
#define CONFIG_PHYDM_DFS_MASTER
|
||||
#endif
|
||||
|
||||
#if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1)
|
||||
#define CONFIG_RECEIVER_BLOCKING
|
||||
#endif
|
||||
/*#define CONFIG_RA_DBG_CMD*/
|
||||
#define CONFIG_RA_FW_DBG_CODE 0
|
||||
/*#define CONFIG_ANT_DETECTION*/
|
||||
/*#define CONFIG_PATH_DIVERSITY*/
|
||||
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
|
||||
#define CONFIG_BB_POWER_SAVING
|
||||
#define CONFIG_BB_TXBF_API
|
||||
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
#define BT_SUPPORT 1
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
3628
hal/phydm/phydm_hwconfig.c
Normal file
3628
hal/phydm/phydm_hwconfig.c
Normal file
File diff suppressed because it is too large
Load diff
574
hal/phydm/phydm_hwconfig.h
Normal file
574
hal/phydm/phydm_hwconfig.h
Normal file
|
|
@ -0,0 +1,574 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __HALHWOUTSRC_H__
|
||||
#define __HALHWOUTSRC_H__
|
||||
|
||||
|
||||
/*--------------------------Define -------------------------------------------*/
|
||||
#define CCK_RSSI_INIT_COUNT 5
|
||||
|
||||
#define RA_RSSI_STATE_INIT 0
|
||||
#define RA_RSSI_STATE_SEND 1
|
||||
#define RA_RSSI_STATE_HOLD 2
|
||||
|
||||
#define CFO_HW_RPT_2_MHZ(val) ((val<<1) + (val>>1))
|
||||
/* ((X* 3125) / 10)>>7 = (X*10)>>2 = X*2.5 = X<<1 + X>>1 */
|
||||
|
||||
#define AGC_DIFF_CONFIG_MP(ic, band) (odm_read_and_config_mp_##ic##_agc_tab_diff(p_dm_odm, array_mp_##ic##_agc_tab_diff_##band, \
|
||||
sizeof(array_mp_##ic##_agc_tab_diff_##band)/sizeof(u32)))
|
||||
#define AGC_DIFF_CONFIG_TC(ic, band) (odm_read_and_config_tc_##ic##_agc_tab_diff(p_dm_odm, array_tc_##ic##_agc_tab_diff_##band, \
|
||||
sizeof(array_tc_##ic##_agc_tab_diff_##band)/sizeof(u32)))
|
||||
|
||||
#define AGC_DIFF_CONFIG(ic, band) do {\
|
||||
if (p_dm_odm->is_mp_chip)\
|
||||
AGC_DIFF_CONFIG_MP(ic, band);\
|
||||
else\
|
||||
AGC_DIFF_CONFIG_TC(ic, band);\
|
||||
} while (0)
|
||||
|
||||
|
||||
/* ************************************************************
|
||||
* structure and define
|
||||
* ************************************************************ */
|
||||
|
||||
__PACK struct _phy_rx_agc_info {
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 gain: 7, trsw: 1;
|
||||
#else
|
||||
u8 trsw: 1, gain: 7;
|
||||
#endif
|
||||
};
|
||||
|
||||
__PACK struct _phy_status_rpt_8192cd {
|
||||
struct _phy_rx_agc_info path_agc[2];
|
||||
u8 ch_corr[2];
|
||||
u8 cck_sig_qual_ofdm_pwdb_all;
|
||||
u8 cck_agc_rpt_ofdm_cfosho_a;
|
||||
u8 cck_rpt_b_ofdm_cfosho_b;
|
||||
u8 rsvd_1;/*ch_corr_msb;*/
|
||||
u8 noise_power_db_msb;
|
||||
s8 path_cfotail[2];
|
||||
u8 pcts_mask[2];
|
||||
s8 stream_rxevm[2];
|
||||
u8 path_rxsnr[2];
|
||||
u8 noise_power_db_lsb;
|
||||
u8 rsvd_2[3];
|
||||
u8 stream_csi[2];
|
||||
u8 stream_target_csi[2];
|
||||
s8 sig_evm;
|
||||
u8 rsvd_3;
|
||||
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 antsel_rx_keep_2: 1; /*ex_intf_flg:1;*/
|
||||
u8 sgi_en: 1;
|
||||
u8 rxsc: 2;
|
||||
u8 idle_long: 1;
|
||||
u8 r_ant_train_en: 1;
|
||||
u8 ant_sel_b: 1;
|
||||
u8 ant_sel: 1;
|
||||
#else /*_BIG_ENDIAN_ */
|
||||
u8 ant_sel: 1;
|
||||
u8 ant_sel_b: 1;
|
||||
u8 r_ant_train_en: 1;
|
||||
u8 idle_long: 1;
|
||||
u8 rxsc: 2;
|
||||
u8 sgi_en: 1;
|
||||
u8 antsel_rx_keep_2: 1;/*ex_intf_flg:1;*/
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
struct _phy_status_rpt_8812 {
|
||||
/* DWORD 0*/
|
||||
u8 gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/
|
||||
u8 chl_num_LSB; /*channel number[7:0]*/
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 chl_num_MSB: 2; /*channel number[9:8]*/
|
||||
u8 sub_chnl: 4; /*sub-channel location[3:0]*/
|
||||
u8 r_RFMOD: 2; /*RF mode[1:0]*/
|
||||
#else /*_BIG_ENDIAN_ */
|
||||
u8 r_RFMOD: 2;
|
||||
u8 sub_chnl: 4;
|
||||
u8 chl_num_MSB: 2;
|
||||
#endif
|
||||
|
||||
/* DWORD 1*/
|
||||
u8 pwdb_all; /*CCK signal quality / OFDM pwdb all*/
|
||||
s8 cfosho[2]; /*DW1 byte 1 DW1 byte2 CCK AGC report and CCK_BB_Power / OFDM path-A and path-B short CFO*/
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
/*this should be checked again because the definition of 8812 and 8814 is different*/
|
||||
/* u8 r_cck_rx_enable_pathc:2; cck rx enable pathc[1:0]*/
|
||||
/* u8 cck_rx_path:4; cck rx path[3:0]*/
|
||||
u8 resvd_0: 6;
|
||||
u8 bt_RF_ch_MSB: 2; /*8812A:2'b0 8814A: bt rf channel keep[7:6]*/
|
||||
#else /*_BIG_ENDIAN_*/
|
||||
u8 bt_RF_ch_MSB: 2;
|
||||
u8 resvd_0: 6;
|
||||
#endif
|
||||
|
||||
/* DWORD 2*/
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 ant_div_sw_a: 1; /*8812A: ant_div_sw_a 8814A: 1'b0*/
|
||||
u8 ant_div_sw_b: 1; /*8812A: ant_div_sw_b 8814A: 1'b0*/
|
||||
u8 bt_RF_ch_LSB: 6; /*8812A: 6'b0 8814A: bt rf channel keep[5:0]*/
|
||||
#else /*_BIG_ENDIAN_ */
|
||||
u8 bt_RF_ch_LSB: 6;
|
||||
u8 ant_div_sw_b: 1;
|
||||
u8 ant_div_sw_a: 1;
|
||||
#endif
|
||||
s8 cfotail[2]; /*DW2 byte 1 DW2 byte 2 path-A and path-B CFO tail*/
|
||||
u8 PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/
|
||||
u8 PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/
|
||||
|
||||
/* DWORD 3*/
|
||||
s8 rxevm[2]; /*DW3 byte 1 DW3 byte 2 stream 1 and stream 2 RX EVM*/
|
||||
s8 rxsnr[2]; /*DW3 byte 3 DW4 byte 0 path-A and path-B RX SNR*/
|
||||
|
||||
/* DWORD 4*/
|
||||
u8 PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 PCTS_MSK_RPT_3: 6; /*PCTS mask report[29:24]*/
|
||||
u8 pcts_rpt_valid: 1; /*pcts_rpt_valid*/
|
||||
u8 resvd_1: 1; /*1'b0*/
|
||||
#else /*_BIG_ENDIAN_*/
|
||||
u8 resvd_1: 1;
|
||||
u8 pcts_rpt_valid: 1;
|
||||
u8 PCTS_MSK_RPT_3: 6;
|
||||
#endif
|
||||
s8 rxevm_cd[2]; /*DW 4 byte 3 DW5 byte 0 8812A: 16'b0 8814A: stream 3 and stream 4 RX EVM*/
|
||||
|
||||
/* DWORD 5*/
|
||||
u8 csi_current[2]; /*DW5 byte 1 DW5 byte 2 8812A: stream 1 and 2 CSI 8814A: path-C and path-D RX SNR*/
|
||||
u8 gain_trsw_cd[2]; /*DW5 byte 3 DW6 byte 0 path-C and path-D {TRSW, gain[6:0] }*/
|
||||
|
||||
/* DWORD 6*/
|
||||
s8 sigevm; /*signal field EVM*/
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 antidx_antc: 3; /*8812A: 3'b0 8814A: antidx_antc[2:0]*/
|
||||
u8 antidx_antd: 3; /*8812A: 3'b0 8814A: antidx_antd[2:0]*/
|
||||
u8 dpdt_ctrl_keep: 1; /*8812A: 1'b0 8814A: dpdt_ctrl_keep*/
|
||||
u8 GNT_BT_keep: 1; /*8812A: 1'b0 8814A: GNT_BT_keep*/
|
||||
#else /*_BIG_ENDIAN_*/
|
||||
u8 GNT_BT_keep: 1;
|
||||
u8 dpdt_ctrl_keep: 1;
|
||||
u8 antidx_antd: 3;
|
||||
u8 antidx_antc: 3;
|
||||
#endif
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 antidx_anta: 3; /*antidx_anta[2:0]*/
|
||||
u8 antidx_antb: 3; /*antidx_antb[2:0]*/
|
||||
u8 hw_antsw_occur: 2; /*1'b0*/
|
||||
#else /*_BIG_ENDIAN_*/
|
||||
u8 hw_antsw_occur: 2;
|
||||
u8 antidx_antb: 3;
|
||||
u8 antidx_anta: 3;
|
||||
#endif
|
||||
};
|
||||
|
||||
void
|
||||
phydm_reset_rssi_for_dm(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 station_id
|
||||
);
|
||||
|
||||
void
|
||||
odm_init_rssi_for_dm(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void
|
||||
phydm_normal_driver_rx_sniffer(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 *p_desc,
|
||||
PRT_RFD_STATUS p_rt_rfd_status,
|
||||
u8 *p_drv_info,
|
||||
u8 phy_status
|
||||
);
|
||||
#endif
|
||||
|
||||
void
|
||||
odm_phy_status_query(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
struct _odm_phy_status_info_ *p_phy_info,
|
||||
u8 *p_phy_status,
|
||||
struct _odm_per_pkt_info_ *p_pktinfo
|
||||
);
|
||||
|
||||
void
|
||||
odm_mac_status_query(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 *p_mac_status,
|
||||
u8 mac_id,
|
||||
bool is_packet_match_bssid,
|
||||
bool is_packet_to_self,
|
||||
bool is_packet_beacon
|
||||
);
|
||||
|
||||
enum hal_status
|
||||
odm_config_rf_with_tx_pwr_track_header_file(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
enum hal_status
|
||||
odm_config_rf_with_header_file(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
enum odm_rf_config_type config_type,
|
||||
enum odm_rf_radio_path_e e_rf_path
|
||||
);
|
||||
|
||||
enum hal_status
|
||||
odm_config_bb_with_header_file(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
enum odm_bb_config_type config_type
|
||||
);
|
||||
|
||||
enum hal_status
|
||||
odm_config_mac_with_header_file(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
enum hal_status
|
||||
odm_config_fw_with_header_file(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
enum odm_fw_config_type config_type,
|
||||
u8 *p_firmware,
|
||||
u32 *p_size
|
||||
);
|
||||
|
||||
u32
|
||||
odm_get_hw_img_version(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
s32
|
||||
odm_signal_scale_mapping(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
s32 curr_sig
|
||||
);
|
||||
|
||||
#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
|
||||
/*For 8822B only!! need to move to FW finally */
|
||||
/*==============================================*/
|
||||
void
|
||||
phydm_rx_phy_status_new_type(
|
||||
struct PHY_DM_STRUCT *p_phydm,
|
||||
u8 *p_phy_status,
|
||||
struct _odm_per_pkt_info_ *p_pktinfo,
|
||||
struct _odm_phy_status_info_ *p_phy_info
|
||||
);
|
||||
|
||||
bool
|
||||
phydm_query_is_mu_api(
|
||||
struct PHY_DM_STRUCT *p_phydm,
|
||||
u8 ppdu_idx,
|
||||
u8 *p_data_rate,
|
||||
u8 *p_gid
|
||||
);
|
||||
|
||||
struct _phy_status_rpt_jaguar2_type0 {
|
||||
/* DW0 */
|
||||
u8 page_num;
|
||||
u8 pwdb;
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 gain: 6;
|
||||
u8 rsvd_0: 1;
|
||||
u8 trsw: 1;
|
||||
#else
|
||||
u8 trsw: 1;
|
||||
u8 rsvd_0: 1;
|
||||
u8 gain: 6;
|
||||
#endif
|
||||
u8 rsvd_1;
|
||||
|
||||
/* DW1 */
|
||||
u8 rsvd_2;
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 rxsc: 4;
|
||||
u8 agc_table: 4;
|
||||
#else
|
||||
u8 agc_table: 4;
|
||||
u8 rxsc: 4;
|
||||
#endif
|
||||
u8 channel;
|
||||
u8 band;
|
||||
|
||||
/* DW2 */
|
||||
u16 length;
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 antidx_a: 3;
|
||||
u8 antidx_b: 3;
|
||||
u8 rsvd_3: 2;
|
||||
u8 antidx_c: 3;
|
||||
u8 antidx_d: 3;
|
||||
u8 rsvd_4:2;
|
||||
#else
|
||||
u8 rsvd_3: 2;
|
||||
u8 antidx_b: 3;
|
||||
u8 antidx_a: 3;
|
||||
u8 rsvd_4:2;
|
||||
u8 antidx_d: 3;
|
||||
u8 antidx_c: 3;
|
||||
#endif
|
||||
|
||||
/* DW3 */
|
||||
u8 signal_quality;
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 vga:5;
|
||||
u8 lna_l:3;
|
||||
u8 bb_power:6;
|
||||
u8 rsvd_9:1;
|
||||
u8 lna_h:1;
|
||||
#else
|
||||
u8 lna_l:3;
|
||||
u8 vga:5;
|
||||
u8 lna_h:1;
|
||||
u8 rsvd_9:1;
|
||||
u8 bb_power:6;
|
||||
#endif
|
||||
u8 rsvd_5;
|
||||
|
||||
/* DW4 */
|
||||
u32 rsvd_6;
|
||||
|
||||
/* DW5 */
|
||||
u32 rsvd_7;
|
||||
|
||||
/* DW6 */
|
||||
u32 rsvd_8;
|
||||
};
|
||||
|
||||
struct _phy_status_rpt_jaguar2_type1 {
|
||||
/* DW0 and DW1 */
|
||||
u8 page_num;
|
||||
u8 pwdb[4];
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 l_rxsc: 4;
|
||||
u8 ht_rxsc: 4;
|
||||
#else
|
||||
u8 ht_rxsc: 4;
|
||||
u8 l_rxsc: 4;
|
||||
#endif
|
||||
u8 channel;
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 band: 2;
|
||||
u8 rsvd_0: 1;
|
||||
u8 hw_antsw_occu: 1;
|
||||
u8 gnt_bt: 1;
|
||||
u8 ldpc: 1;
|
||||
u8 stbc: 1;
|
||||
u8 beamformed: 1;
|
||||
#else
|
||||
u8 beamformed: 1;
|
||||
u8 stbc: 1;
|
||||
u8 ldpc: 1;
|
||||
u8 gnt_bt: 1;
|
||||
u8 hw_antsw_occu: 1;
|
||||
u8 rsvd_0: 1;
|
||||
u8 band: 2;
|
||||
#endif
|
||||
|
||||
/* DW2 */
|
||||
u16 lsig_length;
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 antidx_a: 3;
|
||||
u8 antidx_b: 3;
|
||||
u8 rsvd_1: 2;
|
||||
u8 antidx_c: 3;
|
||||
u8 antidx_d: 3;
|
||||
u8 rsvd_2: 2;
|
||||
#else
|
||||
u8 rsvd_1: 2;
|
||||
u8 antidx_b: 3;
|
||||
u8 antidx_a: 3;
|
||||
u8 rsvd_2: 2;
|
||||
u8 antidx_d: 3;
|
||||
u8 antidx_c: 3;
|
||||
#endif
|
||||
|
||||
/* DW3 */
|
||||
u8 paid;
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 paid_msb: 1;
|
||||
u8 gid: 6;
|
||||
u8 rsvd_3: 1;
|
||||
#else
|
||||
u8 rsvd_3: 1;
|
||||
u8 gid: 6;
|
||||
u8 paid_msb: 1;
|
||||
#endif
|
||||
u8 intf_pos;
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 intf_pos_msb: 1;
|
||||
u8 rsvd_4: 2;
|
||||
u8 nb_intf_flag: 1;
|
||||
u8 rf_mode: 2;
|
||||
u8 rsvd_5: 2;
|
||||
#else
|
||||
u8 rsvd_5: 2;
|
||||
u8 rf_mode: 2;
|
||||
u8 nb_intf_flag: 1;
|
||||
u8 rsvd_4: 2;
|
||||
u8 intf_pos_msb: 1;
|
||||
#endif
|
||||
|
||||
/* DW4 */
|
||||
s8 rxevm[4]; /* s(8,1) */
|
||||
|
||||
/* DW5 */
|
||||
s8 cfo_tail[4]; /* s(8,7) */
|
||||
|
||||
/* DW6 */
|
||||
s8 rxsnr[4]; /* s(8,1) */
|
||||
};
|
||||
|
||||
struct _phy_status_rpt_jaguar2_type2 {
|
||||
/* DW0 ane DW1 */
|
||||
u8 page_num;
|
||||
u8 pwdb[4];
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 l_rxsc: 4;
|
||||
u8 ht_rxsc: 4;
|
||||
#else
|
||||
u8 ht_rxsc: 4;
|
||||
u8 l_rxsc: 4;
|
||||
#endif
|
||||
u8 channel;
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 band: 2;
|
||||
u8 rsvd_0: 1;
|
||||
u8 hw_antsw_occu: 1;
|
||||
u8 gnt_bt: 1;
|
||||
u8 ldpc: 1;
|
||||
u8 stbc: 1;
|
||||
u8 beamformed: 1;
|
||||
#else
|
||||
u8 beamformed: 1;
|
||||
u8 stbc: 1;
|
||||
u8 ldpc: 1;
|
||||
u8 gnt_bt: 1;
|
||||
u8 hw_antsw_occu: 1;
|
||||
u8 rsvd_0: 1;
|
||||
u8 band: 2;
|
||||
#endif
|
||||
|
||||
/* DW2 */
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 shift_l_map: 6;
|
||||
u8 rsvd_1: 2;
|
||||
#else
|
||||
u8 rsvd_1: 2;
|
||||
u8 shift_l_map: 6;
|
||||
#endif
|
||||
u8 cnt_pw2cca;
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 agc_table_a: 4;
|
||||
u8 agc_table_b: 4;
|
||||
u8 agc_table_c: 4;
|
||||
u8 agc_table_d: 4;
|
||||
#else
|
||||
u8 agc_table_b: 4;
|
||||
u8 agc_table_a: 4;
|
||||
u8 agc_table_d: 4;
|
||||
u8 agc_table_c: 4;
|
||||
#endif
|
||||
|
||||
/* DW3 ~ DW6*/
|
||||
u8 cnt_cca2agc_rdy;
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 gain_a: 6;
|
||||
u8 rsvd_2: 1;
|
||||
u8 trsw_a: 1;
|
||||
u8 gain_b: 6;
|
||||
u8 rsvd_3: 1;
|
||||
u8 trsw_b: 1;
|
||||
u8 gain_c: 6;
|
||||
u8 rsvd_4: 1;
|
||||
u8 trsw_c: 1;
|
||||
u8 gain_d: 6;
|
||||
u8 rsvd_5: 1;
|
||||
u8 trsw_d: 1;
|
||||
u8 aagc_step_a: 2;
|
||||
u8 aagc_step_b: 2;
|
||||
u8 aagc_step_c: 2;
|
||||
u8 aagc_step_d: 2;
|
||||
#else
|
||||
u8 trsw_a: 1;
|
||||
u8 rsvd_2: 1;
|
||||
u8 gain_a: 6;
|
||||
u8 trsw_b: 1;
|
||||
u8 rsvd_3: 1;
|
||||
u8 gain_b: 6;
|
||||
u8 trsw_c: 1;
|
||||
u8 rsvd_4: 1;
|
||||
u8 gain_c: 6;
|
||||
u8 trsw_d: 1;
|
||||
u8 rsvd_5: 1;
|
||||
u8 gain_d: 6;
|
||||
u8 aagc_step_d: 2;
|
||||
u8 aagc_step_c: 2;
|
||||
u8 aagc_step_b: 2;
|
||||
u8 aagc_step_a: 2;
|
||||
#endif
|
||||
u8 ht_aagc_gain[4];
|
||||
u8 dagc_gain[4];
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 counter: 6;
|
||||
u8 rsvd_6: 2;
|
||||
u8 syn_count: 5;
|
||||
u8 rsvd_7:3;
|
||||
#else
|
||||
u8 rsvd_6: 2;
|
||||
u8 counter: 6;
|
||||
u8 rsvd_7:3;
|
||||
u8 syn_count: 5;
|
||||
#endif
|
||||
};
|
||||
/*==============================================*/
|
||||
#endif /*#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)*/
|
||||
|
||||
u32
|
||||
query_phydm_trx_capability(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
u32
|
||||
query_phydm_stbc_capability(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
u32
|
||||
query_phydm_ldpc_capability(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
u32
|
||||
query_phydm_txbf_parameters(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
u32
|
||||
query_phydm_txbf_capability(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
#endif /*#ifndef __HALHWOUTSRC_H__*/
|
||||
1004
hal/phydm/phydm_interface.c
Normal file
1004
hal/phydm/phydm_interface.c
Normal file
File diff suppressed because it is too large
Load diff
416
hal/phydm/phydm_interface.h
Normal file
416
hal/phydm/phydm_interface.h
Normal file
|
|
@ -0,0 +1,416 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __ODM_INTERFACE_H__
|
||||
#define __ODM_INTERFACE_H__
|
||||
|
||||
#define INTERFACE_VERSION "1.1" /*2015.07.29 YuChen*/
|
||||
|
||||
/*
|
||||
* =========== Constant/Structure/Enum/... Define
|
||||
* */
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* =========== Macro Define
|
||||
* */
|
||||
|
||||
#define _reg_all(_name) ODM_##_name
|
||||
#define _reg_ic(_name, _ic) ODM_##_name##_ic
|
||||
#define _bit_all(_name) BIT_##_name
|
||||
#define _bit_ic(_name, _ic) BIT_##_name##_ic
|
||||
|
||||
/* _cat: implemented by Token-Pasting Operator. */
|
||||
#if 0
|
||||
#define _cat(_name, _ic_type, _func) \
|
||||
(\
|
||||
_func##_all(_name) \
|
||||
)
|
||||
#endif
|
||||
|
||||
/*===================================
|
||||
|
||||
#define ODM_REG_DIG_11N 0xC50
|
||||
#define ODM_REG_DIG_11AC 0xDDD
|
||||
|
||||
ODM_REG(DIG,_pdm_odm)
|
||||
=====================================*/
|
||||
|
||||
#define _reg_11N(_name) ODM_REG_##_name##_11N
|
||||
#define _reg_11AC(_name) ODM_REG_##_name##_11AC
|
||||
#define _bit_11N(_name) ODM_BIT_##_name##_11N
|
||||
#define _bit_11AC(_name) ODM_BIT_##_name##_11AC
|
||||
|
||||
#ifdef __ECOS
|
||||
#define _rtk_cat(_name, _ic_type, _func) \
|
||||
(\
|
||||
((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \
|
||||
_func##_11AC(_name) \
|
||||
)
|
||||
#else
|
||||
|
||||
#define _cat(_name, _ic_type, _func) \
|
||||
(\
|
||||
((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \
|
||||
_func##_11AC(_name) \
|
||||
)
|
||||
#endif
|
||||
/*
|
||||
* only sample code
|
||||
*#define _cat(_name, _ic_type, _func) \
|
||||
* ( \
|
||||
* ((_ic_type) & ODM_RTL8188E) ? _func##_ic(_name, _8188E) : \
|
||||
* _func##_ic(_name, _8195) \
|
||||
* )
|
||||
*/
|
||||
|
||||
/* _name: name of register or bit.
|
||||
* Example: "ODM_REG(R_A_AGC_CORE1, p_dm_odm)"
|
||||
* gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on support_ic_type. */
|
||||
#ifdef __ECOS
|
||||
#define ODM_REG(_name, _pdm_odm) _rtk_cat(_name, _pdm_odm->support_ic_type, _reg)
|
||||
#define ODM_BIT(_name, _pdm_odm) _rtk_cat(_name, _pdm_odm->support_ic_type, _bit)
|
||||
#else
|
||||
#define ODM_REG(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _reg)
|
||||
#define ODM_BIT(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _bit)
|
||||
#endif
|
||||
enum phydm_h2c_cmd {
|
||||
PHYDM_H2C_TXBF = 0x41,
|
||||
ODM_H2C_RSSI_REPORT = 0x42,
|
||||
ODM_H2C_IQ_CALIBRATION = 0x45,
|
||||
ODM_H2C_RA_PARA_ADJUST = 0x47,
|
||||
PHYDM_H2C_DYNAMIC_TX_PATH = 0x48,
|
||||
PHYDM_H2C_FW_TRACE_EN = 0x49,
|
||||
ODM_H2C_WIFI_CALIBRATION = 0x6d,
|
||||
PHYDM_H2C_MU = 0x4a,
|
||||
ODM_MAX_H2CCMD
|
||||
};
|
||||
|
||||
enum phydm_c2h_evt {
|
||||
PHYDM_C2H_DBG = 0,
|
||||
PHYDM_C2H_LB = 1,
|
||||
PHYDM_C2H_XBF = 2,
|
||||
PHYDM_C2H_TX_REPORT = 3,
|
||||
PHYDM_C2H_INFO = 9,
|
||||
PHYDM_C2H_BT_MP = 11,
|
||||
PHYDM_C2H_RA_RPT = 12,
|
||||
PHYDM_C2H_RA_PARA_RPT = 14,
|
||||
PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15,
|
||||
PHYDM_C2H_IQK_FINISH = 17, /*0x11*/
|
||||
PHYDM_C2H_DBG_CODE = 0xFE,
|
||||
PHYDM_C2H_EXTEND = 0xFF,
|
||||
};
|
||||
|
||||
enum phydm_extend_c2h_evt {
|
||||
PHYDM_EXTEND_C2H_DBG_PRINT = 0
|
||||
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* =========== Extern Variable ??? It should be forbidden.
|
||||
* */
|
||||
|
||||
|
||||
/*
|
||||
* =========== EXtern Function Prototype
|
||||
* */
|
||||
|
||||
|
||||
u8
|
||||
odm_read_1byte(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 reg_addr
|
||||
);
|
||||
|
||||
u16
|
||||
odm_read_2byte(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 reg_addr
|
||||
);
|
||||
|
||||
u32
|
||||
odm_read_4byte(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 reg_addr
|
||||
);
|
||||
|
||||
void
|
||||
odm_write_1byte(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 reg_addr,
|
||||
u8 data
|
||||
);
|
||||
|
||||
void
|
||||
odm_write_2byte(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 reg_addr,
|
||||
u16 data
|
||||
);
|
||||
|
||||
void
|
||||
odm_write_4byte(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 reg_addr,
|
||||
u32 data
|
||||
);
|
||||
|
||||
void
|
||||
odm_set_mac_reg(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 reg_addr,
|
||||
u32 bit_mask,
|
||||
u32 data
|
||||
);
|
||||
|
||||
u32
|
||||
odm_get_mac_reg(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 reg_addr,
|
||||
u32 bit_mask
|
||||
);
|
||||
|
||||
void
|
||||
odm_set_bb_reg(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 reg_addr,
|
||||
u32 bit_mask,
|
||||
u32 data
|
||||
);
|
||||
|
||||
u32
|
||||
odm_get_bb_reg(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 reg_addr,
|
||||
u32 bit_mask
|
||||
);
|
||||
|
||||
void
|
||||
odm_set_rf_reg(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
enum odm_rf_radio_path_e e_rf_path,
|
||||
u32 reg_addr,
|
||||
u32 bit_mask,
|
||||
u32 data
|
||||
);
|
||||
|
||||
u32
|
||||
odm_get_rf_reg(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
enum odm_rf_radio_path_e e_rf_path,
|
||||
u32 reg_addr,
|
||||
u32 bit_mask
|
||||
);
|
||||
|
||||
|
||||
/*
|
||||
* Memory Relative Function.
|
||||
* */
|
||||
void
|
||||
odm_allocate_memory(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
void **p_ptr,
|
||||
u32 length
|
||||
);
|
||||
void
|
||||
odm_free_memory(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
void *p_ptr,
|
||||
u32 length
|
||||
);
|
||||
|
||||
void
|
||||
odm_move_memory(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
void *p_dest,
|
||||
void *p_src,
|
||||
u32 length
|
||||
);
|
||||
|
||||
s32 odm_compare_memory(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
void *p_buf1,
|
||||
void *p_buf2,
|
||||
u32 length
|
||||
);
|
||||
|
||||
void odm_memory_set
|
||||
(struct PHY_DM_STRUCT *p_dm_odm,
|
||||
void *pbuf,
|
||||
s8 value,
|
||||
u32 length);
|
||||
|
||||
/*
|
||||
* ODM MISC-spin lock relative API.
|
||||
* */
|
||||
void
|
||||
odm_acquire_spin_lock(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
enum rt_spinlock_type type
|
||||
);
|
||||
|
||||
void
|
||||
odm_release_spin_lock(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
enum rt_spinlock_type type
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
/*
|
||||
* ODM MISC-workitem relative API.
|
||||
* */
|
||||
void
|
||||
odm_initialize_work_item(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
PRT_WORK_ITEM p_rt_work_item,
|
||||
RT_WORKITEM_CALL_BACK rt_work_item_callback,
|
||||
void *p_context,
|
||||
const char *sz_id
|
||||
);
|
||||
|
||||
void
|
||||
odm_start_work_item(
|
||||
PRT_WORK_ITEM p_rt_work_item
|
||||
);
|
||||
|
||||
void
|
||||
odm_stop_work_item(
|
||||
PRT_WORK_ITEM p_rt_work_item
|
||||
);
|
||||
|
||||
void
|
||||
odm_free_work_item(
|
||||
PRT_WORK_ITEM p_rt_work_item
|
||||
);
|
||||
|
||||
void
|
||||
odm_schedule_work_item(
|
||||
PRT_WORK_ITEM p_rt_work_item
|
||||
);
|
||||
|
||||
bool
|
||||
odm_is_work_item_scheduled(
|
||||
PRT_WORK_ITEM p_rt_work_item
|
||||
);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* ODM Timer relative API.
|
||||
* */
|
||||
void
|
||||
odm_stall_execution(
|
||||
u32 us_delay
|
||||
);
|
||||
|
||||
void
|
||||
ODM_delay_ms(u32 ms);
|
||||
|
||||
|
||||
|
||||
void
|
||||
ODM_delay_us(u32 us);
|
||||
|
||||
void
|
||||
ODM_sleep_ms(u32 ms);
|
||||
|
||||
void
|
||||
ODM_sleep_us(u32 us);
|
||||
|
||||
void
|
||||
odm_set_timer(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
struct timer_list *p_timer,
|
||||
u32 ms_delay
|
||||
);
|
||||
|
||||
void
|
||||
odm_initialize_timer(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
struct timer_list *p_timer,
|
||||
void *call_back_func,
|
||||
void *p_context,
|
||||
const char *sz_id
|
||||
);
|
||||
|
||||
void
|
||||
odm_cancel_timer(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
struct timer_list *p_timer
|
||||
);
|
||||
|
||||
void
|
||||
odm_release_timer(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
struct timer_list *p_timer
|
||||
);
|
||||
|
||||
/*
|
||||
* ODM FW relative API.
|
||||
* */
|
||||
void
|
||||
odm_fill_h2c_cmd(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 element_id,
|
||||
u32 cmd_len,
|
||||
u8 *p_cmd_buffer
|
||||
);
|
||||
|
||||
u8
|
||||
phydm_c2H_content_parsing(
|
||||
void *p_dm_void,
|
||||
u8 c2h_cmd_id,
|
||||
u8 c2h_cmd_len,
|
||||
u8 *tmp_buf
|
||||
);
|
||||
|
||||
u64
|
||||
odm_get_current_time(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
u64
|
||||
odm_get_progressing_time(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u64 start_time
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
|
||||
void
|
||||
phydm_set_hw_reg_handler_interface (
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 reg_Name,
|
||||
u8 *val
|
||||
);
|
||||
|
||||
void
|
||||
phydm_get_hal_def_var_handler_interface (
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
enum _HAL_DEF_VARIABLE e_variable,
|
||||
void *p_value
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __ODM_INTERFACE_H__ */
|
||||
|
||||
65
hal/phydm/phydm_iqk.h
Normal file
65
hal/phydm/phydm_iqk.h
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMIQK_H__
|
||||
#define __PHYDMIQK_H__
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
#define LOK_delay 1
|
||||
#define WBIQK_delay 10
|
||||
#define TX_IQK 0
|
||||
#define RX_IQK 1
|
||||
#define TXIQK 0
|
||||
#define RXIQK1 1
|
||||
#define RXIQK2 2
|
||||
#define kcount_limit_80m 2
|
||||
#define kcount_limit_others 4
|
||||
#define rxiqk_gs_limit 4
|
||||
|
||||
#define NUM 4
|
||||
/*---------------------------End Define Parameters-------------------------------*/
|
||||
|
||||
struct _IQK_INFORMATION {
|
||||
boolean LOK_fail[NUM];
|
||||
boolean IQK_fail[2][NUM];
|
||||
u32 iqc_matrix[2][NUM];
|
||||
u8 iqk_times;
|
||||
u32 rf_reg18;
|
||||
u32 lna_idx;
|
||||
u8 rxiqk_step;
|
||||
u8 tmp1bcc;
|
||||
u8 kcount;
|
||||
|
||||
u32 iqk_channel[2];
|
||||
boolean IQK_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */
|
||||
u32 IQK_CFIR_real[2][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_real*/
|
||||
u32 IQK_CFIR_imag[2][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/
|
||||
u8 retry_count[2][4][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */
|
||||
u8 gs_retry_count[2][4][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */
|
||||
u8 RXIQK_fail_code[2][4]; /* channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail */
|
||||
u32 LOK_IDAC[2][4]; /*channel / path*/
|
||||
u16 RXIQK_AGC[2][4]; /*channel / path*/
|
||||
u32 bypass_iqk[2][4]; /*channel / 0xc94/0xe94*/
|
||||
u32 tmp_GNTWL;
|
||||
boolean is_BTG;
|
||||
boolean isbnd;
|
||||
};
|
||||
|
||||
#endif
|
||||
190
hal/phydm/phydm_kfree.c
Normal file
190
hal/phydm/phydm_kfree.c
Normal file
|
|
@ -0,0 +1,190 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*============================================================*/
|
||||
/*include files*/
|
||||
/*============================================================*/
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
|
||||
/*<YuChen, 150720> Add for KFree Feature Requested by RF David.*/
|
||||
/*This is a phydm API*/
|
||||
|
||||
void
|
||||
phydm_set_kfree_to_rf_8814a(
|
||||
void *p_dm_void,
|
||||
u8 e_rf_path,
|
||||
u8 data
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
|
||||
bool is_odd;
|
||||
|
||||
if ((data % 2) != 0) { /*odd->positive*/
|
||||
data = data - 1;
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19), 1);
|
||||
is_odd = true;
|
||||
} else { /*even->negative*/
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19), 0);
|
||||
is_odd = false;
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): RF_0x55[19]= %d\n", is_odd));
|
||||
switch (data) {
|
||||
case 0:
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 0);
|
||||
p_rf_calibrate_info->kfree_offset[e_rf_path] = 0;
|
||||
break;
|
||||
case 2:
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1);
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 0);
|
||||
p_rf_calibrate_info->kfree_offset[e_rf_path] = 0;
|
||||
break;
|
||||
case 4:
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 1);
|
||||
p_rf_calibrate_info->kfree_offset[e_rf_path] = 1;
|
||||
break;
|
||||
case 6:
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1);
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 1);
|
||||
p_rf_calibrate_info->kfree_offset[e_rf_path] = 1;
|
||||
break;
|
||||
case 8:
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 2);
|
||||
p_rf_calibrate_info->kfree_offset[e_rf_path] = 2;
|
||||
break;
|
||||
case 10:
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1);
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 2);
|
||||
p_rf_calibrate_info->kfree_offset[e_rf_path] = 2;
|
||||
break;
|
||||
case 12:
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 3);
|
||||
p_rf_calibrate_info->kfree_offset[e_rf_path] = 3;
|
||||
break;
|
||||
case 14:
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1);
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 3);
|
||||
p_rf_calibrate_info->kfree_offset[e_rf_path] = 3;
|
||||
break;
|
||||
case 16:
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 4);
|
||||
p_rf_calibrate_info->kfree_offset[e_rf_path] = 4;
|
||||
break;
|
||||
case 18:
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1);
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 4);
|
||||
p_rf_calibrate_info->kfree_offset[e_rf_path] = 4;
|
||||
break;
|
||||
case 20:
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
|
||||
odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 5);
|
||||
p_rf_calibrate_info->kfree_offset[e_rf_path] = 5;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (is_odd == false) {
|
||||
/*that means Kfree offset is negative, we need to record it.*/
|
||||
p_rf_calibrate_info->kfree_offset[e_rf_path] = (-1) * p_rf_calibrate_info->kfree_offset[e_rf_path];
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): kfree_offset = %d\n", p_rf_calibrate_info->kfree_offset[e_rf_path]));
|
||||
} else
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): kfree_offset = %d\n", p_rf_calibrate_info->kfree_offset[e_rf_path]));
|
||||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
phydm_set_kfree_to_rf(
|
||||
void *p_dm_void,
|
||||
u8 e_rf_path,
|
||||
u8 data
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
phydm_set_kfree_to_rf_8814a(p_dm_odm, e_rf_path, data);
|
||||
}
|
||||
|
||||
void
|
||||
phydm_config_kfree(
|
||||
void *p_dm_void,
|
||||
u8 channel_to_sw,
|
||||
u8 *kfree_table
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
|
||||
u8 rfpath = 0, max_rf_path = 0;
|
||||
u8 channel_idx = 0;
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
max_rf_path = 4; /*0~3*/
|
||||
else if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E | ODM_RTL8822B))
|
||||
max_rf_path = 2; /*0~1*/
|
||||
else
|
||||
max_rf_path = 1;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("===>phy_ConfigKFree8814A()\n"));
|
||||
|
||||
if (p_rf_calibrate_info->reg_rf_kfree_enable == 2) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): reg_rf_kfree_enable == 2, Disable\n"));
|
||||
return;
|
||||
} else if (p_rf_calibrate_info->reg_rf_kfree_enable == 1 || p_rf_calibrate_info->reg_rf_kfree_enable == 0) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): reg_rf_kfree_enable == true\n"));
|
||||
/*Make sure the targetval is defined*/
|
||||
if (((p_rf_calibrate_info->reg_rf_kfree_enable == 1) && (kfree_table[0] != 0xFF)) || (p_rf_calibrate_info->rf_kfree_enable == true)) {
|
||||
/*if kfree_table[0] == 0xff, means no Kfree*/
|
||||
if (*p_dm_odm->p_band_type == ODM_BAND_2_4G) {
|
||||
if (channel_to_sw <= 14 && channel_to_sw >= 1)
|
||||
channel_idx = PHYDM_2G;
|
||||
} else if (*p_dm_odm->p_band_type == ODM_BAND_5G) {
|
||||
if (channel_to_sw >= 36 && channel_to_sw <= 48)
|
||||
channel_idx = PHYDM_5GLB1;
|
||||
if (channel_to_sw >= 52 && channel_to_sw <= 64)
|
||||
channel_idx = PHYDM_5GLB2;
|
||||
if (channel_to_sw >= 100 && channel_to_sw <= 120)
|
||||
channel_idx = PHYDM_5GMB1;
|
||||
if (channel_to_sw >= 124 && channel_to_sw <= 144)
|
||||
channel_idx = PHYDM_5GMB2;
|
||||
if (channel_to_sw >= 149 && channel_to_sw <= 177)
|
||||
channel_idx = PHYDM_5GHB;
|
||||
}
|
||||
|
||||
for (rfpath = ODM_RF_PATH_A; rfpath < max_rf_path; rfpath++) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phydm_kfree(): PATH_%d: %#x\n", rfpath, kfree_table[channel_idx * max_rf_path + rfpath]));
|
||||
phydm_set_kfree_to_rf(p_dm_odm, rfpath, kfree_table[channel_idx * max_rf_path + rfpath]);
|
||||
}
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): targetval not defined, Don't execute KFree Process.\n"));
|
||||
return;
|
||||
}
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("<===phy_ConfigKFree8814A()\n"));
|
||||
}
|
||||
45
hal/phydm/phydm_kfree.h
Normal file
45
hal/phydm/phydm_kfree.h
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMKFREE_H__
|
||||
#define __PHYDKFREE_H__
|
||||
|
||||
#define KFREE_VERSION "1.0"
|
||||
|
||||
enum phydm_kfree_channeltosw {
|
||||
PHYDM_2G = 0,
|
||||
PHYDM_5GLB1 = 1,
|
||||
PHYDM_5GLB2 = 2,
|
||||
PHYDM_5GMB1 = 3,
|
||||
PHYDM_5GMB2 = 4,
|
||||
PHYDM_5GHB = 5,
|
||||
};
|
||||
|
||||
|
||||
void
|
||||
phydm_config_kfree(
|
||||
void *p_dm_void,
|
||||
u8 channel_to_sw,
|
||||
u8 *kfree_table
|
||||
);
|
||||
|
||||
|
||||
#endif
|
||||
292
hal/phydm/phydm_noisemonitor.c
Normal file
292
hal/phydm/phydm_noisemonitor.c
Normal file
|
|
@ -0,0 +1,292 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* ************************************************************
|
||||
* include files
|
||||
* ************************************************************ */
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
#include "phydm_noisemonitor.h"
|
||||
|
||||
/* *************************************************
|
||||
* This function is for inband noise test utility only
|
||||
* To obtain the inband noise level(dbm), do the following.
|
||||
* 1. disable DIG and Power Saving
|
||||
* 2. Set initial gain = 0x1a
|
||||
* 3. Stop updating idle time pwer report (for driver read)
|
||||
* - 0x80c[25]
|
||||
*
|
||||
* ************************************************* */
|
||||
|
||||
#define VALID_MIN -35
|
||||
#define VALID_MAX 10
|
||||
#define VALID_CNT 5
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
|
||||
|
||||
s16 odm_inband_noise_monitor_n_series(struct PHY_DM_STRUCT *p_dm_odm, u8 is_pause_dig, u8 igi_value, u32 max_time)
|
||||
{
|
||||
u32 tmp4b;
|
||||
u8 max_rf_path = 0, rf_path;
|
||||
u8 reg_c50, reg_c58, valid_done = 0;
|
||||
struct noise_level noise_data;
|
||||
u64 start = 0, func_start = 0, func_end = 0;
|
||||
|
||||
func_start = odm_get_current_time(p_dm_odm);
|
||||
p_dm_odm->noise_level.noise_all = 0;
|
||||
|
||||
if ((p_dm_odm->rf_type == ODM_1T2R) || (p_dm_odm->rf_type == ODM_2T2R))
|
||||
max_rf_path = 2;
|
||||
else
|
||||
max_rf_path = 1;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() ==>\n"));
|
||||
|
||||
odm_memory_set(p_dm_odm, &noise_data, 0, sizeof(struct noise_level));
|
||||
|
||||
/* */
|
||||
/* step 1. Disable DIG && Set initial gain. */
|
||||
/* */
|
||||
|
||||
if (is_pause_dig)
|
||||
odm_pause_dig(p_dm_odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value);
|
||||
/* */
|
||||
/* step 2. Disable all power save for read registers */
|
||||
/* */
|
||||
/* dcmd_DebugControlPowerSave(p_adapter, PSDisable); */
|
||||
|
||||
/* */
|
||||
/* step 3. Get noise power level */
|
||||
/* */
|
||||
start = odm_get_current_time(p_dm_odm);
|
||||
while (1) {
|
||||
|
||||
/* Stop updating idle time pwer report (for driver read) */
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 1);
|
||||
|
||||
/* Read Noise Floor Report */
|
||||
tmp4b = odm_get_bb_reg(p_dm_odm, 0x8f8, MASKDWORD);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Noise Floor Report (0x8f8) = 0x%08x\n", tmp4b));
|
||||
|
||||
/* odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0, TestInitialGain); */
|
||||
/* if(max_rf_path == 2) */
|
||||
/* odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XB_AGC_CORE1, MASKBYTE0, TestInitialGain); */
|
||||
|
||||
/* update idle time pwer report per 5us */
|
||||
odm_set_bb_reg(p_dm_odm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 0);
|
||||
|
||||
noise_data.value[ODM_RF_PATH_A] = (u8)(tmp4b & 0xff);
|
||||
noise_data.value[ODM_RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8);
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("value_a = 0x%x(%d), value_b = 0x%x(%d)\n",
|
||||
noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_B], noise_data.value[ODM_RF_PATH_B]));
|
||||
|
||||
for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) {
|
||||
noise_data.sval[rf_path] = (s8)noise_data.value[rf_path];
|
||||
noise_data.sval[rf_path] /= 2;
|
||||
}
|
||||
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("sval_a = %d, sval_b = %d\n",
|
||||
noise_data.sval[ODM_RF_PATH_A], noise_data.sval[ODM_RF_PATH_B]));
|
||||
/* ODM_delay_ms(10); */
|
||||
/* ODM_sleep_ms(10); */
|
||||
|
||||
for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) {
|
||||
if ((noise_data.valid_cnt[rf_path] < VALID_CNT) && (noise_data.sval[rf_path] < VALID_MAX && noise_data.sval[rf_path] >= VALID_MIN)) {
|
||||
noise_data.valid_cnt[rf_path]++;
|
||||
noise_data.sum[rf_path] += noise_data.sval[rf_path];
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("rf_path:%d Valid sval = %d\n", rf_path, noise_data.sval[rf_path]));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Sum of sval = %d,\n", noise_data.sum[rf_path]));
|
||||
if (noise_data.valid_cnt[rf_path] == VALID_CNT) {
|
||||
valid_done++;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, rf_path:%d,sum = %d\n", rf_path, noise_data.sum[rf_path]));
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* printk("####### valid_done:%d #############\n",valid_done); */
|
||||
if ((valid_done == max_rf_path) || (odm_get_progressing_time(p_dm_odm, start) > max_time)) {
|
||||
for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) {
|
||||
/* printk("%s PATH_%d - sum = %d, VALID_CNT = %d\n",__FUNCTION__,rf_path,noise_data.sum[rf_path], noise_data.valid_cnt[rf_path]); */
|
||||
if (noise_data.valid_cnt[rf_path])
|
||||
noise_data.sum[rf_path] /= noise_data.valid_cnt[rf_path];
|
||||
else
|
||||
noise_data.sum[rf_path] = 0;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
reg_c50 = (u8)odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0);
|
||||
reg_c50 &= ~BIT(7);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("0x%x = 0x%02x(%d)\n", REG_OFDM_0_XA_AGC_CORE1, reg_c50, reg_c50));
|
||||
p_dm_odm->noise_level.noise[ODM_RF_PATH_A] = (u8)(-110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A]);
|
||||
p_dm_odm->noise_level.noise_all += p_dm_odm->noise_level.noise[ODM_RF_PATH_A];
|
||||
|
||||
if (max_rf_path == 2) {
|
||||
reg_c58 = (u8)odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XB_AGC_CORE1, MASKBYTE0);
|
||||
reg_c58 &= ~BIT(7);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("0x%x = 0x%02x(%d)\n", REG_OFDM_0_XB_AGC_CORE1, reg_c58, reg_c58));
|
||||
p_dm_odm->noise_level.noise[ODM_RF_PATH_B] = (u8)(-110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B]);
|
||||
p_dm_odm->noise_level.noise_all += p_dm_odm->noise_level.noise[ODM_RF_PATH_B];
|
||||
}
|
||||
p_dm_odm->noise_level.noise_all /= max_rf_path;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("noise_a = %d, noise_b = %d\n",
|
||||
p_dm_odm->noise_level.noise[ODM_RF_PATH_A],
|
||||
p_dm_odm->noise_level.noise[ODM_RF_PATH_B]));
|
||||
|
||||
/* */
|
||||
/* step 4. Recover the Dig */
|
||||
/* */
|
||||
if (is_pause_dig)
|
||||
odm_pause_dig(p_dm_odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value);
|
||||
func_end = odm_get_progressing_time(p_dm_odm, func_start) ;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() <==\n"));
|
||||
return p_dm_odm->noise_level.noise_all;
|
||||
|
||||
}
|
||||
|
||||
s16
|
||||
odm_inband_noise_monitor_ac_series(struct PHY_DM_STRUCT *p_dm_odm, u8 is_pause_dig, u8 igi_value, u32 max_time
|
||||
)
|
||||
{
|
||||
s32 rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/
|
||||
s32 value32, pwdb_A = 0, sval, noise, sum;
|
||||
bool pd_flag;
|
||||
u8 i, valid_cnt;
|
||||
u64 start = 0, func_start = 0, func_end = 0;
|
||||
|
||||
|
||||
if (!(p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A)))
|
||||
return 0;
|
||||
|
||||
func_start = odm_get_current_time(p_dm_odm);
|
||||
p_dm_odm->noise_level.noise_all = 0;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_inband_noise_monitor_ac_series() ==>\n"));
|
||||
|
||||
/* step 1. Disable DIG && Set initial gain. */
|
||||
if (is_pause_dig)
|
||||
odm_pause_dig(p_dm_odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value);
|
||||
|
||||
/* step 2. Disable all power save for read registers */
|
||||
/*dcmd_DebugControlPowerSave(p_adapter, PSDisable); */
|
||||
|
||||
/* step 3. Get noise power level */
|
||||
start = odm_get_current_time(p_dm_odm);
|
||||
|
||||
/* reset counters */
|
||||
sum = 0;
|
||||
valid_cnt = 0;
|
||||
|
||||
/* step 3. Get noise power level */
|
||||
while (1) {
|
||||
/*Set IGI=0x1C */
|
||||
odm_write_dig(p_dm_odm, 0x1C);
|
||||
/*stop CK320&CK88 */
|
||||
odm_set_bb_reg(p_dm_odm, 0x8B4, BIT(6), 1);
|
||||
/*Read path-A */
|
||||
odm_set_bb_reg(p_dm_odm, 0x8FC, MASKDWORD, 0x200); /*set debug port*/
|
||||
value32 = odm_get_bb_reg(p_dm_odm, 0xFA0, MASKDWORD); /*read debug port*/
|
||||
|
||||
rxi_buf_anta = (value32 & 0xFFC00) >> 10; /*rxi_buf_anta=RegFA0[19:10]*/
|
||||
rxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/
|
||||
|
||||
pd_flag = (bool)((value32 & BIT(31)) >> 31);
|
||||
|
||||
/*Not in packet detection period or Tx state */
|
||||
if ((!pd_flag) || (rxi_buf_anta != 0x200)) {
|
||||
/*sign conversion*/
|
||||
rxi_buf_anta = odm_sign_conversion(rxi_buf_anta, 10);
|
||||
rxq_buf_anta = odm_sign_conversion(rxq_buf_anta, 10);
|
||||
|
||||
pwdb_A = odm_pwdb_conversion(rxi_buf_anta * rxi_buf_anta + rxq_buf_anta * rxq_buf_anta, 20, 18); /*S(10,9)*S(10,9)=S(20,18)*/
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n", pwdb_A, rxi_buf_anta & 0x3FF, rxq_buf_anta & 0x3FF));
|
||||
}
|
||||
/*Start CK320&CK88*/
|
||||
odm_set_bb_reg(p_dm_odm, 0x8B4, BIT(6), 0);
|
||||
/*BB Reset*/
|
||||
odm_write_1byte(p_dm_odm, 0x02, odm_read_1byte(p_dm_odm, 0x02) & (~BIT(0)));
|
||||
odm_write_1byte(p_dm_odm, 0x02, odm_read_1byte(p_dm_odm, 0x02) | BIT(0));
|
||||
/*PMAC Reset*/
|
||||
odm_write_1byte(p_dm_odm, 0xB03, odm_read_1byte(p_dm_odm, 0xB03) & (~BIT(0)));
|
||||
odm_write_1byte(p_dm_odm, 0xB03, odm_read_1byte(p_dm_odm, 0xB03) | BIT(0));
|
||||
/*CCK Reset*/
|
||||
if (odm_read_1byte(p_dm_odm, 0x80B) & BIT(4)) {
|
||||
odm_write_1byte(p_dm_odm, 0x80B, odm_read_1byte(p_dm_odm, 0x80B) & (~BIT(4)));
|
||||
odm_write_1byte(p_dm_odm, 0x80B, odm_read_1byte(p_dm_odm, 0x80B) | BIT(4));
|
||||
}
|
||||
|
||||
sval = pwdb_A;
|
||||
|
||||
if (sval < 0 && sval >= -27) {
|
||||
if (valid_cnt < VALID_CNT) {
|
||||
valid_cnt++;
|
||||
sum += sval;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Valid sval = %d\n", sval));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Sum of sval = %d,\n", sum));
|
||||
if ((valid_cnt >= VALID_CNT) || (odm_get_progressing_time(p_dm_odm, start) > max_time)) {
|
||||
sum /= VALID_CNT;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, sum = %d\n", sum));
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*ADC backoff is 12dB,*/
|
||||
/*Ptarget=0x1C-110=-82dBm*/
|
||||
noise = sum + 12 + 0x1C - 110;
|
||||
|
||||
/*Offset*/
|
||||
noise = noise - 3;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("noise = %d\n", noise));
|
||||
p_dm_odm->noise_level.noise_all = (s16)noise;
|
||||
|
||||
/* step 4. Recover the Dig*/
|
||||
if (is_pause_dig)
|
||||
odm_pause_dig(p_dm_odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value);
|
||||
|
||||
func_end = odm_get_progressing_time(p_dm_odm, func_start);
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_inband_noise_monitor_ac_series() <==\n"));
|
||||
|
||||
return p_dm_odm->noise_level.noise_all;
|
||||
}
|
||||
|
||||
|
||||
|
||||
s16
|
||||
odm_inband_noise_monitor(void *p_dm_void, u8 is_pause_dig, u8 igi_value, u32 max_time)
|
||||
{
|
||||
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)
|
||||
return odm_inband_noise_monitor_ac_series(p_dm_odm, is_pause_dig, igi_value, max_time);
|
||||
else
|
||||
return odm_inband_noise_monitor_n_series(p_dm_odm, is_pause_dig, igi_value, max_time);
|
||||
}
|
||||
|
||||
#endif
|
||||
47
hal/phydm/phydm_noisemonitor.h
Normal file
47
hal/phydm/phydm_noisemonitor.h
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __ODMNOISEMONITOR_H__
|
||||
#define __ODMNOISEMONITOR_H__
|
||||
|
||||
#define ODM_MAX_CHANNEL_NUM 38/* 14+24 */
|
||||
struct noise_level {
|
||||
/* u8 value_a, value_b; */
|
||||
u8 value[MAX_RF_PATH];
|
||||
/* s8 sval_a, sval_b; */
|
||||
s8 sval[MAX_RF_PATH];
|
||||
|
||||
/* s32 noise_a=0, noise_b=0,sum_a=0, sum_b=0; */
|
||||
/* s32 noise[ODM_RF_PATH_MAX]; */
|
||||
s32 sum[MAX_RF_PATH];
|
||||
/* u8 valid_cnt_a=0, valid_cnt_b=0, */
|
||||
u8 valid[MAX_RF_PATH];
|
||||
u8 valid_cnt[MAX_RF_PATH];
|
||||
|
||||
};
|
||||
|
||||
|
||||
struct _ODM_NOISE_MONITOR_ {
|
||||
s8 noise[MAX_RF_PATH];
|
||||
s16 noise_all;
|
||||
};
|
||||
|
||||
s16 odm_inband_noise_monitor(void *p_dm_void, u8 is_pause_dig, u8 igi_value, u32 max_time);
|
||||
|
||||
#endif
|
||||
696
hal/phydm/phydm_pathdiv.c
Normal file
696
hal/phydm/phydm_pathdiv.c
Normal file
|
|
@ -0,0 +1,696 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* ************************************************************
|
||||
* include files
|
||||
* ************************************************************ */
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
#if (defined(CONFIG_PATH_DIVERSITY))
|
||||
#if RTL8814A_SUPPORT
|
||||
|
||||
void
|
||||
phydm_dtp_fix_tx_path(
|
||||
void *p_dm_void,
|
||||
u8 path
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &p_dm_odm->dm_path_div;
|
||||
u8 i, num_enable_path = 0;
|
||||
|
||||
if (path == p_dm_path_div->pre_tx_path)
|
||||
return;
|
||||
else
|
||||
p_dm_path_div->pre_tx_path = path;
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(18) | BIT(19), 3);
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
if (path & BIT(i))
|
||||
num_enable_path++;
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" number of trun-on path : (( %d ))\n", num_enable_path));
|
||||
|
||||
if (num_enable_path == 1) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, 0xf00000, path);
|
||||
|
||||
if (path == PHYDM_A) { /* 1-1 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A ))\n"));
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0);
|
||||
} else if (path == PHYDM_B) { /* 1-2 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B ))\n"));
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 0);
|
||||
} else if (path == PHYDM_C) { /* 1-3 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( C ))\n"));
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 0);
|
||||
|
||||
} else if (path == PHYDM_D) { /* 1-4 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( D ))\n"));
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 0);
|
||||
}
|
||||
|
||||
} else if (num_enable_path == 2) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, 0xf00000, path);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, 0xf0, path);
|
||||
|
||||
if (path == PHYDM_AB) { /* 2-1 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B ))\n"));
|
||||
/* set for 1ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 1);
|
||||
/* set for 2ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 1);
|
||||
} else if (path == PHYDM_AC) { /* 2-2 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A C ))\n"));
|
||||
/* set for 1ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 1);
|
||||
/* set for 2ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 1);
|
||||
} else if (path == PHYDM_AD) { /* 2-3 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A D ))\n"));
|
||||
/* set for 1ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 1);
|
||||
/* set for 2ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 1);
|
||||
} else if (path == PHYDM_BC) { /* 2-4 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B C ))\n"));
|
||||
/* set for 1ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 1);
|
||||
/* set for 2ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 1);
|
||||
} else if (path == PHYDM_BD) { /* 2-5 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B D ))\n"));
|
||||
/* set for 1ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 1);
|
||||
/* set for 2ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 1);
|
||||
} else if (path == PHYDM_CD) { /* 2-6 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( C D ))\n"));
|
||||
/* set for 1ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 1);
|
||||
/* set for 2ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 1);
|
||||
}
|
||||
|
||||
} else if (num_enable_path == 3) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, 0xf00000, path);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, 0xf0, path);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, 0xf0000, path);
|
||||
|
||||
if (path == PHYDM_ABC) { /* 3-1 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B C))\n"));
|
||||
/* set for 1ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 2);
|
||||
/* set for 2ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 2);
|
||||
/* set for 3ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(21) | BIT(20), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(23) | BIT(22), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(25) | BIT(24), 2);
|
||||
} else if (path == PHYDM_ABD) { /* 3-2 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B D ))\n"));
|
||||
/* set for 1ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 2);
|
||||
/* set for 2ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 2);
|
||||
/* set for 3ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(21) | BIT(20), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(23) | BIT(22), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(27) | BIT(26), 2);
|
||||
|
||||
} else if (path == PHYDM_ACD) { /* 3-3 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A C D ))\n"));
|
||||
/* set for 1ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 2);
|
||||
/* set for 2ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 2);
|
||||
/* set for 3ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(21) | BIT(20), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(25) | BIT(24), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(27) | BIT(26), 2);
|
||||
} else if (path == PHYDM_BCD) { /* 3-4 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B C D))\n"));
|
||||
/* set for 1ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 2);
|
||||
/* set for 2ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 2);
|
||||
/* set for 3ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(23) | BIT(22), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(25) | BIT(24), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(27) | BIT(26), 2);
|
||||
}
|
||||
} else if (num_enable_path == 4)
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path ((A B C D))\n"));
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
phydm_find_default_path(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &p_dm_odm->dm_path_div;
|
||||
u32 rssi_avg_a = 0, rssi_avg_b = 0, rssi_avg_c = 0, rssi_avg_d = 0, rssi_avg_bcd = 0;
|
||||
u32 rssi_total_a = 0, rssi_total_b = 0, rssi_total_c = 0, rssi_total_d = 0;
|
||||
|
||||
/* 2 Default path Selection By RSSI */
|
||||
|
||||
rssi_avg_a = (p_dm_path_div->path_a_cnt_all > 0) ? (p_dm_path_div->path_a_sum_all / p_dm_path_div->path_a_cnt_all) : 0 ;
|
||||
rssi_avg_b = (p_dm_path_div->path_b_cnt_all > 0) ? (p_dm_path_div->path_b_sum_all / p_dm_path_div->path_b_cnt_all) : 0 ;
|
||||
rssi_avg_c = (p_dm_path_div->path_c_cnt_all > 0) ? (p_dm_path_div->path_c_sum_all / p_dm_path_div->path_c_cnt_all) : 0 ;
|
||||
rssi_avg_d = (p_dm_path_div->path_d_cnt_all > 0) ? (p_dm_path_div->path_d_sum_all / p_dm_path_div->path_d_cnt_all) : 0 ;
|
||||
|
||||
|
||||
p_dm_path_div->path_a_sum_all = 0;
|
||||
p_dm_path_div->path_a_cnt_all = 0;
|
||||
p_dm_path_div->path_b_sum_all = 0;
|
||||
p_dm_path_div->path_b_cnt_all = 0;
|
||||
p_dm_path_div->path_c_sum_all = 0;
|
||||
p_dm_path_div->path_c_cnt_all = 0;
|
||||
p_dm_path_div->path_d_sum_all = 0;
|
||||
p_dm_path_div->path_d_cnt_all = 0;
|
||||
|
||||
if (p_dm_path_div->use_path_a_as_default_ant == 1) {
|
||||
rssi_avg_bcd = (rssi_avg_b + rssi_avg_c + rssi_avg_d) / 3;
|
||||
|
||||
if ((rssi_avg_a + ANT_DECT_RSSI_TH) > rssi_avg_bcd) {
|
||||
p_dm_path_div->is_path_a_exist = true;
|
||||
p_dm_path_div->default_path = PATH_A;
|
||||
} else
|
||||
p_dm_path_div->is_path_a_exist = false;
|
||||
} else {
|
||||
if ((rssi_avg_a >= rssi_avg_b) && (rssi_avg_a >= rssi_avg_c) && (rssi_avg_a >= rssi_avg_d))
|
||||
p_dm_path_div->default_path = PATH_A;
|
||||
else if ((rssi_avg_b >= rssi_avg_c) && (rssi_avg_b >= rssi_avg_d))
|
||||
p_dm_path_div->default_path = PATH_B;
|
||||
else if (rssi_avg_c >= rssi_avg_d)
|
||||
p_dm_path_div->default_path = PATH_C;
|
||||
else
|
||||
p_dm_path_div->default_path = PATH_D;
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
phydm_candidate_dtp_update(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &p_dm_odm->dm_path_div;
|
||||
|
||||
p_dm_path_div->num_candidate = 3;
|
||||
|
||||
if (p_dm_path_div->use_path_a_as_default_ant == 1) {
|
||||
if (p_dm_path_div->num_tx_path == 3) {
|
||||
if (p_dm_path_div->is_path_a_exist) {
|
||||
p_dm_path_div->ant_candidate_1 = PHYDM_ABC;
|
||||
p_dm_path_div->ant_candidate_2 = PHYDM_ABD;
|
||||
p_dm_path_div->ant_candidate_3 = PHYDM_ACD;
|
||||
} else { /* use path BCD */
|
||||
p_dm_path_div->num_candidate = 1;
|
||||
phydm_dtp_fix_tx_path(p_dm_odm, PHYDM_BCD);
|
||||
return;
|
||||
}
|
||||
} else if (p_dm_path_div->num_tx_path == 2) {
|
||||
if (p_dm_path_div->is_path_a_exist) {
|
||||
p_dm_path_div->ant_candidate_1 = PHYDM_AB;
|
||||
p_dm_path_div->ant_candidate_2 = PHYDM_AC;
|
||||
p_dm_path_div->ant_candidate_3 = PHYDM_AD;
|
||||
} else {
|
||||
p_dm_path_div->ant_candidate_1 = PHYDM_BC;
|
||||
p_dm_path_div->ant_candidate_2 = PHYDM_BD;
|
||||
p_dm_path_div->ant_candidate_3 = PHYDM_CD;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
/* 2 3 TX mode */
|
||||
if (p_dm_path_div->num_tx_path == 3) { /* choose 3 ant form 4 */
|
||||
if (p_dm_path_div->default_path == PATH_A) { /* choose 2 ant form 3 */
|
||||
p_dm_path_div->ant_candidate_1 = PHYDM_ABC;
|
||||
p_dm_path_div->ant_candidate_2 = PHYDM_ABD;
|
||||
p_dm_path_div->ant_candidate_3 = PHYDM_ACD;
|
||||
} else if (p_dm_path_div->default_path == PATH_B) {
|
||||
p_dm_path_div->ant_candidate_1 = PHYDM_ABC;
|
||||
p_dm_path_div->ant_candidate_2 = PHYDM_ABD;
|
||||
p_dm_path_div->ant_candidate_3 = PHYDM_BCD;
|
||||
} else if (p_dm_path_div->default_path == PATH_C) {
|
||||
p_dm_path_div->ant_candidate_1 = PHYDM_ABC;
|
||||
p_dm_path_div->ant_candidate_2 = PHYDM_ACD;
|
||||
p_dm_path_div->ant_candidate_3 = PHYDM_BCD;
|
||||
} else if (p_dm_path_div->default_path == PATH_D) {
|
||||
p_dm_path_div->ant_candidate_1 = PHYDM_ABD;
|
||||
p_dm_path_div->ant_candidate_2 = PHYDM_ACD;
|
||||
p_dm_path_div->ant_candidate_3 = PHYDM_BCD;
|
||||
}
|
||||
}
|
||||
|
||||
/* 2 2 TX mode */
|
||||
else if (p_dm_path_div->num_tx_path == 2) { /* choose 2 ant form 4 */
|
||||
if (p_dm_path_div->default_path == PATH_A) { /* choose 2 ant form 3 */
|
||||
p_dm_path_div->ant_candidate_1 = PHYDM_AB;
|
||||
p_dm_path_div->ant_candidate_2 = PHYDM_AC;
|
||||
p_dm_path_div->ant_candidate_3 = PHYDM_AD;
|
||||
} else if (p_dm_path_div->default_path == PATH_B) {
|
||||
p_dm_path_div->ant_candidate_1 = PHYDM_AB;
|
||||
p_dm_path_div->ant_candidate_2 = PHYDM_BC;
|
||||
p_dm_path_div->ant_candidate_3 = PHYDM_BD;
|
||||
} else if (p_dm_path_div->default_path == PATH_C) {
|
||||
p_dm_path_div->ant_candidate_1 = PHYDM_AC;
|
||||
p_dm_path_div->ant_candidate_2 = PHYDM_BC;
|
||||
p_dm_path_div->ant_candidate_3 = PHYDM_CD;
|
||||
} else if (p_dm_path_div->default_path == PATH_D) {
|
||||
p_dm_path_div->ant_candidate_1 = PHYDM_AD;
|
||||
p_dm_path_div->ant_candidate_2 = PHYDM_BD;
|
||||
p_dm_path_div->ant_candidate_3 = PHYDM_CD;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
phydm_dynamic_tx_path(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &p_dm_odm->dm_path_div;
|
||||
|
||||
struct sta_info *p_entry;
|
||||
u32 i;
|
||||
u8 num_client = 0;
|
||||
u8 h2c_parameter[6] = {0};
|
||||
|
||||
|
||||
if (!p_dm_odm->is_linked) { /* is_linked==False */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("DTP_8814 [No Link!!!]\n"));
|
||||
|
||||
if (p_dm_path_div->is_become_linked == true) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" [Be disconnected]----->\n"));
|
||||
p_dm_path_div->is_become_linked = p_dm_odm->is_linked;
|
||||
}
|
||||
return;
|
||||
} else {
|
||||
if (p_dm_path_div->is_become_linked == false) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" [Be Linked !!!]----->\n"));
|
||||
p_dm_path_div->is_become_linked = p_dm_odm->is_linked;
|
||||
}
|
||||
}
|
||||
|
||||
/* 2 [period CTRL] */
|
||||
if (p_dm_path_div->dtp_period >= 2)
|
||||
p_dm_path_div->dtp_period = 0;
|
||||
else {
|
||||
/* ODM_RT_TRACE(p_dm_odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Phydm_Dynamic_Tx_Path_8814A() Stay = (( %d ))\n",p_dm_path_div->dtp_period)); */
|
||||
p_dm_path_div->dtp_period++;
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/* 2 [Fix path] */
|
||||
if (p_dm_odm->path_select != PHYDM_AUTO_PATH)
|
||||
return;
|
||||
|
||||
/* 2 [Check Bfer] */
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
{
|
||||
enum beamforming_cap beamform_cap = (p_dm_odm->beamforming_info.beamform_cap);
|
||||
|
||||
if (beamform_cap & BEAMFORMER_CAP) { /* BFmer On && Div On->Div Off */
|
||||
if (p_dm_path_div->fix_path_bfer == 0) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("[ PathDiv : OFF ] BFmer ==1\n"));
|
||||
p_dm_path_div->fix_path_bfer = 1 ;
|
||||
}
|
||||
return;
|
||||
} else { /* BFmer Off && Div Off->Div On */
|
||||
if (p_dm_path_div->fix_path_bfer == 1) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("[ PathDiv : ON ] BFmer ==0\n"));
|
||||
p_dm_path_div->fix_path_bfer = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
if (p_dm_path_div->use_path_a_as_default_ant == 1) {
|
||||
phydm_find_default_path(p_dm_odm);
|
||||
phydm_candidate_dtp_update(p_dm_odm);
|
||||
} else {
|
||||
if (p_dm_path_div->phydm_dtp_state == PHYDM_DTP_INIT) {
|
||||
phydm_find_default_path(p_dm_odm);
|
||||
phydm_candidate_dtp_update(p_dm_odm);
|
||||
p_dm_path_div->phydm_dtp_state = PHYDM_DTP_RUNNING_1;
|
||||
}
|
||||
|
||||
else if (p_dm_path_div->phydm_dtp_state == PHYDM_DTP_RUNNING_1) {
|
||||
p_dm_path_div->dtp_check_patha_counter++;
|
||||
|
||||
if (p_dm_path_div->dtp_check_patha_counter >= NUM_RESET_DTP_PERIOD) {
|
||||
p_dm_path_div->dtp_check_patha_counter = 0;
|
||||
p_dm_path_div->phydm_dtp_state = PHYDM_DTP_INIT;
|
||||
}
|
||||
/* 2 Search space update */
|
||||
else {
|
||||
/* 1. find the worst candidate */
|
||||
|
||||
|
||||
/* 2. repalce the worst candidate */
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* 2 Dynamic path Selection H2C */
|
||||
|
||||
if (p_dm_path_div->num_candidate == 1)
|
||||
return;
|
||||
else {
|
||||
h2c_parameter[0] = p_dm_path_div->num_candidate;
|
||||
h2c_parameter[1] = p_dm_path_div->num_tx_path;
|
||||
h2c_parameter[2] = p_dm_path_div->ant_candidate_1;
|
||||
h2c_parameter[3] = p_dm_path_div->ant_candidate_2;
|
||||
h2c_parameter[4] = p_dm_path_div->ant_candidate_3;
|
||||
|
||||
odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_DYNAMIC_TX_PATH, 6, h2c_parameter);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
void
|
||||
phydm_dynamic_tx_path_init(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &(p_dm_odm->dm_path_div);
|
||||
struct _ADAPTER *p_adapter = p_dm_odm->adapter;
|
||||
#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) && USB_SWITCH_SUPPORT)
|
||||
USB_MODE_MECH *p_usb_mode_mech = &p_adapter->usb_mode_mechanism;
|
||||
#endif
|
||||
u8 search_space_2[NUM_CHOOSE2_FROM4] = {PHYDM_AB, PHYDM_AC, PHYDM_AD, PHYDM_BC, PHYDM_BD, PHYDM_CD };
|
||||
u8 search_space_3[NUM_CHOOSE3_FROM4] = {PHYDM_BCD, PHYDM_ACD, PHYDM_ABD, PHYDM_ABC};
|
||||
|
||||
#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) && USB_SWITCH_SUPPORT)
|
||||
p_dm_path_div->is_u3_mode = (p_usb_mode_mech->cur_usb_mode == USB_MODE_U3) ? 1 : 0 ;
|
||||
#else
|
||||
p_dm_path_div->is_u3_mode = 1;
|
||||
#endif
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Dynamic TX path Init 8814\n"));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("is_u3_mode = (( %d ))\n", p_dm_path_div->is_u3_mode));
|
||||
|
||||
memcpy(&(p_dm_path_div->search_space_2[0]), &(search_space_2[0]), NUM_CHOOSE2_FROM4);
|
||||
memcpy(&(p_dm_path_div->search_space_3[0]), &(search_space_3[0]), NUM_CHOOSE3_FROM4);
|
||||
|
||||
p_dm_path_div->use_path_a_as_default_ant = 1;
|
||||
p_dm_path_div->phydm_dtp_state = PHYDM_DTP_INIT;
|
||||
p_dm_odm->path_select = PHYDM_AUTO_PATH;
|
||||
p_dm_path_div->phydm_path_div_type = PHYDM_4R_PATH_DIV;
|
||||
|
||||
|
||||
if (p_dm_path_div->is_u3_mode) {
|
||||
p_dm_path_div->num_tx_path = 3;
|
||||
phydm_dtp_fix_tx_path(p_dm_odm, PHYDM_BCD);/* 3TX Set Init TX path*/
|
||||
|
||||
} else {
|
||||
p_dm_path_div->num_tx_path = 2;
|
||||
phydm_dtp_fix_tx_path(p_dm_odm, PHYDM_BC);/* 2TX // Set Init TX path*/
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
phydm_process_rssi_for_path_div(
|
||||
void *p_dm_void,
|
||||
void *p_phy_info_void,
|
||||
void *p_pkt_info_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)p_phy_info_void;
|
||||
struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pkt_info_void;
|
||||
struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &(p_dm_odm->dm_path_div);
|
||||
|
||||
if (p_pktinfo->is_packet_to_self || p_pktinfo->is_packet_match_bssid) {
|
||||
if (p_pktinfo->data_rate > ODM_RATE11M) {
|
||||
if (p_dm_path_div->phydm_path_div_type == PHYDM_4R_PATH_DIV) {
|
||||
#if RTL8814A_SUPPORT
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8814A) {
|
||||
p_dm_path_div->path_a_sum_all += p_phy_info->rx_mimo_signal_strength[0];
|
||||
p_dm_path_div->path_a_cnt_all++;
|
||||
|
||||
p_dm_path_div->path_b_sum_all += p_phy_info->rx_mimo_signal_strength[1];
|
||||
p_dm_path_div->path_b_cnt_all++;
|
||||
|
||||
p_dm_path_div->path_c_sum_all += p_phy_info->rx_mimo_signal_strength[2];
|
||||
p_dm_path_div->path_c_cnt_all++;
|
||||
|
||||
p_dm_path_div->path_d_sum_all += p_phy_info->rx_mimo_signal_strength[3];
|
||||
p_dm_path_div->path_d_cnt_all++;
|
||||
}
|
||||
#endif
|
||||
} else {
|
||||
p_dm_path_div->path_a_sum[p_pktinfo->station_id] += p_phy_info->rx_mimo_signal_strength[0];
|
||||
p_dm_path_div->path_a_cnt[p_pktinfo->station_id]++;
|
||||
|
||||
p_dm_path_div->path_b_sum[p_pktinfo->station_id] += p_phy_info->rx_mimo_signal_strength[1];
|
||||
p_dm_path_div->path_b_cnt[p_pktinfo->station_id]++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
#endif /* #if RTL8814A_SUPPORT */
|
||||
|
||||
void
|
||||
odm_pathdiv_debug(
|
||||
void *p_dm_void,
|
||||
u32 *const dm_value,
|
||||
u32 *_used,
|
||||
char *output,
|
||||
u32 *_out_len
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &(p_dm_odm->dm_path_div);
|
||||
u32 used = *_used;
|
||||
u32 out_len = *_out_len;
|
||||
|
||||
p_dm_odm->path_select = (dm_value[0] & 0xf);
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "Path_select = (( 0x%x ))\n", p_dm_odm->path_select));
|
||||
|
||||
/* 2 [Fix path] */
|
||||
if (p_dm_odm->path_select != PHYDM_AUTO_PATH) {
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "Trun on path [%s%s%s%s]\n",
|
||||
((p_dm_odm->path_select) & 0x1) ? "A" : "",
|
||||
((p_dm_odm->path_select) & 0x2) ? "B" : "",
|
||||
((p_dm_odm->path_select) & 0x4) ? "C" : "",
|
||||
((p_dm_odm->path_select) & 0x8) ? "D" : ""));
|
||||
|
||||
phydm_dtp_fix_tx_path(p_dm_odm, p_dm_odm->path_select);
|
||||
} else
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "Auto path"));
|
||||
}
|
||||
|
||||
#endif /* #if(defined(CONFIG_PATH_DIVERSITY)) */
|
||||
|
||||
void
|
||||
phydm_c2h_dtp_handler(
|
||||
void *p_dm_void,
|
||||
u8 *cmd_buf,
|
||||
u8 cmd_len
|
||||
)
|
||||
{
|
||||
#if (defined(CONFIG_PATH_DIVERSITY))
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &(p_dm_odm->dm_path_div);
|
||||
|
||||
u8 macid = cmd_buf[0];
|
||||
u8 target = cmd_buf[1];
|
||||
u8 nsc_1 = cmd_buf[2];
|
||||
u8 nsc_2 = cmd_buf[3];
|
||||
u8 nsc_3 = cmd_buf[4];
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Target_candidate = (( %d ))\n", target));
|
||||
/*
|
||||
if( (nsc_1 >= nsc_2) && (nsc_1 >= nsc_3))
|
||||
{
|
||||
phydm_dtp_fix_tx_path(p_dm_odm, p_dm_path_div->ant_candidate_1);
|
||||
}
|
||||
else if( nsc_2 >= nsc_3)
|
||||
{
|
||||
phydm_dtp_fix_tx_path(p_dm_odm, p_dm_path_div->ant_candidate_2);
|
||||
}
|
||||
else
|
||||
{
|
||||
phydm_dtp_fix_tx_path(p_dm_odm, p_dm_path_div->ant_candidate_3);
|
||||
}
|
||||
*/
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
odm_path_diversity(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
#if (defined(CONFIG_PATH_DIVERSITY))
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
if (!(p_dm_odm->support_ability & ODM_BB_PATH_DIV)) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Return: Not Support PathDiv\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
#if RTL8812A_SUPPORT
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8812)
|
||||
odm_path_diversity_8812a(p_dm_odm);
|
||||
else
|
||||
#endif
|
||||
|
||||
#if RTL8814A_SUPPORT
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
phydm_dynamic_tx_path(p_dm_odm);
|
||||
else
|
||||
#endif
|
||||
{}
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
odm_path_diversity_init(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
#if (defined(CONFIG_PATH_DIVERSITY))
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
|
||||
/*p_dm_odm->support_ability |= ODM_BB_PATH_DIV;*/
|
||||
|
||||
if (p_dm_odm->mp_mode == true)
|
||||
return;
|
||||
|
||||
if (!(p_dm_odm->support_ability & ODM_BB_PATH_DIV)) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Return: Not Support PathDiv\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
#if RTL8812A_SUPPORT
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8812)
|
||||
odm_path_diversity_init_8812a(p_dm_odm);
|
||||
else
|
||||
#endif
|
||||
|
||||
#if RTL8814A_SUPPORT
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
phydm_dynamic_tx_path_init(p_dm_odm);
|
||||
else
|
||||
#endif
|
||||
{}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
/*
|
||||
* 2011/12/02 MH Copy from MP oursrc for temporarily test.
|
||||
* */
|
||||
|
||||
void
|
||||
odm_path_div_chk_ant_switch_callback(
|
||||
struct timer_list *p_timer
|
||||
)
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
odm_path_div_chk_ant_switch_workitem_callback(
|
||||
void *p_context
|
||||
)
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
odm_cck_tx_path_diversity_callback(
|
||||
struct timer_list *p_timer
|
||||
)
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
odm_cck_tx_path_diversity_work_item_callback(
|
||||
void *p_context
|
||||
)
|
||||
{
|
||||
}
|
||||
u8
|
||||
odm_sw_ant_div_select_scan_chnl(
|
||||
struct _ADAPTER *adapter
|
||||
)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
void
|
||||
odm_sw_ant_div_construct_scan_chnl(
|
||||
struct _ADAPTER *adapter,
|
||||
u8 scan_chnl
|
||||
)
|
||||
{
|
||||
}
|
||||
|
||||
#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) */
|
||||
319
hal/phydm/phydm_pathdiv.h
Normal file
319
hal/phydm/phydm_pathdiv.h
Normal file
|
|
@ -0,0 +1,319 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMPATHDIV_H__
|
||||
#define __PHYDMPATHDIV_H__
|
||||
/*#define PATHDIV_VERSION "2.0" //2014.11.04*/
|
||||
#define PATHDIV_VERSION "3.1" /*2015.07.29 by YuChen*/
|
||||
|
||||
#if (defined(CONFIG_PATH_DIVERSITY))
|
||||
#define USE_PATH_A_AS_DEFAULT_ANT /* for 8814 dynamic TX path selection */
|
||||
|
||||
#define NUM_RESET_DTP_PERIOD 5
|
||||
#define ANT_DECT_RSSI_TH 3
|
||||
|
||||
#define PATH_A 1
|
||||
#define PATH_B 2
|
||||
#define PATH_C 3
|
||||
#define PATH_D 4
|
||||
|
||||
#define PHYDM_AUTO_PATH 0
|
||||
#define PHYDM_FIX_PATH 1
|
||||
|
||||
#define NUM_CHOOSE2_FROM4 6
|
||||
#define NUM_CHOOSE3_FROM4 4
|
||||
|
||||
|
||||
#define PHYDM_A BIT(0)
|
||||
#define PHYDM_B BIT(1)
|
||||
#define PHYDM_C BIT(2)
|
||||
#define PHYDM_D BIT(3)
|
||||
#define PHYDM_AB (BIT(0) | BIT1) /* 0 */
|
||||
#define PHYDM_AC (BIT(0) | BIT2) /* 1 */
|
||||
#define PHYDM_AD (BIT(0) | BIT3) /* 2 */
|
||||
#define PHYDM_BC (BIT(1) | BIT2) /* 3 */
|
||||
#define PHYDM_BD (BIT(1) | BIT3) /* 4 */
|
||||
#define PHYDM_CD (BIT(2) | BIT3) /* 5 */
|
||||
|
||||
#define PHYDM_ABC (BIT(0) | BIT1 | BIT2) /* 0*/
|
||||
#define PHYDM_ABD (BIT(0) | BIT1 | BIT3) /* 1*/
|
||||
#define PHYDM_ACD (BIT(0) | BIT2 | BIT3) /* 2*/
|
||||
#define PHYDM_BCD (BIT(1) | BIT2 | BIT3) /* 3*/
|
||||
|
||||
#define PHYDM_ABCD (BIT(0) | BIT(1) | BIT(2) | BIT(3))
|
||||
|
||||
|
||||
enum phydm_dtp_state {
|
||||
PHYDM_DTP_INIT = 1,
|
||||
PHYDM_DTP_RUNNING_1
|
||||
|
||||
};
|
||||
|
||||
enum phydm_path_div_type {
|
||||
PHYDM_2R_PATH_DIV = 1,
|
||||
PHYDM_4R_PATH_DIV = 2
|
||||
};
|
||||
|
||||
void
|
||||
phydm_process_rssi_for_path_div(
|
||||
void *p_dm_void,
|
||||
void *p_phy_info_void,
|
||||
void *p_pkt_info_void
|
||||
);
|
||||
|
||||
struct _ODM_PATH_DIVERSITY_ {
|
||||
u8 resp_tx_path;
|
||||
u8 path_sel[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u32 path_a_sum[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u32 path_b_sum[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u16 path_a_cnt[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u16 path_b_cnt[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u8 phydm_path_div_type;
|
||||
#if RTL8814A_SUPPORT
|
||||
|
||||
u32 path_a_sum_all;
|
||||
u32 path_b_sum_all;
|
||||
u32 path_c_sum_all;
|
||||
u32 path_d_sum_all;
|
||||
|
||||
u32 path_a_cnt_all;
|
||||
u32 path_b_cnt_all;
|
||||
u32 path_c_cnt_all;
|
||||
u32 path_d_cnt_all;
|
||||
|
||||
u8 dtp_period;
|
||||
bool is_become_linked;
|
||||
bool is_u3_mode;
|
||||
u8 num_tx_path;
|
||||
u8 default_path;
|
||||
u8 num_candidate;
|
||||
u8 ant_candidate_1;
|
||||
u8 ant_candidate_2;
|
||||
u8 ant_candidate_3;
|
||||
u8 phydm_dtp_state;
|
||||
u8 dtp_check_patha_counter;
|
||||
bool fix_path_bfer;
|
||||
u8 search_space_2[NUM_CHOOSE2_FROM4];
|
||||
u8 search_space_3[NUM_CHOOSE3_FROM4];
|
||||
|
||||
u8 pre_tx_path;
|
||||
u8 use_path_a_as_default_ant;
|
||||
bool is_path_a_exist;
|
||||
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
#endif /* #if(defined(CONFIG_PATH_DIVERSITY)) */
|
||||
|
||||
void
|
||||
phydm_c2h_dtp_handler(
|
||||
void *p_dm_void,
|
||||
u8 *cmd_buf,
|
||||
u8 cmd_len
|
||||
);
|
||||
|
||||
void
|
||||
odm_path_diversity_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_path_diversity(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_pathdiv_debug(
|
||||
void *p_dm_void,
|
||||
u32 *const dm_value,
|
||||
u32 *_used,
|
||||
char *output,
|
||||
u32 *_out_len
|
||||
);
|
||||
|
||||
|
||||
|
||||
/* 1 [OLD IC]-------------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
|
||||
|
||||
/* #define PATHDIV_ENABLE 1 */
|
||||
#define dm_path_div_rssi_check odm_path_div_chk_per_pkt_rssi
|
||||
#define path_div_check_before_link8192c odm_path_diversity_before_link92c
|
||||
|
||||
|
||||
|
||||
|
||||
struct _path_div_parameter_define_ {
|
||||
u32 org_5g_rege30;
|
||||
u32 org_5g_regc14;
|
||||
u32 org_5g_regca0;
|
||||
u32 swt_5g_rege30;
|
||||
u32 swt_5g_regc14;
|
||||
u32 swt_5g_regca0;
|
||||
/* for 2G IQK information */
|
||||
u32 org_2g_regc80;
|
||||
u32 org_2g_regc4c;
|
||||
u32 org_2g_regc94;
|
||||
u32 org_2g_regc14;
|
||||
u32 org_2g_regca0;
|
||||
|
||||
u32 swt_2g_regc80;
|
||||
u32 swt_2g_regc4c;
|
||||
u32 swt_2g_regc94;
|
||||
u32 swt_2g_regc14;
|
||||
u32 swt_2g_regca0;
|
||||
};
|
||||
|
||||
void
|
||||
odm_path_diversity_init_92c(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_2t_path_diversity_init_92c(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_1t_path_diversity_init_92c(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
bool
|
||||
odm_is_connected_92c(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
bool
|
||||
odm_path_diversity_before_link92c(
|
||||
/* struct _ADAPTER* adapter */
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
void
|
||||
odm_path_diversity_after_link_92c(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_set_resp_path_92c(
|
||||
struct _ADAPTER *adapter,
|
||||
u8 default_resp_path
|
||||
);
|
||||
|
||||
void
|
||||
odm_ofdm_tx_path_diversity_92c(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_cck_tx_path_diversity_92c(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_reset_path_diversity_92c(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_cck_tx_path_diversity_callback(
|
||||
struct timer_list *p_timer
|
||||
);
|
||||
|
||||
void
|
||||
odm_cck_tx_path_diversity_work_item_callback(
|
||||
void *p_context
|
||||
);
|
||||
|
||||
void
|
||||
odm_path_div_chk_ant_switch_callback(
|
||||
struct timer_list *p_timer
|
||||
);
|
||||
|
||||
void
|
||||
odm_path_div_chk_ant_switch_workitem_callback(
|
||||
void *p_context
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
odm_path_div_chk_ant_switch(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
void
|
||||
odm_cck_path_diversity_chk_per_pkt_rssi(
|
||||
struct _ADAPTER *adapter,
|
||||
bool is_def_port,
|
||||
bool is_match_bssid,
|
||||
struct _WLAN_STA *p_entry,
|
||||
PRT_RFD p_rfd,
|
||||
u8 *p_desc
|
||||
);
|
||||
|
||||
void
|
||||
odm_path_div_chk_per_pkt_rssi(
|
||||
struct _ADAPTER *adapter,
|
||||
bool is_def_port,
|
||||
bool is_match_bssid,
|
||||
struct _WLAN_STA *p_entry,
|
||||
PRT_RFD p_rfd
|
||||
);
|
||||
|
||||
void
|
||||
odm_path_div_rest_after_link(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
void
|
||||
odm_fill_tx_path_in_txdesc(
|
||||
struct _ADAPTER *adapter,
|
||||
PRT_TCB p_tcb,
|
||||
u8 *p_desc
|
||||
);
|
||||
|
||||
void
|
||||
odm_path_div_init_92d(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
u8
|
||||
odm_sw_ant_div_select_scan_chnl(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_sw_ant_div_construct_scan_chnl(
|
||||
struct _ADAPTER *adapter,
|
||||
u8 scan_chnl
|
||||
);
|
||||
|
||||
#endif /* #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) */
|
||||
|
||||
|
||||
#endif /* #ifndef __ODMPATHDIV_H__ */
|
||||
1205
hal/phydm/phydm_powertracking_ap.c
Normal file
1205
hal/phydm/phydm_powertracking_ap.c
Normal file
File diff suppressed because it is too large
Load diff
351
hal/phydm/phydm_powertracking_ap.h
Normal file
351
hal/phydm/phydm_powertracking_ap.h
Normal file
|
|
@ -0,0 +1,351 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMPOWERTRACKING_H__
|
||||
#define __PHYDMPOWERTRACKING_H__
|
||||
|
||||
#define POWRTRACKING_VERSION "1.1"
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#ifdef RTK_AC_SUPPORT
|
||||
#define ODM_IC_11AC_SERIES_SUPPORT 1
|
||||
#else
|
||||
#define ODM_IC_11AC_SERIES_SUPPORT 0
|
||||
#endif
|
||||
#else
|
||||
#define ODM_IC_11AC_SERIES_SUPPORT 1
|
||||
#endif
|
||||
|
||||
#define DPK_DELTA_MAPPING_NUM 13
|
||||
#define index_mapping_HP_NUM 15
|
||||
#define DELTA_SWINGIDX_SIZE 30
|
||||
#define DELTA_SWINTSSI_SIZE 61
|
||||
#define BAND_NUM 3
|
||||
#define MAX_RF_PATH 4
|
||||
#define TXSCALE_TABLE_SIZE 37
|
||||
#define CCK_TABLE_SIZE_8723D 41
|
||||
|
||||
#define IQK_MAC_REG_NUM 4
|
||||
#define IQK_ADDA_REG_NUM 16
|
||||
#define IQK_BB_REG_NUM_MAX 10
|
||||
|
||||
#define IQK_BB_REG_NUM 9
|
||||
|
||||
#define HP_THERMAL_NUM 8
|
||||
|
||||
#define AVG_THERMAL_NUM 8
|
||||
#define iqk_matrix_reg_num 8
|
||||
/* #define IQK_MATRIX_SETTINGS_NUM 1+24+21 */
|
||||
#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
|
||||
|
||||
#if !defined(_OUTSRC_COEXIST)
|
||||
#define OFDM_TABLE_SIZE_92D 43
|
||||
#define OFDM_TABLE_SIZE 37
|
||||
#define CCK_TABLE_SIZE 33
|
||||
#define CCK_TABLE_SIZE_88F 21
|
||||
|
||||
|
||||
|
||||
/* #define OFDM_TABLE_SIZE_92E 54 */
|
||||
/* #define CCK_TABLE_SIZE_92E 54 */
|
||||
extern u32 ofdm_swing_table[OFDM_TABLE_SIZE_92D];
|
||||
extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
|
||||
extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
|
||||
|
||||
|
||||
extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE_92D];
|
||||
extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
|
||||
extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
|
||||
extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
|
||||
extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
|
||||
extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
|
||||
|
||||
#endif
|
||||
|
||||
#define ODM_OFDM_TABLE_SIZE 37
|
||||
#define ODM_CCK_TABLE_SIZE 33
|
||||
/* <20140613, YuChen> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
|
||||
extern u8 delta_swing_table_idx_2ga_p_default[DELTA_SWINGIDX_SIZE];
|
||||
extern u8 delta_swing_table_idx_2ga_n_default[DELTA_SWINGIDX_SIZE];
|
||||
|
||||
static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
|
||||
static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
|
||||
|
||||
/* extern u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E];
|
||||
* extern u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8];
|
||||
* extern u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8]; */
|
||||
|
||||
#ifdef CONFIG_WLAN_HAL_8192EE
|
||||
#define OFDM_TABLE_SIZE_92E 54
|
||||
#define CCK_TABLE_SIZE_92E 54
|
||||
extern u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E];
|
||||
extern u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8];
|
||||
extern u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8];
|
||||
#endif
|
||||
|
||||
#define OFDM_TABLE_SIZE_8812 43
|
||||
#define AVG_THERMAL_NUM_8812 4
|
||||
|
||||
#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
|
||||
extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
|
||||
#elif(ODM_IC_11AC_SERIES_SUPPORT)
|
||||
extern unsigned int ofdm_swing_table_8812[OFDM_TABLE_SIZE_8812];
|
||||
#endif
|
||||
|
||||
extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
|
||||
|
||||
#define dm_check_txpowertracking odm_txpowertracking_check
|
||||
|
||||
struct _IQK_MATRIX_REGS_SETTING {
|
||||
bool is_iqk_done;
|
||||
s32 value[1][iqk_matrix_reg_num];
|
||||
};
|
||||
|
||||
struct odm_rf_calibration_structure {
|
||||
/* for tx power tracking */
|
||||
|
||||
u32 rega24; /* for TempCCK */
|
||||
s32 rege94;
|
||||
s32 rege9c;
|
||||
s32 regeb4;
|
||||
s32 regebc;
|
||||
|
||||
/* u8 is_txpowertracking; */
|
||||
u8 tx_powercount;
|
||||
bool is_txpowertracking_init;
|
||||
bool is_txpowertracking;
|
||||
u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
|
||||
u8 tm_trigger;
|
||||
u8 internal_pa_5g[2]; /* pathA / pathB */
|
||||
|
||||
u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
|
||||
u8 thermal_value;
|
||||
u8 thermal_value_lck;
|
||||
u8 thermal_value_iqk;
|
||||
s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
|
||||
u8 thermal_value_dpk;
|
||||
u8 thermal_value_avg[AVG_THERMAL_NUM];
|
||||
u8 thermal_value_avg_index;
|
||||
u8 thermal_value_rx_gain;
|
||||
u8 thermal_value_crystal;
|
||||
u8 thermal_value_dpk_store;
|
||||
u8 thermal_value_dpk_track;
|
||||
bool txpowertracking_in_progress;
|
||||
bool is_dpk_enable;
|
||||
|
||||
bool is_reloadtxpowerindex;
|
||||
u8 is_rf_pi_enable;
|
||||
u32 txpowertracking_callback_cnt; /* cosa add for debug */
|
||||
|
||||
u8 is_cck_in_ch14;
|
||||
u8 CCK_index;
|
||||
u8 OFDM_index[MAX_RF_PATH];
|
||||
s8 power_index_offset;
|
||||
s8 delta_power_index;
|
||||
s8 delta_power_index_last;
|
||||
bool is_tx_power_changed;
|
||||
|
||||
u8 thermal_value_hp[HP_THERMAL_NUM];
|
||||
u8 thermal_value_hp_index;
|
||||
struct _IQK_MATRIX_REGS_SETTING iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
|
||||
u8 delta_lck;
|
||||
u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
|
||||
|
||||
u8 bb_swing_idx_ofdm[MAX_RF_PATH];
|
||||
u8 bb_swing_idx_ofdm_current;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
|
||||
#else
|
||||
u8 bb_swing_idx_ofdm_base;
|
||||
#endif
|
||||
bool bb_swing_flag_ofdm;
|
||||
u8 bb_swing_idx_cck;
|
||||
u8 bb_swing_idx_cck_current;
|
||||
u8 bb_swing_idx_cck_base;
|
||||
u8 default_ofdm_index;
|
||||
u8 default_cck_index;
|
||||
bool bb_swing_flag_cck;
|
||||
|
||||
s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
|
||||
s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
|
||||
s8 absolute_cck_swing_idx[MAX_RF_PATH];
|
||||
s8 remnant_cck_swing_idx;
|
||||
s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
|
||||
bool modify_tx_agc_flag_path_a;
|
||||
bool modify_tx_agc_flag_path_b;
|
||||
bool modify_tx_agc_flag_path_c;
|
||||
bool modify_tx_agc_flag_path_d;
|
||||
bool modify_tx_agc_flag_path_a_cck;
|
||||
|
||||
s8 kfree_offset[MAX_RF_PATH];
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
|
||||
/* for IQK */
|
||||
u32 regc04;
|
||||
u32 reg874;
|
||||
u32 regc08;
|
||||
u32 regb68;
|
||||
u32 regb6c;
|
||||
u32 reg870;
|
||||
u32 reg860;
|
||||
u32 reg864;
|
||||
|
||||
bool is_iqk_initialized;
|
||||
bool is_lck_in_progress;
|
||||
bool is_antenna_detected;
|
||||
bool is_need_iqk;
|
||||
bool is_iqk_in_progress;
|
||||
bool is_iqk_pa_off;
|
||||
u8 delta_iqk;
|
||||
u32 ADDA_backup[IQK_ADDA_REG_NUM];
|
||||
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
|
||||
u32 IQK_BB_backup_recover[9];
|
||||
u32 IQK_BB_backup[IQK_BB_REG_NUM];
|
||||
u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
|
||||
u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
|
||||
u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
|
||||
u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
|
||||
|
||||
u64 iqk_start_time;
|
||||
u64 iqk_total_progressing_time;
|
||||
u64 iqk_progressing_time;
|
||||
u32 lok_result;
|
||||
u8 iqk_step;
|
||||
u8 kcount;
|
||||
u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
|
||||
bool is_mp_mode;
|
||||
|
||||
/* for APK */
|
||||
u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
|
||||
u8 is_ap_kdone;
|
||||
u8 is_apk_thermal_meter_ignore;
|
||||
u8 is_dp_done;
|
||||
u8 is_dp_path_aok;
|
||||
u8 is_dp_path_bok;
|
||||
|
||||
/*Add by Yuchen for Kfree Phydm*/
|
||||
u8 reg_rf_kfree_enable; /*for registry*/
|
||||
u8 rf_kfree_enable; /*for efuse enable check*/
|
||||
u32 tx_lok[2];
|
||||
};
|
||||
|
||||
void
|
||||
odm_txpowertracking_check_ap(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_check(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
odm_txpowertracking_thermal_meter_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_check_mp(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
odm_txpowertracking_check_ce(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
|
||||
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter92c(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_callback_rx_gain_thermal_meter92d(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter92d(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_direct_call92c(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_thermal_meter_check(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
745
hal/phydm/phydm_powertracking_ce.c
Normal file
745
hal/phydm/phydm_powertracking_ce.c
Normal file
|
|
@ -0,0 +1,745 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*============================================================ */
|
||||
/* include files */
|
||||
/*============================================================ */
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
/* ************************************************************
|
||||
* Global var
|
||||
* ************************************************************ */
|
||||
|
||||
u32 ofdm_swing_table[OFDM_TABLE_SIZE] = {
|
||||
0x7f8001fe, /* 0, +6.0dB */
|
||||
0x788001e2, /* 1, +5.5dB */
|
||||
0x71c001c7, /* 2, +5.0dB*/
|
||||
0x6b8001ae, /* 3, +4.5dB*/
|
||||
0x65400195, /* 4, +4.0dB*/
|
||||
0x5fc0017f, /* 5, +3.5dB*/
|
||||
0x5a400169, /* 6, +3.0dB*/
|
||||
0x55400155, /* 7, +2.5dB*/
|
||||
0x50800142, /* 8, +2.0dB*/
|
||||
0x4c000130, /* 9, +1.5dB*/
|
||||
0x47c0011f, /* 10, +1.0dB*/
|
||||
0x43c0010f, /* 11, +0.5dB*/
|
||||
0x40000100, /* 12, +0dB*/
|
||||
0x3c8000f2, /* 13, -0.5dB*/
|
||||
0x390000e4, /* 14, -1.0dB*/
|
||||
0x35c000d7, /* 15, -1.5dB*/
|
||||
0x32c000cb, /* 16, -2.0dB*/
|
||||
0x300000c0, /* 17, -2.5dB*/
|
||||
0x2d4000b5, /* 18, -3.0dB*/
|
||||
0x2ac000ab, /* 19, -3.5dB*/
|
||||
0x288000a2, /* 20, -4.0dB*/
|
||||
0x26000098, /* 21, -4.5dB*/
|
||||
0x24000090, /* 22, -5.0dB*/
|
||||
0x22000088, /* 23, -5.5dB*/
|
||||
0x20000080, /* 24, -6.0dB*/
|
||||
0x1e400079, /* 25, -6.5dB*/
|
||||
0x1c800072, /* 26, -7.0dB*/
|
||||
0x1b00006c, /* 27. -7.5dB*/
|
||||
0x19800066, /* 28, -8.0dB*/
|
||||
0x18000060, /* 29, -8.5dB*/
|
||||
0x16c0005b, /* 30, -9.0dB*/
|
||||
0x15800056, /* 31, -9.5dB*/
|
||||
0x14400051, /* 32, -10.0dB*/
|
||||
0x1300004c, /* 33, -10.5dB*/
|
||||
0x12000048, /* 34, -11.0dB*/
|
||||
0x11000044, /* 35, -11.5dB*/
|
||||
0x10000040, /* 36, -12.0dB*/
|
||||
};
|
||||
|
||||
u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
|
||||
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
|
||||
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
|
||||
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB*/
|
||||
{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB*/
|
||||
{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
|
||||
{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB*/
|
||||
{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB*/
|
||||
{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB*/
|
||||
{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
|
||||
{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB*/
|
||||
{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
|
||||
{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB*/
|
||||
{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB <== default */
|
||||
{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB*/
|
||||
{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
|
||||
{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB*/
|
||||
{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
|
||||
{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB*/
|
||||
{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
|
||||
{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB*/
|
||||
{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB*/
|
||||
{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB*/
|
||||
{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB*/
|
||||
{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB*/
|
||||
{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB*/
|
||||
{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB*/
|
||||
{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB*/
|
||||
{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB*/
|
||||
{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB*/
|
||||
{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB*/
|
||||
{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB*/
|
||||
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB*/
|
||||
{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB*/
|
||||
};
|
||||
|
||||
|
||||
u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
|
||||
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
|
||||
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
|
||||
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
|
||||
{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB*/
|
||||
{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
|
||||
{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB*/
|
||||
{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
|
||||
{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
|
||||
{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
|
||||
{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB*/
|
||||
{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
|
||||
{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB*/
|
||||
{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB <== default*/
|
||||
{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
|
||||
{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
|
||||
{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB*/
|
||||
{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
|
||||
{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB*/
|
||||
{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
|
||||
{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB*/
|
||||
{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB*/
|
||||
{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB*/
|
||||
{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB*/
|
||||
{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB*/
|
||||
{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB*/
|
||||
{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB*/
|
||||
{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB*/
|
||||
{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB*/
|
||||
{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB*/
|
||||
{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB*/
|
||||
{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB*/
|
||||
{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB*/
|
||||
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB*/
|
||||
};
|
||||
|
||||
|
||||
u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
|
||||
0x0b40002d, /* 0, -15.0dB */
|
||||
0x0c000030, /* 1, -14.5dB*/
|
||||
0x0cc00033, /* 2, -14.0dB*/
|
||||
0x0d800036, /* 3, -13.5dB*/
|
||||
0x0e400039, /* 4, -13.0dB */
|
||||
0x0f00003c, /* 5, -12.5dB*/
|
||||
0x10000040, /* 6, -12.0dB*/
|
||||
0x11000044, /* 7, -11.5dB*/
|
||||
0x12000048, /* 8, -11.0dB*/
|
||||
0x1300004c, /* 9, -10.5dB*/
|
||||
0x14400051, /* 10, -10.0dB*/
|
||||
0x15800056, /* 11, -9.5dB*/
|
||||
0x16c0005b, /* 12, -9.0dB*/
|
||||
0x18000060, /* 13, -8.5dB*/
|
||||
0x19800066, /* 14, -8.0dB*/
|
||||
0x1b00006c, /* 15, -7.5dB*/
|
||||
0x1c800072, /* 16, -7.0dB*/
|
||||
0x1e400079, /* 17, -6.5dB*/
|
||||
0x20000080, /* 18, -6.0dB*/
|
||||
0x22000088, /* 19, -5.5dB*/
|
||||
0x24000090, /* 20, -5.0dB*/
|
||||
0x26000098, /* 21, -4.5dB*/
|
||||
0x288000a2, /* 22, -4.0dB*/
|
||||
0x2ac000ab, /* 23, -3.5dB*/
|
||||
0x2d4000b5, /* 24, -3.0dB*/
|
||||
0x300000c0, /* 25, -2.5dB*/
|
||||
0x32c000cb, /* 26, -2.0dB*/
|
||||
0x35c000d7, /* 27, -1.5dB*/
|
||||
0x390000e4, /* 28, -1.0dB*/
|
||||
0x3c8000f2, /* 29, -0.5dB*/
|
||||
0x40000100, /* 30, +0dB*/
|
||||
0x43c0010f, /* 31, +0.5dB*/
|
||||
0x47c0011f, /* 32, +1.0dB*/
|
||||
0x4c000130, /* 33, +1.5dB*/
|
||||
0x50800142, /* 34, +2.0dB*/
|
||||
0x55400155, /* 35, +2.5dB*/
|
||||
0x5a400169, /* 36, +3.0dB*/
|
||||
0x5fc0017f, /* 37, +3.5dB*/
|
||||
0x65400195, /* 38, +4.0dB*/
|
||||
0x6b8001ae, /* 39, +4.5dB*/
|
||||
0x71c001c7, /* 40, +5.0dB*/
|
||||
0x788001e2, /* 41, +5.5dB*/
|
||||
0x7f8001fe /* 42, +6.0dB*/
|
||||
};
|
||||
|
||||
|
||||
u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
|
||||
{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
|
||||
{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
|
||||
{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
|
||||
{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
|
||||
{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
|
||||
{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
|
||||
{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
|
||||
{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
|
||||
{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
|
||||
{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
|
||||
{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
|
||||
{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
|
||||
{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
|
||||
{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
|
||||
{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
|
||||
{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
|
||||
{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
|
||||
{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
|
||||
{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
|
||||
{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
|
||||
{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
|
||||
};
|
||||
|
||||
|
||||
u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
|
||||
{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
|
||||
{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
|
||||
{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
|
||||
{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
|
||||
{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
|
||||
{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
|
||||
{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
|
||||
{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
|
||||
{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
|
||||
{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
|
||||
{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
|
||||
{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
|
||||
{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
|
||||
{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
|
||||
{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
|
||||
{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
|
||||
{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
|
||||
{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
|
||||
{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
|
||||
{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
|
||||
{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
|
||||
};
|
||||
|
||||
|
||||
u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
|
||||
{0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
|
||||
{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
|
||||
{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
|
||||
{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
|
||||
{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
|
||||
{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
|
||||
{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
|
||||
{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
|
||||
{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
|
||||
{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
|
||||
{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
|
||||
{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
|
||||
{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
|
||||
{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
|
||||
{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
|
||||
{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
|
||||
{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
|
||||
{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
|
||||
{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
|
||||
{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
|
||||
{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
|
||||
};
|
||||
|
||||
|
||||
u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
|
||||
{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB*/
|
||||
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB*/
|
||||
{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB*/
|
||||
{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB*/
|
||||
{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB*/
|
||||
{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB*/
|
||||
{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB*/
|
||||
{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB*/
|
||||
{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB*/
|
||||
{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB*/
|
||||
{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB*/
|
||||
{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB*/
|
||||
{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB*/
|
||||
{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB*/
|
||||
{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */
|
||||
{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB*/
|
||||
{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
|
||||
{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB*/
|
||||
{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */
|
||||
{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB*/
|
||||
{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*20, -6.0dB */
|
||||
{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB*/
|
||||
{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */
|
||||
{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB*/
|
||||
{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */
|
||||
{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB*/
|
||||
{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB*/
|
||||
{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB*/
|
||||
{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */
|
||||
{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB*/
|
||||
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB*/
|
||||
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB*/
|
||||
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB*/
|
||||
};
|
||||
|
||||
|
||||
u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
|
||||
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB*/
|
||||
{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB*/
|
||||
{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB*/
|
||||
{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB*/
|
||||
{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB*/
|
||||
{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*5, -13.5dB*/
|
||||
{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB*/
|
||||
{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB*/
|
||||
{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB*/
|
||||
{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB*/
|
||||
{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB*/
|
||||
{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*11, -10.5dB*/
|
||||
{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB*/
|
||||
{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB*/
|
||||
{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*14, -9.0dB */
|
||||
{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB*/
|
||||
{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
|
||||
{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB*/
|
||||
{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */
|
||||
{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */
|
||||
{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */
|
||||
{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB*/
|
||||
{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */
|
||||
{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*23, -4.5dB*/
|
||||
{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */
|
||||
{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */
|
||||
{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */
|
||||
{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*27, -2.5dB*/
|
||||
{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */
|
||||
{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*29, -1.5dB*/
|
||||
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */
|
||||
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */
|
||||
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */
|
||||
};
|
||||
u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
|
||||
0x0CD, /*0 , -20dB*/
|
||||
0x0D9,
|
||||
0x0E6,
|
||||
0x0F3,
|
||||
0x102,
|
||||
0x111,
|
||||
0x121,
|
||||
0x132,
|
||||
0x144,
|
||||
0x158,
|
||||
0x16C,
|
||||
0x182,
|
||||
0x198,
|
||||
0x1B1,
|
||||
0x1CA,
|
||||
0x1E5,
|
||||
0x202,
|
||||
0x221,
|
||||
0x241,
|
||||
0x263,
|
||||
0x287,
|
||||
0x2AE,
|
||||
0x2D6,
|
||||
0x301,
|
||||
0x32F,
|
||||
0x35F,
|
||||
0x392,
|
||||
0x3C9,
|
||||
0x402,
|
||||
0x43F,
|
||||
0x47F,
|
||||
0x4C3,
|
||||
0x50C,
|
||||
0x558,
|
||||
0x5A9,
|
||||
0x5FF,
|
||||
0x65A,
|
||||
0x6BA,
|
||||
0x720,
|
||||
0x78C,
|
||||
0x7FF,
|
||||
};
|
||||
|
||||
|
||||
u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
|
||||
0x081, /* 0, -12.0dB*/
|
||||
0x088, /* 1, -11.5dB*/
|
||||
0x090, /* 2, -11.0dB*/
|
||||
0x099, /* 3, -10.5dB*/
|
||||
0x0A2, /* 4, -10.0dB*/
|
||||
0x0AC, /* 5, -9.5dB*/
|
||||
0x0B6, /* 6, -9.0dB*/
|
||||
0x0C0, /*7, -8.5dB*/
|
||||
0x0CC, /* 8, -8.0dB*/
|
||||
0x0D8, /* 9, -7.5dB*/
|
||||
0x0E5, /* 10, -7.0dB*/
|
||||
0x0F2, /* 11, -6.5dB*/
|
||||
0x101, /* 12, -6.0dB*/
|
||||
0x110, /* 13, -5.5dB*/
|
||||
0x120, /* 14, -5.0dB*/
|
||||
0x131, /* 15, -4.5dB*/
|
||||
0x143, /* 16, -4.0dB*/
|
||||
0x156, /* 17, -3.5dB*/
|
||||
0x16A, /* 18, -3.0dB*/
|
||||
0x180, /* 19, -2.5dB*/
|
||||
0x197, /* 20, -2.0dB*/
|
||||
0x1AF, /* 21, -1.5dB*/
|
||||
0x1C8, /* 22, -1.0dB*/
|
||||
0x1E3, /* 23, -0.5dB*/
|
||||
0x200, /* 24, +0 dB*/
|
||||
0x21E, /* 25, +0.5dB*/
|
||||
0x23E, /* 26, +1.0dB*/
|
||||
0x261, /* 27, +1.5dB*/
|
||||
0x285,/* 28, +2.0dB*/
|
||||
0x2AB, /* 29, +2.5dB*/
|
||||
0x2D3, /*30, +3.0dB*/
|
||||
0x2FE, /* 31, +3.5dB*/
|
||||
0x32B, /* 32, +4.0dB*/
|
||||
0x35C, /* 33, +4.5dB*/
|
||||
0x38E, /* 34, +5.0dB*/
|
||||
0x3C4, /* 35, +5.5dB*/
|
||||
0x3FE /* 36, +6.0dB */
|
||||
};
|
||||
|
||||
#ifdef AP_BUILD_WORKAROUND
|
||||
|
||||
unsigned int tx_pwr_trk_ofdm_swing_tbl[tx_pwr_trk_ofdm_swing_tbl_len] = {
|
||||
/* +6.0dB */ 0x7f8001fe,
|
||||
/* +5.5dB */ 0x788001e2,
|
||||
/* +5.0dB */ 0x71c001c7,
|
||||
/* +4.5dB */ 0x6b8001ae,
|
||||
/* +4.0dB */ 0x65400195,
|
||||
/* +3.5dB */ 0x5fc0017f,
|
||||
/* +3.0dB */ 0x5a400169,
|
||||
/* +2.5dB */ 0x55400155,
|
||||
/* +2.0dB */ 0x50800142,
|
||||
/* +1.5dB */ 0x4c000130,
|
||||
/* +1.0dB */ 0x47c0011f,
|
||||
/* +0.5dB */ 0x43c0010f,
|
||||
/* 0.0dB */ 0x40000100,
|
||||
/* -0.5dB */ 0x3c8000f2,
|
||||
/* -1.0dB */ 0x390000e4,
|
||||
/* -1.5dB */ 0x35c000d7,
|
||||
/* -2.0dB */ 0x32c000cb,
|
||||
/* -2.5dB */ 0x300000c0,
|
||||
/* -3.0dB */ 0x2d4000b5,
|
||||
/* -3.5dB */ 0x2ac000ab,
|
||||
/* -4.0dB */ 0x288000a2,
|
||||
/* -4.5dB */ 0x26000098,
|
||||
/* -5.0dB */ 0x24000090,
|
||||
/* -5.5dB */ 0x22000088,
|
||||
/* -6.0dB */ 0x20000080,
|
||||
/* -6.5dB */ 0x1a00006c,
|
||||
/* -7.0dB */ 0x1c800072,
|
||||
/* -7.5dB */ 0x18000060,
|
||||
/* -8.0dB */ 0x19800066,
|
||||
/* -8.5dB */ 0x15800056,
|
||||
/* -9.0dB */ 0x26c0005b,
|
||||
/* -9.5dB */ 0x14400051,
|
||||
/* -10.0dB */ 0x24400051,
|
||||
/* -10.5dB */ 0x1300004c,
|
||||
/* -11.0dB */ 0x12000048,
|
||||
/* -11.5dB */ 0x11000044,
|
||||
/* -12.0dB */ 0x10000040
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
void
|
||||
odm_txpowertracking_init(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
if (!(p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_IC_11N_SERIES | ODM_RTL8822B)))
|
||||
return;
|
||||
#endif
|
||||
|
||||
odm_txpowertracking_thermal_meter_init(p_dm_odm);
|
||||
}
|
||||
|
||||
u8
|
||||
get_swing_index(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
u8 i = 0;
|
||||
u32 bb_swing;
|
||||
u32 swing_table_size;
|
||||
u32 *p_swing_table;
|
||||
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B
|
||||
|| p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8703B
|
||||
) {
|
||||
bb_swing = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000);
|
||||
|
||||
p_swing_table = ofdm_swing_table_new;
|
||||
swing_table_size = OFDM_TABLE_SIZE;
|
||||
} else {
|
||||
#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8821) {
|
||||
bb_swing = phy_get_tx_bb_swing_8812a(adapter, p_hal_data->current_band_type, ODM_RF_PATH_A);
|
||||
p_swing_table = tx_scaling_table_jaguar;
|
||||
swing_table_size = TXSCALE_TABLE_SIZE;
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
bb_swing = 0;
|
||||
p_swing_table = ofdm_swing_table;
|
||||
swing_table_size = OFDM_TABLE_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < swing_table_size; ++i) {
|
||||
u32 table_value = p_swing_table[i];
|
||||
|
||||
if (table_value >= 0x100000)
|
||||
table_value >>= 22;
|
||||
if (bb_swing == table_value)
|
||||
break;
|
||||
}
|
||||
return i;
|
||||
}
|
||||
|
||||
void
|
||||
odm_txpowertracking_thermal_meter_init(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u8 default_swing_index = get_swing_index(p_dm_odm);
|
||||
u8 p = 0;
|
||||
struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
|
||||
if (p_dm_odm->mp_mode == false)
|
||||
p_hal_data->txpowertrack_control = true;
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
|
||||
p_rf_calibrate_info->is_txpowertracking = _TRUE;
|
||||
p_rf_calibrate_info->tx_powercount = 0;
|
||||
p_rf_calibrate_info->is_txpowertracking_init = _FALSE;
|
||||
|
||||
if (p_dm_odm->mp_mode == false)
|
||||
p_rf_calibrate_info->txpowertrack_control = _TRUE;
|
||||
else
|
||||
p_rf_calibrate_info->txpowertrack_control = _FALSE;
|
||||
|
||||
if (p_dm_odm->mp_mode == false)
|
||||
p_rf_calibrate_info->txpowertrack_control = _TRUE;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("p_dm_odm txpowertrack_control = %d\n", p_rf_calibrate_info->txpowertrack_control));
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
#ifdef RTL8188E_SUPPORT
|
||||
{
|
||||
p_rf_calibrate_info->is_txpowertracking = _TRUE;
|
||||
p_rf_calibrate_info->tx_powercount = 0;
|
||||
p_rf_calibrate_info->is_txpowertracking_init = _FALSE;
|
||||
p_rf_calibrate_info->txpowertrack_control = _TRUE;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* p_dm_odm->rf_calibrate_info.txpowertrack_control = true; */
|
||||
p_rf_calibrate_info->thermal_value = p_hal_data->eeprom_thermal_meter;
|
||||
p_rf_calibrate_info->thermal_value_iqk = p_hal_data->eeprom_thermal_meter;
|
||||
p_rf_calibrate_info->thermal_value_lck = p_hal_data->eeprom_thermal_meter;
|
||||
|
||||
if (p_rf_calibrate_info->default_bb_swing_index_flag != true) {
|
||||
/*The index of "0 dB" in SwingTable.*/
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8703B) {
|
||||
p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index;
|
||||
p_rf_calibrate_info->default_cck_index = 20;
|
||||
} else if (p_dm_odm->support_ic_type == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/
|
||||
p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/
|
||||
p_rf_calibrate_info->default_cck_index = 20; /*CCK:-6dB*/
|
||||
} else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/
|
||||
p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/
|
||||
p_rf_calibrate_info->default_cck_index = 28; /*CCK: -6dB*/
|
||||
} else {
|
||||
p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index;
|
||||
p_rf_calibrate_info->default_cck_index = 24;
|
||||
}
|
||||
p_rf_calibrate_info->default_bb_swing_index_flag = true;
|
||||
}
|
||||
|
||||
p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index;
|
||||
p_rf_calibrate_info->CCK_index = p_rf_calibrate_info->default_cck_index;
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) {
|
||||
p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->default_ofdm_index;
|
||||
p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index;
|
||||
p_rf_calibrate_info->delta_power_index[p] = 0;
|
||||
p_rf_calibrate_info->delta_power_index_last[p] = 0;
|
||||
p_rf_calibrate_info->power_index_offset[p] = 0;
|
||||
}
|
||||
p_rf_calibrate_info->modify_tx_agc_value_ofdm = 0;
|
||||
p_rf_calibrate_info->modify_tx_agc_value_cck = 0;
|
||||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_txpowertracking_check(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
|
||||
at the same time. In the stage2/3, we need to prive universal interface and merge all
|
||||
HW dynamic mechanism. */
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
switch (p_dm_odm->support_platform) {
|
||||
case ODM_WIN:
|
||||
odm_txpowertracking_check_mp(p_dm_odm);
|
||||
break;
|
||||
|
||||
case ODM_CE:
|
||||
odm_txpowertracking_check_ce(p_dm_odm);
|
||||
break;
|
||||
|
||||
case ODM_AP:
|
||||
odm_txpowertracking_check_ap(p_dm_odm);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
odm_txpowertracking_check_ce(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
|
||||
if (!(p_dm_odm->support_ability & ODM_RF_TX_PWR_TRACK))
|
||||
return;
|
||||
|
||||
if (!p_dm_odm->rf_calibrate_info.tm_trigger) {
|
||||
|
||||
if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8192E(adapter)
|
||||
|| IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8814A(adapter)
|
||||
|| IS_HARDWARE_TYPE_8703B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8822B(adapter)
|
||||
|| IS_HARDWARE_TYPE_8821C(adapter)
|
||||
)
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_T_METER_NEW, (BIT(17) | BIT(16)), 0x03);
|
||||
else
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_T_METER_OLD, RFREGOFFSETMASK, 0x60);
|
||||
|
||||
|
||||
|
||||
p_dm_odm->rf_calibrate_info.tm_trigger = 1;
|
||||
return;
|
||||
} else {
|
||||
|
||||
odm_txpowertracking_callback_thermal_meter(adapter);
|
||||
p_dm_odm->rf_calibrate_info.tm_trigger = 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
odm_txpowertracking_check_mp(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
|
||||
if (odm_check_power_status(adapter) == false) {
|
||||
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===>odm_check_power_status() return false\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
odm_txpowertracking_thermal_meter_check(adapter);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_txpowertracking_check_ap(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
struct rtl8192cd_priv *priv = p_dm_odm->priv;
|
||||
|
||||
return;
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void
|
||||
odm_txpowertracking_thermal_meter_check(
|
||||
struct _ADAPTER *adapter
|
||||
)
|
||||
{
|
||||
#ifndef AP_BUILD_WORKAROUND
|
||||
static u8 tm_trigger = 0;
|
||||
|
||||
if (!(GET_HAL_DATA(adapter)->DM_OutSrc.support_ability & ODM_RF_TX_PWR_TRACK)) {
|
||||
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
|
||||
("===>odm_txpowertracking_thermal_meter_check(),p_mgnt_info->is_txpowertracking is false, return!!\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
if (!tm_trigger) {
|
||||
if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8192E(adapter) ||
|
||||
IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8814A(adapter) || IS_HARDWARE_TYPE_8188F(adapter)
|
||||
|| IS_HARDWARE_TYPE_8703B(adapter) || IS_HARDWARE_TYPE_8723D(adapter))
|
||||
phy_set_rf_reg(adapter, ODM_RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);
|
||||
else
|
||||
phy_set_rf_reg(adapter, ODM_RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
|
||||
|
||||
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Trigger Thermal Meter!!\n"));
|
||||
|
||||
tm_trigger = 1;
|
||||
return;
|
||||
} else {
|
||||
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Schedule TxPowerTracking direct call!!\n"));
|
||||
odm_txpowertracking_direct_call(adapter);
|
||||
tm_trigger = 0;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
334
hal/phydm/phydm_powertracking_ce.h
Normal file
334
hal/phydm/phydm_powertracking_ce.h
Normal file
|
|
@ -0,0 +1,334 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMPOWERTRACKING_H__
|
||||
#define __PHYDMPOWERTRACKING_H__
|
||||
|
||||
#define POWRTRACKING_VERSION "1.1"
|
||||
|
||||
#define DPK_DELTA_MAPPING_NUM 13
|
||||
#define index_mapping_HP_NUM 15
|
||||
#define OFDM_TABLE_SIZE 43
|
||||
#define CCK_TABLE_SIZE 33
|
||||
#define CCK_TABLE_SIZE_88F 21
|
||||
#define TXSCALE_TABLE_SIZE 37
|
||||
#define CCK_TABLE_SIZE_8723D 41
|
||||
|
||||
#define TXPWR_TRACK_TABLE_SIZE 30
|
||||
#define DELTA_SWINGIDX_SIZE 30
|
||||
#define DELTA_SWINTSSI_SIZE 61
|
||||
#define BAND_NUM 4
|
||||
|
||||
#define AVG_THERMAL_NUM 8
|
||||
#define HP_THERMAL_NUM 8
|
||||
#define IQK_MAC_REG_NUM 4
|
||||
#define IQK_ADDA_REG_NUM 16
|
||||
#define IQK_BB_REG_NUM_MAX 10
|
||||
|
||||
#define IQK_BB_REG_NUM 9
|
||||
|
||||
|
||||
|
||||
#define iqk_matrix_reg_num 8
|
||||
#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
|
||||
|
||||
extern u32 ofdm_swing_table[OFDM_TABLE_SIZE];
|
||||
extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
|
||||
extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
|
||||
|
||||
extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
|
||||
extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
|
||||
extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
|
||||
extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
|
||||
extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
|
||||
extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
|
||||
extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
|
||||
|
||||
extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
|
||||
|
||||
/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
|
||||
static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
|
||||
static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
|
||||
|
||||
#define dm_check_txpowertracking odm_txpowertracking_check
|
||||
|
||||
struct _IQK_MATRIX_REGS_SETTING {
|
||||
bool is_iqk_done;
|
||||
s32 value[3][iqk_matrix_reg_num];
|
||||
bool is_bw_iqk_result_saved[3];
|
||||
};
|
||||
|
||||
struct odm_rf_calibration_structure {
|
||||
/* for tx power tracking */
|
||||
|
||||
u32 rega24; /* for TempCCK */
|
||||
s32 rege94;
|
||||
s32 rege9c;
|
||||
s32 regeb4;
|
||||
s32 regebc;
|
||||
|
||||
u8 tx_powercount;
|
||||
bool is_txpowertracking_init;
|
||||
bool is_txpowertracking;
|
||||
u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
|
||||
u8 tm_trigger;
|
||||
u8 internal_pa_5g[2]; /* pathA / pathB */
|
||||
|
||||
u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
|
||||
u8 thermal_value;
|
||||
u8 thermal_value_lck;
|
||||
u8 thermal_value_iqk;
|
||||
s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
|
||||
u8 thermal_value_dpk;
|
||||
u8 thermal_value_avg[AVG_THERMAL_NUM];
|
||||
u8 thermal_value_avg_index;
|
||||
u8 thermal_value_rx_gain;
|
||||
u8 thermal_value_crystal;
|
||||
u8 thermal_value_dpk_store;
|
||||
u8 thermal_value_dpk_track;
|
||||
bool txpowertracking_in_progress;
|
||||
|
||||
bool is_reloadtxpowerindex;
|
||||
u8 is_rf_pi_enable;
|
||||
u32 txpowertracking_callback_cnt; /* cosa add for debug */
|
||||
|
||||
|
||||
/* ------------------------- Tx power Tracking ------------------------- */
|
||||
u8 is_cck_in_ch14;
|
||||
u8 CCK_index;
|
||||
u8 OFDM_index[MAX_RF_PATH];
|
||||
s8 power_index_offset[MAX_RF_PATH];
|
||||
s8 delta_power_index[MAX_RF_PATH];
|
||||
s8 delta_power_index_last[MAX_RF_PATH];
|
||||
bool is_tx_power_changed;
|
||||
s8 xtal_offset;
|
||||
s8 xtal_offset_last;
|
||||
|
||||
u8 thermal_value_hp[HP_THERMAL_NUM];
|
||||
u8 thermal_value_hp_index;
|
||||
struct _IQK_MATRIX_REGS_SETTING iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
|
||||
u8 delta_lck;
|
||||
s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
|
||||
u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
|
||||
s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
|
||||
|
||||
u8 bb_swing_idx_ofdm[MAX_RF_PATH];
|
||||
u8 bb_swing_idx_ofdm_current;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
|
||||
#else
|
||||
u8 bb_swing_idx_ofdm_base;
|
||||
#endif
|
||||
bool default_bb_swing_index_flag;
|
||||
bool bb_swing_flag_ofdm;
|
||||
u8 bb_swing_idx_cck;
|
||||
u8 bb_swing_idx_cck_current;
|
||||
u8 bb_swing_idx_cck_base;
|
||||
u8 default_ofdm_index;
|
||||
u8 default_cck_index;
|
||||
bool bb_swing_flag_cck;
|
||||
|
||||
s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
|
||||
s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
|
||||
s8 absolute_cck_swing_idx[MAX_RF_PATH];
|
||||
s8 remnant_cck_swing_idx;
|
||||
s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
|
||||
bool modify_tx_agc_flag_path_a;
|
||||
bool modify_tx_agc_flag_path_b;
|
||||
bool modify_tx_agc_flag_path_c;
|
||||
bool modify_tx_agc_flag_path_d;
|
||||
bool modify_tx_agc_flag_path_a_cck;
|
||||
|
||||
s8 kfree_offset[MAX_RF_PATH];
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
|
||||
/* for IQK */
|
||||
u32 regc04;
|
||||
u32 reg874;
|
||||
u32 regc08;
|
||||
u32 regb68;
|
||||
u32 regb6c;
|
||||
u32 reg870;
|
||||
u32 reg860;
|
||||
u32 reg864;
|
||||
|
||||
bool is_iqk_initialized;
|
||||
bool is_lck_in_progress;
|
||||
bool is_antenna_detected;
|
||||
bool is_need_iqk;
|
||||
bool is_iqk_in_progress;
|
||||
bool is_iqk_pa_off;
|
||||
u8 delta_iqk;
|
||||
u32 ADDA_backup[IQK_ADDA_REG_NUM];
|
||||
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
|
||||
u32 IQK_BB_backup_recover[9];
|
||||
u32 IQK_BB_backup[IQK_BB_REG_NUM];
|
||||
u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
|
||||
u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
|
||||
u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
|
||||
u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
|
||||
u32 tx_iqc_8723d[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
|
||||
u32 rx_iqc_8723d[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
|
||||
|
||||
u8 iqk_step;
|
||||
u8 kcount;
|
||||
u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
|
||||
bool is_mp_mode;
|
||||
|
||||
|
||||
|
||||
/* <James> IQK time measurement */
|
||||
u64 iqk_start_time;
|
||||
u64 iqk_progressing_time;
|
||||
u64 iqk_total_progressing_time;
|
||||
|
||||
u32 lok_result;
|
||||
|
||||
/* for APK */
|
||||
u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
|
||||
u8 is_ap_kdone;
|
||||
u8 is_apk_thermal_meter_ignore;
|
||||
|
||||
/* DPK */
|
||||
bool is_dpk_fail;
|
||||
u8 is_dp_done;
|
||||
u8 is_dp_path_aok;
|
||||
u8 is_dp_path_bok;
|
||||
|
||||
u32 tx_lok[2];
|
||||
u32 dpk_tx_agc;
|
||||
s32 dpk_gain;
|
||||
u32 dpk_thermal[4];
|
||||
s8 modify_tx_agc_value_ofdm;
|
||||
s8 modify_tx_agc_value_cck;
|
||||
|
||||
/*Add by Yuchen for Kfree Phydm*/
|
||||
u8 reg_rf_kfree_enable; /*for registry*/
|
||||
u8 rf_kfree_enable; /*for efuse enable check*/
|
||||
|
||||
};
|
||||
|
||||
|
||||
void
|
||||
odm_txpowertracking_check(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
odm_txpowertracking_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_check_ap(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_thermal_meter_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_check_mp(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
odm_txpowertracking_check_ce(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
|
||||
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter92c(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_callback_rx_gain_thermal_meter92d(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter92d(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_direct_call92c(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_thermal_meter_check(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
776
hal/phydm/phydm_powertracking_win.c
Normal file
776
hal/phydm/phydm_powertracking_win.c
Normal file
|
|
@ -0,0 +1,776 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* ************************************************************
|
||||
* include files
|
||||
* ************************************************************ */
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
/* ************************************************************
|
||||
* Global var
|
||||
* ************************************************************ */
|
||||
|
||||
u32 ofdm_swing_table[OFDM_TABLE_SIZE] = {
|
||||
0x7f8001fe, /* 0, +6.0dB */
|
||||
0x788001e2, /* 1, +5.5dB */
|
||||
0x71c001c7, /* 2, +5.0dB */
|
||||
0x6b8001ae, /* 3, +4.5dB */
|
||||
0x65400195, /* 4, +4.0dB */
|
||||
0x5fc0017f, /* 5, +3.5dB */
|
||||
0x5a400169, /* 6, +3.0dB */
|
||||
0x55400155, /* 7, +2.5dB */
|
||||
0x50800142, /* 8, +2.0dB */
|
||||
0x4c000130, /* 9, +1.5dB */
|
||||
0x47c0011f, /* 10, +1.0dB */
|
||||
0x43c0010f, /* 11, +0.5dB */
|
||||
0x40000100, /* 12, +0dB */
|
||||
0x3c8000f2, /* 13, -0.5dB */
|
||||
0x390000e4, /* 14, -1.0dB */
|
||||
0x35c000d7, /* 15, -1.5dB */
|
||||
0x32c000cb, /* 16, -2.0dB */
|
||||
0x300000c0, /* 17, -2.5dB */
|
||||
0x2d4000b5, /* 18, -3.0dB */
|
||||
0x2ac000ab, /* 19, -3.5dB */
|
||||
0x288000a2, /* 20, -4.0dB */
|
||||
0x26000098, /* 21, -4.5dB */
|
||||
0x24000090, /* 22, -5.0dB */
|
||||
0x22000088, /* 23, -5.5dB */
|
||||
0x20000080, /* 24, -6.0dB */
|
||||
0x1e400079, /* 25, -6.5dB */
|
||||
0x1c800072, /* 26, -7.0dB */
|
||||
0x1b00006c, /* 27. -7.5dB */
|
||||
0x19800066, /* 28, -8.0dB */
|
||||
0x18000060, /* 29, -8.5dB */
|
||||
0x16c0005b, /* 30, -9.0dB */
|
||||
0x15800056, /* 31, -9.5dB */
|
||||
0x14400051, /* 32, -10.0dB */
|
||||
0x1300004c, /* 33, -10.5dB */
|
||||
0x12000048, /* 34, -11.0dB */
|
||||
0x11000044, /* 35, -11.5dB */
|
||||
0x10000040, /* 36, -12.0dB */
|
||||
};
|
||||
|
||||
u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
|
||||
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
|
||||
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
|
||||
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
|
||||
{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
|
||||
{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
|
||||
{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
|
||||
{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
|
||||
{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
|
||||
{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
|
||||
{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
|
||||
{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
|
||||
{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
|
||||
{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB <== default */
|
||||
{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
|
||||
{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
|
||||
{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
|
||||
{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
|
||||
{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
|
||||
{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
|
||||
{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
|
||||
{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */
|
||||
{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */
|
||||
{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */
|
||||
{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */
|
||||
{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */
|
||||
{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */
|
||||
{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */
|
||||
{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */
|
||||
{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */
|
||||
{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */
|
||||
{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */
|
||||
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */
|
||||
{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */
|
||||
};
|
||||
|
||||
|
||||
u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
|
||||
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
|
||||
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
|
||||
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
|
||||
{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
|
||||
{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
|
||||
{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
|
||||
{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
|
||||
{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
|
||||
{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
|
||||
{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
|
||||
{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
|
||||
{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
|
||||
{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB <== default */
|
||||
{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
|
||||
{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
|
||||
{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
|
||||
{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
|
||||
{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
|
||||
{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
|
||||
{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
|
||||
{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */
|
||||
{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */
|
||||
{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */
|
||||
{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */
|
||||
{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */
|
||||
{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */
|
||||
{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */
|
||||
{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */
|
||||
{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */
|
||||
{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */
|
||||
{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */
|
||||
{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */
|
||||
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */
|
||||
};
|
||||
|
||||
|
||||
u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
|
||||
0x0b40002d, /* 0, -15.0dB */
|
||||
0x0c000030, /* 1, -14.5dB */
|
||||
0x0cc00033, /* 2, -14.0dB */
|
||||
0x0d800036, /* 3, -13.5dB */
|
||||
0x0e400039, /* 4, -13.0dB */
|
||||
0x0f00003c, /* 5, -12.5dB */
|
||||
0x10000040, /* 6, -12.0dB */
|
||||
0x11000044, /* 7, -11.5dB */
|
||||
0x12000048, /* 8, -11.0dB */
|
||||
0x1300004c, /* 9, -10.5dB */
|
||||
0x14400051, /* 10, -10.0dB */
|
||||
0x15800056, /* 11, -9.5dB */
|
||||
0x16c0005b, /* 12, -9.0dB */
|
||||
0x18000060, /* 13, -8.5dB */
|
||||
0x19800066, /* 14, -8.0dB */
|
||||
0x1b00006c, /* 15, -7.5dB */
|
||||
0x1c800072, /* 16, -7.0dB */
|
||||
0x1e400079, /* 17, -6.5dB */
|
||||
0x20000080, /* 18, -6.0dB */
|
||||
0x22000088, /* 19, -5.5dB */
|
||||
0x24000090, /* 20, -5.0dB */
|
||||
0x26000098, /* 21, -4.5dB */
|
||||
0x288000a2, /* 22, -4.0dB */
|
||||
0x2ac000ab, /* 23, -3.5dB */
|
||||
0x2d4000b5, /* 24, -3.0dB */
|
||||
0x300000c0, /* 25, -2.5dB */
|
||||
0x32c000cb, /* 26, -2.0dB */
|
||||
0x35c000d7, /* 27, -1.5dB */
|
||||
0x390000e4, /* 28, -1.0dB */
|
||||
0x3c8000f2, /* 29, -0.5dB */
|
||||
0x40000100, /* 30, +0dB */
|
||||
0x43c0010f, /* 31, +0.5dB */
|
||||
0x47c0011f, /* 32, +1.0dB */
|
||||
0x4c000130, /* 33, +1.5dB */
|
||||
0x50800142, /* 34, +2.0dB */
|
||||
0x55400155, /* 35, +2.5dB */
|
||||
0x5a400169, /* 36, +3.0dB */
|
||||
0x5fc0017f, /* 37, +3.5dB */
|
||||
0x65400195, /* 38, +4.0dB */
|
||||
0x6b8001ae, /* 39, +4.5dB */
|
||||
0x71c001c7, /* 40, +5.0dB */
|
||||
0x788001e2, /* 41, +5.5dB */
|
||||
0x7f8001fe /* 42, +6.0dB */
|
||||
};
|
||||
|
||||
|
||||
u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
|
||||
{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
|
||||
{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
|
||||
{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
|
||||
{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
|
||||
{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
|
||||
{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
|
||||
{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
|
||||
{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
|
||||
{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
|
||||
{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
|
||||
{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
|
||||
{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
|
||||
{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
|
||||
{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
|
||||
{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
|
||||
{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
|
||||
{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
|
||||
{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
|
||||
{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
|
||||
{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
|
||||
{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
|
||||
};
|
||||
|
||||
|
||||
u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
|
||||
{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
|
||||
{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
|
||||
{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
|
||||
{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
|
||||
{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
|
||||
{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
|
||||
{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
|
||||
{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
|
||||
{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
|
||||
{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
|
||||
{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
|
||||
{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
|
||||
{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
|
||||
{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
|
||||
{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
|
||||
{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
|
||||
{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
|
||||
{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
|
||||
{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
|
||||
{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
|
||||
{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
|
||||
};
|
||||
|
||||
|
||||
u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
|
||||
{0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
|
||||
{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
|
||||
{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
|
||||
{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
|
||||
{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
|
||||
{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
|
||||
{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
|
||||
{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
|
||||
{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
|
||||
{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
|
||||
{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
|
||||
{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
|
||||
{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
|
||||
{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
|
||||
{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
|
||||
{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
|
||||
{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
|
||||
{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
|
||||
{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
|
||||
{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
|
||||
{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
|
||||
{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB */
|
||||
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB */
|
||||
{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB */
|
||||
{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB */
|
||||
{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB */
|
||||
{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB */
|
||||
{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB */
|
||||
{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB */
|
||||
{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB */
|
||||
{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB */
|
||||
{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB */
|
||||
{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB */
|
||||
{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB */
|
||||
{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB */
|
||||
{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */
|
||||
{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB */
|
||||
{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
|
||||
{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB */
|
||||
{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */
|
||||
{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB */
|
||||
{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 20, -6.0dB */
|
||||
{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB */
|
||||
{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */
|
||||
{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB */
|
||||
{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */
|
||||
{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB */
|
||||
{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB */
|
||||
{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB */
|
||||
{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */
|
||||
{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB */
|
||||
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB */
|
||||
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB */
|
||||
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB */
|
||||
};
|
||||
|
||||
|
||||
u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
|
||||
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB */
|
||||
{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB */
|
||||
{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB */
|
||||
{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB */
|
||||
{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB */
|
||||
{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 5, -13.5dB */
|
||||
{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB */
|
||||
{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB */
|
||||
{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB */
|
||||
{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB */
|
||||
{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB */
|
||||
{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 11, -10.5dB */
|
||||
{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB */
|
||||
{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB */
|
||||
{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 14, -9.0dB */
|
||||
{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB */
|
||||
{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
|
||||
{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB */
|
||||
{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */
|
||||
{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */
|
||||
{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */
|
||||
{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB */
|
||||
{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */
|
||||
{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 23, -4.5dB */
|
||||
{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */
|
||||
{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */
|
||||
{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */
|
||||
{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 27, -2.5dB */
|
||||
{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */
|
||||
{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 29, -1.5dB */
|
||||
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */
|
||||
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */
|
||||
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */
|
||||
};
|
||||
u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
|
||||
0x0CD,
|
||||
0x0D9,
|
||||
0x0E6,
|
||||
0x0F3,
|
||||
0x102,
|
||||
0x111,
|
||||
0x121,
|
||||
0x132,
|
||||
0x144,
|
||||
0x158,
|
||||
0x16C,
|
||||
0x182,
|
||||
0x198,
|
||||
0x1B1,
|
||||
0x1CA,
|
||||
0x1E5,
|
||||
0x202,
|
||||
0x221,
|
||||
0x241,
|
||||
0x263,
|
||||
0x287,
|
||||
0x2AE,
|
||||
0x2D6,
|
||||
0x301,
|
||||
0x32F,
|
||||
0x35F,
|
||||
0x392,
|
||||
0x3C9,
|
||||
0x402,
|
||||
0x43F,
|
||||
0x47F,
|
||||
0x4C3,
|
||||
0x50C,
|
||||
0x558,
|
||||
0x5A9,
|
||||
0x5FF,
|
||||
0x65A,
|
||||
0x6BA,
|
||||
0x720,
|
||||
0x78C,
|
||||
0x7FF,
|
||||
};
|
||||
|
||||
|
||||
u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
|
||||
0x081, /* 0, -12.0dB */
|
||||
0x088, /* 1, -11.5dB */
|
||||
0x090, /* 2, -11.0dB */
|
||||
0x099, /* 3, -10.5dB */
|
||||
0x0A2, /* 4, -10.0dB */
|
||||
0x0AC, /* 5, -9.5dB */
|
||||
0x0B6, /* 6, -9.0dB */
|
||||
0x0C0, /* 7, -8.5dB */
|
||||
0x0CC, /* 8, -8.0dB */
|
||||
0x0D8, /* 9, -7.5dB */
|
||||
0x0E5, /* 10, -7.0dB */
|
||||
0x0F2, /* 11, -6.5dB */
|
||||
0x101, /* 12, -6.0dB */
|
||||
0x110, /* 13, -5.5dB */
|
||||
0x120, /* 14, -5.0dB */
|
||||
0x131, /* 15, -4.5dB */
|
||||
0x143, /* 16, -4.0dB */
|
||||
0x156, /* 17, -3.5dB */
|
||||
0x16A, /* 18, -3.0dB */
|
||||
0x180, /* 19, -2.5dB */
|
||||
0x197, /* 20, -2.0dB */
|
||||
0x1AF, /* 21, -1.5dB */
|
||||
0x1C8, /* 22, -1.0dB */
|
||||
0x1E3, /* 23, -0.5dB */
|
||||
0x200, /* 24, +0 dB */
|
||||
0x21E, /* 25, +0.5dB */
|
||||
0x23E, /* 26, +1.0dB */
|
||||
0x261, /* 27, +1.5dB */
|
||||
0x285, /* 28, +2.0dB */
|
||||
0x2AB, /* 29, +2.5dB */
|
||||
0x2D3, /* 30, +3.0dB */
|
||||
0x2FE, /* 31, +3.5dB */
|
||||
0x32B, /* 32, +4.0dB */
|
||||
0x35C, /* 33, +4.5dB */
|
||||
0x38E, /* 34, +5.0dB */
|
||||
0x3C4, /* 35, +5.5dB */
|
||||
0x3FE /* 36, +6.0dB */
|
||||
};
|
||||
|
||||
|
||||
#ifdef AP_BUILD_WORKAROUND
|
||||
|
||||
unsigned int tx_pwr_trk_ofdm_swing_tbl[tx_pwr_trk_ofdm_swing_tbl_len] = {
|
||||
/* +6.0dB */ 0x7f8001fe,
|
||||
/* +5.5dB */ 0x788001e2,
|
||||
/* +5.0dB */ 0x71c001c7,
|
||||
/* +4.5dB */ 0x6b8001ae,
|
||||
/* +4.0dB */ 0x65400195,
|
||||
/* +3.5dB */ 0x5fc0017f,
|
||||
/* +3.0dB */ 0x5a400169,
|
||||
/* +2.5dB */ 0x55400155,
|
||||
/* +2.0dB */ 0x50800142,
|
||||
/* +1.5dB */ 0x4c000130,
|
||||
/* +1.0dB */ 0x47c0011f,
|
||||
/* +0.5dB */ 0x43c0010f,
|
||||
/* 0.0dB */ 0x40000100,
|
||||
/* -0.5dB */ 0x3c8000f2,
|
||||
/* -1.0dB */ 0x390000e4,
|
||||
/* -1.5dB */ 0x35c000d7,
|
||||
/* -2.0dB */ 0x32c000cb,
|
||||
/* -2.5dB */ 0x300000c0,
|
||||
/* -3.0dB */ 0x2d4000b5,
|
||||
/* -3.5dB */ 0x2ac000ab,
|
||||
/* -4.0dB */ 0x288000a2,
|
||||
/* -4.5dB */ 0x26000098,
|
||||
/* -5.0dB */ 0x24000090,
|
||||
/* -5.5dB */ 0x22000088,
|
||||
/* -6.0dB */ 0x20000080,
|
||||
/* -6.5dB */ 0x1a00006c,
|
||||
/* -7.0dB */ 0x1c800072,
|
||||
/* -7.5dB */ 0x18000060,
|
||||
/* -8.0dB */ 0x19800066,
|
||||
/* -8.5dB */ 0x15800056,
|
||||
/* -9.0dB */ 0x26c0005b,
|
||||
/* -9.5dB */ 0x14400051,
|
||||
/* -10.0dB */ 0x24400051,
|
||||
/* -10.5dB */ 0x1300004c,
|
||||
/* -11.0dB */ 0x12000048,
|
||||
/* -11.5dB */ 0x11000044,
|
||||
/* -12.0dB */ 0x10000040
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
void
|
||||
odm_txpowertracking_init(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
if (!(p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_IC_11N_SERIES | ODM_RTL8822B)))
|
||||
return;
|
||||
#endif
|
||||
|
||||
odm_txpowertracking_thermal_meter_init(p_dm_odm);
|
||||
}
|
||||
|
||||
u8
|
||||
get_swing_index(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
u8 i = 0;
|
||||
u32 bb_swing;
|
||||
u32 swing_table_size;
|
||||
u32 *p_swing_table;
|
||||
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8703B) {
|
||||
bb_swing = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000);
|
||||
|
||||
p_swing_table = ofdm_swing_table_new;
|
||||
swing_table_size = OFDM_TABLE_SIZE;
|
||||
} else {
|
||||
bb_swing = PHY_GetTxBBSwing_8812A(adapter, p_hal_data->CurrentBandType, ODM_RF_PATH_A);
|
||||
p_swing_table = tx_scaling_table_jaguar;
|
||||
swing_table_size = TXSCALE_TABLE_SIZE;
|
||||
}
|
||||
|
||||
for (i = 0; i < swing_table_size; ++i) {
|
||||
u32 table_value = p_swing_table[i];
|
||||
|
||||
if (table_value >= 0x100000)
|
||||
table_value >>= 22;
|
||||
if (bb_swing == table_value)
|
||||
break;
|
||||
}
|
||||
return i;
|
||||
}
|
||||
|
||||
void
|
||||
odm_txpowertracking_thermal_meter_init(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u8 default_swing_index = get_swing_index(p_dm_odm);
|
||||
struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
u8 p = 0;
|
||||
|
||||
if (p_dm_odm->mp_mode == false)
|
||||
p_rf_calibrate_info->txpowertrack_control = true;
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#ifdef CONFIG_RTL8188E
|
||||
{
|
||||
p_rf_calibrate_info->is_txpowertracking = _TRUE;
|
||||
p_rf_calibrate_info->tx_powercount = 0;
|
||||
p_rf_calibrate_info->is_txpowertracking_init = _FALSE;
|
||||
|
||||
if (p_dm_odm->mp_mode == false)
|
||||
p_rf_calibrate_info->txpowertrack_control = _TRUE;
|
||||
|
||||
MSG_8192C("p_dm_odm txpowertrack_control = %d\n", p_rf_calibrate_info->txpowertrack_control);
|
||||
}
|
||||
#else
|
||||
{
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct dm_priv *pdmpriv = &p_hal_data->dmpriv;
|
||||
|
||||
pdmpriv->is_txpowertracking = _TRUE;
|
||||
pdmpriv->tx_powercount = 0;
|
||||
pdmpriv->is_txpowertracking_init = _FALSE;
|
||||
|
||||
if (p_dm_odm->mp_mode == false)
|
||||
pdmpriv->txpowertrack_control = _TRUE;
|
||||
|
||||
MSG_8192C("pdmpriv->txpowertrack_control = %d\n", pdmpriv->txpowertrack_control);
|
||||
|
||||
}
|
||||
#endif
|
||||
#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
#ifdef RTL8188E_SUPPORT
|
||||
{
|
||||
p_rf_calibrate_info->is_txpowertracking = _TRUE;
|
||||
p_rf_calibrate_info->tx_powercount = 0;
|
||||
p_rf_calibrate_info->is_txpowertracking_init = _FALSE;
|
||||
p_rf_calibrate_info->txpowertrack_control = _TRUE;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#if (MP_DRIVER == 1)
|
||||
p_rf_calibrate_info->txpowertrack_control = false;
|
||||
#else
|
||||
p_rf_calibrate_info->txpowertrack_control = true;
|
||||
#endif
|
||||
#else
|
||||
p_rf_calibrate_info->txpowertrack_control = true;
|
||||
#endif
|
||||
|
||||
p_rf_calibrate_info->thermal_value = p_hal_data->eeprom_thermal_meter;
|
||||
p_rf_calibrate_info->thermal_value_iqk = p_hal_data->eeprom_thermal_meter;
|
||||
p_rf_calibrate_info->thermal_value_lck = p_hal_data->eeprom_thermal_meter;
|
||||
|
||||
if (p_rf_calibrate_info->default_bb_swing_index_flag != true) {
|
||||
/*The index of "0 dB" in SwingTable.*/
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8703B) {
|
||||
p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index;
|
||||
p_rf_calibrate_info->default_cck_index = 20;
|
||||
} else if (p_dm_odm->support_ic_type == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/
|
||||
p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/
|
||||
p_rf_calibrate_info->default_cck_index = 20; /*CCK:-6dB*/
|
||||
} else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/
|
||||
p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/
|
||||
p_rf_calibrate_info->default_cck_index = 28; /*CCK: -6dB*/
|
||||
} else {
|
||||
p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index;
|
||||
p_rf_calibrate_info->default_cck_index = 24;
|
||||
}
|
||||
p_rf_calibrate_info->default_bb_swing_index_flag = true;
|
||||
}
|
||||
|
||||
p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index;
|
||||
p_rf_calibrate_info->CCK_index = p_rf_calibrate_info->default_cck_index;
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) {
|
||||
p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->default_ofdm_index;
|
||||
p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index;
|
||||
p_rf_calibrate_info->delta_power_index[p] = 0;
|
||||
p_rf_calibrate_info->delta_power_index_last[p] = 0;
|
||||
p_rf_calibrate_info->power_index_offset[p] = 0;
|
||||
p_rf_calibrate_info->kfree_offset[p] = 0;
|
||||
}
|
||||
p_rf_calibrate_info->modify_tx_agc_value_ofdm = 0;
|
||||
p_rf_calibrate_info->modify_tx_agc_value_cck = 0;
|
||||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_txpowertracking_check(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
|
||||
#if 0
|
||||
/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
|
||||
/* at the same time. In the stage2/3, we need to prive universal interface and merge all */
|
||||
/* HW dynamic mechanism. */
|
||||
#endif
|
||||
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
switch (p_dm_odm->support_platform) {
|
||||
case ODM_WIN:
|
||||
odm_txpowertracking_check_mp(p_dm_odm);
|
||||
break;
|
||||
|
||||
case ODM_CE:
|
||||
odm_txpowertracking_check_ce(p_dm_odm);
|
||||
break;
|
||||
|
||||
case ODM_AP:
|
||||
odm_txpowertracking_check_ap(p_dm_odm);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
odm_txpowertracking_check_ce(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
#if ((RTL8188F_SUPPORT == 1))
|
||||
rtl8192c_odm_check_txpowertracking(adapter);
|
||||
#endif
|
||||
|
||||
#if (RTL8188E_SUPPORT == 1)
|
||||
|
||||
if (!(p_dm_odm->support_ability & ODM_RF_TX_PWR_TRACK))
|
||||
return;
|
||||
|
||||
if (!p_rf_calibrate_info->tm_trigger) {
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
|
||||
/*DBG_8192C("Trigger 92C Thermal Meter!!\n");*/
|
||||
|
||||
p_rf_calibrate_info->tm_trigger = 1;
|
||||
return;
|
||||
|
||||
} else {
|
||||
/*DBG_8192C("Schedule TxPowerTracking direct call!!\n");*/
|
||||
odm_txpowertracking_callback_thermal_meter_8188e(adapter);
|
||||
p_rf_calibrate_info->tm_trigger = 0;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
odm_txpowertracking_check_mp(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
|
||||
if (*p_dm_odm->p_is_fcs_mode_enable)
|
||||
return;
|
||||
|
||||
if (odm_check_power_status(adapter) == false) {
|
||||
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===>odm_check_power_status() return false\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
if (IS_HARDWARE_TYPE_8821B(adapter)) /* TODO: Don't Do PowerTracking*/
|
||||
return;
|
||||
|
||||
odm_txpowertracking_thermal_meter_check(adapter);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_txpowertracking_check_ap(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
return;
|
||||
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
|
||||
void
|
||||
odm_txpowertracking_direct_call(
|
||||
struct _ADAPTER *adapter
|
||||
)
|
||||
{
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
|
||||
odm_txpowertracking_callback_thermal_meter(adapter);
|
||||
}
|
||||
|
||||
void
|
||||
odm_txpowertracking_thermal_meter_check(
|
||||
struct _ADAPTER *adapter
|
||||
)
|
||||
{
|
||||
#ifndef AP_BUILD_WORKAROUND
|
||||
static u8 tm_trigger = 0;
|
||||
|
||||
if (!(GET_HAL_DATA(adapter)->DM_OutSrc.support_ability & ODM_RF_TX_PWR_TRACK)) {
|
||||
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
|
||||
("===>odm_txpowertracking_thermal_meter_check(),p_mgnt_info->is_txpowertracking is false, return!!\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
if (!tm_trigger) {
|
||||
if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8192E(adapter) ||
|
||||
IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8814A(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8703B(adapter)
|
||||
|| IS_HARDWARE_TYPE_8822B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8821C(adapter))
|
||||
PHY_SetRFReg(adapter, ODM_RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);
|
||||
else
|
||||
PHY_SetRFReg(adapter, ODM_RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
|
||||
|
||||
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Trigger Thermal Meter!!\n"));
|
||||
|
||||
tm_trigger = 1;
|
||||
return;
|
||||
} else {
|
||||
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Schedule TxPowerTracking direct call!!\n"));
|
||||
odm_txpowertracking_direct_call(adapter);
|
||||
tm_trigger = 0;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
299
hal/phydm/phydm_powertracking_win.h
Normal file
299
hal/phydm/phydm_powertracking_win.h
Normal file
|
|
@ -0,0 +1,299 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMPOWERTRACKING_H__
|
||||
#define __PHYDMPOWERTRACKING_H__
|
||||
|
||||
#define POWRTRACKING_VERSION "1.1"
|
||||
|
||||
#define DPK_DELTA_MAPPING_NUM 13
|
||||
#define index_mapping_HP_NUM 15
|
||||
#define TXSCALE_TABLE_SIZE 37
|
||||
#define CCK_TABLE_SIZE_8723D 41
|
||||
#define TXPWR_TRACK_TABLE_SIZE 30
|
||||
#define DELTA_SWINGIDX_SIZE 30
|
||||
#define DELTA_SWINTSSI_SIZE 61
|
||||
#define BAND_NUM 3
|
||||
#define MAX_RF_PATH 4
|
||||
#define CCK_TABLE_SIZE_88F 21
|
||||
|
||||
|
||||
#define dm_check_txpowertracking odm_txpowertracking_check
|
||||
|
||||
#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
|
||||
#define AVG_THERMAL_NUM 8
|
||||
#define HP_THERMAL_NUM 8
|
||||
#define iqk_matrix_reg_num 8
|
||||
#define IQK_MAC_REG_NUM 4
|
||||
#define IQK_ADDA_REG_NUM 16
|
||||
|
||||
#define IQK_BB_REG_NUM 9
|
||||
|
||||
|
||||
extern u32 ofdm_swing_table[OFDM_TABLE_SIZE];
|
||||
extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
|
||||
extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
|
||||
|
||||
extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
|
||||
extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
|
||||
extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
|
||||
extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
|
||||
extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
|
||||
extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
|
||||
extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
|
||||
|
||||
extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
|
||||
|
||||
/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
|
||||
static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
|
||||
static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
|
||||
|
||||
void
|
||||
odm_txpowertracking_check(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_check_ap(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_thermal_meter_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_check_mp(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
odm_txpowertracking_check_ce(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
|
||||
|
||||
|
||||
void
|
||||
odm_txpowertracking_thermal_meter_check(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
struct _IQK_MATRIX_REGS_SETTING {
|
||||
bool is_iqk_done;
|
||||
s32 value[3][iqk_matrix_reg_num];
|
||||
bool is_bw_iqk_result_saved[3];
|
||||
};
|
||||
|
||||
struct odm_rf_calibration_structure {
|
||||
/* for tx power tracking */
|
||||
|
||||
u32 rega24; /* for TempCCK */
|
||||
s32 rege94;
|
||||
s32 rege9c;
|
||||
s32 regeb4;
|
||||
s32 regebc;
|
||||
/* u8 is_txpowertracking; */
|
||||
u8 tx_powercount;
|
||||
bool is_txpowertracking_init;
|
||||
bool is_txpowertracking;
|
||||
u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
|
||||
u8 tm_trigger;
|
||||
u8 internal_pa_5g[2]; /* pathA / pathB */
|
||||
|
||||
u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
|
||||
u8 thermal_value;
|
||||
u8 thermal_value_lck;
|
||||
u8 thermal_value_iqk;
|
||||
s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
|
||||
u8 thermal_value_avg[AVG_THERMAL_NUM];
|
||||
u8 thermal_value_avg_index;
|
||||
u8 thermal_value_rx_gain;
|
||||
|
||||
bool is_reloadtxpowerindex;
|
||||
u8 is_rf_pi_enable;
|
||||
u32 txpowertracking_callback_cnt; /* cosa add for debug */
|
||||
|
||||
|
||||
/* ------------------------- Tx power Tracking ------------------------- */
|
||||
u8 is_cck_in_ch14;
|
||||
u8 CCK_index;
|
||||
u8 OFDM_index[MAX_RF_PATH];
|
||||
s8 power_index_offset[MAX_RF_PATH];
|
||||
s8 delta_power_index[MAX_RF_PATH];
|
||||
s8 delta_power_index_last[MAX_RF_PATH];
|
||||
bool is_tx_power_changed;
|
||||
s8 xtal_offset;
|
||||
s8 xtal_offset_last;
|
||||
|
||||
u8 thermal_value_hp[HP_THERMAL_NUM];
|
||||
u8 thermal_value_hp_index;
|
||||
struct _IQK_MATRIX_REGS_SETTING iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
|
||||
u8 delta_lck;
|
||||
s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
|
||||
u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
|
||||
s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
|
||||
s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
|
||||
u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
|
||||
|
||||
u8 bb_swing_idx_ofdm[MAX_RF_PATH];
|
||||
u8 bb_swing_idx_ofdm_current;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
|
||||
#else
|
||||
u8 bb_swing_idx_ofdm_base;
|
||||
#endif
|
||||
bool default_bb_swing_index_flag;
|
||||
bool bb_swing_flag_ofdm;
|
||||
u8 bb_swing_idx_cck;
|
||||
u8 bb_swing_idx_cck_current;
|
||||
u8 bb_swing_idx_cck_base;
|
||||
u8 default_ofdm_index;
|
||||
u8 default_cck_index;
|
||||
bool bb_swing_flag_cck;
|
||||
|
||||
s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
|
||||
s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
|
||||
s8 absolute_cck_swing_idx[MAX_RF_PATH];
|
||||
s8 remnant_cck_swing_idx;
|
||||
s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
|
||||
bool modify_tx_agc_flag_path_a;
|
||||
bool modify_tx_agc_flag_path_b;
|
||||
bool modify_tx_agc_flag_path_c;
|
||||
bool modify_tx_agc_flag_path_d;
|
||||
bool modify_tx_agc_flag_path_a_cck;
|
||||
|
||||
s8 kfree_offset[MAX_RF_PATH];
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
|
||||
/* for IQK */
|
||||
u32 regc04;
|
||||
u32 reg874;
|
||||
u32 regc08;
|
||||
u32 regb68;
|
||||
u32 regb6c;
|
||||
u32 reg870;
|
||||
u32 reg860;
|
||||
u32 reg864;
|
||||
|
||||
bool is_iqk_initialized;
|
||||
bool is_lck_in_progress;
|
||||
bool is_antenna_detected;
|
||||
bool is_need_iqk;
|
||||
bool is_iqk_in_progress;
|
||||
bool is_iqk_pa_off;
|
||||
u8 delta_iqk;
|
||||
u32 ADDA_backup[IQK_ADDA_REG_NUM];
|
||||
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
|
||||
u32 IQK_BB_backup_recover[9];
|
||||
u32 IQK_BB_backup[IQK_BB_REG_NUM];
|
||||
u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
|
||||
u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
|
||||
u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
|
||||
u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
|
||||
u32 tx_iqc_8723d[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
|
||||
u32 rx_iqc_8723d[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
|
||||
|
||||
u64 iqk_start_time;
|
||||
u64 iqk_total_progressing_time;
|
||||
u64 iqk_progressing_time;
|
||||
u32 lok_result;
|
||||
u8 iqk_step;
|
||||
u8 kcount;
|
||||
u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
|
||||
bool is_mp_mode;
|
||||
|
||||
/* for APK */
|
||||
u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
|
||||
u8 is_ap_kdone;
|
||||
u8 is_apk_thermal_meter_ignore;
|
||||
|
||||
/* DPK */
|
||||
bool is_dpk_fail;
|
||||
u8 is_dp_done;
|
||||
u8 is_dp_path_aok;
|
||||
u8 is_dp_path_bok;
|
||||
|
||||
u32 tx_lok[2];
|
||||
u32 dpk_tx_agc;
|
||||
s32 dpk_gain;
|
||||
u32 dpk_thermal[4];
|
||||
|
||||
s8 modify_tx_agc_value_ofdm;
|
||||
s8 modify_tx_agc_value_cck;
|
||||
|
||||
/*Add by Yuchen for Kfree Phydm*/
|
||||
u8 reg_rf_kfree_enable; /*for registry*/
|
||||
u8 rf_kfree_enable; /*for efuse enable check*/
|
||||
|
||||
HALMAC_PWR_TRACKING_OPTION HALMAC_PWR_TRACKING_INFO;
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
677
hal/phydm/phydm_pre_define.h
Normal file
677
hal/phydm/phydm_pre_define.h
Normal file
|
|
@ -0,0 +1,677 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __PHYDMPREDEFINE_H__
|
||||
#define __PHYDMPREDEFINE_H__
|
||||
|
||||
/* 1 ============================================================
|
||||
* 1 Definition
|
||||
* 1 ============================================================ */
|
||||
|
||||
#define PHYDM_CODE_BASE "PHYDM_012"
|
||||
#define PHYDM_RELEASE_DATE "20160900"
|
||||
|
||||
/* Max path of IC */
|
||||
#define MAX_PATH_NUM_8188E 1
|
||||
#define MAX_PATH_NUM_8192E 2
|
||||
#define MAX_PATH_NUM_8723B 1
|
||||
#define MAX_PATH_NUM_8812A 2
|
||||
#define MAX_PATH_NUM_8821A 1
|
||||
#define MAX_PATH_NUM_8814A 4
|
||||
#define MAX_PATH_NUM_8822B 2
|
||||
#define MAX_PATH_NUM_8821B 2
|
||||
#define MAX_PATH_NUM_8703B 1
|
||||
#define MAX_PATH_NUM_8188F 1
|
||||
#define MAX_PATH_NUM_8723D 1
|
||||
#define MAX_PATH_NUM_8197F 2
|
||||
#define MAX_PATH_NUM_8821C 1
|
||||
|
||||
/* Max RF path */
|
||||
#define ODM_RF_PATH_MAX 2
|
||||
#define ODM_RF_PATH_MAX_JAGUAR 4
|
||||
|
||||
/*Bit define path*/
|
||||
#define PHYDM_A BIT(0)
|
||||
#define PHYDM_B BIT(1)
|
||||
#define PHYDM_C BIT(2)
|
||||
#define PHYDM_D BIT(3)
|
||||
#define PHYDM_AB (BIT(0) | BIT(1))
|
||||
#define PHYDM_AC (BIT(0) | BIT(2))
|
||||
#define PHYDM_AD (BIT(0) | BIT(3))
|
||||
#define PHYDM_BC (BIT(1) | BIT(2))
|
||||
#define PHYDM_BD (BIT(1) | BIT(3))
|
||||
#define PHYDM_CD (BIT(2) | BIT(3))
|
||||
#define PHYDM_ABC (BIT(0) | BIT(1) | BIT(2))
|
||||
#define PHYDM_ABD (BIT(0) | BIT(1) | BIT(3))
|
||||
#define PHYDM_ACD (BIT(0) | BIT(2) | BIT(3))
|
||||
#define PHYDM_BCD (BIT(1) | BIT(2) | BIT(3))
|
||||
#define PHYDM_ABCD (BIT(0) | BIT(1) | BIT(2) | BIT(3))
|
||||
|
||||
/* number of entry */
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
|
||||
#define ASSOCIATE_ENTRY_NUM MACID_NUM_SW_LIMIT /* Max size of asoc_entry[].*/
|
||||
#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
|
||||
#elif(DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
#define ASSOCIATE_ENTRY_NUM NUM_STAT
|
||||
#define ODM_ASSOCIATE_ENTRY_NUM (ASSOCIATE_ENTRY_NUM+1)
|
||||
#else
|
||||
#define ODM_ASSOCIATE_ENTRY_NUM ((ASSOCIATE_ENTRY_NUM*3)+1)
|
||||
#endif
|
||||
|
||||
/* -----MGN rate--------------------------------- */
|
||||
|
||||
enum ODM_MGN_RATE {
|
||||
ODM_MGN_1M = 0x02,
|
||||
ODM_MGN_2M = 0x04,
|
||||
ODM_MGN_5_5M = 0x0B,
|
||||
ODM_MGN_6M = 0x0C,
|
||||
ODM_MGN_9M = 0x12,
|
||||
ODM_MGN_11M = 0x16,
|
||||
ODM_MGN_12M = 0x18,
|
||||
ODM_MGN_18M = 0x24,
|
||||
ODM_MGN_24M = 0x30,
|
||||
ODM_MGN_36M = 0x48,
|
||||
ODM_MGN_48M = 0x60,
|
||||
ODM_MGN_54M = 0x6C,
|
||||
ODM_MGN_MCS32 = 0x7F,
|
||||
ODM_MGN_MCS0,
|
||||
ODM_MGN_MCS1,
|
||||
ODM_MGN_MCS2,
|
||||
ODM_MGN_MCS3,
|
||||
ODM_MGN_MCS4,
|
||||
ODM_MGN_MCS5,
|
||||
ODM_MGN_MCS6,
|
||||
ODM_MGN_MCS7,
|
||||
ODM_MGN_MCS8,
|
||||
ODM_MGN_MCS9,
|
||||
ODM_MGN_MCS10,
|
||||
ODM_MGN_MCS11,
|
||||
ODM_MGN_MCS12,
|
||||
ODM_MGN_MCS13,
|
||||
ODM_MGN_MCS14,
|
||||
ODM_MGN_MCS15,
|
||||
ODM_MGN_MCS16,
|
||||
ODM_MGN_MCS17,
|
||||
ODM_MGN_MCS18,
|
||||
ODM_MGN_MCS19,
|
||||
ODM_MGN_MCS20,
|
||||
ODM_MGN_MCS21,
|
||||
ODM_MGN_MCS22,
|
||||
ODM_MGN_MCS23,
|
||||
ODM_MGN_MCS24,
|
||||
ODM_MGN_MCS25,
|
||||
ODM_MGN_MCS26,
|
||||
ODM_MGN_MCS27,
|
||||
ODM_MGN_MCS28,
|
||||
ODM_MGN_MCS29,
|
||||
ODM_MGN_MCS30,
|
||||
ODM_MGN_MCS31,
|
||||
ODM_MGN_VHT1SS_MCS0,
|
||||
ODM_MGN_VHT1SS_MCS1,
|
||||
ODM_MGN_VHT1SS_MCS2,
|
||||
ODM_MGN_VHT1SS_MCS3,
|
||||
ODM_MGN_VHT1SS_MCS4,
|
||||
ODM_MGN_VHT1SS_MCS5,
|
||||
ODM_MGN_VHT1SS_MCS6,
|
||||
ODM_MGN_VHT1SS_MCS7,
|
||||
ODM_MGN_VHT1SS_MCS8,
|
||||
ODM_MGN_VHT1SS_MCS9,
|
||||
ODM_MGN_VHT2SS_MCS0,
|
||||
ODM_MGN_VHT2SS_MCS1,
|
||||
ODM_MGN_VHT2SS_MCS2,
|
||||
ODM_MGN_VHT2SS_MCS3,
|
||||
ODM_MGN_VHT2SS_MCS4,
|
||||
ODM_MGN_VHT2SS_MCS5,
|
||||
ODM_MGN_VHT2SS_MCS6,
|
||||
ODM_MGN_VHT2SS_MCS7,
|
||||
ODM_MGN_VHT2SS_MCS8,
|
||||
ODM_MGN_VHT2SS_MCS9,
|
||||
ODM_MGN_VHT3SS_MCS0,
|
||||
ODM_MGN_VHT3SS_MCS1,
|
||||
ODM_MGN_VHT3SS_MCS2,
|
||||
ODM_MGN_VHT3SS_MCS3,
|
||||
ODM_MGN_VHT3SS_MCS4,
|
||||
ODM_MGN_VHT3SS_MCS5,
|
||||
ODM_MGN_VHT3SS_MCS6,
|
||||
ODM_MGN_VHT3SS_MCS7,
|
||||
ODM_MGN_VHT3SS_MCS8,
|
||||
ODM_MGN_VHT3SS_MCS9,
|
||||
ODM_MGN_VHT4SS_MCS0,
|
||||
ODM_MGN_VHT4SS_MCS1,
|
||||
ODM_MGN_VHT4SS_MCS2,
|
||||
ODM_MGN_VHT4SS_MCS3,
|
||||
ODM_MGN_VHT4SS_MCS4,
|
||||
ODM_MGN_VHT4SS_MCS5,
|
||||
ODM_MGN_VHT4SS_MCS6,
|
||||
ODM_MGN_VHT4SS_MCS7,
|
||||
ODM_MGN_VHT4SS_MCS8,
|
||||
ODM_MGN_VHT4SS_MCS9,
|
||||
ODM_MGN_UNKNOWN
|
||||
};
|
||||
|
||||
#define ODM_MGN_MCS0_SG 0xc0
|
||||
#define ODM_MGN_MCS1_SG 0xc1
|
||||
#define ODM_MGN_MCS2_SG 0xc2
|
||||
#define ODM_MGN_MCS3_SG 0xc3
|
||||
#define ODM_MGN_MCS4_SG 0xc4
|
||||
#define ODM_MGN_MCS5_SG 0xc5
|
||||
#define ODM_MGN_MCS6_SG 0xc6
|
||||
#define ODM_MGN_MCS7_SG 0xc7
|
||||
#define ODM_MGN_MCS8_SG 0xc8
|
||||
#define ODM_MGN_MCS9_SG 0xc9
|
||||
#define ODM_MGN_MCS10_SG 0xca
|
||||
#define ODM_MGN_MCS11_SG 0xcb
|
||||
#define ODM_MGN_MCS12_SG 0xcc
|
||||
#define ODM_MGN_MCS13_SG 0xcd
|
||||
#define ODM_MGN_MCS14_SG 0xce
|
||||
#define ODM_MGN_MCS15_SG 0xcf
|
||||
|
||||
/* -----DESC rate--------------------------------- */
|
||||
|
||||
#define ODM_RATEMCS15_SG 0x1c
|
||||
#define ODM_RATEMCS32 0x20
|
||||
|
||||
|
||||
/* CCK Rates, TxHT = 0 */
|
||||
#define ODM_RATE1M 0x00
|
||||
#define ODM_RATE2M 0x01
|
||||
#define ODM_RATE5_5M 0x02
|
||||
#define ODM_RATE11M 0x03
|
||||
/* OFDM Rates, TxHT = 0 */
|
||||
#define ODM_RATE6M 0x04
|
||||
#define ODM_RATE9M 0x05
|
||||
#define ODM_RATE12M 0x06
|
||||
#define ODM_RATE18M 0x07
|
||||
#define ODM_RATE24M 0x08
|
||||
#define ODM_RATE36M 0x09
|
||||
#define ODM_RATE48M 0x0A
|
||||
#define ODM_RATE54M 0x0B
|
||||
/* MCS Rates, TxHT = 1 */
|
||||
#define ODM_RATEMCS0 0x0C
|
||||
#define ODM_RATEMCS1 0x0D
|
||||
#define ODM_RATEMCS2 0x0E
|
||||
#define ODM_RATEMCS3 0x0F
|
||||
#define ODM_RATEMCS4 0x10
|
||||
#define ODM_RATEMCS5 0x11
|
||||
#define ODM_RATEMCS6 0x12
|
||||
#define ODM_RATEMCS7 0x13
|
||||
#define ODM_RATEMCS8 0x14
|
||||
#define ODM_RATEMCS9 0x15
|
||||
#define ODM_RATEMCS10 0x16
|
||||
#define ODM_RATEMCS11 0x17
|
||||
#define ODM_RATEMCS12 0x18
|
||||
#define ODM_RATEMCS13 0x19
|
||||
#define ODM_RATEMCS14 0x1A
|
||||
#define ODM_RATEMCS15 0x1B
|
||||
#define ODM_RATEMCS16 0x1C
|
||||
#define ODM_RATEMCS17 0x1D
|
||||
#define ODM_RATEMCS18 0x1E
|
||||
#define ODM_RATEMCS19 0x1F
|
||||
#define ODM_RATEMCS20 0x20
|
||||
#define ODM_RATEMCS21 0x21
|
||||
#define ODM_RATEMCS22 0x22
|
||||
#define ODM_RATEMCS23 0x23
|
||||
#define ODM_RATEMCS24 0x24
|
||||
#define ODM_RATEMCS25 0x25
|
||||
#define ODM_RATEMCS26 0x26
|
||||
#define ODM_RATEMCS27 0x27
|
||||
#define ODM_RATEMCS28 0x28
|
||||
#define ODM_RATEMCS29 0x29
|
||||
#define ODM_RATEMCS30 0x2A
|
||||
#define ODM_RATEMCS31 0x2B
|
||||
#define ODM_RATEVHTSS1MCS0 0x2C
|
||||
#define ODM_RATEVHTSS1MCS1 0x2D
|
||||
#define ODM_RATEVHTSS1MCS2 0x2E
|
||||
#define ODM_RATEVHTSS1MCS3 0x2F
|
||||
#define ODM_RATEVHTSS1MCS4 0x30
|
||||
#define ODM_RATEVHTSS1MCS5 0x31
|
||||
#define ODM_RATEVHTSS1MCS6 0x32
|
||||
#define ODM_RATEVHTSS1MCS7 0x33
|
||||
#define ODM_RATEVHTSS1MCS8 0x34
|
||||
#define ODM_RATEVHTSS1MCS9 0x35
|
||||
#define ODM_RATEVHTSS2MCS0 0x36
|
||||
#define ODM_RATEVHTSS2MCS1 0x37
|
||||
#define ODM_RATEVHTSS2MCS2 0x38
|
||||
#define ODM_RATEVHTSS2MCS3 0x39
|
||||
#define ODM_RATEVHTSS2MCS4 0x3A
|
||||
#define ODM_RATEVHTSS2MCS5 0x3B
|
||||
#define ODM_RATEVHTSS2MCS6 0x3C
|
||||
#define ODM_RATEVHTSS2MCS7 0x3D
|
||||
#define ODM_RATEVHTSS2MCS8 0x3E
|
||||
#define ODM_RATEVHTSS2MCS9 0x3F
|
||||
#define ODM_RATEVHTSS3MCS0 0x40
|
||||
#define ODM_RATEVHTSS3MCS1 0x41
|
||||
#define ODM_RATEVHTSS3MCS2 0x42
|
||||
#define ODM_RATEVHTSS3MCS3 0x43
|
||||
#define ODM_RATEVHTSS3MCS4 0x44
|
||||
#define ODM_RATEVHTSS3MCS5 0x45
|
||||
#define ODM_RATEVHTSS3MCS6 0x46
|
||||
#define ODM_RATEVHTSS3MCS7 0x47
|
||||
#define ODM_RATEVHTSS3MCS8 0x48
|
||||
#define ODM_RATEVHTSS3MCS9 0x49
|
||||
#define ODM_RATEVHTSS4MCS0 0x4A
|
||||
#define ODM_RATEVHTSS4MCS1 0x4B
|
||||
#define ODM_RATEVHTSS4MCS2 0x4C
|
||||
#define ODM_RATEVHTSS4MCS3 0x4D
|
||||
#define ODM_RATEVHTSS4MCS4 0x4E
|
||||
#define ODM_RATEVHTSS4MCS5 0x4F
|
||||
#define ODM_RATEVHTSS4MCS6 0x50
|
||||
#define ODM_RATEVHTSS4MCS7 0x51
|
||||
#define ODM_RATEVHTSS4MCS8 0x52
|
||||
#define ODM_RATEVHTSS4MCS9 0x53
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1)
|
||||
#else
|
||||
#if (RTL8192E_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)
|
||||
#define ODM_NUM_RATE_IDX (ODM_RATEMCS15+1)
|
||||
#elif (RTL8723B_SUPPORT == 1) || (RTL8188E_SUPPORT == 1) || (RTL8188F_SUPPORT == 1)
|
||||
#define ODM_NUM_RATE_IDX (ODM_RATEMCS7+1)
|
||||
#elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1)
|
||||
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS1MCS9+1)
|
||||
#elif (RTL8812A_SUPPORT == 1)
|
||||
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS2MCS9+1)
|
||||
#elif (RTL8814A_SUPPORT == 1)
|
||||
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS3MCS9+1)
|
||||
#else
|
||||
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define CONFIG_SFW_SUPPORTED
|
||||
#endif
|
||||
|
||||
/* 1 ============================================================
|
||||
* 1 enumeration
|
||||
* 1 ============================================================ */
|
||||
|
||||
|
||||
/* ODM_CMNINFO_INTERFACE */
|
||||
enum odm_interface_e {
|
||||
ODM_ITRF_PCIE = 0x1,
|
||||
ODM_ITRF_USB = 0x2,
|
||||
ODM_ITRF_SDIO = 0x4,
|
||||
ODM_ITRF_ALL = 0x7,
|
||||
};
|
||||
|
||||
/* ODM_CMNINFO_IC_TYPE */
|
||||
enum odm_ic_type_e {
|
||||
ODM_RTL8188E = BIT(0),
|
||||
ODM_RTL8812 = BIT(1),
|
||||
ODM_RTL8821 = BIT(2),
|
||||
ODM_RTL8192E = BIT(3),
|
||||
ODM_RTL8723B = BIT(4),
|
||||
ODM_RTL8814A = BIT(5),
|
||||
ODM_RTL8881A = BIT(6),
|
||||
ODM_RTL8822B = BIT(7),
|
||||
ODM_RTL8703B = BIT(8),
|
||||
ODM_RTL8195A = BIT(9),
|
||||
ODM_RTL8188F = BIT(10),
|
||||
ODM_RTL8723D = BIT(11),
|
||||
ODM_RTL8197F = BIT(12),
|
||||
ODM_RTL8821C = BIT(13),
|
||||
ODM_RTL8814B = BIT(14),
|
||||
ODM_RTL8198F = BIT(15)
|
||||
};
|
||||
|
||||
|
||||
#define ODM_IC_1SS (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C | ODM_RTL8195A)
|
||||
#define ODM_IC_2SS (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8812 | ODM_RTL8822B)
|
||||
#define ODM_IC_3SS (ODM_RTL8814A)
|
||||
#define ODM_IC_4SS (ODM_RTL8814B | ODM_RTL8198F)
|
||||
|
||||
|
||||
#define ODM_IC_11N_SERIES (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8197F)
|
||||
#define ODM_IC_11AC_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8821C)
|
||||
#define ODM_IC_11AC_1_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)
|
||||
#define ODM_IC_11AC_2_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)
|
||||
#define ODM_IC_TXBF_SUPPORT (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)
|
||||
#define ODM_IC_11N_GAIN_IDX_EDCCA (ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8197F)
|
||||
#define ODM_IC_11AC_GAIN_IDX_EDCCA (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)
|
||||
#define ODM_IC_PHY_STATUE_NEW_TYPE (ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D | ODM_RTL8821C)
|
||||
|
||||
#define PHYDM_IC_8051_SERIES (ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8188F)
|
||||
#define PHYDM_IC_3081_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)
|
||||
|
||||
#define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
|
||||
#ifdef RTK_AC_SUPPORT
|
||||
#define ODM_IC_11AC_SERIES_SUPPORT 1
|
||||
#else
|
||||
#define ODM_IC_11AC_SERIES_SUPPORT 0
|
||||
#endif
|
||||
|
||||
#define ODM_IC_11N_SERIES_SUPPORT 1
|
||||
#define ODM_CONFIG_BT_COEXIST 0
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
|
||||
#define ODM_IC_11AC_SERIES_SUPPORT 1
|
||||
#define ODM_IC_11N_SERIES_SUPPORT 1
|
||||
#define ODM_CONFIG_BT_COEXIST 1
|
||||
|
||||
#else
|
||||
|
||||
#if ((RTL8188E_SUPPORT == 1) || \
|
||||
(RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8195A_SUPPORT == 1) || (RTL8703B_SUPPORT == 1) || \
|
||||
(RTL8188F_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
|
||||
#define ODM_IC_11N_SERIES_SUPPORT 1
|
||||
#define ODM_IC_11AC_SERIES_SUPPORT 0
|
||||
#else
|
||||
#define ODM_IC_11N_SERIES_SUPPORT 0
|
||||
#define ODM_IC_11AC_SERIES_SUPPORT 1
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
#define ODM_CONFIG_BT_COEXIST 1
|
||||
#else
|
||||
#define ODM_CONFIG_BT_COEXIST 0
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if ((RTL8197F_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1))
|
||||
#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 1
|
||||
#else
|
||||
#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 0
|
||||
#endif
|
||||
|
||||
/* ODM_CMNINFO_CUT_VER */
|
||||
enum odm_cut_version_e {
|
||||
ODM_CUT_A = 0,
|
||||
ODM_CUT_B = 1,
|
||||
ODM_CUT_C = 2,
|
||||
ODM_CUT_D = 3,
|
||||
ODM_CUT_E = 4,
|
||||
ODM_CUT_F = 5,
|
||||
|
||||
ODM_CUT_I = 8,
|
||||
ODM_CUT_J = 9,
|
||||
ODM_CUT_K = 10,
|
||||
ODM_CUT_TEST = 15,
|
||||
};
|
||||
|
||||
/* ODM_CMNINFO_FAB_VER */
|
||||
enum odm_fab_e {
|
||||
ODM_TSMC = 0,
|
||||
ODM_UMC = 1,
|
||||
};
|
||||
|
||||
/* ODM_CMNINFO_RF_TYPE
|
||||
*
|
||||
* For example 1T2R (A+AB = BIT(0)|BIT(4)|BIT(5))
|
||||
* */
|
||||
enum odm_rf_path_e {
|
||||
ODM_RF_A = BIT(0),
|
||||
ODM_RF_B = BIT(1),
|
||||
ODM_RF_C = BIT(2),
|
||||
ODM_RF_D = BIT(3),
|
||||
};
|
||||
|
||||
enum odm_rf_tx_num_e {
|
||||
ODM_1T = 1,
|
||||
ODM_2T = 2,
|
||||
ODM_3T = 3,
|
||||
ODM_4T = 4,
|
||||
};
|
||||
|
||||
enum odm_rf_type_e {
|
||||
ODM_1T1R,
|
||||
ODM_1T2R,
|
||||
ODM_2T2R,
|
||||
ODM_2T2R_GREEN,
|
||||
ODM_2T3R,
|
||||
ODM_2T4R,
|
||||
ODM_3T3R,
|
||||
ODM_3T4R,
|
||||
ODM_4T4R,
|
||||
ODM_XTXR
|
||||
};
|
||||
|
||||
|
||||
enum odm_mac_phy_mode_e {
|
||||
ODM_SMSP = 0,
|
||||
ODM_DMSP = 1,
|
||||
ODM_DMDP = 2,
|
||||
};
|
||||
|
||||
|
||||
enum odm_bt_coexist_e {
|
||||
ODM_BT_BUSY = 1,
|
||||
ODM_BT_ON = 2,
|
||||
ODM_BT_OFF = 3,
|
||||
ODM_BT_NONE = 4,
|
||||
};
|
||||
|
||||
/* ODM_CMNINFO_OP_MODE */
|
||||
enum odm_operation_mode_e {
|
||||
ODM_NO_LINK = BIT(0),
|
||||
ODM_LINK = BIT(1),
|
||||
ODM_SCAN = BIT(2),
|
||||
ODM_POWERSAVE = BIT(3),
|
||||
ODM_AP_MODE = BIT(4),
|
||||
ODM_CLIENT_MODE = BIT(5),
|
||||
ODM_AD_HOC = BIT(6),
|
||||
ODM_WIFI_DIRECT = BIT(7),
|
||||
ODM_WIFI_DISPLAY = BIT(8),
|
||||
};
|
||||
|
||||
/* ODM_CMNINFO_WM_MODE */
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
|
||||
enum odm_wireless_mode_e {
|
||||
ODM_WM_UNKNOW = 0x0,
|
||||
ODM_WM_B = BIT(0),
|
||||
ODM_WM_G = BIT(1),
|
||||
ODM_WM_A = BIT(2),
|
||||
ODM_WM_N24G = BIT(3),
|
||||
ODM_WM_N5G = BIT(4),
|
||||
ODM_WM_AUTO = BIT(5),
|
||||
ODM_WM_AC = BIT(6),
|
||||
};
|
||||
#else
|
||||
enum odm_wireless_mode_e {
|
||||
ODM_WM_UNKNOWN = 0x00,/*0x0*/
|
||||
ODM_WM_A = BIT(0), /* 0x1*/
|
||||
ODM_WM_B = BIT(1), /* 0x2*/
|
||||
ODM_WM_G = BIT(2),/* 0x4*/
|
||||
ODM_WM_AUTO = BIT(3),/* 0x8*/
|
||||
ODM_WM_N24G = BIT(4),/* 0x10*/
|
||||
ODM_WM_N5G = BIT(5),/* 0x20*/
|
||||
ODM_WM_AC_5G = BIT(6),/* 0x40*/
|
||||
ODM_WM_AC_24G = BIT(7),/* 0x80*/
|
||||
ODM_WM_AC_ONLY = BIT(8),/* 0x100*/
|
||||
ODM_WM_MAX = BIT(11)/* 0x800*/
|
||||
|
||||
};
|
||||
#endif
|
||||
|
||||
/* ODM_CMNINFO_BAND */
|
||||
enum odm_band_type_e {
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
ODM_BAND_2_4G = BIT(0),
|
||||
ODM_BAND_5G = BIT(1),
|
||||
#else
|
||||
ODM_BAND_2_4G = 0,
|
||||
ODM_BAND_5G,
|
||||
ODM_BAND_ON_BOTH,
|
||||
ODM_BANDMAX
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* ODM_CMNINFO_SEC_CHNL_OFFSET */
|
||||
enum phydm_sec_chnl_offset_e {
|
||||
|
||||
PHYDM_DONT_CARE = 0,
|
||||
PHYDM_BELOW = 1,
|
||||
PHYDM_ABOVE = 2
|
||||
};
|
||||
|
||||
/* ODM_CMNINFO_SEC_MODE */
|
||||
enum odm_security_e {
|
||||
ODM_SEC_OPEN = 0,
|
||||
ODM_SEC_WEP40 = 1,
|
||||
ODM_SEC_TKIP = 2,
|
||||
ODM_SEC_RESERVE = 3,
|
||||
ODM_SEC_AESCCMP = 4,
|
||||
ODM_SEC_WEP104 = 5,
|
||||
ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */
|
||||
ODM_SEC_SMS4 = 7,
|
||||
};
|
||||
|
||||
/* ODM_CMNINFO_BW */
|
||||
enum odm_bw_e {
|
||||
ODM_BW20M = 0,
|
||||
ODM_BW40M = 1,
|
||||
ODM_BW80M = 2,
|
||||
ODM_BW160M = 3,
|
||||
ODM_BW5M = 4,
|
||||
ODM_BW10M = 5,
|
||||
ODM_BW_MAX = 6
|
||||
};
|
||||
|
||||
/* ODM_CMNINFO_CHNL */
|
||||
|
||||
/* ODM_CMNINFO_BOARD_TYPE */
|
||||
enum odm_board_type_e {
|
||||
ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */
|
||||
ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1= mini card. */
|
||||
ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */
|
||||
ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */
|
||||
ODM_BOARD_EXT_PA = BIT(3), /* 0 = no 2G ext-PA, 1 = existing 2G ext-PA */
|
||||
ODM_BOARD_EXT_LNA = BIT(4), /* 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */
|
||||
ODM_BOARD_EXT_TRSW = BIT(5), /* 0 = no ext-TRSW, 1 = existing ext-TRSW */
|
||||
ODM_BOARD_EXT_PA_5G = BIT(6), /* 0 = no 5G ext-PA, 1 = existing 5G ext-PA */
|
||||
ODM_BOARD_EXT_LNA_5G = BIT(7), /* 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */
|
||||
};
|
||||
|
||||
enum odm_package_type_e {
|
||||
ODM_PACKAGE_DEFAULT = 0,
|
||||
ODM_PACKAGE_QFN68 = BIT(0),
|
||||
ODM_PACKAGE_TFBGA90 = BIT(1),
|
||||
ODM_PACKAGE_TFBGA79 = BIT(2),
|
||||
};
|
||||
|
||||
enum odm_type_gpa_e {
|
||||
TYPE_GPA0 = 0x0000,
|
||||
TYPE_GPA1 = 0x0055,
|
||||
TYPE_GPA2 = 0x00AA,
|
||||
TYPE_GPA3 = 0x00FF,
|
||||
TYPE_GPA4 = 0x5500,
|
||||
TYPE_GPA5 = 0x5555,
|
||||
TYPE_GPA6 = 0x55AA,
|
||||
TYPE_GPA7 = 0x55FF,
|
||||
TYPE_GPA8 = 0xAA00,
|
||||
TYPE_GPA9 = 0xAA55,
|
||||
TYPE_GPA10 = 0xAAAA,
|
||||
TYPE_GPA11 = 0xAAFF,
|
||||
TYPE_GPA12 = 0xFF00,
|
||||
TYPE_GPA13 = 0xFF55,
|
||||
TYPE_GPA14 = 0xFFAA,
|
||||
TYPE_GPA15 = 0xFFFF,
|
||||
};
|
||||
|
||||
enum odm_type_apa_e {
|
||||
TYPE_APA0 = 0x0000,
|
||||
TYPE_APA1 = 0x0055,
|
||||
TYPE_APA2 = 0x00AA,
|
||||
TYPE_APA3 = 0x00FF,
|
||||
TYPE_APA4 = 0x5500,
|
||||
TYPE_APA5 = 0x5555,
|
||||
TYPE_APA6 = 0x55AA,
|
||||
TYPE_APA7 = 0x55FF,
|
||||
TYPE_APA8 = 0xAA00,
|
||||
TYPE_APA9 = 0xAA55,
|
||||
TYPE_APA10 = 0xAAAA,
|
||||
TYPE_APA11 = 0xAAFF,
|
||||
TYPE_APA12 = 0xFF00,
|
||||
TYPE_APA13 = 0xFF55,
|
||||
TYPE_APA14 = 0xFFAA,
|
||||
TYPE_APA15 = 0xFFFF,
|
||||
};
|
||||
|
||||
enum odm_type_glna_e {
|
||||
TYPE_GLNA0 = 0x0000,
|
||||
TYPE_GLNA1 = 0x0055,
|
||||
TYPE_GLNA2 = 0x00AA,
|
||||
TYPE_GLNA3 = 0x00FF,
|
||||
TYPE_GLNA4 = 0x5500,
|
||||
TYPE_GLNA5 = 0x5555,
|
||||
TYPE_GLNA6 = 0x55AA,
|
||||
TYPE_GLNA7 = 0x55FF,
|
||||
TYPE_GLNA8 = 0xAA00,
|
||||
TYPE_GLNA9 = 0xAA55,
|
||||
TYPE_GLNA10 = 0xAAAA,
|
||||
TYPE_GLNA11 = 0xAAFF,
|
||||
TYPE_GLNA12 = 0xFF00,
|
||||
TYPE_GLNA13 = 0xFF55,
|
||||
TYPE_GLNA14 = 0xFFAA,
|
||||
TYPE_GLNA15 = 0xFFFF,
|
||||
};
|
||||
|
||||
enum odm_type_alna_e {
|
||||
TYPE_ALNA0 = 0x0000,
|
||||
TYPE_ALNA1 = 0x0055,
|
||||
TYPE_ALNA2 = 0x00AA,
|
||||
TYPE_ALNA3 = 0x00FF,
|
||||
TYPE_ALNA4 = 0x5500,
|
||||
TYPE_ALNA5 = 0x5555,
|
||||
TYPE_ALNA6 = 0x55AA,
|
||||
TYPE_ALNA7 = 0x55FF,
|
||||
TYPE_ALNA8 = 0xAA00,
|
||||
TYPE_ALNA9 = 0xAA55,
|
||||
TYPE_ALNA10 = 0xAAAA,
|
||||
TYPE_ALNA11 = 0xAAFF,
|
||||
TYPE_ALNA12 = 0xFF00,
|
||||
TYPE_ALNA13 = 0xFF55,
|
||||
TYPE_ALNA14 = 0xFFAA,
|
||||
TYPE_ALNA15 = 0xFFFF,
|
||||
};
|
||||
|
||||
|
||||
enum odm_rf_radio_path_e {
|
||||
ODM_RF_PATH_A = 0, /* Radio path A */
|
||||
ODM_RF_PATH_B = 1, /* Radio path B */
|
||||
ODM_RF_PATH_C = 2, /* Radio path C */
|
||||
ODM_RF_PATH_D = 3, /* Radio path D */
|
||||
ODM_RF_PATH_AB,
|
||||
ODM_RF_PATH_AC,
|
||||
ODM_RF_PATH_AD,
|
||||
ODM_RF_PATH_BC,
|
||||
ODM_RF_PATH_BD,
|
||||
ODM_RF_PATH_CD,
|
||||
ODM_RF_PATH_ABC,
|
||||
ODM_RF_PATH_ACD,
|
||||
ODM_RF_PATH_BCD,
|
||||
ODM_RF_PATH_ABCD,
|
||||
/* ODM_RF_PATH_MAX, */ /* Max RF number 90 support */
|
||||
};
|
||||
|
||||
enum odm_parameter_init_e {
|
||||
ODM_PRE_SETTING = 0,
|
||||
ODM_POST_SETTING = 1,
|
||||
};
|
||||
|
||||
#endif
|
||||
351
hal/phydm/phydm_precomp.h
Normal file
351
hal/phydm/phydm_precomp.h
Normal file
|
|
@ -0,0 +1,351 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ODM_PRECOMP_H__
|
||||
#define __ODM_PRECOMP_H__
|
||||
|
||||
#include "phydm_types.h"
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#include "Precomp.h" /* We need to include mp_precomp.h due to batch file setting. */
|
||||
#else
|
||||
#define TEST_FALG___ 1
|
||||
#endif
|
||||
|
||||
/* 2 Config Flags and Structs - defined by each ODM type */
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#include "../8192cd_cfg.h"
|
||||
#include "../odm_inc.h"
|
||||
|
||||
#include "../8192cd.h"
|
||||
#include "../8192cd_util.h"
|
||||
#ifdef _BIG_ENDIAN_
|
||||
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
|
||||
#else
|
||||
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
|
||||
#endif
|
||||
|
||||
#ifdef AP_BUILD_WORKAROUND
|
||||
#include "../8192cd_headers.h"
|
||||
#include "../8192cd_debug.h"
|
||||
#endif
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#define __PACK
|
||||
#define __WLAN_ATTRIB_PACK__
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#include "mp_precomp.h"
|
||||
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
|
||||
#define __PACK
|
||||
#define __WLAN_ATTRIB_PACK__
|
||||
#endif
|
||||
|
||||
/* 2 OutSrc Header Files */
|
||||
|
||||
#include "phydm.h"
|
||||
#include "phydm_hwconfig.h"
|
||||
#include "phydm_debug.h"
|
||||
#include "phydm_regdefine11ac.h"
|
||||
#include "phydm_regdefine11n.h"
|
||||
#include "phydm_interface.h"
|
||||
#include "phydm_reg.h"
|
||||
|
||||
#include "phydm_adc_sampling.h"
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
|
||||
void
|
||||
phy_set_tx_power_limit(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 *regulation,
|
||||
u8 *band,
|
||||
u8 *bandwidth,
|
||||
u8 *rate_section,
|
||||
u8 *rf_path,
|
||||
u8 *channel,
|
||||
u8 *power_limit
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
#define RTL8703B_SUPPORT 0
|
||||
#define RTL8188F_SUPPORT 0
|
||||
#define RTL8723D_SUPPORT 0
|
||||
#endif
|
||||
|
||||
#if RTL8188E_SUPPORT == 1
|
||||
#define RTL8188E_T_SUPPORT 1
|
||||
#ifdef CONFIG_SFW_SUPPORTED
|
||||
#define RTL8188E_S_SUPPORT 1
|
||||
#else
|
||||
#define RTL8188E_S_SUPPORT 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (RTL8188E_SUPPORT == 1)
|
||||
#include "rtl8188e/hal8188erateadaptive.h" /* for RA,Power training */
|
||||
#include "rtl8188e/halhwimg8188e_mac.h"
|
||||
#include "rtl8188e/halhwimg8188e_rf.h"
|
||||
#include "rtl8188e/halhwimg8188e_bb.h"
|
||||
#include "rtl8188e/halhwimg8188e_t_fw.h"
|
||||
#include "rtl8188e/halhwimg8188e_s_fw.h"
|
||||
#include "rtl8188e/phydm_regconfig8188e.h"
|
||||
#include "rtl8188e/phydm_rtl8188e.h"
|
||||
#include "rtl8188e/hal8188ereg.h"
|
||||
#include "rtl8188e/version_rtl8188e.h"
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8188e_hal.h"
|
||||
#include "rtl8188e/halphyrf_8188e_ce.h"
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#include "rtl8188e/halphyrf_8188e_win.h"
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#include "rtl8188e/halphyrf_8188e_ap.h"
|
||||
#endif
|
||||
#endif /* 88E END */
|
||||
|
||||
#if (RTL8192E_SUPPORT == 1)
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#include "rtl8192e/halphyrf_8192e_win.h" /*FOR_8192E_IQK*/
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#include "rtl8192e/halphyrf_8192e_ap.h" /*FOR_8192E_IQK*/
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8192e/halphyrf_8192e_ce.h" /*FOR_8192E_IQK*/
|
||||
#endif
|
||||
|
||||
#include "rtl8192e/phydm_rtl8192e.h" /* FOR_8192E_IQK */
|
||||
#include "rtl8192e/version_rtl8192e.h"
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
|
||||
#include "rtl8192e/halhwimg8192e_bb.h"
|
||||
#include "rtl8192e/halhwimg8192e_mac.h"
|
||||
#include "rtl8192e/halhwimg8192e_rf.h"
|
||||
#include "rtl8192e/phydm_regconfig8192e.h"
|
||||
#include "rtl8192e/halhwimg8192e_fw.h"
|
||||
#include "rtl8192e/hal8192ereg.h"
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8192e_hal.h"
|
||||
#endif
|
||||
#endif /* 92E END */
|
||||
|
||||
#if (RTL8812A_SUPPORT == 1)
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#include "rtl8812a/halphyrf_8812a_win.h"
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#include "rtl8812a/halphyrf_8812a_ap.h"
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8812a/halphyrf_8812a_ce.h"
|
||||
#endif
|
||||
|
||||
/* #include "rtl8812a/HalPhyRf_8812A.h" */ /* FOR_8812_IQK */
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
|
||||
#include "rtl8812a/halhwimg8812a_bb.h"
|
||||
#include "rtl8812a/halhwimg8812a_mac.h"
|
||||
#include "rtl8812a/halhwimg8812a_rf.h"
|
||||
#include "rtl8812a/phydm_regconfig8812a.h"
|
||||
#include "rtl8812a/halhwimg8812a_fw.h"
|
||||
#include "rtl8812a/phydm_rtl8812a.h"
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8812a_hal.h"
|
||||
#endif
|
||||
#include "rtl8812a/version_rtl8812a.h"
|
||||
|
||||
#endif /* 8812 END */
|
||||
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
|
||||
#include "rtl8814a/halhwimg8814a_mac.h"
|
||||
#include "rtl8814a/halhwimg8814a_rf.h"
|
||||
#include "rtl8814a/halhwimg8814a_bb.h"
|
||||
#include "rtl8814a/version_rtl8814a.h"
|
||||
#include "rtl8814a/phydm_rtl8814a.h"
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
|
||||
#include "rtl8814a/halhwimg8814a_fw.h"
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#include "rtl8814a/halphyrf_8814a_win.h"
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8814a/halphyrf_8814a_ce.h"
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#include "rtl8814a/halphyrf_8814a_ap.h"
|
||||
#endif
|
||||
#include "rtl8814a/phydm_regconfig8814a.h"
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8814a_hal.h"
|
||||
#include "rtl8814a/phydm_iqk_8814a.h"
|
||||
#endif
|
||||
#endif /* 8814 END */
|
||||
|
||||
#if (RTL8881A_SUPPORT == 1)/* FOR_8881_IQK */
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#include "rtl8821a/phydm_iqk_8821a_win.h"
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8821a/phydm_iqk_8821a_ce.h"
|
||||
#else
|
||||
#include "rtl8821a/phydm_iqk_8821a_ap.h"
|
||||
#endif
|
||||
/* #include "rtl8881a/HalHWImg8881A_BB.h" */
|
||||
/* #include "rtl8881a/HalHWImg8881A_MAC.h" */
|
||||
/* #include "rtl8881a/HalHWImg8881A_RF.h" */
|
||||
/* #include "rtl8881a/odm_RegConfig8881A.h" */
|
||||
#endif
|
||||
|
||||
#if (RTL8723B_SUPPORT == 1)
|
||||
#include "rtl8723b/halhwimg8723b_mac.h"
|
||||
#include "rtl8723b/halhwimg8723b_rf.h"
|
||||
#include "rtl8723b/halhwimg8723b_bb.h"
|
||||
#include "rtl8723b/halhwimg8723b_fw.h"
|
||||
#include "rtl8723b/phydm_regconfig8723b.h"
|
||||
#include "rtl8723b/phydm_rtl8723b.h"
|
||||
#include "rtl8723b/hal8723breg.h"
|
||||
#include "rtl8723b/version_rtl8723b.h"
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#include "rtl8723b/halphyrf_8723b_win.h"
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8723b/halphyrf_8723b_ce.h"
|
||||
#include "rtl8723b/halhwimg8723b_mp.h"
|
||||
#include "rtl8723b_hal.h"
|
||||
#else
|
||||
#include "rtl8723b/halphyrf_8723b_ap.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (RTL8821A_SUPPORT == 1)
|
||||
#include "rtl8821a/halhwimg8821a_mac.h"
|
||||
#include "rtl8821a/halhwimg8821a_rf.h"
|
||||
#include "rtl8821a/halhwimg8821a_bb.h"
|
||||
#include "rtl8821a/halhwimg8821a_fw.h"
|
||||
#include "rtl8821a/phydm_regconfig8821a.h"
|
||||
#include "rtl8821a/phydm_rtl8821a.h"
|
||||
#include "rtl8821a/version_rtl8821a.h"
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#include "rtl8821a/halphyrf_8821a_win.h"
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8821a/halphyrf_8821a_ce.h"
|
||||
#include "rtl8821a/phydm_iqk_8821a_ce.h"/*for IQK*/
|
||||
#include "rtl8812a/halphyrf_8812a_ce.h"/*for IQK,LCK,Power-tracking*/
|
||||
#include "rtl8812a_hal.h"
|
||||
#else
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
#include "rtl8822b/halhwimg8822b_mac.h"
|
||||
#include "rtl8822b/halhwimg8822b_rf.h"
|
||||
#include "rtl8822b/halhwimg8822b_bb.h"
|
||||
#include "rtl8822b/halhwimg8822b_fw.h"
|
||||
#include "rtl8822b/phydm_regconfig8822b.h"
|
||||
#include "rtl8822b/halphyrf_8822b.h"
|
||||
#include "rtl8822b/phydm_rtl8822b.h"
|
||||
#include "rtl8822b/phydm_hal_api8822b.h"
|
||||
#include "rtl8822b/version_rtl8822b.h"
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include <hal_data.h> /* struct HAL_DATA_TYPE */
|
||||
#include <rtl8822b_hal.h> /* RX_SMOOTH_FACTOR, reg definition and etc.*/
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if (RTL8703B_SUPPORT == 1)
|
||||
#include "rtl8703b/phydm_regconfig8703b.h"
|
||||
#include "rtl8703b/halhwimg8703b_mac.h"
|
||||
#include "rtl8703b/halhwimg8703b_rf.h"
|
||||
#include "rtl8703b/halhwimg8703b_bb.h"
|
||||
#include "rtl8703b/halhwimg8703b_fw.h"
|
||||
#include "rtl8703b/halphyrf_8703b.h"
|
||||
#include "rtl8703b/version_rtl8703b.h"
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8703b_hal.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (RTL8188F_SUPPORT == 1)
|
||||
#include "rtl8188f/halhwimg8188f_mac.h"
|
||||
#include "rtl8188f/halhwimg8188f_rf.h"
|
||||
#include "rtl8188f/halhwimg8188f_bb.h"
|
||||
#include "rtl8188f/halhwimg8188f_fw.h"
|
||||
#include "rtl8188f/hal8188freg.h"
|
||||
#include "rtl8188f/phydm_rtl8188f.h"
|
||||
#include "rtl8188f/phydm_regconfig8188f.h"
|
||||
#include "rtl8188f/halphyrf_8188f.h" /* for IQK,LCK,Power-tracking */
|
||||
#include "rtl8188f/version_rtl8188f.h"
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8188f_hal.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (RTL8723D_SUPPORT == 1)
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
|
||||
|
||||
#include "rtl8723d/halhwimg8723d_bb.h"
|
||||
#include "rtl8723d/halhwimg8723d_mac.h"
|
||||
#include "rtl8723d/halhwimg8723d_rf.h"
|
||||
#include "rtl8723d/phydm_regconfig8723d.h"
|
||||
#include "rtl8723d/halhwimg8723d_fw.h"
|
||||
#include "rtl8723d/hal8723dreg.h"
|
||||
#include "rtl8723d/phydm_rtl8723d.h"
|
||||
#include "rtl8723d/halphyrf_8723d.h"
|
||||
#include "rtl8723d/version_rtl8723d.h"
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8723d_hal.h"
|
||||
#endif
|
||||
#endif /* 8723D End */
|
||||
|
||||
#if (RTL8197F_SUPPORT == 1)
|
||||
#include "rtl8197f/halhwimg8197f_mac.h"
|
||||
#include "rtl8197f/halhwimg8197f_rf.h"
|
||||
#include "rtl8197f/halhwimg8197f_bb.h"
|
||||
#include "rtl8197f/phydm_hal_api8197f.h"
|
||||
#include "rtl8197f/version_rtl8197f.h"
|
||||
#include "rtl8197f/phydm_rtl8197f.h"
|
||||
#include "rtl8197f/phydm_regconfig8197f.h"
|
||||
#include "rtl8197f/halphyrf_8197f.h"
|
||||
#include "rtl8197f/phydm_iqk_8197f.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8821C_SUPPORT == 1)
|
||||
#include "rtl8821c/phydm_hal_api8821c.h"
|
||||
#include "rtl8821c/halhwimg8821c_testchip_mac.h"
|
||||
#include "rtl8821c/halhwimg8821c_testchip_rf.h"
|
||||
#include "rtl8821c/halhwimg8821c_testchip_bb.h"
|
||||
#include "rtl8821c/halhwimg8821c_mac.h"
|
||||
#include "rtl8821c/halhwimg8821c_rf.h"
|
||||
#include "rtl8821c/halhwimg8821c_bb.h"
|
||||
#include "rtl8821c/halhwimg8821c_fw.h"
|
||||
#include "rtl8821c/phydm_regconfig8821c.h"
|
||||
#include "rtl8821c/halphyrf_8821c.h"
|
||||
#include "rtl8821c/version_rtl8821c.h"
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include "rtl8821c_hal.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* __ODM_PRECOMP_H__ */
|
||||
3429
hal/phydm/phydm_rainfo.c
Normal file
3429
hal/phydm/phydm_rainfo.c
Normal file
File diff suppressed because it is too large
Load diff
585
hal/phydm/phydm_rainfo.h
Normal file
585
hal/phydm/phydm_rainfo.h
Normal file
|
|
@ -0,0 +1,585 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __PHYDMRAINFO_H__
|
||||
#define __PHYDMRAINFO_H__
|
||||
|
||||
/*#define RAINFO_VERSION "2.0" //2014.11.04*/
|
||||
/*#define RAINFO_VERSION "3.0" //2015.01.13 Dino*/
|
||||
/*#define RAINFO_VERSION "3.1" //2015.01.14 Dino*/
|
||||
/*#define RAINFO_VERSION "3.3" 2015.07.29 YuChen*/
|
||||
/*#define RAINFO_VERSION "3.4"*/ /*2015.12.15 Stanley*/
|
||||
/*#define RAINFO_VERSION "4.0"*/ /*2016.03.24 Dino, Add more RA mask state and Phydm-lize partial ra mask function */
|
||||
/*#define RAINFO_VERSION "4.1"*/ /*2016.04.20 Dino, Add new function to adjust PCR RA threshold */
|
||||
/*#define RAINFO_VERSION "4.2"*/ /*2016.05.17 Dino, Add H2C debug cmd */
|
||||
#define RAINFO_VERSION "4.3" /*2016.07.11 Dino, Fix RA hang in CCK 1M problem */
|
||||
|
||||
#define FORCED_UPDATE_RAMASK_PERIOD 5
|
||||
|
||||
#define H2C_0X42_LENGTH 5
|
||||
#define H2C_MAX_LENGTH 7
|
||||
|
||||
#define RA_FLOOR_UP_GAP 3
|
||||
#define RA_FLOOR_TABLE_SIZE 7
|
||||
|
||||
#define ACTIVE_TP_THRESHOLD 150
|
||||
#define RA_RETRY_DESCEND_NUM 2
|
||||
#define RA_RETRY_LIMIT_LOW 4
|
||||
#define RA_RETRY_LIMIT_HIGH 32
|
||||
|
||||
#define RAINFO_BE_RX_STATE BIT(0) /* 1:RX */ /* ULDL */
|
||||
#define RAINFO_STBC_STATE BIT(1)
|
||||
/* #define RAINFO_LDPC_STATE BIT2 */
|
||||
#define RAINFO_NOISY_STATE BIT(2) /* set by Noisy_Detection */
|
||||
#define RAINFO_SHURTCUT_STATE BIT(3)
|
||||
#define RAINFO_SHURTCUT_FLAG BIT(4)
|
||||
#define RAINFO_INIT_RSSI_RATE_STATE BIT(5)
|
||||
#define RAINFO_BF_STATE BIT(6)
|
||||
#define RAINFO_BE_TX_STATE BIT(7) /* 1:TX */
|
||||
|
||||
#define RA_MASK_CCK 0xf
|
||||
#define RA_MASK_OFDM 0xff0
|
||||
#define RA_MASK_HT1SS 0xff000
|
||||
#define RA_MASK_HT2SS 0xff00000
|
||||
/*#define RA_MASK_MCS3SS */
|
||||
#define RA_MASK_HT4SS 0xff0
|
||||
#define RA_MASK_VHT1SS 0x3ff000
|
||||
#define RA_MASK_VHT2SS 0xffc00000
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#define RA_FIRST_MACID 1
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define RA_FIRST_MACID 0
|
||||
#define WIN_DEFAULT_PORT_MACID 0
|
||||
#define WIN_BT_PORT_MACID 2
|
||||
#else /*if (DM_ODM_SUPPORT_TYPE == ODM_CE)*/
|
||||
#define RA_FIRST_MACID 0
|
||||
#endif
|
||||
|
||||
#define ap_init_rate_adaptive_state odm_rate_adaptive_state_ap_init
|
||||
|
||||
#if (RA_MASK_PHYDMLIZE_CE || RA_MASK_PHYDMLIZE_AP || RA_MASK_PHYDMLIZE_WIN)
|
||||
#define DM_RATR_STA_INIT 0
|
||||
#define DM_RATR_STA_HIGH 1
|
||||
#define DM_RATR_STA_MIDDLE 2
|
||||
#define DM_RATR_STA_LOW 3
|
||||
#define DM_RATR_STA_ULTRA_LOW 4
|
||||
#endif
|
||||
|
||||
enum phydm_ra_arfr_num_e {
|
||||
ARFR_0_RATE_ID = 0x9,
|
||||
ARFR_1_RATE_ID = 0xa,
|
||||
ARFR_2_RATE_ID = 0xb,
|
||||
ARFR_3_RATE_ID = 0xc,
|
||||
ARFR_4_RATE_ID = 0xd,
|
||||
ARFR_5_RATE_ID = 0xe
|
||||
};
|
||||
|
||||
enum phydm_ra_dbg_para_e {
|
||||
RADBG_PCR_TH_OFFSET = 0,
|
||||
RADBG_RTY_PENALTY = 1,
|
||||
RADBG_N_HIGH = 2,
|
||||
RADBG_N_LOW = 3,
|
||||
RADBG_TRATE_UP_TABLE = 4,
|
||||
RADBG_TRATE_DOWN_TABLE = 5,
|
||||
RADBG_TRYING_NECESSARY = 6,
|
||||
RADBG_TDROPING_NECESSARY = 7,
|
||||
RADBG_RATE_UP_RTY_RATIO = 8,
|
||||
RADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */
|
||||
|
||||
RADBG_DEBUG_MONITOR1 = 0xc,
|
||||
RADBG_DEBUG_MONITOR2 = 0xd,
|
||||
RADBG_DEBUG_MONITOR3 = 0xe,
|
||||
RADBG_DEBUG_MONITOR4 = 0xf,
|
||||
RADBG_DEBUG_MONITOR5 = 0x10,
|
||||
NUM_RA_PARA
|
||||
};
|
||||
|
||||
enum phydm_wireless_mode_e {
|
||||
|
||||
PHYDM_WIRELESS_MODE_UNKNOWN = 0x00,
|
||||
PHYDM_WIRELESS_MODE_A = 0x01,
|
||||
PHYDM_WIRELESS_MODE_B = 0x02,
|
||||
PHYDM_WIRELESS_MODE_G = 0x04,
|
||||
PHYDM_WIRELESS_MODE_AUTO = 0x08,
|
||||
PHYDM_WIRELESS_MODE_N_24G = 0x10,
|
||||
PHYDM_WIRELESS_MODE_N_5G = 0x20,
|
||||
PHYDM_WIRELESS_MODE_AC_5G = 0x40,
|
||||
PHYDM_WIRELESS_MODE_AC_24G = 0x80,
|
||||
PHYDM_WIRELESS_MODE_AC_ONLY = 0x100,
|
||||
PHYDM_WIRELESS_MODE_MAX = 0x800,
|
||||
PHYDM_WIRELESS_MODE_ALL = 0xFFFF
|
||||
};
|
||||
|
||||
enum phydm_rateid_idx_e {
|
||||
|
||||
PHYDM_BGN_40M_2SS = 0,
|
||||
PHYDM_BGN_40M_1SS = 1,
|
||||
PHYDM_BGN_20M_2SS = 2,
|
||||
PHYDM_BGN_20M_1SS = 3,
|
||||
PHYDM_GN_N2SS = 4,
|
||||
PHYDM_GN_N1SS = 5,
|
||||
PHYDM_BG = 6,
|
||||
PHYDM_G = 7,
|
||||
PHYDM_B_20M = 8,
|
||||
PHYDM_ARFR0_AC_2SS = 9,
|
||||
PHYDM_ARFR1_AC_1SS = 10,
|
||||
PHYDM_ARFR2_AC_2G_1SS = 11,
|
||||
PHYDM_ARFR3_AC_2G_2SS = 12,
|
||||
PHYDM_ARFR4_AC_3SS = 13,
|
||||
PHYDM_ARFR5_N_3SS = 14
|
||||
};
|
||||
|
||||
enum phydm_rf_type_def_e {
|
||||
PHYDM_RF_1T1R = 0,
|
||||
PHYDM_RF_1T2R,
|
||||
PHYDM_RF_2T2R,
|
||||
PHYDM_RF_2T2R_GREEN,
|
||||
PHYDM_RF_2T3R,
|
||||
PHYDM_RF_2T4R,
|
||||
PHYDM_RF_3T3R,
|
||||
PHYDM_RF_3T4R,
|
||||
PHYDM_RF_4T4R,
|
||||
PHYDM_RF_MAX_TYPE
|
||||
};
|
||||
|
||||
enum phydm_bw_e {
|
||||
PHYDM_BW_20 = 0,
|
||||
PHYDM_BW_40,
|
||||
PHYDM_BW_80,
|
||||
PHYDM_BW_80_80,
|
||||
PHYDM_BW_160,
|
||||
PHYDM_BW_10,
|
||||
PHYDM_BW_5
|
||||
};
|
||||
|
||||
|
||||
#if (RATE_ADAPTIVE_SUPPORT == 1)/* 88E RA */
|
||||
struct _odm_ra_info_ {
|
||||
u8 rate_id;
|
||||
u32 rate_mask;
|
||||
u32 ra_use_rate;
|
||||
u8 rate_sgi;
|
||||
u8 rssi_sta_ra;
|
||||
u8 pre_rssi_sta_ra;
|
||||
u8 sgi_enable;
|
||||
u8 decision_rate;
|
||||
u8 pre_rate;
|
||||
u8 highest_rate;
|
||||
u8 lowest_rate;
|
||||
u32 nsc_up;
|
||||
u32 nsc_down;
|
||||
u16 RTY[5];
|
||||
u32 TOTAL;
|
||||
u16 DROP;
|
||||
u8 active;
|
||||
u16 rpt_time;
|
||||
u8 ra_waiting_counter;
|
||||
u8 ra_pending_counter;
|
||||
u8 ra_drop_after_down;
|
||||
#if 1 /* POWER_TRAINING_ACTIVE == 1 */ /* For compile pass only~! */
|
||||
u8 pt_active; /* on or off */
|
||||
u8 pt_try_state; /* 0 trying state, 1 for decision state */
|
||||
u8 pt_stage; /* 0~6 */
|
||||
u8 pt_stop_count; /* Stop PT counter */
|
||||
u8 pt_pre_rate; /* if rate change do PT */
|
||||
u8 pt_pre_rssi; /* if RSSI change 5% do PT */
|
||||
u8 pt_mode_ss; /* decide whitch rate should do PT */
|
||||
u8 ra_stage; /* StageRA, decide how many times RA will be done between PT */
|
||||
u8 pt_smooth_factor;
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
|
||||
u8 rate_down_counter;
|
||||
u8 rate_up_counter;
|
||||
u8 rate_direction;
|
||||
u8 bounding_type;
|
||||
u8 bounding_counter;
|
||||
u8 bounding_learning_time;
|
||||
u8 rate_down_start_time;
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
struct _rate_adaptive_table_ {
|
||||
u8 firstconnect;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
bool PT_collision_pre;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_RA_DBG_CMD))
|
||||
bool is_ra_dbg_init;
|
||||
|
||||
u8 RTY_P[ODM_NUM_RATE_IDX];
|
||||
u8 RTY_P_default[ODM_NUM_RATE_IDX];
|
||||
bool RTY_P_modify_note[ODM_NUM_RATE_IDX];
|
||||
|
||||
u8 RATE_UP_RTY_RATIO[ODM_NUM_RATE_IDX];
|
||||
u8 RATE_UP_RTY_RATIO_default[ODM_NUM_RATE_IDX];
|
||||
bool RATE_UP_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX];
|
||||
|
||||
u8 RATE_DOWN_RTY_RATIO[ODM_NUM_RATE_IDX];
|
||||
u8 RATE_DOWN_RTY_RATIO_default[ODM_NUM_RATE_IDX];
|
||||
bool RATE_DOWN_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX];
|
||||
|
||||
bool ra_para_feedback_req;
|
||||
|
||||
u8 para_idx;
|
||||
u8 rate_idx;
|
||||
u8 value;
|
||||
u16 value_16;
|
||||
u8 rate_length;
|
||||
#endif
|
||||
u8 link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u8 highest_client_tx_order;
|
||||
u16 highest_client_tx_rate_order;
|
||||
u8 power_tracking_flag;
|
||||
u8 RA_threshold_offset;
|
||||
u8 RA_offset_direction;
|
||||
u8 force_update_ra_mask_count;
|
||||
|
||||
#if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT))
|
||||
u8 per_rate_retrylimit_20M[ODM_NUM_RATE_IDX];
|
||||
u8 per_rate_retrylimit_40M[ODM_NUM_RATE_IDX];
|
||||
u8 retry_descend_num;
|
||||
u8 retrylimit_low;
|
||||
u8 retrylimit_high;
|
||||
#endif
|
||||
|
||||
|
||||
};
|
||||
|
||||
struct _ODM_RATE_ADAPTIVE {
|
||||
u8 type; /* dm_type_by_fw/dm_type_by_driver */
|
||||
u8 high_rssi_thresh; /* if RSSI > high_rssi_thresh => ratr_state is DM_RATR_STA_HIGH */
|
||||
u8 low_rssi_thresh; /* if RSSI <= low_rssi_thresh => ratr_state is DM_RATR_STA_LOW */
|
||||
u8 ratr_state; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
u8 ldpc_thres; /* if RSSI > ldpc_thres => switch from LPDC to BCC */
|
||||
bool is_lower_rts_rate;
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
u8 rts_thres;
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
bool is_use_ldpc;
|
||||
#else
|
||||
u8 ultra_low_rssi_thresh;
|
||||
u32 last_ratr; /* RATR Register Content */
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
void
|
||||
phydm_h2C_debug(
|
||||
void *p_dm_void,
|
||||
u32 *const dm_value,
|
||||
u32 *_used,
|
||||
char *output,
|
||||
u32 *_out_len
|
||||
);
|
||||
|
||||
#if (defined(CONFIG_RA_DBG_CMD))
|
||||
|
||||
void
|
||||
odm_RA_debug(
|
||||
void *p_dm_void,
|
||||
u32 *const dm_value
|
||||
);
|
||||
|
||||
void
|
||||
odm_ra_para_adjust_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
#else
|
||||
|
||||
void
|
||||
phydm_RA_debug_PCR(
|
||||
void *p_dm_void,
|
||||
u32 *const dm_value,
|
||||
u32 *_used,
|
||||
char *output,
|
||||
u32 *_out_len
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
void
|
||||
odm_c2h_ra_para_report_handler(
|
||||
void *p_dm_void,
|
||||
u8 *cmd_buf,
|
||||
u8 cmd_len
|
||||
);
|
||||
|
||||
void
|
||||
odm_ra_para_adjust(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_ra_dynamic_retry_count(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_ra_dynamic_retry_limit(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_ra_dynamic_rate_id_on_assoc(
|
||||
void *p_dm_void,
|
||||
u8 wireless_mode,
|
||||
u8 init_rate_id
|
||||
);
|
||||
|
||||
void
|
||||
phydm_print_rate(
|
||||
void *p_dm_void,
|
||||
u8 rate,
|
||||
u32 dbg_component
|
||||
);
|
||||
|
||||
void
|
||||
phydm_c2h_ra_report_handler(
|
||||
void *p_dm_void,
|
||||
u8 *cmd_buf,
|
||||
u8 cmd_len
|
||||
);
|
||||
|
||||
u8
|
||||
phydm_rate_order_compute(
|
||||
void *p_dm_void,
|
||||
u8 rate_idx
|
||||
);
|
||||
|
||||
void
|
||||
phydm_ra_info_watchdog(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_ra_info_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_rssi_monitor_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_modify_RA_PCR_threshold(
|
||||
void *p_dm_void,
|
||||
u8 RA_offset_direction,
|
||||
u8 RA_threshold_offset
|
||||
);
|
||||
|
||||
void
|
||||
odm_rssi_monitor_check(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_init_ra_info(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
u8
|
||||
phydm_vht_en_mapping(
|
||||
void *p_dm_void,
|
||||
u32 wireless_mode
|
||||
);
|
||||
|
||||
u8
|
||||
phydm_rate_id_mapping(
|
||||
void *p_dm_void,
|
||||
u32 wireless_mode,
|
||||
u8 rf_type,
|
||||
u8 bw
|
||||
);
|
||||
|
||||
void
|
||||
phydm_update_hal_ra_mask(
|
||||
void *p_dm_void,
|
||||
u32 wireless_mode,
|
||||
u8 rf_type,
|
||||
u8 BW,
|
||||
u8 mimo_ps_enable,
|
||||
u8 disable_cck_rate,
|
||||
u32 *ratr_bitmap_msb_in,
|
||||
u32 *ratr_bitmap_in,
|
||||
u8 tx_rate_level
|
||||
);
|
||||
|
||||
void
|
||||
odm_rate_adaptive_mask_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_refresh_rate_adaptive_mask(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_refresh_rate_adaptive_mask_mp(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_refresh_rate_adaptive_mask_ce(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_refresh_rate_adaptive_mask_apadsl(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
u8
|
||||
phydm_RA_level_decision(
|
||||
void *p_dm_void,
|
||||
u32 rssi,
|
||||
u8 ratr_state
|
||||
);
|
||||
|
||||
bool
|
||||
odm_ra_state_check(
|
||||
void *p_dm_void,
|
||||
s32 RSSI,
|
||||
bool is_force_update,
|
||||
u8 *p_ra_tr_state
|
||||
);
|
||||
|
||||
void
|
||||
odm_refresh_basic_rate_mask(
|
||||
void *p_dm_void
|
||||
);
|
||||
void
|
||||
odm_ra_post_action_on_assoc(
|
||||
void *p_dm_odm
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
|
||||
u8
|
||||
odm_find_rts_rate(
|
||||
void *p_dm_void,
|
||||
u8 tx_rate,
|
||||
bool is_erp_protect
|
||||
);
|
||||
|
||||
void
|
||||
odm_update_noisy_state(
|
||||
void *p_dm_void,
|
||||
bool is_noisy_state_from_c2h
|
||||
);
|
||||
|
||||
void
|
||||
phydm_update_pwr_track(
|
||||
void *p_dm_void,
|
||||
u8 rate
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
|
||||
s32
|
||||
phydm_find_minimum_rssi(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
struct _ADAPTER *p_adapter,
|
||||
OUT bool *p_is_link_temp
|
||||
);
|
||||
|
||||
void
|
||||
odm_update_init_rate_work_item_callback(
|
||||
void *p_context
|
||||
);
|
||||
|
||||
void
|
||||
odm_rssi_dump_to_register(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_refresh_ldpc_rts_mp(
|
||||
struct _ADAPTER *p_adapter,
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 m_mac_id,
|
||||
u8 iot_peer,
|
||||
s32 undecorated_smoothed_pwdb
|
||||
);
|
||||
|
||||
#if 0
|
||||
void
|
||||
odm_dynamic_arfb_select(
|
||||
void *p_dm_void,
|
||||
u8 rate,
|
||||
bool collision_state
|
||||
);
|
||||
#endif
|
||||
|
||||
void
|
||||
odm_rate_adaptive_state_ap_init(
|
||||
void *PADAPTER_VOID,
|
||||
struct sta_info *p_entry
|
||||
);
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
|
||||
static void
|
||||
find_minimum_rssi(
|
||||
struct _ADAPTER *p_adapter
|
||||
);
|
||||
|
||||
u64
|
||||
phydm_get_rate_bitmap_ex(
|
||||
void *p_dm_void,
|
||||
u32 macid,
|
||||
u64 ra_mask,
|
||||
u8 rssi_level,
|
||||
u64 *dm_ra_mask,
|
||||
u8 *dm_rte_id
|
||||
);
|
||||
u32
|
||||
odm_get_rate_bitmap(
|
||||
void *p_dm_void,
|
||||
u32 macid,
|
||||
u32 ra_mask,
|
||||
u8 rssi_level
|
||||
);
|
||||
|
||||
void phydm_ra_rssi_rpt_wk(void *p_context);
|
||||
#endif/*#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)*/
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
/*
|
||||
void
|
||||
phydm_gen_ramask_h2c_AP(
|
||||
void *p_dm_void,
|
||||
struct rtl8192cd_priv *priv,
|
||||
struct sta_info *p_entry,
|
||||
u8 rssi_level
|
||||
);
|
||||
*/
|
||||
#endif/*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/
|
||||
|
||||
#endif /*#ifndef __ODMRAINFO_H__*/
|
||||
214
hal/phydm/phydm_reg.h
Normal file
214
hal/phydm/phydm_reg.h
Normal file
|
|
@ -0,0 +1,214 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
/* ************************************************************
|
||||
* File Name: odm_reg.h
|
||||
*
|
||||
* Description:
|
||||
*
|
||||
* This file is for general register definition.
|
||||
*
|
||||
*
|
||||
* ************************************************************ */
|
||||
#ifndef __HAL_ODM_REG_H__
|
||||
#define __HAL_ODM_REG_H__
|
||||
|
||||
/*
|
||||
* Register Definition
|
||||
* */
|
||||
|
||||
/* MAC REG */
|
||||
#define ODM_BB_RESET 0x002
|
||||
#define ODM_DUMMY 0x4fe
|
||||
#define RF_T_METER_OLD 0x24
|
||||
#define RF_T_METER_NEW 0x42
|
||||
|
||||
#define ODM_EDCA_VO_PARAM 0x500
|
||||
#define ODM_EDCA_VI_PARAM 0x504
|
||||
#define ODM_EDCA_BE_PARAM 0x508
|
||||
#define ODM_EDCA_BK_PARAM 0x50C
|
||||
#define ODM_TXPAUSE 0x522
|
||||
|
||||
/* LTE_COEX */
|
||||
#define REG_LTECOEX_CTRL 0x07C0
|
||||
#define REG_LTECOEX_WRITE_DATA 0x07C4
|
||||
#define REG_LTECOEX_READ_DATA 0x07C8
|
||||
#define REG_LTECOEX_PATH_CONTROL 0x70
|
||||
|
||||
/* BB REG */
|
||||
#define ODM_FPGA_PHY0_PAGE8 0x800
|
||||
#define ODM_PSD_SETTING 0x808
|
||||
#define ODM_AFE_SETTING 0x818
|
||||
#define ODM_TXAGC_B_6_18 0x830
|
||||
#define ODM_TXAGC_B_24_54 0x834
|
||||
#define ODM_TXAGC_B_MCS32_5 0x838
|
||||
#define ODM_TXAGC_B_MCS0_MCS3 0x83c
|
||||
#define ODM_TXAGC_B_MCS4_MCS7 0x848
|
||||
#define ODM_TXAGC_B_MCS8_MCS11 0x84c
|
||||
#define ODM_ANALOG_REGISTER 0x85c
|
||||
#define ODM_RF_INTERFACE_OUTPUT 0x860
|
||||
#define ODM_TXAGC_B_MCS12_MCS15 0x868
|
||||
#define ODM_TXAGC_B_11_A_2_11 0x86c
|
||||
#define ODM_AD_DA_LSB_MASK 0x874
|
||||
#define ODM_ENABLE_3_WIRE 0x88c
|
||||
#define ODM_PSD_REPORT 0x8b4
|
||||
#define ODM_R_ANT_SELECT 0x90c
|
||||
#define ODM_CCK_ANT_SELECT 0xa07
|
||||
#define ODM_CCK_PD_THRESH 0xa0a
|
||||
#define ODM_CCK_RF_REG1 0xa11
|
||||
#define ODM_CCK_MATCH_FILTER 0xa20
|
||||
#define ODM_CCK_RAKE_MAC 0xa2e
|
||||
#define ODM_CCK_CNT_RESET 0xa2d
|
||||
#define ODM_CCK_TX_DIVERSITY 0xa2f
|
||||
#define ODM_CCK_FA_CNT_MSB 0xa5b
|
||||
#define ODM_CCK_FA_CNT_LSB 0xa5c
|
||||
#define ODM_CCK_NEW_FUNCTION 0xa75
|
||||
#define ODM_OFDM_PHY0_PAGE_C 0xc00
|
||||
#define ODM_OFDM_RX_ANT 0xc04
|
||||
#define ODM_R_A_RXIQI 0xc14
|
||||
#define ODM_R_A_AGC_CORE1 0xc50
|
||||
#define ODM_R_A_AGC_CORE2 0xc54
|
||||
#define ODM_R_B_AGC_CORE1 0xc58
|
||||
#define ODM_R_AGC_PAR 0xc70
|
||||
#define ODM_R_HTSTF_AGC_PAR 0xc7c
|
||||
#define ODM_TX_PWR_TRAINING_A 0xc90
|
||||
#define ODM_TX_PWR_TRAINING_B 0xc98
|
||||
#define ODM_OFDM_FA_CNT1 0xcf0
|
||||
#define ODM_OFDM_PHY0_PAGE_D 0xd00
|
||||
#define ODM_OFDM_FA_CNT2 0xda0
|
||||
#define ODM_OFDM_FA_CNT3 0xda4
|
||||
#define ODM_OFDM_FA_CNT4 0xda8
|
||||
#define ODM_TXAGC_A_6_18 0xe00
|
||||
#define ODM_TXAGC_A_24_54 0xe04
|
||||
#define ODM_TXAGC_A_1_MCS32 0xe08
|
||||
#define ODM_TXAGC_A_MCS0_MCS3 0xe10
|
||||
#define ODM_TXAGC_A_MCS4_MCS7 0xe14
|
||||
#define ODM_TXAGC_A_MCS8_MCS11 0xe18
|
||||
#define ODM_TXAGC_A_MCS12_MCS15 0xe1c
|
||||
|
||||
/* RF REG */
|
||||
#define ODM_GAIN_SETTING 0x00
|
||||
#define ODM_CHANNEL 0x18
|
||||
#define ODM_RF_T_METER 0x24
|
||||
#define ODM_RF_T_METER_92D 0x42
|
||||
#define ODM_RF_T_METER_88E 0x42
|
||||
#define ODM_RF_T_METER_92E 0x42
|
||||
#define ODM_RF_T_METER_8812 0x42
|
||||
#define REG_RF_TX_GAIN_OFFSET 0x55
|
||||
|
||||
/* ant Detect Reg */
|
||||
#define ODM_DPDT 0x300
|
||||
|
||||
/* PSD Init */
|
||||
#define ODM_PSDREG 0x808
|
||||
|
||||
/* 92D path Div */
|
||||
#define PATHDIV_REG 0xB30
|
||||
#define PATHDIV_TRI 0xBA0
|
||||
|
||||
|
||||
/*
|
||||
* Bitmap Definition
|
||||
* */
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
/* TX AGC */
|
||||
#define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR 0xc20
|
||||
#define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR 0xc24
|
||||
#define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR 0xc28
|
||||
#define REG_TX_AGC_A_MCS3_MCS0_JAGUAR 0xc2c
|
||||
#define REG_TX_AGC_A_MCS7_MCS4_JAGUAR 0xc30
|
||||
#define REG_TX_AGC_A_MCS11_MCS8_JAGUAR 0xc34
|
||||
#define REG_TX_AGC_A_MCS15_MCS12_JAGUAR 0xc38
|
||||
#define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0xc3c
|
||||
#define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0xc40
|
||||
#define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0xc44
|
||||
#define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0xc48
|
||||
#define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0xc4c
|
||||
#if defined(CONFIG_WLAN_HAL_8814AE)
|
||||
#define REG_TX_AGC_A_MCS19_MCS16_JAGUAR 0xcd8
|
||||
#define REG_TX_AGC_A_MCS23_MCS20_JAGUAR 0xcdc
|
||||
#define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0xce0
|
||||
#define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0xce4
|
||||
#define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0xce8
|
||||
#endif
|
||||
#define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR 0xe20
|
||||
#define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR 0xe24
|
||||
#define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR 0xe28
|
||||
#define REG_TX_AGC_B_MCS3_MCS0_JAGUAR 0xe2c
|
||||
#define REG_TX_AGC_B_MCS7_MCS4_JAGUAR 0xe30
|
||||
#define REG_TX_AGC_B_MCS11_MCS8_JAGUAR 0xe34
|
||||
#define REG_TX_AGC_B_MCS15_MCS12_JAGUAR 0xe38
|
||||
#define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0xe3c
|
||||
#define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0xe40
|
||||
#define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0xe44
|
||||
#define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0xe48
|
||||
#define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0xe4c
|
||||
#if defined(CONFIG_WLAN_HAL_8814AE)
|
||||
#define REG_TX_AGC_B_MCS19_MCS16_JAGUAR 0xed8
|
||||
#define REG_TX_AGC_B_MCS23_MCS20_JAGUAR 0xedc
|
||||
#define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0xee0
|
||||
#define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0xee4
|
||||
#define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0xee8
|
||||
#define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR 0x1820
|
||||
#define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR 0x1824
|
||||
#define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR 0x1828
|
||||
#define REG_TX_AGC_C_MCS3_MCS0_JAGUAR 0x182c
|
||||
#define REG_TX_AGC_C_MCS7_MCS4_JAGUAR 0x1830
|
||||
#define REG_TX_AGC_C_MCS11_MCS8_JAGUAR 0x1834
|
||||
#define REG_TX_AGC_C_MCS15_MCS12_JAGUAR 0x1838
|
||||
#define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0x183c
|
||||
#define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0x1840
|
||||
#define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0x1844
|
||||
#define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0x1848
|
||||
#define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0x184c
|
||||
#define REG_TX_AGC_C_MCS19_MCS16_JAGUAR 0x18d8
|
||||
#define REG_TX_AGC_C_MCS23_MCS20_JAGUAR 0x18dc
|
||||
#define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0x18e0
|
||||
#define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0x18e4
|
||||
#define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0x18e8
|
||||
#define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR 0x1a20
|
||||
#define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR 0x1a24
|
||||
#define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR 0x1a28
|
||||
#define REG_TX_AGC_D_MCS3_MCS0_JAGUAR 0x1a2c
|
||||
#define REG_TX_AGC_D_MCS7_MCS4_JAGUAR 0x1a30
|
||||
#define REG_TX_AGC_D_MCS11_MCS8_JAGUAR 0x1a34
|
||||
#define REG_TX_AGC_D_MCS15_MCS12_JAGUAR 0x1a38
|
||||
#define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0x1a3c
|
||||
#define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0x1a40
|
||||
#define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0x1a44
|
||||
#define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0x1a48
|
||||
#define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0x1a4c
|
||||
#define REG_TX_AGC_D_MCS19_MCS16_JAGUAR 0x1ad8
|
||||
#define REG_TX_AGC_D_MCS23_MCS20_JAGUAR 0x1adc
|
||||
#define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0x1ae0
|
||||
#define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0x1ae4
|
||||
#define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0x1ae8
|
||||
#endif
|
||||
|
||||
#define is_tx_agc_byte0_jaguar 0xff
|
||||
#define is_tx_agc_byte1_jaguar 0xff00
|
||||
#define is_tx_agc_byte2_jaguar 0xff0000
|
||||
#define is_tx_agc_byte3_jaguar 0xff000000
|
||||
#endif
|
||||
|
||||
#define BIT_FA_RESET BIT(0)
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
93
hal/phydm/phydm_regdefine11ac.h
Normal file
93
hal/phydm/phydm_regdefine11ac.h
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ODM_REGDEFINE11AC_H__
|
||||
#define __ODM_REGDEFINE11AC_H__
|
||||
|
||||
/* 2 RF REG LIST */
|
||||
|
||||
|
||||
|
||||
/* 2 BB REG LIST
|
||||
* PAGE 8 */
|
||||
#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
|
||||
#define ODM_REG_BB_RX_PATH_11AC 0x808
|
||||
#define ODM_REG_BB_TX_PATH_11AC 0x80c
|
||||
#define ODM_REG_BB_ATC_11AC 0x860
|
||||
#define ODM_REG_EDCCA_POWER_CAL 0x8dc
|
||||
#define ODM_REG_DBG_RPT_11AC 0x8fc
|
||||
/* PAGE 9 */
|
||||
#define ODM_REG_EDCCA_DOWN_OPT 0x900
|
||||
#define ODM_REG_ACBB_EDCCA_ENHANCE 0x944
|
||||
#define odm_adc_trigger_jaguar2 0x95C /*ADC sample mode*/
|
||||
#define ODM_REG_OFDM_FA_RST_11AC 0x9A4
|
||||
#define ODM_REG_CCX_PERIOD_11AC 0x990
|
||||
#define ODM_REG_NHM_TH9_TH10_11AC 0x994
|
||||
#define ODM_REG_CLM_11AC 0x994
|
||||
#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998
|
||||
#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c
|
||||
#define ODM_REG_NHM_TH8_11AC 0x9a0
|
||||
#define ODM_REG_NHM_9E8_11AC 0x9e8
|
||||
#define ODM_REG_CSI_CONTENT_VALUE 0x9b4
|
||||
/* PAGE A */
|
||||
#define ODM_REG_CCK_CCA_11AC 0xA0A
|
||||
#define ODM_REG_CCK_FA_RST_11AC 0xA2C
|
||||
#define ODM_REG_CCK_FA_11AC 0xA5C
|
||||
/* PAGE B */
|
||||
#define ODM_REG_RST_RPT_11AC 0xB58
|
||||
/* PAGE C */
|
||||
#define ODM_REG_TRMUX_11AC 0xC08
|
||||
#define ODM_REG_IGI_A_11AC 0xC50
|
||||
/* PAGE E */
|
||||
#define ODM_REG_IGI_B_11AC 0xE50
|
||||
#define ODM_REG_TRMUX_11AC_B 0xE08
|
||||
/* PAGE F */
|
||||
#define ODM_REG_CCK_CRC32_CNT_11AC 0xF04
|
||||
#define ODM_REG_CCK_CCA_CNT_11AC 0xF08
|
||||
#define ODM_REG_VHT_CRC32_CNT_11AC 0xF0c
|
||||
#define ODM_REG_HT_CRC32_CNT_11AC 0xF10
|
||||
#define ODM_REG_OFDM_CRC32_CNT_11AC 0xF14
|
||||
#define ODM_REG_OFDM_FA_11AC 0xF48
|
||||
#define ODM_REG_RPT_11AC 0xfa0
|
||||
#define ODM_REG_CLM_RESULT_11AC 0xfa4
|
||||
#define ODM_REG_NHM_CNT_11AC 0xfa8
|
||||
#define ODM_REG_NHM_DUR_READY_11AC 0xfb4
|
||||
|
||||
#define ODM_REG_NHM_CNT7_TO_CNT4_11AC 0xfac
|
||||
#define ODM_REG_NHM_CNT11_TO_CNT8_11AC 0xfb0
|
||||
#define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0
|
||||
/* PAGE 18 */
|
||||
#define ODM_REG_IGI_C_11AC 0x1850
|
||||
/* PAGE 1A */
|
||||
#define ODM_REG_IGI_D_11AC 0x1A50
|
||||
|
||||
/* 2 MAC REG LIST */
|
||||
#define ODM_REG_RESP_TX_11AC 0x6D8
|
||||
|
||||
|
||||
|
||||
/* DIG Related */
|
||||
#define ODM_BIT_IGI_11AC 0xFFFFFFFF
|
||||
#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT(16)
|
||||
#define ODM_BIT_BB_RX_PATH_11AC 0xF
|
||||
#define ODM_BIT_BB_TX_PATH_11AC 0xF
|
||||
#define ODM_BIT_BB_ATC_11AC BIT(14)
|
||||
|
||||
#endif
|
||||
212
hal/phydm/phydm_regdefine11n.h
Normal file
212
hal/phydm/phydm_regdefine11n.h
Normal file
|
|
@ -0,0 +1,212 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ODM_REGDEFINE11N_H__
|
||||
#define __ODM_REGDEFINE11N_H__
|
||||
|
||||
|
||||
/* 2 RF REG LIST */
|
||||
#define ODM_REG_RF_MODE_11N 0x00
|
||||
#define ODM_REG_RF_0B_11N 0x0B
|
||||
#define ODM_REG_CHNBW_11N 0x18
|
||||
#define ODM_REG_T_METER_11N 0x24
|
||||
#define ODM_REG_RF_25_11N 0x25
|
||||
#define ODM_REG_RF_26_11N 0x26
|
||||
#define ODM_REG_RF_27_11N 0x27
|
||||
#define ODM_REG_RF_2B_11N 0x2B
|
||||
#define ODM_REG_RF_2C_11N 0x2C
|
||||
#define ODM_REG_RXRF_A3_11N 0x3C
|
||||
#define ODM_REG_T_METER_92D_11N 0x42
|
||||
#define ODM_REG_T_METER_88E_11N 0x42
|
||||
|
||||
|
||||
|
||||
/* 2 BB REG LIST
|
||||
* PAGE 8 */
|
||||
#define ODM_REG_BB_CTRL_11N 0x800
|
||||
#define ODM_REG_RF_PIN_11N 0x804
|
||||
#define ODM_REG_PSD_CTRL_11N 0x808
|
||||
#define ODM_REG_TX_ANT_CTRL_11N 0x80C
|
||||
#define ODM_REG_BB_PWR_SAV5_11N 0x818
|
||||
#define ODM_REG_CCK_RPT_FORMAT_11N 0x824
|
||||
#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C
|
||||
#define ODM_REG_RX_DEFUALT_A_11N 0x858
|
||||
#define ODM_REG_RX_DEFUALT_B_11N 0x85A
|
||||
#define ODM_REG_BB_PWR_SAV3_11N 0x85C
|
||||
#define ODM_REG_ANTSEL_CTRL_11N 0x860
|
||||
#define ODM_REG_RX_ANT_CTRL_11N 0x864
|
||||
#define ODM_REG_PIN_CTRL_11N 0x870
|
||||
#define ODM_REG_BB_PWR_SAV1_11N 0x874
|
||||
#define ODM_REG_ANTSEL_PATH_11N 0x878
|
||||
#define ODM_REG_BB_3WIRE_11N 0x88C
|
||||
#define ODM_REG_SC_CNT_11N 0x8C4
|
||||
#define ODM_REG_PSD_DATA_11N 0x8B4
|
||||
#define ODM_REG_CCX_PERIOD_11N 0x894
|
||||
#define ODM_REG_NHM_TH9_TH10_11N 0x890
|
||||
#define ODM_REG_CLM_11N 0x890
|
||||
#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898
|
||||
#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c
|
||||
#define ODM_REG_NHM_TH8_11N 0xe28
|
||||
#define ODM_REG_CLM_READY_11N 0x8b4
|
||||
#define ODM_REG_CLM_RESULT_11N 0x8d0
|
||||
#define ODM_REG_NHM_CNT_11N 0x8d8
|
||||
|
||||
/* For struct _ACS_, Jeffery, 2014-12-26 */
|
||||
#define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc
|
||||
#define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0
|
||||
#define ODM_REG_NHM_CNT10_TO_CNT11_11N 0x8d4
|
||||
|
||||
/* PAGE 9 */
|
||||
#define ODM_REG_BB_CTRL_PAGE9_11N 0x900
|
||||
#define ODM_REG_DBG_RPT_11N 0x908
|
||||
#define ODM_REG_BB_TX_PATH_11N 0x90c
|
||||
#define ODM_REG_ANT_MAPPING1_11N 0x914
|
||||
#define ODM_REG_ANT_MAPPING2_11N 0x918
|
||||
#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948
|
||||
#define ODM_REG_RX_DFIR_MOD_97F 0x948
|
||||
|
||||
/* PAGE A */
|
||||
#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
|
||||
#define ODM_REG_CCK_ANT_SEL_11N 0xA04
|
||||
#define ODM_REG_CCK_CCA_11N 0xA0A
|
||||
#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
|
||||
#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10
|
||||
#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14
|
||||
#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22
|
||||
#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23
|
||||
#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24
|
||||
#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25
|
||||
#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26
|
||||
#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27
|
||||
#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28
|
||||
#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29
|
||||
#define ODM_REG_CCK_FA_RST_11N 0xA2C
|
||||
#define ODM_REG_CCK_FA_MSB_11N 0xA58
|
||||
#define ODM_REG_CCK_FA_LSB_11N 0xA5C
|
||||
#define ODM_REG_CCK_CCA_CNT_11N 0xA60
|
||||
#define ODM_REG_BB_PWR_SAV4_11N 0xA74
|
||||
/* PAGE B */
|
||||
#define ODM_REG_LNA_SWITCH_11N 0xB2C
|
||||
#define ODM_REG_PATH_SWITCH_11N 0xB30
|
||||
#define ODM_REG_RSSI_CTRL_11N 0xB38
|
||||
#define ODM_REG_CONFIG_ANTA_11N 0xB68
|
||||
#define ODM_REG_RSSI_BT_11N 0xB9C
|
||||
#define ODM_REG_RXCK_RFMOD 0xBB0
|
||||
#define ODM_REG_EDCCA_DCNF_97F 0xBC0
|
||||
|
||||
/* PAGE C */
|
||||
#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
|
||||
#define ODM_REG_BB_RX_PATH_11N 0xC04
|
||||
#define ODM_REG_TRMUX_11N 0xC08
|
||||
#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C
|
||||
#define ODM_REG_DOWNSAM_FACTOR_11N 0xC10
|
||||
#define ODM_REG_RXIQI_MATRIX_11N 0xC14
|
||||
#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
|
||||
#define ODM_REG_IGI_A_11N 0xC50
|
||||
#define ODM_REG_ANTDIV_PARA2_11N 0xC54
|
||||
#define ODM_REG_IGI_B_11N 0xC58
|
||||
#define ODM_REG_ANTDIV_PARA3_11N 0xC5C
|
||||
#define ODM_REG_L1SBD_PD_CH_11N 0XC6C
|
||||
#define ODM_REG_BB_PWR_SAV2_11N 0xC70
|
||||
#define ODM_REG_BB_AGC_SET_2_11N 0xc74
|
||||
#define ODM_REG_RX_OFF_11N 0xC7C
|
||||
#define ODM_REG_TXIQK_MATRIXA_11N 0xC80
|
||||
#define ODM_REG_TXIQK_MATRIXB_11N 0xC88
|
||||
#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
|
||||
#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
|
||||
#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
|
||||
#define ODM_REG_ANTDIV_PARA1_11N 0xCA4
|
||||
#define ODM_REG_SMALL_BANDWIDTH_11N 0xCE4
|
||||
#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
|
||||
/* PAGE D */
|
||||
#define ODM_REG_OFDM_FA_RSTD_11N 0xD00
|
||||
#define ODM_REG_BB_RX_ANT_11N 0xD04
|
||||
#define ODM_REG_BB_ATC_11N 0xD2C
|
||||
#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
|
||||
#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
|
||||
#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
|
||||
#define ODM_REG_RPT_11N 0xDF4
|
||||
/* PAGE E */
|
||||
#define ODM_REG_TXAGC_A_6_18_11N 0xE00
|
||||
#define ODM_REG_TXAGC_A_24_54_11N 0xE04
|
||||
#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08
|
||||
#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10
|
||||
#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14
|
||||
#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18
|
||||
#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C
|
||||
#define ODM_REG_EDCCA_DCNF_11N 0xE24
|
||||
#define ODM_REG_TAP_UPD_97F 0xE24
|
||||
#define ODM_REG_FPGA0_IQK_11N 0xE28
|
||||
#define ODM_REG_PAGE_B1_97F 0xE28
|
||||
#define ODM_REG_TXIQK_TONE_A_11N 0xE30
|
||||
#define ODM_REG_RXIQK_TONE_A_11N 0xE34
|
||||
#define ODM_REG_TXIQK_PI_A_11N 0xE38
|
||||
#define ODM_REG_RXIQK_PI_A_11N 0xE3C
|
||||
#define ODM_REG_TXIQK_11N 0xE40
|
||||
#define ODM_REG_RXIQK_11N 0xE44
|
||||
#define ODM_REG_IQK_AGC_PTS_11N 0xE48
|
||||
#define ODM_REG_IQK_AGC_RSP_11N 0xE4C
|
||||
#define ODM_REG_BLUETOOTH_11N 0xE6C
|
||||
#define ODM_REG_RX_WAIT_CCA_11N 0xE70
|
||||
#define ODM_REG_TX_CCK_RFON_11N 0xE74
|
||||
#define ODM_REG_TX_CCK_BBON_11N 0xE78
|
||||
#define ODM_REG_OFDM_RFON_11N 0xE7C
|
||||
#define ODM_REG_OFDM_BBON_11N 0xE80
|
||||
#define ODM_REG_TX2RX_11N 0xE84
|
||||
#define ODM_REG_TX2TX_11N 0xE88
|
||||
#define ODM_REG_RX_CCK_11N 0xE8C
|
||||
#define ODM_REG_RX_OFDM_11N 0xED0
|
||||
#define ODM_REG_RX_WAIT_RIFS_11N 0xED4
|
||||
#define ODM_REG_RX2RX_11N 0xED8
|
||||
#define ODM_REG_STANDBY_11N 0xEDC
|
||||
#define ODM_REG_SLEEP_11N 0xEE0
|
||||
#define ODM_REG_PMPD_ANAEN_11N 0xEEC
|
||||
/* PAGE F */
|
||||
#define ODM_REG_PAGE_F_RST_11N 0xF14
|
||||
#define ODM_REG_IGI_C_11N 0xF84
|
||||
#define ODM_REG_IGI_D_11N 0xF88
|
||||
#define ODM_REG_CCK_CRC32_ERROR_CNT_11N 0xF84
|
||||
#define ODM_REG_CCK_CRC32_OK_CNT_11N 0xF88
|
||||
#define ODM_REG_HT_CRC32_CNT_11N 0xF90
|
||||
#define ODM_REG_OFDM_CRC32_CNT_11N 0xF94
|
||||
|
||||
/* 2 MAC REG LIST */
|
||||
#define ODM_REG_BB_RST_11N 0x02
|
||||
#define ODM_REG_ANTSEL_PIN_11N 0x4C
|
||||
#define ODM_REG_EARLY_MODE_11N 0x4D0
|
||||
#define ODM_REG_RSSI_MONITOR_11N 0x4FE
|
||||
#define ODM_REG_EDCA_VO_11N 0x500
|
||||
#define ODM_REG_EDCA_VI_11N 0x504
|
||||
#define ODM_REG_EDCA_BE_11N 0x508
|
||||
#define ODM_REG_EDCA_BK_11N 0x50C
|
||||
#define ODM_REG_TXPAUSE_11N 0x522
|
||||
#define ODM_REG_RESP_TX_11N 0x6D8
|
||||
#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0
|
||||
#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4
|
||||
|
||||
|
||||
/* DIG Related */
|
||||
#define ODM_BIT_IGI_11N 0x0000007F
|
||||
#define ODM_BIT_CCK_RPT_FORMAT_11N BIT(9)
|
||||
#define ODM_BIT_BB_RX_PATH_11N 0xF
|
||||
#define ODM_BIT_BB_TX_PATH_11N 0xF
|
||||
#define ODM_BIT_BB_ATC_11N BIT(11)
|
||||
|
||||
#endif
|
||||
294
hal/phydm/phydm_types.h
Normal file
294
hal/phydm/phydm_types.h
Normal file
|
|
@ -0,0 +1,294 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __ODM_TYPES_H__
|
||||
#define __ODM_TYPES_H__
|
||||
|
||||
|
||||
/*Define Different SW team support*/
|
||||
#define ODM_AP 0x01 /*BIT0*/
|
||||
#define ODM_CE 0x04 /*BIT2*/
|
||||
#define ODM_WIN 0x08 /*BIT3*/
|
||||
#define ODM_ADSL 0x10 /*BIT4*/
|
||||
#define ODM_IOT 0x20 /*BIT5*/
|
||||
|
||||
/*Deifne HW endian support*/
|
||||
#define ODM_ENDIAN_BIG 0
|
||||
#define ODM_ENDIAN_LITTLE 1
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define GET_PDM_ODM(__padapter) ((struct PHY_DM_STRUCT*)(&((GET_HAL_DATA(__padapter))->DM_OutSrc)))
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#define GET_PDM_ODM(__padapter) ((struct PHY_DM_STRUCT*)(&((GET_HAL_DATA(__padapter))->odmpriv)))
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
|
||||
#define RT_PCI_INTERFACE 1
|
||||
#define RT_USB_INTERFACE 2
|
||||
#define RT_SDIO_INTERFACE 3
|
||||
#endif
|
||||
|
||||
enum hal_status {
|
||||
HAL_STATUS_SUCCESS,
|
||||
HAL_STATUS_FAILURE,
|
||||
/*RT_STATUS_PENDING,
|
||||
RT_STATUS_RESOURCE,
|
||||
RT_STATUS_INVALID_CONTEXT,
|
||||
RT_STATUS_INVALID_PARAMETER,
|
||||
RT_STATUS_NOT_SUPPORT,
|
||||
RT_STATUS_OS_API_FAILED,*/
|
||||
};
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#define MP_DRIVER 0
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
|
||||
|
||||
#define VISTA_USB_RX_REVISE 0
|
||||
|
||||
/*
|
||||
* Declare for ODM spin lock defintion temporarily fro compile pass.
|
||||
* */
|
||||
enum rt_spinlock_type {
|
||||
RT_TX_SPINLOCK = 1,
|
||||
RT_RX_SPINLOCK = 2,
|
||||
RT_RM_SPINLOCK = 3,
|
||||
RT_CAM_SPINLOCK = 4,
|
||||
RT_SCAN_SPINLOCK = 5,
|
||||
RT_LOG_SPINLOCK = 7,
|
||||
RT_BW_SPINLOCK = 8,
|
||||
RT_CHNLOP_SPINLOCK = 9,
|
||||
RT_RF_OPERATE_SPINLOCK = 10,
|
||||
RT_INITIAL_SPINLOCK = 11,
|
||||
RT_RF_STATE_SPINLOCK = 12, /* For RF state. Added by Bruce, 2007-10-30. */
|
||||
#if VISTA_USB_RX_REVISE
|
||||
RT_USBRX_CONTEXT_SPINLOCK = 13,
|
||||
RT_USBRX_POSTPROC_SPINLOCK = 14, /* protect data of adapter->IndicateW/ IndicateR */
|
||||
#endif
|
||||
/* Shall we define Ndis 6.2 SpinLock Here ? */
|
||||
RT_PORT_SPINLOCK = 16,
|
||||
RT_VNIC_SPINLOCK = 17,
|
||||
RT_HVL_SPINLOCK = 18,
|
||||
RT_H2C_SPINLOCK = 20, /* For H2C cmd. Added by tynli. 2009.11.09. */
|
||||
|
||||
rt_bt_data_spinlock = 25,
|
||||
|
||||
RT_WAPI_OPTION_SPINLOCK = 26,
|
||||
RT_WAPI_RX_SPINLOCK = 27,
|
||||
|
||||
/* add for 92D CCK control issue */
|
||||
RT_CCK_PAGEA_SPINLOCK = 28,
|
||||
RT_BUFFER_SPINLOCK = 29,
|
||||
RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30,
|
||||
RT_GEN_TEMP_BUF_SPINLOCK = 31,
|
||||
RT_AWB_SPINLOCK = 32,
|
||||
RT_FW_PS_SPINLOCK = 33,
|
||||
RT_HW_TIMER_SPIN_LOCK = 34,
|
||||
RT_MPT_WI_SPINLOCK = 35,
|
||||
RT_P2P_SPIN_LOCK = 36, /* Protect P2P context */
|
||||
RT_DBG_SPIN_LOCK = 37,
|
||||
RT_IQK_SPINLOCK = 38,
|
||||
RT_PENDED_OID_SPINLOCK = 39,
|
||||
RT_CHNLLIST_SPINLOCK = 40,
|
||||
RT_INDIC_SPINLOCK = 41, /* protect indication */
|
||||
RT_RFD_SPINLOCK = 42,
|
||||
RT_SYNC_IO_CNT_SPINLOCK = 43,
|
||||
RT_LAST_SPINLOCK,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define sta_info _RT_WLAN_STA
|
||||
#define __func__ __FUNCTION__
|
||||
#define PHYDM_TESTCHIP_SUPPORT TESTCHIP_SUPPORT
|
||||
#define MASKH3BYTES 0xffffff00
|
||||
#define SUCCESS 0
|
||||
#define FAIL (-1)
|
||||
|
||||
#define u8 u1Byte
|
||||
#define s8 s1Byte
|
||||
|
||||
#define u16 u2Byte
|
||||
#define s16 s2Byte
|
||||
|
||||
#define u32 u4Byte
|
||||
#define s32 s4Byte
|
||||
|
||||
#define u64 u8Byte
|
||||
#define s64 s8Byte
|
||||
|
||||
#define bool BOOLEAN
|
||||
|
||||
#define timer_list _RT_TIMER
|
||||
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
|
||||
/* To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07. */
|
||||
#define ADSL_AP_BUILD_WORKAROUND
|
||||
#define AP_BUILD_WORKAROUND
|
||||
|
||||
#ifdef AP_BUILD_WORKAROUND
|
||||
#include "../typedef.h"
|
||||
#else
|
||||
typedef void void, *void *;
|
||||
typedef unsigned char bool, *bool *;
|
||||
typedef unsigned char u8, *u8 *;
|
||||
typedef unsigned short u16, *u16 *;
|
||||
typedef unsigned int u32, *u32 *;
|
||||
typedef unsigned long long u64, *u64 *;
|
||||
#if 1
|
||||
/* In ARM platform, system would use the type -- "char" as "unsigned char"
|
||||
* And we only use s8/s8* as INT8 now, so changes the type of s8.*/
|
||||
typedef signed char s8, *s8 *;
|
||||
#else
|
||||
typedef char s8, *s8 *;
|
||||
#endif
|
||||
typedef short s16, *s16 *;
|
||||
typedef long s32, *s32 *;
|
||||
typedef long long s64, *s64 *;
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#define DEV_BUS_TYPE RT_PCI_INTERFACE
|
||||
#endif
|
||||
|
||||
#define _TRUE 1
|
||||
#define _FALSE 0
|
||||
|
||||
#if (defined(TESTCHIP_SUPPORT))
|
||||
#define PHYDM_TESTCHIP_SUPPORT 1
|
||||
#else
|
||||
#define PHYDM_TESTCHIP_SUPPORT 0
|
||||
#endif
|
||||
|
||||
#define sta_info stat_info
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include <drv_types.h>
|
||||
#if 0
|
||||
typedef u8 u8, *u8 *;
|
||||
typedef u16 u16, *u16 *;
|
||||
typedef u32 u32, *u32 *;
|
||||
typedef u64 u64, *u64 *;
|
||||
typedef s8 s8, *s8 *;
|
||||
typedef s16 s16, *s16 *;
|
||||
typedef s32 s32, *s32 *;
|
||||
typedef s64 s64, *s64 *;
|
||||
#elif 0
|
||||
#define u8 u8
|
||||
#define u8 *u8*
|
||||
|
||||
#define u16 u16
|
||||
#define u16 *u16*
|
||||
|
||||
#define u32 u32
|
||||
#define u32 *u32*
|
||||
|
||||
#define u64 u64
|
||||
#define u64* u64*
|
||||
|
||||
#define s8 s8
|
||||
#define s8* s8*
|
||||
|
||||
#define s16 s16
|
||||
#define s16* s16*
|
||||
|
||||
#define s32 s32
|
||||
#define s32* s32*
|
||||
|
||||
#define s64 s64
|
||||
#define s64* s64*
|
||||
|
||||
#endif
|
||||
#ifdef CONFIG_USB_HCI
|
||||
#define DEV_BUS_TYPE RT_USB_INTERFACE
|
||||
#elif defined(CONFIG_PCI_HCI)
|
||||
#define DEV_BUS_TYPE RT_PCI_INTERFACE
|
||||
#elif defined(CONFIG_SDIO_HCI)
|
||||
#define DEV_BUS_TYPE RT_SDIO_INTERFACE
|
||||
#elif defined(CONFIG_GSPI_HCI)
|
||||
#define DEV_BUS_TYPE RT_SDIO_INTERFACE
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(CONFIG_LITTLE_ENDIAN)
|
||||
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
|
||||
#elif defined (CONFIG_BIG_ENDIAN)
|
||||
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
|
||||
#endif
|
||||
|
||||
//#define struct sta_info struct sta_info
|
||||
//#define struct sta_info* struct sta_info *
|
||||
|
||||
|
||||
|
||||
#define true _TRUE
|
||||
#define false _FALSE
|
||||
|
||||
|
||||
#define SET_TX_DESC_ANTSEL_A_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc+8, 24, 1, __value)
|
||||
#define SET_TX_DESC_ANTSEL_B_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc+8, 25, 1, __value)
|
||||
#define SET_TX_DESC_ANTSEL_C_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc+28, 29, 1, __value)
|
||||
|
||||
/* define useless flag to avoid compile warning */
|
||||
#define USE_WORKITEM 0
|
||||
#define FOR_BRAZIL_PRETEST 0
|
||||
#define FPGA_TWO_MAC_VERIFICATION 0
|
||||
#define RTL8881A_SUPPORT 0
|
||||
|
||||
#if (defined(TESTCHIP_SUPPORT))
|
||||
#define PHYDM_TESTCHIP_SUPPORT 1
|
||||
#else
|
||||
#define PHYDM_TESTCHIP_SUPPORT 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define READ_NEXT_PAIR(v1, v2, i) do { if (i+2 >= array_len) break; i += 2; v1 = array[i]; v2 = array[i+1]; } while (0)
|
||||
#define COND_ELSE 2
|
||||
#define COND_ENDIF 3
|
||||
|
||||
#define MASKBYTE0 0xff
|
||||
#define MASKBYTE1 0xff00
|
||||
#define MASKBYTE2 0xff0000
|
||||
#define MASKBYTE3 0xff000000
|
||||
#define MASKHWORD 0xffff0000
|
||||
#define MASKLWORD 0x0000ffff
|
||||
#define MASKDWORD 0xffffffff
|
||||
#define MASK7BITS 0x7f
|
||||
#define MASK12BITS 0xfff
|
||||
#define MASKH4BITS 0xf0000000
|
||||
#define MASK20BITS 0xfffff
|
||||
#define MASKOFDM_D 0xffc00000
|
||||
#define MASKCCK 0x3f3f3f3f
|
||||
#define RFREGOFFSETMASK 0xfffff
|
||||
#define MASKH3BYTES 0xffffff00
|
||||
#define MASKL3BYTES 0x00ffffff
|
||||
#define MASKBYTE2HIGHNIBBLE 0x00f00000
|
||||
#define MASKBYTE3LOWNIBBLE 0x0f000000
|
||||
#define MASKL3BYTES 0x00ffffff
|
||||
#define RFREGOFFSETMASK 0xfffff
|
||||
|
||||
|
||||
#include "phydm_features.h"
|
||||
|
||||
#endif /* __ODM_TYPES_H__ */
|
||||
475
hal/phydm/rtchnlplan.c
Normal file
475
hal/phydm/rtchnlplan.c
Normal file
|
|
@ -0,0 +1,475 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
|
||||
History:
|
||||
data Who Remark (Internal History)
|
||||
|
||||
05/14/2012 MH Collect RTK inernal infromation and generate channel plan draft.
|
||||
|
||||
******************************************************************************/
|
||||
|
||||
/* ************************************************************
|
||||
* include files
|
||||
* ************************************************************ */
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
#include "rtchnlplan.h"
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* channel Plan Domain Code
|
||||
* */
|
||||
|
||||
/*
|
||||
channel Plan Contents
|
||||
Domain Code EEPROM Countries in Specific Domain
|
||||
2G RD 5G RD Bit[6:0] 2G 5G
|
||||
Case Old Define 00h~1Fh Old Define Old Define
|
||||
1 2G_WORLD 5G_NULL 20h Worldwird 13 NA
|
||||
2 2G_ETSI1 5G_NULL 21h Europe 2G NA
|
||||
3 2G_FCC1 5G_NULL 22h US 2G NA
|
||||
4 2G_MKK1 5G_NULL 23h Japan 2G NA
|
||||
5 2G_ETSI2 5G_NULL 24h France 2G NA
|
||||
6 2G_FCC1 5G_FCC1 25h US 2G US 5G 八大國認證
|
||||
7 2G_WORLD 5G_ETSI1 26h Worldwird 13 Europe 八大國認證
|
||||
8 2G_MKK1 5G_MKK1 27h Japan 2G Japan 5G 八大國認證
|
||||
9 2G_WORLD 5G_KCC1 28h Worldwird 13 Korea 八大國認證
|
||||
10 2G_WORLD 5G_FCC2 29h Worldwird 13 US o/w DFS Channels
|
||||
11 2G_WORLD 5G_FCC3 30h Worldwird 13 India, Mexico
|
||||
12 2G_WORLD 5G_FCC4 31h Worldwird 13 Venezuela
|
||||
13 2G_WORLD 5G_FCC5 32h Worldwird 13 China
|
||||
14 2G_WORLD 5G_FCC6 33h Worldwird 13 Israel
|
||||
15 2G_FCC1 5G_FCC7 34h US 2G US/Canada 八大國認證
|
||||
16 2G_WORLD 5G_ETSI2 35h Worldwird 13 Australia, New Zealand 八大國認證
|
||||
17 2G_WORLD 5G_ETSI3 36h Worldwird 13 Russia
|
||||
18 2G_MKK1 5G_MKK2 37h Japan 2G Japan (W52, W53)
|
||||
19 2G_MKK1 5G_MKK3 38h Japan 2G Japan (W56)
|
||||
20 2G_FCC1 5G_NCC1 39h US 2G Taiwan 八大國認證
|
||||
|
||||
NA 2G_WORLD 5G_FCC1 7F FCC FCC DFS Channels Realtek Define
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
2.4G Regulatory Domains
|
||||
Case 2G RD regulation Channels Frequencyes Note Countries in Specific Domain
|
||||
1 2G_WORLD ETSI 1~13 2412~2472 Passive scan CH 12, 13 Worldwird 13
|
||||
2 2G_ETSI1 ETSI 1~13 2412~2472 Europe
|
||||
3 2G_FCC1 FCC 1~11 2412~2462 US
|
||||
4 2G_MKK1 MKK 1~13, 14 2412~2472, 2484 Japan
|
||||
5 2G_ETSI2 ETSI 10~13 2457~2472 France
|
||||
|
||||
|
||||
|
||||
|
||||
5G Regulatory Domains
|
||||
Case 5G RD regulation Channels Frequencyes Note Countries in Specific Domain
|
||||
1 5G_NULL NA NA NA Do not support 5GHz
|
||||
2 5G_ETSI1 ETSI "36~48, 52~64,
|
||||
100~140" "5180~5240, 5260~5230
|
||||
5500~5700" Band1, Ban2, Band3 Europe
|
||||
3 5G_ETSI2 ETSI "36~48, 52~64,
|
||||
100~140, 149~165" "5180~5240, 5260~5230
|
||||
5500~5700, 5745~5825" Band1, Ban2, Band3, Band4 Australia, New Zealand
|
||||
4 5G_ETSI3 ETSI "36~48, 52~64,
|
||||
100~132, 149~165"
|
||||
"5180~5240, 5260~5230
|
||||
5500~5660, 5745~5825" Band1, Ban2, Band3(except CH 136, 140), Band4" Russia
|
||||
5 5G_FCC1 FCC "36~48, 52~64,
|
||||
100~140, 149~165"
|
||||
"5180~5240, 5260~5230
|
||||
5500~5700, 5745~5825" Band1(5150~5250MHz),
|
||||
Band2(5250~5350MHz),
|
||||
Band3(5470~5725MHz),
|
||||
Band4(5725~5850MHz)" US
|
||||
6 5G_FCC2 FCC 36~48, 149~165 5180~5240, 5745~5825 Band1, Band4 FCC o/w DFS Channels
|
||||
7 5G_FCC3 FCC "36~48, 52~64,
|
||||
149~165" "5180~5240, 5260~5230
|
||||
5745~5825" Band1, Ban2, Band4 India, Mexico
|
||||
8 5G_FCC4 FCC "36~48, 52~64,
|
||||
149~161" "5180~5240, 5260~5230
|
||||
5745~5805" Band1, Ban2,
|
||||
Band4(except CH 165)" Venezuela
|
||||
9 5G_FCC5 FCC 149~165 5745~5825 Band4 China
|
||||
10 5G_FCC6 FCC 36~48, 52~64 5180~5240, 5260~5230 Band1, Band2 Israel
|
||||
11 5G_FCC7
|
||||
5G_IC1 FCC
|
||||
IC" "36~48, 52~64,
|
||||
100~116, 136, 140,
|
||||
149~165" "5180~5240, 5260~5230
|
||||
5500~5580, 5680, 5700,
|
||||
5745~5825" "Band1, Band2,
|
||||
Band3(except 5600~5650MHz),
|
||||
Band4" "US
|
||||
Canada"
|
||||
12 5G_KCC1 KCC "36~48, 52~64,
|
||||
100~124, 149~165" "5180~5240, 5260~5230
|
||||
5500~5620, 5745~5825" "Band1, Ban2,
|
||||
Band3(5470~5650MHz),
|
||||
Band4" Korea
|
||||
13 5G_MKK1 MKK "36~48, 52~64,
|
||||
100~140" "5180~5240, 5260~5230
|
||||
5500~5700" W52, W53, W56 Japan
|
||||
14 5G_MKK2 MKK 36~48, 52~64 5180~5240, 5260~5230 W52, W53 Japan (W52, W53)
|
||||
15 5G_MKK3 MKK 100~140 5500~5700 W56 Japan (W56)
|
||||
16 5G_NCC1 NCC "56~64,
|
||||
100~116, 136, 140,
|
||||
149~165" "5260~5320
|
||||
5500~5580, 5680, 5700,
|
||||
5745~5825" "Band2(except CH 52),
|
||||
Band3(except 5600~5650MHz),
|
||||
Band4" Taiwan
|
||||
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
* 2.4G CHannel
|
||||
*
|
||||
*
|
||||
|
||||
2.4G band Regulatory Domains RTL8192D
|
||||
channel number channel Frequency US Canada Europe Spain France Japan Japan 20M 40M
|
||||
(MHz) (FCC) (IC) (ETSI) (MPHPT)
|
||||
1 2412 v v v v v
|
||||
2 2417 v v v v v
|
||||
3 2422 v v v v v v
|
||||
4 2427 v v v v v v
|
||||
5 2432 v v v v v v
|
||||
6 2437 v v v v v v
|
||||
7 2442 v v v v v v
|
||||
8 2447 v v v v v v
|
||||
9 2452 v v v v v v
|
||||
10 2457 v v v v v v v v
|
||||
11 2462 v v v v v v v v
|
||||
12 2467 v v v v v
|
||||
13 2472 v v v v
|
||||
14 2484 v v
|
||||
|
||||
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* 5G Operating channel
|
||||
*
|
||||
*
|
||||
|
||||
5G band RTL8192D RTL8195 (Jaguar) Jaguar 2 Regulatory Domains
|
||||
channel number channel Frequency Global Global Global "US
|
||||
(FCC 15.407)" "Canada
|
||||
(FCC, except 5.6~5.65GHz)" Argentina, Australia, New Zealand, Brazil, S. Africa (FCC/ETSI) "Europe
|
||||
(CE 301 893)" China India, Mexico, Singapore Israel, Turkey "Japan
|
||||
(MIC Item 19-3, 19-3-2)" Korea Russia, Ukraine "Taiwan
|
||||
(NCC)" Venezuela
|
||||
(MHz) (20MHz) (20MHz) (40MHz) (80MHz) (160MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz)
|
||||
"band 1
|
||||
5.15GHz
|
||||
~
|
||||
5.25GHz" 36 5180 v v v v v Indoor Indoor v Indoor v Indoor Indoor v v v
|
||||
40 5200 v v v Indoor Indoor v Indoor v Indoor Indoor v v v
|
||||
44 5220 v v v v Indoor Indoor v Indoor v Indoor Indoor v v v
|
||||
48 5240 v v v Indoor Indoor v Indoor v Indoor Indoor v v v
|
||||
"band 2
|
||||
5.25GHz
|
||||
~
|
||||
5.35GHz
|
||||
(DFS)" 52 5260 v v v v v v v v Indoor v Indoor Indoor v v v
|
||||
56 5280 v v v v v v Indoor v Indoor Indoor v v Indoor v
|
||||
60 5300 v v v v v v v Indoor v Indoor Indoor v v Indoor v
|
||||
64 5320 v v v v v v Indoor v Indoor Indoor v v Indoor v
|
||||
|
||||
"band 3
|
||||
5.47GHz
|
||||
~
|
||||
5.725GHz
|
||||
(DFS)" 100 5500 v v v v v v v v v v v v v
|
||||
104 5520 v v v v v v v v v v v
|
||||
108 5540 v v v v v v v v v v v v
|
||||
112 5560 v v v v v v v v v v v
|
||||
116 5580 v v v v v v v v v v v v v
|
||||
120 5600 v v v Indoor v Indoor v v v
|
||||
124 5620 v v v v Indoor v Indoor v v v
|
||||
128 5640 v v v Indoor v Indoor v v
|
||||
132 5660 v v v E v Indoor v Indoor v v
|
||||
136 5680 v v v v v v v v v
|
||||
140 5700 v v E v v v v v v v
|
||||
144 5720 E E E
|
||||
"band 4
|
||||
5.725GHz
|
||||
~
|
||||
5.85GHz
|
||||
(~5.9GHz)" 149 5745 v v v v v v v v v v v v v v
|
||||
153 5765 v v v v v v v v v v v v
|
||||
157 5785 v v v v v v v v v v v v v
|
||||
161 5805 v v v v v v v v v v v v
|
||||
165 5825 v v P P v v v v v v v v v
|
||||
169 5845 P P P
|
||||
173 5865 P P P P
|
||||
177 5885 P P P
|
||||
channel count 28 28 14 7 0 28 24 20 24 19 5 13 8 19 20 22 15 12
|
||||
E: FCC accepted the ask for CH144 from Accord. PS: 160MHz 用 80MHz+80MHz實現？ Argentina Belgium (比利時) India Israel Russia
|
||||
P: Customer's requirement from James. Australia The Netherlands (荷蘭) Mexico Turkey Ukraine
|
||||
New Zealand UK (英國) Singapore
|
||||
Brazil Switzerland (瑞士)
|
||||
|
||||
|
||||
*/
|
||||
|
||||
/*---------------------------Define Local Constant---------------------------*/
|
||||
|
||||
|
||||
/* define Maximum Power v.s each band for each region
|
||||
* ISRAEL
|
||||
* Format:
|
||||
* RT_CHANNEL_DOMAIN_Region ={{{chnl_start, chnl_end, Pwr_dB_Max}, {Chn2_Start, Chn2_end, Pwr_dB_Max}, {Chn3_Start, Chn3_end, Pwr_dB_Max}, {Chn4_Start, Chn4_end, Pwr_dB_Max}, {Chn5_Start, Chn5_end, Pwr_dB_Max}}, Limit_Num}
|
||||
* RT_CHANNEL_DOMAIN_FCC ={{{01,11,30}, {36,48,17}, {52,64,24}, {100,140,24}, {149,165,30}}, 5}
|
||||
* "NR" is non-release channle.
|
||||
* Issue--- Israel--Russia--New Zealand
|
||||
* DOMAIN_01= (2G_WORLD, 5G_NULL)
|
||||
* DOMAIN_02= (2G_ETSI1, 5G_NULL)
|
||||
* DOMAIN_03= (2G_FCC1, 5G_NULL)
|
||||
* DOMAIN_04= (2G_MKK1, 5G_NULL)
|
||||
* DOMAIN_05= (2G_ETSI2, 5G_NULL)
|
||||
* DOMAIN_06= (2G_FCC1, 5G_FCC1)
|
||||
* DOMAIN_07= (2G_WORLD, 5G_ETSI1)
|
||||
* DOMAIN_08= (2G_MKK1, 5G_MKK1)
|
||||
* DOMAIN_09= (2G_WORLD, 5G_KCC1)
|
||||
* DOMAIN_10= (2G_WORLD, 5G_FCC2)
|
||||
* DOMAIN_11= (2G_WORLD, 5G_FCC3)----india
|
||||
* DOMAIN_12= (2G_WORLD, 5G_FCC4)----Venezuela
|
||||
* DOMAIN_13= (2G_WORLD, 5G_FCC5)----China
|
||||
* DOMAIN_14= (2G_WORLD, 5G_FCC6)----Israel
|
||||
* DOMAIN_15= (2G_FCC1, 5G_FCC7)-----Canada
|
||||
* DOMAIN_16= (2G_WORLD, 5G_ETSI2)---Australia
|
||||
* DOMAIN_17= (2G_WORLD, 5G_ETSI3)---Russia
|
||||
* DOMAIN_18= (2G_MKK1, 5G_MKK2)-----Japan
|
||||
* DOMAIN_19= (2G_MKK1, 5G_MKK3)-----Japan
|
||||
* DOMAIN_20= (2G_FCC1, 5G_NCC1)-----Taiwan
|
||||
* DOMAIN_21= (2G_FCC1, 5G_NCC1)-----Taiwan */
|
||||
|
||||
|
||||
static struct _RT_CHANNEL_PLAN_MAXPWR chnl_plan_pwr_max_2g[] = {
|
||||
|
||||
/* 2G_WORLD, */
|
||||
{{1, 13, 20}, 1},
|
||||
|
||||
/* 2G_ETSI1 */
|
||||
{{1, 13, 20}, 1},
|
||||
|
||||
/* RT_CHANNEL_DOMAIN_ETSI */
|
||||
{{{1, 11, 17}, {40, 56, 17}, {60, 128, 17}, {0, 0, 0}, {149, 165, 17}}, 4},
|
||||
|
||||
/* RT_CHANNEL_DOMAIN_MKK */
|
||||
{{{1, 11, 17}, {0, 0, 0}, {0, 0, 0}, {0, 0, 0}, {0, 0, 0}}, 1},
|
||||
|
||||
/* Add new channel plan mex power table. */
|
||||
/* ...... */
|
||||
};
|
||||
|
||||
|
||||
#if 0
|
||||
/* ===========================================1:(2G_WORLD, 5G_NULL) */
|
||||
|
||||
struct _RT_CHANNEL_PLAN_MAXPWR RT_DOMAIN_01 = {{{01, 13, 20}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}}, 1}
|
||||
|
||||
/* ===========================================2:(2G_ETSI1, 5G_NULL) */
|
||||
|
||||
RT_DOMAIN_02 = {{{01, 13, 20}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}}, 1}
|
||||
|
||||
/* ===========================================3:(2G_FCC1, 5G_NULL) */
|
||||
|
||||
RT_DOMAIN_03 = {{{01, 11, 30}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}}, 1}
|
||||
|
||||
/* ===========================================4:(2G_MKK1, 5G_NULL) */
|
||||
|
||||
RT_DOMAIN_04 = {{{01, 14, 23}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}}, 1}
|
||||
|
||||
/* ===========================================5:(2G_ETSI2, 5G_NULL) */
|
||||
|
||||
RT_DOMAIN_05 = {{{10, 13, 20}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}}, 1}
|
||||
|
||||
/* ===========================================6:(2G_FCC1, 5G_FCC1) */
|
||||
|
||||
RT_DOMAIN_06 = {{{01, 13, 30}, {36, 48, 17}, {52, 64, 24}, {100, 140, 24}, {149, 165, 30}}, 5}
|
||||
|
||||
/* ===========================================7:(2G_WORLD, 5G_ETSI1) */
|
||||
|
||||
RT_DOMAIN_07 = {{{01, 13, 20}, {36, 48, 23}, {52, 64, 23}, {100, 140, 30}, {NR, NR, 0}}, 4}
|
||||
|
||||
/* ===========================================8:(2G_MKK1, 5G_MKK1) */
|
||||
|
||||
RT_DOMAIN_08 = {{{01, 14, 23}, {36, 48, 23}, {52, 64, 23}, {100, 140, 23}, {NR, NR, 0}}, 4}
|
||||
|
||||
/* ===========================================9:(2G_WORLD, 5G_KCC1) */
|
||||
|
||||
RT_DOMAIN_09 = {{{01, 13, 20}, {36, 48, 17}, {52, 64, 23}, {100, 124, 23}, {149, 165, 23}}, 5}
|
||||
|
||||
/* ===========================================10:(2G_WORLD, 5G_FCC2) */
|
||||
|
||||
RT_DOMAIN_10 = {{{01, 13, 20}, {36, 48, 17}, {NR, NR, 0}, {NR, NR, 0}, {149, 165, 30}}, 3}
|
||||
|
||||
/* ===========================================11:(2G_WORLD, 5G_FCC3) */
|
||||
RT_DOMAIN_11 = {{{01, 13, 20}, {36, 48, 23}, {52, 64, 23}, {NR, NR, 0}, {149, 165, 23}}, 4}
|
||||
|
||||
/* ===========================================12:(2G_WORLD, 5G_FCC4) */
|
||||
RT_DOMAIN_12 = {{{01, 13, 20}, {36, 48, 24}, {52, 64, 24}, {NR, NR, 0}, {149, 161, 27}}, 4}
|
||||
|
||||
/* ===========================================13:(2G_WORLD, 5G_FCC5) */
|
||||
RT_DOMAIN_13 = {{{01, 13, 20}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}, {149, 165, 27}}, 2}
|
||||
|
||||
/* ===========================================14:(2G_WORLD, 5G_FCC6) */
|
||||
RT_DOMAIN_14 = {{{01, 13, 20}, {36, 48, 17}, {52, 64, 17}, {NR, NR, 0}, {NR, NR, 0}}, 3}
|
||||
|
||||
/* ===========================================15:(2G_FCC1, 5G_FCC7) */
|
||||
RT_DOMAIN_15 = {{{01, 11, 30}, {36, 48, 23}, {52, 64, 24}, {100, 140, 24}, {149, 165, 30}}, 5}
|
||||
|
||||
/* ===========================================16:(2G_WORLD, 5G_ETSI2) */
|
||||
RT_DOMAIN_16 = {{{01, 13, 20}, {36, 48, 23}, {52, 64, 23}, {100, 140, 30}, {149, 165, 30}}, 5}
|
||||
|
||||
/* ===========================================17:(2G_WORLD, 5G_ETSI3) */
|
||||
RT_DOMAIN_17 = {{{01, 13, 20}, {36, 48, 23}, {52, 64, 23}, {100, 132, 30}, {149, 165, 20}}, 5}
|
||||
|
||||
/* ===========================================18:(2G_MKK1, 5G_MKK2) */
|
||||
RT_DOMAIN_18 = {{{01, 14, 23}, {36, 48, 23}, {52, 64, 23}, {NR, NR, 0}, {NR, NR, 0}}, 3}
|
||||
|
||||
/* ===========================================19:(2G_MKK1, 5G_MKK3) */
|
||||
RT_DOMAIN_19 = {{{01, 14, 23}, {NR, NR, 0}, {NR, NR, 0}, {100, 140, 23}, {NR, NR, 0}}, 2}
|
||||
|
||||
/* ===========================================20:(2G_FCC1, 5G_NCC1) */
|
||||
RT_DOMAIN_20 = {{{01, 11, 30}, {NR, NR, 0}, {56, 64, 23}, {100, 140, 24}, {149, 165, 30}}, 4}
|
||||
|
||||
/* ===========================================21:(2G_FCC1, 5G_NCC2) */
|
||||
RT_DOMAIN_21 = {{{01, 11, 30}, {NR, NR, 0}, {56, 64, 23}, {NR, NR, 0}, {149, 165, 30}}, 3}
|
||||
|
||||
/* ===========================================22:(2G_WORLD, 5G_FCC3) */
|
||||
RT_DOMAIN_22 = {{{01, 13, 24}, {36, 48, 20}, {52, 64, 24}, {NR, NR, 0}, {149, 165, 30}}, 4}
|
||||
|
||||
/* ===========================================23:(2G_WORLD, 5G_ETSI2) */
|
||||
RT_DOMAIN_23 = {{{01, 13, 20}, {36, 48, 23}, {52, 64, 23}, {100, 140, 30}, {149, 165, 30}}, 5}
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* counter & Realtek channel plan transfer table.
|
||||
* */
|
||||
struct _RT_CHANNEL_PLAN_COUNTRY_TRANSFER_TABLE rt_ctry_chnl_tbl[] = {
|
||||
|
||||
{
|
||||
RT_CTRY_AL, /* "Albania阿爾巴尼亞" */
|
||||
"AL",
|
||||
RT_2G_WORLD,
|
||||
RT_5G_WORLD,
|
||||
RT_CHANNEL_DOMAIN_UNDEFINED /* 2G/5G world. */
|
||||
},
|
||||
#if 0
|
||||
{
|
||||
RT_CTRY_BB, /* "Barbados巴巴多斯" */
|
||||
"BB",
|
||||
RT_2G_WORLD,
|
||||
RT_5G_NULL,
|
||||
RT_CHANNEL_DOMAIN_EFUSE_0x20 /* 2G world. 5G_NULL */
|
||||
},
|
||||
|
||||
{
|
||||
RT_CTRY_DE, /* "Germany德國" */
|
||||
"DE",
|
||||
RT_2G_WORLD,
|
||||
RT_5G_ETSI1,
|
||||
RT_CHANNEL_DOMAIN_EFUSE_0x26
|
||||
},
|
||||
|
||||
{
|
||||
RT_CTRY_US, /* "Germany德國" */
|
||||
"US",
|
||||
RT_2G_FCC1,
|
||||
RT_5G_FCC7,
|
||||
RT_CHANNEL_DOMAIN_EFUSE_0x34
|
||||
},
|
||||
|
||||
{
|
||||
RT_CTRY_JP, /* "Germany德國" */
|
||||
"JP",
|
||||
RT_2G_MKK1,
|
||||
RT_5G_MKK1,
|
||||
RT_CHANNEL_DOMAIN_EFUSE_0x34
|
||||
},
|
||||
|
||||
{
|
||||
RT_CTRY_TW, /* "Germany德國" */
|
||||
"TW",
|
||||
RT_2G_FCC1,
|
||||
RT_5G_NCC1,
|
||||
RT_CHANNEL_DOMAIN_EFUSE_0x39
|
||||
},
|
||||
#endif
|
||||
|
||||
}; /* rt_ctry_chnl_tbl */
|
||||
|
||||
/*
|
||||
* Realtek Defined channel plan.
|
||||
* */
|
||||
#if 0
|
||||
|
||||
static struct _RT_CHANNEL_PLAN_NEW rt_chnl_plan[] = {
|
||||
/* channel Plan 0x20. */
|
||||
{
|
||||
&rt_ctry_chnl_tbl[1], /* struct _RT_CHANNEL_PLAN_COUNTRY_TRANSFER_TABLE Country & channel plan transfer table. */
|
||||
RT_CHANNEL_DOMAIN_EFUSE_0x20, /* RT_CHANNEL_DOMAIN RT channel Plan Define */
|
||||
RT_2G_WORLD, /* enum rt_regulation_2g */
|
||||
RT_5G_NULL, /* enum rt_regulation_5g */
|
||||
RT_WORLD, /* enum rt_regulation_cmn RT Regulatory domain definition. */
|
||||
RT_SREQ_NA, /* RT channel plan special & customerize requirement. */
|
||||
|
||||
CHNL_RT_2G_WORLD,
|
||||
CHNL_RT_2G_WORLD_SCAN_TYPE,
|
||||
&chnl_plan_pwr_max_2g[0],
|
||||
|
||||
CHNL_RT_5G_NULL,
|
||||
CHNL_RT_5G_NULL_SCAN_TYPE,
|
||||
|
||||
|
||||
},
|
||||
|
||||
/* channel Plan 0x26. */
|
||||
{
|
||||
&rt_ctry_chnl_tbl[1], /* struct _RT_CHANNEL_PLAN_COUNTRY_TRANSFER_TABLE Country & channel plan transfer table. */
|
||||
RT_CHANNEL_DOMAIN_EFUSE_0x26, /* RT_CHANNEL_DOMAIN RT channel Plan Define */
|
||||
RT_2G_WORLD, /* enum rt_regulation_2g */
|
||||
RT_5G_ETSI1, /* enum rt_regulation_5g */
|
||||
RT_WORLD, /* enum rt_regulation_cmn RT Regulatory domain definition. */
|
||||
RT_SREQ_NA, /* RT channel plan special & customerize requirement. */
|
||||
|
||||
CHNL_RT_2G_WORLD, /* 2G workd cannel */
|
||||
CHNL_RT_2G_WORLD_SCAN_TYPE,
|
||||
&chnl_plan_pwr_max_2g[1],
|
||||
|
||||
CHNL_RT_5G_ETSI1,
|
||||
CHNL_RT_5G_ETSI1_SCAN_TYPE,
|
||||
|
||||
}
|
||||
|
||||
|
||||
};
|
||||
#endif
|
||||
682
hal/phydm/rtchnlplan.h
Normal file
682
hal/phydm/rtchnlplan.h
Normal file
|
|
@ -0,0 +1,682 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __RT_CHANNELPLAN_H__
|
||||
#define __RT_CHANNELPLAN_H__
|
||||
|
||||
enum rt_channel_domain_new {
|
||||
|
||||
/* ===== Add new channel plan above this line =============== */
|
||||
|
||||
/* For new architecture we define different 2G/5G CH area for all country. */
|
||||
/* 2.4 G only */
|
||||
RT_CHANNEL_DOMAIN_2G_WORLD_5G_NULL = 0x20,
|
||||
RT_CHANNEL_DOMAIN_2G_ETSI1_5G_NULL = 0x21,
|
||||
RT_CHANNEL_DOMAIN_2G_FCC1_5G_NULL = 0x22,
|
||||
RT_CHANNEL_DOMAIN_2G_MKK1_5G_NULL = 0x23,
|
||||
RT_CHANNEL_DOMAIN_2G_ETSI2_5G_NULL = 0x24,
|
||||
/* 2.4 G + 5G type 1 */
|
||||
RT_CHANNEL_DOMAIN_2G_FCC1_5G_FCC1 = 0x25,
|
||||
RT_CHANNEL_DOMAIN_2G_WORLD_5G_ETSI1 = 0x26,
|
||||
/* RT_CHANNEL_DOMAIN_2G_WORLD_5G_ETSI1 = 0x27, */
|
||||
/* ..... */
|
||||
|
||||
RT_CHANNEL_DOMAIN_MAX_NEW,
|
||||
|
||||
};
|
||||
|
||||
|
||||
#if 0
|
||||
#define DOMAIN_CODE_2G_WORLD \
|
||||
{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13
|
||||
#define DOMAIN_CODE_2G_ETSI1 \
|
||||
{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13
|
||||
#define DOMAIN_CODE_2G_ETSI2 \
|
||||
{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}, 11
|
||||
#define DOMAIN_CODE_2G_FCC1 \
|
||||
{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}, 14
|
||||
#define DOMAIN_CODE_2G_MKK1 \
|
||||
{10, 11, 12, 13}, 4
|
||||
|
||||
#define DOMAIN_CODE_5G_ETSI1 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 19
|
||||
#define DOMAIN_CODE_5G_ETSI2 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 24
|
||||
#define DOMAIN_CODE_5G_ETSI3 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165}, 22
|
||||
#define DOMAIN_CODE_5G_FCC1 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 24
|
||||
#define DOMAIN_CODE_5G_FCC2 \
|
||||
{36, 40, 44, 48, 149, 153, 157, 161, 165}, 9
|
||||
#define DOMAIN_CODE_5G_FCC3 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165}, 13
|
||||
#define DOMAIN_CODE_5G_FCC4 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161}, 12
|
||||
#define DOMAIN_CODE_5G_FCC5 \
|
||||
{149, 153, 157, 161, 165}, 5
|
||||
#define DOMAIN_CODE_5G_FCC6 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64}, 8
|
||||
#define DOMAIN_CODE_5G_FCC7 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 20
|
||||
#define DOMAIN_CODE_5G_IC1 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 20
|
||||
#define DOMAIN_CODE_5G_KCC1 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165}, 20
|
||||
#define DOMAIN_CODE_5G_MKK1 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 19
|
||||
#define DOMAIN_CODE_5G_MKK2 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64}, 8
|
||||
#define DOMAIN_CODE_5G_MKK3 \
|
||||
{100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 11
|
||||
#define DOMAIN_CODE_5G_NCC1 \
|
||||
{56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 24
|
||||
#define DOMAIN_CODE_5G_NCC2 \
|
||||
{56, 60, 64, 149, 153, 157, 161, 165}, 8
|
||||
#define UNDEFINED \
|
||||
{0}, 0
|
||||
#endif
|
||||
|
||||
/*
|
||||
*
|
||||
*
|
||||
*
|
||||
|
||||
Countries "Country Abbreviation" Domain Code SKU's Ch# of 20MHz
|
||||
2G 5G Ch# of 40MHz
|
||||
"Albania阿爾巴尼亞" AL Local Test
|
||||
|
||||
"Algeria阿爾及利亞" DZ CE TCF
|
||||
|
||||
"Antigua & Barbuda安提瓜島&巴布達" AG 2G_WORLD FCC TCF
|
||||
|
||||
"Argentina阿根廷" AR 2G_WORLD Local Test
|
||||
|
||||
"Armenia亞美尼亞" AM 2G_WORLD ETSI
|
||||
|
||||
"Aruba阿魯巴島" AW 2G_WORLD FCC TCF
|
||||
|
||||
"Australia澳洲" AU 2G_WORLD 5G_ETSI2
|
||||
|
||||
"Austria奧地利" AT 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Azerbaijan阿塞拜彊" AZ 2G_WORLD CE TCF
|
||||
|
||||
"Bahamas巴哈馬" BS 2G_WORLD
|
||||
|
||||
"Barbados巴巴多斯" BB 2G_WORLD FCC TCF
|
||||
|
||||
"Belgium比利時" BE 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Bermuda百慕達" BM 2G_WORLD FCC TCF
|
||||
|
||||
"Brazil巴西" BR 2G_WORLD Local Test
|
||||
|
||||
"Bulgaria保加利亞" BG 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Canada加拿大" CA 2G_FCC1 5G_FCC7 IC / FCC IC / FCC
|
||||
|
||||
"Cayman Islands開曼群島" KY 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Chile智利" CL 2G_WORLD FCC TCF
|
||||
|
||||
"China中國" CN 2G_WORLD 5G_FCC5 信部?【2002】353?
|
||||
|
||||
"Columbia哥倫比亞" CO 2G_WORLD Voluntary
|
||||
|
||||
"Costa Rica哥斯達黎加" CR 2G_WORLD FCC TCF
|
||||
|
||||
"Cyprus塞浦路斯" CY 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Czech 捷克" CZ 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Denmark丹麥" DK 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Dominican Republic多明尼加共和國" DO 2G_WORLD FCC TCF
|
||||
|
||||
"Egypt埃及" EG 2G_WORLD CE T CF
|
||||
|
||||
"El Salvador薩爾瓦多" SV 2G_WORLD Voluntary
|
||||
|
||||
"Estonia愛沙尼亞" EE 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Finland芬蘭" FI 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"France法國" FR 5G_E TSI1 CE
|
||||
|
||||
"Germany德國" DE 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Greece 希臘" GR 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Guam關島" GU 2G_WORLD
|
||||
|
||||
"Guatemala瓜地馬拉" GT 2G_WORLD
|
||||
|
||||
"Haiti海地" HT 2G_WORLD FCC TCF
|
||||
|
||||
"Honduras宏都拉斯" HN 2G_WORLD FCC TCF
|
||||
|
||||
"Hungary匈牙利" HU 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Iceland冰島" IS 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"India印度" 2G_WORLD 5G_FCC3 FCC/CE TCF
|
||||
|
||||
"Ireland愛爾蘭" IE 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Israel以色列" IL 5G_F CC6 CE TCF
|
||||
|
||||
"Italy義大利" IT 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Japan日本" JP 2G_MKK1 5G_MKK1 MKK MKK
|
||||
|
||||
"Korea韓國" KR 2G_WORLD 5G_KCC1 KCC KCC
|
||||
|
||||
"Latvia拉脫維亞" LV 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Lithuania立陶宛" LT 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Luxembourg盧森堡" LU 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Malaysia馬來西亞" MY 2G_WORLD Local Test
|
||||
|
||||
"Malta馬爾他" MT 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Mexico墨西哥" MX 2G_WORLD 5G_FCC3 Local Test
|
||||
|
||||
"Morocco摩洛哥" MA CE TCF
|
||||
|
||||
"Netherlands荷蘭" NL 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"New Zealand紐西蘭" NZ 2G_WORLD 5G_ETSI2
|
||||
|
||||
"Norway挪威" NO 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Panama巴拿馬 " PA 2G_FCC1 Voluntary
|
||||
|
||||
"Philippines菲律賓" PH 2G_WORLD FCC TCF
|
||||
|
||||
"Poland波蘭" PL 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Portugal葡萄牙" PT 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Romania羅馬尼亞" RO 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Russia俄羅斯" RU 2G_WORLD 5G_ETSI3 CE TCF
|
||||
|
||||
"Saudi Arabia沙地阿拉伯" SA 2G_WORLD CE TCF
|
||||
|
||||
"Singapore新加坡" SG 2G_WORLD
|
||||
|
||||
"Slovakia斯洛伐克" SK 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Slovenia斯洛維尼亞" SI 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"South Africa南非" ZA 2G_WORLD CE TCF
|
||||
|
||||
"Spain西班牙" ES 5G_ETSI1 CE
|
||||
|
||||
"Sweden瑞典" SE 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Switzerland瑞士" CH 2G_WORLD 5G_ETSI1 CE
|
||||
|
||||
"Taiwan臺灣" TW 2G_FCC1 5G_NCC1 NCC
|
||||
|
||||
"Thailand泰國" TH 2G_WORLD FCC/CE TCF
|
||||
|
||||
"Turkey土耳其" TR 2G_WORLD
|
||||
|
||||
"Ukraine烏克蘭" UA 2G_WORLD Local Test
|
||||
|
||||
"United Kingdom英國" GB 2G_WORLD 5G_ETSI1 CE ETSI
|
||||
|
||||
"United States美國" US 2G_FCC1 5G_FCC7 FCC FCC
|
||||
|
||||
"Venezuela委內瑞拉" VE 2G_WORLD 5G_FCC4 FCC TCF
|
||||
|
||||
"Vietnam越南" VN 2G_WORLD FCC/CE TCF
|
||||
|
||||
|
||||
|
||||
*/
|
||||
|
||||
/* counter abbervation. */
|
||||
enum rt_country_name {
|
||||
RT_CTRY_AL, /* "Albania阿爾巴尼亞" */
|
||||
RT_CTRY_DZ, /* "Algeria阿爾及利亞" */
|
||||
RT_CTRY_AG, /* "Antigua & Barbuda安提瓜島&巴布達" */
|
||||
RT_CTRY_AR, /* "Argentina阿根廷" */
|
||||
RT_CTRY_AM, /* "Armenia亞美尼亞" */
|
||||
RT_CTRY_AW, /* "Aruba阿魯巴島" */
|
||||
RT_CTRY_AU, /* "Australia澳洲" */
|
||||
RT_CTRY_AT, /* "Austria奧地利" */
|
||||
RT_CTRY_AZ, /* "Azerbaijan阿塞拜彊" */
|
||||
RT_CTRY_BS, /* "Bahamas巴哈馬" */
|
||||
RT_CTRY_BB, /* "Barbados巴巴多斯" */
|
||||
RT_CTRY_BE, /* "Belgium比利時" */
|
||||
RT_CTRY_BM, /* "Bermuda百慕達" */
|
||||
RT_CTRY_BR, /* "Brazil巴西" */
|
||||
RT_CTRY_BG, /* "Bulgaria保加利亞" */
|
||||
RT_CTRY_CA, /* "Canada加拿大" */
|
||||
RT_CTRY_KY, /* "Cayman Islands開曼群島" */
|
||||
RT_CTRY_CL, /* "Chile智利" */
|
||||
RT_CTRY_CN, /* "China中國" */
|
||||
RT_CTRY_CO, /* "Columbia哥倫比亞" */
|
||||
RT_CTRY_CR, /* "Costa Rica哥斯達黎加" */
|
||||
RT_CTRY_CY, /* "Cyprus塞浦路斯" */
|
||||
RT_CTRY_CZ, /* "Czech 捷克" */
|
||||
RT_CTRY_DK, /* "Denmark丹麥" */
|
||||
RT_CTRY_DO, /* "Dominican Republic多明尼加共和國" */
|
||||
RT_CTRY_CE, /* "Egypt埃及" EG 2G_WORLD */
|
||||
RT_CTRY_SV, /* "El Salvador薩爾瓦多" */
|
||||
RT_CTRY_EE, /* "Estonia愛沙尼亞" */
|
||||
RT_CTRY_FI, /* "Finland芬蘭" */
|
||||
RT_CTRY_FR, /* "France法國" */
|
||||
RT_CTRY_DE, /* "Germany德國" */
|
||||
RT_CTRY_GR, /* "Greece 希臘" */
|
||||
RT_CTRY_GU, /* "Guam關島" */
|
||||
RT_CTRY_GT, /* "Guatemala瓜地馬拉" */
|
||||
RT_CTRY_HT, /* "Haiti海地" */
|
||||
RT_CTRY_HN, /* "Honduras宏都拉斯" */
|
||||
RT_CTRY_HU, /* "Hungary匈牙利" */
|
||||
RT_CTRY_IS, /* "Iceland冰島" */
|
||||
RT_CTRY_IN, /* "India印度" */
|
||||
RT_CTRY_IE, /* "Ireland愛爾蘭" */
|
||||
RT_CTRY_IL, /* "Israel以色列" */
|
||||
RT_CTRY_IT, /* "Italy義大利" */
|
||||
RT_CTRY_JP, /* "Japan日本" */
|
||||
RT_CTRY_KR, /* "Korea韓國" */
|
||||
RT_CTRY_LV, /* "Latvia拉脫維亞" */
|
||||
RT_CTRY_LT, /* "Lithuania立陶宛" */
|
||||
RT_CTRY_LU, /* "Luxembourg盧森堡" */
|
||||
RT_CTRY_MY, /* "Malaysia馬來西亞" */
|
||||
RT_CTRY_MT, /* "Malta馬爾他" */
|
||||
RT_CTRY_MX, /* "Mexico墨西哥" */
|
||||
RT_CTRY_MA, /* "Morocco摩洛哥" */
|
||||
RT_CTRY_NL, /* "Netherlands荷蘭" */
|
||||
RT_CTRY_NZ, /* "New Zealand紐西蘭" */
|
||||
RT_CTRY_NO, /* "Norway挪威" */
|
||||
RT_CTRY_PA, /* "Panama巴拿馬 " */
|
||||
RT_CTRY_PH, /* "Philippines菲律賓" */
|
||||
RT_CTRY_PL, /* "Poland波蘭" */
|
||||
RT_CTRY_PT, /* "Portugal葡萄牙" */
|
||||
RT_CTRY_RO, /* "Romania羅馬尼亞" */
|
||||
RT_CTRY_RU, /* "Russia俄羅斯" */
|
||||
RT_CTRY_SA, /* "Saudi Arabia沙地阿拉伯" */
|
||||
RT_CTRY_SG, /* "Singapore新加坡" */
|
||||
RT_CTRY_SK, /* "Slovakia斯洛伐克" */
|
||||
RT_CTRY_SI, /* "Slovenia斯洛維尼亞" */
|
||||
RT_CTRY_ZA, /* "South Africa南非" */
|
||||
RT_CTRY_ES, /* "Spain西班牙" */
|
||||
RT_CTRY_SE, /* "Sweden瑞典" */
|
||||
RT_CTRY_CH, /* "Switzerland瑞士" */
|
||||
RT_CTRY_TW, /* "Taiwan臺灣" */
|
||||
RT_CTRY_TH, /* "Thailand泰國" */
|
||||
RT_CTRY_TR, /* "Turkey土耳其" */
|
||||
RT_CTRY_UA, /* "Ukraine烏克蘭" */
|
||||
RT_CTRY_GB, /* "United Kingdom英國" */
|
||||
RT_CTRY_US, /* "United States美國" */
|
||||
RT_CTRY_VE, /* "Venezuela委內瑞拉" */
|
||||
RT_CTRY_VN, /* "Vietnam越南" */
|
||||
RT_CTRY_MAX,
|
||||
|
||||
};
|
||||
|
||||
/* Scan type including active and passive scan. */
|
||||
enum rt_scan_type_new {
|
||||
SCAN_NULL,
|
||||
SCAN_ACT,
|
||||
SCAN_PAS,
|
||||
SCAN_BOTH,
|
||||
};
|
||||
|
||||
|
||||
/* Power table sample. */
|
||||
|
||||
struct _RT_CHNL_PLAN_LIMIT {
|
||||
u16 chnl_start;
|
||||
u16 chnl_end;
|
||||
|
||||
u16 freq_start;
|
||||
u16 freq_end;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* 2.4G Regulatory Domains
|
||||
* */
|
||||
enum rt_regulation_2g {
|
||||
RT_2G_NULL,
|
||||
RT_2G_WORLD,
|
||||
RT_2G_ETSI1,
|
||||
RT_2G_FCC1,
|
||||
RT_2G_MKK1,
|
||||
RT_2G_ETSI2
|
||||
|
||||
};
|
||||
|
||||
|
||||
/* typedef struct _RT_CHANNEL_BEHAVIOR
|
||||
* {
|
||||
* u8 chnl;
|
||||
* enum rt_scan_type_new
|
||||
*
|
||||
* }RT_CHANNEL_BEHAVIOR, *PRT_CHANNEL_BEHAVIOR; */
|
||||
|
||||
/* typedef struct _RT_CHANNEL_PLAN_TYPE
|
||||
* {
|
||||
* RT_CHANNEL_BEHAVIOR
|
||||
* u8 Chnl_num;
|
||||
* }RT_CHNL_PLAN_TYPE, *PRT_CHNL_PLAN_TYPE; */
|
||||
|
||||
/*
|
||||
* 2.4G channel number
|
||||
* channel definition & number
|
||||
* */
|
||||
#define CHNL_RT_2G_NULL \
|
||||
{0}, 0
|
||||
#define CHNL_RT_2G_WORLD \
|
||||
{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13
|
||||
#define CHNL_RT_2G_WORLD_TEST \
|
||||
{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13
|
||||
|
||||
#define CHNL_RT_2G_EFSI1 \
|
||||
{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13
|
||||
#define CHNL_RT_2G_FCC1 \
|
||||
{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}, 11
|
||||
#define CHNL_RT_2G_MKK1 \
|
||||
{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}, 14
|
||||
#define CHNL_RT_2G_ETSI2 \
|
||||
{10, 11, 12, 13}, 4
|
||||
|
||||
/*
|
||||
* 2.4G channel active or passive scan.
|
||||
* */
|
||||
#define CHNL_RT_2G_NULL_SCAN_TYPE \
|
||||
{SCAN_NULL}
|
||||
#define CHNL_RT_2G_WORLD_SCAN_TYPE \
|
||||
{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0}
|
||||
#define CHNL_RT_2G_EFSI1_SCAN_TYPE \
|
||||
{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
|
||||
#define CHNL_RT_2G_FCC1_SCAN_TYPE \
|
||||
{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
|
||||
#define CHNL_RT_2G_MKK1_SCAN_TYPE \
|
||||
{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
|
||||
#define CHNL_RT_2G_ETSI2_SCAN_TYPE \
|
||||
{1, 1, 1, 1}
|
||||
|
||||
|
||||
/*
|
||||
* 2.4G band & Frequency Section
|
||||
* Freqency start & end / band number
|
||||
* */
|
||||
#define FREQ_RT_2G_NULL \
|
||||
{0}, 0
|
||||
/* Passive scan CH 12, 13 */
|
||||
#define FREQ_RT_2G_WORLD \
|
||||
{2412, 2472}, 1
|
||||
#define FREQ_RT_2G_EFSI1 \
|
||||
{2412, 2472}, 1
|
||||
#define FREQ_RT_2G_FCC1 \
|
||||
{2412, 2462}, 1
|
||||
#define FREQ_RT_2G_MKK1 \
|
||||
{2412, 2484}, 1
|
||||
#define FREQ_RT_2G_ETSI2 \
|
||||
{2457, 2472}, 1
|
||||
|
||||
|
||||
/*
|
||||
* 5G Regulatory Domains
|
||||
* */
|
||||
enum rt_regulation_5g {
|
||||
RT_5G_NULL,
|
||||
RT_5G_WORLD,
|
||||
RT_5G_ETSI1,
|
||||
RT_5G_ETSI2,
|
||||
RT_5G_ETSI3,
|
||||
RT_5G_FCC1,
|
||||
RT_5G_FCC2,
|
||||
RT_5G_FCC3,
|
||||
RT_5G_FCC4,
|
||||
RT_5G_FCC5,
|
||||
RT_5G_FCC6,
|
||||
RT_5G_FCC7,
|
||||
RT_5G_IC1,
|
||||
RT_5G_KCC1,
|
||||
RT_5G_MKK1,
|
||||
RT_5G_MKK2,
|
||||
RT_5G_MKK3,
|
||||
RT_5G_NCC1,
|
||||
|
||||
};
|
||||
|
||||
/*
|
||||
* 5G channel number
|
||||
* */
|
||||
#define CHNL_RT_5G_NULL \
|
||||
{0}, 0
|
||||
#define CHNL_RT_5G_WORLD \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 19
|
||||
#define CHNL_RT_5G_ETSI1 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 24
|
||||
#define CHNL_RT_5G_ETSI2 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165}, 22
|
||||
#define CHNL_RT_5G_ETSI3 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 24
|
||||
#define CHNL_RT_5G_FCC1 \
|
||||
{36, 40, 44, 48, 149, 153, 157, 161, 165}, 9
|
||||
#define CHNL_RT_5G_FCC2 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165}, 13
|
||||
#define CHNL_RT_5G_FCC3 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161}, 12
|
||||
#define CHNL_RT_5G_FCC4 \
|
||||
{149, 153, 157, 161, 165}, 5
|
||||
#define CHNL_RT_5G_FCC5 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64}, 8
|
||||
#define CHNL_RT_5G_FCC6 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 20
|
||||
#define CHNL_RT_5G_FCC7 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 20
|
||||
#define CHNL_RT_5G_IC1 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165}, 20
|
||||
#define CHNL_RT_5G_KCC1 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 19
|
||||
#define CHNL_RT_5G_MKK1 \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64}, 8
|
||||
#define CHNL_RT_5G_MKK2 \
|
||||
{100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 11
|
||||
#define CHNL_RT_5G_MKK3 \
|
||||
{56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 24
|
||||
#define CHNL_RT_5G_NCC1 \
|
||||
{56, 60, 64, 149, 153, 157, 161, 165}, 8
|
||||
|
||||
/*
|
||||
* 5G channel active or passive scan.
|
||||
* */
|
||||
#define CHNL_RT_5G_NULL_SCAN_TYPE \
|
||||
{SCAN_NULL}
|
||||
#define CHNL_RT_5G_WORLD_SCAN_TYPE \
|
||||
{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
|
||||
#define CHNL_RT_5G_ETSI1_SCAN_TYPE \
|
||||
{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
|
||||
#define CHNL_RT_5G_ETSI2_SCAN_TYPE \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165}, 22
|
||||
#define CHNL_RT_5G_ETSI3_SCAN_TYPE \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 24
|
||||
#define CHNL_RT_5G_FCC1_SCAN_TYPE \
|
||||
{36, 40, 44, 48, 149, 153, 157, 161, 165}, 9
|
||||
#define CHNL_RT_5G_FCC2_SCAN_TYPE \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165}, 13
|
||||
#define CHNL_RT_5G_FCC3_SCAN_TYPE \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161}, 12
|
||||
#define CHNL_RT_5G_FCC4_SCAN_TYPE \
|
||||
{149, 153, 157, 161, 165}, 5
|
||||
#define CHNL_RT_5G_FCC5_SCAN_TYPE \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64}, 8
|
||||
#define CHNL_RT_5G_FCC6_SCAN_TYPE \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 20
|
||||
#define CHNL_RT_5G_FCC7_SCAN_TYPE \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 20
|
||||
#define CHNL_RT_5G_IC1_SCAN_TYPE \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165}, 20
|
||||
#define CHNL_RT_5G_KCC1_SCAN_TYPE \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 19
|
||||
#define CHNL_RT_5G_MKK1_SCAN_TYPE \
|
||||
{36, 40, 44, 48, 52, 56, 60, 64}, 8
|
||||
#define CHNL_RT_5G_MKK2_SCAN_TYPE \
|
||||
{100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 11
|
||||
#define CHNL_RT_5G_MKK3_SCAN_TYPE \
|
||||
{56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 24
|
||||
#define CHNL_RT_5G_NCC1_SCAN_TYPE \
|
||||
{56, 60, 64, 149, 153, 157, 161, 165}, 8
|
||||
|
||||
/*
|
||||
* Global regulation
|
||||
* */
|
||||
enum rt_regulation_cmn {
|
||||
RT_WORLD,
|
||||
RT_FCC,
|
||||
RT_MKK,
|
||||
RT_ETSI,
|
||||
RT_IC,
|
||||
RT_CE,
|
||||
RT_NCC,
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Special requirement for different regulation domain.
|
||||
* For internal test or customerize special request.
|
||||
* */
|
||||
enum rt_chnlplan_sreq {
|
||||
RT_SREQ_NA = 0x0,
|
||||
RT_SREQ_2G_ADHOC_11N = 0x00000001,
|
||||
RT_SREQ_2G_ADHOC_11B = 0x00000002,
|
||||
RT_SREQ_2G_ALL_PASS = 0x00000004,
|
||||
RT_SREQ_2G_ALL_ACT = 0x00000008,
|
||||
RT_SREQ_5G_ADHOC_11N = 0x00000010,
|
||||
RT_SREQ_5G_ADHOC_11AC = 0x00000020,
|
||||
RT_SREQ_5G_ALL_PASS = 0x00000040,
|
||||
RT_SREQ_5G_ALL_ACT = 0x00000080,
|
||||
RT_SREQ_C1_PLAN = 0x00000100,
|
||||
RT_SREQ_C2_PLAN = 0x00000200,
|
||||
RT_SREQ_C3_PLAN = 0x00000400,
|
||||
RT_SREQ_C4_PLAN = 0x00000800,
|
||||
RT_SREQ_NFC_ON = 0x00001000,
|
||||
RT_SREQ_MASK = 0x0000FFFF, /* Requirements bit mask */
|
||||
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* enum rt_country_name & enum rt_regulation_2g & enum rt_regulation_5g transfer table
|
||||
*
|
||||
* */
|
||||
struct _RT_CHANNEL_PLAN_COUNTRY_TRANSFER_TABLE {
|
||||
/* */
|
||||
/* Define countery domain and corresponding */
|
||||
/* */
|
||||
enum rt_country_name country_enum;
|
||||
char country_name[3];
|
||||
|
||||
/* char Domain_Name[12]; */
|
||||
enum rt_regulation_2g domain_2g;
|
||||
|
||||
enum rt_regulation_5g domain_5g;
|
||||
|
||||
RT_CHANNEL_DOMAIN rt_ch_domain;
|
||||
/* u8 Country_Area; */
|
||||
|
||||
};
|
||||
|
||||
|
||||
#define RT_MAX_CHNL_NUM_2G 13
|
||||
#define RT_MAX_CHNL_NUM_5G 44
|
||||
|
||||
/* Power table sample. */
|
||||
|
||||
struct _RT_CHNL_PLAN_PWR_LIMIT {
|
||||
u16 chnl_start;
|
||||
u16 chnl_end;
|
||||
u8 db_max;
|
||||
u16 m_w_max;
|
||||
};
|
||||
|
||||
|
||||
#define RT_MAX_BAND_NUM 5
|
||||
|
||||
struct _RT_CHANNEL_PLAN_MAXPWR {
|
||||
/* STRING_T */
|
||||
struct _RT_CHNL_PLAN_PWR_LIMIT chnl[RT_MAX_BAND_NUM];
|
||||
u8 band_useful_num;
|
||||
|
||||
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Power By rate Table.
|
||||
* */
|
||||
|
||||
|
||||
|
||||
struct _RT_CHANNEL_PLAN_NEW {
|
||||
/* */
|
||||
/* Define countery domain and corresponding */
|
||||
/* */
|
||||
/* char country_name[36]; */
|
||||
/* u8 country_enum; */
|
||||
|
||||
/* char Domain_Name[12]; */
|
||||
|
||||
|
||||
struct _RT_CHANNEL_PLAN_COUNTRY_TRANSFER_TABLE *p_ctry_transfer;
|
||||
|
||||
RT_CHANNEL_DOMAIN rt_ch_domain;
|
||||
|
||||
enum rt_regulation_2g domain_2g;
|
||||
|
||||
enum rt_regulation_5g domain_5g;
|
||||
|
||||
enum rt_regulation_cmn regulator;
|
||||
|
||||
enum rt_chnlplan_sreq chnl_sreq;
|
||||
|
||||
/* struct _RT_CHNL_PLAN_LIMIT RtChnl; */
|
||||
|
||||
u8 chnl_2g[MAX_CHANNEL_NUM]; /* CHNL_RT_2G_WORLD */
|
||||
u8 len_2g;
|
||||
u8 chnl_2g_scan_tp[MAX_CHANNEL_NUM]; /* CHNL_RT_2G_WORLD_SCAN_TYPE */
|
||||
/* u8 Freq2G[2]; */ /* FREQ_RT_2G_WORLD */
|
||||
|
||||
u8 chnl_5g[MAX_CHANNEL_NUM];
|
||||
u8 len_5g;
|
||||
u8 chnl_5g_scan_tp[MAX_CHANNEL_NUM];
|
||||
/* u8 Freq2G[2]; */ /* FREQ_RT_2G_WORLD */
|
||||
|
||||
struct _RT_CHANNEL_PLAN_MAXPWR chnl_max_pwr;
|
||||
|
||||
|
||||
};
|
||||
|
||||
|
||||
#endif /* __RT_CHANNELPLAN_H__ */
|
||||
1417
hal/phydm/rtl8188e/hal8188erateadaptive.c
Normal file
1417
hal/phydm/rtl8188e/hal8188erateadaptive.c
Normal file
File diff suppressed because it is too large
Load diff
110
hal/phydm/rtl8188e/hal8188erateadaptive.h
Normal file
110
hal/phydm/rtl8188e/hal8188erateadaptive.h
Normal file
|
|
@ -0,0 +1,110 @@
|
|||
#ifndef __INC_RA_H
|
||||
#define __INC_RA_H
|
||||
/*++
|
||||
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
|
||||
|
||||
Module Name:
|
||||
rate_adaptive.h
|
||||
|
||||
Abstract:
|
||||
Prototype of RA and related data structure.
|
||||
|
||||
Major Change History:
|
||||
When Who What
|
||||
---------- --------------- -------------------------------
|
||||
2011-08-12 Page Create.
|
||||
--*/
|
||||
|
||||
/* rate adaptive define */
|
||||
#define PERENTRY 23
|
||||
#define RETRYSIZE 5
|
||||
#define RATESIZE 28
|
||||
#define TX_RPT2_ITEM_SIZE 8
|
||||
|
||||
#define DM_RA_RATE_UP 1
|
||||
#define DM_RA_RATE_DOWN 2
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
|
||||
/*
|
||||
* TX report 2 format in Rx desc
|
||||
* */
|
||||
#define GET_TX_RPT2_DESC_PKT_LEN_88E(__prx_status_desc) LE_BITS_TO_4BYTE(__prx_status_desc, 0, 9)
|
||||
#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__prx_status_desc) LE_BITS_TO_4BYTE(__prx_status_desc+16, 0, 32)
|
||||
#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__prx_status_desc) LE_BITS_TO_4BYTE(__prx_status_desc+20, 0, 32)
|
||||
|
||||
#define GET_TX_REPORT_TYPE1_RERTY_0(__paddr) LE_BITS_TO_4BYTE(__paddr, 0, 16)
|
||||
#define GET_TX_REPORT_TYPE1_RERTY_1(__paddr) LE_BITS_TO_1BYTE(__paddr+2, 0, 8)
|
||||
#define GET_TX_REPORT_TYPE1_RERTY_2(__paddr) LE_BITS_TO_1BYTE(__paddr+3, 0, 8)
|
||||
#define GET_TX_REPORT_TYPE1_RERTY_3(__paddr) LE_BITS_TO_1BYTE(__paddr+4, 0, 8)
|
||||
#define GET_TX_REPORT_TYPE1_RERTY_4(__paddr) LE_BITS_TO_1BYTE(__paddr+4+1, 0, 8)
|
||||
#define GET_TX_REPORT_TYPE1_DROP_0(__paddr) LE_BITS_TO_1BYTE(__paddr+4+2, 0, 8)
|
||||
#define GET_TX_REPORT_TYPE1_DROP_1(__paddr) LE_BITS_TO_1BYTE(__paddr+4+3, 0, 8)
|
||||
#endif
|
||||
|
||||
/* End rate adaptive define */
|
||||
|
||||
void
|
||||
odm_ra_support_init(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
int
|
||||
odm_ra_info_init_all(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
int
|
||||
odm_ra_info_init(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 mac_id
|
||||
);
|
||||
|
||||
u8
|
||||
odm_ra_get_sgi_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 mac_id
|
||||
);
|
||||
|
||||
u8
|
||||
odm_ra_get_decision_rate_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 mac_id
|
||||
);
|
||||
|
||||
u8
|
||||
odm_ra_get_hw_pwr_status_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 mac_id
|
||||
);
|
||||
void
|
||||
odm_ra_update_rate_info_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 mac_id,
|
||||
u8 rate_id,
|
||||
u32 rate_mask,
|
||||
u8 sgi_enable
|
||||
);
|
||||
|
||||
void
|
||||
odm_ra_set_rssi_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 mac_id,
|
||||
u8 rssi
|
||||
);
|
||||
|
||||
void
|
||||
odm_ra_tx_rpt2_handle_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 *tx_rpt_buf,
|
||||
u16 tx_rpt_len,
|
||||
u32 mac_id_valid_entry0,
|
||||
u32 mac_id_valid_entry1
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
odm_ra_set_tx_rpt_time(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u16 min_rpt_time
|
||||
);
|
||||
#endif
|
||||
64
hal/phydm/rtl8188e/hal8188ereg.h
Normal file
64
hal/phydm/rtl8188e/hal8188ereg.h
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
/* ************************************************************
|
||||
* File Name: hal8188ereg.h
|
||||
*
|
||||
* Description:
|
||||
*
|
||||
* This file is for RTL8188E register definition.
|
||||
*
|
||||
*
|
||||
* ************************************************************ */
|
||||
#ifndef __HAL_8188E_REG_H__
|
||||
#define __HAL_8188E_REG_H__
|
||||
|
||||
/*
|
||||
* Register Definition
|
||||
* */
|
||||
#define TRX_ANTDIV_PATH 0x860
|
||||
#define RX_ANTDIV_PATH 0xb2c
|
||||
#define ODM_R_A_AGC_CORE1_8188E 0xc50
|
||||
|
||||
#define REG_GPIO_EXT_CTRL 0x0060
|
||||
|
||||
#define REG_MCUFWDL_8188E 0x0080
|
||||
#define REG_FW_DBG_STATUS_8188E 0x0088
|
||||
#define REG_FW_DBG_CTRL_8188E 0x008F
|
||||
|
||||
#define REG_CR_8188E 0x0100
|
||||
|
||||
|
||||
/*
|
||||
* Bitmap Definition
|
||||
* */
|
||||
#define BIT_FA_RESET_8188E BIT(0)
|
||||
#define REG_ADAPTIVE_DATA_RATE_0 0x2B0
|
||||
#define REG_DBI_WDATA_8188 0x0348 /* DBI Write data */
|
||||
#define REG_DBI_RDATA_8188 0x034C /* DBI Read data */
|
||||
#define REG_DBI_ADDR_8188 0x0350 /* DBI Address */
|
||||
#define REG_DBI_FLAG_8188 0x0352 /* DBI Read/Write Flag */
|
||||
#define REG_MDIO_WDATA_8188E 0x0354 /* MDIO for Write PCIE PHY */
|
||||
#define REG_MDIO_RDATA_8188E 0x0356 /* MDIO for Reads PCIE PHY */
|
||||
#define REG_MDIO_CTL_8188E 0x0358 /* MDIO for Control */
|
||||
|
||||
/* [0-63] */
|
||||
#define REG_MACID_NO_LINK 0x484 /* No Link register (bit[x] enabled means dropping packets for MACID in HW queue) */
|
||||
|
||||
#endif
|
||||
1764
hal/phydm/rtl8188e/halhwimg8188e_bb.c
Normal file
1764
hal/phydm/rtl8188e/halhwimg8188e_bb.c
Normal file
File diff suppressed because it is too large
Load diff
58
hal/phydm/rtl8188e/halhwimg8188e_bb.h
Normal file
58
hal/phydm/rtl8188e/halhwimg8188e_bb.h
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*Image2HeaderVersion: 2.18*/
|
||||
#if (RTL8188E_SUPPORT == 1)
|
||||
#ifndef __INC_MP_BB_HW_IMG_8188E_H
|
||||
#define __INC_MP_BB_HW_IMG_8188E_H
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* AGC_TAB.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
odm_read_and_config_mp_8188e_agc_tab(/* TC: Test Chip, MP: MP Chip*/
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
u32 odm_get_version_mp_8188e_agc_tab(void);
|
||||
|
||||
/******************************************************************************
|
||||
* PHY_REG.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
odm_read_and_config_mp_8188e_phy_reg(/* TC: Test Chip, MP: MP Chip*/
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
u32 odm_get_version_mp_8188e_phy_reg(void);
|
||||
|
||||
/******************************************************************************
|
||||
* PHY_REG_PG.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
odm_read_and_config_mp_8188e_phy_reg_pg(/* TC: Test Chip, MP: MP Chip*/
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
u32 odm_get_version_mp_8188e_phy_reg_pg(void);
|
||||
|
||||
#endif
|
||||
#endif /* end of HWIMG_SUPPORT*/
|
||||
288
hal/phydm/rtl8188e/halhwimg8188e_mac.c
Normal file
288
hal/phydm/rtl8188e/halhwimg8188e_mac.c
Normal file
|
|
@ -0,0 +1,288 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*Image2HeaderVersion: 2.18*/
|
||||
#include "mp_precomp.h"
|
||||
#include "../phydm_precomp.h"
|
||||
|
||||
#if (RTL8188E_SUPPORT == 1)
|
||||
static bool
|
||||
check_positive(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
const u32 condition1,
|
||||
const u32 condition2,
|
||||
const u32 condition3,
|
||||
const u32 condition4
|
||||
)
|
||||
{
|
||||
u8 _board_type = ((p_dm_odm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
|
||||
((p_dm_odm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
|
||||
((p_dm_odm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
|
||||
((p_dm_odm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
|
||||
((p_dm_odm->board_type & BIT(2)) >> 2) << 4; /* _BT*/
|
||||
|
||||
u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
|
||||
u32 driver1 = p_dm_odm->cut_version << 24 |
|
||||
(p_dm_odm->support_interface & 0xF0) << 16 |
|
||||
p_dm_odm->support_platform << 16 |
|
||||
p_dm_odm->package_type << 12 |
|
||||
(p_dm_odm->support_interface & 0x0F) << 8 |
|
||||
_board_type;
|
||||
|
||||
u32 driver2 = (p_dm_odm->type_glna & 0xFF) << 0 |
|
||||
(p_dm_odm->type_gpa & 0xFF) << 8 |
|
||||
(p_dm_odm->type_alna & 0xFF) << 16 |
|
||||
(p_dm_odm->type_apa & 0xFF) << 24;
|
||||
|
||||
u32 driver3 = 0;
|
||||
|
||||
u32 driver4 = (p_dm_odm->type_glna & 0xFF00) >> 8 |
|
||||
(p_dm_odm->type_gpa & 0xFF00) |
|
||||
(p_dm_odm->type_alna & 0xFF00) << 8 |
|
||||
(p_dm_odm->type_apa & 0xFF00) << 16;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
|
||||
("===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
|
||||
("===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4));
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
|
||||
(" (Platform, Interface) = (0x%X, 0x%X)\n", p_dm_odm->support_platform, p_dm_odm->support_interface));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
|
||||
(" (Board, Package) = (0x%X, 0x%X)\n", p_dm_odm->board_type, p_dm_odm->package_type));
|
||||
|
||||
|
||||
/*============== value Defined Check ===============*/
|
||||
/*QFN type [15:12] and cut version [27:24] need to do value check*/
|
||||
|
||||
if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
|
||||
return false;
|
||||
if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
|
||||
return false;
|
||||
|
||||
/*=============== Bit Defined Check ================*/
|
||||
/* We don't care [31:28] */
|
||||
|
||||
cond1 &= 0x00FF0FFF;
|
||||
driver1 &= 0x00FF0FFF;
|
||||
|
||||
if ((cond1 & driver1) == cond1) {
|
||||
u32 bit_mask = 0;
|
||||
|
||||
if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
|
||||
return true;
|
||||
|
||||
if ((cond1 & BIT(0)) != 0) /*GLNA*/
|
||||
bit_mask |= 0x000000FF;
|
||||
if ((cond1 & BIT(1)) != 0) /*GPA*/
|
||||
bit_mask |= 0x0000FF00;
|
||||
if ((cond1 & BIT(2)) != 0) /*ALNA*/
|
||||
bit_mask |= 0x00FF0000;
|
||||
if ((cond1 & BIT(3)) != 0) /*APA*/
|
||||
bit_mask |= 0xFF000000;
|
||||
|
||||
if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask))) /* board_type of each RF path is matched*/
|
||||
return true;
|
||||
else
|
||||
return false;
|
||||
} else
|
||||
return false;
|
||||
}
|
||||
static bool
|
||||
check_negative(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
const u32 condition1,
|
||||
const u32 condition2
|
||||
)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* MAC_REG.TXT
|
||||
******************************************************************************/
|
||||
|
||||
u32 array_mp_8188e_mac_reg[] = {
|
||||
0x026, 0x00000041,
|
||||
0x027, 0x00000035,
|
||||
0x80000002, 0x00000000, 0x40000000, 0x00000000,
|
||||
0x040, 0x0000000C,
|
||||
0x90000001, 0x00000000, 0x40000000, 0x00000000,
|
||||
0x040, 0x0000000C,
|
||||
0x90000001, 0x00000001, 0x40000000, 0x00000000,
|
||||
0x040, 0x0000000C,
|
||||
0x90000001, 0x00000002, 0x40000000, 0x00000000,
|
||||
0x040, 0x0000000C,
|
||||
0xA0000000, 0x00000000,
|
||||
0x040, 0x00000000,
|
||||
0xB0000000, 0x00000000,
|
||||
0x421, 0x0000000F,
|
||||
0x428, 0x0000000A,
|
||||
0x429, 0x00000010,
|
||||
0x430, 0x00000000,
|
||||
0x431, 0x00000001,
|
||||
0x432, 0x00000002,
|
||||
0x433, 0x00000004,
|
||||
0x434, 0x00000005,
|
||||
0x435, 0x00000006,
|
||||
0x436, 0x00000007,
|
||||
0x437, 0x00000008,
|
||||
0x438, 0x00000000,
|
||||
0x439, 0x00000000,
|
||||
0x43A, 0x00000001,
|
||||
0x43B, 0x00000002,
|
||||
0x43C, 0x00000004,
|
||||
0x43D, 0x00000005,
|
||||
0x43E, 0x00000006,
|
||||
0x43F, 0x00000007,
|
||||
0x440, 0x0000005D,
|
||||
0x441, 0x00000001,
|
||||
0x442, 0x00000000,
|
||||
0x444, 0x00000015,
|
||||
0x445, 0x000000F0,
|
||||
0x446, 0x0000000F,
|
||||
0x447, 0x00000000,
|
||||
0x458, 0x00000041,
|
||||
0x459, 0x000000A8,
|
||||
0x45A, 0x00000072,
|
||||
0x45B, 0x000000B9,
|
||||
0x460, 0x00000066,
|
||||
0x461, 0x00000066,
|
||||
0x480, 0x00000008,
|
||||
0x4C8, 0x000000FF,
|
||||
0x4C9, 0x00000008,
|
||||
0x4CC, 0x000000FF,
|
||||
0x4CD, 0x000000FF,
|
||||
0x4CE, 0x00000001,
|
||||
0x4D3, 0x00000001,
|
||||
0x500, 0x00000026,
|
||||
0x501, 0x000000A2,
|
||||
0x502, 0x0000002F,
|
||||
0x503, 0x00000000,
|
||||
0x504, 0x00000028,
|
||||
0x505, 0x000000A3,
|
||||
0x506, 0x0000005E,
|
||||
0x507, 0x00000000,
|
||||
0x508, 0x0000002B,
|
||||
0x509, 0x000000A4,
|
||||
0x50A, 0x0000005E,
|
||||
0x50B, 0x00000000,
|
||||
0x50C, 0x0000004F,
|
||||
0x50D, 0x000000A4,
|
||||
0x50E, 0x00000000,
|
||||
0x50F, 0x00000000,
|
||||
0x512, 0x0000001C,
|
||||
0x514, 0x0000000A,
|
||||
0x516, 0x0000000A,
|
||||
0x525, 0x0000004F,
|
||||
0x550, 0x00000010,
|
||||
0x551, 0x00000010,
|
||||
0x559, 0x00000002,
|
||||
0x55D, 0x000000FF,
|
||||
0x605, 0x00000030,
|
||||
0x608, 0x0000000E,
|
||||
0x609, 0x0000002A,
|
||||
0x620, 0x000000FF,
|
||||
0x621, 0x000000FF,
|
||||
0x622, 0x000000FF,
|
||||
0x623, 0x000000FF,
|
||||
0x624, 0x000000FF,
|
||||
0x625, 0x000000FF,
|
||||
0x626, 0x000000FF,
|
||||
0x627, 0x000000FF,
|
||||
0x63C, 0x00000008,
|
||||
0x63D, 0x00000008,
|
||||
0x63E, 0x0000000C,
|
||||
0x63F, 0x0000000C,
|
||||
0x640, 0x00000040,
|
||||
0x652, 0x00000020,
|
||||
0x66E, 0x00000005,
|
||||
0x700, 0x00000021,
|
||||
0x701, 0x00000043,
|
||||
0x702, 0x00000065,
|
||||
0x703, 0x00000087,
|
||||
0x708, 0x00000021,
|
||||
0x709, 0x00000043,
|
||||
0x70A, 0x00000065,
|
||||
0x70B, 0x00000087,
|
||||
|
||||
};
|
||||
|
||||
void
|
||||
odm_read_and_config_mp_8188e_mac_reg(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
)
|
||||
{
|
||||
u32 i = 0;
|
||||
u8 c_cond;
|
||||
bool is_matched = true, is_skipped = false;
|
||||
u32 array_len = sizeof(array_mp_8188e_mac_reg) / sizeof(u32);
|
||||
u32 *array = array_mp_8188e_mac_reg;
|
||||
|
||||
u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8188e_mac_reg\n"));
|
||||
|
||||
while ((i + 1) < array_len) {
|
||||
v1 = array[i];
|
||||
v2 = array[i + 1];
|
||||
|
||||
if (v1 & (BIT(31) | BIT30)) {/*positive & negative condition*/
|
||||
if (v1 & BIT(31)) {/* positive condition*/
|
||||
c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
|
||||
if (c_cond == COND_ENDIF) {/*end*/
|
||||
is_matched = true;
|
||||
is_skipped = false;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n"));
|
||||
} else if (c_cond == COND_ELSE) { /*else*/
|
||||
is_matched = is_skipped ? false : true;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n"));
|
||||
} else {/*if , else if*/
|
||||
pre_v1 = v1;
|
||||
pre_v2 = v2;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n"));
|
||||
}
|
||||
} else if (v1 & BIT(30)) { /*negative condition*/
|
||||
if (is_skipped == false) {
|
||||
if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) {
|
||||
is_matched = true;
|
||||
is_skipped = true;
|
||||
} else {
|
||||
is_matched = false;
|
||||
is_skipped = false;
|
||||
}
|
||||
} else
|
||||
is_matched = false;
|
||||
}
|
||||
} else {
|
||||
if (is_matched)
|
||||
odm_config_mac_8188e(p_dm_odm, v1, (u8)v2);
|
||||
}
|
||||
i = i + 2;
|
||||
}
|
||||
}
|
||||
|
||||
u32
|
||||
odm_get_version_mp_8188e_mac_reg(void)
|
||||
{
|
||||
return 70;
|
||||
}
|
||||
|
||||
#endif /* end of HWIMG_SUPPORT*/
|
||||
38
hal/phydm/rtl8188e/halhwimg8188e_mac.h
Normal file
38
hal/phydm/rtl8188e/halhwimg8188e_mac.h
Normal file
|
|
@ -0,0 +1,38 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*Image2HeaderVersion: 2.18*/
|
||||
#if (RTL8188E_SUPPORT == 1)
|
||||
#ifndef __INC_MP_MAC_HW_IMG_8188E_H
|
||||
#define __INC_MP_MAC_HW_IMG_8188E_H
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* MAC_REG.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
odm_read_and_config_mp_8188e_mac_reg(/* TC: Test Chip, MP: MP Chip*/
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
u32 odm_get_version_mp_8188e_mac_reg(void);
|
||||
|
||||
#endif
|
||||
#endif /* end of HWIMG_SUPPORT*/
|
||||
2370
hal/phydm/rtl8188e/halhwimg8188e_rf.c
Normal file
2370
hal/phydm/rtl8188e/halhwimg8188e_rf.c
Normal file
File diff suppressed because it is too large
Load diff
128
hal/phydm/rtl8188e/halhwimg8188e_rf.h
Normal file
128
hal/phydm/rtl8188e/halhwimg8188e_rf.h
Normal file
|
|
@ -0,0 +1,128 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*Image2HeaderVersion: 2.18*/
|
||||
#if (RTL8188E_SUPPORT == 1)
|
||||
#ifndef __INC_MP_RF_HW_IMG_8188E_H
|
||||
#define __INC_MP_RF_HW_IMG_8188E_H
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* RadioA.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
odm_read_and_config_mp_8188e_radioa(/* TC: Test Chip, MP: MP Chip*/
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
u32 odm_get_version_mp_8188e_radioa(void);
|
||||
|
||||
/******************************************************************************
|
||||
* TxPowerTrack_AP.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
odm_read_and_config_mp_8188e_txpowertrack_ap(/* TC: Test Chip, MP: MP Chip*/
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
u32 odm_get_version_mp_8188e_txpowertrack_ap(void);
|
||||
|
||||
/******************************************************************************
|
||||
* TxPowerTrack_PCIE.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
odm_read_and_config_mp_8188e_txpowertrack_pcie(/* TC: Test Chip, MP: MP Chip*/
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
u32 odm_get_version_mp_8188e_txpowertrack_pcie(void);
|
||||
|
||||
/******************************************************************************
|
||||
* TxPowerTrack_PCIE_ICUT.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
odm_read_and_config_mp_8188e_txpowertrack_pcie_icut(/* TC: Test Chip, MP: MP Chip*/
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
u32 odm_get_version_mp_8188e_txpowertrack_pcie_icut(void);
|
||||
|
||||
/******************************************************************************
|
||||
* TxPowerTrack_SDIO.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
odm_read_and_config_mp_8188e_txpowertrack_sdio(/* TC: Test Chip, MP: MP Chip*/
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
u32 odm_get_version_mp_8188e_txpowertrack_sdio(void);
|
||||
|
||||
/******************************************************************************
|
||||
* TxPowerTrack_SDIO_ICUT.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
odm_read_and_config_mp_8188e_txpowertrack_sdio_icut(/* TC: Test Chip, MP: MP Chip*/
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
u32 odm_get_version_mp_8188e_txpowertrack_sdio_icut(void);
|
||||
|
||||
/******************************************************************************
|
||||
* TxPowerTrack_USB.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
odm_read_and_config_mp_8188e_txpowertrack_usb(/* TC: Test Chip, MP: MP Chip*/
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
u32 odm_get_version_mp_8188e_txpowertrack_usb(void);
|
||||
|
||||
/******************************************************************************
|
||||
* TxPowerTrack_USB_ICUT.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
odm_read_and_config_mp_8188e_txpowertrack_usb_icut(/* TC: Test Chip, MP: MP Chip*/
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
u32 odm_get_version_mp_8188e_txpowertrack_usb_icut(void);
|
||||
|
||||
/******************************************************************************
|
||||
* TXPWR_LMT.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
odm_read_and_config_mp_8188e_txpwr_lmt(/* TC: Test Chip, MP: MP Chip*/
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
u32 odm_get_version_mp_8188e_txpwr_lmt(void);
|
||||
|
||||
/******************************************************************************
|
||||
* TXPWR_LMT_88EE_M2_for_MSI.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
odm_read_and_config_mp_8188e_txpwr_lmt_88e_e_m2_for_msi(/* TC: Test Chip, MP: MP Chip*/
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
u32 odm_get_version_mp_8188e_txpwr_lmt_88ee_m2_for_msi(void);
|
||||
|
||||
#endif
|
||||
#endif /* end of HWIMG_SUPPORT*/
|
||||
3647
hal/phydm/rtl8188e/halhwimg8188e_s_fw.c
Normal file
3647
hal/phydm/rtl8188e/halhwimg8188e_s_fw.c
Normal file
File diff suppressed because it is too large
Load diff
61
hal/phydm/rtl8188e/halhwimg8188e_s_fw.h
Normal file
61
hal/phydm/rtl8188e/halhwimg8188e_s_fw.h
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*Image2HeaderVersion: 2.16*/
|
||||
#if (RTL8188E_S_SUPPORT == 1)
|
||||
#ifndef __INC_MP_FW_HW_IMG_8188E_S_H
|
||||
#define __INC_MP_FW_HW_IMG_8188E_S_H
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* FW_AP.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
odm_read_firmware_mp_8188e_s_fw_ap(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 *p_firmware,
|
||||
u32 *p_firmware_size
|
||||
);
|
||||
|
||||
/******************************************************************************
|
||||
* FW_NIC.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
odm_read_firmware_mp_8188e_s_fw_nic(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 *p_firmware,
|
||||
u32 *p_firmware_size
|
||||
);
|
||||
|
||||
/******************************************************************************
|
||||
* FW_WoWLAN.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
odm_read_firmware_mp_8188e_s_fw_wowlan(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 *p_firmware,
|
||||
u32 *p_firmware_size
|
||||
);
|
||||
|
||||
#endif
|
||||
#endif /* end of HWIMG_SUPPORT*/
|
||||
3901
hal/phydm/rtl8188e/halhwimg8188e_t_fw.c
Normal file
3901
hal/phydm/rtl8188e/halhwimg8188e_t_fw.c
Normal file
File diff suppressed because it is too large
Load diff
72
hal/phydm/rtl8188e/halhwimg8188e_t_fw.h
Normal file
72
hal/phydm/rtl8188e/halhwimg8188e_t_fw.h
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*Image2HeaderVersion: 2.16*/
|
||||
#if (RTL8188E_T_SUPPORT == 1)
|
||||
#ifndef __INC_MP_FW_HW_IMG_8188E_T_H
|
||||
#define __INC_MP_FW_HW_IMG_8188E_T_H
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* FW_AP.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
odm_read_firmware_mp_8188e_t_fw_ap(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 *p_firmware,
|
||||
u32 *p_firmware_size
|
||||
);
|
||||
|
||||
/******************************************************************************
|
||||
* FW_NIC.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
odm_read_firmware_mp_8188e_t_fw_nic(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 *p_firmware,
|
||||
u32 *p_firmware_size
|
||||
);
|
||||
|
||||
/******************************************************************************
|
||||
* FW_NIC_89EM.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
odm_read_firmware_mp_8188e_t_fw_nic_89e_m(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 *p_firmware,
|
||||
u32 *p_firmware_size
|
||||
);
|
||||
|
||||
/******************************************************************************
|
||||
* FW_WoWLAN.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
odm_read_firmware_mp_8188e_t_fw_wowlan(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 *p_firmware,
|
||||
u32 *p_firmware_size
|
||||
);
|
||||
|
||||
#endif
|
||||
#endif /* end of HWIMG_SUPPORT*/
|
||||
2996
hal/phydm/rtl8188e/halphyrf_8188e_ap.c
Normal file
2996
hal/phydm/rtl8188e/halphyrf_8188e_ap.c
Normal file
File diff suppressed because it is too large
Load diff
135
hal/phydm/rtl8188e/halphyrf_8188e_ap.h
Normal file
135
hal/phydm/rtl8188e/halphyrf_8188e_ap.h
Normal file
|
|
@ -0,0 +1,135 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HAL_PHY_RF_8188E_H__
|
||||
#define __HAL_PHY_RF_8188E_H__
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
#define IQK_DELAY_TIME_88E 10 /* ms */
|
||||
#define index_mapping_NUM_88E 15
|
||||
#define AVG_THERMAL_NUM_88E 4
|
||||
|
||||
#include "../halphyrf_ap.h"
|
||||
|
||||
void configure_txpower_track_8188e(
|
||||
struct _TXPWRTRACK_CFG *p_config
|
||||
);
|
||||
|
||||
void do_iqk_8188e(
|
||||
void *p_dm_void,
|
||||
u8 delta_thermal_index,
|
||||
u8 thermal_value,
|
||||
u8 threshold
|
||||
);
|
||||
|
||||
void
|
||||
odm_tx_pwr_track_set_pwr88_e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
enum pwrtrack_method method,
|
||||
u8 rf_path,
|
||||
u8 channel_mapped_index
|
||||
);
|
||||
|
||||
/* 1 7. IQK */
|
||||
|
||||
void
|
||||
phy_iq_calibrate_8188e(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#else
|
||||
struct _ADAPTER *adapter,
|
||||
#endif
|
||||
bool is_recovery);
|
||||
|
||||
|
||||
/*
|
||||
* LC calibrate
|
||||
* */
|
||||
void
|
||||
phy_lc_calibrate_8188e(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
#else
|
||||
struct _ADAPTER *p_adapter
|
||||
#endif
|
||||
);
|
||||
|
||||
/*
|
||||
* AP calibrate
|
||||
* */
|
||||
void
|
||||
phy_ap_calibrate_8188e(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#else
|
||||
struct _ADAPTER *p_adapter,
|
||||
#endif
|
||||
s8 delta);
|
||||
void
|
||||
phy_digital_predistortion_8188e(struct _ADAPTER *p_adapter);
|
||||
|
||||
|
||||
void
|
||||
_phy_save_adda_registers(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#else
|
||||
struct _ADAPTER *p_adapter,
|
||||
#endif
|
||||
u32 *adda_reg,
|
||||
u32 *adda_backup,
|
||||
u32 register_num
|
||||
);
|
||||
|
||||
void
|
||||
_phy_path_adda_on(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#else
|
||||
struct _ADAPTER *p_adapter,
|
||||
#endif
|
||||
u32 *adda_reg,
|
||||
bool is_path_a_on,
|
||||
bool is2T
|
||||
);
|
||||
|
||||
void
|
||||
_phy_mac_setting_calibration(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#else
|
||||
struct _ADAPTER *p_adapter,
|
||||
#endif
|
||||
u32 *mac_reg,
|
||||
u32 *mac_backup
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
_phy_path_a_stand_by(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
#else
|
||||
struct _ADAPTER *p_adapter
|
||||
#endif
|
||||
);
|
||||
|
||||
|
||||
#endif /* #ifndef __HAL_PHY_RF_8188E_H__ */
|
||||
3150
hal/phydm/rtl8188e/halphyrf_8188e_ce.c
Normal file
3150
hal/phydm/rtl8188e/halphyrf_8188e_ce.c
Normal file
File diff suppressed because it is too large
Load diff
142
hal/phydm/rtl8188e/halphyrf_8188e_ce.h
Normal file
142
hal/phydm/rtl8188e/halphyrf_8188e_ce.h
Normal file
|
|
@ -0,0 +1,142 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HAL_PHY_RF_8188E_H__
|
||||
#define __HAL_PHY_RF_8188E_H__
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
#define IQK_DELAY_TIME_88E 10 /* ms */
|
||||
#define index_mapping_NUM_88E 15
|
||||
#define AVG_THERMAL_NUM_88E 4
|
||||
|
||||
#include "../halphyrf_ce.h"
|
||||
|
||||
void configure_txpower_track_8188e(
|
||||
struct _TXPWRTRACK_CFG *p_config
|
||||
);
|
||||
|
||||
void
|
||||
get_delta_swing_table_8188e(
|
||||
void *p_dm_void,
|
||||
u8 **temperature_up_a,
|
||||
u8 **temperature_down_a,
|
||||
u8 **temperature_up_b,
|
||||
u8 **temperature_down_b
|
||||
);
|
||||
|
||||
void do_iqk_8188e(
|
||||
void *p_dm_void,
|
||||
u8 delta_thermal_index,
|
||||
u8 thermal_value,
|
||||
u8 threshold
|
||||
);
|
||||
|
||||
void
|
||||
odm_tx_pwr_track_set_pwr88_e(
|
||||
void *p_dm_void,
|
||||
enum pwrtrack_method method,
|
||||
u8 rf_path,
|
||||
u8 channel_mapped_index
|
||||
);
|
||||
|
||||
/* 1 7. IQK */
|
||||
|
||||
void
|
||||
phy_iq_calibrate_8188e(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#else
|
||||
struct _ADAPTER *adapter,
|
||||
#endif
|
||||
bool is_recovery);
|
||||
|
||||
|
||||
/*
|
||||
* LC calibrate
|
||||
* */
|
||||
void
|
||||
phy_lc_calibrate_8188e(
|
||||
void *p_dm_void
|
||||
);
|
||||
#if 0
|
||||
/*
|
||||
* AP calibrate
|
||||
* */
|
||||
void
|
||||
phy_ap_calibrate_8188e(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#else
|
||||
struct _ADAPTER *p_adapter,
|
||||
#endif
|
||||
s8 delta);
|
||||
#endif
|
||||
|
||||
void
|
||||
phy_digital_predistortion_8188e(struct _ADAPTER *p_adapter);
|
||||
|
||||
|
||||
void
|
||||
_phy_save_adda_registers(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#else
|
||||
struct _ADAPTER *p_adapter,
|
||||
#endif
|
||||
u32 *adda_reg,
|
||||
u32 *adda_backup,
|
||||
u32 register_num
|
||||
);
|
||||
|
||||
void
|
||||
_phy_path_adda_on(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#else
|
||||
struct _ADAPTER *p_adapter,
|
||||
#endif
|
||||
u32 *adda_reg,
|
||||
bool is_path_a_on,
|
||||
bool is2T
|
||||
);
|
||||
|
||||
void
|
||||
_phy_mac_setting_calibration(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#else
|
||||
struct _ADAPTER *p_adapter,
|
||||
#endif
|
||||
u32 *mac_reg,
|
||||
u32 *mac_backup
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
_phy_path_a_stand_by(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
#else
|
||||
struct _ADAPTER *p_adapter
|
||||
#endif
|
||||
);
|
||||
|
||||
|
||||
#endif /* #ifndef __HAL_PHY_RF_8188E_H__ */
|
||||
3189
hal/phydm/rtl8188e/halphyrf_8188e_win.c
Normal file
3189
hal/phydm/rtl8188e/halphyrf_8188e_win.c
Normal file
File diff suppressed because it is too large
Load diff
143
hal/phydm/rtl8188e/halphyrf_8188e_win.h
Normal file
143
hal/phydm/rtl8188e/halphyrf_8188e_win.h
Normal file
|
|
@ -0,0 +1,143 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HAL_PHY_RF_8188E_H__
|
||||
#define __HAL_PHY_RF_8188E_H__
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
#define IQK_DELAY_TIME_88E 15 /* ms */
|
||||
#define IQK_DELAY_TIME_8723B 10 /* ms */
|
||||
|
||||
#define index_mapping_NUM_88E 15
|
||||
#define AVG_THERMAL_NUM_88E 4
|
||||
|
||||
#include "halphyrf_win.h"
|
||||
|
||||
void configure_txpower_track_8188e(
|
||||
struct _TXPWRTRACK_CFG *p_config
|
||||
);
|
||||
|
||||
void
|
||||
get_delta_swing_table_8188e(
|
||||
void *p_dm_void,
|
||||
u8 **temperature_up_a,
|
||||
u8 **temperature_down_a,
|
||||
u8 **temperature_up_b,
|
||||
u8 **temperature_down_b
|
||||
);
|
||||
|
||||
void do_iqk_8188e(
|
||||
void *p_dm_void,
|
||||
u8 delta_thermal_index,
|
||||
u8 thermal_value,
|
||||
u8 threshold
|
||||
);
|
||||
|
||||
void
|
||||
odm_tx_pwr_track_set_pwr88_e(
|
||||
void *p_dm_void,
|
||||
enum pwrtrack_method method,
|
||||
u8 rf_path,
|
||||
u8 channel_mapped_index
|
||||
);
|
||||
|
||||
/* 1 7. IQK */
|
||||
|
||||
void
|
||||
phy_iq_calibrate_8188e(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#else
|
||||
struct _ADAPTER *adapter,
|
||||
#endif
|
||||
bool is_recovery);
|
||||
|
||||
|
||||
/*
|
||||
* LC calibrate
|
||||
* */
|
||||
void
|
||||
phy_lc_calibrate_8188e(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
/*
|
||||
* AP calibrate
|
||||
* */
|
||||
void
|
||||
phy_ap_calibrate_8188e(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#else
|
||||
struct _ADAPTER *p_adapter,
|
||||
#endif
|
||||
s8 delta);
|
||||
void
|
||||
phy_digital_predistortion_8188e(struct _ADAPTER *p_adapter);
|
||||
|
||||
#define phy_dp_calibrate_8821a phy_dp_calibrate_8812a
|
||||
|
||||
void
|
||||
_phy_save_adda_registers(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#else
|
||||
struct _ADAPTER *p_adapter,
|
||||
#endif
|
||||
u32 *adda_reg,
|
||||
u32 *adda_backup,
|
||||
u32 register_num
|
||||
);
|
||||
|
||||
void
|
||||
_phy_path_adda_on(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#else
|
||||
struct _ADAPTER *p_adapter,
|
||||
#endif
|
||||
u32 *adda_reg,
|
||||
bool is_path_a_on,
|
||||
bool is2T
|
||||
);
|
||||
|
||||
void
|
||||
_phy_mac_setting_calibration(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#else
|
||||
struct _ADAPTER *p_adapter,
|
||||
#endif
|
||||
u32 *mac_reg,
|
||||
u32 *mac_backup
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
_phy_path_a_stand_by(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
#else
|
||||
struct _ADAPTER *p_adapter
|
||||
#endif
|
||||
);
|
||||
|
||||
|
||||
#endif /* #ifndef __HAL_PHY_RF_8188E_H__ */
|
||||
219
hal/phydm/rtl8188e/phydm_regconfig8188e.c
Normal file
219
hal/phydm/rtl8188e/phydm_regconfig8188e.c
Normal file
|
|
@ -0,0 +1,219 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "mp_precomp.h"
|
||||
|
||||
#include "../phydm_precomp.h"
|
||||
|
||||
#if (RTL8188E_SUPPORT == 1)
|
||||
|
||||
void
|
||||
odm_config_rf_reg_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 addr,
|
||||
u32 data,
|
||||
enum odm_rf_radio_path_e RF_PATH,
|
||||
u32 reg_addr
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#ifndef SMP_SYNC
|
||||
unsigned long x;
|
||||
#endif
|
||||
struct rtl8192cd_priv *priv = p_dm_odm->priv;
|
||||
#endif
|
||||
|
||||
if (addr == 0xffe) {
|
||||
#ifdef CONFIG_LONG_DELAY_ISSUE
|
||||
ODM_sleep_ms(50);
|
||||
#else
|
||||
ODM_delay_ms(50);
|
||||
#endif
|
||||
} else if (addr == 0xfd)
|
||||
ODM_delay_ms(5);
|
||||
else if (addr == 0xfc)
|
||||
ODM_delay_ms(1);
|
||||
else if (addr == 0xfb)
|
||||
ODM_delay_us(50);
|
||||
else if (addr == 0xfa)
|
||||
ODM_delay_us(5);
|
||||
else if (addr == 0xf9)
|
||||
ODM_delay_us(1);
|
||||
else {
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
SAVE_INT_AND_CLI(x);
|
||||
odm_set_rf_reg(p_dm_odm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
|
||||
RESTORE_INT(x);
|
||||
#else
|
||||
odm_set_rf_reg(p_dm_odm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
|
||||
#endif
|
||||
/* Add 1us delay between BB/RF register setting. */
|
||||
ODM_delay_us(1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_config_rf_radio_a_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 addr,
|
||||
u32 data
|
||||
)
|
||||
{
|
||||
u32 content = 0x1000; /* RF_Content: radioa_txt */
|
||||
u32 maskfor_phy_set = (u32)(content & 0xE000);
|
||||
|
||||
odm_config_rf_reg_8188e(p_dm_odm, addr, data, ODM_RF_PATH_A, addr | maskfor_phy_set);
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n", addr, data));
|
||||
}
|
||||
|
||||
void
|
||||
odm_config_rf_radio_b_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 addr,
|
||||
u32 data
|
||||
)
|
||||
{
|
||||
u32 content = 0x1001; /* RF_Content: radiob_txt */
|
||||
u32 maskfor_phy_set = (u32)(content & 0xE000);
|
||||
|
||||
odm_config_rf_reg_8188e(p_dm_odm, addr, data, ODM_RF_PATH_B, addr | maskfor_phy_set);
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n", addr, data));
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
odm_config_mac_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 addr,
|
||||
u8 data
|
||||
)
|
||||
{
|
||||
odm_write_1byte(p_dm_odm, addr, data);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n", addr, data));
|
||||
}
|
||||
|
||||
void
|
||||
odm_config_bb_agc_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 addr,
|
||||
u32 bitmask,
|
||||
u32 data
|
||||
)
|
||||
{
|
||||
odm_set_bb_reg(p_dm_odm, addr, bitmask, data);
|
||||
/* Add 1us delay between BB/RF register setting. */
|
||||
ODM_delay_us(1);
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n", addr, data));
|
||||
}
|
||||
|
||||
void
|
||||
odm_config_bb_phy_reg_pg_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 band,
|
||||
u32 rf_path,
|
||||
u32 tx_num,
|
||||
u32 addr,
|
||||
u32 bitmask,
|
||||
u32 data
|
||||
)
|
||||
{
|
||||
if (addr == 0xfe) {
|
||||
#ifdef CONFIG_LONG_DELAY_ISSUE
|
||||
ODM_sleep_ms(50);
|
||||
#else
|
||||
ODM_delay_ms(50);
|
||||
#endif
|
||||
} else if (addr == 0xfd)
|
||||
ODM_delay_ms(5);
|
||||
else if (addr == 0xfc)
|
||||
ODM_delay_ms(1);
|
||||
else if (addr == 0xfb)
|
||||
ODM_delay_us(50);
|
||||
else if (addr == 0xfa)
|
||||
ODM_delay_us(5);
|
||||
else if (addr == 0xf9)
|
||||
ODM_delay_us(1);
|
||||
else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n", addr, bitmask, data));
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE&ODM_AP)
|
||||
phy_store_tx_power_by_rate(p_dm_odm->adapter, band, rf_path, tx_num, addr, bitmask, data);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
odm_config_bb_txpwr_lmt_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 *regulation,
|
||||
u8 *band,
|
||||
u8 *bandwidth,
|
||||
u8 *rate_section,
|
||||
u8 *rf_path,
|
||||
u8 *channel,
|
||||
u8 *power_limit
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
phy_set_tx_power_limit(p_dm_odm, regulation, band,
|
||||
bandwidth, rate_section, rf_path, channel, power_limit);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
odm_config_bb_phy_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 addr,
|
||||
u32 bitmask,
|
||||
u32 data
|
||||
)
|
||||
{
|
||||
if (addr == 0xfe) {
|
||||
#ifdef CONFIG_LONG_DELAY_ISSUE
|
||||
ODM_sleep_ms(50);
|
||||
#else
|
||||
ODM_delay_ms(50);
|
||||
#endif
|
||||
} else if (addr == 0xfd)
|
||||
ODM_delay_ms(5);
|
||||
else if (addr == 0xfc)
|
||||
ODM_delay_ms(1);
|
||||
else if (addr == 0xfb)
|
||||
ODM_delay_us(50);
|
||||
else if (addr == 0xfa)
|
||||
ODM_delay_us(5);
|
||||
else if (addr == 0xf9)
|
||||
ODM_delay_us(1);
|
||||
else {
|
||||
if (addr == 0xa24)
|
||||
p_dm_odm->rf_calibrate_info.rega24 = data;
|
||||
odm_set_bb_reg(p_dm_odm, addr, bitmask, data);
|
||||
|
||||
/* Add 1us delay between BB/RF register setting. */
|
||||
ODM_delay_us(1);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X\n", addr, data));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
95
hal/phydm/rtl8188e/phydm_regconfig8188e.h
Normal file
95
hal/phydm/rtl8188e/phydm_regconfig8188e.h
Normal file
|
|
@ -0,0 +1,95 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __INC_ODM_REGCONFIG_H_8188E
|
||||
#define __INC_ODM_REGCONFIG_H_8188E
|
||||
|
||||
#if (RTL8188E_SUPPORT == 1)
|
||||
|
||||
void
|
||||
odm_config_rf_reg_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 addr,
|
||||
u32 data,
|
||||
enum odm_rf_radio_path_e RF_PATH,
|
||||
u32 reg_addr
|
||||
);
|
||||
|
||||
void
|
||||
odm_config_rf_radio_a_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 addr,
|
||||
u32 data
|
||||
);
|
||||
|
||||
void
|
||||
odm_config_rf_radio_b_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 addr,
|
||||
u32 data
|
||||
);
|
||||
|
||||
void
|
||||
odm_config_mac_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 addr,
|
||||
u8 data
|
||||
);
|
||||
|
||||
void
|
||||
odm_config_bb_agc_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 addr,
|
||||
u32 bitmask,
|
||||
u32 data
|
||||
);
|
||||
|
||||
void
|
||||
odm_config_bb_phy_reg_pg_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 band,
|
||||
u32 rf_path,
|
||||
u32 tx_num,
|
||||
u32 addr,
|
||||
u32 bitmask,
|
||||
u32 data
|
||||
);
|
||||
|
||||
void
|
||||
odm_config_bb_phy_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 addr,
|
||||
u32 bitmask,
|
||||
u32 data
|
||||
);
|
||||
|
||||
void
|
||||
odm_config_bb_txpwr_lmt_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 *regulation,
|
||||
u8 *band,
|
||||
u8 *bandwidth,
|
||||
u8 *rate_section,
|
||||
u8 *rf_path,
|
||||
u8 *channel,
|
||||
u8 *power_limit
|
||||
);
|
||||
|
||||
#endif
|
||||
#endif /* end of SUPPORT */
|
||||
388
hal/phydm/rtl8188e/phydm_rtl8188e.c
Normal file
388
hal/phydm/rtl8188e/phydm_rtl8188e.c
Normal file
|
|
@ -0,0 +1,388 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* ************************************************************
|
||||
* include files
|
||||
* ************************************************************ */
|
||||
|
||||
#include "mp_precomp.h"
|
||||
|
||||
#include "../phydm_precomp.h"
|
||||
|
||||
#if (RTL8188E_SUPPORT == 1)
|
||||
|
||||
void
|
||||
odm_dig_lower_bound_88e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
)
|
||||
{
|
||||
struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table;
|
||||
|
||||
if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) {
|
||||
p_dm_dig_table->rx_gain_range_min = (u8) p_dm_dig_table->ant_div_rssi_max;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_dig_lower_bound_88e(): p_dm_dig_table->ant_div_rssi_max=%d\n", p_dm_dig_table->ant_div_rssi_max));
|
||||
}
|
||||
/* If only one Entry connected */
|
||||
}
|
||||
|
||||
/*=============================================================
|
||||
* AntDiv Before Link
|
||||
===============================================================*/
|
||||
void
|
||||
odm_sw_ant_div_reset_before_link(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
)
|
||||
{
|
||||
|
||||
struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table;
|
||||
|
||||
p_dm_swat_table->swas_no_link_state = 0;
|
||||
|
||||
}
|
||||
|
||||
|
||||
/* 3============================================================
|
||||
* 3 Dynamic Primary CCA
|
||||
* 3============================================================ */
|
||||
|
||||
void
|
||||
odm_primary_cca_init(
|
||||
struct PHY_DM_STRUCT *p_dm_odm)
|
||||
{
|
||||
struct _dynamic_primary_cca *primary_cca = &(p_dm_odm->dm_pri_cca);
|
||||
primary_cca->dup_rts_flag = 0;
|
||||
primary_cca->intf_flag = 0;
|
||||
primary_cca->intf_type = 0;
|
||||
primary_cca->monitor_flag = 0;
|
||||
primary_cca->pri_cca_flag = 0;
|
||||
}
|
||||
|
||||
bool
|
||||
odm_dynamic_primary_cca_dup_rts(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
)
|
||||
{
|
||||
struct _dynamic_primary_cca *primary_cca = &(p_dm_odm->dm_pri_cca);
|
||||
|
||||
return primary_cca->dup_rts_flag;
|
||||
}
|
||||
|
||||
void
|
||||
odm_dynamic_primary_cca(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
)
|
||||
{
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_CE)
|
||||
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter; /* for NIC */
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
|
||||
struct sta_info *p_entry;
|
||||
#endif
|
||||
|
||||
struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT);
|
||||
struct _dynamic_primary_cca *primary_cca = &(p_dm_odm->dm_pri_cca);
|
||||
|
||||
bool is_40mhz;
|
||||
bool client_40mhz = false, client_tmp = false; /* connected client BW */
|
||||
bool is_connected = false; /* connected or not */
|
||||
static u8 client_40mhz_pre = 0;
|
||||
static u64 last_tx_ok_cnt = 0;
|
||||
static u64 last_rx_ok_cnt = 0;
|
||||
static u32 counter = 0;
|
||||
static u8 delay = 1;
|
||||
u64 cur_tx_ok_cnt;
|
||||
u64 cur_rx_ok_cnt;
|
||||
u8 sec_ch_offset;
|
||||
u8 i;
|
||||
|
||||
if (!(p_dm_odm->support_ability & ODM_BB_PRIMARY_CCA))
|
||||
return;
|
||||
|
||||
if (p_dm_odm->support_ic_type != ODM_RTL8188E)
|
||||
return;
|
||||
|
||||
is_40mhz = *(p_dm_odm->p_band_width);
|
||||
sec_ch_offset = *(p_dm_odm->p_sec_ch_offset);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Second CH Offset = %d\n", sec_ch_offset));
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
if (is_40mhz == 1)
|
||||
sec_ch_offset = sec_ch_offset % 2 + 1; /* NIC's definition is reverse to AP 1:secondary below, 2: secondary above */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Second CH Offset = %d\n", sec_ch_offset));
|
||||
/* 3 Check Current WLAN Traffic */
|
||||
cur_tx_ok_cnt = adapter->TxStats.NumTxBytesUnicast - last_tx_ok_cnt;
|
||||
cur_rx_ok_cnt = adapter->RxStats.NumRxBytesUnicast - last_rx_ok_cnt;
|
||||
last_tx_ok_cnt = adapter->TxStats.NumTxBytesUnicast;
|
||||
last_rx_ok_cnt = adapter->RxStats.NumRxBytesUnicast;
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
/* 3 Check Current WLAN Traffic */
|
||||
cur_tx_ok_cnt = *(p_dm_odm->p_num_tx_bytes_unicast) - last_tx_ok_cnt;
|
||||
cur_rx_ok_cnt = *(p_dm_odm->p_num_rx_bytes_unicast) - last_rx_ok_cnt;
|
||||
last_tx_ok_cnt = *(p_dm_odm->p_num_tx_bytes_unicast);
|
||||
last_rx_ok_cnt = *(p_dm_odm->p_num_rx_bytes_unicast);
|
||||
#endif
|
||||
|
||||
/* ==================Debug Message==================== */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("TP = %llu\n", cur_tx_ok_cnt + cur_rx_ok_cnt));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("is_40mhz = %d\n", is_40mhz));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("BW_LSC = %d\n", false_alm_cnt->cnt_bw_lsc));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("BW_USC = %d\n", false_alm_cnt->cnt_bw_usc));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCA OFDM = %d\n", false_alm_cnt->cnt_ofdm_cca));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCA CCK = %d\n", false_alm_cnt->cnt_cck_cca));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("OFDM FA = %d\n", false_alm_cnt->cnt_ofdm_fail));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCK FA = %d\n", false_alm_cnt->cnt_cck_fail));
|
||||
/* ================================================ */
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
if (ACTING_AS_AP(adapter)) /* primary cca process only do at AP mode */
|
||||
#endif
|
||||
{
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("ACTING as AP mode=%d\n", ACTING_AS_AP(adapter)));
|
||||
/* 3 To get entry's connection and BW infomation status. */
|
||||
for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) {
|
||||
if (IsAPModeExist(adapter) && GetFirstExtAdapter(adapter) != NULL)
|
||||
p_entry = AsocEntry_EnumStation(GetFirstExtAdapter(adapter), i);
|
||||
else
|
||||
p_entry = AsocEntry_EnumStation(GetDefaultAdapter(adapter), i);
|
||||
if (p_entry != NULL) {
|
||||
client_tmp = p_entry->BandWidth; /* client BW */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Client_BW=%d\n", client_tmp));
|
||||
if (client_tmp > client_40mhz)
|
||||
client_40mhz = client_tmp; /* 40M/20M coexist => 40M priority is High */
|
||||
|
||||
if (p_entry->bAssociated) {
|
||||
is_connected = true; /* client is connected or not */
|
||||
break;
|
||||
}
|
||||
} else
|
||||
break;
|
||||
}
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
/* 3 To get entry's connection and BW infomation status. */
|
||||
|
||||
struct sta_info *pstat;
|
||||
|
||||
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
|
||||
pstat = p_dm_odm->p_odm_sta_info[i];
|
||||
if (IS_STA_VALID(pstat)) {
|
||||
client_tmp = pstat->tx_bw;
|
||||
if (client_tmp > client_40mhz)
|
||||
client_40mhz = client_tmp; /* 40M/20M coexist => 40M priority is High */
|
||||
|
||||
is_connected = true;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("is_connected=%d\n", is_connected));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Is Client 40MHz=%d\n", client_40mhz));
|
||||
/* 1 Monitor whether the interference exists or not */
|
||||
if (primary_cca->monitor_flag == 1) {
|
||||
if (sec_ch_offset == 1) { /* secondary channel is below the primary channel */
|
||||
if ((false_alm_cnt->cnt_ofdm_cca > 500) && (false_alm_cnt->cnt_bw_lsc > false_alm_cnt->cnt_bw_usc + 500)) {
|
||||
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1) {
|
||||
primary_cca->intf_type = 1;
|
||||
primary_cca->pri_cca_flag = 1;
|
||||
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT7, 2); /* USC MF */
|
||||
if (primary_cca->dup_rts_flag == 1)
|
||||
primary_cca->dup_rts_flag = 0;
|
||||
} else {
|
||||
primary_cca->intf_type = 2;
|
||||
if (primary_cca->dup_rts_flag == 0)
|
||||
primary_cca->dup_rts_flag = 1;
|
||||
}
|
||||
|
||||
} else { /* interferecne disappear */
|
||||
primary_cca->dup_rts_flag = 0;
|
||||
primary_cca->intf_flag = 0;
|
||||
primary_cca->intf_type = 0;
|
||||
}
|
||||
} else if (sec_ch_offset == 2) { /* secondary channel is above the primary channel */
|
||||
if ((false_alm_cnt->cnt_ofdm_cca > 500) && (false_alm_cnt->cnt_bw_usc > false_alm_cnt->cnt_bw_lsc + 500)) {
|
||||
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1) {
|
||||
primary_cca->intf_type = 1;
|
||||
primary_cca->pri_cca_flag = 1;
|
||||
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT7, 1); /* LSC MF */
|
||||
if (primary_cca->dup_rts_flag == 1)
|
||||
primary_cca->dup_rts_flag = 0;
|
||||
} else {
|
||||
primary_cca->intf_type = 2;
|
||||
if (primary_cca->dup_rts_flag == 0)
|
||||
primary_cca->dup_rts_flag = 1;
|
||||
}
|
||||
|
||||
} else { /* interferecne disappear */
|
||||
primary_cca->dup_rts_flag = 0;
|
||||
primary_cca->intf_flag = 0;
|
||||
primary_cca->intf_type = 0;
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
primary_cca->monitor_flag = 0;
|
||||
}
|
||||
|
||||
/* 1 Dynamic Primary CCA Main Function */
|
||||
if (primary_cca->monitor_flag == 0) {
|
||||
if (is_40mhz) { /* if RFBW==40M mode which require to process primary cca */
|
||||
/* 2 STA is NOT Connected */
|
||||
if (!is_connected) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("STA NOT Connected!!!!\n"));
|
||||
|
||||
if (primary_cca->pri_cca_flag == 1) { /* reset primary cca when STA is disconnected */
|
||||
primary_cca->pri_cca_flag = 0;
|
||||
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT(7), 0);
|
||||
}
|
||||
if (primary_cca->dup_rts_flag == 1) /* reset Duplicate RTS when STA is disconnected */
|
||||
primary_cca->dup_rts_flag = 0;
|
||||
|
||||
if (sec_ch_offset == 1) { /* secondary channel is below the primary channel */
|
||||
if ((false_alm_cnt->cnt_ofdm_cca > 800) && (false_alm_cnt->cnt_bw_lsc * 5 > false_alm_cnt->cnt_bw_usc * 9)) {
|
||||
primary_cca->intf_flag = 1; /* secondary channel interference is detected!!! */
|
||||
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
|
||||
primary_cca->intf_type = 1; /* interference is shift */
|
||||
else
|
||||
primary_cca->intf_type = 2; /* interference is in-band */
|
||||
} else {
|
||||
primary_cca->intf_flag = 0;
|
||||
primary_cca->intf_type = 0;
|
||||
}
|
||||
} else if (sec_ch_offset == 2) { /* secondary channel is above the primary channel */
|
||||
if ((false_alm_cnt->cnt_ofdm_cca > 800) && (false_alm_cnt->cnt_bw_usc * 5 > false_alm_cnt->cnt_bw_lsc * 9)) {
|
||||
primary_cca->intf_flag = 1; /* secondary channel interference is detected!!! */
|
||||
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
|
||||
primary_cca->intf_type = 1; /* interference is shift */
|
||||
else
|
||||
primary_cca->intf_type = 2; /* interference is in-band */
|
||||
} else {
|
||||
primary_cca->intf_flag = 0;
|
||||
primary_cca->intf_type = 0;
|
||||
}
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("primary_cca=%d\n", primary_cca->pri_cca_flag));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Intf_Type=%d\n", primary_cca->intf_type));
|
||||
}
|
||||
/* 2 STA is Connected */
|
||||
else {
|
||||
if (client_40mhz == 0) /* 3 */ { /* client BW = 20MHz */
|
||||
if (primary_cca->pri_cca_flag == 0) {
|
||||
primary_cca->pri_cca_flag = 1;
|
||||
if (sec_ch_offset == 1)
|
||||
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT(7), 2);
|
||||
else if (sec_ch_offset == 2)
|
||||
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT(7), 1);
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("STA Connected 20M!!! primary_cca=%d\n", primary_cca->pri_cca_flag));
|
||||
} else /* 3 */ { /* client BW = 40MHz */
|
||||
if (primary_cca->intf_flag == 1) { /* interference is detected!! */
|
||||
if (primary_cca->intf_type == 1) {
|
||||
if (primary_cca->pri_cca_flag != 1) {
|
||||
primary_cca->pri_cca_flag = 1;
|
||||
if (sec_ch_offset == 1)
|
||||
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT(7), 2);
|
||||
else if (sec_ch_offset == 2)
|
||||
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT(7), 1);
|
||||
}
|
||||
} else if (primary_cca->intf_type == 2) {
|
||||
if (primary_cca->dup_rts_flag != 1)
|
||||
primary_cca->dup_rts_flag = 1;
|
||||
}
|
||||
} else { /* if intf_flag==0 */
|
||||
if ((cur_tx_ok_cnt + cur_rx_ok_cnt) < 10000) { /* idle mode or TP traffic is very low */
|
||||
if (sec_ch_offset == 1) {
|
||||
if ((false_alm_cnt->cnt_ofdm_cca > 800) && (false_alm_cnt->cnt_bw_lsc * 5 > false_alm_cnt->cnt_bw_usc * 9)) {
|
||||
primary_cca->intf_flag = 1;
|
||||
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
|
||||
primary_cca->intf_type = 1; /* interference is shift */
|
||||
else
|
||||
primary_cca->intf_type = 2; /* interference is in-band */
|
||||
}
|
||||
} else if (sec_ch_offset == 2) {
|
||||
if ((false_alm_cnt->cnt_ofdm_cca > 800) && (false_alm_cnt->cnt_bw_usc * 5 > false_alm_cnt->cnt_bw_lsc * 9)) {
|
||||
primary_cca->intf_flag = 1;
|
||||
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
|
||||
primary_cca->intf_type = 1; /* interference is shift */
|
||||
else
|
||||
primary_cca->intf_type = 2; /* interference is in-band */
|
||||
}
|
||||
|
||||
}
|
||||
} else { /* TP Traffic is High */
|
||||
if (sec_ch_offset == 1) {
|
||||
if (false_alm_cnt->cnt_bw_lsc > (false_alm_cnt->cnt_bw_usc + 500)) {
|
||||
if (delay == 0) { /* add delay to avoid interference occurring abruptly, jump one time */
|
||||
primary_cca->intf_flag = 1;
|
||||
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
|
||||
primary_cca->intf_type = 1; /* interference is shift */
|
||||
else
|
||||
primary_cca->intf_type = 2; /* interference is in-band */
|
||||
delay = 1;
|
||||
} else
|
||||
delay = 0;
|
||||
}
|
||||
} else if (sec_ch_offset == 2) {
|
||||
if (false_alm_cnt->cnt_bw_usc > (false_alm_cnt->cnt_bw_lsc + 500)) {
|
||||
if (delay == 0) { /* add delay to avoid interference occurring abruptly */
|
||||
primary_cca->intf_flag = 1;
|
||||
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
|
||||
primary_cca->intf_type = 1; /* interference is shift */
|
||||
else
|
||||
primary_cca->intf_type = 2; /* interference is in-band */
|
||||
delay = 1;
|
||||
} else
|
||||
delay = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Primary CCA=%d\n", primary_cca->pri_cca_flag));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Duplicate RTS=%d\n", primary_cca->dup_rts_flag));
|
||||
}
|
||||
|
||||
} /* end of connected */
|
||||
}
|
||||
}
|
||||
/* 1 Dynamic Primary CCA Monitor counter */
|
||||
if ((primary_cca->pri_cca_flag == 1) || (primary_cca->dup_rts_flag == 1)) {
|
||||
if (client_40mhz == 0) { /* client=20M no need to monitor primary cca flag */
|
||||
client_40mhz_pre = client_40mhz;
|
||||
return;
|
||||
}
|
||||
counter++;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("counter=%d\n", counter));
|
||||
if ((counter == 30) || ((client_40mhz - client_40mhz_pre) == 1)) { /* Every 60 sec to monitor one time */
|
||||
primary_cca->monitor_flag = 1; /* monitor flag is triggered!!!!! */
|
||||
if (primary_cca->pri_cca_flag == 1) {
|
||||
primary_cca->pri_cca_flag = 0;
|
||||
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT(7), 0);
|
||||
}
|
||||
counter = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
client_40mhz_pre = client_40mhz;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* #if (RTL8188E_SUPPORT == 1) */
|
||||
78
hal/phydm/rtl8188e/phydm_rtl8188e.h
Normal file
78
hal/phydm/rtl8188e/phydm_rtl8188e.h
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __ODM_RTL8188E_H__
|
||||
#define __ODM_RTL8188E_H__
|
||||
|
||||
#if (RTL8188E_SUPPORT == 1)
|
||||
|
||||
|
||||
|
||||
#define MAIN_ANT_CG_TRX 1
|
||||
#define AUX_ANT_CG_TRX 0
|
||||
#define MAIN_ANT_CGCS_RX 0
|
||||
#define AUX_ANT_CGCS_RX 1
|
||||
|
||||
void
|
||||
odm_dig_lower_bound_88e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
|
||||
#define sw_ant_div_reset_before_link odm_sw_ant_div_reset_before_link
|
||||
|
||||
void odm_sw_ant_div_reset_before_link(struct PHY_DM_STRUCT *p_dm_odm);
|
||||
|
||||
void
|
||||
odm_set_tx_ant_by_tx_info_88e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 *p_desc,
|
||||
u8 mac_id
|
||||
);
|
||||
#else/* (DM_ODM_SUPPORT_TYPE == ODM_AP) */
|
||||
void
|
||||
odm_set_tx_ant_by_tx_info_88e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
#endif
|
||||
|
||||
void
|
||||
odm_primary_cca_init(
|
||||
struct PHY_DM_STRUCT *p_dm_odm);
|
||||
|
||||
bool
|
||||
odm_dynamic_primary_cca_dup_rts(
|
||||
struct PHY_DM_STRUCT *p_dm_odm);
|
||||
|
||||
void
|
||||
odm_dynamic_primary_cca(
|
||||
struct PHY_DM_STRUCT *p_dm_odm);
|
||||
|
||||
#else /* (RTL8188E_SUPPORT == 0)*/
|
||||
|
||||
#define odm_primary_cca_init(_pdm_odm)
|
||||
#define odm_dynamic_primary_cca(_pdm_odm)
|
||||
|
||||
#endif /* RTL8188E_SUPPORT */
|
||||
|
||||
#endif
|
||||
10
hal/phydm/rtl8188e/version_rtl8188e.h
Normal file
10
hal/phydm/rtl8188e/version_rtl8188e.h
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/*RTL8188E PHY Parameters*/
|
||||
/*
|
||||
[Caution]
|
||||
Since 01/Aug/2015, the commit rules will be simplified.
|
||||
You do not need to fill up the version.h anymore,
|
||||
only the maintenance supervisor fills it before formal release.
|
||||
*/
|
||||
#define RELEASE_DATE_8188E 20160517
|
||||
#define COMMIT_BY_8188E "RF_Eason"
|
||||
#define RELEASE_VERSION_8188E 70
|
||||
538
hal/phydm/txbf/halcomtxbf.c
Normal file
538
hal/phydm/txbf/halcomtxbf.c
Normal file
|
|
@ -0,0 +1,538 @@
|
|||
/* ************************************************************
|
||||
* Description:
|
||||
*
|
||||
* This file is for TXBF mechanism
|
||||
*
|
||||
* ************************************************************ */
|
||||
#include "mp_precomp.h"
|
||||
#include "../phydm_precomp.h"
|
||||
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
/*Beamforming halcomtxbf API create by YuChen 2015/05*/
|
||||
|
||||
void
|
||||
hal_com_txbf_beamform_init(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
bool is_iqgen_setting_ok = false;
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8814A) {
|
||||
is_iqgen_setting_ok = phydm_beamforming_set_iqgen_8814A(p_dm_odm);
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] is_iqgen_setting_ok = %d\n", __func__, is_iqgen_setting_ok));
|
||||
}
|
||||
}
|
||||
|
||||
/*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/
|
||||
void
|
||||
hal_com_txbf_config_gtab(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8822B)
|
||||
hal_txbf_8822b_config_gtab(p_dm_odm);
|
||||
}
|
||||
|
||||
void
|
||||
phydm_beamform_set_sounding_enter(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_enter_work_item)) == false)
|
||||
odm_schedule_work_item(&(p_txbf_info->txbf_enter_work_item));
|
||||
#else
|
||||
hal_com_txbf_enter_work_item_callback(p_dm_odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
phydm_beamform_set_sounding_leave(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_leave_work_item)) == false)
|
||||
odm_schedule_work_item(&(p_txbf_info->txbf_leave_work_item));
|
||||
#else
|
||||
hal_com_txbf_leave_work_item_callback(p_dm_odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
phydm_beamform_set_sounding_rate(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_rate_work_item)) == false)
|
||||
odm_schedule_work_item(&(p_txbf_info->txbf_rate_work_item));
|
||||
#else
|
||||
hal_com_txbf_rate_work_item_callback(p_dm_odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
phydm_beamform_set_sounding_status(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_status_work_item)) == false)
|
||||
odm_schedule_work_item(&(p_txbf_info->txbf_status_work_item));
|
||||
#else
|
||||
hal_com_txbf_status_work_item_callback(p_dm_odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
phydm_beamform_set_sounding_fw_ndpa(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
if (*p_dm_odm->p_is_fw_dw_rsvd_page_in_progress)
|
||||
odm_set_timer(p_dm_odm, &(p_txbf_info->txbf_fw_ndpa_timer), 5);
|
||||
else
|
||||
odm_schedule_work_item(&(p_txbf_info->txbf_fw_ndpa_work_item));
|
||||
#else
|
||||
hal_com_txbf_fw_ndpa_work_item_callback(p_dm_odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
phydm_beamform_set_sounding_clk(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_clk_work_item)) == false)
|
||||
odm_schedule_work_item(&(p_txbf_info->txbf_clk_work_item));
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
struct _ADAPTER *padapter = p_dm_odm->adapter;
|
||||
|
||||
rtw_run_in_thread_cmd(padapter, hal_com_txbf_clk_work_item_callback, padapter);
|
||||
#else
|
||||
hal_com_txbf_clk_work_item_callback(p_dm_odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
phydm_beamform_set_reset_tx_path(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_reset_tx_path_work_item)) == false)
|
||||
odm_schedule_work_item(&(p_txbf_info->txbf_reset_tx_path_work_item));
|
||||
#else
|
||||
hal_com_txbf_reset_tx_path_work_item_callback(p_dm_odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
phydm_beamform_set_get_tx_rate(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_get_tx_rate_work_item)) == false)
|
||||
odm_schedule_work_item(&(p_txbf_info->txbf_get_tx_rate_work_item));
|
||||
#else
|
||||
hal_com_txbf_get_tx_rate_work_item_callback(p_dm_odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
hal_com_txbf_enter_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#else
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#endif
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
u8 idx = p_txbf_info->txbf_idx;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))
|
||||
hal_txbf_jaguar_enter(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8192E)
|
||||
hal_txbf_8192e_enter(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
hal_txbf_8814a_enter(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8822B)
|
||||
hal_txbf_8822b_enter(p_dm_odm, idx);
|
||||
}
|
||||
|
||||
void
|
||||
hal_com_txbf_leave_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#else
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#endif
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
u8 idx = p_txbf_info->txbf_idx;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))
|
||||
hal_txbf_jaguar_leave(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8192E)
|
||||
hal_txbf_8192e_leave(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
hal_txbf_8814a_leave(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8822B)
|
||||
hal_txbf_8822b_leave(p_dm_odm, idx);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
hal_com_txbf_fw_ndpa_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#else
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#endif
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
u8 idx = p_txbf_info->ndpa_idx;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))
|
||||
hal_txbf_jaguar_fw_txbf(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8192E)
|
||||
hal_txbf_8192e_fw_tx_bf(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
hal_txbf_8814a_fw_txbf(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8822B)
|
||||
hal_txbf_8822b_fw_txbf(p_dm_odm, idx);
|
||||
}
|
||||
|
||||
void
|
||||
hal_com_txbf_clk_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#else
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#endif
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8812)
|
||||
hal_txbf_jaguar_clk_8812a(p_dm_odm);
|
||||
}
|
||||
|
||||
|
||||
|
||||
void
|
||||
hal_com_txbf_rate_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#else
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#endif
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
u8 BW = p_txbf_info->BW;
|
||||
u8 rate = p_txbf_info->rate;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8812)
|
||||
hal_txbf_8812a_set_ndpa_rate(p_dm_odm, BW, rate);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8192E)
|
||||
hal_txbf_8192e_set_ndpa_rate(p_dm_odm, BW, rate);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
hal_txbf_8814a_set_ndpa_rate(p_dm_odm, BW, rate);
|
||||
|
||||
}
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void
|
||||
hal_com_txbf_fw_ndpa_timer_callback(
|
||||
struct timer_list *p_timer
|
||||
)
|
||||
{
|
||||
|
||||
struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->Adapter;
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (*p_dm_odm->p_is_fw_dw_rsvd_page_in_progress)
|
||||
odm_set_timer(p_dm_odm, &(p_txbf_info->txbf_fw_ndpa_timer), 5);
|
||||
else
|
||||
odm_schedule_work_item(&(p_txbf_info->txbf_fw_ndpa_work_item));
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
void
|
||||
hal_com_txbf_status_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#else
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#endif
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
u8 idx = p_txbf_info->txbf_idx;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))
|
||||
hal_txbf_jaguar_status(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8192E)
|
||||
hal_txbf_8192e_status(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
hal_txbf_8814a_status(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8822B)
|
||||
hal_txbf_8822b_status(p_dm_odm, idx);
|
||||
}
|
||||
|
||||
void
|
||||
hal_com_txbf_reset_tx_path_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#else
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#endif
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
u8 idx = p_txbf_info->txbf_idx;
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
hal_txbf_8814a_reset_tx_path(p_dm_odm, idx);
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
hal_com_txbf_get_tx_rate_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#else
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#endif
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
hal_txbf_8814a_get_tx_rate(p_dm_odm);
|
||||
}
|
||||
|
||||
|
||||
bool
|
||||
hal_com_txbf_set(
|
||||
void *p_dm_void,
|
||||
u8 set_type,
|
||||
void *p_in_buf
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u8 *p_u1_tmp = (u8 *)p_in_buf;
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] set_type = 0x%X\n", __func__, set_type));
|
||||
|
||||
switch (set_type) {
|
||||
case TXBF_SET_SOUNDING_ENTER:
|
||||
p_txbf_info->txbf_idx = *p_u1_tmp;
|
||||
phydm_beamform_set_sounding_enter(p_dm_odm);
|
||||
break;
|
||||
|
||||
case TXBF_SET_SOUNDING_LEAVE:
|
||||
p_txbf_info->txbf_idx = *p_u1_tmp;
|
||||
phydm_beamform_set_sounding_leave(p_dm_odm);
|
||||
break;
|
||||
|
||||
case TXBF_SET_SOUNDING_RATE:
|
||||
p_txbf_info->BW = p_u1_tmp[0];
|
||||
p_txbf_info->rate = p_u1_tmp[1];
|
||||
phydm_beamform_set_sounding_rate(p_dm_odm);
|
||||
break;
|
||||
|
||||
case TXBF_SET_SOUNDING_STATUS:
|
||||
p_txbf_info->txbf_idx = *p_u1_tmp;
|
||||
phydm_beamform_set_sounding_status(p_dm_odm);
|
||||
break;
|
||||
|
||||
case TXBF_SET_SOUNDING_FW_NDPA:
|
||||
p_txbf_info->ndpa_idx = *p_u1_tmp;
|
||||
phydm_beamform_set_sounding_fw_ndpa(p_dm_odm);
|
||||
break;
|
||||
|
||||
case TXBF_SET_SOUNDING_CLK:
|
||||
phydm_beamform_set_sounding_clk(p_dm_odm);
|
||||
break;
|
||||
|
||||
case TXBF_SET_TX_PATH_RESET:
|
||||
p_txbf_info->txbf_idx = *p_u1_tmp;
|
||||
phydm_beamform_set_reset_tx_path(p_dm_odm);
|
||||
break;
|
||||
|
||||
case TXBF_SET_GET_TX_RATE:
|
||||
phydm_beamform_set_get_tx_rate(p_dm_odm);
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
bool
|
||||
hal_com_txbf_get(
|
||||
struct _ADAPTER *adapter,
|
||||
u8 get_type,
|
||||
void *p_out_buf
|
||||
)
|
||||
{
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
bool *p_boolean = (bool *)p_out_buf;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (get_type == TXBF_GET_EXPLICIT_BEAMFORMEE) {
|
||||
if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(adapter))
|
||||
*p_boolean = false;
|
||||
else if (/*IS_HARDWARE_TYPE_8822B(adapter) ||*/
|
||||
IS_HARDWARE_TYPE_8821B(adapter) ||
|
||||
IS_HARDWARE_TYPE_8192E(adapter) ||
|
||||
IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
|
||||
*p_boolean = true;
|
||||
else
|
||||
*p_boolean = false;
|
||||
} else if (get_type == TXBF_GET_EXPLICIT_BEAMFORMER) {
|
||||
if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(adapter))
|
||||
*p_boolean = false;
|
||||
else if (/*IS_HARDWARE_TYPE_8822B(adapter) ||*/
|
||||
IS_HARDWARE_TYPE_8821B(adapter) ||
|
||||
IS_HARDWARE_TYPE_8192E(adapter) ||
|
||||
IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) {
|
||||
if (p_hal_data->RF_Type == RF_2T2R || p_hal_data->RF_Type == RF_3T3R)
|
||||
*p_boolean = true;
|
||||
else
|
||||
*p_boolean = false;
|
||||
} else
|
||||
*p_boolean = false;
|
||||
} else if (get_type == TXBF_GET_MU_MIMO_STA) {
|
||||
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1))
|
||||
if (IS_HARDWARE_TYPE_8822B(adapter) || IS_HARDWARE_TYPE_8821C(adapter))
|
||||
*p_boolean = true;
|
||||
else
|
||||
#endif
|
||||
*p_boolean = false;
|
||||
|
||||
|
||||
} else if (get_type == TXBF_GET_MU_MIMO_AP) {
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
if (IS_HARDWARE_TYPE_8822B(adapter))
|
||||
*p_boolean = true;
|
||||
else
|
||||
#endif
|
||||
*p_boolean = false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
179
hal/phydm/txbf/halcomtxbf.h
Normal file
179
hal/phydm/txbf/halcomtxbf.h
Normal file
|
|
@ -0,0 +1,179 @@
|
|||
#ifndef __HAL_COM_TXBF_H__
|
||||
#define __HAL_COM_TXBF_H__
|
||||
|
||||
/*
|
||||
typedef bool
|
||||
(*TXBF_GET)(
|
||||
void* p_adapter,
|
||||
u8 get_type,
|
||||
void* p_out_buf
|
||||
);
|
||||
|
||||
typedef bool
|
||||
(*TXBF_SET)(
|
||||
void* p_adapter,
|
||||
u8 set_type,
|
||||
void* p_in_buf
|
||||
);
|
||||
*/
|
||||
|
||||
enum txbf_set_type {
|
||||
TXBF_SET_SOUNDING_ENTER,
|
||||
TXBF_SET_SOUNDING_LEAVE,
|
||||
TXBF_SET_SOUNDING_RATE,
|
||||
TXBF_SET_SOUNDING_STATUS,
|
||||
TXBF_SET_SOUNDING_FW_NDPA,
|
||||
TXBF_SET_SOUNDING_CLK,
|
||||
TXBF_SET_TX_PATH_RESET,
|
||||
TXBF_SET_GET_TX_RATE
|
||||
};
|
||||
|
||||
|
||||
enum txbf_get_type {
|
||||
TXBF_GET_EXPLICIT_BEAMFORMEE,
|
||||
TXBF_GET_EXPLICIT_BEAMFORMER,
|
||||
TXBF_GET_MU_MIMO_STA,
|
||||
TXBF_GET_MU_MIMO_AP
|
||||
};
|
||||
|
||||
|
||||
|
||||
/* 2 HAL TXBF related */
|
||||
struct _HAL_TXBF_INFO {
|
||||
u8 txbf_idx;
|
||||
u8 ndpa_idx;
|
||||
u8 BW;
|
||||
u8 rate;
|
||||
|
||||
struct timer_list txbf_fw_ndpa_timer;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
RT_WORK_ITEM txbf_enter_work_item;
|
||||
RT_WORK_ITEM txbf_leave_work_item;
|
||||
RT_WORK_ITEM txbf_fw_ndpa_work_item;
|
||||
RT_WORK_ITEM txbf_clk_work_item;
|
||||
RT_WORK_ITEM txbf_status_work_item;
|
||||
RT_WORK_ITEM txbf_rate_work_item;
|
||||
RT_WORK_ITEM txbf_reset_tx_path_work_item;
|
||||
RT_WORK_ITEM txbf_get_tx_rate_work_item;
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
|
||||
void
|
||||
hal_com_txbf_beamform_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
hal_com_txbf_config_gtab(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
hal_com_txbf_enter_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
);
|
||||
|
||||
void
|
||||
hal_com_txbf_leave_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
);
|
||||
|
||||
void
|
||||
hal_com_txbf_fw_ndpa_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
);
|
||||
|
||||
void
|
||||
hal_com_txbf_clk_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
);
|
||||
|
||||
void
|
||||
hal_com_txbf_reset_tx_path_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
);
|
||||
|
||||
void
|
||||
hal_com_txbf_get_tx_rate_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
);
|
||||
|
||||
void
|
||||
hal_com_txbf_rate_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
);
|
||||
|
||||
void
|
||||
hal_com_txbf_fw_ndpa_timer_callback(
|
||||
struct timer_list *p_timer
|
||||
);
|
||||
|
||||
void
|
||||
hal_com_txbf_status_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
);
|
||||
|
||||
bool
|
||||
hal_com_txbf_set(
|
||||
void *p_dm_void,
|
||||
u8 set_type,
|
||||
void *p_in_buf
|
||||
);
|
||||
|
||||
bool
|
||||
hal_com_txbf_get(
|
||||
struct _ADAPTER *adapter,
|
||||
u8 get_type,
|
||||
void *p_out_buf
|
||||
);
|
||||
|
||||
#else
|
||||
#define hal_com_txbf_beamform_init(p_dm_void) NULL
|
||||
#define hal_com_txbf_config_gtab(p_dm_void) NULL
|
||||
#define hal_com_txbf_enter_work_item_callback(_adapter) NULL
|
||||
#define hal_com_txbf_leave_work_item_callback(_adapter) NULL
|
||||
#define hal_com_txbf_fw_ndpa_work_item_callback(_adapter) NULL
|
||||
#define hal_com_txbf_clk_work_item_callback(_adapter) NULL
|
||||
#define hal_com_txbf_rate_work_item_callback(_adapter) NULL
|
||||
#define hal_com_txbf_fw_ndpa_timer_callback(_adapter) NULL
|
||||
#define hal_com_txbf_status_work_item_callback(_adapter) NULL
|
||||
#define hal_com_txbf_get(_adapter, _get_type, _pout_buf)
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* #ifndef __HAL_COM_TXBF_H__ */
|
||||
391
hal/phydm/txbf/haltxbf8192e.c
Normal file
391
hal/phydm/txbf/haltxbf8192e.c
Normal file
|
|
@ -0,0 +1,391 @@
|
|||
/* ************************************************************
|
||||
* Description:
|
||||
*
|
||||
* This file is for 8192E TXBF mechanism
|
||||
*
|
||||
* ************************************************************ */
|
||||
#include "mp_precomp.h"
|
||||
#include "../phydm_precomp.h"
|
||||
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
#if (RTL8192E_SUPPORT == 1)
|
||||
|
||||
void
|
||||
hal_txbf_8192e_set_ndpa_rate(
|
||||
void *p_dm_void,
|
||||
u8 BW,
|
||||
u8 rate
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
|
||||
odm_write_1byte(p_dm_odm, REG_NDPA_OPT_CTRL_8192E, (rate << 2 | BW));
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
hal_txbf_8192e_rf_mode(
|
||||
void *p_dm_void,
|
||||
struct _RT_BEAMFORMING_INFO *p_beam_info
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
bool is_self_beamformer = false;
|
||||
bool is_self_beamformee = false;
|
||||
enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (p_dm_odm->rf_type == ODM_1T1R)
|
||||
return;
|
||||
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/
|
||||
|
||||
if (p_beam_info->beamformee_su_cnt > 0) {
|
||||
/*Path_A*/
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*Select RX mode 0x30=0x18000*/
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f); /*Set Table data*/
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/
|
||||
/*Path_B*/
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*Select RX mode*/
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f); /*Set Table data*/
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/
|
||||
} else {
|
||||
/*Path_A*/
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*Select RX mode*/
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f); /*Set Table data*/
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/
|
||||
/*Path_B*/
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*Select RX mode*/
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f); /*Set Table data*/
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/
|
||||
}
|
||||
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
|
||||
|
||||
if (p_beam_info->beamformee_su_cnt > 0) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x83321333);
|
||||
odm_set_bb_reg(p_dm_odm, 0xa04, MASKBYTE3, 0xc1);
|
||||
} else
|
||||
odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x81121313);
|
||||
}
|
||||
|
||||
|
||||
|
||||
void
|
||||
hal_txbf_8192e_fw_txbf_cmd(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u8 idx, period0 = 0, period1 = 0;
|
||||
u8 PageNum0 = 0xFF, PageNum1 = 0xFF;
|
||||
u8 u1_tx_bf_parm[3] = {0};
|
||||
struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info;
|
||||
|
||||
for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
|
||||
if (p_beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
|
||||
if (idx == 0) {
|
||||
if (p_beam_info->beamformee_entry[idx].is_sound)
|
||||
PageNum0 = 0xFE;
|
||||
else
|
||||
PageNum0 = 0xFF; /* stop sounding */
|
||||
period0 = (u8)(p_beam_info->beamformee_entry[idx].sound_period);
|
||||
} else if (idx == 1) {
|
||||
if (p_beam_info->beamformee_entry[idx].is_sound)
|
||||
PageNum1 = 0xFE;
|
||||
else
|
||||
PageNum1 = 0xFF; /* stop sounding */
|
||||
period1 = (u8)(p_beam_info->beamformee_entry[idx].sound_period);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
u1_tx_bf_parm[0] = PageNum0;
|
||||
u1_tx_bf_parm[1] = PageNum1;
|
||||
u1_tx_bf_parm[2] = (period1 << 4) | period0;
|
||||
odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD,
|
||||
("[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n", __func__, PageNum0, period0, PageNum1, period1));
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
hal_txbf_8192e_download_ndpa(
|
||||
void *p_dm_void,
|
||||
u8 idx
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u8 u1b_tmp = 0, tmp_reg422 = 0, head_page;
|
||||
u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
|
||||
bool is_send_beacon = false;
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812;
|
||||
/*default reseved 1 page for the IC type which is undefined.*/
|
||||
struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info;
|
||||
struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
*p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = true;
|
||||
#endif
|
||||
if (idx == 0)
|
||||
head_page = 0xFE;
|
||||
else
|
||||
head_page = 0xFE;
|
||||
|
||||
phydm_get_hal_def_var_handler_interface(p_dm_odm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy);
|
||||
|
||||
/*Set REG_CR bit 8. DMA beacon by SW.*/
|
||||
u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8192E+1);
|
||||
odm_write_1byte(p_dm_odm, REG_CR_8192E+1, (u1b_tmp | BIT(0)));
|
||||
|
||||
/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
|
||||
tmp_reg422 = odm_read_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8192E+2);
|
||||
odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8192E+2, tmp_reg422 & (~BIT(6)));
|
||||
|
||||
if (tmp_reg422 & BIT(6)) {
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s There is an adapter is sending beacon.\n", __func__));
|
||||
is_send_beacon = true;
|
||||
}
|
||||
|
||||
/*TDECTRL[15:8] 0x209[7:0] = 0xFE/0xFD NDPA Head for TXDMA*/
|
||||
odm_write_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+1, head_page);
|
||||
|
||||
do {
|
||||
/*Clear beacon valid check bit.*/
|
||||
bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+2);
|
||||
odm_write_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+2, (bcn_valid_reg | BIT(0)));
|
||||
|
||||
/* download NDPA rsvd page. */
|
||||
beamforming_send_ht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
|
||||
|
||||
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
|
||||
u1b_tmp = odm_read_1byte(p_dm_odm, REG_MGQ_TXBD_NUM_8192E+3);
|
||||
count = 0;
|
||||
while ((count < 20) && (u1b_tmp & BIT(4))) {
|
||||
count++;
|
||||
ODM_delay_us(10);
|
||||
u1b_tmp = odm_read_1byte(p_dm_odm, REG_MGQ_TXBD_NUM_8192E+3);
|
||||
}
|
||||
odm_write_1byte(p_dm_odm, REG_MGQ_TXBD_NUM_8192E+3, u1b_tmp | BIT(4));
|
||||
#endif
|
||||
|
||||
/*check rsvd page download OK.*/
|
||||
bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+2);
|
||||
count = 0;
|
||||
while (!(bcn_valid_reg & BIT(0)) && count < 20) {
|
||||
count++;
|
||||
ODM_delay_us(10);
|
||||
bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+2);
|
||||
}
|
||||
dl_bcn_count++;
|
||||
} while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5);
|
||||
|
||||
if (!(bcn_valid_reg & BIT(0)))
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s Download RSVD page failed!\n", __func__));
|
||||
|
||||
/*TDECTRL[15:8] 0x209[7:0] = 0xF9 Beacon Head for TXDMA*/
|
||||
odm_write_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+1, tx_page_bndy);
|
||||
|
||||
/*To make sure that if there exists an adapter which would like to send beacon.*/
|
||||
/*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
|
||||
/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/
|
||||
/*the beacon cannot be sent by HW.*/
|
||||
/*2010.06.23. Added by tynli.*/
|
||||
if (is_send_beacon)
|
||||
odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8192E+2, tmp_reg422);
|
||||
|
||||
/*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
|
||||
/*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
|
||||
u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8192E+1);
|
||||
odm_write_1byte(p_dm_odm, REG_CR_8192E+1, (u1b_tmp & (~BIT(0))));
|
||||
|
||||
p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
*p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = false;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
hal_txbf_8192e_enter(
|
||||
void *p_dm_void,
|
||||
u8 bfer_bfee_idx
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u8 i = 0;
|
||||
u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
|
||||
u8 bfee_idx = (bfer_bfee_idx & 0xF);
|
||||
u32 csi_param;
|
||||
struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info;
|
||||
struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
|
||||
struct _RT_BEAMFORMER_ENTRY beamformer_entry;
|
||||
u16 sta_id = 0;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
hal_txbf_8192e_rf_mode(p_dm_odm, p_beamforming_info);
|
||||
|
||||
if (p_dm_odm->rf_type == ODM_2T2R)
|
||||
odm_write_4byte(p_dm_odm, 0xd80, 0x00000000); /*nc =2*/
|
||||
|
||||
if ((p_beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) {
|
||||
beamformer_entry = p_beamforming_info->beamformer_entry[bfer_idx];
|
||||
|
||||
/*Sounding protocol control*/
|
||||
odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8192E, 0xCB);
|
||||
|
||||
/*MAC address/Partial AID of Beamformer*/
|
||||
if (bfer_idx == 0) {
|
||||
for (i = 0; i < 6 ; i++)
|
||||
odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER0_INFO_8192E+i), beamformer_entry.mac_addr[i]);
|
||||
} else {
|
||||
for (i = 0; i < 6 ; i++)
|
||||
odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER1_INFO_8192E+i), beamformer_entry.mac_addr[i]);
|
||||
}
|
||||
|
||||
/*CSI report parameters of Beamformer Default use nc = 2*/
|
||||
csi_param = 0x03090309;
|
||||
|
||||
odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8192E, csi_param);
|
||||
odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW40_8192E, csi_param);
|
||||
odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW80_8192E, csi_param);
|
||||
|
||||
/*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/
|
||||
odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8192E+3, 0x50);
|
||||
|
||||
}
|
||||
|
||||
if ((p_beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) {
|
||||
beamformee_entry = p_beamforming_info->beamformee_entry[bfee_idx];
|
||||
|
||||
if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss))
|
||||
sta_id = beamformee_entry.mac_id;
|
||||
else
|
||||
sta_id = beamformee_entry.p_aid;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s], sta_id=0x%X\n", __func__, sta_id));
|
||||
|
||||
/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
|
||||
if (bfee_idx == 0) {
|
||||
odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8192E, sta_id);
|
||||
odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8192E+3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8192E+3) | BIT(4) | BIT(6) | BIT(7));
|
||||
} else
|
||||
odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8192E+2, sta_id | BIT(12) | BIT(14) | BIT(15));
|
||||
|
||||
/*CSI report parameters of Beamformee*/
|
||||
if (bfee_idx == 0) {
|
||||
/*Get BIT24 & BIT25*/
|
||||
u8 tmp = odm_read_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3) & 0x3;
|
||||
|
||||
odm_write_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3, tmp | 0x60);
|
||||
odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E, sta_id | BIT(9));
|
||||
} else {
|
||||
/*Set BIT25*/
|
||||
odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, sta_id | 0xE200);
|
||||
}
|
||||
phydm_beamforming_notify(p_dm_odm);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
hal_txbf_8192e_leave(
|
||||
void *p_dm_void,
|
||||
u8 idx
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info;
|
||||
|
||||
hal_txbf_8192e_rf_mode(p_dm_odm, p_beam_info);
|
||||
|
||||
/* Clear P_AID of Beamformee
|
||||
* Clear MAC addresss of Beamformer
|
||||
* Clear Associated Bfmee Sel
|
||||
*/
|
||||
if (p_beam_info->beamform_cap == BEAMFORMING_CAP_NONE)
|
||||
odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8192E, 0xC8);
|
||||
|
||||
if (idx == 0) {
|
||||
odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8192E, 0);
|
||||
odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0);
|
||||
odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8192E+4, 0);
|
||||
odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0);
|
||||
} else {
|
||||
odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8192E+2, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8192E+2) & 0xF000);
|
||||
odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0);
|
||||
odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8192E+4, 0);
|
||||
odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, odm_read_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2) & 0x60);
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx %d\n", __func__, idx));
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
hal_txbf_8192e_status(
|
||||
void *p_dm_void,
|
||||
u8 idx
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u16 beam_ctrl_val;
|
||||
u32 beam_ctrl_reg;
|
||||
struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info;
|
||||
struct _RT_BEAMFORMEE_ENTRY beamform_entry = p_beam_info->beamformee_entry[idx];
|
||||
|
||||
if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss))
|
||||
beam_ctrl_val = beamform_entry.mac_id;
|
||||
else
|
||||
beam_ctrl_val = beamform_entry.p_aid;
|
||||
|
||||
if (idx == 0)
|
||||
beam_ctrl_reg = REG_TXBF_CTRL_8192E;
|
||||
else {
|
||||
beam_ctrl_reg = REG_TXBF_CTRL_8192E+2;
|
||||
beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
|
||||
}
|
||||
|
||||
if ((beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (p_beam_info->apply_v_matrix == true)) {
|
||||
if (beamform_entry.sound_bw == CHANNEL_WIDTH_20)
|
||||
beam_ctrl_val |= BIT(9);
|
||||
else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)
|
||||
beam_ctrl_val |= BIT(10);
|
||||
} else
|
||||
beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
|
||||
|
||||
odm_write_2byte(p_dm_odm, beam_ctrl_reg, beam_ctrl_val);
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx %d beam_ctrl_reg %x beam_ctrl_val %x\n", __func__, idx, beam_ctrl_reg, beam_ctrl_val));
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
hal_txbf_8192e_fw_tx_bf(
|
||||
void *p_dm_void,
|
||||
u8 idx
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info;
|
||||
struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
|
||||
hal_txbf_8192e_download_ndpa(p_dm_odm, idx);
|
||||
|
||||
hal_txbf_8192e_fw_txbf_cmd(p_dm_odm);
|
||||
}
|
||||
|
||||
#endif /* #if (RTL8192E_SUPPORT == 1)*/
|
||||
|
||||
#endif
|
||||
60
hal/phydm/txbf/haltxbf8192e.h
Normal file
60
hal/phydm/txbf/haltxbf8192e.h
Normal file
|
|
@ -0,0 +1,60 @@
|
|||
#ifndef __HAL_TXBF_8192E_H__
|
||||
#define __HAL_TXBF_8192E_H__
|
||||
|
||||
#if (RTL8192E_SUPPORT == 1)
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
|
||||
void
|
||||
hal_txbf_8192e_set_ndpa_rate(
|
||||
void *p_dm_void,
|
||||
u8 BW,
|
||||
u8 rate
|
||||
);
|
||||
|
||||
void
|
||||
hal_txbf_8192e_enter(
|
||||
void *p_dm_void,
|
||||
u8 idx
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
hal_txbf_8192e_leave(
|
||||
void *p_dm_void,
|
||||
u8 idx
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
hal_txbf_8192e_status(
|
||||
void *p_dm_void,
|
||||
u8 idx
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
hal_txbf_8192e_fw_tx_bf(
|
||||
void *p_dm_void,
|
||||
u8 idx
|
||||
);
|
||||
#else
|
||||
|
||||
#define hal_txbf_8192e_set_ndpa_rate(p_dm_void, BW, rate)
|
||||
#define hal_txbf_8192e_enter(p_dm_void, idx)
|
||||
#define hal_txbf_8192e_leave(p_dm_void, idx)
|
||||
#define hal_txbf_8192e_status(p_dm_void, idx)
|
||||
#define hal_txbf_8192e_fw_tx_bf(p_dm_void, idx)
|
||||
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
#define hal_txbf_8192e_set_ndpa_rate(p_dm_void, BW, rate)
|
||||
#define hal_txbf_8192e_enter(p_dm_void, idx)
|
||||
#define hal_txbf_8192e_leave(p_dm_void, idx)
|
||||
#define hal_txbf_8192e_status(p_dm_void, idx)
|
||||
#define hal_txbf_8192e_fw_tx_bf(p_dm_void, idx)
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
700
hal/phydm/txbf/haltxbf8814a.c
Normal file
700
hal/phydm/txbf/haltxbf8814a.c
Normal file
|
|
@ -0,0 +1,700 @@
|
|||
/* ************************************************************
|
||||
* Description:
|
||||
*
|
||||
* This file is for 8814A TXBF mechanism
|
||||
*
|
||||
* ************************************************************ */
|
||||
|
||||
#include "mp_precomp.h"
|
||||
#include "../phydm_precomp.h"
|
||||
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
|
||||
bool
|
||||
phydm_beamforming_set_iqgen_8814A(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u8 i = 0;
|
||||
u16 counter = 0;
|
||||
u32 rf_mode[4];
|
||||
|
||||
for (i = ODM_RF_PATH_A ; i < MAX_RF_PATH ; i++)
|
||||
odm_set_rf_reg(p_dm_odm, i, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/
|
||||
|
||||
while (1) {
|
||||
counter++;
|
||||
for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++)
|
||||
odm_set_rf_reg(p_dm_odm, i, RF_RCK_OS, 0xfffff, 0x18000); /*Select Rx mode*/
|
||||
|
||||
ODM_delay_us(2);
|
||||
|
||||
for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++)
|
||||
rf_mode[i] = odm_get_rf_reg(p_dm_odm, i, RF_RCK_OS, 0xfffff);
|
||||
|
||||
if ((rf_mode[0] == 0x18000) && (rf_mode[1] == 0x18000) && (rf_mode[2] == 0x18000) && (rf_mode[3] == 0x18000))
|
||||
break;
|
||||
else if (counter == 100) {
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("iqgen setting fail:8814A\n"));
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = ODM_RF_PATH_A ; i < MAX_RF_PATH ; i++) {
|
||||
odm_set_rf_reg(p_dm_odm, i, RF_TXPA_G1, 0xfffff, 0xBE77F); /*Set Table data*/
|
||||
odm_set_rf_reg(p_dm_odm, i, RF_TXPA_G2, 0xfffff, 0x226BF); /*Enable TXIQGEN in Rx mode*/
|
||||
}
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_TXPA_G2, 0xfffff, 0xE26BF); /*Enable TXIQGEN in Rx mode*/
|
||||
|
||||
for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++)
|
||||
odm_set_rf_reg(p_dm_odm, i, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
|
||||
|
||||
return true;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
void
|
||||
hal_txbf_8814a_set_ndpa_rate(
|
||||
void *p_dm_void,
|
||||
u8 BW,
|
||||
u8 rate
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
|
||||
odm_write_1byte(p_dm_odm, REG_NDPA_OPT_CTRL_8814A, BW);
|
||||
odm_write_1byte(p_dm_odm, REG_NDPA_RATE_8814A, (u8) rate);
|
||||
|
||||
}
|
||||
|
||||
#define PHYDM_MEMORY_MAP_BUF_READ 0x8000
|
||||
#define PHYDM_CTRL_INFO_PAGE 0x660
|
||||
|
||||
void
|
||||
phydm_data_rate_8814a(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 mac_id,
|
||||
u32 *data,
|
||||
u8 data_len
|
||||
)
|
||||
{
|
||||
u8 i = 0;
|
||||
u16 x_read_data_addr = 0;
|
||||
|
||||
odm_write_2byte(p_dm_odm, REG_PKTBUF_DBG_CTRL_8814A, PHYDM_CTRL_INFO_PAGE);
|
||||
x_read_data_addr = PHYDM_MEMORY_MAP_BUF_READ + mac_id * 32; /*Ctrl Info: 32Bytes for each macid(n)*/
|
||||
|
||||
if ((x_read_data_addr < PHYDM_MEMORY_MAP_BUF_READ) || (x_read_data_addr > 0x8FFF)) {
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("x_read_data_addr(0x%x) is not correct!\n", x_read_data_addr));
|
||||
return;
|
||||
}
|
||||
|
||||
/* Read data */
|
||||
for (i = 0; i < data_len; i++)
|
||||
*(data + i) = odm_read_2byte(p_dm_odm, x_read_data_addr + i);
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
hal_txbf_8814a_get_tx_rate(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info;
|
||||
struct _RT_BEAMFORMEE_ENTRY *p_entry;
|
||||
u32 tx_rpt_data = 0;
|
||||
u8 data_rate = 0xFF;
|
||||
|
||||
p_entry = &(p_beam_info->beamformee_entry[p_beam_info->beamformee_cur_idx]);
|
||||
|
||||
phydm_data_rate_8814a(p_dm_odm, (u8)p_entry->mac_id, &tx_rpt_data, 1);
|
||||
data_rate = (u8)tx_rpt_data;
|
||||
data_rate &= 0x7f; /*Bit7 indicates SGI*/
|
||||
|
||||
p_dm_odm->tx_bf_data_rate = data_rate;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] p_dm_odm->tx_bf_data_rate = 0x%x\n", __func__, p_dm_odm->tx_bf_data_rate));
|
||||
}
|
||||
|
||||
void
|
||||
hal_txbf_8814a_reset_tx_path(
|
||||
void *p_dm_void,
|
||||
u8 idx
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if DEV_BUS_TYPE == RT_USB_INTERFACE
|
||||
struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info;
|
||||
struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
|
||||
u8 nr_index = 0, tx_ss = 0;
|
||||
|
||||
if (idx < BEAMFORMEE_ENTRY_NUM)
|
||||
beamformee_entry = p_beamforming_info->beamformee_entry[idx];
|
||||
else
|
||||
return;
|
||||
|
||||
if ((p_dm_odm->last_usb_hub) != (*p_dm_odm->hub_usb_mode)) {
|
||||
nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(p_dm_odm), beamformee_entry.comp_steering_num_of_bfer);
|
||||
|
||||
if (*p_dm_odm->hub_usb_mode == 2) {
|
||||
if (p_dm_odm->rf_type == ODM_4T4R)
|
||||
tx_ss = 0xf;
|
||||
else if (p_dm_odm->rf_type == ODM_3T3R)
|
||||
tx_ss = 0xe;
|
||||
else
|
||||
tx_ss = 0x6;
|
||||
} else if (*p_dm_odm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/
|
||||
tx_ss = 0x6;
|
||||
else
|
||||
tx_ss = 0x6;
|
||||
|
||||
if (tx_ss == 0xf) {
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f);
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0);
|
||||
} else if (tx_ss == 0xe) {
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e);
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0);
|
||||
} else if (tx_ss == 0x6) {
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936);
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360);
|
||||
}
|
||||
|
||||
if (idx == 0) {
|
||||
switch (nr_index) {
|
||||
case 0:
|
||||
break;
|
||||
|
||||
case 1: /*Nsts = 2 BC*/
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
|
||||
break;
|
||||
|
||||
case 2: /*Nsts = 3 BCD*/
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
|
||||
break;
|
||||
|
||||
default: /*nr>3, same as Case 3*/
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
switch (nr_index) {
|
||||
case 0:
|
||||
break;
|
||||
|
||||
case 1: /*Nsts = 2 BC*/
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
|
||||
break;
|
||||
|
||||
case 2: /*Nsts = 3 BCD*/
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
|
||||
break;
|
||||
|
||||
default: /*nr>3, same as Case 3*/
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
p_dm_odm->last_usb_hub = *p_dm_odm->hub_usb_mode;
|
||||
} else
|
||||
return;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
u8
|
||||
hal_txbf_8814a_get_ntx(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u8 ntx = 0, tx_ss = 3;
|
||||
|
||||
#if DEV_BUS_TYPE == RT_USB_INTERFACE
|
||||
tx_ss = *p_dm_odm->hub_usb_mode;
|
||||
#endif
|
||||
if (tx_ss == 3 || tx_ss == 2) {
|
||||
if (p_dm_odm->rf_type == ODM_4T4R)
|
||||
ntx = 3;
|
||||
else if (p_dm_odm->rf_type == ODM_3T3R)
|
||||
ntx = 2;
|
||||
else
|
||||
ntx = 1;
|
||||
} else if (tx_ss == 1) /*USB 2.0 always 2Tx*/
|
||||
ntx = 1;
|
||||
else
|
||||
ntx = 1;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ntx = %d\n", __func__, ntx));
|
||||
return ntx;
|
||||
}
|
||||
|
||||
u8
|
||||
hal_txbf_8814a_get_nrx(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u8 nrx = 0;
|
||||
|
||||
if (p_dm_odm->rf_type == ODM_4T4R)
|
||||
nrx = 3;
|
||||
else if (p_dm_odm->rf_type == ODM_3T3R)
|
||||
nrx = 2;
|
||||
else if (p_dm_odm->rf_type == ODM_2T2R)
|
||||
nrx = 1;
|
||||
else if (p_dm_odm->rf_type == ODM_2T3R)
|
||||
nrx = 2;
|
||||
else if (p_dm_odm->rf_type == ODM_2T4R)
|
||||
nrx = 3;
|
||||
else if (p_dm_odm->rf_type == ODM_1T1R)
|
||||
nrx = 0;
|
||||
else if (p_dm_odm->rf_type == ODM_1T2R)
|
||||
nrx = 1;
|
||||
else
|
||||
nrx = 0;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] nrx = %d\n", __func__, nrx));
|
||||
return nrx;
|
||||
}
|
||||
|
||||
void
|
||||
hal_txbf_8814a_rf_mode(
|
||||
void *p_dm_void,
|
||||
struct _RT_BEAMFORMING_INFO *p_beamforming_info,
|
||||
u8 idx
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u8 i, nr_index = 0;
|
||||
u8 tx_ss = 3; /*default use 3 Tx*/
|
||||
struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
|
||||
|
||||
if (idx < BEAMFORMEE_ENTRY_NUM)
|
||||
beamformee_entry = p_beamforming_info->beamformee_entry[idx];
|
||||
else
|
||||
return;
|
||||
|
||||
nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(p_dm_odm), beamformee_entry.comp_steering_num_of_bfer);
|
||||
|
||||
if (p_dm_odm->rf_type == ODM_1T1R)
|
||||
return;
|
||||
|
||||
if (p_beamforming_info->beamformee_su_cnt > 0) {
|
||||
#if DEV_BUS_TYPE == RT_USB_INTERFACE
|
||||
p_dm_odm->last_usb_hub = *p_dm_odm->hub_usb_mode;
|
||||
tx_ss = *p_dm_odm->hub_usb_mode;
|
||||
#endif
|
||||
if (tx_ss == 3 || tx_ss == 2) {
|
||||
if (p_dm_odm->rf_type == ODM_4T4R)
|
||||
tx_ss = 0xf;
|
||||
else if (p_dm_odm->rf_type == ODM_3T3R)
|
||||
tx_ss = 0xe;
|
||||
else
|
||||
tx_ss = 0x6;
|
||||
} else if (tx_ss == 1) /*USB 2.0 always 2Tx*/
|
||||
tx_ss = 0x6;
|
||||
else
|
||||
tx_ss = 0x6;
|
||||
|
||||
if (tx_ss == 0xf) {
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f);
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0);
|
||||
} else if (tx_ss == 0xe) {
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e);
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0);
|
||||
} else if (tx_ss == 0x6) {
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936);
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360);
|
||||
}
|
||||
|
||||
/*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT(28) | BIT29, 0x2); /*enable BB TxBF ant mapping register*/
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT30, 0x1); /*if Nsts > Nc don't apply V matrix*/
|
||||
|
||||
if (idx == 0) {
|
||||
switch (nr_index) {
|
||||
case 0:
|
||||
break;
|
||||
|
||||
case 1: /*Nsts = 2 BC*/
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
|
||||
break;
|
||||
|
||||
case 2: /*Nsts = 3 BCD*/
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
|
||||
break;
|
||||
|
||||
default: /*nr>3, same as Case 3*/
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
|
||||
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
switch (nr_index) {
|
||||
case 0:
|
||||
break;
|
||||
|
||||
case 1: /*Nsts = 2 BC*/
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
|
||||
break;
|
||||
|
||||
case 2: /*Nsts = 3 BCD*/
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
|
||||
break;
|
||||
|
||||
default: /*nr>3, same as Case 3*/
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if ((p_beamforming_info->beamformee_su_cnt == 0) && (p_beamforming_info->beamformer_su_cnt == 0)) {
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x932); /*set tx_path selection for 8814a BFer bug refine*/
|
||||
odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e9360);
|
||||
}
|
||||
}
|
||||
#if 0
|
||||
void
|
||||
hal_txbf_8814a_download_ndpa(
|
||||
void *p_dm_void,
|
||||
u8 idx
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u8 u1b_tmp = 0, tmp_reg422 = 0;
|
||||
u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
|
||||
u16 head_page = 0x7FE;
|
||||
bool is_send_beacon = false;
|
||||
u16 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*default reseved 1 page for the IC type which is undefined.*/
|
||||
struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info;
|
||||
struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx;
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
*p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = true;
|
||||
#endif
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
phydm_get_hal_def_var_handler_interface(p_dm_odm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy);
|
||||
|
||||
/*Set REG_CR bit 8. DMA beacon by SW.*/
|
||||
u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8814A + 1);
|
||||
odm_write_1byte(p_dm_odm, REG_CR_8814A + 1, (u1b_tmp | BIT(0)));
|
||||
|
||||
|
||||
/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
|
||||
tmp_reg422 = odm_read_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8814A + 2);
|
||||
odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422 & (~BIT(6)));
|
||||
|
||||
if (tmp_reg422 & BIT(6)) {
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: There is an adapter is sending beacon.\n", __func__));
|
||||
is_send_beacon = true;
|
||||
}
|
||||
|
||||
/*0x204[11:0] Beacon Head for TXDMA*/
|
||||
odm_write_2byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A, head_page);
|
||||
|
||||
do {
|
||||
/*Clear beacon valid check bit.*/
|
||||
bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A + 1);
|
||||
odm_write_1byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A + 1, (bcn_valid_reg | BIT(7)));
|
||||
|
||||
/*download NDPA rsvd page.*/
|
||||
if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)
|
||||
beamforming_send_vht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE);
|
||||
else
|
||||
beamforming_send_ht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
|
||||
|
||||
/*check rsvd page download OK.*/
|
||||
bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A + 1);
|
||||
count = 0;
|
||||
while (!(bcn_valid_reg & BIT(7)) && count < 20) {
|
||||
count++;
|
||||
ODM_delay_ms(10);
|
||||
bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A + 2);
|
||||
}
|
||||
dl_bcn_count++;
|
||||
} while (!(bcn_valid_reg & BIT(7)) && dl_bcn_count < 5);
|
||||
|
||||
if (!(bcn_valid_reg & BIT(7)))
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Download RSVD page failed!\n", __func__));
|
||||
|
||||
/*0x204[11:0] Beacon Head for TXDMA*/
|
||||
odm_write_2byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A, tx_page_bndy);
|
||||
|
||||
/*To make sure that if there exists an adapter which would like to send beacon.*/
|
||||
/*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
|
||||
/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
|
||||
/*the beacon cannot be sent by HW.*/
|
||||
/*2010.06.23. Added by tynli.*/
|
||||
if (is_send_beacon)
|
||||
odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422);
|
||||
|
||||
/*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
|
||||
/*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
|
||||
u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8814A + 1);
|
||||
odm_write_1byte(p_dm_odm, REG_CR_8814A + 1, (u1b_tmp & (~BIT(0))));
|
||||
|
||||
p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
*p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = false;
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
hal_txbf_8814a_fw_txbf_cmd(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u8 idx, period = 0;
|
||||
u8 PageNum0 = 0xFF, PageNum1 = 0xFF;
|
||||
u8 u1_tx_bf_parm[3] = {0};
|
||||
struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info;
|
||||
|
||||
for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
|
||||
if (p_beam_info->beamformee_entry[idx].is_used && p_beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
|
||||
if (p_beam_info->beamformee_entry[idx].is_sound) {
|
||||
PageNum0 = 0xFE;
|
||||
PageNum1 = 0x07;
|
||||
period = (u8)(p_beam_info->beamformee_entry[idx].sound_period);
|
||||
} else if (PageNum0 == 0xFF) {
|
||||
PageNum0 = 0xFF; /*stop sounding*/
|
||||
PageNum1 = 0x0F;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
u1_tx_bf_parm[0] = PageNum0;
|
||||
u1_tx_bf_parm[1] = PageNum1;
|
||||
u1_tx_bf_parm[2] = period;
|
||||
odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD,
|
||||
("[%s] PageNum0 = %d, PageNum1 = %d period = %d\n", __func__, PageNum0, PageNum1, period));
|
||||
}
|
||||
#endif
|
||||
void
|
||||
hal_txbf_8814a_enter(
|
||||
void *p_dm_void,
|
||||
u8 bfer_bfee_idx
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u8 i = 0;
|
||||
u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
|
||||
u8 bfee_idx = (bfer_bfee_idx & 0xF);
|
||||
struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info;
|
||||
struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
|
||||
struct _RT_BEAMFORMER_ENTRY beamformer_entry;
|
||||
u16 sta_id = 0, csi_param = 0;
|
||||
u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] bfer_idx=%d, bfee_idx=%d\n", __func__, bfer_idx, bfee_idx));
|
||||
odm_set_mac_reg(p_dm_odm, REG_SND_PTCL_CTRL_8814A, MASKBYTE1 | MASKBYTE2, 0x0202);
|
||||
|
||||
if ((p_beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) {
|
||||
beamformer_entry = p_beamforming_info->beamformer_entry[bfer_idx];
|
||||
/*Sounding protocol control*/
|
||||
odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8814A, 0xDB);
|
||||
|
||||
/*MAC address/Partial AID of Beamformer*/
|
||||
if (bfer_idx == 0) {
|
||||
for (i = 0; i < 6 ; i++)
|
||||
odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER0_INFO_8814A + i), beamformer_entry.mac_addr[i]);
|
||||
} else {
|
||||
for (i = 0; i < 6 ; i++)
|
||||
odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER1_INFO_8814A + i), beamformer_entry.mac_addr[i]);
|
||||
}
|
||||
|
||||
/*CSI report parameters of Beamformer*/
|
||||
nc_index = hal_txbf_8814a_get_nrx(p_dm_odm); /*for 8814A nrx = 3(4 ant), min=0(1 ant)*/
|
||||
nr_index = beamformer_entry.num_of_sounding_dim; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/
|
||||
|
||||
grouping = 0;
|
||||
|
||||
/*for ac = 1, for n = 3*/
|
||||
if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU)
|
||||
codebookinfo = 1;
|
||||
else if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT)
|
||||
codebookinfo = 3;
|
||||
|
||||
coefficientsize = 3;
|
||||
|
||||
csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index));
|
||||
|
||||
if (bfer_idx == 0)
|
||||
odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8814A, csi_param);
|
||||
else
|
||||
odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, csi_param);
|
||||
/*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/
|
||||
odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8814A + 3, 0x40);
|
||||
|
||||
}
|
||||
|
||||
if ((p_beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) {
|
||||
beamformee_entry = p_beamforming_info->beamformee_entry[bfee_idx];
|
||||
|
||||
hal_txbf_8814a_rf_mode(p_dm_odm, p_beamforming_info, bfee_idx);
|
||||
|
||||
if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss))
|
||||
sta_id = beamformee_entry.mac_id;
|
||||
else
|
||||
sta_id = beamformee_entry.p_aid;
|
||||
|
||||
/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
|
||||
if (bfee_idx == 0) {
|
||||
odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A, sta_id);
|
||||
odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7));
|
||||
} else
|
||||
odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A + 2, sta_id | BIT(14) | BIT(15) | BIT(12));
|
||||
|
||||
/*CSI report parameters of Beamformee*/
|
||||
if (bfee_idx == 0) {
|
||||
/*Get BIT24 & BIT25*/
|
||||
u8 tmp = odm_read_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3;
|
||||
|
||||
odm_write_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3, tmp | 0x60);
|
||||
odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A, sta_id | BIT(9));
|
||||
} else
|
||||
odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, sta_id | 0xE200); /*Set BIT25*/
|
||||
|
||||
phydm_beamforming_notify(p_dm_odm);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
hal_txbf_8814a_leave(
|
||||
void *p_dm_void,
|
||||
u8 idx
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info;
|
||||
struct _RT_BEAMFORMER_ENTRY beamformer_entry;
|
||||
struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
|
||||
|
||||
if (idx < BEAMFORMER_ENTRY_NUM) {
|
||||
beamformer_entry = p_beamforming_info->beamformer_entry[idx];
|
||||
beamformee_entry = p_beamforming_info->beamformee_entry[idx];
|
||||
} else
|
||||
return;
|
||||
|
||||
/*Clear P_AID of Beamformee*/
|
||||
/*Clear MAC address of Beamformer*/
|
||||
/*Clear Associated Bfmee Sel*/
|
||||
|
||||
if (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
|
||||
odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8814A, 0xD8);
|
||||
if (idx == 0) {
|
||||
odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8814A, 0);
|
||||
odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8814A + 4, 0);
|
||||
odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8814A, 0);
|
||||
} else {
|
||||
odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8814A, 0);
|
||||
odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8814A + 4, 0);
|
||||
odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, 0);
|
||||
}
|
||||
}
|
||||
|
||||
if (beamformee_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
|
||||
hal_txbf_8814a_rf_mode(p_dm_odm, p_beamforming_info, idx);
|
||||
if (idx == 0) {
|
||||
odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A, 0x0);
|
||||
odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7));
|
||||
odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A, 0);
|
||||
} else {
|
||||
odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A + 2, 0x0 | BIT(14) | BIT(15) | BIT(12));
|
||||
|
||||
odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, odm_read_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2) & 0x60);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
hal_txbf_8814a_status(
|
||||
void *p_dm_void,
|
||||
u8 idx
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u16 beam_ctrl_val, tmp_val;
|
||||
u32 beam_ctrl_reg;
|
||||
struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info;
|
||||
struct _RT_BEAMFORMEE_ENTRY beamform_entry;
|
||||
|
||||
if (idx < BEAMFORMEE_ENTRY_NUM)
|
||||
beamform_entry = p_beamforming_info->beamformee_entry[idx];
|
||||
else
|
||||
return;
|
||||
|
||||
if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss))
|
||||
beam_ctrl_val = beamform_entry.mac_id;
|
||||
else
|
||||
beam_ctrl_val = beamform_entry.p_aid;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, beamform_entry.beamform_entry_state = %d", __func__, beamform_entry.beamform_entry_state));
|
||||
|
||||
if (idx == 0)
|
||||
beam_ctrl_reg = REG_TXBF_CTRL_8814A;
|
||||
else {
|
||||
beam_ctrl_reg = REG_TXBF_CTRL_8814A + 2;
|
||||
beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
|
||||
}
|
||||
|
||||
if ((beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (p_beamforming_info->apply_v_matrix == true)) {
|
||||
if (beamform_entry.sound_bw == CHANNEL_WIDTH_20)
|
||||
beam_ctrl_val |= BIT(9);
|
||||
else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)
|
||||
beam_ctrl_val |= (BIT(9) | BIT(10));
|
||||
else if (beamform_entry.sound_bw == CHANNEL_WIDTH_80)
|
||||
beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11));
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, Don't apply Vmatrix", __func__));
|
||||
beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
|
||||
}
|
||||
|
||||
odm_write_2byte(p_dm_odm, beam_ctrl_reg, beam_ctrl_val);
|
||||
/*disable NDP packet use beamforming */
|
||||
tmp_val = odm_read_2byte(p_dm_odm, REG_TXBF_CTRL_8814A);
|
||||
odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A, tmp_val | BIT(15));
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
void
|
||||
hal_txbf_8814a_fw_txbf(
|
||||
void *p_dm_void,
|
||||
u8 idx
|
||||
)
|
||||
{
|
||||
#if 0
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info;
|
||||
struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
|
||||
hal_txbf_8814a_download_ndpa(p_dm_odm, idx);
|
||||
|
||||
hal_txbf_8814a_fw_txbf_cmd(p_dm_odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (RTL8814A_SUPPORT == 1)*/
|
||||
|
||||
#endif
|
||||
89
hal/phydm/txbf/haltxbf8814a.h
Normal file
89
hal/phydm/txbf/haltxbf8814a.h
Normal file
|
|
@ -0,0 +1,89 @@
|
|||
#ifndef __HAL_TXBF_8814A_H__
|
||||
#define __HAL_TXBF_8814A_H__
|
||||
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
|
||||
bool
|
||||
phydm_beamforming_set_iqgen_8814A(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
hal_txbf_8814a_set_ndpa_rate(
|
||||
void *p_dm_void,
|
||||
u8 BW,
|
||||
u8 rate
|
||||
);
|
||||
|
||||
u8
|
||||
hal_txbf_8814a_get_ntx(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
hal_txbf_8814a_enter(
|
||||
void *p_dm_void,
|
||||
u8 idx
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
hal_txbf_8814a_leave(
|
||||
void *p_dm_void,
|
||||
u8 idx
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
hal_txbf_8814a_status(
|
||||
void *p_dm_void,
|
||||
u8 idx
|
||||
);
|
||||
|
||||
void
|
||||
hal_txbf_8814a_reset_tx_path(
|
||||
void *p_dm_void,
|
||||
u8 idx
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
hal_txbf_8814a_get_tx_rate(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
hal_txbf_8814a_fw_txbf(
|
||||
void *p_dm_void,
|
||||
u8 idx
|
||||
);
|
||||
|
||||
#else
|
||||
|
||||
#define hal_txbf_8814a_set_ndpa_rate(p_dm_void, BW, rate)
|
||||
#define hal_txbf_8814a_get_ntx(p_dm_void) 0
|
||||
#define hal_txbf_8814a_enter(p_dm_void, idx)
|
||||
#define hal_txbf_8814a_leave(p_dm_void, idx)
|
||||
#define hal_txbf_8814a_status(p_dm_void, idx)
|
||||
#define hal_txbf_8814a_reset_tx_path(p_dm_void, idx)
|
||||
#define hal_txbf_8814a_get_tx_rate(p_dm_void)
|
||||
#define hal_txbf_8814a_fw_txbf(p_dm_void, idx)
|
||||
#define phydm_beamforming_set_iqgen_8814A(p_dm_void) 0
|
||||
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
#define hal_txbf_8814a_set_ndpa_rate(p_dm_void, BW, rate)
|
||||
#define hal_txbf_8814a_get_ntx(p_dm_void) 0
|
||||
#define hal_txbf_8814a_enter(p_dm_void, idx)
|
||||
#define hal_txbf_8814a_leave(p_dm_void, idx)
|
||||
#define hal_txbf_8814a_status(p_dm_void, idx)
|
||||
#define hal_txbf_8814a_reset_tx_path(p_dm_void, idx)
|
||||
#define hal_txbf_8814a_get_tx_rate(p_dm_void)
|
||||
#define hal_txbf_8814a_fw_txbf(p_dm_void, idx)
|
||||
#define phydm_beamforming_set_iqgen_8814A(p_dm_void) 0
|
||||
#endif
|
||||
|
||||
#endif
|
||||
1099
hal/phydm/txbf/haltxbf8822b.c
Normal file
1099
hal/phydm/txbf/haltxbf8822b.c
Normal file
File diff suppressed because it is too large
Load diff
79
hal/phydm/txbf/haltxbf8822b.h
Normal file
79
hal/phydm/txbf/haltxbf8822b.h
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
#ifndef __HAL_TXBF_8822B_H__
|
||||
#define __HAL_TXBF_8822B_H__
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
|
||||
void
|
||||
hal_txbf_8822b_enter(
|
||||
void *p_dm_void,
|
||||
u8 idx
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
hal_txbf_8822b_leave(
|
||||
void *p_dm_void,
|
||||
u8 idx
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
hal_txbf_8822b_status(
|
||||
void *p_dm_void,
|
||||
u8 beamform_idx
|
||||
);
|
||||
|
||||
void
|
||||
hal_txbf_8822b_config_gtab(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
hal_txbf_8822b_fw_txbf(
|
||||
void *p_dm_void,
|
||||
u8 idx
|
||||
);
|
||||
#else
|
||||
#define hal_txbf_8822b_enter(p_dm_void, idx)
|
||||
#define hal_txbf_8822b_leave(p_dm_void, idx)
|
||||
#define hal_txbf_8822b_status(p_dm_void, idx)
|
||||
#define hal_txbf_8822b_fw_txbf(p_dm_void, idx)
|
||||
#define hal_txbf_8822b_config_gtab(p_dm_void)
|
||||
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_BB_TXBF_API))
|
||||
void
|
||||
phydm_8822btxbf_rfmode(
|
||||
void *p_dm_void,
|
||||
u8 su_bfee_cnt,
|
||||
u8 mu_bfee_cnt
|
||||
);
|
||||
|
||||
void
|
||||
phydm_8822b_sutxbfer_workaroud(
|
||||
void *p_dm_void,
|
||||
bool enable_su_bfer,
|
||||
u8 nc,
|
||||
u8 nr,
|
||||
u8 ng,
|
||||
u8 CB,
|
||||
u8 BW,
|
||||
bool is_vht
|
||||
);
|
||||
|
||||
#else
|
||||
#define phydm_8822btxbf_rfmode(p_dm_void, su_bfee_cnt, mu_bfee_cnt)
|
||||
#define phydm_8822b_sutxbfer_workaroud(p_dm_void, enable_su_bfer, nc, nr, ng, CB, BW, is_vht)
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define hal_txbf_8822b_enter(p_dm_void, idx)
|
||||
#define hal_txbf_8822b_leave(p_dm_void, idx)
|
||||
#define hal_txbf_8822b_status(p_dm_void, idx)
|
||||
#define hal_txbf_8822b_fw_txbf(p_dm_void, idx)
|
||||
#define hal_txbf_8822b_config_gtab(p_dm_void)
|
||||
|
||||
#endif
|
||||
#endif
|
||||
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Reference in a new issue