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rtl8188EUS: Initial addition of files in branch v5.2.2.4

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2018-10-14 19:07:45 -05:00
parent 77471b4361
commit 6fa9ed423c
541 changed files with 393757 additions and 85553 deletions
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1417
hal/phydm/rtl8188e/hal8188erateadaptive.c Normal file
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hal/phydm/rtl8188e/hal8188erateadaptive.h Normal file
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#ifndef __INC_RA_H
#define __INC_RA_H
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
rate_adaptive.h
Abstract:
Prototype of RA and related data structure.
Major Change History:
When Who What
---------- --------------- -------------------------------
2011-08-12 Page Create.
--*/
/* rate adaptive define */
#define PERENTRY 23
#define RETRYSIZE 5
#define RATESIZE 28
#define TX_RPT2_ITEM_SIZE 8
#define DM_RA_RATE_UP 1
#define DM_RA_RATE_DOWN 2
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
/*
* TX report 2 format in Rx desc
* */
#define GET_TX_RPT2_DESC_PKT_LEN_88E(__prx_status_desc) LE_BITS_TO_4BYTE(__prx_status_desc, 0, 9)
#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__prx_status_desc) LE_BITS_TO_4BYTE(__prx_status_desc+16, 0, 32)
#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__prx_status_desc) LE_BITS_TO_4BYTE(__prx_status_desc+20, 0, 32)
#define GET_TX_REPORT_TYPE1_RERTY_0(__paddr) LE_BITS_TO_4BYTE(__paddr, 0, 16)
#define GET_TX_REPORT_TYPE1_RERTY_1(__paddr) LE_BITS_TO_1BYTE(__paddr+2, 0, 8)
#define GET_TX_REPORT_TYPE1_RERTY_2(__paddr) LE_BITS_TO_1BYTE(__paddr+3, 0, 8)
#define GET_TX_REPORT_TYPE1_RERTY_3(__paddr) LE_BITS_TO_1BYTE(__paddr+4, 0, 8)
#define GET_TX_REPORT_TYPE1_RERTY_4(__paddr) LE_BITS_TO_1BYTE(__paddr+4+1, 0, 8)
#define GET_TX_REPORT_TYPE1_DROP_0(__paddr) LE_BITS_TO_1BYTE(__paddr+4+2, 0, 8)
#define GET_TX_REPORT_TYPE1_DROP_1(__paddr) LE_BITS_TO_1BYTE(__paddr+4+3, 0, 8)
#endif
/* End rate adaptive define */
void
odm_ra_support_init(
struct PHY_DM_STRUCT *p_dm_odm
);
int
odm_ra_info_init_all(
struct PHY_DM_STRUCT *p_dm_odm
);
int
odm_ra_info_init(
struct PHY_DM_STRUCT *p_dm_odm,
u32 mac_id
);
u8
odm_ra_get_sgi_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u8 mac_id
);
u8
odm_ra_get_decision_rate_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u8 mac_id
);
u8
odm_ra_get_hw_pwr_status_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u8 mac_id
);
void
odm_ra_update_rate_info_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u8 mac_id,
u8 rate_id,
u32 rate_mask,
u8 sgi_enable
);
void
odm_ra_set_rssi_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u8 mac_id,
u8 rssi
);
void
odm_ra_tx_rpt2_handle_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u8 *tx_rpt_buf,
u16 tx_rpt_len,
u32 mac_id_valid_entry0,
u32 mac_id_valid_entry1
);
void
odm_ra_set_tx_rpt_time(
struct PHY_DM_STRUCT *p_dm_odm,
u16 min_rpt_time
);
#endif

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hal/phydm/rtl8188e/hal8188ereg.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/* ************************************************************
* File Name: hal8188ereg.h
*
* Description:
*
* This file is for RTL8188E register definition.
*
*
* ************************************************************ */
#ifndef __HAL_8188E_REG_H__
#define __HAL_8188E_REG_H__
/*
* Register Definition
* */
#define TRX_ANTDIV_PATH 0x860
#define RX_ANTDIV_PATH 0xb2c
#define ODM_R_A_AGC_CORE1_8188E 0xc50
#define REG_GPIO_EXT_CTRL 0x0060
#define REG_MCUFWDL_8188E 0x0080
#define REG_FW_DBG_STATUS_8188E 0x0088
#define REG_FW_DBG_CTRL_8188E 0x008F
#define REG_CR_8188E 0x0100
/*
* Bitmap Definition
* */
#define BIT_FA_RESET_8188E BIT(0)
#define REG_ADAPTIVE_DATA_RATE_0 0x2B0
#define REG_DBI_WDATA_8188 0x0348 /* DBI Write data */
#define REG_DBI_RDATA_8188 0x034C /* DBI Read data */
#define REG_DBI_ADDR_8188 0x0350 /* DBI Address */
#define REG_DBI_FLAG_8188 0x0352 /* DBI Read/Write Flag */
#define REG_MDIO_WDATA_8188E 0x0354 /* MDIO for Write PCIE PHY */
#define REG_MDIO_RDATA_8188E 0x0356 /* MDIO for Reads PCIE PHY */
#define REG_MDIO_CTL_8188E 0x0358 /* MDIO for Control */
/* [0-63] */
#define REG_MACID_NO_LINK 0x484 /* No Link register (bit[x] enabled means dropping packets for MACID in HW queue) */
#endif

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hal/phydm/rtl8188e/halhwimg8188e_bb.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.18*/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_MP_BB_HW_IMG_8188E_H
#define __INC_MP_BB_HW_IMG_8188E_H
/******************************************************************************
* AGC_TAB.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_agc_tab(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8188e_agc_tab(void);
/******************************************************************************
* PHY_REG.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_phy_reg(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8188e_phy_reg(void);
/******************************************************************************
* PHY_REG_PG.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_phy_reg_pg(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8188e_phy_reg_pg(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.18*/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8188E_SUPPORT == 1)
static bool
check_positive(
struct PHY_DM_STRUCT *p_dm_odm,
const u32 condition1,
const u32 condition2,
const u32 condition3,
const u32 condition4
)
{
u8 _board_type = ((p_dm_odm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
((p_dm_odm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
((p_dm_odm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
((p_dm_odm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
((p_dm_odm->board_type & BIT(2)) >> 2) << 4; /* _BT*/
u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
u32 driver1 = p_dm_odm->cut_version << 24 |
(p_dm_odm->support_interface & 0xF0) << 16 |
p_dm_odm->support_platform << 16 |
p_dm_odm->package_type << 12 |
(p_dm_odm->support_interface & 0x0F) << 8 |
_board_type;
u32 driver2 = (p_dm_odm->type_glna & 0xFF) << 0 |
(p_dm_odm->type_gpa & 0xFF) << 8 |
(p_dm_odm->type_alna & 0xFF) << 16 |
(p_dm_odm->type_apa & 0xFF) << 24;
u32 driver3 = 0;
u32 driver4 = (p_dm_odm->type_glna & 0xFF00) >> 8 |
(p_dm_odm->type_gpa & 0xFF00) |
(p_dm_odm->type_alna & 0xFF00) << 8 |
(p_dm_odm->type_apa & 0xFF00) << 16;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
("===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
("===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
(" (Platform, Interface) = (0x%X, 0x%X)\n", p_dm_odm->support_platform, p_dm_odm->support_interface));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
(" (Board, Package) = (0x%X, 0x%X)\n", p_dm_odm->board_type, p_dm_odm->package_type));
/*============== value Defined Check ===============*/
/*QFN type [15:12] and cut version [27:24] need to do value check*/
if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
return false;
if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
return false;
/*=============== Bit Defined Check ================*/
/* We don't care [31:28] */
cond1 &= 0x00FF0FFF;
driver1 &= 0x00FF0FFF;
if ((cond1 & driver1) == cond1) {
u32 bit_mask = 0;
if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
return true;
if ((cond1 & BIT(0)) != 0) /*GLNA*/
bit_mask |= 0x000000FF;
if ((cond1 & BIT(1)) != 0) /*GPA*/
bit_mask |= 0x0000FF00;
if ((cond1 & BIT(2)) != 0) /*ALNA*/
bit_mask |= 0x00FF0000;
if ((cond1 & BIT(3)) != 0) /*APA*/
bit_mask |= 0xFF000000;
if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask))) /* board_type of each RF path is matched*/
return true;
else
return false;
} else
return false;
}
static bool
check_negative(
struct PHY_DM_STRUCT *p_dm_odm,
const u32 condition1,
const u32 condition2
)
{
return true;
}
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
u32 array_mp_8188e_mac_reg[] = {
0x026, 0x00000041,
0x027, 0x00000035,
0x80000002, 0x00000000, 0x40000000, 0x00000000,
0x040, 0x0000000C,
0x90000001, 0x00000000, 0x40000000, 0x00000000,
0x040, 0x0000000C,
0x90000001, 0x00000001, 0x40000000, 0x00000000,
0x040, 0x0000000C,
0x90000001, 0x00000002, 0x40000000, 0x00000000,
0x040, 0x0000000C,
0xA0000000, 0x00000000,
0x040, 0x00000000,
0xB0000000, 0x00000000,
0x421, 0x0000000F,
0x428, 0x0000000A,
0x429, 0x00000010,
0x430, 0x00000000,
0x431, 0x00000001,
0x432, 0x00000002,
0x433, 0x00000004,
0x434, 0x00000005,
0x435, 0x00000006,
0x436, 0x00000007,
0x437, 0x00000008,
0x438, 0x00000000,
0x439, 0x00000000,
0x43A, 0x00000001,
0x43B, 0x00000002,
0x43C, 0x00000004,
0x43D, 0x00000005,
0x43E, 0x00000006,
0x43F, 0x00000007,
0x440, 0x0000005D,
0x441, 0x00000001,
0x442, 0x00000000,
0x444, 0x00000015,
0x445, 0x000000F0,
0x446, 0x0000000F,
0x447, 0x00000000,
0x458, 0x00000041,
0x459, 0x000000A8,
0x45A, 0x00000072,
0x45B, 0x000000B9,
0x460, 0x00000066,
0x461, 0x00000066,
0x480, 0x00000008,
0x4C8, 0x000000FF,
0x4C9, 0x00000008,
0x4CC, 0x000000FF,
0x4CD, 0x000000FF,
0x4CE, 0x00000001,
0x4D3, 0x00000001,
0x500, 0x00000026,
0x501, 0x000000A2,
0x502, 0x0000002F,
0x503, 0x00000000,
0x504, 0x00000028,
0x505, 0x000000A3,
0x506, 0x0000005E,
0x507, 0x00000000,
0x508, 0x0000002B,
0x509, 0x000000A4,
0x50A, 0x0000005E,
0x50B, 0x00000000,
0x50C, 0x0000004F,
0x50D, 0x000000A4,
0x50E, 0x00000000,
0x50F, 0x00000000,
0x512, 0x0000001C,
0x514, 0x0000000A,
0x516, 0x0000000A,
0x525, 0x0000004F,
0x550, 0x00000010,
0x551, 0x00000010,
0x559, 0x00000002,
0x55D, 0x000000FF,
0x605, 0x00000030,
0x608, 0x0000000E,
0x609, 0x0000002A,
0x620, 0x000000FF,
0x621, 0x000000FF,
0x622, 0x000000FF,
0x623, 0x000000FF,
0x624, 0x000000FF,
0x625, 0x000000FF,
0x626, 0x000000FF,
0x627, 0x000000FF,
0x63C, 0x00000008,
0x63D, 0x00000008,
0x63E, 0x0000000C,
0x63F, 0x0000000C,
0x640, 0x00000040,
0x652, 0x00000020,
0x66E, 0x00000005,
0x700, 0x00000021,
0x701, 0x00000043,
0x702, 0x00000065,
0x703, 0x00000087,
0x708, 0x00000021,
0x709, 0x00000043,
0x70A, 0x00000065,
0x70B, 0x00000087,
};
void
odm_read_and_config_mp_8188e_mac_reg(
struct PHY_DM_STRUCT *p_dm_odm
)
{
u32 i = 0;
u8 c_cond;
bool is_matched = true, is_skipped = false;
u32 array_len = sizeof(array_mp_8188e_mac_reg) / sizeof(u32);
u32 *array = array_mp_8188e_mac_reg;
u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8188e_mac_reg\n"));
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
if (v1 & (BIT(31) | BIT30)) {/*positive & negative condition*/
if (v1 & BIT(31)) {/* positive condition*/
c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
if (c_cond == COND_ENDIF) {/*end*/
is_matched = true;
is_skipped = false;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n"));
} else if (c_cond == COND_ELSE) { /*else*/
is_matched = is_skipped ? false : true;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n"));
} else {/*if , else if*/
pre_v1 = v1;
pre_v2 = v2;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n"));
}
} else if (v1 & BIT(30)) { /*negative condition*/
if (is_skipped == false) {
if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) {
is_matched = true;
is_skipped = true;
} else {
is_matched = false;
is_skipped = false;
}
} else
is_matched = false;
}
} else {
if (is_matched)
odm_config_mac_8188e(p_dm_odm, v1, (u8)v2);
}
i = i + 2;
}
}
u32
odm_get_version_mp_8188e_mac_reg(void)
{
return 70;
}
#endif /* end of HWIMG_SUPPORT*/

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.18*/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_MP_MAC_HW_IMG_8188E_H
#define __INC_MP_MAC_HW_IMG_8188E_H
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_mac_reg(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8188e_mac_reg(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.18*/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_MP_RF_HW_IMG_8188E_H
#define __INC_MP_RF_HW_IMG_8188E_H
/******************************************************************************
* RadioA.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_radioa(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8188e_radioa(void);
/******************************************************************************
* TxPowerTrack_AP.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpowertrack_ap(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8188e_txpowertrack_ap(void);
/******************************************************************************
* TxPowerTrack_PCIE.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpowertrack_pcie(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8188e_txpowertrack_pcie(void);
/******************************************************************************
* TxPowerTrack_PCIE_ICUT.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpowertrack_pcie_icut(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8188e_txpowertrack_pcie_icut(void);
/******************************************************************************
* TxPowerTrack_SDIO.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpowertrack_sdio(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8188e_txpowertrack_sdio(void);
/******************************************************************************
* TxPowerTrack_SDIO_ICUT.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpowertrack_sdio_icut(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8188e_txpowertrack_sdio_icut(void);
/******************************************************************************
* TxPowerTrack_USB.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpowertrack_usb(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8188e_txpowertrack_usb(void);
/******************************************************************************
* TxPowerTrack_USB_ICUT.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpowertrack_usb_icut(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8188e_txpowertrack_usb_icut(void);
/******************************************************************************
* TXPWR_LMT.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpwr_lmt(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8188e_txpwr_lmt(void);
/******************************************************************************
* TXPWR_LMT_88EE_M2_for_MSI.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpwr_lmt_88e_e_m2_for_msi(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8188e_txpwr_lmt_88ee_m2_for_msi(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.16*/
#if (RTL8188E_S_SUPPORT == 1)
#ifndef __INC_MP_FW_HW_IMG_8188E_S_H
#define __INC_MP_FW_HW_IMG_8188E_S_H
/******************************************************************************
* FW_AP.TXT
******************************************************************************/
void
odm_read_firmware_mp_8188e_s_fw_ap(
struct PHY_DM_STRUCT *p_dm_odm,
u8 *p_firmware,
u32 *p_firmware_size
);
/******************************************************************************
* FW_NIC.TXT
******************************************************************************/
void
odm_read_firmware_mp_8188e_s_fw_nic(
struct PHY_DM_STRUCT *p_dm_odm,
u8 *p_firmware,
u32 *p_firmware_size
);
/******************************************************************************
* FW_WoWLAN.TXT
******************************************************************************/
void
odm_read_firmware_mp_8188e_s_fw_wowlan(
struct PHY_DM_STRUCT *p_dm_odm,
u8 *p_firmware,
u32 *p_firmware_size
);
#endif
#endif /* end of HWIMG_SUPPORT*/

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.16*/
#if (RTL8188E_T_SUPPORT == 1)
#ifndef __INC_MP_FW_HW_IMG_8188E_T_H
#define __INC_MP_FW_HW_IMG_8188E_T_H
/******************************************************************************
* FW_AP.TXT
******************************************************************************/
void
odm_read_firmware_mp_8188e_t_fw_ap(
struct PHY_DM_STRUCT *p_dm_odm,
u8 *p_firmware,
u32 *p_firmware_size
);
/******************************************************************************
* FW_NIC.TXT
******************************************************************************/
void
odm_read_firmware_mp_8188e_t_fw_nic(
struct PHY_DM_STRUCT *p_dm_odm,
u8 *p_firmware,
u32 *p_firmware_size
);
/******************************************************************************
* FW_NIC_89EM.TXT
******************************************************************************/
void
odm_read_firmware_mp_8188e_t_fw_nic_89e_m(
struct PHY_DM_STRUCT *p_dm_odm,
u8 *p_firmware,
u32 *p_firmware_size
);
/******************************************************************************
* FW_WoWLAN.TXT
******************************************************************************/
void
odm_read_firmware_mp_8188e_t_fw_wowlan(
struct PHY_DM_STRUCT *p_dm_odm,
u8 *p_firmware,
u32 *p_firmware_size
);
#endif
#endif /* end of HWIMG_SUPPORT*/

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_8188E_H__
#define __HAL_PHY_RF_8188E_H__
/*--------------------------Define Parameters-------------------------------*/
#define IQK_DELAY_TIME_88E 10 /* ms */
#define index_mapping_NUM_88E 15
#define AVG_THERMAL_NUM_88E 4
#include "../halphyrf_ap.h"
void configure_txpower_track_8188e(
struct _TXPWRTRACK_CFG *p_config
);
void do_iqk_8188e(
void *p_dm_void,
u8 delta_thermal_index,
u8 thermal_value,
u8 threshold
);
void
odm_tx_pwr_track_set_pwr88_e(
struct PHY_DM_STRUCT *p_dm_odm,
enum pwrtrack_method method,
u8 rf_path,
u8 channel_mapped_index
);
/* 1 7. IQK */
void
phy_iq_calibrate_8188e(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm,
#else
struct _ADAPTER *adapter,
#endif
bool is_recovery);
/*
* LC calibrate
* */
void
phy_lc_calibrate_8188e(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm
#else
struct _ADAPTER *p_adapter
#endif
);
/*
* AP calibrate
* */
void
phy_ap_calibrate_8188e(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm,
#else
struct _ADAPTER *p_adapter,
#endif
s8 delta);
void
phy_digital_predistortion_8188e(struct _ADAPTER *p_adapter);
void
_phy_save_adda_registers(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm,
#else
struct _ADAPTER *p_adapter,
#endif
u32 *adda_reg,
u32 *adda_backup,
u32 register_num
);
void
_phy_path_adda_on(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm,
#else
struct _ADAPTER *p_adapter,
#endif
u32 *adda_reg,
bool is_path_a_on,
bool is2T
);
void
_phy_mac_setting_calibration(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm,
#else
struct _ADAPTER *p_adapter,
#endif
u32 *mac_reg,
u32 *mac_backup
);
void
_phy_path_a_stand_by(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm
#else
struct _ADAPTER *p_adapter
#endif
);
#endif /* #ifndef __HAL_PHY_RF_8188E_H__ */

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_8188E_H__
#define __HAL_PHY_RF_8188E_H__
/*--------------------------Define Parameters-------------------------------*/
#define IQK_DELAY_TIME_88E 10 /* ms */
#define index_mapping_NUM_88E 15
#define AVG_THERMAL_NUM_88E 4
#include "../halphyrf_ce.h"
void configure_txpower_track_8188e(
struct _TXPWRTRACK_CFG *p_config
);
void
get_delta_swing_table_8188e(
void *p_dm_void,
u8 **temperature_up_a,
u8 **temperature_down_a,
u8 **temperature_up_b,
u8 **temperature_down_b
);
void do_iqk_8188e(
void *p_dm_void,
u8 delta_thermal_index,
u8 thermal_value,
u8 threshold
);
void
odm_tx_pwr_track_set_pwr88_e(
void *p_dm_void,
enum pwrtrack_method method,
u8 rf_path,
u8 channel_mapped_index
);
/* 1 7. IQK */
void
phy_iq_calibrate_8188e(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm,
#else
struct _ADAPTER *adapter,
#endif
bool is_recovery);
/*
* LC calibrate
* */
void
phy_lc_calibrate_8188e(
void *p_dm_void
);
#if 0
/*
* AP calibrate
* */
void
phy_ap_calibrate_8188e(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm,
#else
struct _ADAPTER *p_adapter,
#endif
s8 delta);
#endif
void
phy_digital_predistortion_8188e(struct _ADAPTER *p_adapter);
void
_phy_save_adda_registers(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm,
#else
struct _ADAPTER *p_adapter,
#endif
u32 *adda_reg,
u32 *adda_backup,
u32 register_num
);
void
_phy_path_adda_on(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm,
#else
struct _ADAPTER *p_adapter,
#endif
u32 *adda_reg,
bool is_path_a_on,
bool is2T
);
void
_phy_mac_setting_calibration(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm,
#else
struct _ADAPTER *p_adapter,
#endif
u32 *mac_reg,
u32 *mac_backup
);
void
_phy_path_a_stand_by(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm
#else
struct _ADAPTER *p_adapter
#endif
);
#endif /* #ifndef __HAL_PHY_RF_8188E_H__ */

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_8188E_H__
#define __HAL_PHY_RF_8188E_H__
/*--------------------------Define Parameters-------------------------------*/
#define IQK_DELAY_TIME_88E 15 /* ms */
#define IQK_DELAY_TIME_8723B 10 /* ms */
#define index_mapping_NUM_88E 15
#define AVG_THERMAL_NUM_88E 4
#include "halphyrf_win.h"
void configure_txpower_track_8188e(
struct _TXPWRTRACK_CFG *p_config
);
void
get_delta_swing_table_8188e(
void *p_dm_void,
u8 **temperature_up_a,
u8 **temperature_down_a,
u8 **temperature_up_b,
u8 **temperature_down_b
);
void do_iqk_8188e(
void *p_dm_void,
u8 delta_thermal_index,
u8 thermal_value,
u8 threshold
);
void
odm_tx_pwr_track_set_pwr88_e(
void *p_dm_void,
enum pwrtrack_method method,
u8 rf_path,
u8 channel_mapped_index
);
/* 1 7. IQK */
void
phy_iq_calibrate_8188e(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm,
#else
struct _ADAPTER *adapter,
#endif
bool is_recovery);
/*
* LC calibrate
* */
void
phy_lc_calibrate_8188e(
void *p_dm_void
);
/*
* AP calibrate
* */
void
phy_ap_calibrate_8188e(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm,
#else
struct _ADAPTER *p_adapter,
#endif
s8 delta);
void
phy_digital_predistortion_8188e(struct _ADAPTER *p_adapter);
#define phy_dp_calibrate_8821a phy_dp_calibrate_8812a
void
_phy_save_adda_registers(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm,
#else
struct _ADAPTER *p_adapter,
#endif
u32 *adda_reg,
u32 *adda_backup,
u32 register_num
);
void
_phy_path_adda_on(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm,
#else
struct _ADAPTER *p_adapter,
#endif
u32 *adda_reg,
bool is_path_a_on,
bool is2T
);
void
_phy_mac_setting_calibration(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm,
#else
struct _ADAPTER *p_adapter,
#endif
u32 *mac_reg,
u32 *mac_backup
);
void
_phy_path_a_stand_by(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct PHY_DM_STRUCT *p_dm_odm
#else
struct _ADAPTER *p_adapter
#endif
);
#endif /* #ifndef __HAL_PHY_RF_8188E_H__ */

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8188E_SUPPORT == 1)
void
odm_config_rf_reg_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u32 data,
enum odm_rf_radio_path_e RF_PATH,
u32 reg_addr
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#ifndef SMP_SYNC
unsigned long x;
#endif
struct rtl8192cd_priv *priv = p_dm_odm->priv;
#endif
if (addr == 0xffe) {
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
} else if (addr == 0xfd)
ODM_delay_ms(5);
else if (addr == 0xfc)
ODM_delay_ms(1);
else if (addr == 0xfb)
ODM_delay_us(50);
else if (addr == 0xfa)
ODM_delay_us(5);
else if (addr == 0xf9)
ODM_delay_us(1);
else {
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
SAVE_INT_AND_CLI(x);
odm_set_rf_reg(p_dm_odm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
RESTORE_INT(x);
#else
odm_set_rf_reg(p_dm_odm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
#endif
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
}
}
void
odm_config_rf_radio_a_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u32 data
)
{
u32 content = 0x1000; /* RF_Content: radioa_txt */
u32 maskfor_phy_set = (u32)(content & 0xE000);
odm_config_rf_reg_8188e(p_dm_odm, addr, data, ODM_RF_PATH_A, addr | maskfor_phy_set);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n", addr, data));
}
void
odm_config_rf_radio_b_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u32 data
)
{
u32 content = 0x1001; /* RF_Content: radiob_txt */
u32 maskfor_phy_set = (u32)(content & 0xE000);
odm_config_rf_reg_8188e(p_dm_odm, addr, data, ODM_RF_PATH_B, addr | maskfor_phy_set);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n", addr, data));
}
void
odm_config_mac_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u8 data
)
{
odm_write_1byte(p_dm_odm, addr, data);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n", addr, data));
}
void
odm_config_bb_agc_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u32 bitmask,
u32 data
)
{
odm_set_bb_reg(p_dm_odm, addr, bitmask, data);
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n", addr, data));
}
void
odm_config_bb_phy_reg_pg_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u32 band,
u32 rf_path,
u32 tx_num,
u32 addr,
u32 bitmask,
u32 data
)
{
if (addr == 0xfe) {
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
} else if (addr == 0xfd)
ODM_delay_ms(5);
else if (addr == 0xfc)
ODM_delay_ms(1);
else if (addr == 0xfb)
ODM_delay_us(50);
else if (addr == 0xfa)
ODM_delay_us(5);
else if (addr == 0xf9)
ODM_delay_us(1);
else {
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n", addr, bitmask, data));
#if !(DM_ODM_SUPPORT_TYPE&ODM_AP)
phy_store_tx_power_by_rate(p_dm_odm->adapter, band, rf_path, tx_num, addr, bitmask, data);
#endif
}
}
void
odm_config_bb_txpwr_lmt_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u8 *regulation,
u8 *band,
u8 *bandwidth,
u8 *rate_section,
u8 *rf_path,
u8 *channel,
u8 *power_limit
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
phy_set_tx_power_limit(p_dm_odm, regulation, band,
bandwidth, rate_section, rf_path, channel, power_limit);
#endif
}
void
odm_config_bb_phy_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u32 bitmask,
u32 data
)
{
if (addr == 0xfe) {
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
} else if (addr == 0xfd)
ODM_delay_ms(5);
else if (addr == 0xfc)
ODM_delay_ms(1);
else if (addr == 0xfb)
ODM_delay_us(50);
else if (addr == 0xfa)
ODM_delay_us(5);
else if (addr == 0xf9)
ODM_delay_us(1);
else {
if (addr == 0xa24)
p_dm_odm->rf_calibrate_info.rega24 = data;
odm_set_bb_reg(p_dm_odm, addr, bitmask, data);
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X\n", addr, data));
}
}
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_ODM_REGCONFIG_H_8188E
#define __INC_ODM_REGCONFIG_H_8188E
#if (RTL8188E_SUPPORT == 1)
void
odm_config_rf_reg_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u32 data,
enum odm_rf_radio_path_e RF_PATH,
u32 reg_addr
);
void
odm_config_rf_radio_a_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u32 data
);
void
odm_config_rf_radio_b_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u32 data
);
void
odm_config_mac_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u8 data
);
void
odm_config_bb_agc_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u32 bitmask,
u32 data
);
void
odm_config_bb_phy_reg_pg_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u32 band,
u32 rf_path,
u32 tx_num,
u32 addr,
u32 bitmask,
u32 data
);
void
odm_config_bb_phy_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u32 bitmask,
u32 data
);
void
odm_config_bb_txpwr_lmt_8188e(
struct PHY_DM_STRUCT *p_dm_odm,
u8 *regulation,
u8 *band,
u8 *bandwidth,
u8 *rate_section,
u8 *rf_path,
u8 *channel,
u8 *power_limit
);
#endif
#endif /* end of SUPPORT */

388
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/* ************************************************************
* include files
* ************************************************************ */
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8188E_SUPPORT == 1)
void
odm_dig_lower_bound_88e(
struct PHY_DM_STRUCT *p_dm_odm
)
{
struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table;
if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) {
p_dm_dig_table->rx_gain_range_min = (u8) p_dm_dig_table->ant_div_rssi_max;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_dig_lower_bound_88e(): p_dm_dig_table->ant_div_rssi_max=%d\n", p_dm_dig_table->ant_div_rssi_max));
}
/* If only one Entry connected */
}
/*=============================================================
* AntDiv Before Link
===============================================================*/
void
odm_sw_ant_div_reset_before_link(
struct PHY_DM_STRUCT *p_dm_odm
)
{
struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table;
p_dm_swat_table->swas_no_link_state = 0;
}
/* 3============================================================
* 3 Dynamic Primary CCA
* 3============================================================ */
void
odm_primary_cca_init(
struct PHY_DM_STRUCT *p_dm_odm)
{
struct _dynamic_primary_cca *primary_cca = &(p_dm_odm->dm_pri_cca);
primary_cca->dup_rts_flag = 0;
primary_cca->intf_flag = 0;
primary_cca->intf_type = 0;
primary_cca->monitor_flag = 0;
primary_cca->pri_cca_flag = 0;
}
bool
odm_dynamic_primary_cca_dup_rts(
struct PHY_DM_STRUCT *p_dm_odm
)
{
struct _dynamic_primary_cca *primary_cca = &(p_dm_odm->dm_pri_cca);
return primary_cca->dup_rts_flag;
}
void
odm_dynamic_primary_cca(
struct PHY_DM_STRUCT *p_dm_odm
)
{
#if (DM_ODM_SUPPORT_TYPE != ODM_CE)
struct _ADAPTER *adapter = p_dm_odm->adapter; /* for NIC */
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
struct sta_info *p_entry;
#endif
struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT);
struct _dynamic_primary_cca *primary_cca = &(p_dm_odm->dm_pri_cca);
bool is_40mhz;
bool client_40mhz = false, client_tmp = false; /* connected client BW */
bool is_connected = false; /* connected or not */
static u8 client_40mhz_pre = 0;
static u64 last_tx_ok_cnt = 0;
static u64 last_rx_ok_cnt = 0;
static u32 counter = 0;
static u8 delay = 1;
u64 cur_tx_ok_cnt;
u64 cur_rx_ok_cnt;
u8 sec_ch_offset;
u8 i;
if (!(p_dm_odm->support_ability & ODM_BB_PRIMARY_CCA))
return;
if (p_dm_odm->support_ic_type != ODM_RTL8188E)
return;
is_40mhz = *(p_dm_odm->p_band_width);
sec_ch_offset = *(p_dm_odm->p_sec_ch_offset);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Second CH Offset = %d\n", sec_ch_offset));
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
if (is_40mhz == 1)
sec_ch_offset = sec_ch_offset % 2 + 1; /* NIC's definition is reverse to AP 1:secondary below, 2: secondary above */
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Second CH Offset = %d\n", sec_ch_offset));
/* 3 Check Current WLAN Traffic */
cur_tx_ok_cnt = adapter->TxStats.NumTxBytesUnicast - last_tx_ok_cnt;
cur_rx_ok_cnt = adapter->RxStats.NumRxBytesUnicast - last_rx_ok_cnt;
last_tx_ok_cnt = adapter->TxStats.NumTxBytesUnicast;
last_rx_ok_cnt = adapter->RxStats.NumRxBytesUnicast;
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
/* 3 Check Current WLAN Traffic */
cur_tx_ok_cnt = *(p_dm_odm->p_num_tx_bytes_unicast) - last_tx_ok_cnt;
cur_rx_ok_cnt = *(p_dm_odm->p_num_rx_bytes_unicast) - last_rx_ok_cnt;
last_tx_ok_cnt = *(p_dm_odm->p_num_tx_bytes_unicast);
last_rx_ok_cnt = *(p_dm_odm->p_num_rx_bytes_unicast);
#endif
/* ==================Debug Message==================== */
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("TP = %llu\n", cur_tx_ok_cnt + cur_rx_ok_cnt));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("is_40mhz = %d\n", is_40mhz));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("BW_LSC = %d\n", false_alm_cnt->cnt_bw_lsc));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("BW_USC = %d\n", false_alm_cnt->cnt_bw_usc));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCA OFDM = %d\n", false_alm_cnt->cnt_ofdm_cca));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCA CCK = %d\n", false_alm_cnt->cnt_cck_cca));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("OFDM FA = %d\n", false_alm_cnt->cnt_ofdm_fail));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCK FA = %d\n", false_alm_cnt->cnt_cck_fail));
/* ================================================ */
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
if (ACTING_AS_AP(adapter)) /* primary cca process only do at AP mode */
#endif
{
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("ACTING as AP mode=%d\n", ACTING_AS_AP(adapter)));
/* 3 To get entry's connection and BW infomation status. */
for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) {
if (IsAPModeExist(adapter) && GetFirstExtAdapter(adapter) != NULL)
p_entry = AsocEntry_EnumStation(GetFirstExtAdapter(adapter), i);
else
p_entry = AsocEntry_EnumStation(GetDefaultAdapter(adapter), i);
if (p_entry != NULL) {
client_tmp = p_entry->BandWidth; /* client BW */
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Client_BW=%d\n", client_tmp));
if (client_tmp > client_40mhz)
client_40mhz = client_tmp; /* 40M/20M coexist => 40M priority is High */
if (p_entry->bAssociated) {
is_connected = true; /* client is connected or not */
break;
}
} else
break;
}
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
/* 3 To get entry's connection and BW infomation status. */
struct sta_info *pstat;
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
pstat = p_dm_odm->p_odm_sta_info[i];
if (IS_STA_VALID(pstat)) {
client_tmp = pstat->tx_bw;
if (client_tmp > client_40mhz)
client_40mhz = client_tmp; /* 40M/20M coexist => 40M priority is High */
is_connected = true;
}
}
#endif
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("is_connected=%d\n", is_connected));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Is Client 40MHz=%d\n", client_40mhz));
/* 1 Monitor whether the interference exists or not */
if (primary_cca->monitor_flag == 1) {
if (sec_ch_offset == 1) { /* secondary channel is below the primary channel */
if ((false_alm_cnt->cnt_ofdm_cca > 500) && (false_alm_cnt->cnt_bw_lsc > false_alm_cnt->cnt_bw_usc + 500)) {
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1) {
primary_cca->intf_type = 1;
primary_cca->pri_cca_flag = 1;
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT7, 2); /* USC MF */
if (primary_cca->dup_rts_flag == 1)
primary_cca->dup_rts_flag = 0;
} else {
primary_cca->intf_type = 2;
if (primary_cca->dup_rts_flag == 0)
primary_cca->dup_rts_flag = 1;
}
} else { /* interferecne disappear */
primary_cca->dup_rts_flag = 0;
primary_cca->intf_flag = 0;
primary_cca->intf_type = 0;
}
} else if (sec_ch_offset == 2) { /* secondary channel is above the primary channel */
if ((false_alm_cnt->cnt_ofdm_cca > 500) && (false_alm_cnt->cnt_bw_usc > false_alm_cnt->cnt_bw_lsc + 500)) {
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1) {
primary_cca->intf_type = 1;
primary_cca->pri_cca_flag = 1;
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT7, 1); /* LSC MF */
if (primary_cca->dup_rts_flag == 1)
primary_cca->dup_rts_flag = 0;
} else {
primary_cca->intf_type = 2;
if (primary_cca->dup_rts_flag == 0)
primary_cca->dup_rts_flag = 1;
}
} else { /* interferecne disappear */
primary_cca->dup_rts_flag = 0;
primary_cca->intf_flag = 0;
primary_cca->intf_type = 0;
}
}
primary_cca->monitor_flag = 0;
}
/* 1 Dynamic Primary CCA Main Function */
if (primary_cca->monitor_flag == 0) {
if (is_40mhz) { /* if RFBW==40M mode which require to process primary cca */
/* 2 STA is NOT Connected */
if (!is_connected) {
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("STA NOT Connected!!!!\n"));
if (primary_cca->pri_cca_flag == 1) { /* reset primary cca when STA is disconnected */
primary_cca->pri_cca_flag = 0;
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT(7), 0);
}
if (primary_cca->dup_rts_flag == 1) /* reset Duplicate RTS when STA is disconnected */
primary_cca->dup_rts_flag = 0;
if (sec_ch_offset == 1) { /* secondary channel is below the primary channel */
if ((false_alm_cnt->cnt_ofdm_cca > 800) && (false_alm_cnt->cnt_bw_lsc * 5 > false_alm_cnt->cnt_bw_usc * 9)) {
primary_cca->intf_flag = 1; /* secondary channel interference is detected!!! */
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
primary_cca->intf_type = 1; /* interference is shift */
else
primary_cca->intf_type = 2; /* interference is in-band */
} else {
primary_cca->intf_flag = 0;
primary_cca->intf_type = 0;
}
} else if (sec_ch_offset == 2) { /* secondary channel is above the primary channel */
if ((false_alm_cnt->cnt_ofdm_cca > 800) && (false_alm_cnt->cnt_bw_usc * 5 > false_alm_cnt->cnt_bw_lsc * 9)) {
primary_cca->intf_flag = 1; /* secondary channel interference is detected!!! */
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
primary_cca->intf_type = 1; /* interference is shift */
else
primary_cca->intf_type = 2; /* interference is in-band */
} else {
primary_cca->intf_flag = 0;
primary_cca->intf_type = 0;
}
}
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("primary_cca=%d\n", primary_cca->pri_cca_flag));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Intf_Type=%d\n", primary_cca->intf_type));
}
/* 2 STA is Connected */
else {
if (client_40mhz == 0) /* 3 */ { /* client BW = 20MHz */
if (primary_cca->pri_cca_flag == 0) {
primary_cca->pri_cca_flag = 1;
if (sec_ch_offset == 1)
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT(7), 2);
else if (sec_ch_offset == 2)
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT(7), 1);
}
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("STA Connected 20M!!! primary_cca=%d\n", primary_cca->pri_cca_flag));
} else /* 3 */ { /* client BW = 40MHz */
if (primary_cca->intf_flag == 1) { /* interference is detected!! */
if (primary_cca->intf_type == 1) {
if (primary_cca->pri_cca_flag != 1) {
primary_cca->pri_cca_flag = 1;
if (sec_ch_offset == 1)
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT(7), 2);
else if (sec_ch_offset == 2)
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT(7), 1);
}
} else if (primary_cca->intf_type == 2) {
if (primary_cca->dup_rts_flag != 1)
primary_cca->dup_rts_flag = 1;
}
} else { /* if intf_flag==0 */
if ((cur_tx_ok_cnt + cur_rx_ok_cnt) < 10000) { /* idle mode or TP traffic is very low */
if (sec_ch_offset == 1) {
if ((false_alm_cnt->cnt_ofdm_cca > 800) && (false_alm_cnt->cnt_bw_lsc * 5 > false_alm_cnt->cnt_bw_usc * 9)) {
primary_cca->intf_flag = 1;
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
primary_cca->intf_type = 1; /* interference is shift */
else
primary_cca->intf_type = 2; /* interference is in-band */
}
} else if (sec_ch_offset == 2) {
if ((false_alm_cnt->cnt_ofdm_cca > 800) && (false_alm_cnt->cnt_bw_usc * 5 > false_alm_cnt->cnt_bw_lsc * 9)) {
primary_cca->intf_flag = 1;
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
primary_cca->intf_type = 1; /* interference is shift */
else
primary_cca->intf_type = 2; /* interference is in-band */
}
}
} else { /* TP Traffic is High */
if (sec_ch_offset == 1) {
if (false_alm_cnt->cnt_bw_lsc > (false_alm_cnt->cnt_bw_usc + 500)) {
if (delay == 0) { /* add delay to avoid interference occurring abruptly, jump one time */
primary_cca->intf_flag = 1;
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
primary_cca->intf_type = 1; /* interference is shift */
else
primary_cca->intf_type = 2; /* interference is in-band */
delay = 1;
} else
delay = 0;
}
} else if (sec_ch_offset == 2) {
if (false_alm_cnt->cnt_bw_usc > (false_alm_cnt->cnt_bw_lsc + 500)) {
if (delay == 0) { /* add delay to avoid interference occurring abruptly */
primary_cca->intf_flag = 1;
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
primary_cca->intf_type = 1; /* interference is shift */
else
primary_cca->intf_type = 2; /* interference is in-band */
delay = 1;
} else
delay = 0;
}
}
}
}
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Primary CCA=%d\n", primary_cca->pri_cca_flag));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Duplicate RTS=%d\n", primary_cca->dup_rts_flag));
}
} /* end of connected */
}
}
/* 1 Dynamic Primary CCA Monitor counter */
if ((primary_cca->pri_cca_flag == 1) || (primary_cca->dup_rts_flag == 1)) {
if (client_40mhz == 0) { /* client=20M no need to monitor primary cca flag */
client_40mhz_pre = client_40mhz;
return;
}
counter++;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("counter=%d\n", counter));
if ((counter == 30) || ((client_40mhz - client_40mhz_pre) == 1)) { /* Every 60 sec to monitor one time */
primary_cca->monitor_flag = 1; /* monitor flag is triggered!!!!! */
if (primary_cca->pri_cca_flag == 1) {
primary_cca->pri_cca_flag = 0;
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT(7), 0);
}
counter = 0;
}
}
}
client_40mhz_pre = client_40mhz;
#endif
}
#endif /* #if (RTL8188E_SUPPORT == 1) */

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_RTL8188E_H__
#define __ODM_RTL8188E_H__
#if (RTL8188E_SUPPORT == 1)
#define MAIN_ANT_CG_TRX 1
#define AUX_ANT_CG_TRX 0
#define MAIN_ANT_CGCS_RX 0
#define AUX_ANT_CGCS_RX 1
void
odm_dig_lower_bound_88e(
struct PHY_DM_STRUCT *p_dm_odm
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#define sw_ant_div_reset_before_link odm_sw_ant_div_reset_before_link
void odm_sw_ant_div_reset_before_link(struct PHY_DM_STRUCT *p_dm_odm);
void
odm_set_tx_ant_by_tx_info_88e(
struct PHY_DM_STRUCT *p_dm_odm,
u8 *p_desc,
u8 mac_id
);
#else/* (DM_ODM_SUPPORT_TYPE == ODM_AP) */
void
odm_set_tx_ant_by_tx_info_88e(
struct PHY_DM_STRUCT *p_dm_odm
);
#endif
void
odm_primary_cca_init(
struct PHY_DM_STRUCT *p_dm_odm);
bool
odm_dynamic_primary_cca_dup_rts(
struct PHY_DM_STRUCT *p_dm_odm);
void
odm_dynamic_primary_cca(
struct PHY_DM_STRUCT *p_dm_odm);
#else /* (RTL8188E_SUPPORT == 0)*/
#define odm_primary_cca_init(_pdm_odm)
#define odm_dynamic_primary_cca(_pdm_odm)
#endif /* RTL8188E_SUPPORT */
#endif

10
hal/phydm/rtl8188e/version_rtl8188e.h Normal file
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/*RTL8188E PHY Parameters*/
/*
[Caution]
Since 01/Aug/2015, the commit rules will be simplified.
You do not need to fill up the version.h anymore,
only the maintenance supervisor fills it before formal release.
*/
#define RELEASE_DATE_8188E 20160517
#define COMMIT_BY_8188E "RF_Eason"
#define RELEASE_VERSION_8188E 70