diff --git a/include/Hal8188EPhyReg.h b/include/Hal8188EPhyReg.h index 8aa837e..0e06d29 100644 --- a/include/Hal8188EPhyReg.h +++ b/include/Hal8188EPhyReg.h @@ -148,7 +148,7 @@ #define rCCK0_RxHP 0xa14 /* Timing recovery & Channel estimation threshold */ -#define rCCK0_DSPParameter1 0xa18i +#define rCCK0_DSPParameter1 0xa18 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ #define rCCK0_TxFilter1 0xa20 @@ -192,7 +192,7 @@ #define rOFDM0_XDRxAFE 0xc28 #define rOFDM0_XDRxIQImbalance 0xc2c -#define rOFDM0_RxDetector1 0xc30 /* PD,BW & SBD DM tune init gain */ +#define rOFDM0_RxDetector1 0xc30 /*PD,BW & SBD DM tune init gain*/ #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ diff --git a/include/Hal8188ERateAdaptive.h b/include/Hal8188ERateAdaptive.h index 87aad81..21996a1 100644 --- a/include/Hal8188ERateAdaptive.h +++ b/include/Hal8188ERateAdaptive.h @@ -25,26 +25,26 @@ Major Change History: /* TX report 2 format in Rx desc */ /* */ #define GET_TX_RPT2_DESC_PKT_LEN_88E(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 9) + LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 9) #define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE( __pRxStatusDesc+16, 0, 32) + LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 0, 32) #define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__pRxStatusDesc) \ - LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32) + LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32) #define GET_TX_REPORT_TYPE1_RERTY_0(__pAddr) \ - LE_BITS_TO_4BYTE( __pAddr, 0, 16) + LE_BITS_TO_4BYTE(__pAddr, 0, 16) #define GET_TX_REPORT_TYPE1_RERTY_1(__pAddr) \ - LE_BITS_TO_1BYTE( __pAddr+2, 0, 8) + LE_BITS_TO_1BYTE(__pAddr+2, 0, 8) #define GET_TX_REPORT_TYPE1_RERTY_2(__pAddr) \ - LE_BITS_TO_1BYTE( __pAddr+3, 0, 8) + LE_BITS_TO_1BYTE(__pAddr+3, 0, 8) #define GET_TX_REPORT_TYPE1_RERTY_3(__pAddr) \ - LE_BITS_TO_1BYTE( __pAddr+4, 0, 8) + LE_BITS_TO_1BYTE(__pAddr+4, 0, 8) #define GET_TX_REPORT_TYPE1_RERTY_4(__pAddr) \ - LE_BITS_TO_1BYTE( __pAddr+4+1, 0, 8) + LE_BITS_TO_1BYTE(__pAddr+4+1, 0, 8) #define GET_TX_REPORT_TYPE1_DROP_0(__pAddr) \ - LE_BITS_TO_1BYTE( __pAddr+4+2, 0, 8) + LE_BITS_TO_1BYTE(__pAddr+4+2, 0, 8) #define GET_TX_REPORT_TYPE1_DROP_1(__pAddr) \ - LE_BITS_TO_1BYTE( __pAddr+4+3, 0, 8) + LE_BITS_TO_1BYTE(__pAddr+4+3, 0, 8) /* End rate adaptive define */ diff --git a/include/HalPhyRf_8188e.h b/include/HalPhyRf_8188e.h index 4cf5d76..fa583f2 100644 --- a/include/HalPhyRf_8188e.h +++ b/include/HalPhyRf_8188e.h @@ -47,7 +47,7 @@ void PHY_LCCalibrate_8188E(struct adapter *pAdapter); /* AP calibrate */ void PHY_APCalibrate_8188E(struct adapter *pAdapter, s8 delta); -void PHY_DigitalPredistortion_8188E(struct adapter *pAdapter); +void PHY_DigitalPredistortion_8188E(struct adapter *pAdapter); void _PHY_SaveADDARegisters(struct adapter *pAdapter, u32 *ADDAReg, u32 *ADDABackup, u32 RegisterNum); @@ -56,7 +56,7 @@ void _PHY_PathADDAOn(struct adapter *pAdapter, u32 *ADDAReg, bool isPathAOn, bool is2T); void _PHY_MACSettingCalibration(struct adapter *pAdapter, u32 *MACReg, - u32 *MACBackup); + u32 *MACBackup); void _PHY_PathAStandBy(struct adapter *pAdapter); diff --git a/include/HalVerDef.h b/include/HalVerDef.h index 727636a..97047cf 100644 --- a/include/HalVerDef.h +++ b/include/HalVerDef.h @@ -138,20 +138,20 @@ struct HAL_VERSION { ((IS_81XXC(version) && IS_2T2R(version)) ? true : false) #define IS_81xxC_VENDOR_UMC_A_CUT(version) \ (IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? \ - (IS_A_CUT(version) ? true : false) : false): false) + (IS_A_CUT(version) ? true : false) : false) : false) #define IS_81xxC_VENDOR_UMC_B_CUT(version) \ (IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? \ - (IS_B_CUT(version) ? true : false) : false): false) + (IS_B_CUT(version) ? true : false) : false) : false) #define IS_81xxC_VENDOR_UMC_C_CUT(version) \ (IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? \ - (IS_C_CUT(version) ? true : false) : false): false) + (IS_C_CUT(version) ? true : false) : false) : false) #define IS_NORMAL_CHIP92D(version) \ - (( IS_92D(version)) ? \ - ((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP)? true : false) : false) + ((IS_92D(version)) ? \ + ((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? true : false) : false) #define IS_92D_SINGLEPHY(version) \ - ((IS_92D(version)) ? (IS_2T2R(version) ? true: false) : false) + ((IS_92D(version)) ? (IS_2T2R(version) ? true : false) : false) #define IS_92D_C_CUT(version) \ ((IS_92D(version)) ? (IS_C_CUT(version) ? true : false) : false) #define IS_92D_D_CUT(version) \ @@ -160,8 +160,8 @@ struct HAL_VERSION { ((IS_92D(version)) ? (IS_E_CUT(version) ? true : false) : false) #define IS_8723A_A_CUT(version) \ - ((IS_8723_SERIES(version)) ? ( IS_A_CUT(version)?true : false) : false) + ((IS_8723_SERIES(version)) ? (IS_A_CUT(version) ? true : false) : false) #define IS_8723A_B_CUT(version) \ - ((IS_8723_SERIES(version)) ? ( IS_B_CUT(version)?true : false) : false) + ((IS_8723_SERIES(version)) ? (IS_B_CUT(version) ? true : false) : false) #endif diff --git a/include/basic_types.h b/include/basic_types.h index 49bd5ff..8a7ca99 100644 --- a/include/basic_types.h +++ b/include/basic_types.h @@ -157,31 +157,25 @@ value to host byte ordering.*/ * Set subfield of little-endian 4-byte value to specified value. */ #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \ - do { \ *((u32 *)(__pstart)) = \ ( \ LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \ ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \ - ); \ - } while (0) - + ) + #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \ - do { \ *((u16 *)(__pstart)) = \ ( \ LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \ ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \ - ); \ - } while (0) + ); #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \ - do { \ *((u8 *)(__pstart)) = EF1BYTE \ - ( \ + ( \ LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \ ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \ - ); \ - } while (0) + ) /* Get the N-bytes aligment offset from the current length */ #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \ diff --git a/include/circ_buf.h b/include/circ_buf.h index 01c3b11..b7f96be 100644 --- a/include/circ_buf.h +++ b/include/circ_buf.h @@ -20,8 +20,5 @@ #ifndef __CIRC_BUF_H_ #define __CIRC_BUF_H_ 1 -//#define CIRC_CNT(head, tail, size) (((head) - (tail)) & ((size)-1)) - -//#define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), ((head)+1), (size)) #endif /* _CIRC_BUF_H_ */ diff --git a/include/hal_intf.h b/include/hal_intf.h index ba9dc86..f569931 100644 --- a/include/hal_intf.h +++ b/include/hal_intf.h @@ -245,7 +245,7 @@ struct hal_ops { void (*ReadEFuse)(struct adapter *padapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, bool bPseudoTest); void (*EFUSEGetEfuseDefinition)(struct adapter *padapter, u8 efuseType, - u8 type, void *pOut, bool bPseudoTest); + u8 type, void *pOut, bool bPseudoTest); u16 (*EfuseGetCurrentSize)(struct adapter *padapter, u8 efuseType, bool bPseudoTest); int (*Efuse_PgPacketRead)(struct adapter *adapter, u8 offset, @@ -269,8 +269,8 @@ struct hal_ops { struct xmit_frame *frame, u32 max_wait, u32 bndy_cnt); - void (*hal_notch_filter)(struct adapter * adapter, bool enable); - void (*hal_reset_security_engine)(struct adapter * adapter); + void (*hal_notch_filter)(struct adapter *adapter, bool enable); + void (*hal_reset_security_engine)(struct adapter *adapter); s32 (*c2h_handler)(struct adapter *padapter, struct c2h_evt_hdr *c2h_evt); c2h_id_filter c2h_id_filter_ccx; @@ -313,38 +313,38 @@ enum hardware_type { /* RTL8192C Series */ #define IS_HARDWARE_TYPE_8192CE(_Adapter) \ -(((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192CE) +(((struct adapter *)_Adapter)->HardwareType == HARDWARE_TYPE_RTL8192CE) #define IS_HARDWARE_TYPE_8192CU(_Adapter) \ -(((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192CU) +(((struct adapter *)_Adapter)->HardwareType == HARDWARE_TYPE_RTL8192CU) #define IS_HARDWARE_TYPE_8192C(_Adapter) \ (IS_HARDWARE_TYPE_8192CE(_Adapter) || IS_HARDWARE_TYPE_8192CU(_Adapter)) /* RTL8192D Series */ #define IS_HARDWARE_TYPE_8192DE(_Adapter) \ - (((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192DE) + (((struct adapter *)_Adapter)->HardwareType == HARDWARE_TYPE_RTL8192DE) #define IS_HARDWARE_TYPE_8192DU(_Adapter) \ - (((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192DU) + (((struct adapter *)_Adapter)->HardwareType == HARDWARE_TYPE_RTL8192DU) #define IS_HARDWARE_TYPE_8192D(_Adapter) \ (IS_HARDWARE_TYPE_8192DE(_Adapter) || IS_HARDWARE_TYPE_8192DU(_Adapter)) /* RTL8723A Series */ #define IS_HARDWARE_TYPE_8723AE(_Adapter) \ -(((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AE) +(((struct adapter *)_Adapter)->HardwareType == HARDWARE_TYPE_RTL8723AE) #define IS_HARDWARE_TYPE_8723AU(_Adapter) \ -(((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AU) +(((struct adapter *)_Adapter)->HardwareType == HARDWARE_TYPE_RTL8723AU) #define IS_HARDWARE_TYPE_8723AS(_Adapter) \ -(((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AS) +(((struct adapter *)_Adapter)->HardwareType == HARDWARE_TYPE_RTL8723AS) #define IS_HARDWARE_TYPE_8723A(_Adapter) \ (IS_HARDWARE_TYPE_8723AE(_Adapter) || IS_HARDWARE_TYPE_8723AU(_Adapter) || \ IS_HARDWARE_TYPE_8723AS(_Adapter)) /* RTL8188E Series */ #define IS_HARDWARE_TYPE_8188EE(_Adapter) \ -(((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188EE) +(((struct adapter *)_Adapter)->HardwareType == HARDWARE_TYPE_RTL8188EE) #define IS_HARDWARE_TYPE_8188EU(_Adapter) \ -(((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188EU) +(((struct adapter *)_Adapter)->HardwareType == HARDWARE_TYPE_RTL8188EU) #define IS_HARDWARE_TYPE_8188ES(_Adapter) \ -(((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188ES) +(((struct adapter *)_Adapter)->HardwareType == HARDWARE_TYPE_RTL8188ES) #define IS_HARDWARE_TYPE_8188E(_Adapter) \ (IS_HARDWARE_TYPE_8188EE(_Adapter) || IS_HARDWARE_TYPE_8188EU(_Adapter) || \ IS_HARDWARE_TYPE_8188ES(_Adapter)) @@ -368,7 +368,7 @@ enum wowlan_subcode { WOWLAN_DEBUG_2 = 11 }; -struct wowlan_ioctl_param{ +struct wowlan_ioctl_param { unsigned int subcode; unsigned int subcode_value; unsigned int wakeup_reason; @@ -399,8 +399,8 @@ u32 rtw_hal_power_on(struct adapter *padapter); uint rtw_hal_init(struct adapter *padapter); uint rtw_hal_deinit(struct adapter *padapter); void rtw_hal_stop(struct adapter *padapter); -void rtw_hal_set_hwreg(struct adapter * padapter, u8 variable, u8 *val); -void rtw_hal_get_hwreg(struct adapter * padapter, u8 variable, u8 *val); +void rtw_hal_set_hwreg(struct adapter *padapter, u8 variable, u8 *val); +void rtw_hal_get_hwreg(struct adapter *padapter, u8 variable, u8 *val); void rtw_hal_chip_configure(struct adapter *padapter); void rtw_hal_read_chip_info(struct adapter *padapter); @@ -471,17 +471,17 @@ void rtw_hal_sreset_init(struct adapter *padapter); void rtw_hal_sreset_reset(struct adapter *padapter); void rtw_hal_sreset_reset_value(struct adapter *padapter); void rtw_hal_sreset_xmit_status_check(struct adapter *padapter); -void rtw_hal_sreset_linked_status_check (struct adapter *padapter); +void rtw_hal_sreset_linked_status_check(struct adapter *padapter); u8 rtw_hal_sreset_get_wifi_status(struct adapter *padapter); int rtw_hal_iol_cmd(struct adapter *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt); -void rtw_hal_notch_filter(struct adapter * adapter, bool enable); -void rtw_hal_reset_security_engine(struct adapter * adapter); +void rtw_hal_notch_filter(struct adapter *adapter, bool enable); +void rtw_hal_reset_security_engine(struct adapter *adapter); s32 rtw_hal_c2h_handler(struct adapter *adapter, - struct c2h_evt_hdr *c2h_evt); + struct c2h_evt_hdr *c2h_evt); c2h_id_filter rtw_hal_c2h_id_filter_ccx(struct adapter *adapter); #endif /* __HAL_INTF_H__ */ diff --git a/include/ieee80211.h b/include/ieee80211.h index 12184b3..a1c66b8 100644 --- a/include/ieee80211.h +++ b/include/ieee80211.h @@ -162,21 +162,27 @@ enum ratr_table_mode { enum NETWORK_TYPE { WIRELESS_INVALID = 0, /* Sub-Element */ - WIRELESS_11B = BIT(0), /* tx: cck only, rx: cck only, hw: cck */ - WIRELESS_11G = BIT(1), /* tx: ofdm only, rx: ofdm & cck, hw: cck & ofdm */ - WIRELESS_11A = BIT(2), /* tx: ofdm only, rx: ofdm only, hw: ofdm only */ - WIRELESS_11_24N = BIT(3), /* tx: MCS only, rx: MCS & cck, hw: MCS & cck */ - WIRELESS_11_5N = BIT(4), /* tx: MCS only, rx: MCS & ofdm, hw: ofdm only */ - /* WIRELESS_AUTO = BIT(5), */ + WIRELESS_11B = BIT(0), /* tx:cck only, rx:cck only, hw: cck */ + WIRELESS_11G = BIT(1), /* tx:ofdm only, rx:ofdm & cck, hw:cck & ofdm*/ + WIRELESS_11A = BIT(2), /* tx:ofdm only, rx: ofdm only, hw:ofdm only */ + WIRELESS_11_24N = BIT(3), /* tx:MCS only, rx:MCS & cck, hw:MCS & cck */ + WIRELESS_11_5N = BIT(4), /* tx:MCS only, rx:MCS & ofdm, hw:ofdm only */ WIRELESS_AC = BIT(6), /* Combination */ - WIRELESS_11BG = (WIRELESS_11B|WIRELESS_11G), /* tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm */ - WIRELESS_11G_24N = (WIRELESS_11G|WIRELESS_11_24N), /* tx: ofdm & MCS, rx: ofdm & cck & MCS, hw: cck & ofdm */ - WIRELESS_11A_5N = (WIRELESS_11A|WIRELESS_11_5N), /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */ - WIRELESS_11BG_24N = (WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N), /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */ - WIRELESS_11AGN = (WIRELESS_11A|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N), /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */ - WIRELESS_11ABGN = (WIRELESS_11A|WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N), + /* tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm */ + WIRELESS_11BG = (WIRELESS_11B | WIRELESS_11G), + /* tx: ofdm & MCS, rx: ofdm & cck & MCS, hw: cck & ofdm */ + WIRELESS_11G_24N = (WIRELESS_11G | WIRELESS_11_24N), + /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */ + WIRELESS_11A_5N = (WIRELESS_11A | WIRELESS_11_5N), + /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */ + WIRELESS_11BG_24N = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N), + /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */ + WIRELESS_11AGN = (WIRELESS_11A | WIRELESS_11G | WIRELESS_11_24N | + WIRELESS_11_5N), + WIRELESS_11ABGN = (WIRELESS_11A | WIRELESS_11B | WIRELESS_11G | + WIRELESS_11_24N | WIRELESS_11_5N), }; #define SUPPORTED_24G_NETTYPE_MSK \ @@ -257,7 +263,7 @@ struct ieee_param_ex { u8 data[0]; }; -struct sta_data{ +struct sta_data { u16 aid; u16 capability; int flags; @@ -373,21 +379,21 @@ enum eap_type { /* Frame control field constants */ #define RTW_IEEE80211_FCTL_VERS 0x0003 -#define RTW_IEEE80211_FCTL_FTYPE 0x000c -#define RTW_IEEE80211_FCTL_STYPE 0x00f0 +#define RTW_IEEE80211_FCTL_FTYPE 0x000c +#define RTW_IEEE80211_FCTL_STYPE 0x00f0 #define RTW_IEEE80211_FCTL_TODS 0x0100 #define RTW_IEEE80211_FCTL_FROMDS 0x0200 #define RTW_IEEE80211_FCTL_MOREFRAGS 0x0400 -#define RTW_IEEE80211_FCTL_RETRY 0x0800 +#define RTW_IEEE80211_FCTL_RETRY 0x0800 #define RTW_IEEE80211_FCTL_PM 0x1000 #define RTW_IEEE80211_FCTL_MOREDATA 0x2000 #define RTW_IEEE80211_FCTL_PROTECTED 0x4000 -#define RTW_IEEE80211_FCTL_ORDER 0x8000 +#define RTW_IEEE80211_FCTL_ORDER 0x8000 #define RTW_IEEE80211_FCTL_CTL_EXT 0x0f00 -#define RTW_IEEE80211_FTYPE_MGMT 0x0000 +#define RTW_IEEE80211_FTYPE_MGMT 0x0000 #define RTW_IEEE80211_FTYPE_CTL 0x0004 -#define RTW_IEEE80211_FTYPE_DATA 0x0008 +#define RTW_IEEE80211_FTYPE_DATA 0x0008 #define RTW_IEEE80211_FTYPE_EXT 0x000c /* management */ @@ -397,36 +403,36 @@ enum eap_type { #define RTW_IEEE80211_STYPE_REASSOC_RESP 0x0030 #define RTW_IEEE80211_STYPE_PROBE_REQ 0x0040 #define RTW_IEEE80211_STYPE_PROBE_RESP 0x0050 -#define RTW_IEEE80211_STYPE_BEACON 0x0080 -#define RTW_IEEE80211_STYPE_ATIM 0x0090 +#define RTW_IEEE80211_STYPE_BEACON 0x0080 +#define RTW_IEEE80211_STYPE_ATIM 0x0090 #define RTW_IEEE80211_STYPE_DISASSOC 0x00A0 -#define RTW_IEEE80211_STYPE_AUTH 0x00B0 -#define RTW_IEEE80211_STYPE_DEAUTH 0x00C0 -#define RTW_IEEE80211_STYPE_ACTION 0x00D0 +#define RTW_IEEE80211_STYPE_AUTH 0x00B0 +#define RTW_IEEE80211_STYPE_DEAUTH 0x00C0 +#define RTW_IEEE80211_STYPE_ACTION 0x00D0 /* control */ -#define RTW_IEEE80211_STYPE_CTL_EXT 0x0060 -#define RTW_IEEE80211_STYPE_BACK_REQ 0x0080 -#define RTW_IEEE80211_STYPE_BACK 0x0090 -#define RTW_IEEE80211_STYPE_PSPOLL 0x00A0 +#define RTW_IEEE80211_STYPE_CTL_EXT 0x0060 +#define RTW_IEEE80211_STYPE_BACK_REQ 0x0080 +#define RTW_IEEE80211_STYPE_BACK 0x0090 +#define RTW_IEEE80211_STYPE_PSPOLL 0x00A0 #define RTW_IEEE80211_STYPE_RTS 0x00B0 #define RTW_IEEE80211_STYPE_CTS 0x00C0 #define RTW_IEEE80211_STYPE_ACK 0x00D0 -#define RTW_IEEE80211_STYPE_CFEND 0x00E0 -#define RTW_IEEE80211_STYPE_CFENDACK 0x00F0 +#define RTW_IEEE80211_STYPE_CFEND 0x00E0 +#define RTW_IEEE80211_STYPE_CFENDACK 0x00F0 /* data */ -#define RTW_IEEE80211_STYPE_DATA 0x0000 +#define RTW_IEEE80211_STYPE_DATA 0x0000 #define RTW_IEEE80211_STYPE_DATA_CFACK 0x0010 #define RTW_IEEE80211_STYPE_DATA_CFPOLL 0x0020 #define RTW_IEEE80211_STYPE_DATA_CFACKPOLL 0x0030 #define RTW_IEEE80211_STYPE_NULLFUNC 0x0040 -#define RTW_IEEE80211_STYPE_CFACK 0x0050 -#define RTW_IEEE80211_STYPE_CFPOLL 0x0060 +#define RTW_IEEE80211_STYPE_CFACK 0x0050 +#define RTW_IEEE80211_STYPE_CFPOLL 0x0060 #define RTW_IEEE80211_STYPE_CFACKPOLL 0x0070 -#define RTW_IEEE80211_STYPE_QOS_DATA 0x0080 -#define RTW_IEEE80211_STYPE_QOS_DATA_CFACK 0x0090 -#define RTW_IEEE80211_STYPE_QOS_DATA_CFPOLL 0x00A0 +#define RTW_IEEE80211_STYPE_QOS_DATA 0x0080 +#define RTW_IEEE80211_STYPE_QOS_DATA_CFACK 0x0090 +#define RTW_IEEE80211_STYPE_QOS_DATA_CFPOLL 0x00A0 #define RTW_IEEE80211_STYPE_QOS_DATA_CFACKPOLL 0x00B0 #define RTW_IEEE80211_STYPE_QOS_NULLFUNC 0x00C0 #define RTW_IEEE80211_STYPE_QOS_CFACK 0x00D0 @@ -445,7 +451,7 @@ enum eap_type { /* QoS, QOS */ #define NORMAL_ACK 0 #define NO_ACK 1 -#define NON_EXPLICIT_ACK 2 +#define NON_EXPLICIT_ACK 2 #define BLOCK_ACK 3 #ifndef ETH_P_PAE @@ -618,22 +624,25 @@ struct ieee80211_snap_hdr { #define IEEE80211_CCK_RATES_MASK 0x0000000F #define IEEE80211_CCK_BASIC_RATES_MASK (IEEE80211_CCK_RATE_1MB_MASK | \ IEEE80211_CCK_RATE_2MB_MASK) -#define IEEE80211_CCK_DEFAULT_RATES_MASK (IEEE80211_CCK_BASIC_RATES_MASK | \ - IEEE80211_CCK_RATE_5MB_MASK | \ +#define IEEE80211_CCK_DEFAULT_RATES_MASK \ + (IEEE80211_CCK_BASIC_RATES_MASK | \ + IEEE80211_CCK_RATE_5MB_MASK | \ IEEE80211_CCK_RATE_11MB_MASK) #define IEEE80211_OFDM_RATES_MASK 0x00000FF0 #define IEEE80211_OFDM_BASIC_RATES_MASK (IEEE80211_OFDM_RATE_6MB_MASK | \ - IEEE80211_OFDM_RATE_12MB_MASK | \ + IEEE80211_OFDM_RATE_12MB_MASK | \ IEEE80211_OFDM_RATE_24MB_MASK) -#define IEEE80211_OFDM_DEFAULT_RATES_MASK (IEEE80211_OFDM_BASIC_RATES_MASK | \ - IEEE80211_OFDM_RATE_9MB_MASK | \ - IEEE80211_OFDM_RATE_18MB_MASK | \ - IEEE80211_OFDM_RATE_36MB_MASK | \ - IEEE80211_OFDM_RATE_48MB_MASK | \ +#define IEEE80211_OFDM_DEFAULT_RATES_MASK \ + (IEEE80211_OFDM_BASIC_RATES_MASK | \ + IEEE80211_OFDM_RATE_9MB_MASK | \ + IEEE80211_OFDM_RATE_18MB_MASK | \ + IEEE80211_OFDM_RATE_36MB_MASK | \ + IEEE80211_OFDM_RATE_48MB_MASK | \ IEEE80211_OFDM_RATE_54MB_MASK) -#define IEEE80211_DEFAULT_RATES_MASK (IEEE80211_OFDM_DEFAULT_RATES_MASK | \ - IEEE80211_CCK_DEFAULT_RATES_MASK) +#define IEEE80211_DEFAULT_RATES_MASK \ + (IEEE80211_OFDM_DEFAULT_RATES_MASK | \ + IEEE80211_CCK_DEFAULT_RATES_MASK) #define IEEE80211_NUM_OFDM_RATES 8 #define IEEE80211_NUM_CCK_RATES 4 @@ -952,7 +961,7 @@ static inline int is_multicast_mac_addr(const u8 *addr) static inline int is_broadcast_mac_addr(const u8 *addr) { - return (addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) && \ + return (addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) && (addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff); } @@ -1001,7 +1010,7 @@ enum rtw_ieee80211_spectrum_mgmt_actioncode { RTW_WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5, }; -enum _PUBLIC_ACTION{ +enum _PUBLIC_ACTION { ACT_PUBLIC_BSSCOEXIST = 0, /* 20/40 BSS Coexistence */ ACT_PUBLIC_DSE_ENABLE = 1, ACT_PUBLIC_DSE_DEENABLE = 2, @@ -1031,14 +1040,14 @@ enum rtw_ieee80211_back_actioncode { /* HT features action code */ enum rtw_ieee80211_ht_actioncode { RTW_WLAN_ACTION_NOTIFY_CH_WIDTH = 0, - RTW_WLAN_ACTION_SM_PS = 1, - RTW_WLAN_ACTION_PSPM = 2, - RTW_WLAN_ACTION_PCO_PHASE = 3, - RTW_WLAN_ACTION_MIMO_CSI_MX = 4, - RTW_WLAN_ACTION_MIMO_NONCP_BF = 5, - RTW_WLAN_ACTION_MIMP_CP_BF = 6, - RTW_WLAN_ACTION_ASEL_INDICATES_FB = 7, - RTW_WLAN_ACTION_HI_INFO_EXCHG = 8, + RTW_WLAN_ACTION_SM_PS = 1, + RTW_WLAN_ACTION_PSPM = 2, + RTW_WLAN_ACTION_PCO_PHASE = 3, + RTW_WLAN_ACTION_MIMO_CSI_MX = 4, + RTW_WLAN_ACTION_MIMO_NONCP_BF = 5, + RTW_WLAN_ACTION_MIMP_CP_BF = 6, + RTW_WLAN_ACTION_ASEL_INDICATES_FB = 7, + RTW_WLAN_ACTION_HI_INFO_EXCHG = 8, }; /* BACK (block-ack) parties */ @@ -1192,7 +1201,7 @@ u8 *rtw_set_ie_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl, u8 flags, u16 reason, u16 precedence); -u8 *rtw_get_ie(u8*pbuf, int index, int *len, int limit); +u8 *rtw_get_ie(u8 *pbuf, int index, int *len, int limit); u8 *rtw_get_ie_ex(u8 *in_ie, uint in_len, u8 eid, u8 *oui, u8 oui_len, u8 *ie, uint *ielen); int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, @@ -1205,9 +1214,9 @@ unsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit); int rtw_get_wpa_cipher_suite(u8 *s); int rtw_get_wpa2_cipher_suite(u8 *s); int rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len); -int rtw_parse_wpa_ie(u8* wpa_ie, int wpa_ie_len, int *group_cipher, +int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x); -int rtw_parse_wpa2_ie(u8* wpa_ie, int wpa_ie_len, int *group_cipher, +int rtw_parse_wpa2_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x); int rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, @@ -1227,8 +1236,8 @@ u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id, * @buf_len: */ #define for_each_ie(ie, buf, buf_len) \ - for (ie = (void*)buf; (((u8*)ie) - ((u8*)buf) + 1) < buf_len; \ - ie = (void*)(((u8*)ie) + *(((u8*)ie)+1) + 2)) + for (ie = (void *)buf; (((u8 *)ie) - ((u8 *)buf) + 1) < buf_len; \ + ie = (void *)(((u8 *)ie) + *(((u8 *)ie)+1) + 2)) void dump_ies(u8 *buf, u32 buf_len); void dump_wps_ie(u8 *ie, u32 ie_len); @@ -1267,7 +1276,7 @@ void rtw_macaddr_cfg(u8 *mac_addr); u16 rtw_mcs_rate(u8 rf_type, u8 bw_40MHz, u8 short_GI_20, u8 short_GI_40, unsigned char *MCS_rate); -int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8* category, +int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8 *category, u8 *action); const char *action_public_str(u8 action); diff --git a/include/ieee80211_ext.h b/include/ieee80211_ext.h index fb20dfd..1052d18 100644 --- a/include/ieee80211_ext.h +++ b/include/ieee80211_ext.h @@ -284,6 +284,7 @@ struct ieee80211_mgmt { } __packed; /* mgmt header + 1 byte category code */ -#define IEEE80211_MIN_ACTION_SIZE FIELD_OFFSET(struct ieee80211_mgmt, u.action.u) +#define IEEE80211_MIN_ACTION_SIZE \ + FIELD_OFFSET(struct ieee80211_mgmt, u.action.u) #endif diff --git a/include/if_ether.h b/include/if_ether.h index 50f6d89..db15771 100644 --- a/include/if_ether.h +++ b/include/if_ether.h @@ -44,7 +44,7 @@ #define ETH_P_ARP 0x0806 /* Address Resolution packet */ #define ETH_P_BPQ 0x08FF /* G8BPQ AX.25 Ethernet Packet */ #define ETH_P_IEEEPUP 0x0a00 /* Xerox IEEE802.3 PUP packet */ -#define ETH_P_IEEEPUPAT 0x0a01 /* Xerox IEEE802.3 PUP */ +#define ETH_P_IEEEPUPAT 0x0a01 /* Xerox IEEE802.3 PUP */ #define ETH_P_DEC 0x6000 /* DEC Assigned proto */ #define ETH_P_DNA_DL 0x6001 /* DEC DNA Dump/Load */ #define ETH_P_DNA_RC 0x6002 /* DEC DNA Remote Console */ @@ -90,8 +90,7 @@ * This is an Ethernet frame header. */ -struct ethhdr -{ +struct ethhdr { unsigned char h_dest[ETH_ALEN]; /* destination eth addr */ unsigned char h_source[ETH_ALEN]; /* source ether addr */ unsigned short h_proto; /* packet type ID field */ @@ -103,9 +102,9 @@ struct _vlan { }; #define get_vlan_id(pvlan) \ - ((ntohs((unsigned short )pvlan->h_vlan_TCI)) & 0xfff) + ((ntohs((unsigned short)pvlan->h_vlan_TCI)) & 0xfff) #define get_vlan_priority(pvlan) \ - ((ntohs((unsigned short )pvlan->h_vlan_TCI))>>13) + ((ntohs((unsigned short)pvlan->h_vlan_TCI))>>13) #define get_vlan_encap_proto(pvlan) \ (ntohs((unsigned short)pvlan->h_vlan_encapsulated_proto)) diff --git a/include/ioctl_cfg80211.h b/include/ioctl_cfg80211.h index f0b3446..25571dc 100644 --- a/include/ioctl_cfg80211.h +++ b/include/ioctl_cfg80211.h @@ -61,9 +61,6 @@ struct rtw_wdev_priv { #define wdev_to_priv(w) ((struct rtw_wdev_priv *)(wdev_priv(w))) -#define wiphy_tostruct adapter(x) \ -((struct adapter *)(((struct rtw_wdev_priv *)wiphy_priv(x))->padapter)) - #define wiphy_to_wdev(x) \ ((struct wireless_dev *)(((struct rtw_wdev_priv *)wiphy_priv(x))->rtw_wdev)) @@ -102,8 +99,8 @@ int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, bool rtw_cfg80211_pwr_mgmt(struct adapter *adapter); -#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) && \ - !defined(COMPAT_KERNEL_RELEASE) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) && \ + !defined(COMPAT_KERNEL_RELEASE) #define rtw_cfg80211_rx_mgmt(dev, freq, sig_dbm, buf, len, gfp) \ cfg80211_rx_mgmt(dev, freq, buf, len, gfp) #define rtw_cfg80211_send_rx_assoc(dev, bss, buf, len) \ diff --git a/include/ip.h b/include/ip.h index 40b706b..9fdac6d 100644 --- a/include/ip.h +++ b/include/ip.h @@ -107,7 +107,7 @@ struct iphdr { #if defined(__LITTLE_ENDIAN_BITFIELD) __u8 ihl:4, version:4; -#elif defined (__BIG_ENDIAN_BITFIELD) +#elif defined(__BIG_ENDIAN_BITFIELD) __u8 version:4, ihl:4; #endif diff --git a/include/mlme_osdep.h b/include/mlme_osdep.h index 2fac9fb..ae1722c 100644 --- a/include/mlme_osdep.h +++ b/include/mlme_osdep.h @@ -23,13 +23,13 @@ #include #include -extern void rtw_init_mlme_timer(struct adapter *padapter); -extern void rtw_os_indicate_disconnect( struct adapter *adapter ); -extern void rtw_os_indicate_connect( struct adapter *adapter ); -void rtw_os_indicate_scan_done( struct adapter *padapter, bool aborted); -extern void rtw_report_sec_ie(struct adapter *adapter,u8 authmode,u8 *sec_ie); +void rtw_init_mlme_timer(struct adapter *padapter); +void rtw_os_indicate_disconnect(struct adapter *adapter); +void rtw_os_indicate_connect(struct adapter *adapter); +void rtw_os_indicate_scan_done(struct adapter *padapter, bool aborted); +void rtw_report_sec_ie(struct adapter *adapter, u8 authmode, u8 *sec_ie); -void rtw_reset_securitypriv( struct adapter *adapter ); +void rtw_reset_securitypriv(struct adapter *adapter); void indicate_wx_scan_complete_event(struct adapter *padapter); #endif /* _MLME_OSDEP_H_ */ diff --git a/include/mp_custom_oid.h b/include/mp_custom_oid.h index 1867ea5..6fa52cf 100644 --- a/include/mp_custom_oid.h +++ b/include/mp_custom_oid.h @@ -31,9 +31,9 @@ /* For Production Kit with Agilent Equipments */ /* in order to make our custom oids hopefully somewhat unique */ /* we will use 0xFF (indicating implementation specific OID) */ -/* 81(first byte of non zero Realtek unique identifier) */ -/* 80 (second byte of non zero Realtek unique identifier) */ -/* XX (the custom OID number - providing 255 possible custom oids) */ +/* 81(first byte of non zero Realtek unique identifier) */ +/* 80 (second byte of non zero Realtek unique identifier) */ +/* XX (the custom OID number - providing 255 possible custom oids) */ #define OID_RT_PRO_RESET_DUT 0xFF818000 #define OID_RT_PRO_SET_DATA_RATE 0xFF818001 @@ -98,13 +98,14 @@ /* by Owen for RTL8185 Phy Status Report Utility */ -#define OID_RT_UTILITY_false_ALARM_COUNTERS 0xFF818580 -#define OID_RT_UTILITY_SELECT_DEBUG_MODE 0xFF818581 -#define OID_RT_UTILITY_SELECT_SUBCARRIER_NUMBER 0xFF818582 -#define OID_RT_UTILITY_GET_RSSI_STATUS 0xFF818583 -#define OID_RT_UTILITY_GET_FRAME_DETECTION_STATUS 0xFF818584 -#define OID_RT_UTILITY_GET_AGC_AND_FREQUENCY_OFFSET_ESTIMATION_STATUS 0xFF818585 -#define OID_RT_UTILITY_GET_CHANNEL_ESTIMATION_STATUS 0xFF818586 +#define OID_RT_UTILITY_false_ALARM_COUNTERS 0xFF818580 +#define OID_RT_UTILITY_SELECT_DEBUG_MODE 0xFF818581 +#define OID_RT_UTILITY_SELECT_SUBCARRIER_NUMBER 0xFF818582 +#define OID_RT_UTILITY_GET_RSSI_STATUS 0xFF818583 +#define OID_RT_UTILITY_GET_FRAME_DETECTION_STATUS 0xFF818584 +#define OID_RT_UTILITY_GET_AGC_AND_FREQUENCY_OFFSET_ESTIMATION_STATUS \ + 0xFF818585 +#define OID_RT_UTILITY_GET_CHANNEL_ESTIMATION_STATUS 0xFF818586 /* */ /* by Owen on 03/09/19-03/09/22 for RTL8185 */ @@ -199,13 +200,9 @@ /* Vincent 8185MP */ #define OID_RT_PRO_RX_FILTER 0xFF0111C0 -/* Andy TEST */ -/* define OID_RT_PRO_WRITE_REGISTRY 0xFF0111C1 */ -/* define OID_RT_PRO_READ_REGISTRY 0xFF0111C2 */ #define OID_CE_USB_WRITE_REGISTRY 0xFF0111C1 #define OID_CE_USB_READ_REGISTRY 0xFF0111C2 - #define OID_RT_PRO_SET_INITIAL_GA 0xFF0111C3 #define OID_RT_PRO_SET_BB_RF_STANDBY_MODE 0xFF0111C4 #define OID_RT_PRO_SET_BB_RF_SHUTDOWN_MODE 0xFF0111C5 @@ -220,8 +217,10 @@ #define OID_RT_AP_GET_CURRENT_TIME_STAMP 0xFF010301 #define OID_RT_AP_SWITCH_INTO_AP_MODE 0xFF010302 #define OID_RT_AP_SET_DTIM_PERIOD 0xFF010303 -#define OID_RT_AP_SUPPORTED 0xFF010304 /* Determine if driver supports AP mode. 2004.08.27, by rcnjko. */ -#define OID_RT_AP_SET_PASSPHRASE 0xFF010305 /* Set WPA-PSK passphrase into authenticator. 2005.07.08, byrcnjko. */ +/* Determine if driver supports AP mode. */ +#define OID_RT_AP_SUPPORTED 0xFF010304 +/* Set WPA-PSK passphrase into authenticator. */ +#define OID_RT_AP_SET_PASSPHRASE 0xFF010305 /* 8187MP. 2004.09.06, by rcnjko. */ #define OID_RT_PRO8187_WI_POLL 0xFF818780 diff --git a/include/odm.h b/include/odm.h index 2c495a9..2bfe728 100644 --- a/include/odm.h +++ b/include/odm.h @@ -22,46 +22,32 @@ #ifndef __HALDMOUTSRC_H__ #define __HALDMOUTSRC_H__ -/* */ /* Definition */ -/* */ -/* */ -/* 2011/09/22 MH Define all team supprt ability. */ -/* */ +/* Define all team support ability. */ + +/* Define for all teams. Please Define the constant in your precomp header. */ -/* */ -/* 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header. */ -/* */ /* define DM_ODM_SUPPORT_AP 0 */ /* define DM_ODM_SUPPORT_ADSL 0 */ /* define DM_ODM_SUPPORT_CE 0 */ /* define DM_ODM_SUPPORT_MP 1 */ -/* */ -/* 2011/09/28 MH Define ODM SW team support flag. */ -/* */ +/* Define ODM SW team support flag. */ - - -/* */ /* Antenna Switch Relative Definition. */ -/* */ -/* */ -/* 20100503 Joseph: */ /* Add new function SwAntDivCheck8192C(). */ /* This is the main function of Antenna diversity function before link. */ /* Mainly, it just retains last scan result and scan again. */ -/* After that, it compares the scan result to see which one gets better RSSI. */ -/* It selects antenna with better receiving power and returns better scan result. */ -/* */ -#define TP_MODE 0 +/* After that, it compares the scan result to see which one gets better + * RSSI. It selects antenna with better receiving power and returns better + * scan result. */ + +#define TP_MODE 0 #define RSSI_MODE 1 -#define TRAFFIC_LOW 0 -#define TRAFFIC_HIGH 1 +#define TRAFFIC_LOW 0 +#define TRAFFIC_HIGH 1 - -/* */ /* 3 Tx Power Tracking */ /* 3============================================================ */ #define DPK_DELTA_MAPPING_NUM 13 @@ -73,46 +59,41 @@ /* 3============================================================ */ #define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */ -#define MODE_40M 0 /* 0:20M, 1:40M */ +#define MODE_40M 0 /* 0:20M, 1:40M */ #define PSD_TH2 3 #define PSD_CHM 20 /* Minimum channel number for BT AFH */ #define SIR_STEP_SIZE 3 -#define Smooth_Size_1 5 +#define Smooth_Size_1 5 #define Smooth_TH_1 3 -#define Smooth_Size_2 10 +#define Smooth_Size_2 10 #define Smooth_TH_2 4 -#define Smooth_Size_3 20 +#define Smooth_Size_3 20 #define Smooth_TH_3 4 -#define Smooth_Step_Size 5 +#define Smooth_Step_Size 5 #define Adaptive_SIR 1 -#define PSD_RESCAN 4 +#define PSD_RESCAN 4 #define PSD_SCAN_INTERVAL 700 /* ms */ /* 8723A High Power IGI Setting */ -#define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 -#define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 -#define DM_DIG_HIGH_PWR_THRESHOLD 0x3a +#define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 +#define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 +#define DM_DIG_HIGH_PWR_THRESHOLD 0x3a /* LPS define */ -#define DM_DIG_FA_TH0_LPS 4 /* 4 in lps */ -#define DM_DIG_FA_TH1_LPS 15 /* 15 lps */ -#define DM_DIG_FA_TH2_LPS 30 /* 30 lps */ -#define RSSI_OFFSET_DIG 0x05; +#define DM_DIG_FA_TH0_LPS 4 /* 4 in lps */ +#define DM_DIG_FA_TH1_LPS 15 /* 15 lps */ +#define DM_DIG_FA_TH2_LPS 30 /* 30 lps */ +#define RSSI_OFFSET_DIG 0x05; /* ANT Test */ -#define ANTTESTALL 0x00 /* Ant A or B will be Testing */ -#define ANTTESTA 0x01 /* Ant A will be Testing */ -#define ANTTESTB 0x02 /* Ant B will be testing */ +#define ANTTESTALL 0x00 /* Ant A or B will be Testing */ +#define ANTTESTA 0x01 /* Ant A will be Testing */ +#define ANTTESTB 0x02 /* Ant B will be testing */ - -/* */ /* structure and define */ -/* */ -/* */ -/* 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement. */ +/* Add for AP/ADSLpseudo DM structuer requirement. */ /* We need to remove to other position??? */ -/* */ struct rtl8192cd_priv { u8 temp; }; @@ -213,62 +194,64 @@ struct rx_hpc { struct timer_list PSDTimer; }; -#define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ -#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM +#define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ +#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM + +/* This indicates two different steps. */ +/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to + * the signal on the air. */ +/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in + * SWAW_STEP_PEAK with original RSSI to determine if it is necessary to + * switch antenna. */ -/* This indicates two different the steps. */ -/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ -/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ -/* with original RSSI to determine if it is necessary to switch antenna. */ #define SWAW_STEP_PEAK 0 #define SWAW_STEP_DETERMINE 1 -#define TP_MODE 0 +#define TP_MODE 0 #define RSSI_MODE 1 -#define TRAFFIC_LOW 0 -#define TRAFFIC_HIGH 1 +#define TRAFFIC_LOW 0 +#define TRAFFIC_HIGH 1 struct sw_ant_switch { - u8 try_flag; - s32 PreRSSI; - u8 CurAntenna; - u8 PreAntenna; - u8 RSSI_Trying; - u8 TestMode; - u8 bTriggerAntennaSwitch; - u8 SelectAntennaMap; - u8 RSSI_target; + u8 try_flag; + s32 PreRSSI; + u8 CurAntenna; + u8 PreAntenna; + u8 RSSI_Trying; + u8 TestMode; + u8 bTriggerAntennaSwitch; + u8 SelectAntennaMap; + u8 RSSI_target; /* Before link Antenna Switch check */ - u8 SWAS_NoLink_State; - u32 SWAS_NoLink_BK_Reg860; - bool ANTA_ON; /* To indicate Ant A is or not */ - bool ANTB_ON; /* To indicate Ant B is on or not */ + u8 SWAS_NoLink_State; + u32 SWAS_NoLink_BK_Reg860; + bool ANTA_ON; /* To indicate Ant A is or not */ + bool ANTB_ON; /* To indicate Ant B is on or not */ - s32 RSSI_sum_A; - s32 RSSI_sum_B; - s32 RSSI_cnt_A; - s32 RSSI_cnt_B; - - u64 lastTxOkCnt; - u64 lastRxOkCnt; - u64 TXByteCnt_A; - u64 TXByteCnt_B; - u64 RXByteCnt_A; - u64 RXByteCnt_B; - u8 TrafficLoad; + s32 RSSI_sum_A; + s32 RSSI_sum_B; + s32 RSSI_cnt_A; + s32 RSSI_cnt_B; + u64 lastTxOkCnt; + u64 lastRxOkCnt; + u64 TXByteCnt_A; + u64 TXByteCnt_B; + u64 RXByteCnt_A; + u64 RXByteCnt_B; + u8 TrafficLoad; struct timer_list SwAntennaSwitchTimer; /* Hybrid Antenna Diversity */ - u32 CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM]; - u32 CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM]; - u32 OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM]; - u32 OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM]; - u32 RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM]; - u32 RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM]; - u8 TxAnt[ASSOCIATE_ENTRY_NUM]; - u8 TargetSTA; - u8 antsel; - u8 RxIdleAnt; + u32 CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM]; + u32 CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM]; + u32 OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM]; + u32 OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM]; + u32 RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM]; + u32 RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM]; + u8 TxAnt[ASSOCIATE_ENTRY_NUM]; + u8 TargetSTA; + u8 antsel; + u8 RxIdleAnt; }; struct edca_turbo { @@ -278,16 +261,15 @@ struct edca_turbo { }; struct odm_rate_adapt { - u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */ - u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ - u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ - u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ - u32 LastRATR; /* RATR Register Content */ - + u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */ + u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ + u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ + u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ + u32 LastRATR; /* RATR Register Content */ }; #define IQK_MAC_REG_NUM 4 -#define IQK_ADDA_REG_NUM 16 +#define IQK_ADDA_REG_NUM 16 #define IQK_BB_REG_NUM_MAX 10 #define IQK_BB_REG_NUM 9 #define HP_THERMAL_NUM 8 @@ -296,114 +278,98 @@ struct odm_rate_adapt { #define IQK_Matrix_REG_NUM 8 #define IQK_Matrix_Settings_NUM 1+24+21 -#define DM_Type_ByFW 0 -#define DM_Type_ByDriver 1 +#define DM_Type_ByFWi 0 +#define DM_Type_ByDriver 1 -/* */ /* Declare for common info */ -/* */ -/* Declare for common info */ -/* */ -#define MAX_PATH_NUM_92CS 2 + +#define MAX_PATH_NUM_92CS 2 struct odm_phy_status_info { - u8 RxPWDBAll; - u8 SignalQuality; /* in 0-100 index. */ - u8 RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; /* EVM */ - u8 RxMIMOSignalStrength[MAX_PATH_NUM_92CS];/* in 0~100 index */ - s8 RxPower; /* in dBm Translate from PWdB */ - s8 RecvSignalPower;/* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ - u8 BTRxRSSIPercentage; - u8 SignalStrength; /* in 0-100 index. */ - u8 RxPwr[MAX_PATH_NUM_92CS];/* per-path's pwdb */ - u8 RxSNR[MAX_PATH_NUM_92CS];/* per-path's SNR */ + u8 RxPWDBAll; + u8 SignalQuality; /* in 0-100 index. */ + u8 RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; /* EVM */ + u8 RxMIMOSignalStrength[MAX_PATH_NUM_92CS];/* in 0~100 index */ + s8 RxPower; /* in dBm Translate from PWdB */ + s8 RecvSignalPower;/* Real power in dBm for this packet, no + * beautification and aggregation. Keep this raw + * info to be used for the other procedures. */ + u8 BTRxRSSIPercentage; + u8 SignalStrength; /* in 0-100 index. */ + u8 RxPwr[MAX_PATH_NUM_92CS];/* per-path's pwdb */ + u8 RxSNR[MAX_PATH_NUM_92CS];/* per-path's SNR */ }; - struct odm_phy_dbg_info { /* ODM Write,debug info */ - s8 RxSNRdB[MAX_PATH_NUM_92CS]; - u64 NumQryPhyStatus; - u64 NumQryPhyStatusCCK; - u64 NumQryPhyStatusOFDM; + s8 RxSNRdB[MAX_PATH_NUM_92CS]; + u64 NumQryPhyStatus; + u64 NumQryPhyStatusCCK; + u64 NumQryPhyStatusOFDM; /* Others */ - s32 RxEVM[MAX_PATH_NUM_92CS]; - + s32 RxEVM[MAX_PATH_NUM_92CS]; }; struct odm_per_pkt_info { - s8 Rate; - u8 StationID; - bool bPacketMatchBSSID; - bool bPacketToSelf; - bool bPacketBeacon; + s8 Rate; + u8 StationID; + bool bPacketMatchBSSID; + bool bPacketToSelf; + bool bPacketBeacon; }; struct odm_mac_status_info { u8 test; - }; enum odm_ability { /* BB Team */ - ODM_DIG = 0x00000001, + ODM_DIG = 0x00000001, ODM_HIGH_POWER = 0x00000002, ODM_CCK_CCA_TH = 0x00000004, - ODM_FA_STATISTICS = 0x00000008, - ODM_RAMASK = 0x00000010, - ODM_RSSI_MONITOR = 0x00000020, + ODM_FA_STATISTICS = 0x00000008, + ODM_RAMASK = 0x00000010, + ODM_RSSI_MONITOR = 0x00000020, ODM_SW_ANTDIV = 0x00000040, ODM_HW_ANTDIV = 0x00000080, - ODM_BB_PWRSV = 0x00000100, - ODM_2TPATHDIV = 0x00000200, - ODM_1TPATHDIV = 0x00000400, - ODM_PSD2AFH = 0x00000800 + ODM_BB_PWRSV = 0x00000100, + ODM_2TPATHDIV = 0x00000200, + ODM_1TPATHDIV = 0x00000400, + ODM_PSD2AFH = 0x00000800 }; -/* */ /* 2011/20/20 MH For MP driver RT_WLAN_STA = struct sta_info */ /* Please declare below ODM relative info in your STA info structure. */ -/* */ + struct odm_sta_info { /* Driver Write */ - bool bUsed; /* record the sta status link or not? */ - u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */ + bool bUsed; /* record the sta status link or not? */ + u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */ /* ODM Write */ /* 1 PHY_STATUS_INFO */ - u8 RSSI_Path[4]; /* */ - u8 RSSI_Ave; - u8 RXEVM[4]; - u8 RXSNR[4]; - - /* */ - /* Please use compile flag to disable the struictrue for other IC except 88E. */ - /* Move To lower layer. */ - /* */ - /* ODM Write Wilson will handle this part(said by Luke.Lee) */ - + u8 RSSI_Path[4]; /* */ + u8 RSSI_Ave; + u8 RXEVM[4]; + u8 RXSNR[4]; }; -/* */ /* 2011/10/20 MH Define Common info enum for all team. */ -/* */ -enum odm_common_info_def { - /* */ +enum odm_common_info_def { /* Fixed value: */ - /* */ /* HOOK BEFORE REG INIT----------- */ ODM_CMNINFO_PLATFORM = 0, - ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */ - ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */ + ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */ + ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */ ODM_CMNINFO_MP_TEST_CHIP, - ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */ - ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */ - ODM_CMNINFO_FAB_VER, /* ODM_FAB_E */ - ODM_CMNINFO_RF_TYPE, /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */ - ODM_CMNINFO_BOARD_TYPE, /* ODM_BOARD_TYPE_E */ - ODM_CMNINFO_EXT_LNA, /* true */ + ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */ + ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */ + ODM_CMNINFO_FAB_VER, /* ODM_FAB_E */ + ODM_CMNINFO_RF_TYPE, /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */ + ODM_CMNINFO_BOARD_TYPE, /* ODM_BOARD_TYPE_E */ + ODM_CMNINFO_EXT_LNA, /* true */ ODM_CMNINFO_EXT_PA, ODM_CMNINFO_EXT_TRSW, ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */ @@ -412,9 +378,7 @@ enum odm_common_info_def { ODM_CMNINFO_SMART_CONCURRENT, /* HOOK BEFORE REG INIT----------- */ - /* */ /* Dynamic value: */ - /* */ /* POINTER REFERENCE----------- */ ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */ ODM_CMNINFO_TX_UNI, @@ -445,62 +409,51 @@ enum odm_common_info_def { ODM_CMNINFO_WIFI_DISPLAY, ODM_CMNINFO_LINK, ODM_CMNINFO_RSSI_MIN, - ODM_CMNINFO_DBG_COMP, /* u64 */ - ODM_CMNINFO_DBG_LEVEL, /* u32 */ + ODM_CMNINFO_DBG_COMP, /* u64 */ + ODM_CMNINFO_DBG_LEVEL, /* u32 */ ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */ ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */ ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ ODM_CMNINFO_BT_DISABLED, ODM_CMNINFO_BT_OPERATION, ODM_CMNINFO_BT_DIG, - ODM_CMNINFO_BT_BUSY, /* Check Bt is using or not */ + ODM_CMNINFO_BT_BUSY, /* Check Bt is using or not */ ODM_CMNINFO_BT_DISABLE_EDCA, /* CALL BY VALUE-------------*/ - /* */ /* Dynamic ptr array hook itms. */ - /* */ ODM_CMNINFO_STA_STATUS, ODM_CMNINFO_PHY_STATUS, ODM_CMNINFO_MAC_STATUS, - ODM_CMNINFO_MAX, }; -/* */ /* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */ -/* */ + enum odm_ability_def { - /* */ /* BB ODM section BIT 0-15 */ - /* */ - ODM_BB_DIG = BIT0, - ODM_BB_RA_MASK = BIT1, + ODM_BB_DIG = BIT0, + ODM_BB_RA_MASK = BIT1, ODM_BB_DYNAMIC_TXPWR = BIT2, - ODM_BB_FA_CNT = BIT3, - ODM_BB_RSSI_MONITOR = BIT4, - ODM_BB_CCK_PD = BIT5, - ODM_BB_ANT_DIV = BIT6, - ODM_BB_PWR_SAVE = BIT7, - ODM_BB_PWR_TRA = BIT8, - ODM_BB_RATE_ADAPTIVE = BIT9, - ODM_BB_PATH_DIV = BIT10, - ODM_BB_PSD = BIT11, - ODM_BB_RXHP = BIT12, + ODM_BB_FA_CNT = BIT3, + ODM_BB_RSSI_MONITOR = BIT4, + ODM_BB_CCK_PD = BIT5, + ODM_BB_ANT_DIV = BIT6, + ODM_BB_PWR_SAVE = BIT7, + ODM_BB_PWR_TRA = BIT8, + ODM_BB_RATE_ADAPTIVE = BIT9, + ODM_BB_PATH_DIV = BIT10, + ODM_BB_PSD = BIT11, + ODM_BB_RXHP = BIT12, - /* */ /* MAC DM section BIT 16-23 */ - /* */ - ODM_MAC_EDCA_TURBO = BIT16, - ODM_MAC_EARLY_MODE = BIT17, + ODM_MAC_EDCA_TURBO = BIT16, + ODM_MAC_EARLY_MODE = BIT17, - /* */ /* RF ODM section BIT 24-31 */ - /* */ - ODM_RF_TX_PWR_TRACK = BIT24, - ODM_RF_RX_GAIN_TRACK = BIT25, - ODM_RF_CALIBRATION = BIT26, - + ODM_RF_TX_PWR_TRACK = BIT24, + ODM_RF_RX_GAIN_TRACK = BIT25, + ODM_RF_CALIBRATION = BIT26, }; /* ODM_CMNINFO_INTERFACE */ @@ -522,17 +475,19 @@ enum odm_ic_type { ODM_RTL8821 = BIT6, }; -#define ODM_IC_11N_SERIES (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E) +#define ODM_IC_11N_SERIES \ + (ODM_RTL8192S | ODM_RTL8192C | ODM_RTL8192D | \ + ODM_RTL8723A | ODM_RTL8188E) #define ODM_IC_11AC_SERIES (ODM_RTL8812) /* ODM_CMNINFO_CUT_VER */ enum odm_cut_version { - ODM_CUT_A = 1, - ODM_CUT_B = 2, - ODM_CUT_C = 3, - ODM_CUT_D = 4, - ODM_CUT_E = 5, - ODM_CUT_F = 6, + ODM_CUT_A = 1, + ODM_CUT_B = 2, + ODM_CUT_C = 3, + ODM_CUT_D = 4, + ODM_CUT_E = 5, + ODM_CUT_F = 6, ODM_CUT_TEST = 7, }; @@ -543,9 +498,7 @@ enum odm_fab_Version { }; /* ODM_CMNINFO_RF_TYPE */ -/* */ /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */ -/* */ enum odm_rf_path { ODM_RF_TX_A = BIT0, ODM_RF_TX_B = BIT1, @@ -578,7 +531,7 @@ enum odm_mac_phy_mode { enum odm_bt_coexist { ODM_BT_BUSY = 1, - ODM_BT_ON = 2, + ODM_BT_ON = 2, ODM_BT_OFF = 3, ODM_BT_NONE = 4, }; @@ -586,13 +539,13 @@ enum odm_bt_coexist { /* ODM_CMNINFO_OP_MODE */ enum odm_operation_mode { ODM_NO_LINK = BIT0, - ODM_LINK = BIT1, - ODM_SCAN = BIT2, - ODM_POWERSAVE = BIT3, + ODM_LINK = BIT1, + ODM_SCAN = BIT2, + ODM_POWERSAVE = BIT3, ODM_AP_MODE = BIT4, - ODM_CLIENT_MODE = BIT5, + ODM_CLIENT_MODE = BIT5, ODM_AD_HOC = BIT6, - ODM_WIFI_DIRECT = BIT7, + ODM_WIFI_DIRECT = BIT7, ODM_WIFI_DISPLAY = BIT8, }; @@ -611,26 +564,26 @@ enum odm_wireless_mode { /* ODM_CMNINFO_BAND */ enum odm_band_type { ODM_BAND_2_4G = BIT0, - ODM_BAND_5G = BIT1, + ODM_BAND_5G = BIT1, }; /* ODM_CMNINFO_SEC_CHNL_OFFSET */ enum odm_sec_chnl_offset { ODM_DONT_CARE = 0, - ODM_BELOW = 1, - ODM_ABOVE = 2 + ODM_BELOW = 1, + ODM_ABOVE = 2 }; /* ODM_CMNINFO_SEC_MODE */ enum odm_security { - ODM_SEC_OPEN = 0, + ODM_SEC_OPEN = 0, ODM_SEC_WEP40 = 1, - ODM_SEC_TKIP = 2, - ODM_SEC_RESERVE = 3, - ODM_SEC_AESCCMP = 4, + ODM_SEC_TKIP = 2, + ODM_SEC_RESERVE = 3, + ODM_SEC_AESCCMP = 4, ODM_SEC_WEP104 = 5, - ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */ - ODM_SEC_SMS4 = 7, + ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */ + ODM_SEC_SMS4 = 7, }; /* ODM_CMNINFO_BW */ @@ -653,9 +606,9 @@ enum odm_board_type { /* ODM_CMNINFO_ONE_PATH_CCA */ enum odm_cca_path { - ODM_CCA_2R = 0, - ODM_CCA_1R_A = 1, - ODM_CCA_1R_B = 2, + ODM_CCA_2R = 0, + ODM_CCA_1R_A = 1, + ODM_CCA_1R_B = 2, }; struct odm_ra_info { @@ -679,43 +632,44 @@ struct odm_ra_info { u16 RptTime; u8 RAWaitingCounter; u8 RAPendingCounter; - u8 PTActive; /* on or off */ - u8 PTTryState; /* 0 trying state, 1 for decision state */ - u8 PTStage; /* 0~6 */ - u8 PTStopCount; /* Stop PT counter */ - u8 PTPreRate; /* if rate change do PT */ - u8 PTPreRssi; /* if RSSI change 5% do PT */ - u8 PTModeSS; /* decide whitch rate should do PT */ - u8 RAstage; /* StageRA, decide how many times RA will be done between PT */ + u8 PTActive; /* on or off */ + u8 PTTryState; /* 0 trying state, 1 for decision state */ + u8 PTStage; /* 0~6 */ + u8 PTStopCount; /* Stop PT counter */ + u8 PTPreRate; /* if rate change do PT */ + u8 PTPreRssi; /* if RSSI change 5% do PT */ + u8 PTModeSS; /* decide whitch rate should do PT */ + u8 RAstage; /* StageRA, decide how many times RA will be done + * between PT */ u8 PTSmoothFactor; }; struct ijk_matrix_regs_set { - bool bIQKDone; - s32 Value[1][IQK_Matrix_REG_NUM]; + bool bIQKDone; + s32 Value[1][IQK_Matrix_REG_NUM]; }; struct odm_rf_cal { /* for tx power tracking */ - u32 RegA24; /* for TempCCK */ s32 RegE94; s32 RegE9C; s32 RegEB4; s32 RegEBC; - /* u8 bTXPowerTracking; */ - u8 TXPowercount; - bool bTXPowerTrackingInit; - bool bTXPowerTracking; - u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ - u8 TM_Trigger; - u8 InternalPA5G[2]; /* pathA / pathB */ + u8 TXPowercount; + bool bTXPowerTrackingInit; + bool bTXPowerTracking; + u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking + * as default */ + u8 TM_Trigger; + u8 InternalPA5G[2]; /* pathA / pathB */ - u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ - u8 ThermalValue; - u8 ThermalValue_LCK; - u8 ThermalValue_IQK; + u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, + * and 1 for RFIC1 */ + u8 ThermalValue; + u8 ThermalValue_LCK; + u8 ThermalValue_IQK; u8 ThermalValue_DPK; u8 ThermalValue_AVG[AVG_THERMAL_NUM]; u8 ThermalValue_AVG_index; @@ -753,7 +707,7 @@ struct odm_rf_cal { u32 Reg864; bool bIQKInitialized; - bool bLCKInProgress; + bool bLCKInProgress; bool bAntennaDetected; u32 ADDA_backup[IQK_ADDA_REG_NUM]; u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; @@ -789,7 +743,7 @@ struct fast_ant_train { u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; u8 RxIdleAnt; - bool bBecomeLinked; + bool bBecomeLinked; }; enum fat_state { @@ -806,128 +760,130 @@ enum ant_div_type { CGCS_RX_SW_ANTDIV = 0x05, }; -/* 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */ +/* Copy from SD4 defined structure. We use to support PHY DM integration. */ struct odm_dm_struct { /* Add for different team use temporarily */ - struct adapter * Adapter; /* For CE/NIC team */ - struct rtl8192cd_priv *priv; /* For AP/ADSL team */ - /* WHen you use Adapter or priv pointer, you must make sure the pointer is ready. */ - bool odm_ready; + struct adapter *Adapter; /* For CE/NIC team */ + struct rtl8192cd_priv *priv; /* For AP/ADSL team */ + /* WHen you use above pointers, they must be initialized. */ + bool odm_ready; struct rtl8192cd_priv *fake_priv; - u64 DebugComponents; - u32 DebugLevel; + u64 DebugComponents; + u32 DebugLevel; /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ - bool bCckHighPower; - u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ - u8 ControlChannel; + bool bCckHighPower; + u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ + u8 ControlChannel; /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ /* 1 COMMON INFORMATION */ /* Init Value */ /* HOOK BEFORE REG INIT----------- */ /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */ - u8 SupportPlatform; + u8 SupportPlatform; /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K */ - u32 SupportAbility; + u32 SupportAbility; /* ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 */ - u8 SupportInterface; - /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */ - u32 SupportICType; + u8 SupportInterface; + /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any + * other type = 1/2/3/... */ + u32 SupportICType; /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */ - u8 CutVersion; + u8 CutVersion; /* Fab Version TSMC/UMC = 0/1 */ - u8 FabVersion; + u8 FabVersion; /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */ - u8 RFType; - /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */ - u8 BoardType; + u8 RFType; + /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/. = 0/1/2/3/4/. */ + u8 BoardType; /* with external LNA NO/Yes = 0/1 */ - u8 ExtLNA; + u8 ExtLNA; /* with external PA NO/Yes = 0/1 */ - u8 ExtPA; + u8 ExtPA; /* with external TRSW NO/Yes = 0/1 */ - u8 ExtTRSW; - u8 PatchID; /* Customer ID */ - bool bInHctTest; - bool bWIFITest; + u8 ExtTRSW; + u8 PatchID; /* Customer ID */ + bool bInHctTest; + bool bWIFITest; - bool bDualMacSmartConcurrent; - u32 BK_SupportAbility; - u8 AntDivType; + bool bDualMacSmartConcurrent; + u32 BK_SupportAbility; + u8 AntDivType; /* HOOK BEFORE REG INIT----------- */ - /* */ /* Dynamic Value */ - /* */ /* POINTER REFERENCE----------- */ - u8 u8_temp; - bool bool_temp; + u8 u8_temp; + bool bool_temp; struct adapter *adapter_temp; /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */ - u8 *pMacPhyMode; + u8 *pMacPhyMode; /* TX Unicast byte count */ - u64 *pNumTxBytesUnicast; + u64 *pNumTxBytesUnicast; /* RX Unicast byte count */ - u64 *pNumRxBytesUnicast; + u64 *pNumRxBytesUnicast; /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */ - u8 *pWirelessMode; /* ODM_WIRELESS_MODE_E */ + u8 *pWirelessMode; /* ODM_WIRELESS_MODE_E */ /* Frequence band 2.4G/5G = 0/1 */ - u8 *pBandType; + u8 *pBandType; /* Secondary channel offset don't_care/below/above = 0/1/2 */ - u8 *pSecChOffset; + u8 *pSecChOffset; /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */ - u8 *pSecurity; + u8 *pSecurity; /* BW info 20M/40M/80M = 0/1/2 */ - u8 *pBandWidth; + u8 *pBandWidth; /* Central channel location Ch1/Ch2/.... */ - u8 *pChannel; /* central channel number */ + u8 *pChannel; /* central channel number */ /* Common info for 92D DMSP */ - bool *pbGetValueFromOtherMac; + bool *pbGetValueFromOtherMac; struct adapter **pBuddyAdapter; - bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */ + bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */ /* Common info for Status */ - bool *pbScanInProcess; - bool *pbPowerSaving; + bool *pbScanInProcess; + bool *pbPowerSaving; /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */ - u8 *pOnePathCCA; + u8 *pOnePathCCA; /* pMgntInfo->AntennaTest */ - u8 *pAntennaTest; - bool *pbNet_closed; + u8 *pAntennaTest; + bool *pbNet_closed; /* POINTER REFERENCE----------- */ /* */ /* CALL BY VALUE------------- */ - bool bWIFI_Direct; - bool bWIFI_Display; - bool bLinked; - u8 RSSI_Min; - u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ - bool bIsMPChip; - bool bOneEntryOnly; + bool bWIFI_Direct; + bool bWIFI_Display; + bool bLinked; + u8 RSSI_Min; + u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ + bool bIsMPChip; + bool bOneEntryOnly; /* Common info for BTDM */ - bool bBtDisabled; /* BT is disabled */ - bool bBtHsOperation; /* BT HS mode is under progress */ - u8 btHsDigVal; /* use BT rssi to decide the DIG value */ - bool bBtDisableEdcaTurbo; /* Under some condition, don't enable the EDCA Turbo */ - bool bBtBusy; /* BT is busy. */ + bool bBtDisabled; /* BT is disabled */ + bool bBtHsOperation; /* BT HS mode is under progress */ + u8 btHsDigVal; /* use BT rssi to decide the DIG value */ + bool bBtDisableEdcaTurbo;/* Under some condition, don't enable the + * EDCA Turbo */ + bool bBtBusy; /* BT is busy. */ /* CALL BY VALUE------------- */ /* 2 Define STA info. */ /* _ODM_STA_INFO */ - /* 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */ + /* For MP, we need to reduce one array pointer for default port.?? */ struct sta_info *pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; - u16 CurrminRptTime; - struct odm_ra_info RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; /* Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} */ + u16 CurrminRptTime; + struct odm_ra_info RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; /* Use MacID as + * array index. STA MacID=0, + * VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} */ /* */ /* 2012/02/14 MH Add to share 88E ra with other SW team. */ /* We need to colelct all support abilit to a proper area. */ /* */ - bool RaSupport88E; + bool RaSupport88E; /* Define ........... */ @@ -957,40 +913,35 @@ struct odm_dm_struct { /* ================================================== */ /* */ - bool *pbDriverStopped; - bool *pbDriverIsGoingToPnpSetPowerSleep; - bool *pinit_adpt_in_progress; + bool *pbDriverStopped; + bool *pbDriverIsGoingToPnpSetPowerSleep; + bool *pinit_adpt_in_progress; /* PSD */ - bool bUserAssignLevel; + bool bUserAssignLevel; struct timer_list PSDTimer; - u8 RSSI_BT; /* come from BT */ - bool bPSDinProcess; - bool bDMInitialGainEnable; + u8 RSSI_BT; /* come from BT */ + bool bPSDinProcess; + bool bDMInitialGainEnable; /* for rate adaptive, in fact, 88c/92c fw will handle this */ - u8 bUseRAMask; + u8 bUseRAMask; struct odm_rate_adapt RateAdaptive; - struct odm_rf_cal RFCalibrateInfo; - /* */ /* TX power tracking */ - /* */ - u8 BbSwingIdxOfdm; - u8 BbSwingIdxOfdmCurrent; - u8 BbSwingIdxOfdmBase; - bool BbSwingFlagOfdm; - u8 BbSwingIdxCck; - u8 BbSwingIdxCckCurrent; - u8 BbSwingIdxCckBase; - bool BbSwingFlagCck; - u8 *mp_mode; - /* */ + u8 BbSwingIdxOfdm; + u8 BbSwingIdxOfdmCurrent; + u8 BbSwingIdxOfdmBase; + bool BbSwingFlagOfdm; + u8 BbSwingIdxCck; + u8 BbSwingIdxCckCurrent; + u8 BbSwingIdxCckBase; + bool BbSwingFlagCck; + u8 *mp_mode; /* ODM system resource. */ - /* */ /* ODM relative time. */ struct timer_list PathDivSwitchTimer; @@ -1002,10 +953,10 @@ struct odm_dm_struct { #define ODM_RF_PATH_MAX 2 enum ODM_RF_RADIO_PATH { - ODM_RF_PATH_A = 0, /* Radio Path A */ - ODM_RF_PATH_B = 1, /* Radio Path B */ - ODM_RF_PATH_C = 2, /* Radio Path C */ - ODM_RF_PATH_D = 3, /* Radio Path D */ + ODM_RF_PATH_A = 0, /* Radio Path A */ + ODM_RF_PATH_B = 1, /* Radio Path B */ + ODM_RF_PATH_C = 2, /* Radio Path C */ + ODM_RF_PATH_D = 3, /* Radio Path D */ }; enum ODM_RF_CONTENT { @@ -1050,53 +1001,53 @@ enum dm_dig_op { DIG_OP_TYPE_MAX }; -#define DM_DIG_THRESH_HIGH 40 -#define DM_DIG_THRESH_LOW 35 +#define DM_DIG_THRESH_HIGH 40 +#define DM_DIG_THRESH_LOW 35 -#define DM_SCAN_RSSI_TH 0x14 /* scan return issue for LC */ +#define DM_SCAN_RSSI_TH 0x14 /* scan return issue for LC */ #define DM_false_ALARM_THRESH_LOW 400 #define DM_false_ALARM_THRESH_HIGH 1000 -#define DM_DIG_MAX_NIC 0x3e -#define DM_DIG_MIN_NIC 0x1e /* 0x22/0x1c */ +#define DM_DIG_MAX_NIC 0x3e +#define DM_DIG_MIN_NIC 0x1e /* 0x22/0x1c */ -#define DM_DIG_MAX_AP 0x32 -#define DM_DIG_MIN_AP 0x20 +#define DM_DIG_MAX_AP 0x32 +#define DM_DIG_MIN_AP 0x20 -#define DM_DIG_MAX_NIC_HP 0x46 -#define DM_DIG_MIN_NIC_HP 0x2e +#define DM_DIG_MAX_NIC_HP 0x46 +#define DM_DIG_MIN_NIC_HP 0x2e -#define DM_DIG_MAX_AP_HP 0x42 -#define DM_DIG_MIN_AP_HP 0x30 +#define DM_DIG_MAX_AP_HP 0x42 +#define DM_DIG_MIN_AP_HP 0x30 /* vivi 92c&92d has different definition, 20110504 */ /* this is for 92c */ -#define DM_DIG_FA_TH0 0x200/* 0x20 */ -#define DM_DIG_FA_TH1 0x300/* 0x100 */ -#define DM_DIG_FA_TH2 0x400/* 0x200 */ +#define DM_DIG_FA_TH0 0x200/* 0x20 */ +#define DM_DIG_FA_TH1 0x300/* 0x100 */ +#define DM_DIG_FA_TH2 0x400/* 0x200 */ /* this is for 92d */ -#define DM_DIG_FA_TH0_92D 0x100 -#define DM_DIG_FA_TH1_92D 0x400 -#define DM_DIG_FA_TH2_92D 0x600 +#define DM_DIG_FA_TH0_92D 0x100 +#define DM_DIG_FA_TH1_92D 0x400 +#define DM_DIG_FA_TH2_92D 0x600 -#define DM_DIG_BACKOFF_MAX 12 -#define DM_DIG_BACKOFF_MIN -4 +#define DM_DIG_BACKOFF_MAX 12 +#define DM_DIG_BACKOFF_MIN -4 #define DM_DIG_BACKOFF_DEFAULT 10 /* 3=========================================================== */ /* 3 AGC RX High Power Mode */ /* 3=========================================================== */ -#define LNA_Low_Gain_1 0x64 -#define LNA_Low_Gain_2 0x5A -#define LNA_Low_Gain_3 0x58 +#define LNA_Low_Gain_1 0x64 +#define LNA_Low_Gain_2 0x5A +#define LNA_Low_Gain_3 0x58 -#define FA_RXHP_TH1 5000 -#define FA_RXHP_TH2 1500 -#define FA_RXHP_TH3 800 -#define FA_RXHP_TH4 600 -#define FA_RXHP_TH5 500 +#define FA_RXHP_TH1 5000 +#define FA_RXHP_TH2 1500 +#define FA_RXHP_TH3 800 +#define FA_RXHP_TH4 600 +#define FA_RXHP_TH5 500 /* 3=========================================================== */ /* 3 EDCA */ @@ -1113,21 +1064,21 @@ enum dm_dig_op { #define TxHighPwrLevel_Normal 0 #define TxHighPwrLevel_Level1 1 #define TxHighPwrLevel_Level2 2 -#define TxHighPwrLevel_BT1 3 -#define TxHighPwrLevel_BT2 4 -#define TxHighPwrLevel_15 5 -#define TxHighPwrLevel_35 6 -#define TxHighPwrLevel_50 7 -#define TxHighPwrLevel_70 8 -#define TxHighPwrLevel_100 9 +#define TxHighPwrLevel_BT1 3 +#define TxHighPwrLevel_BT2 4 +#define TxHighPwrLevel_15 5 +#define TxHighPwrLevel_35 6 +#define TxHighPwrLevel_50 7 +#define TxHighPwrLevel_70 8 +#define TxHighPwrLevel_100 9 /* 3=========================================================== */ /* 3 Rate Adaptive */ /* 3=========================================================== */ -#define DM_RATR_STA_INIT 0 -#define DM_RATR_STA_HIGH 1 -#define DM_RATR_STA_MIDDLE 2 -#define DM_RATR_STA_LOW 3 +#define DM_RATR_STA_INIT 0 +#define DM_RATR_STA_HIGH 1 +#define DM_RATR_STA_MIDDLE 2 +#define DM_RATR_STA_LOW 3 /* 3=========================================================== */ /* 3 BB Power Save */ @@ -1135,13 +1086,13 @@ enum dm_dig_op { enum dm_1r_cca { - CCA_1R =0, + CCA_1R = 0, CCA_2R = 1, CCA_MAX = 2, }; enum dm_rf { - RF_Save =0, + RF_Save = 0, RF_Normal = 1, RF_MAX = 2, }; @@ -1155,13 +1106,10 @@ enum dm_swas { Antenna_MAX = 3, }; - -/* Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */ +/* Maximal number of antenna detection mechanism needs to perform. */ #define MAX_ANTENNA_DETECTION_CNT 10 -/* */ /* Extern Global Variables. */ -/* */ #define OFDM_TABLE_SIZE_92C 37 #define OFDM_TABLE_SIZE_92D 43 #define CCK_TABLE_SIZE 33 @@ -1170,141 +1118,80 @@ extern u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D]; extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; extern u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; - - -/* */ /* check Sta pointer valid or not */ -/* */ #define IS_STA_VALID(pSta) (pSta) /* 20100514 Joseph: Add definition for antenna switching test after link. */ /* This indicates two different the steps. */ -/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ -/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ +/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the + * signal on the air. */ +/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in + * SWAW_STEP_PEAK */ /* with original RSSI to determine if it is necessary to switch antenna. */ #define SWAW_STEP_PEAK 0 #define SWAW_STEP_DETERMINE 1 -void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI); -void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres); +void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI); +void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres); -void -ODM_SetAntenna( - struct odm_dm_struct *pDM_Odm, - u8 Antenna); +void ODM_SetAntenna(struct odm_dm_struct *pDM_Odm, u8 Antenna); #define dm_RF_Saving ODM_RF_Saving -void ODM_RF_Saving( struct odm_dm_struct *pDM_Odm, - u8 bForceInNormal ); +void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal); #define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink -void ODM_SwAntDivRestAfterLink( struct odm_dm_struct *pDM_Odm); +void ODM_SwAntDivRestAfterLink(struct odm_dm_struct *pDM_Odm); -#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck -void -ODM_TXPowerTrackingCheck( - struct odm_dm_struct *pDM_Odm - ); +#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck +void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm); bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, bool bForceUpdate, u8 *pRATRState); #define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi -void ODM_SwAntDivChkPerPktRssi(struct odm_dm_struct *pDM_Odm, u8 StationID, struct odm_phy_status_info *pPhyInfo); +void ODM_SwAntDivChkPerPktRssi(struct odm_dm_struct *pDM_Odm, u8 StationID, + struct odm_phy_status_info *pPhyInfo); u32 ConvertTo_dB(u32 Value); -u32 -GetPSDData( - struct odm_dm_struct *pDM_Odm, - unsigned int point, - u8 initial_gain_psd); +u32 GetPSDData(struct odm_dm_struct *pDM_Odm, unsigned int point, + u8 initial_gain_psd); -void -odm_DIGbyRSSI_LPS( - struct odm_dm_struct *pDM_Odm - ); +void odm_DIGbyRSSI_LPS(struct odm_dm_struct *pDM_Odm); -u32 ODM_Get_Rate_Bitmap( - struct odm_dm_struct *pDM_Odm, - u32 macid, - u32 ra_mask, - u8 rssi_level); +u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, + u32 ra_mask, u8 rssi_level); -void ODM_DMInit( struct odm_dm_struct *pDM_Odm); +void ODM_DMInit(struct odm_dm_struct *pDM_Odm); -void -ODM_DMWatchdog( - struct odm_dm_struct *pDM_Odm /* For common use in the future */ - ); +void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm); -void -ODM_CmnInfoInit( - struct odm_dm_struct *pDM_Odm, - enum odm_common_info_def CmnInfo, - u32 Value - ); +void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm, + enum odm_common_info_def CmnInfo, u32 Value); -void -ODM_CmnInfoHook( - struct odm_dm_struct *pDM_Odm, - enum odm_common_info_def CmnInfo, - void * pValue - ); +void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm, + enum odm_common_info_def CmnInfo, void *pValue); -void -ODM_CmnInfoPtrArrayHook( - struct odm_dm_struct *pDM_Odm, - enum odm_common_info_def CmnInfo, - u16 Index, - void * pValue - ); +void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm, + enum odm_common_info_def CmnInfo, + u16 Index, void *pValue); -void -ODM_CmnInfoUpdate( - struct odm_dm_struct *pDM_Odm, - u32 CmnInfo, - u64 Value - ); +void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value); -void -ODM_InitAllTimers( - struct odm_dm_struct *pDM_Odm - ); +void ODM_InitAllTimers(struct odm_dm_struct *pDM_Odm); -void -ODM_CancelAllTimers( - struct odm_dm_struct *pDM_Odm - ); +void ODM_CancelAllTimers(struct odm_dm_struct *pDM_Odm); -void -ODM_ReleaseAllTimers( - struct odm_dm_struct *pDM_Odm - ); +void ODM_ReleaseAllTimers(struct odm_dm_struct *pDM_Odm); -void -ODM_ResetIQKResult( - struct odm_dm_struct *pDM_Odm - ); +void ODM_ResetIQKResult(struct odm_dm_struct *pDM_Odm); -void -ODM_AntselStatistics_88C( - struct odm_dm_struct *pDM_Odm, - u8 MacId, - u32 PWDBAll, - bool isCCKrate -); +void ODM_AntselStatistics_88C(struct odm_dm_struct *pDM_Odm, u8 MacId, + u32 PWDBAll, bool isCCKrate); -void -ODM_SingleDualAntennaDefaultSetting( - struct odm_dm_struct *pDM_Odm - ); +void ODM_SingleDualAntennaDefaultSetting(struct odm_dm_struct *pDM_Odm); -bool -ODM_SingleDualAntennaDetection( - struct odm_dm_struct *pDM_Odm, - u8 mode - ); +bool ODM_SingleDualAntennaDetection(struct odm_dm_struct *pDM_Odm, u8 mode); void odm_dtc(struct odm_dm_struct *pDM_Odm); diff --git a/include/odm_HWConfig.h b/include/odm_HWConfig.h index 49e90f2..930a2c6 100644 --- a/include/odm_HWConfig.h +++ b/include/odm_HWConfig.h @@ -18,24 +18,19 @@ * ******************************************************************************/ - #ifndef __HALHWOUTSRC_H__ #define __HALHWOUTSRC_H__ -/* */ /* Definition */ -/* */ -/* */ -/* */ /* CCK Rates, TxHT = 0 */ -#define DESC92C_RATE1M 0x00 -#define DESC92C_RATE2M 0x01 -#define DESC92C_RATE5_5M 0x02 +#define DESC92C_RATE1M 0x00 +#define DESC92C_RATE2M 0x01 +#define DESC92C_RATE5_5M 0x02 #define DESC92C_RATE11M 0x03 /* OFDM Rates, TxHT = 0 */ -#define DESC92C_RATE6M 0x04 -#define DESC92C_RATE9M 0x05 +#define DESC92C_RATE6M 0x04 +#define DESC92C_RATE9M 0x05 #define DESC92C_RATE12M 0x06 #define DESC92C_RATE18M 0x07 #define DESC92C_RATE24M 0x08 @@ -44,35 +39,32 @@ #define DESC92C_RATE54M 0x0b /* MCS Rates, TxHT = 1 */ -#define DESC92C_RATEMCS0 0x0c -#define DESC92C_RATEMCS1 0x0d -#define DESC92C_RATEMCS2 0x0e -#define DESC92C_RATEMCS3 0x0f -#define DESC92C_RATEMCS4 0x10 -#define DESC92C_RATEMCS5 0x11 -#define DESC92C_RATEMCS6 0x12 -#define DESC92C_RATEMCS7 0x13 -#define DESC92C_RATEMCS8 0x14 -#define DESC92C_RATEMCS9 0x15 -#define DESC92C_RATEMCS10 0x16 -#define DESC92C_RATEMCS11 0x17 -#define DESC92C_RATEMCS12 0x18 -#define DESC92C_RATEMCS13 0x19 -#define DESC92C_RATEMCS14 0x1a -#define DESC92C_RATEMCS15 0x1b +#define DESC92C_RATEMCS0 0x0c +#define DESC92C_RATEMCS1 0x0d +#define DESC92C_RATEMCS2 0x0e +#define DESC92C_RATEMCS3 0x0f +#define DESC92C_RATEMCS4 0x10 +#define DESC92C_RATEMCS5 0x11 +#define DESC92C_RATEMCS6 0x12 +#define DESC92C_RATEMCS7 0x13 +#define DESC92C_RATEMCS8 0x14 +#define DESC92C_RATEMCS9 0x15 +#define DESC92C_RATEMCS10 0x16 +#define DESC92C_RATEMCS11 0x17 +#define DESC92C_RATEMCS12 0x18 +#define DESC92C_RATEMCS13 0x19 +#define DESC92C_RATEMCS14 0x1a +#define DESC92C_RATEMCS15 0x1b #define DESC92C_RATEMCS15_SG 0x1c -#define DESC92C_RATEMCS32 0x20 +#define DESC92C_RATEMCS32 0x20 - -/* */ /* structure and define */ -/* */ struct phy_rx_agc_info { #ifdef __LITTLE_ENDIAN - u8 gain:7,trsw:1; + u8 gain:7, trsw:1; #else - u8 trsw:1,gain:7; + u8 trsw:1, gain:7; #endif }; @@ -114,45 +106,27 @@ struct phy_status_rpt { #endif }; -void -odm_Init_RSSIForDM( - struct odm_dm_struct *pDM_Odm - ); +void odm_Init_RSSIForDM(struct odm_dm_struct *pDM_Odm); -void -ODM_PhyStatusQuery( - struct odm_dm_struct * pDM_Odm, +void ODM_PhyStatusQuery(struct odm_dm_struct *pDM_Odm, struct odm_phy_status_info *pPhyInfo, u8 *pPhyStatus, - struct odm_per_pkt_info *pPktinfo - ); + struct odm_per_pkt_info *pPktinfo); -void -ODM_MacStatusQuery( - struct odm_dm_struct * pDM_Odm, +void ODM_MacStatusQuery(struct odm_dm_struct *pDM_Odm, u8 *pMacStatus, - u8 MacID, - bool bPacketMatchBSSID, - bool bPacketToSelf, - bool bPacketBeacon - ); + u8 MacID, + bool bPacketMatchBSSID, + bool bPacketToSelf, + bool bPacketBeacon); -enum HAL_STATUS -ODM_ConfigRFWithHeaderFile( - struct odm_dm_struct * pDM_Odm, - enum ODM_RF_RADIO_PATH Content, - enum ODM_RF_RADIO_PATH eRFPath - ); +enum HAL_STATUS ODM_ConfigRFWithHeaderFile(struct odm_dm_struct *pDM_Odm, + enum ODM_RF_RADIO_PATH Content, + enum ODM_RF_RADIO_PATH eRFPath); -enum HAL_STATUS -ODM_ConfigBBWithHeaderFile( - struct odm_dm_struct * pDM_Odm, - enum odm_bb_config_type ConfigType - ); +enum HAL_STATUS ODM_ConfigBBWithHeaderFile(struct odm_dm_struct *pDM_Odm, + enum odm_bb_config_type ConfigType); -enum HAL_STATUS -ODM_ConfigMACWithHeaderFile( - struct odm_dm_struct *pDM_Odm - ); +enum HAL_STATUS ODM_ConfigMACWithHeaderFile(struct odm_dm_struct *pDM_Odm); #endif diff --git a/include/odm_RTL8188E.h b/include/odm_RTL8188E.h index 46ae6d5..f96ad5a 100644 --- a/include/odm_RTL8188E.h +++ b/include/odm_RTL8188E.h @@ -33,41 +33,24 @@ void ODM_AntennaDiversityInit_88E(struct odm_dm_struct *pDM_Odm); void ODM_AntennaDiversity_88E(struct odm_dm_struct *pDM_Odm); -void ODM_SetTxAntByTxInfo_88E(struct odm_dm_struct *pDM_Odm, u8 *pDesc, u8 macId); +void ODM_SetTxAntByTxInfo_88E(struct odm_dm_struct *pDM_Odm, u8 *pDesc, + u8 macId); void ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *pDM_Odm, u8 Ant); -void ODM_AntselStatistics_88E(struct odm_dm_struct *pDM_Odm, - u8 antsel_tr_mux, - u32 MacId, - u8 RxPWDBAll -); +void ODM_AntselStatistics_88E(struct odm_dm_struct *pDM_Odm, u8 antsel_tr_mux, + u32 MacId, u8 RxPWDBAll); -void -odm_FastAntTraining( - struct odm_dm_struct *pDM_Odm -); +void odm_FastAntTraining(struct odm_dm_struct *pDM_Odm); -void -odm_FastAntTrainingCallback( - struct odm_dm_struct *pDM_Odm -); +void odm_FastAntTrainingCallback(struct odm_dm_struct *pDM_Odm); -void -odm_FastAntTrainingWorkItemCallback( - struct odm_dm_struct *pDM_Odm -); +void odm_FastAntTrainingWorkItemCallback(struct odm_dm_struct *pDM_Odm); -void -odm_PrimaryCCA_Init( - struct odm_dm_struct *pDM_Odm); +void odm_PrimaryCCA_Init(struct odm_dm_struct *pDM_Odm); -bool -ODM_DynamicPrimaryCCA_DupRTS( - struct odm_dm_struct *pDM_Odm); +bool ODM_DynamicPrimaryCCA_DupRTS(struct odm_dm_struct *pDM_Odm); -void -odm_DynamicPrimaryCCA( - struct odm_dm_struct *pDM_Odm); +void odm_DynamicPrimaryCCA(struct odm_dm_struct *pDM_Odm); #endif diff --git a/include/odm_RegConfig8188E.h b/include/odm_RegConfig8188E.h index 482bdbf..727e6b2 100644 --- a/include/odm_RegConfig8188E.h +++ b/include/odm_RegConfig8188E.h @@ -23,48 +23,21 @@ void odm_ConfigRFReg_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Data, enum ODM_RF_RADIO_PATH RF_PATH, u32 RegAddr); -void -odm_ConfigRF_RadioA_8188E( - struct odm_dm_struct *pDM_Odm, - u32 Addr, - u32 Data - ); +void odm_ConfigRF_RadioA_8188E(struct odm_dm_struct *pDM_Odm, + u32 Addr, u32 Data); -void -odm_ConfigRF_RadioB_8188E( - struct odm_dm_struct *pDM_Odm, - u32 Addr, - u32 Data - ); +void odm_ConfigRF_RadioB_8188E(struct odm_dm_struct *pDM_Odm, + u32 Addr, u32 Data); -void -odm_ConfigMAC_8188E( - struct odm_dm_struct *pDM_Odm, - u32 Addr, - u8 Data - ); +void odm_ConfigMAC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u8 Data); -void -odm_ConfigBB_AGC_8188E( - struct odm_dm_struct *pDM_Odm, - u32 Addr, - u32 Bitmask, - u32 Data - ); +void odm_ConfigBB_AGC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, + u32 Bitmask, u32 Data); -void -odm_ConfigBB_PHY_REG_PG_8188E( - struct odm_dm_struct *pDM_Odm, - u32 Addr, - u32 Bitmask, - u32 Data - ); +void odm_ConfigBB_PHY_REG_PG_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, + u32 Bitmask, u32 Data); + +void odm_ConfigBB_PHY_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, + u32 Bitmask, u32 Data); -void -odm_ConfigBB_PHY_8188E( - struct odm_dm_struct *pDM_Odm, - u32 Addr, - u32 Bitmask, - u32 Data - ); #endif diff --git a/include/odm_debug.h b/include/odm_debug.h index fdfe12f..c86849c 100644 --- a/include/odm_debug.h +++ b/include/odm_debug.h @@ -24,133 +24,122 @@ /* */ -/* Define the debug levels */ +/* Define the debug levels */ /* */ -/* 1. DBG_TRACE and DBG_LOUD are used for normal cases. */ -/* So that, they can help SW engineer to develope or trace states changed */ -/* and also help HW enginner to trace every operation to and from HW, */ -/* e.g IO, Tx, Rx. */ +/* 1. DBG_TRACE and DBG_LOUD are used for normal cases. */ +/* They can help SW engineer to develope or trace states changed */ +/* and also help HW enginner to trace every operation to and from HW, */ +/* e.g IO, Tx, Rx. */ /* */ -/* 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, */ -/* which help us to debug SW or HW. */ -/* */ -/* */ -/* */ -/* Never used in a call to ODM_RT_TRACE()! */ -/* */ -#define ODM_DBG_OFF 1 +/* 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, */ +/* which help us to debug SW or HW. */ -/* */ -/* Fatal bug. */ -/* For example, Tx/Rx/IO locked up, OS hangs, memory access violation, */ -/* resource allocation failed, unexpected HW behavior, HW BUG and so on. */ -/* */ +/* Never used in a call to ODM_RT_TRACE()! */ +#define ODM_DBG_OFF 1 + +/* Fatal bug. */ +/* For example, Tx/Rx/IO locked up, OS hangs, memory access violation, */ +/* resource allocation failed, unexpected HW behavior, HW BUG and so on. */ #define ODM_DBG_SERIOUS 2 -/* */ -/* Abnormal, rare, or unexpeted cases. */ -/* For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. */ -/* */ +/* Abnormal, rare, or unexpeted cases. */ +/* For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. */ #define ODM_DBG_WARNING 3 -/* */ -/* Normal case with useful information about current SW or HW state. */ -/* For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, */ -/* SW protocol state change, dynamic mechanism state change and so on. */ +/* Normal case with useful information about current SW or HW state. */ +/* For example, Tx/Rx descriptor to fill, Tx/Rx descr. completed status, */ +/* SW protocol state change, dynamic mechanism state change and so on. */ /* */ #define ODM_DBG_LOUD 4 -/* */ -/* Normal case with detail execution flow or information. */ -/* */ +/* Normal case with detail execution flow or information. */ #define ODM_DBG_TRACE 5 -/* */ /* Define the tracing components */ -/* */ -/* */ /* BB Functions */ #define ODM_COMP_DIG BIT0 #define ODM_COMP_RA_MASK BIT1 -#define ODM_COMP_DYNAMIC_TXPWR BIT2 -#define ODM_COMP_FA_CNT BIT3 -#define ODM_COMP_RSSI_MONITOR BIT4 -#define ODM_COMP_CCK_PD BIT5 +#define ODM_COMP_DYNAMIC_TXPWR BIT2 +#define ODM_COMP_FA_CNT BIT3 +#define ODM_COMP_RSSI_MONITOR BIT4 +#define ODM_COMP_CCK_PD BIT5 #define ODM_COMP_ANT_DIV BIT6 -#define ODM_COMP_PWR_SAVE BIT7 -#define ODM_COMP_PWR_TRA BIT8 -#define ODM_COMP_RATE_ADAPTIVE BIT9 +#define ODM_COMP_PWR_SAVE BIT7 +#define ODM_COMP_PWR_TRA BIT8 +#define ODM_COMP_RATE_ADAPTIVE BIT9 #define ODM_COMP_PATH_DIV BIT10 #define ODM_COMP_PSD BIT11 -#define ODM_COMP_DYNAMIC_PRICCA BIT12 -#define ODM_COMP_RXHP BIT13 +#define ODM_COMP_DYNAMIC_PRICCA BIT12 +#define ODM_COMP_RXHP BIT13 /* MAC Functions */ -#define ODM_COMP_EDCA_TURBO BIT16 -#define ODM_COMP_EARLY_MODE BIT17 +#define ODM_COMP_EDCA_TURBO BIT16 +#define ODM_COMP_EARLY_MODE BIT17 /* RF Functions */ -#define ODM_COMP_TX_PWR_TRACK BIT24 -#define ODM_COMP_RX_GAIN_TRACK BIT25 -#define ODM_COMP_CALIBRATION BIT26 +#define ODM_COMP_TX_PWR_TRACK BIT24 +#define ODM_COMP_RX_GAIN_TRACK BIT25 +#define ODM_COMP_CALIBRATION BIT26 /* Common Functions */ -#define ODM_COMP_COMMON BIT30 +#define ODM_COMP_COMMON BIT30 #define ODM_COMP_INIT BIT31 /*------------------------Export Marco Definition---------------------------*/ - #define DbgPrint printk - #define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __func__, ## args); +#define DbgPrint pr_info +#define RT_PRINTK(fmt, args...) \ + DbgPrint( "%s(): " fmt, __func__, ## args); #ifndef ASSERT #define ASSERT(expr) #endif #if DBG -#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \ - if (((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \ - { \ - if (pDM_Odm->SupportICType == ODM_RTL8192C) \ - DbgPrint("[ODM-92C] "); \ - else if (pDM_Odm->SupportICType == ODM_RTL8192D) \ - DbgPrint("[ODM-92D] "); \ - else if (pDM_Odm->SupportICType == ODM_RTL8723A) \ - DbgPrint("[ODM-8723A] "); \ - else if (pDM_Odm->SupportICType == ODM_RTL8188E) \ - DbgPrint("[ODM-8188E] "); \ - else if (pDM_Odm->SupportICType == ODM_RTL8812) \ - DbgPrint("[ODM-8812] "); \ - else if (pDM_Odm->SupportICType == ODM_RTL8821) \ - DbgPrint("[ODM-8821] "); \ - RT_PRINTK fmt; \ - } +#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \ + if (((comp) & pDM_Odm->DebugComponents) && \ + (level <= pDM_Odm->DebugLevel)) { \ + if (pDM_Odm->SupportICType == ODM_RTL8192C) \ + DbgPrint("[ODM-92C] "); \ + else if (pDM_Odm->SupportICType == ODM_RTL8192D) \ + DbgPrint("[ODM-92D] "); \ + else if (pDM_Odm->SupportICType == ODM_RTL8723A) \ + DbgPrint("[ODM-8723A] "); \ + else if (pDM_Odm->SupportICType == ODM_RTL8188E) \ + DbgPrint("[ODM-8188E] "); \ + else if (pDM_Odm->SupportICType == ODM_RTL8812) \ + DbgPrint("[ODM-8812] "); \ + else if (pDM_Odm->SupportICType == ODM_RTL8821) \ + DbgPrint("[ODM-8821] "); \ + RT_PRINTK fmt; \ + } -#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) \ - if (((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \ - { \ - RT_PRINTK fmt; \ - } +#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) \ + if (((comp) & pDM_Odm->DebugComponents) && \ + (level <= pDM_Odm->DebugLevel)) { \ + RT_PRINTK fmt; \ + } -#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \ - if (!(expr)) { \ - DbgPrint( "Assertion failed! %s at ......\n", #expr); \ - DbgPrint( " ......%s,%s,line=%d\n",__FILE__,__func__,__LINE__); \ - RT_PRINTK fmt; \ - ASSERT(false); \ - } +#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \ + if (!(expr)) { \ + DbgPrint( "Assertion failed! %s at ......\n", #expr); \ + DbgPrint( " ......%s,%s,line=%d\n", __FILE__, \ + __func__, __LINE__); \ + RT_PRINTK fmt; \ + ASSERT(false); \ + } #define ODM_dbg_enter() { DbgPrint("==> %s\n", __func__); } #define ODM_dbg_exit() { DbgPrint("<== %s\n", __func__); } #define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __func__, str); } -#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) \ - if (((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \ - { \ - int __i; \ - pu8 __ptr = (pu8)ptr; \ - DbgPrint("[ODM] "); \ - DbgPrint(title_str); \ - DbgPrint(" "); \ - for ( __i=0; __i<6; __i++ ) \ - DbgPrint("%02X%s", __ptr[__i], (__i==5)?"":"-"); \ - DbgPrint("\n"); \ - } +#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) \ + if (((comp) & pDM_Odm->DebugComponents) && \ + (level <= pDM_Odm->DebugLevel)) { \ + int __i; \ + u8 *__ptr = (u8 *)ptr; \ + DbgPrint("[ODM] "); \ + DbgPrint(title_str); \ + DbgPrint(" "); \ + for (__i = 0; __i < 6; __i++) \ + DbgPrint("%02X%s", __ptr[__i], (__i==5)?"":"-");\ + DbgPrint("\n"); \ + } #else #define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) #define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) diff --git a/include/odm_interface.h b/include/odm_interface.h index 8e19342..3dd2eae 100644 --- a/include/odm_interface.h +++ b/include/odm_interface.h @@ -49,39 +49,33 @@ ODM_REG(DIG,_pDM_Odm) #define _bit_11N(_name) ODM_BIT_##_name##_11N #define _bit_11AC(_name) ODM_BIT_##_name##_11AC -#define _cat(_name, _ic_type, _func) \ - ( \ - ((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \ - _func##_11AC(_name) \ +#define _cat(_name, _ic_type, _func) \ + ( \ + ((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \ + _func##_11AC(_name) \ ) /* _name: name of register or bit. */ /* Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)" */ -/* gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType. */ -#define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg) -#define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit) +/* gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", + * depends on SupportICType. */ +#define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg) +#define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit) enum odm_h2c_cmd { ODM_H2C_RSSI_REPORT = 0, - ODM_H2C_PSD_RESULT=1, + ODM_H2C_PSD_RESULT= 1, ODM_H2C_PathDiv = 2, ODM_MAX_H2CCMD }; -/* */ /* 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem. */ /* Suggest HW team to use thread instead of workitem. Windows also support the feature. */ -/* */ -typedef void (*RT_WORKITEM_CALL_BACK)(void * pContext); +typedef void (*RT_WORKITEM_CALL_BACK)(void *pContext); -/* */ /* =========== Extern Variable ??? It should be forbidden. */ -/* */ - -/* */ /* =========== EXtern Function Prototype */ -/* */ u8 ODM_Read1Byte(struct odm_dm_struct *pDM_Odm, u32 RegAddr); @@ -95,36 +89,37 @@ void ODM_Write2Byte(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u16 Data); void ODM_Write4Byte(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 Data); -void ODM_SetMACReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 BitMask, u32 Data); +void ODM_SetMACReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, + u32 BitMask, u32 Data); u32 ODM_GetMACReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 BitMask); -void ODM_SetBBReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 BitMask, u32 Data); +void ODM_SetBBReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, + u32 BitMask, u32 Data); u32 ODM_GetBBReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 BitMask); -void ODM_SetRFReg(struct odm_dm_struct *pDM_Odm, enum ODM_RF_RADIO_PATH eRFPath, u32 RegAddr, u32 BitMask, u32 Data); +void ODM_SetRFReg(struct odm_dm_struct *pDM_Odm, enum ODM_RF_RADIO_PATH eRFPath, + u32 RegAddr, u32 BitMask, u32 Data); -u32 ODM_GetRFReg(struct odm_dm_struct *pDM_Odm, enum ODM_RF_RADIO_PATH eRFPath, u32 RegAddr, u32 BitMask); +u32 ODM_GetRFReg(struct odm_dm_struct *pDM_Odm, enum ODM_RF_RADIO_PATH eRFPath, + u32 RegAddr, u32 BitMask); -/* */ /* Memory Relative Function. */ -/* */ void ODM_AllocateMemory(struct odm_dm_struct *pDM_Odm, void **pPtr, u32 length); void ODM_FreeMemory(struct odm_dm_struct *pDM_Odm, void *pPtr, u32 length); -s32 ODM_CompareMemory(struct odm_dm_struct *pDM_Odm, void *pBuf1, void *pBuf2, u32 length); +s32 ODM_CompareMemory(struct odm_dm_struct *pDM_Odm, void *pBuf1, void *pBuf2, + u32 length); -/* */ /* ODM MISC-spin lock relative API. */ -/* */ -void ODM_AcquireSpinLock(struct odm_dm_struct *pDM_Odm, enum RT_SPINLOCK_TYPE type); +void ODM_AcquireSpinLock(struct odm_dm_struct *pDM_Odm, + enum RT_SPINLOCK_TYPE type); -void ODM_ReleaseSpinLock(struct odm_dm_struct *pDM_Odm, enum RT_SPINLOCK_TYPE type); +void ODM_ReleaseSpinLock(struct odm_dm_struct *pDM_Odm, + enum RT_SPINLOCK_TYPE type); -/* */ /* ODM MISC-workitem relative API. */ -/* */ void ODM_InitializeWorkItem(struct odm_dm_struct *pDM_Odm, void *pRtWorkItem, RT_WORKITEM_CALL_BACK RtWorkItemCallback, void *pContext, const char *szID); @@ -139,9 +134,7 @@ void ODM_ScheduleWorkItem(void *pRtWorkItem); void ODM_IsWorkItemScheduled(void *pRtWorkItem); -/* */ /* ODM Timer relative API. */ -/* */ void ODM_StallExecution(u32 usDelay); void ODM_delay_ms(u32 ms); @@ -152,17 +145,20 @@ void ODM_sleep_ms(u32 ms); void ODM_sleep_us(u32 us); -void ODM_SetTimer(struct odm_dm_struct *pDM_Odm, struct timer_list *pTimer, u32 msDelay); +void ODM_SetTimer(struct odm_dm_struct *pDM_Odm, struct timer_list *pTimer, + u32 msDelay); -void ODM_InitializeTimer(struct odm_dm_struct *pDM_Odm, struct timer_list *pTimer, void *CallBackFunc, void *pContext, const char *szID); +void ODM_InitializeTimer(struct odm_dm_struct *pDM_Odm, + struct timer_list *pTimer, void *CallBackFunc, + void *pContext, const char *szID); void ODM_CancelTimer(struct odm_dm_struct *pDM_Odm, struct timer_list *pTimer); void ODM_ReleaseTimer(struct odm_dm_struct *pDM_Odm, struct timer_list *pTimer); -/* */ /* ODM FW relative API. */ -/* */ -u32 ODM_FillH2CCmd(u8 *pH2CBuffer, u32 H2CBufferLen, u32 CmdNum, u32 *pElementID, u32 *pCmdLen, u8 **pCmbBuffer, u8 *CmdStartSeq); +u32 ODM_FillH2CCmd(u8 *pH2CBuffer, u32 H2CBufferLen, u32 CmdNum, + u32 *pElementID, u32 *pCmdLen, u8 **pCmbBuffer, + u8 *CmdStartSeq); #endif /* __ODM_INTERFACE_H__ */ diff --git a/include/odm_types.h b/include/odm_types.h index 0a1bf60..78ee2ba 100644 --- a/include/odm_types.h +++ b/include/odm_types.h @@ -38,16 +38,19 @@ enum HAL_STATUS { }; enum RT_SPINLOCK_TYPE { - RT_TEMP =1, + RT_TEMP = 1, }; #include #define DEV_BUS_TYPE RT_USB_INTERFACE -#define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value) -#define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value) -#define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value) +#define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value) +#define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value) +#define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value) /* define useless flag to avoid compile warning */ #define USE_WORKITEM 0 diff --git a/include/osdep_intf.h b/include/osdep_intf.h index 32f7d25..5071bae 100644 --- a/include/osdep_intf.h +++ b/include/osdep_intf.h @@ -25,14 +25,13 @@ #include struct intf_priv { - u8 *intf_dev; u32 max_iosz; /* USB2.0: 128, USB1.1: 64, SDIO:64 */ u32 max_xmitsz; /* USB2.0: unlimited, SDIO:512 */ u32 max_recvsz; /* USB2.0: unlimited, SDIO:512 */ - volatile u8 *io_rwmem; - volatile u8 *allocated_io_rwmem; + u8 *io_rwmem; + u8 *allocated_io_rwmem; u32 io_wsz; /* unit: 4bytes */ u32 io_rsz;/* unit: 4bytes */ u8 intf_status; @@ -49,7 +48,7 @@ The protection mechanism is through the pending queue. struct mutex ioctl_mutex; /* when in USB, IO is through interrupt in/out endpoints */ struct usb_device *udev; - struct urb * piorw_urb; + struct urb *piorw_urb; u8 io_irp_cnt; u8 bio_irp_pending; struct semaphore io_retevt; @@ -74,9 +73,9 @@ int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname); struct net_device *rtw_init_netdev(struct adapter *padapter); -#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) u16 rtw_recv_select_queue(struct sk_buff *skb); -#endif /* LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35) */ +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35) */ void rtw_proc_init_one(struct net_device *dev); void rtw_proc_remove_one(struct net_device *dev); @@ -85,7 +84,7 @@ void rtw_ips_dev_unload(struct adapter *padapter); int rtw_ips_pwr_up(struct adapter *padapter); void rtw_ips_pwr_down(struct adapter *padapter); -int rtw_hw_suspend(struct adapter *padapter ); +int rtw_hw_suspend(struct adapter *padapter); int rtw_hw_resume(struct adapter *padapter); #endif /* _OSDEP_INTF_H_ */ diff --git a/include/osdep_service.h b/include/osdep_service.h index d766f7c..6f59bb0 100644 --- a/include/osdep_service.h +++ b/include/osdep_service.h @@ -34,21 +34,17 @@ #include #include #include -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,5)) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 5)) #include #endif #include #include #include -#include +#include #include -#include -#include -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) -#include -#else +#include +#include #include -#endif #include #include #include @@ -63,24 +59,23 @@ #include #include -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 21)) #include #else #include #endif +struct __queue { + struct list_head queue; + spinlock_t lock; +}; - struct __queue { - struct list_head queue; - spinlock_t lock; - }; +#define thread_exit() complete_and_exit(NULL, 0) - #define thread_exit() complete_and_exit(NULL, 0) - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) #endif -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22)) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 22)) /* Porting from linux kernel, for compatible with old kernel. */ static inline unsigned char *skb_tail_pointer(const struct sk_buff *skb) { @@ -103,12 +98,12 @@ static inline unsigned char *skb_end_pointer(const struct sk_buff *skb) } #endif -__inline static struct list_head *get_next(struct list_head *list) +static inline struct list_head *get_next(struct list_head *list) { return list->next; } -__inline static struct list_head *get_list_head(struct __queue *queue) +static inline struct list_head *get_list_head(struct __queue *queue) { return (&(queue->queue)); } @@ -118,37 +113,37 @@ __inline static struct list_head *get_list_head(struct __queue *queue) ((type *)((char *)(ptr)-(size_t)(&((type *)0)->member))) -__inline static void _enter_critical(spinlock_t *plock, unsigned long *pirqL) +static inline void _enter_critical(spinlock_t *plock, unsigned long *pirqL) { spin_lock_irqsave(plock, *pirqL); } -__inline static void _exit_critical(spinlock_t *plock, unsigned long *pirqL) +static inline void _exit_critical(spinlock_t *plock, unsigned long *pirqL) { spin_unlock_irqrestore(plock, *pirqL); } -__inline static void _enter_critical_ex(spinlock_t *plock, unsigned long *pirqL) +static inline void _enter_critical_ex(spinlock_t *plock, unsigned long *pirqL) { spin_lock_irqsave(plock, *pirqL); } -__inline static void _exit_critical_ex(spinlock_t *plock, unsigned long *pirqL) +static inline void _exit_critical_ex(spinlock_t *plock, unsigned long *pirqL) { spin_unlock_irqrestore(plock, *pirqL); } -__inline static void _enter_critical_bh(spinlock_t *plock, unsigned long *pirqL) +static inline void _enter_critical_bh(spinlock_t *plock, unsigned long *pirqL) { spin_lock_bh(plock); } -__inline static void _exit_critical_bh(spinlock_t *plock, unsigned long *pirqL) +static inline void _exit_critical_bh(spinlock_t *plock, unsigned long *pirqL) { spin_unlock_bh(plock); } -__inline static int _enter_critical_mutex(struct mutex *pmutex, unsigned long *pirqL) +static inline int _enter_critical_mutex(struct mutex *pmutex, unsigned long *pirqL) { int ret = 0; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) @@ -160,7 +155,7 @@ __inline static int _enter_critical_mutex(struct mutex *pmutex, unsigned long *p } -__inline static void _exit_critical_mutex(struct mutex *pmutex, unsigned long *pirqL) +static inline void _exit_critical_mutex(struct mutex *pmutex, unsigned long *pirqL) { #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) mutex_unlock(pmutex); @@ -169,24 +164,24 @@ __inline static void _exit_critical_mutex(struct mutex *pmutex, unsigned long *p #endif } -__inline static void rtw_list_delete(struct list_head *plist) +static inline void rtw_list_delete(struct list_head *plist) { list_del_init(plist); } -__inline static void _init_timer(struct timer_list *ptimer,struct net_device *nic_hdl,void *pfunc,void* cntx) +static inline void _init_timer(struct timer_list *ptimer,struct net_device *nic_hdl,void *pfunc,void* cntx) { ptimer->function = pfunc; ptimer->data = (unsigned long)cntx; init_timer(ptimer); } -__inline static void _set_timer(struct timer_list *ptimer,u32 delay_time) +static inline void _set_timer(struct timer_list *ptimer,u32 delay_time) { mod_timer(ptimer , (jiffies+(delay_time*HZ/1000))); } -__inline static void _cancel_timer(struct timer_list *ptimer,u8 *bcancelled) +static inline void _cancel_timer(struct timer_list *ptimer,u8 *bcancelled) { del_timer_sync(ptimer); *bcancelled= true;/* true ==1; false==0 */ @@ -196,7 +191,7 @@ __inline static void _cancel_timer(struct timer_list *ptimer,u8 *bcancelled) #define RTW_TIMER_HDL_NAME(name) rtw_##name##_timer_hdl #define RTW_DECLARE_TIMER_HDL(name) void RTW_TIMER_HDL_NAME(name)(RTW_TIMER_HDL_ARGS) -__inline static void _init_workitem(struct work_struct *pwork, void *pfunc, void * cntx) +static inline void _init_workitem(struct work_struct *pwork, void *pfunc, void * cntx) { #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) INIT_WORK(pwork, pfunc); @@ -205,12 +200,12 @@ __inline static void _init_workitem(struct work_struct *pwork, void *pfunc, void #endif } -__inline static void _set_workitem(struct work_struct *pwork) +static inline void _set_workitem(struct work_struct *pwork) { schedule_work(pwork); } -__inline static void _cancel_workitem_sync(struct work_struct *pwork) +static inline void _cancel_workitem_sync(struct work_struct *pwork) { #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22)) cancel_work_sync(pwork); @@ -401,7 +396,7 @@ extern void rtw_udelay_os(int us); extern void rtw_yield_os(void); -__inline static unsigned char _cancel_timer_ex(struct timer_list *ptimer) +static inline unsigned char _cancel_timer_ex(struct timer_list *ptimer) { return del_timer_sync(ptimer); } @@ -414,13 +409,13 @@ static __inline void thread_enter(char *name) allow_signal(SIGTERM); } -__inline static void flush_signals_thread(void) +static inline void flush_signals_thread(void) { if (signal_pending (current)) flush_signals(current); } -__inline static int res_to_status(int res) +static inline int res_to_status(int res) { return res; } @@ -428,7 +423,7 @@ __inline static int res_to_status(int res) #define _RND(sz, r) ((((sz)+((r)-1))/(r))*(r)) #define RND4(x) (((x >> 2) + (((x & 3) == 0) ? 0: 1)) << 2) -__inline static u32 _RND4(u32 sz) +static inline u32 _RND4(u32 sz) { u32 val; @@ -436,7 +431,7 @@ __inline static u32 _RND4(u32 sz) return val; } -__inline static u32 _RND8(u32 sz) +static inline u32 _RND8(u32 sz) { u32 val; @@ -444,7 +439,7 @@ __inline static u32 _RND8(u32 sz) return val; } -__inline static u32 _RND128(u32 sz) +static inline u32 _RND128(u32 sz) { u32 val; @@ -452,7 +447,7 @@ __inline static u32 _RND128(u32 sz) return val; } -__inline static u32 _RND256(u32 sz) +static inline u32 _RND256(u32 sz) { u32 val; @@ -460,7 +455,7 @@ __inline static u32 _RND256(u32 sz) return val; } -__inline static u32 _RND512(u32 sz) +static inline u32 _RND512(u32 sz) { u32 val; @@ -468,7 +463,7 @@ __inline static u32 _RND512(u32 sz) return val; } -__inline static u32 bitshift(u32 bitmask) +static inline u32 bitshift(u32 bitmask) { u32 i; @@ -477,47 +472,47 @@ __inline static u32 bitshift(u32 bitmask) return i; } -#define STRUCT_PACKED __attribute__ ((packed)) - /* limitation of path length */ - #define PATH_LENGTH_MAX PATH_MAX +#define PATH_LENGTH_MAX PATH_MAX -extern void rtw_suspend_lock_init(void); -extern void rtw_suspend_lock_uninit(void); -extern void rtw_lock_suspend(void); -extern void rtw_unlock_suspend(void); +void rtw_suspend_lock_init(void); +void rtw_suspend_lock_uninit(void); +void rtw_lock_suspend(void); +void rtw_unlock_suspend(void); #ifdef CONFIG_WOWLAN -extern void rtw_lock_suspend_timeout(long timeout); +void rtw_lock_suspend_timeout(long timeout); #endif /* CONFIG_WOWLAN */ /* Atomic integer operations */ #define ATOMIC_T atomic_t -extern void ATOMIC_SET(ATOMIC_T *v, int i); -extern int ATOMIC_READ(ATOMIC_T *v); -extern void ATOMIC_ADD(ATOMIC_T *v, int i); -extern void ATOMIC_SUB(ATOMIC_T *v, int i); -extern void ATOMIC_INC(ATOMIC_T *v); -extern void ATOMIC_DEC(ATOMIC_T *v); -extern int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i); -extern int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i); -extern int ATOMIC_INC_RETURN(ATOMIC_T *v); -extern int ATOMIC_DEC_RETURN(ATOMIC_T *v); +void ATOMIC_SET(ATOMIC_T *v, int i); +int ATOMIC_READ(ATOMIC_T *v); +void ATOMIC_ADD(ATOMIC_T *v, int i); +void ATOMIC_SUB(ATOMIC_T *v, int i); +void ATOMIC_INC(ATOMIC_T *v); +void ATOMIC_DEC(ATOMIC_T *v); +int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i); +int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i); +int ATOMIC_INC_RETURN(ATOMIC_T *v); +int ATOMIC_DEC_RETURN(ATOMIC_T *v); /* File operation APIs, just for linux now */ -extern int rtw_is_file_readable(char *path); -extern int rtw_retrive_from_file(char *path, u8 __user *buf, u32 sz); -extern int rtw_store_to_file(char *path, u8 __user *buf, u32 sz); +int rtw_is_file_readable(char *path); +int rtw_retrive_from_file(char *path, u8 __user *buf, u32 sz); +int rtw_store_to_file(char *path, u8 __user *buf, u32 sz); struct rtw_netdev_priv_indicator { void *priv; u32 sizeof_priv; }; -struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv); -extern struct net_device * rtw_alloc_etherdev(int sizeof_priv); +struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, + void *old_priv); +struct net_device *rtw_alloc_etherdev(int sizeof_priv); -#define rtw_netdev_priv(netdev) ( ((struct rtw_netdev_priv_indicator *)netdev_priv(netdev))->priv ) -extern void rtw_free_netdev(struct net_device * netdev); +#define rtw_netdev_priv(netdev) \ + (((struct rtw_netdev_priv_indicator *)netdev_priv(netdev))->priv) +void rtw_free_netdev(struct net_device *netdev); #define NDEV_FMT "%s" #define NDEV_ARG(ndev) ndev->name @@ -534,8 +529,8 @@ extern void rtw_free_netdev(struct net_device * netdev); #define rtw_signal_process(pid, sig) kill_proc((pid), (sig), 1) #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */ -extern u64 rtw_modular64(u64 x, u64 y); -extern u64 rtw_division64(u64 x, u64 y); +u64 rtw_modular64(u64 x, u64 y); +u64 rtw_division64(u64 x, u64 y); /* Macros for handling unaligned memory accesses */ diff --git a/include/recv_osdep.h b/include/recv_osdep.h index a407446..e61d0b2 100644 --- a/include/recv_osdep.h +++ b/include/recv_osdep.h @@ -24,29 +24,26 @@ #include -extern int _rtw_init_recv_priv(struct recv_priv *precvpriv, struct adapter *padapter); -extern void _rtw_free_recv_priv (struct recv_priv *precvpriv); +int _rtw_init_recv_priv(struct recv_priv *precvpriv, struct adapter *padapter); +void _rtw_free_recv_priv(struct recv_priv *precvpriv); -extern s32 rtw_recv_entry(union recv_frame *precv_frame); -extern int rtw_recv_indicatepkt(struct adapter *adapter, union recv_frame *precv_frame); -extern void rtw_recv_returnpacket(struct net_device *cnxt, struct sk_buff *preturnedpkt); +s32 rtw_recv_entry(union recv_frame *precv_frame); +int rtw_recv_indicatepkt(struct adapter *adapter, union recv_frame *recv_frame); +void rtw_recv_returnpacket(struct net_device *cnxt, struct sk_buff *retpkt); -extern void rtw_hostapd_mlme_rx(struct adapter *padapter, union recv_frame *precv_frame); -extern void rtw_handle_tkip_mic_err(struct adapter *padapter,u8 bgroup); +void rtw_hostapd_mlme_rx(struct adapter *padapter, union recv_frame *recv_fr); +void rtw_handle_tkip_mic_err(struct adapter *padapter, u8 bgroup); +int rtw_init_recv_priv(struct recv_priv *precvpriv, struct adapter *padapter); +void rtw_free_recv_priv(struct recv_priv *precvpriv); -int rtw_init_recv_priv(struct recv_priv *precvpriv, struct adapter *padapter); -void rtw_free_recv_priv (struct recv_priv *precvpriv); - - -int rtw_os_recv_resource_init(struct recv_priv *precvpriv, struct adapter *padapter); -int rtw_os_recv_resource_alloc(struct adapter *padapter, union recv_frame *precvframe); +int rtw_os_recv_resource_init(struct recv_priv *recvpr, struct adapter *adapt); +int rtw_os_recv_resource_alloc(struct adapter *adapt, union recv_frame *recvfr); void rtw_os_recv_resource_free(struct recv_priv *precvpriv); - -int rtw_os_recvbuf_resource_alloc(struct adapter *padapter, struct recv_buf *precvbuf); -int rtw_os_recvbuf_resource_free(struct adapter *padapter, struct recv_buf *precvbuf); +int rtw_os_recvbuf_resource_alloc(struct adapter *adapt, struct recv_buf *buf); +int rtw_os_recvbuf_resource_free(struct adapter *adapt, struct recv_buf *buf); void rtw_os_read_port(struct adapter *padapter, struct recv_buf *precvbuf); @@ -56,5 +53,4 @@ int _netdev_open(struct net_device *pnetdev); int netdev_open(struct net_device *pnetdev); static int netdev_close(struct net_device *pnetdev); - #endif /* */ diff --git a/include/rtl8188e_cmd.h b/include/rtl8188e_cmd.h index 938f757..1861099 100644 --- a/include/rtl8188e_cmd.h +++ b/include/rtl8188e_cmd.h @@ -22,46 +22,46 @@ enum RTL8188E_H2C_CMD_ID { /* Class Common */ - H2C_COM_RSVD_PAGE =0x00, - H2C_COM_MEDIA_STATUS_RPT =0x01, - H2C_COM_SCAN =0x02, - H2C_COM_KEEP_ALIVE =0x03, - H2C_COM_DISCNT_DECISION =0x04, + H2C_COM_RSVD_PAGE = 0x00, + H2C_COM_MEDIA_STATUS_RPT = 0x01, + H2C_COM_SCAN = 0x02, + H2C_COM_KEEP_ALIVE = 0x03, + H2C_COM_DISCNT_DECISION = 0x04, #ifndef CONFIG_WOWLAN - H2C_COM_WWLAN =0x05, + H2C_COM_WWLAN = 0x05, #endif - H2C_COM_INIT_OFFLOAD =0x06, - H2C_COM_REMOTE_WAKE_CTL =0x07, - H2C_COM_AP_OFFLOAD =0x08, - H2C_COM_BCN_RSVD_PAGE =0x09, - H2C_COM_PROB_RSP_RSVD_PAGE =0x0A, + H2C_COM_INIT_OFFLOAD = 0x06, + H2C_COM_REMOTE_WAKE_CTL = 0x07, + H2C_COM_AP_OFFLOAD = 0x08, + H2C_COM_BCN_RSVD_PAGE = 0x09, + H2C_COM_PROB_RSP_RSVD_PAGE = 0x0A, /* Class PS */ - H2C_PS_PWR_MODE =0x20, - H2C_PS_TUNE_PARA =0x21, - H2C_PS_TUNE_PARA_2 =0x22, - H2C_PS_LPS_PARA =0x23, - H2C_PS_P2P_OFFLOAD =0x24, + H2C_PS_PWR_MODE = 0x20, + H2C_PS_TUNE_PARA = 0x21, + H2C_PS_TUNE_PARA_2 = 0x22, + H2C_PS_LPS_PARA = 0x23, + H2C_PS_P2P_OFFLOAD = 0x24, /* Class DM */ - H2C_DM_MACID_CFG =0x40, - H2C_DM_TXBF =0x41, + H2C_DM_MACID_CFG = 0x40, + H2C_DM_TXBF = 0x41, /* Class BT */ - H2C_BT_COEX_MASK =0x60, - H2C_BT_COEX_GPIO_MODE =0x61, - H2C_BT_DAC_SWING_VAL =0x62, - H2C_BT_PSD_RST =0x63, + H2C_BT_COEX_MASK = 0x60, + H2C_BT_COEX_GPIO_MODE = 0x61, + H2C_BT_DAC_SWING_VAL = 0x62, + H2C_BT_PSD_RST = 0x63, /* Class Remote WakeUp */ #ifdef CONFIG_WOWLAN - H2C_COM_WWLAN =0x80, - H2C_COM_REMOTE_WAKE_CTRL =0x81, - H2C_COM_AOAC_GLOBAL_INFO =0x82, + H2C_COM_WWLAN = 0x80, + H2C_COM_REMOTE_WAKE_CTRL = 0x81, + H2C_COM_AOAC_GLOBAL_INFO = 0x82, #endif /* Class */ - H2C_RESET_TSF =0xc0, + H2C_RESET_TSF = 0xc0, }; struct cmd_msg_parm { @@ -70,22 +70,22 @@ struct cmd_msg_parm { u8 buf[6]; }; -enum{ +enum { PWRS }; struct setpwrmode_parm { u8 Mode;/* 0:Active,1:LPS,2:WMMPS */ - u8 SmartPS_RLBM;/* LPS=0:PS_Poll,1:PS_Poll,2:NullData,WMM=0:PS_Poll,1:NullData */ + u8 SmartPS_RLBM;/* LPS= 0:PS_Poll,1:PS_Poll,2:NullData,WMM= 0:PS_Poll,1:NullData */ u8 AwakeInterval; /* unit: beacon interval */ u8 bAllQueueUAPSD; u8 PwrState;/* AllON(0x0c),RFON(0x04),RFOFF(0x00) */ }; -struct H2C_SS_RFOFF_PARAM{ +struct H2C_SS_RFOFF_PARAM { u8 ROFOn; /* 1: on, 0:off */ u16 gpio_period; /* unit: 1024 us */ -}__attribute__ ((packed)); +} __packed; struct joinbssrpt_parm { u8 OpMode; /* RT_MEDIA_STATUS */ @@ -117,41 +117,39 @@ struct P2P_PS_CTWPeriod_t { u8 CTWPeriod; /* TU */ }; - /* host message to firmware cmd */ -void rtl8188e_set_FwPwrMode_cmd(struct adapter * padapter, u8 Mode); -void rtl8188e_set_FwJoinBssReport_cmd(struct adapter * padapter, u8 mstatus); -u8 rtl8188e_set_rssi_cmd(struct adapter * padapter, u8 *param); -u8 rtl8188e_set_raid_cmd(struct adapter * padapter, u32 mask); -void rtl8188e_Add_RateATid(struct adapter * padapter, u32 bitmap, u8 arg, u8 rssi_level); -/* u8 rtl8192c_set_FwSelectSuspend_cmd(struct adapter * padapter, u8 bfwpoll, u16 period); */ - +void rtl8188e_set_FwPwrMode_cmd(struct adapter *padapter, u8 Mode); +void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus); +u8 rtl8188e_set_rssi_cmd(struct adapter *padapter, u8 *param); +u8 rtl8188e_set_raid_cmd(struct adapter *padapter, u32 mask); +void rtl8188e_Add_RateATid(struct adapter *padapter, u32 bitmap, u8 arg, + u8 rssi_level); #ifdef CONFIG_P2P -void rtl8188e_set_p2p_ps_offload_cmd(struct adapter * padapter, u8 p2p_ps_state); +void rtl8188e_set_p2p_ps_offload_cmd(struct adapter *adapt, u8 p2p_ps_state); #endif /* CONFIG_P2P */ -void CheckFwRsvdPageContent(struct adapter * padapter); -void rtl8188e_set_FwMediaStatus_cmd(struct adapter * padapter, __le16 mstatus_rpt); +void CheckFwRsvdPageContent(struct adapter *adapt); +void rtl8188e_set_FwMediaStatus_cmd(struct adapter *adapt, __le16 mstatus_rpt); #ifdef CONFIG_WOWLAN struct setwowlan_parm { - u8 mode; - u8 gpio_index; - u8 gpio_duration; - u8 second_mode; - u8 reserve; + u8 mode; + u8 gpio_index; + u8 gpio_duration; + u8 second_mode; + u8 reserve; }; struct setaoac_glocal_info { - u8 pairwiseEncAlg; - u8 groupEncAlg; + u8 pairwiseEncAlg; + u8 groupEncAlg; }; -#define FW_WOWLAN_FUN_EN BIT(0) +#define FW_WOWLAN_FUN_EN BIT(0) #define FW_WOWLAN_PATTERN_MATCH BIT(1) -#define FW_WOWLAN_MAGIC_PKT BIT(2) -#define FW_WOWLAN_UNICAST BIT(3) +#define FW_WOWLAN_MAGIC_PKT BIT(2) +#define FW_WOWLAN_UNICAST BIT(3) #define FW_WOWLAN_ALL_PKT_DROP BIT(4) #define FW_WOWLAN_GPIO_ACTIVE BIT(5) #define FW_WOWLAN_REKEY_WAKEUP BIT(6) @@ -161,9 +159,9 @@ struct setaoac_glocal_info { #define FW_FW_PARSE_MAGIC_PKT BIT(1) #define FW_REMOTE_WAKE_CTRL_EN BIT(0) -#define FW_REALWOWLAN_EN BIT(5) -void rtl8188es_set_wowlan_cmd(struct adapter* padapter, u8 enable); -void SetFwRelatedForWoWLAN8188ES(struct adapter* padapter, u8 bHostIsGoingtoSleep); +#define FW_REALWOWLAN_EN BIT(5) +void rtl8188es_set_wowlan_cmd(struct adapter *adapt, u8 enable); +void SetFwRelatedForWoWLAN8188ES(struct adapter *adapt, u8 HostIsGoingtoSleep); #endif/* CONFIG_WOWLAN */ #endif/* __RTL8188E_CMD_H__ */ diff --git a/include/rtl8188e_dm.h b/include/rtl8188e_dm.h index 98bcadf..97a3175 100644 --- a/include/rtl8188e_dm.h +++ b/include/rtl8188e_dm.h @@ -29,8 +29,7 @@ enum{ #define IQK_BB_REG_NUM 9 #define HP_THERMAL_NUM 8 /* duplicate code,will move to ODM ######### */ -struct dm_priv -{ +struct dm_priv { u8 DM_Type; u8 DMFlag; u8 InitDMFlag; @@ -47,16 +46,17 @@ struct dm_priv /* for High Power */ u8 bDynamicTxPowerEnable; u8 LastDTPLvl; - u8 DynamicTxHighPowerLvl;/* Add by Jacken Tx Power Control for Near/Far Range */ + u8 DynamicTxHighPowerLvl;/* Tx Power Control for Near/Far Range */ u8 PowerIndex_backup[6]; }; -void rtl8188e_init_dm_priv(struct adapter * Adapter); -void rtl8188e_deinit_dm_priv(struct adapter * Adapter); -void rtl8188e_InitHalDm(struct adapter * Adapter); -void rtl8188e_HalDmWatchDog(struct adapter * Adapter); +void rtl8188e_init_dm_priv(struct adapter *adapt); +void rtl8188e_deinit_dm_priv(struct adapter *adapt); +void rtl8188e_InitHalDm(struct adapter *adapt); +void rtl8188e_HalDmWatchDog(struct adapter *adapt); -void AntDivCompare8188E(struct adapter * Adapter, struct wlan_bssid_ex *dst, struct wlan_bssid_ex *src); -u8 AntDivBeforeLink8188E(struct adapter * Adapter ); +void AntDivCompare8188E(struct adapter *adapt, struct wlan_bssid_ex *dst, + struct wlan_bssid_ex *src); +u8 AntDivBeforeLink8188E(struct adapter *adapt); #endif diff --git a/include/rtl8188e_hal.h b/include/rtl8188e_hal.h index 8369f9f..6d624b2 100644 --- a/include/rtl8188e_hal.h +++ b/include/rtl8188e_hal.h @@ -37,50 +37,48 @@ #include "odm_precomp.h" /* Fw Array */ - #define Rtl8188E_FwImageArray Rtl8188EFwImgArray - #define Rtl8188E_FWImgArrayLength Rtl8188EFWImgArrayLength + #define Rtl8188E_FwImageArray Rtl8188EFwImgArray + #define Rtl8188E_FWImgArrayLength Rtl8188EFWImgArrayLength #ifdef CONFIG_WOWLAN - #define Rtl8188E_FwWoWImageArray Array_8188E_FW_WoWLAN - #define Rtl8188E_FwWoWImgArrayLength ArrayLength_8188E_FW_WoWLAN + #define Rtl8188E_FwWoWImageArray Array_8188E_FW_WoWLAN + #define Rtl8188E_FwWoWImgArrayLength ArrayLength_8188E_FW_WoWLAN #endif /* CONFIG_WOWLAN */ -#define RTL8188E_FW_UMC_IMG "rtl8188E\\rtl8188efw.bin" -#define RTL8188E_PHY_REG "rtl8188E\\PHY_REG_1T.txt" -#define RTL8188E_PHY_RADIO_A "rtl8188E\\radio_a_1T.txt" -#define RTL8188E_PHY_RADIO_B "rtl8188E\\radio_b_1T.txt" -#define RTL8188E_AGC_TAB "rtl8188E\\AGC_TAB_1T.txt" -#define RTL8188E_PHY_MACREG "rtl8188E\\MAC_REG.txt" -#define RTL8188E_PHY_REG_PG "rtl8188E\\PHY_REG_PG.txt" -#define RTL8188E_PHY_REG_MP "rtl8188E\\PHY_REG_MP.txt" +#define RTL8188E_FW_UMC_IMG "rtl8188E\\rtl8188efw.bin" +#define RTL8188E_PHY_REG "rtl8188E\\PHY_REG_1T.txt" +#define RTL8188E_PHY_RADIO_A "rtl8188E\\radio_a_1T.txt" +#define RTL8188E_PHY_RADIO_B "rtl8188E\\radio_b_1T.txt" +#define RTL8188E_AGC_TAB "rtl8188E\\AGC_TAB_1T.txt" +#define RTL8188E_PHY_MACREG "rtl8188E\\MAC_REG.txt" +#define RTL8188E_PHY_REG_PG "rtl8188E\\PHY_REG_PG.txt" +#define RTL8188E_PHY_REG_MP "rtl8188E\\PHY_REG_MP.txt" -/* */ /* RTL8188E Power Configuration CMDs for USB/SDIO interfaces */ -/* */ -#define Rtl8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow -#define Rtl8188E_NIC_RF_OFF_FLOW rtl8188E_radio_off_flow -#define Rtl8188E_NIC_DISABLE_FLOW rtl8188E_card_disable_flow -#define Rtl8188E_NIC_ENABLE_FLOW rtl8188E_card_enable_flow -#define Rtl8188E_NIC_SUSPEND_FLOW rtl8188E_suspend_flow -#define Rtl8188E_NIC_RESUME_FLOW rtl8188E_resume_flow -#define Rtl8188E_NIC_PDN_FLOW rtl8188E_hwpdn_flow -#define Rtl8188E_NIC_LPS_ENTER_FLOW rtl8188E_enter_lps_flow -#define Rtl8188E_NIC_LPS_LEAVE_FLOW rtl8188E_leave_lps_flow +#define Rtl8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow +#define Rtl8188E_NIC_RF_OFF_FLOW rtl8188E_radio_off_flow +#define Rtl8188E_NIC_DISABLE_FLOW rtl8188E_card_disable_flow +#define Rtl8188E_NIC_ENABLE_FLOW rtl8188E_card_enable_flow +#define Rtl8188E_NIC_SUSPEND_FLOW rtl8188E_suspend_flow +#define Rtl8188E_NIC_RESUME_FLOW rtl8188E_resume_flow +#define Rtl8188E_NIC_PDN_FLOW rtl8188E_hwpdn_flow +#define Rtl8188E_NIC_LPS_ENTER_FLOW rtl8188E_enter_lps_flow +#define Rtl8188E_NIC_LPS_LEAVE_FLOW rtl8188E_leave_lps_flow #define DRVINFO_SZ 4 /* unit is 8bytes */ -#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0)) - +#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0)) /* download firmware related data structure */ -#define FW_8188E_SIZE 0x4000 /* 16384,16k */ -#define FW_8188E_START_ADDRESS 0x1000 +#define FW_8188E_SIZE 0x4000 /* 16384,16k */ +#define FW_8188E_START_ADDRESS 0x1000 #define FW_8188E_END_ADDRESS 0x1FFF /* 0x5FFF */ #define MAX_PAGE_SIZE 4096 /* @ page : 4k bytes */ -#define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\ - (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\ - (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300 ||\ - (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88E0) +#define IS_FW_HEADER_EXIST(_pFwHdr) \ + ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 || \ + (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 || \ + (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300 || \ + (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88E0) enum firmware_source { FW_SOURCE_IMG_FILE = 0, @@ -89,11 +87,11 @@ enum firmware_source { struct rt_firmware { enum firmware_source eFWSource; - u8* szFwBuffer; + u8 *szFwBuffer; u32 ulFwLength; #ifdef CONFIG_WOWLAN - u8* szWoWLANFwBuffer; + u8 *szWoWLANFwBuffer; u32 ulWoWLANFwLength; #endif /* CONFIG_WOWLAN */ }; @@ -102,16 +100,19 @@ struct rt_firmware { struct rt_firmware_hdr { /* 8-byte alinment required */ - /* LONG WORD 0 ---- */ - __le16 Signature; /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */ + __le16 Signature; /* 92C0: test chip; 92C, + * 88C0: test chip; 88C1: MP A-cut; + * 92C1: MP A-cut */ u8 Category; /* AP/NIC and USB/PCI */ - u8 Function; /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */ - __le16 Version; /* FW Version */ + u8 Function; /* Reserved for different FW function + * indcation, for further use when + * driver needs to download different + * FW for different conditions */ + __le16 Version; /* FW Version */ u8 Subversion; /* FW Subversion, default 0x00 */ u16 Rsvd1; - /* LONG WORD 1 ---- */ u8 Month; /* Release time Month field */ u8 Date; /* Release time Date field */ @@ -140,34 +141,38 @@ enum usb_rx_agg_mode { USB_RX_AGG_MIX }; -#define MAX_RX_DMA_BUFFER_SIZE_88E 0x2400 /* 9k for 88E nornal chip , MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) */ +#define MAX_RX_DMA_BUFFER_SIZE_88E \ + 0x2400 /* 9k for 88E nornal chip , MaxRxBuff=10k-max(TxReportSize(64*8), + * WOLPattern(16*24)) */ -#define MAX_TX_REPORT_BUFFER_SIZE 0x0400 /* 1k */ +#define MAX_TX_REPORT_BUFFER_SIZE 0x0400 /* 1k */ /* BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */ -#define MAX_TX_QUEUE 9 +#define MAX_TX_QUEUE 9 #define TX_SELE_HQ BIT(0) /* High Queue */ #define TX_SELE_LQ BIT(1) /* Low Queue */ #define TX_SELE_NQ BIT(2) /* Normal Queue */ -/* Note: We will divide number of page equally for each queue other than public queue! */ +/* Note: We will divide number of page equally for each queue other + * than public queue! */ /* 22k = 22528 bytes = 176 pages (@page = 128 bytes) */ /* must reserved about 7 pages for LPS => 176-7 = 169 (0xA9) */ -/* 2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS null-data */ +/* 2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS + * null-data */ #define TX_TOTAL_PAGE_NUMBER_88E 0xA9/* 169 (21632=> 21k) */ #define TX_PAGE_BOUNDARY_88E (TX_TOTAL_PAGE_NUMBER_88E + 1) /* Note: For Normal Chip Setting ,modify later */ -#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER TX_TOTAL_PAGE_NUMBER_88E /* 0xA9 , 0xb0=>176=>22k */ -#define WMM_NORMAL_TX_PAGE_BOUNDARY_88E (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1) /* 0xA9 */ +#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER \ + TX_TOTAL_PAGE_NUMBER_88E /* 0xA9 , 0xb0=>176=>22k */ +#define WMM_NORMAL_TX_PAGE_BOUNDARY_88E \ + (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1) /* 0xA9 */ -/* */ /* Chip specific */ -/* */ #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3) #define CHIP_BONDING_92C_1T2R 0x1 #define CHIP_BONDING_88C_USB_MCARD 0x2 @@ -175,11 +180,8 @@ enum usb_rx_agg_mode { #include "HalVerDef.h" #include "hal_com.h" -/* */ /* Channel Plan */ -/* */ -enum ChannelPlan -{ +enum ChannelPlan { CHPL_FCC = 0, CHPL_IC = 1, CHPL_ETSI = 2, @@ -204,20 +206,19 @@ struct txpowerinfo24g { }; #define EFUSE_REAL_CONTENT_LEN 512 -#define EFUSE_MAP_LEN 128 -#define EFUSE_MAX_SECTION 16 -#define EFUSE_IC_ID_OFFSET 506 /* For some inferiority IC purpose. added by Roger, 2009.09.02. */ +#define EFUSE_MAP_LEN 128 +#define EFUSE_MAX_SECTION 16 +#define EFUSE_IC_ID_OFFSET 506 /* For some inferior IC purpose*/ #define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN) -/* */ -/* */ /* To prevent out of boundary programming case, */ /* leave 1byte and program full section */ /* 9bytes + 1byt + 5bytes and pre 1byte. */ /* For worst case: */ /* | 1byte|----8bytes----|1byte|--5bytes--| */ /* | | Reserved(14bytes) | */ -/* */ -#define EFUSE_OOB_PROTECT_BYTES 15 /* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */ + +/* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */ +#define EFUSE_OOB_PROTECT_BYTES 15 #define HWSET_MAX_SIZE_88E 512 @@ -225,28 +226,26 @@ struct txpowerinfo24g { #define EFUSE_MAP_LEN_88E 512 #define EFUSE_MAX_SECTION_88E 64 #define EFUSE_MAX_WORD_UNIT_88E 4 -#define EFUSE_IC_ID_OFFSET_88E 506 /* For some inferiority IC purpose. added by Roger, 2009.09.02. */ -#define AVAILABLE_EFUSE_ADDR_88E(addr) (addr < EFUSE_REAL_CONTENT_LEN_88E) -/* To prevent out of boundary programming case, leave 1byte and program full section */ +#define EFUSE_IC_ID_OFFSET_88E 506 +#define AVAILABLE_EFUSE_ADDR_88E(addr) \ + (addr < EFUSE_REAL_CONTENT_LEN_88E) +/* To prevent out of boundary programming case, leave 1byte and program + * full section */ /* 9bytes + 1byt + 5bytes and pre 1byte. */ /* For worst case: */ /* | 2byte|----8bytes----|1byte|--7bytes--| 92D */ -#define EFUSE_OOB_PROTECT_BYTES_88E 18 /* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */ +/* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */ +#define EFUSE_OOB_PROTECT_BYTES_88E 18 #define EFUSE_PROTECT_BYTES_BANK_88E 16 - -/* */ /* EFUSE for BT definition */ -/* */ -#define EFUSE_BT_REAL_CONTENT_LEN 1536 /* 512*3 */ -#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */ -#define EFUSE_BT_MAX_SECTION 128 /* 1024/8 */ +#define EFUSE_BT_REAL_CONTENT_LEN 1536 /* 512*3 */ +#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */ +#define EFUSE_BT_MAX_SECTION 128 /* 1024/8 */ -#define EFUSE_PROTECT_BYTES_BANK 16 +#define EFUSE_PROTECT_BYTES_BANK 16 -/* */ -/* For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. */ -/* */ +/* For RTL8723 WiFi/BT/GPS multi-function configuration. */ enum rt_multi_func { RT_MULTI_FUNC_NONE = 0x00, RT_MULTI_FUNC_WIFI = 0x01, @@ -254,9 +253,7 @@ enum rt_multi_func { RT_MULTI_FUNC_GPS = 0x04, }; -/* */ -/* For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. */ -/* */ +/* For RTL8723 WiFi PDn/GPIO polarity control configuration. */ enum rt_polarity_ctl { RT_POLARITY_LOW_ACT = 0, RT_POLARITY_HIGH_ACT = 1, @@ -268,7 +265,6 @@ enum rt_regulator_mode { RT_LDO_REGULATOR = 1, }; - struct hal_data_8188e { struct HAL_VERSION VersionID; enum rt_multi_func MultiFunc; /* For multi-function consideration. */ @@ -297,9 +293,7 @@ struct hal_data_8188e { u8 BoardType; - /* */ /* EEPROM setting. */ - /* */ u16 EEPROMVID; u16 EEPROMPID; u16 EEPROMSVID; @@ -313,13 +307,11 @@ struct hal_data_8188e { u8 EEPROMThermalMeter; u8 bAPKThermalMeterIgnore; - bool EepromOrEfuse; - u8 EfuseMap[2][HWSET_MAX_SIZE_512]; /* 92C:256bytes, 88E:512bytes, we use union set (512bytes) */ - u8 EfuseUsedPercentage; - struct efuse_hal EfuseHal; - - /* u8 bIQKInitialized; */ - + bool EepromOrEfuse; + /* 92C:256bytes, 88E:512bytes, we use union set (512bytes) */ + u8 EfuseMap[2][HWSET_MAX_SIZE_512]; + u8 EfuseUsedPercentage; + struct efuse_hal EfuseHal; u8 Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; u8 Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; @@ -330,10 +322,14 @@ struct hal_data_8188e { s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; - u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; /* For HT 40MHZ pwr */ - u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; /* For HT 40MHZ pwr */ - u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];/* HT 20<->40 Pwr diff */ - u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];/* For HT<->legacy pwr diff */ + /* For HT 40MHZ pwr */ + u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; + /* For HT 40MHZ pwr */ + u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; + /* HT 20<->40 Pwr diff */ + u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; + /* For HT<->legacy pwr diff */ + u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; /* For power group */ u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; @@ -356,12 +352,12 @@ struct hal_data_8188e { u32 CCKTxPowerLevelOriginalOffset; u8 CrystalCap; - u32 AntennaTxPath; /* Antenna path Tx */ - u32 AntennaRxPath; /* Antenna path Rx */ + u32 AntennaTxPath; /* Antenna path Tx */ + u32 AntennaRxPath; /* Antenna path Rx */ u8 BluetoothCoexist; u8 ExternalPA; - u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */ + u8 bLedOpenDrain; /* Open-drain support for controlling the LED.*/ u8 b1x1RecvCombine; /* for 1T1R receive combining */ @@ -400,7 +396,8 @@ struct hal_data_8188e { u8 bDumpRxPkt;/* for debug */ u8 bDumpTxPkt;/* for debug */ - u8 FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. */ + u8 FwRsvdPageStartOffset; /* Reserve page start offset except + * beacon in TxQ. */ /* 2010/08/09 MH Add CU power down mode. */ bool pwrdown; @@ -411,11 +408,12 @@ struct hal_data_8188e { u8 OutEpQueueSel; u8 OutEpNumber; - /* 2010/12/10 MH Add for USB aggreation mode dynamic shceme. */ + /* Add for USB aggreation mode dynamic shceme. */ bool UsbRxHighSpeedMode; /* 2010/11/22 MH Add for slim combo debug mode selective. */ - /* This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock. */ + /* This is used for fix the drawback of CU TSMC-A/UMC-A cut. + * HW auto suspend ability. Close BT clock. */ bool SlimComboDbg; u16 EfuseUsedBytes; @@ -424,8 +422,9 @@ struct hal_data_8188e { struct P2P_PS_Offload_t p2p_ps_offload; #endif - /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */ - u8 bMacPwrCtrlOn; + /* Auto FSM to Turn On, include clock, isolation, power control + * for MAC only */ + u8 bMacPwrCtrlOn; u32 UsbBulkOutSize; @@ -435,67 +434,81 @@ struct hal_data_8188e { u8 C2hArray[16]; u8 UsbTxAggMode; u8 UsbTxAggDescNum; - u16 HwRxPageSize; /* Hardware setting */ + u16 HwRxPageSize; /* Hardware setting */ u32 MaxUsbRxAggBlock; enum usb_rx_agg_mode UsbRxAggMode; - u8 UsbRxAggBlockCount; /* USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed */ + u8 UsbRxAggBlockCount; /* USB Block count. Block size is + * 512-byte in high speed and 64-byte + * in full speed */ u8 UsbRxAggBlockTimeout; - u8 UsbRxAggPageCount; /* 8192C DMA page count */ + u8 UsbRxAggPageCount; /* 8192C DMA page count */ u8 UsbRxAggPageTimeout; }; -#define GET_HAL_DATA(__pAdapter) ((struct hal_data_8188e *)((__pAdapter)->HalData)) -#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type) +#define GET_HAL_DATA(__pAdapter) \ + ((struct hal_data_8188e *)((__pAdapter)->HalData)) +#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type) -#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT) -#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) +#define INCLUDE_MULTI_FUNC_BT(_Adapter) \ + (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT) +#define INCLUDE_MULTI_FUNC_GPS(_Adapter) \ + (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) /* rtl8188e_hal_init.c */ #ifdef CONFIG_WOWLAN -s32 rtl8188e_FirmwareDownload(struct adapter * padapter, bool bUsedWoWLANFw); +s32 rtl8188e_FirmwareDownload(struct adapter *padapter, bool bUsedWoWLANFw); #else -s32 rtl8188e_FirmwareDownload(struct adapter * padapter); +s32 rtl8188e_FirmwareDownload(struct adapter *padapter); #endif -void _8051Reset88E(struct adapter * padapter); -void rtl8188e_InitializeFirmwareVars(struct adapter * padapter); +void _8051Reset88E(struct adapter *padapter); +void rtl8188e_InitializeFirmwareVars(struct adapter *padapter); -s32 InitLLTTable(struct adapter * padapter, u8 txpktbuf_bndy); +s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy); /* EFuse */ -u8 GetEEPROMSize8188E(struct adapter * padapter); -void Hal_InitPGData88E(struct adapter * padapter); -void Hal_EfuseParseIDCode88E(struct adapter * padapter, u8 *hwinfo); -void Hal_ReadTxPowerInfo88E(struct adapter * padapter,u8* hwinfo,bool AutoLoadFail); +u8 GetEEPROMSize8188E(struct adapter *padapter); +void Hal_InitPGData88E(struct adapter *padapter); +void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo); +void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *hwinfo, + bool AutoLoadFail); -void Hal_EfuseParseEEPROMVer88E(struct adapter * padapter, u8 *hwinfo, bool AutoLoadFail); -void rtl8188e_EfuseParseChnlPlan(struct adapter * padapter, u8 *hwinfo, bool AutoLoadFail); -void Hal_EfuseParseCustomerID88E(struct adapter * padapter, u8 *hwinfo, bool AutoLoadFail); -void Hal_ReadAntennaDiversity88E (struct adapter * pAdapter,u8*PROMContent,bool AutoLoadFail); -void Hal_ReadThermalMeter_88E(struct adapter * Adapter,u8* PROMContent,bool AutoloadFail); -void Hal_EfuseParseXtal_8188E(struct adapter * pAdapter,u8* hwinfo,bool AutoLoadFail); -void Hal_EfuseParseBoardType88E(struct adapter * pAdapter,u8* hwinfo,bool AutoLoadFail); -void Hal_ReadPowerSavingMode88E(struct adapter * pAdapter,u8* hwinfo,bool AutoLoadFail); +void Hal_EfuseParseEEPROMVer88E(struct adapter *padapter, u8 *hwinfo, + bool AutoLoadFail); +void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo, + bool AutoLoadFail); +void Hal_EfuseParseCustomerID88E(struct adapter *padapter, u8 *hwinfo, + bool AutoLoadFail); +void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter,u8 *PROMContent, + bool AutoLoadFail); +void Hal_ReadThermalMeter_88E(struct adapter * dapter, u8 *PROMContent, + bool AutoloadFail); +void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo, + bool AutoLoadFail); +void Hal_EfuseParseBoardType88E(struct adapter *pAdapter, u8 *hwinfo, + bool AutoLoadFail); +void Hal_ReadPowerSavingMode88E(struct adapter *pAdapter, u8 *hwinfo, + bool AutoLoadFail); -bool HalDetectPwrDownMode88E(struct adapter * Adapter); +bool HalDetectPwrDownMode88E(struct adapter *Adapter); #ifdef CONFIG_WOWLAN -void Hal_DetectWoWMode(struct adapter * pAdapter); +void Hal_DetectWoWMode(struct adapter *pAdapter); #endif /* CONFIG_WOWLAN */ -void Hal_InitChannelPlan(struct adapter * padapter); +void Hal_InitChannelPlan(struct adapter *padapter); void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc); /* register */ -void SetBcnCtrlReg(struct adapter * padapter, u8 SetBits, u8 ClearBits); +void SetBcnCtrlReg(struct adapter *padapter, u8 SetBits, u8 ClearBits); -void rtl8188e_clone_haldata(struct adapter *dst_adapter, struct adapter *src_adapter); +void rtl8188e_clone_haldata(struct adapter *dst, struct adapter *src); void rtl8188e_start_thread(struct adapter *padapter); void rtl8188e_stop_thread(struct adapter *padapter); -void rtw_IOL_cmd_tx_pkt_buf_dump(struct adapter *Adapter,int data_len); -s32 rtl8188e_iol_efuse_patch(struct adapter * padapter); +void rtw_IOL_cmd_tx_pkt_buf_dump(struct adapter *Adapter, int len); +s32 rtl8188e_iol_efuse_patch(struct adapter *padapter); void rtw_cancel_all_timer(struct adapter *padapter); void _ps_open_RF(struct adapter *adapt); diff --git a/include/rtl8188e_led.h b/include/rtl8188e_led.h index 81a4e52..c0147e7 100644 --- a/include/rtl8188e_led.h +++ b/include/rtl8188e_led.h @@ -27,9 +27,9 @@ /* */ /* Interface to manipulate LED objects. */ /* */ -void rtl8188eu_InitSwLeds(struct adapter * padapter); -void rtl8188eu_DeInitSwLeds(struct adapter * padapter); -void SwLedOn(struct adapter *padapter, struct LED_871x * pLed); -void SwLedOff(struct adapter *padapter, struct LED_871x * pLed); +void rtl8188eu_InitSwLeds(struct adapter *padapter); +void rtl8188eu_DeInitSwLeds(struct adapter *padapter); +void SwLedOn(struct adapter *padapter, struct LED_871x *pLed); +void SwLedOff(struct adapter *padapter, struct LED_871x *pLed); #endif diff --git a/include/rtl8188e_recv.h b/include/rtl8188e_recv.h index e78e062..02ccb40 100644 --- a/include/rtl8188e_recv.h +++ b/include/rtl8188e_recv.h @@ -56,14 +56,14 @@ enum rx_packet_type { }; #define INTERRUPT_MSG_FORMAT_LEN 60 -void rtl8188eu_init_recvbuf(struct adapter *padapter, struct recv_buf *precvbuf); -s32 rtl8188eu_init_recv_priv(struct adapter * padapter); +void rtl8188eu_init_recvbuf(struct adapter *padapter, struct recv_buf *buf); +s32 rtl8188eu_init_recv_priv(struct adapter *padapter); void rtl8188eu_free_recv_priv(struct adapter * padapter); void rtl8188eu_recv_hdl(struct adapter * padapter, struct recv_buf *precvbuf); void rtl8188eu_recv_tasklet(void *priv); -void rtl8188e_query_rx_phy_status(union recv_frame *prframe, struct phy_stat *pphy_stat); +void rtl8188e_query_rx_phy_status(union recv_frame *fr, struct phy_stat *phy); void rtl8188e_process_phy_info(struct adapter * padapter, void *prframe); -void update_recvframe_phyinfo_88e(union recv_frame *precvframe,struct phy_stat *pphy_status); -void update_recvframe_attrib_88e( union recv_frame *precvframe, struct recv_stat *prxstat); +void update_recvframe_phyinfo_88e(union recv_frame *fra, struct phy_stat *phy); +void update_recvframe_attrib_88e(union recv_frame *fra, struct recv_stat *stat); #endif diff --git a/include/rtl8188e_rf.h b/include/rtl8188e_rf.h index cf1805d..10fc356 100644 --- a/include/rtl8188e_rf.h +++ b/include/rtl8188e_rf.h @@ -20,17 +20,17 @@ #ifndef __RTL8188E_RF_H__ #define __RTL8188E_RF_H__ -#define RF6052_MAX_TX_PWR 0x3F -#define RF6052_MAX_REG 0x3F -#define RF6052_MAX_PATH 2 +#define RF6052_MAX_TX_PWR 0x3F +#define RF6052_MAX_REG 0x3F +#define RF6052_MAX_PATH 2 int PHY_RF6052_Config8188E(struct adapter *Adapter); void rtl8188e_RF_ChangeTxPath(struct adapter *Adapter, u16 DataRate); void rtl8188e_PHY_RF6052SetBandwidth(struct adapter *Adapter, enum ht_channel_width Bandwidth); -void rtl8188e_PHY_RF6052SetCckTxPower(struct adapter *Adapter, u8 *pPowerlevel); -void rtl8188e_PHY_RF6052SetOFDMTxPower(struct adapter *Adapter, u8 *pwrofdm, +void rtl8188e_PHY_RF6052SetCckTxPower(struct adapter *Adapter, u8 *level); +void rtl8188e_PHY_RF6052SetOFDMTxPower(struct adapter *Adapter, u8 *ofdm, u8 *pwrbw20, u8 *pwrbw40, u8 channel); #endif/* __RTL8188E_RF_H__ */ diff --git a/include/rtl8188e_spec.h b/include/rtl8188e_spec.h index 7b37dde..ac70f4b 100644 --- a/include/rtl8188e_spec.h +++ b/include/rtl8188e_spec.h @@ -23,16 +23,16 @@ #define BIT(x) (1 << (x)) #endif -#define BIT0 0x00000001 -#define BIT1 0x00000002 -#define BIT2 0x00000004 -#define BIT3 0x00000008 -#define BIT4 0x00000010 -#define BIT5 0x00000020 -#define BIT6 0x00000040 -#define BIT7 0x00000080 -#define BIT8 0x00000100 -#define BIT9 0x00000200 +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 #define BIT10 0x00000400 #define BIT11 0x00000800 #define BIT12 0x00001000 @@ -56,281 +56,252 @@ #define BIT30 0x40000000 #define BIT31 0x80000000 -/* */ /* 8192C Regsiter offset definition */ -/* */ -#define HAL_PS_TIMER_INT_DELAY 50 /* 50 microseconds */ -#define HAL_92C_NAV_UPPER_UNIT 128 /* micro-second */ +#define HAL_PS_TIMER_INT_DELAY 50 /* 50 microseconds */ +#define HAL_92C_NAV_UPPER_UNIT 128 /* micro-second */ -#define MAC_ADDR_LEN 6 +#define MAC_ADDR_LEN 6 /* 8188E PKT_BUFF_ACCESS_CTRL value */ -#define TXPKT_BUF_SELECT 0x69 -#define RXPKT_BUF_SELECT 0xA5 +#define TXPKT_BUF_SELECT 0x69 +#define RXPKT_BUF_SELECT 0xA5 #define DISABLE_TRXPKT_BUF_ACCESS 0x0 -/* */ -/* */ -/* */ -/* */ -/* */ /* 0x0000h ~ 0x00FFh System Configuration */ -/* */ -/* */ -#define REG_SYS_ISO_CTRL 0x0000 -#define REG_SYS_FUNC_EN 0x0002 -#define REG_APS_FSMCO 0x0004 -#define REG_SYS_CLKR 0x0008 -#define REG_9346CR 0x000A -#define REG_EE_VPD 0x000C -#define REG_AFE_MISC 0x0010 -#define REG_SPS0_CTRL 0x0011 -#define REG_SPS_OCP_CFG 0x0018 -#define REG_RSV_CTRL 0x001C -#define REG_RF_CTRL 0x001F -#define REG_LDOA15_CTRL 0x0020 -#define REG_LDOV12D_CTRL 0x0021 -#define REG_LDOHCI12_CTRL 0x0022 -#define REG_LPLDO_CTRL 0x0023 -#define REG_AFE_XTAL_CTRL 0x0024 -#define REG_AFE_PLL_CTRL 0x0028 -#define REG_APE_PLL_CTRL_EXT 0x002c -#define REG_EFUSE_CTRL 0x0030 -#define REG_EFUSE_TEST 0x0034 -#define REG_GPIO_MUXCFG 0x0040 -#define REG_GPIO_IO_SEL 0x0042 -#define REG_MAC_PINMUX_CFG 0x0043 -#define REG_GPIO_PIN_CTRL 0x0044 -#define REG_GPIO_INTM 0x0048 -#define REG_LEDCFG0 0x004C -#define REG_LEDCFG1 0x004D -#define REG_LEDCFG2 0x004E -#define REG_LEDCFG3 0x004F -#define REG_FSIMR 0x0050 -#define REG_FSISR 0x0054 -#define REG_HSIMR 0x0058 -#define REG_HSISR 0x005c -#define REG_GPIO_PIN_CTRL_2 0x0060 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */ -#define REG_GPIO_IO_SEL_2 0x0062 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */ -#define REG_BB_PAD_CTRL 0x0064 -#define REG_MULTI_FUNC_CTRL 0x0068 /* RTL8723 WIFI/BT/GPS Multi-Function control source. */ -#define REG_GPIO_OUTPUT 0x006c -#define REG_AFE_XTAL_CTRL_EXT 0x0078 /* RTL8188E */ -#define REG_XCK_OUT_CTRL 0x007c /* RTL8188E */ -#define REG_MCUFWDL 0x0080 -#define REG_WOL_EVENT 0x0081 /* RTL8188E */ -#define REG_MCUTSTCFG 0x0084 -#define REG_HMEBOX_E0 0x0088 -#define REG_HMEBOX_E1 0x008A -#define REG_HMEBOX_E2 0x008C -#define REG_HMEBOX_E3 0x008E -#define REG_HMEBOX_EXT_0 0x01F0 -#define REG_HMEBOX_EXT_1 0x01F4 -#define REG_HMEBOX_EXT_2 0x01F8 -#define REG_HMEBOX_EXT_3 0x01FC -#define REG_HIMR_88E 0x00B0 -#define REG_HISR_88E 0x00B4 -#define REG_HIMRE_88E 0x00B8 -#define REG_HISRE_88E 0x00BC -#define REG_EFUSE_ACCESS 0x00CF /* Efuse access protection for RTL8723 */ -#define REG_BIST_SCAN 0x00D0 -#define REG_BIST_RPT 0x00D4 -#define REG_BIST_ROM_RPT 0x00D8 -#define REG_USB_SIE_INTF 0x00E0 -#define REG_PCIE_MIO_INTF 0x00E4 -#define REG_PCIE_MIO_INTD 0x00E8 -#define REG_HPON_FSM 0x00EC -#define REG_SYS_CFG 0x00F0 -#define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only. */ -#define REG_TYPE_ID 0x00FC +#define REG_SYS_ISO_CTRL 0x0000 +#define REG_SYS_FUNC_EN 0x0002 +#define REG_APS_FSMCO 0x0004 +#define REG_SYS_CLKR 0x0008 +#define REG_9346CR 0x000A +#define REG_EE_VPD 0x000C +#define REG_AFE_MISC 0x0010 +#define REG_SPS0_CTRL 0x0011 +#define REG_SPS_OCP_CFG 0x0018 +#define REG_RSV_CTRL 0x001C +#define REG_RF_CTRL 0x001F +#define REG_LDOA15_CTRL 0x0020 +#define REG_LDOV12D_CTRL 0x0021 +#define REG_LDOHCI12_CTRL 0x0022 +#define REG_LPLDO_CTRL 0x0023 +#define REG_AFE_XTAL_CTRL 0x0024 +#define REG_AFE_PLL_CTRL 0x0028 +#define REG_APE_PLL_CTRL_EXT 0x002c +#define REG_EFUSE_CTRL 0x0030 +#define REG_EFUSE_TEST 0x0034 +#define REG_GPIO_MUXCFG 0x0040 +#define REG_GPIO_IO_SEL 0x0042 +#define REG_MAC_PINMUX_CFG 0x0043 +#define REG_GPIO_PIN_CTRL 0x0044 +#define REG_GPIO_INTM 0x0048 +#define REG_LEDCFG0 0x004C +#define REG_LEDCFG1 0x004D +#define REG_LEDCFG2 0x004E +#define REG_LEDCFG3 0x004F +#define REG_FSIMR 0x0050 +#define REG_FSISR 0x0054 +#define REG_HSIMR 0x0058 +#define REG_HSISR 0x005c +#define REG_GPIO_PIN_CTRL_2 0x0060 /* RTL8723 WIFI/BT/GPS + * Multi-Function GPIO Pin Control. */ +#define REG_GPIO_IO_SEL_2 0x0062 /* RTL8723 WIFI/BT/GPS + * Multi-Function GPIO Select. */ +#define REG_BB_PAD_CTRL 0x0064 +#define REG_MULTI_FUNC_CTRL 0x0068 /* RTL8723 WIFI/BT/GPS + * Multi-Function control source. */ +#define REG_GPIO_OUTPUT 0x006c +#define REG_AFE_XTAL_CTRL_EXT 0x0078 /* RTL8188E */ +#define REG_XCK_OUT_CTRL 0x007c /* RTL8188E */ +#define REG_MCUFWDL 0x0080 +#define REG_WOL_EVENT 0x0081 /* RTL8188E */ +#define REG_MCUTSTCFG 0x0084 +#define REG_HMEBOX_E0 0x0088 +#define REG_HMEBOX_E1 0x008A +#define REG_HMEBOX_E2 0x008C +#define REG_HMEBOX_E3 0x008E +#define REG_HMEBOX_EXT_0 0x01F0 +#define REG_HMEBOX_EXT_1 0x01F4 +#define REG_HMEBOX_EXT_2 0x01F8 +#define REG_HMEBOX_EXT_3 0x01FC +#define REG_HIMR_88E 0x00B0 +#define REG_HISR_88E 0x00B4 +#define REG_HIMRE_88E 0x00B8 +#define REG_HISRE_88E 0x00BC +#define REG_EFUSE_ACCESS 0x00CF /* Efuse access protection + * for RTL8723 */ +#define REG_BIST_SCAN 0x00D0 +#define REG_BIST_RPT 0x00D4 +#define REG_BIST_ROM_RPT 0x00D8 +#define REG_USB_SIE_INTF 0x00E0 +#define REG_PCIE_MIO_INTF 0x00E4 +#define REG_PCIE_MIO_INTD 0x00E8 +#define REG_HPON_FSM 0x00EC +#define REG_SYS_CFG 0x00F0 +#define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only. */ +#define REG_TYPE_ID 0x00FC #define REG_MAC_PHY_CTRL_NORMAL 0x00f8 -/* */ -/* */ /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ -/* */ -/* */ -#define REG_CR 0x0100 -#define REG_PBP 0x0104 +#define REG_CR 0x0100 +#define REG_PBP 0x0104 #define REG_PKT_BUFF_ACCESS_CTRL 0x0106 -#define REG_TRXDMA_CTRL 0x010C -#define REG_TRXFF_BNDY 0x0114 -#define REG_TRXFF_STATUS 0x0118 -#define REG_RXFF_PTR 0x011C -/* define REG_HIMR 0x0120 */ -/* define REG_HISR 0x0124 */ -#define REG_HIMRE 0x0128 -#define REG_HISRE 0x012C -#define REG_CPWM 0x012F -#define REG_FWIMR 0x0130 -#define REG_FTIMR 0x0138 -#define REG_FWISR 0x0134 -#define REG_PKTBUF_DBG_CTRL 0x0140 -#define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL) -#define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2) -#define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3) -#define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2) -#define REG_PKTBUF_DBG_DATA_L 0x0144 +#define REG_TRXDMA_CTRL 0x010C +#define REG_TRXFF_BNDY 0x0114 +#define REG_TRXFF_STATUS 0x0118 +#define REG_RXFF_PTR 0x011C +/* define REG_HIMR 0x0120 */ +/* define REG_HISR 0x0124 */ +#define REG_HIMRE 0x0128 +#define REG_HISRE 0x012C +#define REG_CPWM 0x012F +#define REG_FWIMR 0x0130 +#define REG_FTIMR 0x0138 +#define REG_FWISR 0x0134 +#define REG_PKTBUF_DBG_CTRL 0x0140 +#define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL) +#define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2) +#define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3) +#define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2) +#define REG_PKTBUF_DBG_DATA_L 0x0144 #define REG_PKTBUF_DBG_DATA_H 0x0148 -#define REG_TC0_CTRL 0x0150 -#define REG_TC1_CTRL 0x0154 -#define REG_TC2_CTRL 0x0158 -#define REG_TC3_CTRL 0x015C -#define REG_TC4_CTRL 0x0160 -#define REG_TCUNIT_BASE 0x0164 -#define REG_MBIST_START 0x0174 -#define REG_MBIST_DONE 0x0178 -#define REG_MBIST_FAIL 0x017C -#define REG_32K_CTRL 0x0194 /* RTL8188E */ +#define REG_TC0_CTRL 0x0150 +#define REG_TC1_CTRL 0x0154 +#define REG_TC2_CTRL 0x0158 +#define REG_TC3_CTRL 0x015C +#define REG_TC4_CTRL 0x0160 +#define REG_TCUNIT_BASE 0x0164 +#define REG_MBIST_START 0x0174 +#define REG_MBIST_DONE 0x0178 +#define REG_MBIST_FAIL 0x017C +#define REG_32K_CTRL 0x0194 /* RTL8188E */ #define REG_C2HEVT_MSG_NORMAL 0x01A0 -#define REG_C2HEVT_CLEAR 0x01AF -#define REG_MCUTST_1 0x01c0 +#define REG_C2HEVT_CLEAR 0x01AF +#define REG_MCUTST_1 0x01c0 #ifdef CONFIG_WOWLAN -#define REG_WOWLAN_WAKE_REASON 0x01c7 +#define REG_WOWLAN_WAKE_REASON 0x01c7 #endif -#define REG_FMETHR 0x01C8 -#define REG_HMETFR 0x01CC -#define REG_HMEBOX_0 0x01D0 -#define REG_HMEBOX_1 0x01D4 -#define REG_HMEBOX_2 0x01D8 -#define REG_HMEBOX_3 0x01DC +#define REG_FMETHR 0x01C8 +#define REG_HMETFR 0x01CC +#define REG_HMEBOX_0 0x01D0 +#define REG_HMEBOX_1 0x01D4 +#define REG_HMEBOX_2 0x01D8 +#define REG_HMEBOX_3 0x01DC -#define REG_LLT_INIT 0x01E0 +#define REG_LLT_INIT 0x01E0 - -/* */ -/* */ /* 0x0200h ~ 0x027Fh TXDMA Configuration */ -/* */ -/* */ -#define REG_RQPN 0x0200 -#define REG_FIFOPAGE 0x0204 -#define REG_TDECTRL 0x0208 -#define REG_TXDMA_OFFSET_CHK 0x020C -#define REG_TXDMA_STATUS 0x0210 -#define REG_RQPN_NPQ 0x0214 +#define REG_RQPN 0x0200 +#define REG_FIFOPAGE 0x0204 +#define REG_TDECTRL 0x0208 +#define REG_TXDMA_OFFSET_CHK 0x020C +#define REG_TXDMA_STATUS 0x0210 +#define REG_RQPN_NPQ 0x0214 -/* */ -/* */ /* 0x0280h ~ 0x02FFh RXDMA Configuration */ -/* */ -/* */ -#define REG_RXDMA_AGG_PG_TH 0x0280 -#define REG_RXPKT_NUM 0x0284 -#define REG_RXDMA_STATUS 0x0288 +#define REG_RXDMA_AGG_PG_TH 0x0280 +#define REG_RXPKT_NUM 0x0284 +#define REG_RXDMA_STATUS 0x0288 -/* */ -/* */ /* 0x0300h ~ 0x03FFh PCIe */ -/* */ -/* */ -#define REG_PCIE_CTRL_REG 0x0300 -#define REG_INT_MIG 0x0304 /* Interrupt Migration */ -#define REG_BCNQ_DESA 0x0308 /* TX Beacon Descriptor Address */ -#define REG_HQ_DESA 0x0310 /* TX High Queue Descriptor Address */ -#define REG_MGQ_DESA 0x0318 /* TX Manage Queue Descriptor Address */ -#define REG_VOQ_DESA 0x0320 /* TX VO Queue Descriptor Address */ -#define REG_VIQ_DESA 0x0328 /* TX VI Queue Descriptor Address */ -#define REG_BEQ_DESA 0x0330 /* TX BE Queue Descriptor Address */ -#define REG_BKQ_DESA 0x0338 /* TX BK Queue Descriptor Address */ -#define REG_RX_DESA 0x0340 /* RX Queue Descriptor Address */ -#define REG_MDIO 0x0354 /* MDIO for Access PCIE PHY */ -#define REG_DBG_SEL 0x0360 /* Debug Selection Register */ -#define REG_PCIE_HRPWM 0x0361 /* PCIe RPWM */ -#define REG_PCIE_HCPWM 0x0363 /* PCIe CPWM */ -#define REG_WATCH_DOG 0x0368 +#define REG_PCIE_CTRL_REG 0x0300 +#define REG_INT_MIG 0x0304 /* Interrupt Migration */ +#define REG_BCNQ_DESA 0x0308 /* TX Beacon Descr Address */ +#define REG_HQ_DESA 0x0310 /* TX High Queue Descr Addr */ +#define REG_MGQ_DESA 0x0318 /* TX Manage Queue Descr Addr*/ +#define REG_VOQ_DESA 0x0320 /* TX VO Queue Descr Addr */ +#define REG_VIQ_DESA 0x0328 /* TX VI Queue Descr Addr */ +#define REG_BEQ_DESA 0x0330 /* TX BE Queue Descr Addr */ +#define REG_BKQ_DESA 0x0338 /* TX BK Queue Descr Addr */ +#define REG_RX_DESA 0x0340 /* RX Queue Descr Addr */ +#define REG_MDIO 0x0354 /* MDIO for Access PCIE PHY */ +#define REG_DBG_SEL 0x0360 /* Debug Selection Register */ +#define REG_PCIE_HRPWM 0x0361 /* PCIe RPWM */ +#define REG_PCIE_HCPWM 0x0363 /* PCIe CPWM */ +#define REG_WATCH_DOG 0x0368 -/* RTL8723 series ------------------------------- */ -#define REG_PCIE_HISR 0x03A0 +/* RTL8723 series ------------------------------ */ +#define REG_PCIE_HISR 0x03A0 /* spec version 11 */ -/* */ -/* */ /* 0x0400h ~ 0x047Fh Protocol Configuration */ -/* */ -/* */ -#define REG_VOQ_INFORMATION 0x0400 -#define REG_VIQ_INFORMATION 0x0404 -#define REG_BEQ_INFORMATION 0x0408 -#define REG_BKQ_INFORMATION 0x040C -#define REG_MGQ_INFORMATION 0x0410 -#define REG_HGQ_INFORMATION 0x0414 -#define REG_BCNQ_INFORMATION 0x0418 -#define REG_TXPKT_EMPTY 0x041A +#define REG_VOQ_INFORMATION 0x0400 +#define REG_VIQ_INFORMATION 0x0404 +#define REG_BEQ_INFORMATION 0x0408 +#define REG_BKQ_INFORMATION 0x040C +#define REG_MGQ_INFORMATION 0x0410 +#define REG_HGQ_INFORMATION 0x0414 +#define REG_BCNQ_INFORMATION 0x0418 +#define REG_TXPKT_EMPTY 0x041A #define REG_CPU_MGQ_INFORMATION 0x041C -#define REG_FWHW_TXQ_CTRL 0x0420 -#define REG_HWSEQ_CTRL 0x0423 +#define REG_FWHW_TXQ_CTRL 0x0420 +#define REG_HWSEQ_CTRL 0x0423 #define REG_TXPKTBUF_BCNQ_BDNY 0x0424 #define REG_TXPKTBUF_MGQ_BDNY 0x0425 -#define REG_LIFETIME_EN 0x0426 -#define REG_MULTI_BCNQ_OFFSET 0x0427 -#define REG_SPEC_SIFS 0x0428 -#define REG_RL 0x042A -#define REG_DARFRC 0x0430 -#define REG_RARFRC 0x0438 -#define REG_RRSR 0x0440 -#define REG_ARFR0 0x0444 -#define REG_ARFR1 0x0448 -#define REG_ARFR2 0x044C -#define REG_ARFR3 0x0450 -#define REG_AGGLEN_LMT 0x0458 -#define REG_AMPDU_MIN_SPACE 0x045C +#define REG_LIFETIME_EN 0x0426 +#define REG_MULTI_BCNQ_OFFSET 0x0427 +#define REG_SPEC_SIFS 0x0428 +#define REG_RL 0x042A +#define REG_DARFRC 0x0430 +#define REG_RARFRC 0x0438 +#define REG_RRSR 0x0440 +#define REG_ARFR0 0x0444 +#define REG_ARFR1 0x0448 +#define REG_ARFR2 0x044C +#define REG_ARFR3 0x0450 +#define REG_AGGLEN_LMT 0x0458 +#define REG_AMPDU_MIN_SPACE 0x045C #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D -#define REG_FAST_EDCA_CTRL 0x0460 -#define REG_RD_RESP_PKT_TH 0x0463 -#define REG_INIRTS_RATE_SEL 0x0480 -/* define REG_INIDATA_RATE_SEL 0x0484 */ -#define REG_POWER_STATUS 0x04A4 -#define REG_POWER_STAGE1 0x04B4 -#define REG_POWER_STAGE2 0x04B8 -#define REG_PKT_VO_VI_LIFE_TIME 0x04C0 -#define REG_PKT_BE_BK_LIFE_TIME 0x04C2 -#define REG_STBC_SETTING 0x04C4 -#define REG_PROT_MODE_CTRL 0x04C8 -#define REG_MAX_AGGR_NUM 0x04CA +#define REG_FAST_EDCA_CTRL 0x0460 +#define REG_RD_RESP_PKT_TH 0x0463 +#define REG_INIRTS_RATE_SEL 0x0480 +/* define REG_INIDATA_RATE_SEL 0x0484 */ +#define REG_POWER_STATUS 0x04A4 +#define REG_POWER_STAGE1 0x04B4 +#define REG_POWER_STAGE2 0x04B8 +#define REG_PKT_VO_VI_LIFE_TIME 0x04C0 +#define REG_PKT_BE_BK_LIFE_TIME 0x04C2 +#define REG_STBC_SETTING 0x04C4 +#define REG_PROT_MODE_CTRL 0x04C8 +#define REG_MAX_AGGR_NUM 0x04CA #define REG_RTS_MAX_AGGR_NUM 0x04CB -#define REG_BAR_MODE_CTRL 0x04CC +#define REG_BAR_MODE_CTRL 0x04CC #define REG_RA_TRY_RATE_AGG_LMT 0x04CF #define REG_EARLY_MODE_CONTROL 0x4D0 -#define REG_NQOS_SEQ 0x04DC -#define REG_QOS_SEQ 0x04DE -#define REG_NEED_CPU_HANDLE 0x04E0 -#define REG_PKT_LOSE_RPT 0x04E1 -#define REG_PTCL_ERR_STATUS 0x04E2 -#define REG_TX_RPT_CTRL 0x04EC -#define REG_TX_RPT_TIME 0x04F0 /* 2 byte */ -#define REG_DUMMY 0x04FC +#define REG_NQOS_SEQ 0x04DC +#define REG_QOS_SEQ 0x04DE +#define REG_NEED_CPU_HANDLE 0x04E0 +#define REG_PKT_LOSE_RPT 0x04E1 +#define REG_PTCL_ERR_STATUS 0x04E2 +#define REG_TX_RPT_CTRL 0x04EC +#define REG_TX_RPT_TIME 0x04F0 /* 2 byte */ +#define REG_DUMMY 0x04FC -/* */ -/* */ /* 0x0500h ~ 0x05FFh EDCA Configuration */ -/* */ -/* */ -#define REG_EDCA_VO_PARAM 0x0500 -#define REG_EDCA_VI_PARAM 0x0504 -#define REG_EDCA_BE_PARAM 0x0508 -#define REG_EDCA_BK_PARAM 0x050C -#define REG_BCNTCFG 0x0510 -#define REG_PIFS 0x0512 -#define REG_RDG_PIFS 0x0513 -#define REG_SIFS_CTX 0x0514 -#define REG_SIFS_TRX 0x0516 -#define REG_TSFTR_SYN_OFFSET 0x0518 -#define REG_AGGR_BREAK_TIME 0x051A -#define REG_SLOT 0x051B -#define REG_TX_PTCL_CTRL 0x0520 -#define REG_TXPAUSE 0x0522 -#define REG_DIS_TXREQ_CLR 0x0523 -#define REG_RD_CTRL 0x0524 -/* */ +#define REG_EDCA_VO_PARAM 0x0500 +#define REG_EDCA_VI_PARAM 0x0504 +#define REG_EDCA_BE_PARAM 0x0508 +#define REG_EDCA_BK_PARAM 0x050C +#define REG_BCNTCFG 0x0510 +#define REG_PIFS 0x0512 +#define REG_RDG_PIFS 0x0513 +#define REG_SIFS_CTX 0x0514 +#define REG_SIFS_TRX 0x0516 +#define REG_TSFTR_SYN_OFFSET 0x0518 +#define REG_AGGR_BREAK_TIME 0x051A +#define REG_SLOT 0x051B +#define REG_TX_PTCL_CTRL 0x0520 +#define REG_TXPAUSE 0x0522 +#define REG_DIS_TXREQ_CLR 0x0523 +#define REG_RD_CTRL 0x0524 /* Format for offset 540h-542h: */ -/* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. */ +/* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting + * beacon content before TBTT. */ /* [7:4]: Reserved. */ -/* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. */ +/* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding + * to send the beacon packet. */ /* [23:20]: Reserved */ /* Description: */ /* | */ @@ -338,240 +309,218 @@ /* --------------|---------------------- */ /* | */ /* TBTT */ -/* Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. */ -/* Described by Designer Tim and Bruce, 2011-01-14. */ -/* */ -#define REG_TBTT_PROHIBIT 0x0540 -#define REG_RD_NAV_NXT 0x0544 -#define REG_NAV_PROT_LEN 0x0546 -#define REG_BCN_CTRL 0x0550 -#define REG_BCN_CTRL_1 0x0551 -#define REG_MBID_NUM 0x0552 -#define REG_DUAL_TSF_RST 0x0553 -#define REG_BCN_INTERVAL 0x0554 /* The same as REG_MBSSID_BCN_SPACE */ -#define REG_DRVERLYINT 0x0558 -#define REG_BCNDMATIM 0x0559 -#define REG_ATIMWND 0x055A -#define REG_BCN_MAX_ERR 0x055D -#define REG_RXTSF_OFFSET_CCK 0x055E -#define REG_RXTSF_OFFSET_OFDM 0x055F -#define REG_TSFTR 0x0560 -#define REG_TSFTR1 0x0568 -#define REG_ATIMWND_1 0x0570 -#define REG_PSTIMER 0x0580 -#define REG_TIMER0 0x0584 -#define REG_TIMER1 0x0588 -#define REG_ACMHWCTRL 0x05C0 +/* Note: We cannot update beacon content to HW or send any AC packets during + * the time between Setup and Hold. */ +#define REG_TBTT_PROHIBIT 0x0540 +#define REG_RD_NAV_NXT 0x0544 +#define REG_NAV_PROT_LEN 0x0546 +#define REG_BCN_CTRL 0x0550 +#define REG_BCN_CTRL_1 0x0551 +#define REG_MBID_NUM 0x0552 +#define REG_DUAL_TSF_RST 0x0553 +#define REG_BCN_INTERVAL 0x0554 +#define REG_DRVERLYINT 0x0558 +#define REG_BCNDMATIM 0x0559 +#define REG_ATIMWND 0x055A +#define REG_BCN_MAX_ERR 0x055D +#define REG_RXTSF_OFFSET_CCK 0x055E +#define REG_RXTSF_OFFSET_OFDM 0x055F +#define REG_TSFTR 0x0560 +#define REG_TSFTR1 0x0568 +#define REG_ATIMWND_1 0x0570 +#define REG_PSTIMER 0x0580 +#define REG_TIMER0 0x0584 +#define REG_TIMER1 0x0588 +#define REG_ACMHWCTRL 0x05C0 -/* define REG_FW_TSF_SYNC_CNT 0x04A0 */ -#define REG_FW_RESET_TSF_CNT_1 0x05FC -#define REG_FW_RESET_TSF_CNT_0 0x05FD -#define REG_FW_BCN_DIS_CNT 0x05FE +/* define REG_FW_TSF_SYNC_CNT 0x04A0 */ +#define REG_FW_RESET_TSF_CNT_1 0x05FC +#define REG_FW_RESET_TSF_CNT_0 0x05FD +#define REG_FW_BCN_DIS_CNT 0x05FE -/* */ -/* */ /* 0x0600h ~ 0x07FFh WMAC Configuration */ -/* */ -/* */ -#define REG_APSD_CTRL 0x0600 -#define REG_BWOPMODE 0x0603 -#define REG_TCR 0x0604 -#define REG_RCR 0x0608 -#define REG_RX_PKT_LIMIT 0x060C -#define REG_RX_DLK_TIME 0x060D -#define REG_RX_DRVINFO_SZ 0x060F +#define REG_APSD_CTRL 0x0600 +#define REG_BWOPMODE 0x0603 +#define REG_TCR 0x0604 +#define REG_RCR 0x0608 +#define REG_RX_PKT_LIMIT 0x060C +#define REG_RX_DLK_TIME 0x060D +#define REG_RX_DRVINFO_SZ 0x060F -#define REG_MACID 0x0610 -#define REG_BSSID 0x0618 -#define REG_MAR 0x0620 -#define REG_MBIDCAMCFG 0x0628 +#define REG_MACID 0x0610 +#define REG_BSSID 0x0618 +#define REG_MAR 0x0620 +#define REG_MBIDCAMCFG 0x0628 -#define REG_USTIME_EDCA 0x0638 -#define REG_MAC_SPEC_SIFS 0x063A +#define REG_USTIME_EDCA 0x0638 +#define REG_MAC_SPEC_SIFS 0x063A /* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ -#define REG_R2T_SIFS 0x063C /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ -#define REG_T2T_SIFS 0x063E /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ -#define REG_ACKTO 0x0640 -#define REG_CTS2TO 0x0641 -#define REG_EIFS 0x0642 - +/* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ +#define REG_R2T_SIFS 0x063C +/* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ +#define REG_T2T_SIFS 0x063E +#define REG_ACKTO 0x0640 +#define REG_CTS2TO 0x0641 +#define REG_EIFS 0x0642 /* RXERR_RPT */ -#define RXERR_TYPE_OFDM_PPDU 0 +#define RXERR_TYPE_OFDM_PPDU 0 #define RXERR_TYPE_OFDM_false_ALARM 1 -#define RXERR_TYPE_OFDM_MPDU_OK 2 -#define RXERR_TYPE_OFDM_MPDU_FAIL 3 -#define RXERR_TYPE_CCK_PPDU 4 -#define RXERR_TYPE_CCK_false_ALARM 5 -#define RXERR_TYPE_CCK_MPDU_OK 6 -#define RXERR_TYPE_CCK_MPDU_FAIL 7 -#define RXERR_TYPE_HT_PPDU 8 -#define RXERR_TYPE_HT_false_ALARM 9 -#define RXERR_TYPE_HT_MPDU_TOTAL 10 -#define RXERR_TYPE_HT_MPDU_OK 11 -#define RXERR_TYPE_HT_MPDU_FAIL 12 -#define RXERR_TYPE_RX_FULL_DROP 15 +#define RXERR_TYPE_OFDM_MPDU_OK 2 +#define RXERR_TYPE_OFDM_MPDU_FAIL 3 +#define RXERR_TYPE_CCK_PPDU 4 +#define RXERR_TYPE_CCK_false_ALARM 5 +#define RXERR_TYPE_CCK_MPDU_OK 6 +#define RXERR_TYPE_CCK_MPDU_FAIL 7 +#define RXERR_TYPE_HT_PPDU 8 +#define RXERR_TYPE_HT_false_ALARM 9 +#define RXERR_TYPE_HT_MPDU_TOTAL 10 +#define RXERR_TYPE_HT_MPDU_OK 11 +#define RXERR_TYPE_HT_MPDU_FAIL 12 +#define RXERR_TYPE_RX_FULL_DROP 15 -#define RXERR_COUNTER_MASK 0xFFFFF -#define RXERR_RPT_RST BIT(27) -#define _RXERR_RPT_SEL(type) ((type) << 28) +#define RXERR_COUNTER_MASK 0xFFFFF +#define RXERR_RPT_RST BIT(27) +#define _RXERR_RPT_SEL(type) ((type) << 28) - -/* */ /* Note: */ -/* The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. The default value is */ -/* always too small, but the WiFi TestPlan test by 25,000 microseconds of NAV through sending */ -/* CTS in the air. We must update this value greater than 25,000 microseconds to pass the item. */ -/* The offset of NAV_UPPER in 8192C Spec is incorrect, and the offset should be 0x0652. Commented */ -/* by SD1 Scott. */ -/* By Bruce, 2011-07-18. */ -/* */ +/* The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. + * The default value is always too small, but the WiFi TestPlan test + * by 25,000 microseconds of NAV through sending CTS in the air. + * We must update this value greater than 25,000 microseconds to pass + * the item. The offset of NAV_UPPER in 8192C Spec is incorrect, and + * the offset should be 0x0652. */ #define REG_NAV_UPPER 0x0652 /* unit of 128 */ /* WMA, BA, CCX */ -/* define REG_NAV_CTRL 0x0650 */ -#define REG_BACAMCMD 0x0654 -#define REG_BACAMCONTENT 0x0658 -#define REG_LBDLY 0x0660 -#define REG_FWDLY 0x0661 -#define REG_RXERR_RPT 0x0664 +/* define REG_NAV_CTRL 0x0650 */ +#define REG_BACAMCMD 0x0654 +#define REG_BACAMCONTENT 0x0658 +#define REG_LBDLY 0x0660 +#define REG_FWDLY 0x0661 +#define REG_RXERR_RPT 0x0664 #define REG_WMAC_TRXPTCL_CTL 0x0668 /* Security */ -#define REG_CAMCMD 0x0670 -#define REG_CAMWRITE 0x0674 -#define REG_CAMREAD 0x0678 -#define REG_CAMDBG 0x067C -#define REG_SECCFG 0x0680 +#define REG_CAMCMD 0x0670 +#define REG_CAMWRITE 0x0674 +#define REG_CAMREAD 0x0678 +#define REG_CAMDBG 0x067C +#define REG_SECCFG 0x0680 /* Power */ -#define REG_WOW_CTRL 0x0690 -#define REG_PS_RX_INFO 0x0692 -#define REG_UAPSD_TID 0x0693 +#define REG_WOW_CTRL 0x0690 +#define REG_PS_RX_INFO 0x0692 +#define REG_UAPSD_TID 0x0693 #define REG_WKFMCAM_CMD 0x0698 -#define REG_WKFMCAM_NUM_88E 0x698 -#define REG_RXFLTMAP0 0x06A0 -#define REG_RXFLTMAP1 0x06A2 -#define REG_RXFLTMAP2 0x06A4 -#define REG_BCN_PSR_RPT 0x06A8 -#define REG_BT_COEX_TABLE 0x06C0 - +#define REG_WKFMCAM_NUM_88E 0x698 +#define REG_RXFLTMAP0 0x06A0 +#define REG_RXFLTMAP1 0x06A2 +#define REG_RXFLTMAP2 0x06A4 +#define REG_BCN_PSR_RPT 0x06A8 +#define REG_BT_COEX_TABLE 0x06C0 /* Hardware Port 2 */ -#define REG_MACID1 0x0700 -#define REG_BSSID1 0x0708 +#define REG_MACID1 0x0700 +#define REG_BSSID1 0x0708 - -/* */ -/* */ /* 0xFE00h ~ 0xFE55h USB Configuration */ -/* */ -/* */ -#define REG_USB_INFO 0xFE17 -#define REG_USB_SPECIAL_OPTION 0xFE55 -#define REG_USB_DMA_AGG_TO 0xFE5B -#define REG_USB_AGG_TO 0xFE5C -#define REG_USB_AGG_TH 0xFE5D - +#define REG_USB_INFO 0xFE17 +#define REG_USB_SPECIAL_OPTION 0xFE55 +#define REG_USB_DMA_AGG_TO 0xFE5B +#define REG_USB_AGG_TO 0xFE5C +#define REG_USB_AGG_TH 0xFE5D /* For normal chip */ -#define REG_NORMAL_SIE_VID 0xFE60 /* 0xFE60~0xFE61 */ -#define REG_NORMAL_SIE_PID 0xFE62 /* 0xFE62~0xFE63 */ +#define REG_NORMAL_SIE_VID 0xFE60 /* 0xFE60~0xFE61 */ +#define REG_NORMAL_SIE_PID 0xFE62 /* 0xFE62~0xFE63 */ #define REG_NORMAL_SIE_OPTIONAL 0xFE64 -#define REG_NORMAL_SIE_EP 0xFE65 /* 0xFE65~0xFE67 */ -#define REG_NORMAL_SIE_PHY 0xFE68 /* 0xFE68~0xFE6B */ -#define REG_NORMAL_SIE_OPTIONAL2 0xFE6C -#define REG_NORMAL_SIE_GPS_EP 0xFE6D /* 0xFE6D, for RTL8723 only. */ +#define REG_NORMAL_SIE_EP 0xFE65 /* 0xFE65~0xFE67 */ +#define REG_NORMAL_SIE_PHY 0xFE68 /* 0xFE68~0xFE6B */ +#define REG_NORMAL_SIE_OPTIONAL2 0xFE6C +#define REG_NORMAL_SIE_GPS_EP 0xFE6D /* 0xFE6D, for RTL8723 only. */ #define REG_NORMAL_SIE_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */ -#define REG_NORMAL_SIE_STRING 0xFE80 /* 0xFE80~0xFEDF */ +#define REG_NORMAL_SIE_STRING 0xFE80 /* 0xFE80~0xFEDF */ - -/* */ -/* */ /* Redifine 8192C register definition for compatibility */ -/* */ -/* */ /* TODO: use these definition when using REG_xxx naming rule. */ /* NOTE: DO NOT Remove these definition. Use later. */ -#define EFUSE_CTRL REG_EFUSE_CTRL /* E-Fuse Control. */ -#define EFUSE_TEST REG_EFUSE_TEST /* E-Fuse Test. */ -#define MSR (REG_CR + 2) /* Media Status register */ -#define ISR REG_HISR_88E -#define TSFR REG_TSFTR /* Timing Sync Function Timer Register. */ +#define EFUSE_CTRL REG_EFUSE_CTRL /* E-Fuse Control. */ +#define EFUSE_TEST REG_EFUSE_TEST /* E-Fuse Test. */ +#define MSR (REG_CR + 2) /* Media Status reg */ +#define ISR REG_HISR_88E +/* Timing Sync Function Timer Register. */ +#define TSFR REG_TSFTR -#define PBP REG_PBP +#define PBP REG_PBP /* Redifine MACID register, to compatible prior ICs. */ -#define IDR0 REG_MACID /* MAC ID Register, Offset 0x0050-0x0053 */ -#define IDR4 (REG_MACID + 4) /* MAC ID Register, Offset 0x0054-0x0055 */ +/* MAC ID Register, Offset 0x0050-0x0053 */ +#define IDR0 REG_MACID +/* MAC ID Register, Offset 0x0054-0x0055 */ +#define IDR4 (REG_MACID + 4) - -/* */ /* 9. Security Control Registers (Offset: ) */ -/* */ -#define RWCAM REG_CAMCMD /* IN 8190 Data Sheet is called CAMcmd */ -#define WCAMI REG_CAMWRITE /* Software write CAM input content */ -#define RCAMO REG_CAMREAD /* Software read/write CAM config */ -#define CAMDBG REG_CAMDBG -#define SECR REG_SECCFG /* Security Configuration Register */ +/* IN 8190 Data Sheet is called CAMcmd */ +#define RWCAM REG_CAMCMD +/* Software write CAM input content */ +#define WCAMI REG_CAMWRITE +/* Software read/write CAM config */ +#define RCAMO REG_CAMREAD +#define CAMDBG REG_CAMDBG +/* Security Configuration Register */ +#define SECR REG_SECCFG /* Unused register */ -#define UnusedRegister 0x1BF -#define DCAM UnusedRegister -#define PSR UnusedRegister -#define BBAddr UnusedRegister -#define PhyDataR UnusedRegister +#define UnusedRegister 0x1BF +#define DCAM UnusedRegister +#define PSR UnusedRegister +#define BBAddr UnusedRegister +#define PhyDataR UnusedRegister /* Min Spacing related settings. */ -#define MAX_MSS_DENSITY_2T 0x13 -#define MAX_MSS_DENSITY_1T 0x0A +#define MAX_MSS_DENSITY_2T 0x13 +#define MAX_MSS_DENSITY_1T 0x0A -/* */ -/* 8192C Cmd9346CR bits (Offset 0xA, 16bit) */ -/* */ -#define CmdEEPROM_En BIT5 /* EEPROM enable when set 1 */ -#define CmdEERPOMSEL BIT4 /* System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */ -#define Cmd9346CR_9356SEL BIT4 +/* 8192C Cmd9346CR bits (Offset 0xA, 16bit) */ +/* EEPROM enable when set 1 */ +#define CmdEEPROM_En BIT5 +/* System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */ +#define CmdEERPOMSEL BIT4 +#define Cmd9346CR_9356SEL BIT4 -/* */ /* 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) */ -/* */ -#define GPIOSEL_GPIO 0 -#define GPIOSEL_ENBT BIT5 +#define GPIOSEL_GPIO 0 +#define GPIOSEL_ENBT BIT5 -/* */ /* 8192C GPIO PIN Control Register (offset 0x44, 4 byte) */ -/* */ -#define GPIO_IN REG_GPIO_PIN_CTRL /* GPIO pins input value */ -#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) /* GPIO pins output value */ -#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) /* GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. */ -#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) +/* GPIO pins input value */ +#define GPIO_IN REG_GPIO_PIN_CTRL +/* GPIO pins output value */ +#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) +/* GPIO pins output enable when a bit is set to "1"; otherwise, + * input is configured. */ +#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) +#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) -/* */ -/* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */ -/* */ +/* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */ #define HSIMR_GPIO12_0_INT_EN BIT0 #define HSIMR_SPS_OCP_INT_EN BIT5 -#define HSIMR_RON_INT_EN BIT6 -#define HSIMR_PDN_INT_EN BIT7 +#define HSIMR_RON_INT_EN BIT6 +#define HSIMR_PDN_INT_EN BIT7 #define HSIMR_GPIO9_INT_EN BIT25 - -/* */ -/* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */ -/* */ -#define HSISR_GPIO12_0_INT BIT0 -#define HSISR_SPS_OCP_INT BIT5 -#define HSISR_RON_INT_EN BIT6 -#define HSISR_PDNINT BIT7 +/* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */ +#define HSISR_GPIO12_0_INT BIT0 +#define HSISR_SPS_OCP_INT BIT5 +#define HSISR_RON_INT_EN BIT6 +#define HSISR_PDNINT BIT7 #define HSISR_GPIO9_INT BIT25 -/* */ -/* 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) */ -/* */ +/* 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) */ /* Network Type 00: No link @@ -580,178 +529,151 @@ Network Type 11: AP mode Default: 00b. */ -#define MSR_NOLINK 0x00 -#define MSR_ADHOC 0x01 -#define MSR_INFRA 0x02 -#define MSR_AP 0x03 +#define MSR_NOLINK 0x00 +#define MSR_ADHOC 0x01 +#define MSR_INFRA 0x02 +#define MSR_AP 0x03 -/* */ -/* 88EU (MSR) Media Status Register (Offset 0x4C, 8 bits) */ -/* */ -#define USB_INTR_CONTENT_C2H_OFFSET 0 +/* 88EU (MSR) Media Status Register (Offset 0x4C, 8 bits) */ +#define USB_INTR_CONTENT_C2H_OFFSET 0 #define USB_INTR_CONTENT_CPWM1_OFFSET 16 #define USB_INTR_CONTENT_CPWM2_OFFSET 20 -#define USB_INTR_CONTENT_HISR_OFFSET 48 +#define USB_INTR_CONTENT_HISR_OFFSET 48 #define USB_INTR_CONTENT_HISRE_OFFSET 52 - -/* */ -/* 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits) */ -/* */ +/* 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits) */ /* IOL config for REG_FDHM0(Reg0x88) */ -#define CMD_INIT_LLT BIT0 +#define CMD_INIT_LLT BIT0 #define CMD_READ_EFUSE_MAP BIT1 #define CMD_EFUSE_PATCH BIT2 -#define CMD_IOCONFIG BIT3 -#define CMD_INIT_LLT_ERR BIT4 -#define CMD_READ_EFUSE_MAP_ERR BIT5 +#define CMD_IOCONFIG BIT3 +#define CMD_INIT_LLT_ERR BIT4 +#define CMD_READ_EFUSE_MAP_ERR BIT5 #define CMD_EFUSE_PATCH_ERR BIT6 -#define CMD_IOCONFIG_ERR BIT7 +#define CMD_IOCONFIG_ERR BIT7 -/* */ /* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */ -/* */ -/* */ -/* 8192C Response Rate Set Register (offset 0x181, 24bits) */ -/* */ -#define RRSR_1M BIT0 -#define RRSR_2M BIT1 -#define RRSR_5_5M BIT2 -#define RRSR_11M BIT3 -#define RRSR_6M BIT4 -#define RRSR_9M BIT5 -#define RRSR_12M BIT6 -#define RRSR_18M BIT7 -#define RRSR_24M BIT8 -#define RRSR_36M BIT9 -#define RRSR_48M BIT10 -#define RRSR_54M BIT11 -#define RRSR_MCS0 BIT12 -#define RRSR_MCS1 BIT13 -#define RRSR_MCS2 BIT14 -#define RRSR_MCS3 BIT15 -#define RRSR_MCS4 BIT16 -#define RRSR_MCS5 BIT17 -#define RRSR_MCS6 BIT18 -#define RRSR_MCS7 BIT19 +/* 8192C Response Rate Set Register (offset 0x181, 24bits) */ +#define RRSR_1M BIT0 +#define RRSR_2M BIT1 +#define RRSR_5_5M BIT2 +#define RRSR_11M BIT3 +#define RRSR_6M BIT4 +#define RRSR_9M BIT5 +#define RRSR_12M BIT6 +#define RRSR_18M BIT7 +#define RRSR_24M BIT8 +#define RRSR_36M BIT9 +#define RRSR_48M BIT10 +#define RRSR_54M BIT11 +#define RRSR_MCS0 BIT12 +#define RRSR_MCS1 BIT13 +#define RRSR_MCS2 BIT14 +#define RRSR_MCS3 BIT15 +#define RRSR_MCS4 BIT16 +#define RRSR_MCS5 BIT17 +#define RRSR_MCS6 BIT18 +#define RRSR_MCS7 BIT19 -/* */ -/* 8192C Response Rate Set Register (offset 0x1BF, 8bits) */ -/* */ +/* 8192C Response Rate Set Register (offset 0x1BF, 8bits) */ /* WOL bit information */ -#define HAL92C_WOL_PTK_UPDATE_EVENT BIT0 -#define HAL92C_WOL_GTK_UPDATE_EVENT BIT1 +#define HAL92C_WOL_PTK_UPDATE_EVENT BIT0 +#define HAL92C_WOL_GTK_UPDATE_EVENT BIT1 -/* */ -/* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */ -/* */ +/* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */ #define BW_OPMODE_20MHZ BIT2 -#define BW_OPMODE_5G BIT1 +#define BW_OPMODE_5G BIT1 - -/* */ /* 8192C CAM Config Setting (offset 0x250, 1 byte) */ -/* */ -#define CAM_VALID BIT15 -#define CAM_NOTVALID 0x0000 -#define CAM_USEDK BIT5 +#define CAM_VALID BIT15 +#define CAM_NOTVALID 0x0000 +#define CAM_USEDK BIT5 #define CAM_CONTENT_COUNT 8 -#define CAM_NONE 0x0 -#define CAM_WEP40 0x01 -#define CAM_TKIP 0x02 -#define CAM_AES 0x04 -#define CAM_WEP104 0x05 -#define CAM_SMS4 0x6 +#define CAM_NONE 0x0 +#define CAM_WEP40 0x01 +#define CAM_TKIP 0x02 +#define CAM_AES 0x04 +#define CAM_WEP104 0x05 +#define CAM_SMS4 0x6 #define TOTAL_CAM_ENTRY 32 #define HALF_CAM_ENTRY 16 -#define CAM_CONFIG_USEDK true +#define CAM_CONFIG_USEDK true #define CAM_CONFIG_NO_USEDK false -#define CAM_WRITE BIT16 -#define CAM_READ 0x00000000 -#define CAM_POLLINIG BIT31 +#define CAM_WRITE BIT16 +#define CAM_READ 0x00000000 +#define CAM_POLLINIG BIT31 -#define SCR_UseDK 0x01 +#define SCR_UseDK 0x01 #define SCR_TxSecEnable 0x02 #define SCR_RxSecEnable 0x04 -/* */ /* 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) */ -/* */ -#define WOW_PMEN BIT0 /* Power management Enable. */ +#define WOW_PMEN BIT0 /* Power management Enable. */ #define WOW_WOMEN BIT1 /* WoW function on or off. */ -#define WOW_MAGIC BIT2 /* Magic packet */ +#define WOW_MAGIC BIT2 /* Magic packet */ #define WOW_UWF BIT3 /* Unicast Wakeup frame. */ -/* */ /* 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) */ -/* */ -/* */ -/* */ /* 8188 IMR/ISR bits */ -/* */ -#define IMR_DISABLED_88E 0x0 +#define IMR_DISABLED_88E 0x0 /* IMR DW0(0x0060-0063) Bit 0-31 */ -#define IMR_TXCCK_88E BIT30 /* TXRPT interrupt when CCX bit of the packet is set */ -#define IMR_PSTIMEOUT_88E BIT29 /* Power Save Time Out Interrupt */ -#define IMR_GTINT4_88E BIT28 /* When GTIMER4 expires, this bit is set to 1 */ -#define IMR_GTINT3_88E BIT27 /* When GTIMER3 expires, this bit is set to 1 */ -#define IMR_TBDER_88E BIT26 /* Transmit Beacon0 Error */ -#define IMR_TBDOK_88E BIT25 /* Transmit Beacon0 OK */ -#define IMR_TSF_BIT32_TOGGLE_88E BIT24 /* TSF Timer BIT32 toggle indication interrupt */ -#define IMR_BCNDMAINT0_88E BIT20 /* Beacon DMA Interrupt 0 */ -#define IMR_BCNDERR0_88E BIT16 /* Beacon Queue DMA Error 0 */ -#define IMR_HSISR_IND_ON_INT_88E BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ -#define IMR_BCNDMAINT_E_88E BIT14 /* Beacon DMA Interrupt Extension for Win7 */ -#define IMR_ATIMEND_88E BIT12 /* CTWidnow End or ATIM Window End */ -#define IMR_HISR1_IND_INT_88E BIT11 /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */ -#define IMR_C2HCMD_88E BIT10 /* CPU to Host Command INT Status, Write 1 clear */ -#define IMR_CPWM2_88E BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_CPWM_88E BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ -#define IMR_HIGHDOK_88E BIT7 /* High Queue DMA OK */ -#define IMR_MGNTDOK_88E BIT6 /* Management Queue DMA OK */ -#define IMR_BKDOK_88E BIT5 /* AC_BK DMA OK */ -#define IMR_BEDOK_88E BIT4 /* AC_BE DMA OK */ -#define IMR_VIDOK_88E BIT3 /* AC_VI DMA OK */ -#define IMR_VODOK_88E BIT2 /* AC_VO DMA OK */ -#define IMR_RDU_88E BIT1 /* Rx Descriptor Unavailable */ -#define IMR_ROK_88E BIT0 /* Receive DMA OK */ +#define IMR_TXCCK_88E BIT30 /* TXRPT interrupt when CCX bit of the packet is set */ +#define IMR_PSTIMEOUT_88E BIT29 /* Power Save Time Out Interrupt */ +#define IMR_GTINT4_88E BIT28 /* When GTIMER4 expires, this bit is set to 1 */ +#define IMR_GTINT3_88E BIT27 /* When GTIMER3 expires, this bit is set to 1 */ +#define IMR_TBDER_88E BIT26 /* Transmit Beacon0 Error */ +#define IMR_TBDOK_88E BIT25 /* Transmit Beacon0 OK */ +#define IMR_TSF_BIT32_TOGGLE_88E BIT24 /* TSF Timer BIT32 toggle indication interrupt */ +#define IMR_BCNDMAINT0_88E BIT20 /* Beacon DMA Interrupt 0 */ +#define IMR_BCNDERR0_88E BIT16 /* Beacon Queue DMA Error 0 */ +#define IMR_HSISR_IND_ON_INT_88E BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ +#define IMR_BCNDMAINT_E_88E BIT14 /* Beacon DMA Interrupt Extension for Win7 */ +#define IMR_ATIMEND_88E BIT12 /* CTWidnow End or ATIM Window End */ +#define IMR_HISR1_IND_INT_88E BIT11 /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */ +#define IMR_C2HCMD_88E BIT10 /* CPU to Host Command INT Status, Write 1 clear */ +#define IMR_CPWM2_88E BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ +#define IMR_CPWM_88E BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ +#define IMR_HIGHDOK_88E BIT7 /* High Queue DMA OK */ +#define IMR_MGNTDOK_88E BIT6 /* Management Queue DMA OK */ +#define IMR_BKDOK_88E BIT5 /* AC_BK DMA OK */ +#define IMR_BEDOK_88E BIT4 /* AC_BE DMA OK */ +#define IMR_VIDOK_88E BIT3 /* AC_VI DMA OK */ +#define IMR_VODOK_88E BIT2 /* AC_VO DMA OK */ +#define IMR_RDU_88E BIT1 /* Rx Descriptor Unavailable */ +#define IMR_ROK_88E BIT0 /* Receive DMA OK */ /* IMR DW1(0x00B4-00B7) Bit 0-31 */ -#define IMR_BCNDMAINT7_88E BIT27 /* Beacon DMA Interrupt 7 */ -#define IMR_BCNDMAINT6_88E BIT26 /* Beacon DMA Interrupt 6 */ -#define IMR_BCNDMAINT5_88E BIT25 /* Beacon DMA Interrupt 5 */ -#define IMR_BCNDMAINT4_88E BIT24 /* Beacon DMA Interrupt 4 */ -#define IMR_BCNDMAINT3_88E BIT23 /* Beacon DMA Interrupt 3 */ -#define IMR_BCNDMAINT2_88E BIT22 /* Beacon DMA Interrupt 2 */ -#define IMR_BCNDMAINT1_88E BIT21 /* Beacon DMA Interrupt 1 */ -#define IMR_BCNDERR7_88E BIT20 /* Beacon Queue DMA Error Interrup 7 */ -#define IMR_BCNDERR6_88E BIT19 /* Beacon Queue DMA Error Interrup 6 */ -#define IMR_BCNDERR5_88E BIT18 /* Beacon Queue DMA Error Interrup 5 */ -#define IMR_BCNDERR4_88E BIT17 /* Beacon Queue DMA Error Interrup 4 */ -#define IMR_BCNDERR3_88E BIT16 /* Beacon Queue DMA Error Interrup 3 */ -#define IMR_BCNDERR2_88E BIT15 /* Beacon Queue DMA Error Interrup 2 */ -#define IMR_BCNDERR1_88E BIT14 /* Beacon Queue DMA Error Interrup 1 */ -#define IMR_ATIMEND_E_88E BIT13 /* ATIM Window End Extension for Win7 */ -#define IMR_TXERR_88E BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ -#define IMR_RXERR_88E BIT10 /* Rx Error Flag INT Status, Write 1 clear */ -#define IMR_TXFOVW_88E BIT9 /* Transmit FIFO Overflow */ -#define IMR_RXFOVW_88E BIT8 /* Receive FIFO Overflow */ +#define IMR_BCNDMAINT7_88E BIT27 /* Beacon DMA Interrupt 7 */ +#define IMR_BCNDMAINT6_88E BIT26 /* Beacon DMA Interrupt 6 */ +#define IMR_BCNDMAINT5_88E BIT25 /* Beacon DMA Interrupt 5 */ +#define IMR_BCNDMAINT4_88E BIT24 /* Beacon DMA Interrupt 4 */ +#define IMR_BCNDMAINT3_88E BIT23 /* Beacon DMA Interrupt 3 */ +#define IMR_BCNDMAINT2_88E BIT22 /* Beacon DMA Interrupt 2 */ +#define IMR_BCNDMAINT1_88E BIT21 /* Beacon DMA Interrupt 1 */ +#define IMR_BCNDERR7_88E BIT20 /* Beacon DMA Error Int 7 */ +#define IMR_BCNDERR6_88E BIT19 /* Beacon DMA Error Int 6 */ +#define IMR_BCNDERR5_88E BIT18 /* Beacon DMA Error Int 5 */ +#define IMR_BCNDERR4_88E BIT17 /* Beacon DMA Error Int 4 */ +#define IMR_BCNDERR3_88E BIT16 /* Beacon DMA Error Int 3 */ +#define IMR_BCNDERR2_88E BIT15 /* Beacon DMA Error Int 2 */ +#define IMR_BCNDERR1_88E BIT14 /* Beacon DMA Error Int 1 */ +#define IMR_ATIMEND_E_88E BIT13 /* ATIM Window End Ext for Win7 */ +#define IMR_TXERR_88E BIT11 /* Tx Err Flag Int Status, write 1 clear. */ +#define IMR_RXERR_88E BIT10 /* Rx Err Flag INT Status, Write 1 clear */ +#define IMR_TXFOVW_88E BIT9 /* Transmit FIFO Overflow */ +#define IMR_RXFOVW_88E BIT8 /* Receive FIFO Overflow */ #define HAL_NIC_UNPLUG_ISR 0xFFFFFFFF /* The value when the NIC is unplugged for PCI. */ - /* 8192C EFUSE */ -/* */ -#define HWSET_MAX_SIZE 256 +#define HWSET_MAX_SIZE 256 #define HWSET_MAX_SIZE_88E 512 - - /*=================================================================== ===================================================================== Here the register defines are for 92C. When the define is as same with 92C, @@ -773,590 +695,510 @@ Current IOREG MAP 0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) 0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) */ - /* */ - /* 8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits) */ - /* */ +/* 8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits) */ /* Note: */ -/* The the bits of stoping AC(VO/VI/BE/BK) queue in datasheet RTL8192S/RTL8192C are wrong, */ -/* the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2, and BK - Bit3. */ -/* 8723 and 88E may be not correct either in the eralier version. Confirmed with DD Tim. */ -/* By Bruce, 2011-09-22. */ +/* The bits of stopping AC(VO/VI/BE/BK) queue in datasheet + * RTL8192S/RTL8192C are wrong, */ +/* the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2, + * and BK - Bit3. */ +/* 8723 and 88E may be not correct either in the earlier version. */ #define StopBecon BIT6 -#define StopHigh BIT5 +#define StopHigh BIT5 #define StopMgt BIT4 #define StopBK BIT3 #define StopBE BIT2 #define StopVI BIT1 #define StopVO BIT0 -/* */ -/* 8192C (RCR) Receive Configuration Register (Offset 0x608, 32 bits) */ -/* */ -#define RCR_APPFCS BIT31 /* WMAC append FCS after pauload */ -#define RCR_APP_MIC BIT30 /* */ -#define RCR_APP_PHYSTS BIT28/* */ -#define RCR_APP_ICV BIT29 /* */ -#define RCR_APP_PHYST_RXFF BIT28 /* */ -#define RCR_APP_BA_SSN BIT27 /* Accept BA SSN */ -#define RCR_ENMBID BIT24 /* Enable Multiple BssId. */ -#define RCR_LSIGEN BIT23 -#define RCR_MFBEN BIT22 -#define RCR_HTC_LOC_CTRL BIT14 /* MFC<--HTC=1 MFC-->HTC=0 */ -#define RCR_AMF BIT13 /* Accept management type frame */ -#define RCR_ACF BIT12 /* Accept control type frame */ -#define RCR_ADF BIT11 /* Accept data type frame */ -#define RCR_AICV BIT9 /* Accept ICV error packet */ -#define RCR_ACRC32 BIT8 /* Accept CRC32 error packet */ -#define RCR_CBSSID_BCN BIT7 /* Accept BSSID match packet (Rx beacon, probe rsp) */ -#define RCR_CBSSID_DATA BIT6 /* Accept BSSID match packet (Data) */ -#define RCR_CBSSID RCR_CBSSID_DATA /* Accept BSSID match packet */ -#define RCR_APWRMGT BIT5 /* Accept power management packet */ -#define RCR_ADD3 BIT4 /* Accept address 3 match packet */ -#define RCR_AB BIT3 /* Accept broadcast packet */ -#define RCR_AM BIT2 /* Accept multicast packet */ -#define RCR_APM BIT1 /* Accept physical match packet */ -#define RCR_AAP BIT0 /* Accept all unicast packet */ -#define RCR_MXDMA_OFFSET 8 -#define RCR_FIFO_OFFSET 13 +/* 8192C (RCR) Receive Configuration Register(Offset 0x608, 32 bits) */ +#define RCR_APPFCS BIT31 /* WMAC append FCS after payload */ +#define RCR_APP_MIC BIT30 +#define RCR_APP_PHYSTS BIT28 +#define RCR_APP_ICV BIT29 +#define RCR_APP_PHYST_RXFF BIT28 +#define RCR_APP_BA_SSN BIT27 /* Accept BA SSN */ +#define RCR_ENMBID BIT24 /* Enable Multiple BssId. */ +#define RCR_LSIGEN BIT23 +#define RCR_MFBEN BIT22 +#define RCR_HTC_LOC_CTRL BIT14 /* MFC<--HTC=1 MFC-->HTC=0 */ +#define RCR_AMF BIT13 /* Accept management type frame */ +#define RCR_ACF BIT12 /* Accept control type frame */ +#define RCR_ADF BIT11 /* Accept data type frame */ +#define RCR_AICV BIT9 /* Accept ICV error packet */ +#define RCR_ACRC32 BIT8 /* Accept CRC32 error packet */ +#define RCR_CBSSID_BCN BIT7 /* Accept BSSID match packet + * (Rx beacon, probe rsp) */ +#define RCR_CBSSID_DATA BIT6 /* Accept BSSID match (Data)*/ +#define RCR_CBSSID RCR_CBSSID_DATA /* Accept BSSID match */ +#define RCR_APWRMGT BIT5 /* Accept power management pkt*/ +#define RCR_ADD3 BIT4 /* Accept address 3 match pkt */ +#define RCR_AB BIT3 /* Accept broadcast packet */ +#define RCR_AM BIT2 /* Accept multicast packet */ +#define RCR_APM BIT1 /* Accept physical match pkt */ +#define RCR_AAP BIT0 /* Accept all unicast packet */ +#define RCR_MXDMA_OFFSET 8 +#define RCR_FIFO_OFFSET 13 -/* */ -/* */ /* 0xFE00h ~ 0xFE55h USB Configuration */ -/* */ -/* */ -#define REG_USB_INFO 0xFE17 -#define REG_USB_SPECIAL_OPTION 0xFE55 -#define REG_USB_DMA_AGG_TO 0xFE5B -#define REG_USB_AGG_TO 0xFE5C -#define REG_USB_AGG_TH 0xFE5D +#define REG_USB_INFO 0xFE17 +#define REG_USB_SPECIAL_OPTION 0xFE55 +#define REG_USB_DMA_AGG_TO 0xFE5B +#define REG_USB_AGG_TO 0xFE5C +#define REG_USB_AGG_TH 0xFE5D -#define REG_USB_HRPWM 0xFE58 -#define REG_USB_HCPWM 0xFE57 - -/* */ +#define REG_USB_HRPWM 0xFE58 +#define REG_USB_HCPWM 0xFE57 /* 8192C Regsiter Bit and Content definition */ -/* */ -/* */ -/* */ /* 0x0000h ~ 0x00FFh System Configuration */ -/* */ -/* */ /* 2 SYS_ISO_CTRL */ -#define ISO_MD2PP BIT(0) -#define ISO_UA2USB BIT(1) -#define ISO_UD2CORE BIT(2) -#define ISO_PA2PCIE BIT(3) -#define ISO_PD2CORE BIT(4) -#define ISO_IP2MAC BIT(5) -#define ISO_DIOP BIT(6) -#define ISO_DIOE BIT(7) -#define ISO_EB2CORE BIT(8) -#define ISO_DIOR BIT(9) -#define PWC_EV12V BIT(15) - +#define ISO_MD2PP BIT(0) +#define ISO_UA2USB BIT(1) +#define ISO_UD2CORE BIT(2) +#define ISO_PA2PCIE BIT(3) +#define ISO_PD2CORE BIT(4) +#define ISO_IP2MAC BIT(5) +#define ISO_DIOP BIT(6) +#define ISO_DIOE BIT(7) +#define ISO_EB2CORE BIT(8) +#define ISO_DIOR BIT(9) +#define PWC_EV12V BIT(15) /* 2 SYS_FUNC_EN */ -#define FEN_BBRSTB BIT(0) -#define FEN_BB_GLB_RSTn BIT(1) -#define FEN_USBA BIT(2) -#define FEN_UPLL BIT(3) -#define FEN_USBD BIT(4) -#define FEN_DIO_PCIE BIT(5) -#define FEN_PCIEA BIT(6) -#define FEN_PPLL BIT(7) -#define FEN_PCIED BIT(8) -#define FEN_DIOE BIT(9) -#define FEN_CPUEN BIT(10) -#define FEN_DCORE BIT(11) -#define FEN_ELDR BIT(12) -#define FEN_DIO_RF BIT(13) -#define FEN_HWPDN BIT(14) -#define FEN_MREGEN BIT(15) +#define FEN_BBRSTB BIT(0) +#define FEN_BB_GLB_RSTn BIT(1) +#define FEN_USBA BIT(2) +#define FEN_UPLL BIT(3) +#define FEN_USBD BIT(4) +#define FEN_DIO_PCIE BIT(5) +#define FEN_PCIEA BIT(6) +#define FEN_PPLL BIT(7) +#define FEN_PCIED BIT(8) +#define FEN_DIOE BIT(9) +#define FEN_CPUEN BIT(10) +#define FEN_DCORE BIT(11) +#define FEN_ELDR BIT(12) +#define FEN_DIO_RF BIT(13) +#define FEN_HWPDN BIT(14) +#define FEN_MREGEN BIT(15) /* 2 APS_FSMCO */ -#define PFM_LDALL BIT(0) -#define PFM_ALDN BIT(1) -#define PFM_LDKP BIT(2) -#define PFM_WOWL BIT(3) -#define EnPDN BIT(4) -#define PDN_PL BIT(5) -#define APFM_ONMAC BIT(8) -#define APFM_OFF BIT(9) -#define APFM_RSM BIT(10) -#define AFSM_HSUS BIT(11) -#define AFSM_PCIE BIT(12) -#define APDM_MAC BIT(13) -#define APDM_HOST BIT(14) -#define APDM_HPDN BIT(15) -#define RDY_MACON BIT(16) -#define SUS_HOST BIT(17) -#define ROP_ALD BIT(20) -#define ROP_PWR BIT(21) -#define ROP_SPS BIT(22) -#define SOP_MRST BIT(25) -#define SOP_FUSE BIT(26) -#define SOP_ABG BIT(27) -#define SOP_AMB BIT(28) -#define SOP_RCK BIT(29) -#define SOP_A8M BIT(30) -#define XOP_BTCK BIT(31) +#define PFM_LDALL BIT(0) +#define PFM_ALDN BIT(1) +#define PFM_LDKP BIT(2) +#define PFM_WOWL BIT(3) +#define EnPDN BIT(4) +#define PDN_PL BIT(5) +#define APFM_ONMAC BIT(8) +#define APFM_OFF BIT(9) +#define APFM_RSM BIT(10) +#define AFSM_HSUS BIT(11) +#define AFSM_PCIE BIT(12) +#define APDM_MAC BIT(13) +#define APDM_HOST BIT(14) +#define APDM_HPDN BIT(15) +#define RDY_MACON BIT(16) +#define SUS_HOST BIT(17) +#define ROP_ALD BIT(20) +#define ROP_PWR BIT(21) +#define ROP_SPS BIT(22) +#define SOP_MRST BIT(25) +#define SOP_FUSE BIT(26) +#define SOP_ABG BIT(27) +#define SOP_AMB BIT(28) +#define SOP_RCK BIT(29) +#define SOP_A8M BIT(30) +#define XOP_BTCK BIT(31) /* 2 SYS_CLKR */ -#define ANAD16V_EN BIT(0) -#define ANA8M BIT(1) -#define MACSLP BIT(4) -#define LOADER_CLK_EN BIT(5) - +#define ANAD16V_EN BIT(0) +#define ANA8M BIT(1) +#define MACSLP BIT(4) +#define LOADER_CLK_EN BIT(5) /* 2 9346CR */ -#define BOOT_FROM_EEPROM BIT(4) -#define EEPROM_EN BIT(5) - +#define BOOT_FROM_EEPROM BIT(4) +#define EEPROM_EN BIT(5) /* 2 SPS0_CTRL */ - /* 2 SPS_OCP_CFG */ - /* 2 RF_CTRL */ -#define RF_EN BIT(0) -#define RF_RSTB BIT(1) -#define RF_SDMRSTB BIT(2) - - +#define RF_EN BIT(0) +#define RF_RSTB BIT(1) +#define RF_SDMRSTB BIT(2) /* 2 LDOV12D_CTRL */ -#define LDV12_EN BIT(0) -#define LDV12_SDBY BIT(1) -#define LPLDO_HSM BIT(2) -#define LPLDO_LSM_DIS BIT(3) -#define _LDV12_VADJ(x) (((x) & 0xF) << 4) - +#define LDV12_EN BIT(0) +#define LDV12_SDBY BIT(1) +#define LPLDO_HSM BIT(2) +#define LPLDO_LSM_DIS BIT(3) +#define _LDV12_VADJ(x) (((x) & 0xF) << 4) /* 2EFUSE_CTRL */ -#define ALD_EN BIT(18) -#define EF_PD BIT(19) -#define EF_FLAG BIT(31) +#define ALD_EN BIT(18) +#define EF_PD BIT(19) +#define EF_FLAG BIT(31) /* 2 EFUSE_TEST (For RTL8723 partially) */ -#define EF_TRPT BIT(7) -#define EF_CELL_SEL (BIT(8)|BIT(9)) /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ -#define LDOE25_EN BIT(31) -#define EFUSE_SEL(x) (((x) & 0x3) << 8) -#define EFUSE_SEL_MASK 0x300 -#define EFUSE_WIFI_SEL_0 0x0 -#define EFUSE_BT_SEL_0 0x1 -#define EFUSE_BT_SEL_1 0x2 -#define EFUSE_BT_SEL_2 0x3 +#define EF_TRPT BIT(7) +/* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ +#define EF_CELL_SEL (BIT(8)|BIT(9)) +#define LDOE25_EN BIT(31) +#define EFUSE_SEL(x) (((x) & 0x3) << 8) +#define EFUSE_SEL_MASK 0x300 +#define EFUSE_WIFI_SEL_0 0x0 +#define EFUSE_BT_SEL_0 0x1 +#define EFUSE_BT_SEL_1 0x2 +#define EFUSE_BT_SEL_2 0x3 #define EFUSE_ACCESS_ON 0x69 /* For RTL8723 only. */ -#define EFUSE_ACCESS_OFF 0x00 /* For RTL8723 only. */ - +#define EFUSE_ACCESS_OFF 0x00 /* For RTL8723 only. */ /* 2 8051FWDL */ /* 2 MCUFWDL */ -#define MCUFWDL_EN BIT(0) -#define MCUFWDL_RDY BIT(1) -#define FWDL_ChkSum_rpt BIT(2) -#define MACINI_RDY BIT(3) -#define BBINI_RDY BIT(4) -#define RFINI_RDY BIT(5) -#define WINTINI_RDY BIT(6) -#define RAM_DL_SEL BIT(7) /* 1:RAM, 0:ROM */ -#define ROM_DLEN BIT(19) -#define CPRST BIT(23) - - +#define MCUFWDL_EN BIT(0) +#define MCUFWDL_RDY BIT(1) +#define FWDL_ChkSum_rpt BIT(2) +#define MACINI_RDY BIT(3) +#define BBINI_RDY BIT(4) +#define RFINI_RDY BIT(5) +#define WINTINI_RDY BIT(6) +#define RAM_DL_SEL BIT(7) /* 1:RAM, 0:ROM */ +#define ROM_DLEN BIT(19) +#define CPRST BIT(23) /* 2 REG_SYS_CFG */ -#define XCLK_VLD BIT(0) -#define ACLK_VLD BIT(1) -#define UCLK_VLD BIT(2) -#define PCLK_VLD BIT(3) -#define PCIRSTB BIT(4) -#define V15_VLD BIT(5) -#define SW_OFFLOAD_EN BIT(7) -#define SIC_IDLE BIT(8) -#define BD_MAC2 BIT(9) -#define BD_MAC1 BIT(10) -#define IC_MACPHY_MODE BIT(11) -#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) -#define BT_FUNC BIT(16) -#define VENDOR_ID BIT(19) -#define PAD_HWPD_IDN BIT(22) -#define TRP_VAUX_EN BIT(23) /* RTL ID */ -#define TRP_BT_EN BIT(24) -#define BD_PKG_SEL BIT(25) -#define BD_HCI_SEL BIT(26) -#define TYPE_ID BIT(27) - -#define CHIP_VER_RTL_MASK 0xF000 /* Bit 12 ~ 15 */ -#define CHIP_VER_RTL_SHIFT 12 +#define XCLK_VLD BIT(0) +#define ACLK_VLD BIT(1) +#define UCLK_VLD BIT(2) +#define PCLK_VLD BIT(3) +#define PCIRSTB BIT(4) +#define V15_VLD BIT(5) +#define SW_OFFLOAD_EN BIT(7) +#define SIC_IDLE BIT(8) +#define BD_MAC2 BIT(9) +#define BD_MAC1 BIT(10) +#define IC_MACPHY_MODE BIT(11) +#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) +#define BT_FUNC BIT(16) +#define VENDOR_ID BIT(19) +#define PAD_HWPD_IDN BIT(22) +#define TRP_VAUX_EN BIT(23) /* RTL ID */ +#define TRP_BT_EN BIT(24) +#define BD_PKG_SEL BIT(25) +#define BD_HCI_SEL BIT(26) +#define TYPE_ID BIT(27) +#define CHIP_VER_RTL_MASK 0xF000 /* Bit 12 ~ 15 */ +#define CHIP_VER_RTL_SHIFT 12 /* 2REG_GPIO_OUTSTS (For RTL8723 only) */ -#define EFS_HCI_SEL (BIT(0)|BIT(1)) -#define PAD_HCI_SEL (BIT(2)|BIT(3)) -#define HCI_SEL (BIT(4)|BIT(5)) -#define PKG_SEL_HCI BIT(6) -#define FEN_GPS BIT(7) -#define FEN_BT BIT(8) -#define FEN_WL BIT(9) -#define FEN_PCI BIT(10) -#define FEN_USB BIT(11) -#define BTRF_HWPDN_N BIT(12) -#define WLRF_HWPDN_N BIT(13) -#define PDN_BT_N BIT(14) -#define PDN_GPS_N BIT(15) -#define BT_CTL_HWPDN BIT(16) -#define GPS_CTL_HWPDN BIT(17) -#define PPHY_SUSB BIT(20) -#define UPHY_SUSB BIT(21) -#define PCI_SUSEN BIT(22) -#define USB_SUSEN BIT(23) -#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) - +#define EFS_HCI_SEL (BIT(0)|BIT(1)) +#define PAD_HCI_SEL (BIT(2)|BIT(3)) +#define HCI_SEL (BIT(4)|BIT(5)) +#define PKG_SEL_HCI BIT(6) +#define FEN_GPS BIT(7) +#define FEN_BT BIT(8) +#define FEN_WL BIT(9) +#define FEN_PCI BIT(10) +#define FEN_USB BIT(11) +#define BTRF_HWPDN_N BIT(12) +#define WLRF_HWPDN_N BIT(13) +#define PDN_BT_N BIT(14) +#define PDN_GPS_N BIT(15) +#define BT_CTL_HWPDN BIT(16) +#define GPS_CTL_HWPDN BIT(17) +#define PPHY_SUSB BIT(20) +#define UPHY_SUSB BIT(21) +#define PCI_SUSEN BIT(22) +#define USB_SUSEN BIT(23) +#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) /* 2SYS_CFG */ -#define RTL_ID BIT(23) /* TestChip ID, 1:Test(RLE); 0:MP(RL) */ +#define RTL_ID BIT(23) /* TestChip ID, 1:Test(RLE); 0:MP(RL) */ -/* */ -/* */ /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ -/* */ -/* */ - /* 2 Function Enable Registers */ /* 2 CR */ - - -#define HCI_TXDMA_EN BIT(0) -#define HCI_RXDMA_EN BIT(1) -#define TXDMA_EN BIT(2) -#define RXDMA_EN BIT(3) -#define PROTOCOL_EN BIT(4) -#define SCHEDULE_EN BIT(5) -#define MACTXEN BIT(6) -#define MACRXEN BIT(7) -#define ENSWBCN BIT(8) -#define ENSEC BIT(9) -#define CALTMR_EN BIT(10) /* 32k CAL TMR enable */ +#define HCI_TXDMA_EN BIT(0) +#define HCI_RXDMA_EN BIT(1) +#define TXDMA_EN BIT(2) +#define RXDMA_EN BIT(3) +#define PROTOCOL_EN BIT(4) +#define SCHEDULE_EN BIT(5) +#define MACTXEN BIT(6) +#define MACRXEN BIT(7) +#define ENSWBCN BIT(8) +#define ENSEC BIT(9) +#define CALTMR_EN BIT(10) /* 32k CAL TMR enable */ /* Network type */ -#define _NETTYPE(x) (((x) & 0x3) << 16) -#define MASK_NETTYPE 0x30000 -#define NT_NO_LINK 0x0 -#define NT_LINK_AD_HOC 0x1 -#define NT_LINK_AP 0x2 -#define NT_AS_AP 0x3 - - +#define _NETTYPE(x) (((x) & 0x3) << 16) +#define MASK_NETTYPE 0x30000 +#define NT_NO_LINK 0x0 +#define NT_LINK_AD_HOC 0x1 +#define NT_LINK_AP 0x2 +#define NT_AS_AP 0x3 /* 2 PBP - Page Size Register */ -#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) -#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) -#define _PSRX_MASK 0xF -#define _PSTX_MASK 0xF0 -#define _PSRX(x) (x) -#define _PSTX(x) ((x) << 4) - -#define PBP_64 0x0 -#define PBP_128 0x1 -#define PBP_256 0x2 -#define PBP_512 0x3 -#define PBP_1024 0x4 +#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) +#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) +#define _PSRX_MASK 0xF +#define _PSTX_MASK 0xF0 +#define _PSRX(x) (x) +#define _PSTX(x) ((x) << 4) +#define PBP_64 0x0 +#define PBP_128 0x1 +#define PBP_256 0x2 +#define PBP_512 0x3 +#define PBP_1024 0x4 /* 2 TX/RXDMA */ -#define RXDMA_ARBBW_EN BIT(0) -#define RXSHFT_EN BIT(1) -#define RXDMA_AGG_EN BIT(2) -#define QS_VO_QUEUE BIT(8) -#define QS_VI_QUEUE BIT(9) -#define QS_BE_QUEUE BIT(10) -#define QS_BK_QUEUE BIT(11) -#define QS_MANAGER_QUEUE BIT(12) -#define QS_HIGH_QUEUE BIT(13) +#define RXDMA_ARBBW_EN BIT(0) +#define RXSHFT_EN BIT(1) +#define RXDMA_AGG_EN BIT(2) +#define QS_VO_QUEUE BIT(8) +#define QS_VI_QUEUE BIT(9) +#define QS_BE_QUEUE BIT(10) +#define QS_BK_QUEUE BIT(11) +#define QS_MANAGER_QUEUE BIT(12) +#define QS_HIGH_QUEUE BIT(13) -#define HQSEL_VOQ BIT(0) -#define HQSEL_VIQ BIT(1) -#define HQSEL_BEQ BIT(2) -#define HQSEL_BKQ BIT(3) -#define HQSEL_MGTQ BIT(4) -#define HQSEL_HIQ BIT(5) +#define HQSEL_VOQ BIT(0) +#define HQSEL_VIQ BIT(1) +#define HQSEL_BEQ BIT(2) +#define HQSEL_BKQ BIT(3) +#define HQSEL_MGTQ BIT(4) +#define HQSEL_HIQ BIT(5) /* For normal driver, 0x10C */ -#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) -#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) -#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) -#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) -#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) -#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) - -#define QUEUE_LOW 1 -#define QUEUE_NORMAL 2 -#define QUEUE_HIGH 3 - +#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) +#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) +#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) +#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) +#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) +#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) +#define QUEUE_LOW 1 +#define QUEUE_NORMAL 2 +#define QUEUE_HIGH 3 /* 2 TRXFF_BNDY */ - /* 2 LLT_INIT */ -#define _LLT_NO_ACTIVE 0x0 -#define _LLT_WRITE_ACCESS 0x1 -#define _LLT_READ_ACCESS 0x2 +#define _LLT_NO_ACTIVE 0x0 +#define _LLT_WRITE_ACCESS 0x1 +#define _LLT_READ_ACCESS 0x2 -#define _LLT_INIT_DATA(x) ((x) & 0xFF) -#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) -#define _LLT_OP(x) (((x) & 0x3) << 30) -#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) +#define _LLT_INIT_DATA(x) ((x) & 0xFF) +#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) +#define _LLT_OP(x) (((x) & 0x3) << 30) +#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) - -/* */ -/* */ /* 0x0200h ~ 0x027Fh TXDMA Configuration */ -/* */ -/* */ /* 2RQPN */ -#define _HPQ(x) ((x) & 0xFF) -#define _LPQ(x) (((x) & 0xFF) << 8) -#define _PUBQ(x) (((x) & 0xFF) << 16) -#define _NPQ(x) ((x) & 0xFF) /* NOTE: in RQPN_NPQ register */ - - -#define HPQ_PUBLIC_DIS BIT(24) -#define LPQ_PUBLIC_DIS BIT(25) -#define LD_RQPN BIT(31) +#define _HPQ(x) ((x) & 0xFF) +#define _LPQ(x) (((x) & 0xFF) << 8) +#define _PUBQ(x) (((x) & 0xFF) << 16) +/* NOTE: in RQPN_NPQ register */ +#define _NPQ(x) ((x) & 0xFF) +#define HPQ_PUBLIC_DIS BIT(24) +#define LPQ_PUBLIC_DIS BIT(25) +#define LD_RQPN BIT(31) /* 2TDECTRL */ -#define BCN_VALID BIT(16) -#define BCN_HEAD(x) (((x) & 0xFF) << 8) -#define BCN_HEAD_MASK 0xFF00 - +#define BCN_VALID BIT(16) +#define BCN_HEAD(x) (((x) & 0xFF) << 8) +#define BCN_HEAD_MASK 0xFF00 /* 2 TDECTL */ -#define BLK_DESC_NUM_SHIFT 4 -#define BLK_DESC_NUM_MASK 0xF - +#define BLK_DESC_NUM_SHIFT 4 +#define BLK_DESC_NUM_MASK 0xF /* 2 TXDMA_OFFSET_CHK */ -#define DROP_DATA_EN BIT(9) +#define DROP_DATA_EN BIT(9) - - - -/* */ -/* */ /* 0x0280h ~ 0x028Bh RX DMA Configuration */ -/* */ -/* */ /* REG_RXDMA_CONTROL, 0x0286h */ -/* Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before */ -/* this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. */ -/* define RXPKT_RELEASE_POLL BIT(0) */ -/* Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in */ -/* this bit. FW can start releasing packets after RXDMA entering idle mode. */ -/* define RXDMA_IDLE BIT(1) */ -/* When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host */ -/* completed, and stop DMA packet to host. RXDMA will then report Default: 0; */ -/* define RW_RELEASE_EN BIT(2) */ /* 2 REG_RXPKT_NUM, 0x0284 */ #define RXPKT_RELEASE_POLL BIT(16) -#define RXDMA_IDLE BIT(17) +#define RXDMA_IDLE BIT(17) #define RW_RELEASE_EN BIT(18) -/* */ -/* */ /* 0x0400h ~ 0x047Fh Protocol Configuration */ -/* */ -/* */ /* 2 FWHW_TXQ_CTRL */ -#define EN_AMPDU_RTY_NEW BIT(7) - +#define EN_AMPDU_RTY_NEW BIT(7) /* 2 SPEC SIFS */ -#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) -#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) +#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) +#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) /* 2 RL */ #define RETRY_LIMIT_SHORT_SHIFT 8 #define RETRY_LIMIT_LONG_SHIFT 0 - - - - -/* */ -/* */ /* 0x0500h ~ 0x05FFh EDCA Configuration */ -/* */ -/* */ - - /* 2 EDCA setting */ #define AC_PARAM_TXOP_LIMIT_OFFSET 16 #define AC_PARAM_ECW_MAX_OFFSET 12 #define AC_PARAM_ECW_MIN_OFFSET 8 -#define AC_PARAM_AIFS_OFFSET 0 - - - -#define _LRL(x) ((x) & 0x3F) -#define _SRL(x) (((x) & 0x3F) << 8) +#define AC_PARAM_AIFS_OFFSET 0 +#define _LRL(x) ((x) & 0x3F) +#define _SRL(x) (((x) & 0x3F) << 8) /* 2 BCN_CTRL */ -#define EN_MBSSID BIT(1) -#define EN_TXBCN_RPT BIT(2) -#define EN_BCN_FUNCTION BIT(3) -#define DIS_TSF_UPDATE BIT(3) +#define EN_MBSSID BIT(1) +#define EN_TXBCN_RPT BIT(2) +#define EN_BCN_FUNCTION BIT(3) +#define DIS_TSF_UPDATE BIT(3) /* The same function but different bit field. */ -#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) -#define DIS_TSF_UDT0_TEST_CHIP BIT(5) -#define STOP_BCNQ BIT(6) - +#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) +#define DIS_TSF_UDT0_TEST_CHIP BIT(5) +#define STOP_BCNQ BIT(6) /* 2 ACMHWCTRL */ -#define AcmHw_HwEn BIT(0) -#define AcmHw_BeqEn BIT(1) -#define AcmHw_ViqEn BIT(2) -#define AcmHw_VoqEn BIT(3) -#define AcmHw_BeqStatus BIT(4) -#define AcmHw_ViqStatus BIT(5) -#define AcmHw_VoqStatus BIT(6) +#define AcmHw_HwEn BIT(0) +#define AcmHw_BeqEn BIT(1) +#define AcmHw_ViqEn BIT(2) +#define AcmHw_VoqEn BIT(3) +#define AcmHw_BeqStatus BIT(4) +#define AcmHw_ViqStatus BIT(5) +#define AcmHw_VoqStatus BIT(6) - - -/* */ -/* */ /* 0x0600h ~ 0x07FFh WMAC Configuration */ -/* */ -/* */ /* 2APSD_CTRL */ -#define APSDOFF BIT(6) -#define APSDOFF_STATUS BIT(7) +#define APSDOFF BIT(6) +#define APSDOFF_STATUS BIT(7) - -#define RATE_BITMAP_ALL 0xFFFFF +#define RATE_BITMAP_ALL 0xFFFFF /* Only use CCK 1M rate for ACK */ -#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 +#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 /* 2 TCR */ -#define TSFRST BIT(0) -#define DIS_GCLK BIT(1) -#define PAD_SEL BIT(2) -#define PWR_ST BIT(6) -#define PWRBIT_OW_EN BIT(7) -#define ACRC BIT(8) -#define CFENDFORM BIT(9) -#define ICV BIT(10) - - +#define TSFRST BIT(0) +#define DIS_GCLK BIT(1) +#define PAD_SEL BIT(2) +#define PWR_ST BIT(6) +#define PWRBIT_OW_EN BIT(7) +#define ACRC BIT(8) +#define CFENDFORM BIT(9) +#define ICV BIT(10) /* 2 RCR */ -#define AAP BIT(0) -#define APM BIT(1) -#define AM BIT(2) -#define AB BIT(3) -#define ADD3 BIT(4) -#define APWRMGT BIT(5) -#define CBSSID BIT(6) -#define CBSSID_DATA BIT(6) -#define CBSSID_BCN BIT(7) -#define ACRC32 BIT(8) -#define AICV BIT(9) -#define ADF BIT(11) -#define ACF BIT(12) -#define AMF BIT(13) -#define HTC_LOC_CTRL BIT(14) -#define UC_DATA_EN BIT(16) -#define BM_DATA_EN BIT(17) -#define MFBEN BIT(22) -#define LSIGEN BIT(23) -#define EnMBID BIT(24) -#define APP_BASSN BIT(27) -#define APP_PHYSTS BIT(28) -#define APP_ICV BIT(29) -#define APP_MIC BIT(30) -#define APP_FCS BIT(31) - +#define AAP BIT(0) +#define APM BIT(1) +#define AM BIT(2) +#define AB BIT(3) +#define ADD3 BIT(4) +#define APWRMGT BIT(5) +#define CBSSID BIT(6) +#define CBSSID_DATA BIT(6) +#define CBSSID_BCN BIT(7) +#define ACRC32 BIT(8) +#define AICV BIT(9) +#define ADF BIT(11) +#define ACF BIT(12) +#define AMF BIT(13) +#define HTC_LOC_CTRL BIT(14) +#define UC_DATA_EN BIT(16) +#define BM_DATA_EN BIT(17) +#define MFBEN BIT(22) +#define LSIGEN BIT(23) +#define EnMBID BIT(24) +#define APP_BASSN BIT(27) +#define APP_PHYSTS BIT(28) +#define APP_ICV BIT(29) +#define APP_MIC BIT(30) +#define APP_FCS BIT(31) /* 2 SECCFG */ -#define SCR_TxUseDK BIT(0) /* Force Tx Use Default Key */ -#define SCR_RxUseDK BIT(1) /* Force Rx Use Default Key */ -#define SCR_TxEncEnable BIT(2) /* Enable Tx Encryption */ -#define SCR_RxDecEnable BIT(3) /* Enable Rx Decryption */ -#define SCR_SKByA2 BIT(4) /* Search kEY BY A2 */ -#define SCR_NoSKMC BIT(5) /* No Key Search Multicast */ -#define SCR_TXBCUSEDK BIT(6) /* Force Tx Broadcast packets Use Default Key */ -#define SCR_RXBCUSEDK BIT(7) /* Force Rx Broadcast packets Use Default Key */ +#define SCR_TxUseDK BIT(0) /* Force Tx Use Default Key */ +#define SCR_RxUseDK BIT(1) /* Force Rx Use Default Key */ +#define SCR_TxEncEnable BIT(2) /* Enable Tx Encryption */ +#define SCR_RxDecEnable BIT(3) /* Enable Rx Decryption */ +#define SCR_SKByA2 BIT(4) /* Search kEY BY A2 */ +#define SCR_NoSKMC BIT(5) /* No Key Search Multicast */ +#define SCR_TXBCUSEDK BIT(6) /* Force Tx Bcast pkt Use Default Key */ +#define SCR_RXBCUSEDK BIT(7) /* Force Rx Bcast pkt Use Default Key */ - -/* */ -/* */ /* RTL8188E SDIO Configuration */ -/* */ -/* */ /* I/O bus domain address mapping */ -#define SDIO_LOCAL_BASE 0x10250000 -#define WLAN_IOREG_BASE 0x10260000 -#define FIRMWARE_FIFO_BASE 0x10270000 -#define TX_HIQ_BASE 0x10310000 -#define TX_MIQ_BASE 0x10320000 -#define TX_LOQ_BASE 0x10330000 -#define RX_RX0FF_BASE 0x10340000 +#define SDIO_LOCAL_BASE 0x10250000 +#define WLAN_IOREG_BASE 0x10260000 +#define FIRMWARE_FIFO_BASE 0x10270000 +#define TX_HIQ_BASE 0x10310000 +#define TX_MIQ_BASE 0x10320000 +#define TX_LOQ_BASE 0x10330000 +#define RX_RX0FF_BASE 0x10340000 /* SDIO host local register space mapping. */ -#define SDIO_LOCAL_MSK 0x0FFF -#define WLAN_IOREG_MSK 0x7FFF -#define WLAN_FIFO_MSK 0x1FFF /* Aggregation Length[12:0] */ -#define WLAN_RX0FF_MSK 0x0003 +#define SDIO_LOCAL_MSK 0x0FFF +#define WLAN_IOREG_MSK 0x7FFF +#define WLAN_FIFO_MSK 0x1FFF /* Aggregation Length[12:0] */ +#define WLAN_RX0FF_MSK 0x0003 -#define SDIO_WITHOUT_REF_DEVICE_ID 0 /* Without reference to the SDIO Device ID */ -#define SDIO_LOCAL_DEVICE_ID 0 /* 0b[16], 000b[15:13] */ -#define WLAN_TX_HIQ_DEVICE_ID 4 /* 0b[16], 100b[15:13] */ -#define WLAN_TX_MIQ_DEVICE_ID 5 /* 0b[16], 101b[15:13] */ -#define WLAN_TX_LOQ_DEVICE_ID 6 /* 0b[16], 110b[15:13] */ -#define WLAN_RX0FF_DEVICE_ID 7 /* 0b[16], 111b[15:13] */ -#define WLAN_IOREG_DEVICE_ID 8 /* 1b[16] */ +/* Without ref to the SDIO Device ID */ +#define SDIO_WITHOUT_REF_DEVICE_ID 0 +#define SDIO_LOCAL_DEVICE_ID 0 /* 0b[16], 000b[15:13] */ +#define WLAN_TX_HIQ_DEVICE_ID 4 /* 0b[16], 100b[15:13] */ +#define WLAN_TX_MIQ_DEVICE_ID 5 /* 0b[16], 101b[15:13] */ +#define WLAN_TX_LOQ_DEVICE_ID 6 /* 0b[16], 110b[15:13] */ +#define WLAN_RX0FF_DEVICE_ID 7 /* 0b[16], 111b[15:13] */ +#define WLAN_IOREG_DEVICE_ID 8 /* 1b[16] */ /* SDIO Tx Free Page Index */ -#define HI_QUEUE_IDX 0 -#define MID_QUEUE_IDX 1 -#define LOW_QUEUE_IDX 2 -#define PUBLIC_QUEUE_IDX 3 +#define HI_QUEUE_IDX 0 +#define MID_QUEUE_IDX 1 +#define LOW_QUEUE_IDX 2 +#define PUBLIC_QUEUE_IDX 3 -#define SDIO_MAX_TX_QUEUE 3 /* HIQ, MIQ and LOQ */ -#define SDIO_MAX_RX_QUEUE 1 +#define SDIO_MAX_TX_QUEUE 3 /* HIQ, MIQ and LOQ */ +#define SDIO_MAX_RX_QUEUE 1 -#define SDIO_REG_TX_CTRL 0x0000 /* SDIO Tx Control */ -#define SDIO_REG_HIMR 0x0014 /* SDIO Host Interrupt Mask */ -#define SDIO_REG_HISR 0x0018 /* SDIO Host Interrupt Service Routine */ -#define SDIO_REG_HCPWM 0x0019 /* HCI Current Power Mode */ -#define SDIO_REG_RX0_REQ_LEN 0x001C /* RXDMA Request Length */ -#define SDIO_REG_FREE_TXPG 0x0020 /* Free Tx Buffer Page */ -#define SDIO_REG_HCPWM1 0x0024 /* HCI Current Power Mode 1 */ -#define SDIO_REG_HCPWM2 0x0026 /* HCI Current Power Mode 2 */ -#define SDIO_REG_HTSFR_INFO 0x0030 /* HTSF Informaion */ -#define SDIO_REG_HRPWM1 0x0080 /* HCI Request Power Mode 1 */ -#define SDIO_REG_HRPWM2 0x0082 /* HCI Request Power Mode 2 */ -#define SDIO_REG_HPS_CLKR 0x0084 /* HCI Power Save Clock */ -#define SDIO_REG_HSUS_CTRL 0x0086 /* SDIO HCI Suspend Control */ -#define SDIO_REG_HIMR_ON 0x0090 /* SDIO Host Extension Interrupt Mask Always */ -#define SDIO_REG_HISR_ON 0x0091 /* SDIO Host Extension Interrupt Status Always */ +/* SDIO Tx Control */ +#define SDIO_REG_TX_CTRL 0x0000 +/* SDIO Host Interrupt Mask */ +#define SDIO_REG_HIMR 0x0014 +/* SDIO Host Interrupt Service Routine */ +#define SDIO_REG_HISR 0x0018 +/* HCI Current Power Mode */ +#define SDIO_REG_HCPWM 0x0019 +/* RXDMA Request Length */ +#define SDIO_REG_RX0_REQ_LEN 0x001C +/* Free Tx Buffer Page */ +#define SDIO_REG_FREE_TXPG 0x0020 +/* HCI Current Power Mode 1 */ +#define SDIO_REG_HCPWM1 0x0024 +/* HCI Current Power Mode 2 */ +#define SDIO_REG_HCPWM2 0x0026 +/* HTSF Informaion */ +#define SDIO_REG_HTSFR_INFO 0x0030 +/* HCI Request Power Mode 1 */ +#define SDIO_REG_HRPWM1 0x0080 +/* HCI Request Power Mode 2 */ +#define SDIO_REG_HRPWM2 0x0082 +/* HCI Power Save Clock */ +#define SDIO_REG_HPS_CLKR 0x0084 +/* SDIO HCI Suspend Control */ +#define SDIO_REG_HSUS_CTRL 0x0086 +/* SDIO Host Extension Interrupt Mask Always */ +#define SDIO_REG_HIMR_ON 0x0090 +/* SDIO Host Extension Interrupt Status Always */ +#define SDIO_REG_HISR_ON 0x0091 #define SDIO_HIMR_DISABLED 0 @@ -1384,7 +1226,7 @@ Current IOREG MAP /* RTL8188E SDIO Specific */ #define SDIO_HIMR_MCU_ERR_MSK BIT28 -#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT29 +#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT29 /* SDIO Host Interrupt Service Routine */ #define SDIO_HISR_RX_REQUEST BIT0 @@ -1409,74 +1251,73 @@ Current IOREG MAP #define SDIO_HISR_CTWEND BIT27 /* RTL8188E SDIO Specific */ -#define SDIO_HISR_MCU_ERR BIT28 +#define SDIO_HISR_MCU_ERR BIT28 #define SDIO_HISR_TSF_BIT32_TOGGLE BIT29 -#define MASK_SDIO_HISR_CLEAR (SDIO_HISR_TXERR |\ - SDIO_HISR_RXERR |\ - SDIO_HISR_TXFOVW |\ - SDIO_HISR_RXFOVW |\ - SDIO_HISR_TXBCNOK |\ - SDIO_HISR_TXBCNERR |\ - SDIO_HISR_C2HCMD |\ - SDIO_HISR_CPWM1 |\ - SDIO_HISR_CPWM2 |\ - SDIO_HISR_HSISR_IND |\ - SDIO_HISR_GTINT3_IND |\ - SDIO_HISR_GTINT4_IND |\ - SDIO_HISR_PSTIMEOUT |\ - SDIO_HISR_OCPINT) +#define MASK_SDIO_HISR_CLEAR \ + (SDIO_HISR_TXERR | SDIO_HISR_RXERR | SDIO_HISR_TXFOVW |\ + SDIO_HISR_RXFOVW | SDIO_HISR_TXBCNOK | SDIO_HISR_TXBCNERR |\ + SDIO_HISR_C2HCMD | SDIO_HISR_CPWM1 | SDIO_HISR_CPWM2 |\ + SDIO_HISR_HSISR_IND | SDIO_HISR_GTINT3_IND | SDIO_HISR_GTINT4_IND |\ + SDIO_HISR_PSTIMEOUT | SDIO_HISR_OCPINT) /* SDIO HCI Suspend Control Register */ -#define HCI_RESUME_PWR_RDY BIT1 -#define HCI_SUS_CTRL BIT0 +#define HCI_RESUME_PWR_RDY BIT1 +#define HCI_SUS_CTRL BIT0 /* SDIO Tx FIFO related */ -#define SDIO_TX_FREE_PG_QUEUE 4 /* The number of Tx FIFO free page */ +/* The number of Tx FIFO free page */ +#define SDIO_TX_FREE_PG_QUEUE 4 #define SDIO_TX_FIFO_PAGE_SZ 128 -/* */ -/* */ /* 0xFE00h ~ 0xFE55h USB Configuration */ -/* */ -/* */ /* 2 USB Information (0xFE17) */ -#define USB_IS_HIGH_SPEED 0 -#define USB_IS_FULL_SPEED 1 -#define USB_SPEED_MASK BIT(5) +#define USB_IS_HIGH_SPEED 0 +#define USB_IS_FULL_SPEED 1 +#define USB_SPEED_MASK BIT(5) #define USB_NORMAL_SIE_EP_MASK 0xF #define USB_NORMAL_SIE_EP_SHIFT 4 - /* 2 Special Option */ -#define USB_AGG_EN BIT(3) +#define USB_AGG_EN BIT(3) /* 0; Use interrupt endpoint to upload interrupt pkt */ /* 1; Use bulk endpoint to upload interrupt pkt, */ -#define INT_BULK_SEL BIT(4) - - +#define INT_BULK_SEL BIT(4) /* 2REG_C2HEVT_CLEAR */ -#define C2H_EVT_HOST_CLOSE 0x00 /* Set by driver and notify FW that the driver has read the C2H command message */ -#define C2H_EVT_FW_CLOSE 0xFF /* Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. */ - +/* Set by driver and notify FW that the driver has read + * the C2H command message */ +#define C2H_EVT_HOST_CLOSE 0x00 +/* Set by FW indicating that FW had set the C2H command + * message and it's not yet read by driver. */ +#define C2H_EVT_FW_CLOSE 0xFF /* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */ -#define WL_HWPDN_EN BIT0 /* Enable GPIO[9] as WiFi HW PDn source */ -#define WL_HWPDN_SL BIT1 /* WiFi HW PDn polarity control */ -#define WL_FUNC_EN BIT2 /* WiFi function enable */ -#define WL_HWROF_EN BIT3 /* Enable GPIO[9] as WiFi RF HW PDn source */ -#define BT_HWPDN_EN BIT16 /* Enable GPIO[11] as BT HW PDn source */ -#define BT_HWPDN_SL BIT17 /* BT HW PDn polarity control */ -#define BT_FUNC_EN BIT18 /* BT function enable */ -#define BT_HWROF_EN BIT19 /* Enable GPIO[11] as BT/GPS RF HW PDn source */ -#define GPS_HWPDN_EN BIT20 /* Enable GPIO[10] as GPS HW PDn source */ -#define GPS_HWPDN_SL BIT21 /* GPS HW PDn polarity control */ -#define GPS_FUNC_EN BIT22 /* GPS function enable */ - +/* Enable GPIO[9] as WiFi HW PDn source */ +#define WL_HWPDN_EN BIT0 +/* WiFi HW PDn polarity control */ +#define WL_HWPDN_SL BIT1 +/* WiFi function enable */ +#define WL_FUNC_EN BIT2 +/* Enable GPIO[9] as WiFi RF HW PDn source */ +#define WL_HWROF_EN BIT3 +/* Enable GPIO[11] as BT HW PDn source */ +#define BT_HWPDN_EN BIT16 +/* BT HW PDn polarity control */ +#define BT_HWPDN_SL BIT17 +/* BT function enable */ +#define BT_FUNC_EN BIT18 +/* Enable GPIO[11] as BT/GPS RF HW PDn source */ +#define BT_HWROF_EN BIT19 +/* Enable GPIO[10] as GPS HW PDn source */ +#define GPS_HWPDN_EN BIT20 +/* GPS HW PDn polarity control */ +#define GPS_HWPDN_SL BIT21 +/* GPS function enable */ +#define GPS_FUNC_EN BIT22 /* 3 REG_LIFECTRL_CTRL */ #define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 @@ -1484,82 +1325,71 @@ Current IOREG MAP #define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 #define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 -#define HAL92C_MSDU_LIFE_TIME_UNIT 128 /* in us, said by Tim. */ +#define HAL92C_MSDU_LIFE_TIME_UNIT 128 /* in us */ -/* */ /* General definitions */ -/* */ #define LAST_ENTRY_OF_TX_PKT_BUFFER 176 /* 22k 22528 bytes */ -#define POLLING_LLT_THRESHOLD 20 +#define POLLING_LLT_THRESHOLD 20 #define POLLING_READY_TIMEOUT_COUNT 1000 /* GPIO BIT */ #define HAL_8192C_HW_GPIO_WPS_BIT BIT2 -/* */ -/* 8192C EEPROM/EFUSE share register definition. */ -/* */ +/* 8192C EEPROM/EFUSE share register definition. */ -/* */ -/* EEPROM/Efuse PG Offset for 88EE/88EU/88ES */ -/* */ -#define EEPROM_TX_PWR_INX_88E 0x10 +/* EEPROM/Efuse PG Offset for 88EE/88EU/88ES */ +#define EEPROM_TX_PWR_INX_88E 0x10 -#define EEPROM_ChannelPlan_88E 0xB8 -#define EEPROM_XTAL_88E 0xB9 -#define EEPROM_THERMAL_METER_88E 0xBA -#define EEPROM_IQK_LCK_88E 0xBB +#define EEPROM_ChannelPlan_88E 0xB8 +#define EEPROM_XTAL_88E 0xB9 +#define EEPROM_THERMAL_METER_88E 0xBA +#define EEPROM_IQK_LCK_88E 0xBB -#define EEPROM_RF_BOARD_OPTION_88E 0xC1 +#define EEPROM_RF_BOARD_OPTION_88E 0xC1 #define EEPROM_RF_FEATURE_OPTION_88E 0xC2 -#define EEPROM_RF_BT_SETTING_88E 0xC3 -#define EEPROM_VERSION_88E 0xC4 -#define EEPROM_CUSTOMERID_88E 0xC5 -#define EEPROM_RF_ANTENNA_OPT_88E 0xC9 +#define EEPROM_RF_BT_SETTING_88E 0xC3 +#define EEPROM_VERSION_88E 0xC4 +#define EEPROM_CUSTOMERID_88E 0xC5 +#define EEPROM_RF_ANTENNA_OPT_88E 0xC9 /* RTL88EE */ -#define EEPROM_MAC_ADDR_88EE 0xD0 -#define EEPROM_VID_88EE 0xD6 -#define EEPROM_DID_88EE 0xD8 -#define EEPROM_SVID_88EE 0xDA -#define EEPROM_SMID_88EE 0xDC +#define EEPROM_MAC_ADDR_88EE 0xD0 +#define EEPROM_VID_88EE 0xD6 +#define EEPROM_DID_88EE 0xD8 +#define EEPROM_SVID_88EE 0xDA +#define EEPROM_SMID_88EE 0xDC /* RTL88EU */ -#define EEPROM_MAC_ADDR_88EU 0xD7 -#define EEPROM_VID_88EU 0xD0 -#define EEPROM_PID_88EU 0xD2 -#define EEPROM_USB_OPTIONAL_FUNCTION0 0xD4 +#define EEPROM_MAC_ADDR_88EU 0xD7 +#define EEPROM_VID_88EU 0xD0 +#define EEPROM_PID_88EU 0xD2 +#define EEPROM_USB_OPTIONAL_FUNCTION0 0xD4 /* RTL88ES */ -#define EEPROM_MAC_ADDR_88ES 0x11A +#define EEPROM_MAC_ADDR_88ES 0x11A +/* EEPROM/Efuse Value Type */ +#define EETYPE_TX_PWR 0x0 - - -/* */ -/* EEPROM/Efuse Value Type */ -/* */ -#define EETYPE_TX_PWR 0x0 - -/* */ /* Default Value for EEPROM or EFUSE!!! */ -/* */ -#define EEPROM_Default_TSSI 0x0 -#define EEPROM_Default_TxPowerDiff 0x0 -#define EEPROM_Default_CrystalCap 0x5 -#define EEPROM_Default_BoardType 0x02 /* Default: 2X2, RTL8192CE(QFPN68) */ -#define EEPROM_Default_TxPower 0x1010 -#define EEPROM_Default_HT2T_TxPwr 0x10 +#define EEPROM_Default_TSSI 0x0 +#define EEPROM_Default_TxPowerDiff 0x0 +#define EEPROM_Default_CrystalCap 0x5 +/* Default: 2X2, RTL8192CE(QFPN68) */ +#define EEPROM_Default_BoardType 0x02 +#define EEPROM_Default_TxPower 0x1010 +#define EEPROM_Default_HT2T_TxPwr 0x10 #define EEPROM_Default_LegacyHTTxPowerDiff 0x3 -#define EEPROM_Default_ThermalMeter 0x12 +#define EEPROM_Default_ThermalMeter 0x12 #define EEPROM_Default_AntTxPowerDiff 0x0 #define EEPROM_Default_TxPwDiff_CrystalCap 0x5 -#define EEPROM_Default_TxPowerLevel 0x2A +#define EEPROM_Default_TxPowerLevel 0x2A -#define EEPROM_Default_HT40_2SDiff 0x0 -#define EEPROM_Default_HT20_Diff 2 /* HT20<->40 default Tx Power Index Difference */ +#define EEPROM_Default_HT40_2SDiff 0x0 +/* HT20<->40 default Tx Power Index Difference */ +#define EEPROM_Default_HT20_Diff 2 #define EEPROM_Default_LegacyHTTxPowerDiff 0x3 #define EEPROM_Default_HT40_PwrMaxOffset 0 #define EEPROM_Default_HT20_PwrMaxOffset 0 @@ -1568,50 +1398,48 @@ Current IOREG MAP #define EEPROM_Default_ThermalMeter_88E 0x18 /* New EFUSE deafult value */ -#define EEPROM_DEFAULT_24G_INDEX 0x2D +#define EEPROM_DEFAULT_24G_INDEX 0x2D #define EEPROM_DEFAULT_24G_HT20_DIFF 0X02 #define EEPROM_DEFAULT_24G_OFDM_DIFF 0X04 -#define EEPROM_DEFAULT_5G_INDEX 0X2A -#define EEPROM_DEFAULT_5G_HT20_DIFF 0X00 -#define EEPROM_DEFAULT_5G_OFDM_DIFF 0X04 +#define EEPROM_DEFAULT_5G_INDEX 0X2A +#define EEPROM_DEFAULT_5G_HT20_DIFF 0X00 +#define EEPROM_DEFAULT_5G_OFDM_DIFF 0X04 -#define EEPROM_DEFAULT_DIFF 0XFE -#define EEPROM_DEFAULT_CHANNEL_PLAN 0x7F -#define EEPROM_DEFAULT_BOARD_OPTION 0x00 -#define EEPROM_DEFAULT_FEATURE_OPTION 0x00 +#define EEPROM_DEFAULT_DIFF 0XFE +#define EEPROM_DEFAULT_CHANNEL_PLAN 0x7F +#define EEPROM_DEFAULT_BOARD_OPTION 0x00 +#define EEPROM_DEFAULT_FEATURE_OPTION 0x00 #define EEPROM_DEFAULT_BT_OPTION 0x10 - /* For debug */ -#define EEPROM_Default_PID 0x1234 -#define EEPROM_Default_VID 0x5678 -#define EEPROM_Default_CustomerID 0xAB +#define EEPROM_Default_PID 0x1234 +#define EEPROM_Default_VID 0x5678 +#define EEPROM_Default_CustomerID 0xAB #define EEPROM_Default_CustomerID_8188E 0x00 #define EEPROM_Default_SubCustomerID 0xCD -#define EEPROM_Default_Version 0 +#define EEPROM_Default_Version 0 -#define EEPROM_CHANNEL_PLAN_FCC 0x0 -#define EEPROM_CHANNEL_PLAN_IC 0x1 -#define EEPROM_CHANNEL_PLAN_ETSI 0x2 +#define EEPROM_CHANNEL_PLAN_FCC 0x0 +#define EEPROM_CHANNEL_PLAN_IC 0x1 +#define EEPROM_CHANNEL_PLAN_ETSI 0x2 #define EEPROM_CHANNEL_PLAN_SPA 0x3 -#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 -#define EEPROM_CHANNEL_PLAN_MKK 0x5 -#define EEPROM_CHANNEL_PLAN_MKK1 0x6 -#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 -#define EEPROM_CHANNEL_PLAN_TELEC 0x8 -#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMA 0x9 +#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 +#define EEPROM_CHANNEL_PLAN_MKK 0x5 +#define EEPROM_CHANNEL_PLAN_MKK1 0x6 +#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 +#define EEPROM_CHANNEL_PLAN_TELEC 0x8 +#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMA 0x9 #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA -#define EEPROM_CHANNEL_PLAN_NCC 0xB -#define EEPROM_USB_OPTIONAL1 0xE +#define EEPROM_CHANNEL_PLAN_NCC 0xB +#define EEPROM_USB_OPTIONAL1 0xE #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 - -#define EEPROM_CID_DEFAULT 0x0 -#define EEPROM_CID_TOSHIBA 0x4 -#define EEPROM_CID_CCX 0x10 /* CCX test. By Bruce, 2009-02-25. */ -#define EEPROM_CID_QMI 0x0D -#define EEPROM_CID_WHQL 0xFE /* added by chiyoko for dtm, 20090108 */ -#define RTL_EEPROM_ID 0x8129 +#define EEPROM_CID_DEFAULT 0x0 +#define EEPROM_CID_TOSHIBA 0x4 +#define EEPROM_CID_CCX 0x10 /* CCX test. */ +#define EEPROM_CID_QMI 0x0D +#define EEPROM_CID_WHQL 0xFE +#define RTL_EEPROM_ID 0x8129 #endif /* __RTL8188E_SPEC_H__ */ diff --git a/include/rtl8188e_sreset.h b/include/rtl8188e_sreset.h index 3ea4f62..a29e695 100644 --- a/include/rtl8188e_sreset.h +++ b/include/rtl8188e_sreset.h @@ -24,8 +24,8 @@ #include #include -extern void rtl8188e_silentreset_for_specific_platform(struct adapter *padapter); -extern void rtl8188e_sreset_xmit_status_check(struct adapter *padapter); -extern void rtl8188e_sreset_linked_status_check(struct adapter *padapter); +void rtl8188e_silentreset_for_specific_platform(struct adapter *padapter); +void rtl8188e_sreset_xmit_status_check(struct adapter *padapter); +void rtl8188e_sreset_linked_status_check(struct adapter *padapter); #endif diff --git a/include/rtl8188e_xmit.h b/include/rtl8188e_xmit.h index c237ebd..cf7267a 100644 --- a/include/rtl8188e_xmit.h +++ b/include/rtl8188e_xmit.h @@ -34,13 +34,20 @@ #define QSLT_CMD 0x13 /* For 88e early mode */ -#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value) -#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value) -#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value) -#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value) -#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value) -#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value) -#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value) +#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) \ + SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value) +#define SET_EARLYMODE_LEN0(__pAddr, __Value) \ + SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value) +#define SET_EARLYMODE_LEN1(__pAddr, __Value) \ + SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value) +#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) \ + SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value) +#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) \ + SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value) +#define SET_EARLYMODE_LEN3(__pAddr, __Value) \ + SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value) +#define SET_EARLYMODE_LEN4(__pAddr, __Value) \ + SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value) /* */ /* defined for TX DESC Operation */ @@ -59,50 +66,50 @@ /* OFFSET 4 */ #define PKT_OFFSET_SZ 0 -#define QSEL_SHT 8 -#define RATE_ID_SHT 16 -#define NAVUSEHDR BIT(20) +#define QSEL_SHT 8 +#define RATE_ID_SHT 16 +#define NAVUSEHDR BIT(20) #define SEC_TYPE_SHT 22 #define PKT_OFFSET_SHT 26 /* OFFSET 8 */ -#define AGG_EN BIT(12) -#define AGG_BK BIT(16) +#define AGG_EN BIT(12) +#define AGG_BK BIT(16) #define AMPDU_DENSITY_SHT 20 -#define ANTSEL_A BIT(24) -#define ANTSEL_B BIT(25) +#define ANTSEL_A BIT(24) +#define ANTSEL_B BIT(25) #define TX_ANT_CCK_SHT 26 -#define TX_ANTL_SHT 28 +#define TX_ANTL_SHT 28 #define TX_ANT_HT_SHT 30 /* OFFSET 12 */ -#define SEQ_SHT 16 -#define EN_HWSEQ BIT(31) +#define SEQ_SHT 16 +#define EN_HWSEQ BIT(31) /* OFFSET 16 */ -#define QOS BIT(6) -#define HW_SSN BIT(7) -#define USERATE BIT(8) -#define DISDATAFB BIT(10) -#define CTS_2_SELF BIT(11) -#define RTS_EN BIT(12) -#define HW_RTS_EN BIT(13) -#define DATA_SHORT BIT(24) -#define PWR_STATUS_SHT 15 -#define DATA_SC_SHT 20 -#define DATA_BW BIT(25) +#define QOS BIT(6) +#define HW_SSN BIT(7) +#define USERATE BIT(8) +#define DISDATAFB BIT(10) +#define CTS_2_SELF BIT(11) +#define RTS_EN BIT(12) +#define HW_RTS_EN BIT(13) +#define DATA_SHORT BIT(24) +#define PWR_STATUS_SHT 15 +#define DATA_SC_SHT 20 +#define DATA_BW BIT(25) /* OFFSET 20 */ -#define RTY_LMT_EN BIT(17) +#define RTY_LMT_EN BIT(17) -enum TXDESC_SC{ +enum TXDESC_SC { SC_DONT_CARE = 0x00, - SC_UPPER= 0x01, - SC_LOWER=0x02, - SC_DUPLICATE=0x03 + SC_UPPER = 0x01, + SC_LOWER = 0x02, + SC_DUPLICATE = 0x03 }; /* OFFSET 20 */ -#define SGI BIT(6) +#define SGI BIT(6) #define USB_TXAGG_NUM_SHT 24 #define txdesc_set_ccx_sw_88e(txdesc, value) \ @@ -146,21 +153,26 @@ struct txrpt_ccx_88e { }; #define txrpt_ccx_sw_88e(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8)) -#define txrpt_ccx_qtime_88e(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8)) +#define txrpt_ccx_qtime_88e(txrpt_ccx) \ + ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8)) -void rtl8188e_fill_fake_txdesc(struct adapter * padapter,u8*pDesc,u32 BufferLen,u8 IsPsPoll,u8 IsBTQosNull); -s32 rtl8188eu_init_xmit_priv(struct adapter * padapter); -void rtl8188eu_free_xmit_priv(struct adapter * padapter); -s32 rtl8188eu_hal_xmit(struct adapter * padapter, struct xmit_frame *pxmitframe); -s32 rtl8188eu_mgnt_xmit(struct adapter * padapter, struct xmit_frame *pmgntframe); -s32 rtl8188eu_xmit_buf_handler(struct adapter * padapter); +void rtl8188e_fill_fake_txdesc(struct adapter *padapter, u8 *pDesc, + u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull); +s32 rtl8188eu_init_xmit_priv(struct adapter *padapter); +void rtl8188eu_free_xmit_priv(struct adapter *padapter); +s32 rtl8188eu_hal_xmit(struct adapter *padapter, struct xmit_frame *frame); +s32 rtl8188eu_mgnt_xmit(struct adapter *padapter, struct xmit_frame *frame); +s32 rtl8188eu_xmit_buf_handler(struct adapter *padapter); #define hal_xmit_handler rtl8188eu_xmit_buf_handler void rtl8188eu_xmit_tasklet(void *priv); -s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); +s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, + struct xmit_priv *pxmitpriv, + struct xmit_buf *pxmitbuf); void dump_txrpt_ccx_88e(void *buf); void handle_txrpt_ccx_88e(struct adapter *adapter, u8 *buf); -void _dbg_dump_tx_info(struct adapter *padapter,int frame_tag,struct tx_desc *ptxdesc); +void _dbg_dump_tx_info(struct adapter *padapter, int frame_tag, + struct tx_desc *ptxdesc); #endif /* __RTL8188E_XMIT_H__ */ diff --git a/include/rtw_ap.h b/include/rtw_ap.h index 6b0f78e..0826066 100644 --- a/include/rtw_ap.h +++ b/include/rtw_ap.h @@ -26,17 +26,20 @@ #ifdef CONFIG_AP_MODE /* external function */ -extern void rtw_indicate_sta_assoc_event(struct adapter *padapter, struct sta_info *psta); -extern void rtw_indicate_sta_disassoc_event(struct adapter *padapter, struct sta_info *psta); - - +void rtw_indicate_sta_assoc_event(struct adapter *padapter, + struct sta_info *psta); +void rtw_indicate_sta_disassoc_event(struct adapter *padapter, + struct sta_info *psta); void init_mlme_ap_info(struct adapter *padapter); void free_mlme_ap_info(struct adapter *padapter); -/* void update_BCNTIM(struct adapter *padapter); */ -void rtw_add_bcn_ie(struct adapter *padapter, struct wlan_bssid_ex *pnetwork, u8 index, u8 *data, u8 len); -void rtw_remove_bcn_ie(struct adapter *padapter, struct wlan_bssid_ex *pnetwork, u8 index); -void update_beacon(struct adapter *padapter, u8 ie_id, u8 *oui, u8 tx); -void add_RATid(struct adapter *padapter, struct sta_info *psta, u8 rssi_level); +void rtw_add_bcn_ie(struct adapter *padapter, struct wlan_bssid_ex *pnetwork, + u8 index, u8 *data, u8 len); +void rtw_remove_bcn_ie(struct adapter *padapter, + struct wlan_bssid_ex *pnetwork, u8 index); +void update_beacon(struct adapter *padapter, u8 ie_id, + u8 *oui, u8 tx); +void add_RATid(struct adapter *padapter, struct sta_info *psta, + u8 rssi_level); void expire_timeout_chk(struct adapter *padapter); void update_sta_info_apmode(struct adapter *padapter, struct sta_info *psta); int rtw_check_beacon_data(struct adapter *padapter, u8 *pbuf, int len); @@ -50,9 +53,10 @@ void bss_cap_update_on_sta_join(struct adapter *padapter, struct sta_info *psta) u8 bss_cap_update_on_sta_leave(struct adapter *padapter, struct sta_info *psta); void sta_info_update(struct adapter *padapter, struct sta_info *psta); void ap_sta_info_defer_update(struct adapter *padapter, struct sta_info *psta); -u8 ap_free_sta(struct adapter *padapter, struct sta_info *psta, bool active, u16 reason); +u8 ap_free_sta(struct adapter *padapter, struct sta_info *psta, + bool active, u16 reason); int rtw_sta_flush(struct adapter *padapter); -int rtw_ap_inform_ch_switch (struct adapter *padapter, u8 new_ch, u8 ch_offset); +int rtw_ap_inform_ch_switch(struct adapter *padapter, u8 new_ch, u8 ch_offset); void start_ap_mode(struct adapter *padapter); void stop_ap_mode(struct adapter *padapter); #endif diff --git a/include/rtw_br_ext.h b/include/rtw_br_ext.h index 6c671dc..136abcb 100644 --- a/include/rtw_br_ext.h +++ b/include/rtw_br_ext.h @@ -56,7 +56,7 @@ struct br_ext_info { unsigned int nat25_disable; unsigned int macclone_enable; unsigned int dhcp_bcst_disable; - int addPPPoETag; /* 1: Add PPPoE relay-SID, 0: disable */ + int addPPPoETag; /* 1: Add PPPoE relay-SID, 0: disable */ unsigned char nat25_dmzMac[MACADDRLEN]; unsigned int nat25sc_disable; }; diff --git a/include/rtw_cmd.h b/include/rtw_cmd.h index 0ed39e7..5891862 100644 --- a/include/rtw_cmd.h +++ b/include/rtw_cmd.h @@ -29,7 +29,6 @@ #include #include /* */ - #define FREE_CMDOBJ_SZ 128 #define MAX_CMDSZ 1024 @@ -81,7 +80,7 @@ do {\ _rtw_init_listhead(&pcmd->list);\ pcmd->cmdcode = code;\ pcmd->parmbuf = (u8 *)(pparm);\ - pcmd->cmdsz = sizeof (*pparm);\ + pcmd->cmdsz = sizeof(*pparm);\ pcmd->rsp = NULL;\ pcmd->rspsz = 0;\ } while (0) @@ -95,25 +94,24 @@ struct c2h_evt_hdr { #define c2h_evt_exist(c2h_evt) ((c2h_evt)->id || (c2h_evt)->plen) -extern u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *obj); -extern struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv); -extern void rtw_free_cmd_obj(struct cmd_obj *pcmd); +u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *obj); +struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv); +void rtw_free_cmd_obj(struct cmd_obj *pcmd); int rtw_cmd_thread(void *context); -extern u32 rtw_init_cmd_priv (struct cmd_priv *pcmdpriv); -extern void rtw_free_cmd_priv (struct cmd_priv *pcmdpriv); +u32 rtw_init_cmd_priv(struct cmd_priv *pcmdpriv); +void rtw_free_cmd_priv(struct cmd_priv *pcmdpriv); -extern u32 rtw_init_evt_priv (struct evt_priv *pevtpriv); -extern void rtw_free_evt_priv (struct evt_priv *pevtpriv); -extern void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv); -extern void rtw_evt_notify_isr(struct evt_priv *pevtpriv); +u32 rtw_init_evt_priv(struct evt_priv *pevtpriv); +void rtw_free_evt_priv(struct evt_priv *pevtpriv); +void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv); +void rtw_evt_notify_isr(struct evt_priv *pevtpriv); #ifdef CONFIG_P2P -u8 p2p_protocol_wk_cmd(struct adapter*padapter, int intCmdType ); +u8 p2p_protocol_wk_cmd(struct adapter *padapter, int intCmdType); #endif /* CONFIG_P2P */ -enum rtw_drvextra_cmd_id -{ +enum rtw_drvextra_cmd_id { NONE_WK_CID, DYNAMIC_CHK_WK_CID, DM_CTRL_WK_CID, @@ -130,14 +128,13 @@ enum rtw_drvextra_cmd_id MAX_WK_CID }; -enum LPS_CTRL_TYPE -{ - LPS_CTRL_SCAN=0, - LPS_CTRL_JOINBSS=1, - LPS_CTRL_CONNECT=2, - LPS_CTRL_DISCONNECT=3, - LPS_CTRL_SPECIAL_PACKET=4, - LPS_CTRL_LEAVE=5, +enum LPS_CTRL_TYPE { + LPS_CTRL_SCAN = 0, + LPS_CTRL_JOINBSS = 1, + LPS_CTRL_CONNECT = 2, + LPS_CTRL_DISCONNECT = 3, + LPS_CTRL_SPECIAL_PACKET = 4, + LPS_CTRL_LEAVE = 5, }; enum RFINTFS { @@ -253,11 +250,12 @@ when 802.1x ==> keyid > 2 ==> unicast key */ struct setkey_parm { - u8 algorithm; /* encryption algorithm, could be none, wep40, TKIP, CCMP, wep104 */ + u8 algorithm; /* could be none, wep40, TKIP, CCMP, wep104 */ u8 keyid; - u8 grpkey; /* 1: this is the grpkey for 802.1x. 0: this is the unicast key for 802.1x */ - u8 set_tx; /* 1: main tx key for wep. 0: other key. */ - u8 key[16]; /* this could be 40 or 104 */ + u8 grpkey; /* 1: this is the grpkey for 802.1x. + * 0: this is the unicast key for 802.1x */ + u8 set_tx; /* 1: main tx key for wep. 0: other key. */ + u8 key[16]; /* this could be 40 or 104 */ }; /* @@ -272,7 +270,8 @@ when shared key ==> algorithm/keyid struct set_stakey_parm { u8 addr[ETH_ALEN]; u8 algorithm; - u8 id;/* currently for erasing cam entry if algorithm == _NO_PRIVACY_ */ + u8 id;/* currently for erasing cam entry if + * algorithm == _NO_PRIVACY_ */ u8 key[16]; }; @@ -386,7 +385,6 @@ struct getdatarate_rsp { u8 datarates[NumRates]; }; - /* Caller Mode: Any AP: AP can use the info for the contents of beacon frame @@ -394,7 +392,6 @@ Infra: STA can use the info when sitesurveying Ad-HoC(M): Like AP Ad-HoC(C): Like STA - Notes: To set the phy capability of the NIC Command Mode @@ -481,7 +478,6 @@ struct getrfintfs_parm { u8 rfintfs; }; - struct Tx_Beacon_param { struct wlan_bssid_ex network; @@ -522,7 +518,7 @@ struct Tx_Beacon_param event: parm: mac[0] = mac[5]; mac[1] = mac[4]; - mac[2] = event's sequence number, starting from 1 to parm's marc[3] + mac[2] = event's seq no, starting from 1 to parm's marc[3] mac[3] = mac[2]; mac[4] = mac[1]; mac[5] = mac[0]; @@ -535,10 +531,7 @@ struct Tx_Beacon_param w1 = swap32(w1) - event.mac[2]; parm->mac[3] is the total event counts that host requested. - - event will be the same with the cmd's param. - */ /* CMD param Format for driver extra cmd handler */ @@ -576,7 +569,6 @@ struct setagcctrl_parm { u32 agcctrl; /* 0: pure hw, 1: fw */ }; - struct setssup_parm { u32 ss_ForceUp[MAX_RATES_LENGTH]; }; @@ -584,11 +576,11 @@ struct setssup_parm { struct getssup_parm { u32 rsvd; }; + struct getssup_rsp { u8 ss_ForceUp[MAX_RATES_LENGTH]; }; - struct setssdlevel_parm { u8 ss_DLevel[MAX_RATES_LENGTH]; }; @@ -596,6 +588,7 @@ struct setssdlevel_parm { struct getssdlevel_parm { u32 rsvd; }; + struct getssdlevel_rsp { u8 ss_DLevel[MAX_RATES_LENGTH]; }; @@ -607,11 +600,11 @@ struct setssulevel_parm { struct getssulevel_parm { u32 rsvd; }; + struct getssulevel_rsp { u8 ss_ULevel[MAX_RATES_LENGTH]; }; - struct setcountjudge_parm { u8 count_judge[MAX_RATES_LENGTH]; }; @@ -619,11 +612,11 @@ struct setcountjudge_parm { struct getcountjudge_parm { u32 rsvd; }; + struct getcountjudge_rsp { u8 count_judge[MAX_RATES_LENGTH]; }; - struct setratable_parm { u8 ss_ForceUp[NumRates]; u8 ss_ULevel[NumRates]; @@ -634,6 +627,7 @@ struct setratable_parm { struct getratable_parm { uint rsvd; }; + struct getratable_rsp { u8 ss_ForceUp[NumRates]; u8 ss_ULevel[NumRates]; @@ -641,42 +635,46 @@ struct getratable_rsp { u8 count_judge[NumRates]; }; - /* to get TX,RX retry count */ -struct gettxretrycnt_parm{ + +struct gettxretrycnt_parm { unsigned int rsvd; }; -struct gettxretrycnt_rsp{ + +struct gettxretrycnt_rsp { unsigned long tx_retrycnt; }; -struct getrxretrycnt_parm{ +struct getrxretrycnt_parm { unsigned int rsvd; }; -struct getrxretrycnt_rsp{ + +struct getrxretrycnt_rsp { unsigned long rx_retrycnt; }; /* to get BCNOK,BCNERR count */ -struct getbcnokcnt_parm{ +struct getbcnokcnt_parm { unsigned int rsvd; }; -struct getbcnokcnt_rsp{ + +struct getbcnokcnt_rsp { unsigned long bcnokcnt; }; -struct getbcnerrcnt_parm{ +struct getbcnerrcnt_parm { unsigned int rsvd; }; -struct getbcnerrcnt_rsp{ + +struct getbcnerrcnt_rsp { unsigned long bcnerrcnt; }; /* to get current TX power level */ -struct getcurtxpwrlevel_parm{ +struct getcurtxpwrlevel_parm { unsigned int rsvd; }; -struct getcurtxpwrlevel_rsp{ +struct getcurtxpwrlevel_rspi { unsigned short tx_power; }; @@ -704,9 +702,7 @@ struct setassocrspextraie_parm { unsigned char ie[0]; }; - -struct addBaReq_parm -{ +struct addBaReq_parm { unsigned int tid; u8 addr[ETH_ALEN]; }; @@ -727,7 +723,7 @@ struct SetChannelPlan_param /*H2C Handler index: 60 */ struct LedBlink_param { - struct LED_871x * pLed; + struct LED_871x *pLed; }; /*H2C Handler index: 61 */ @@ -745,7 +741,6 @@ struct TDLSoption_param #define GEN_CMD_CODE(cmd) cmd ## _CMD_ - /* Result: @@ -757,134 +752,136 @@ Result: */ -#define H2C_RSP_OFFSET 512 +#define H2C_RSP_OFFSET 512 -#define H2C_SUCCESS 0x00 -#define H2C_SUCCESS_RSP 0x01 -#define H2C_DUPLICATED 0x02 -#define H2C_DROPPED 0x03 -#define H2C_PARAMETERS_ERROR 0x04 -#define H2C_REJECTED 0x05 -#define H2C_CMD_OVERFLOW 0x06 -#define H2C_RESERVED 0x07 +#define H2C_SUCCESS 0x00 +#define H2C_SUCCESS_RSP 0x01 +#define H2C_DUPLICATED 0x02 +#define H2C_DROPPED 0x03 +#define H2C_PARAMETERS_ERROR 0x04 +#define H2C_REJECTED 0x05 +#define H2C_CMD_OVERFLOW 0x06 +#define H2C_RESERVED 0x07 -extern u8 rtw_setassocsta_cmd(struct adapter *padapter, u8 *mac_addr); -extern u8 rtw_setstandby_cmd(struct adapter *padapter, uint action); -u8 rtw_sitesurvey_cmd(struct adapter *padapter, struct ndis_802_11_ssid *ssid, int ssid_num, struct rtw_ieee80211_channel *ch, int ch_num); -extern u8 rtw_createbss_cmd(struct adapter *padapter); -extern u8 rtw_createbss_cmd_ex(struct adapter *padapter, unsigned char *pbss, unsigned int sz); -extern u8 rtw_setphy_cmd(struct adapter *padapter, u8 modem, u8 ch); -extern u8 rtw_setstakey_cmd(struct adapter *padapter, u8 *psta, u8 unicast_key); -extern u8 rtw_clearstakey_cmd(struct adapter *padapter, u8 *psta, u8 entry, u8 enqueue); -extern u8 rtw_joinbss_cmd(struct adapter *padapter, struct wlan_network* pnetwork); +u8 rtw_setassocsta_cmd(struct adapter *padapter, u8 *mac_addr); +u8 rtw_setstandby_cmd(struct adapter *padapter, uint action); +u8 rtw_sitesurvey_cmd(struct adapter *padapter, struct ndis_802_11_ssid *ssid, + int ssid_num, struct rtw_ieee80211_channel *ch, + int ch_num); +u8 rtw_createbss_cmd(struct adapter *padapter); +u8 rtw_createbss_cmd_ex(struct adapter *padapter, unsigned char *pbss, + unsigned int sz); +u8 rtw_setphy_cmd(struct adapter *padapter, u8 modem, u8 ch); +u8 rtw_setstakey_cmd(struct adapter *padapter, u8 *psta, u8 unicast_key); +u8 rtw_clearstakey_cmd(struct adapter *padapter, u8 *psta, u8 entry, u8 enqueue); +u8 rtw_joinbss_cmd(struct adapter *padapter, struct wlan_network* pnetwork); u8 rtw_disassoc_cmd(struct adapter *padapter, u32 deauth_timeout_ms, bool enqueue); -extern u8 rtw_setopmode_cmd(struct adapter *padapter, enum ndis_802_11_network_infra networktype); -extern u8 rtw_setdatarate_cmd(struct adapter *padapter, u8 *rateset); -extern u8 rtw_setbasicrate_cmd(struct adapter *padapter, u8 *rateset); -extern u8 rtw_setbbreg_cmd(struct adapter * padapter, u8 offset, u8 val); -extern u8 rtw_setrfreg_cmd(struct adapter * padapter, u8 offset, u32 val); -extern u8 rtw_getbbreg_cmd(struct adapter * padapter, u8 offset, u8 * pval); -extern u8 rtw_getrfreg_cmd(struct adapter * padapter, u8 offset, u8 * pval); -extern u8 rtw_setrfintfs_cmd(struct adapter *padapter, u8 mode); -extern u8 rtw_setrttbl_cmd(struct adapter *padapter, struct setratable_parm *prate_table); -extern u8 rtw_getrttbl_cmd(struct adapter *padapter, struct getratable_rsp *pval); +u8 rtw_setopmode_cmd(struct adapter *padapter, enum ndis_802_11_network_infra networktype); +u8 rtw_setdatarate_cmd(struct adapter *padapter, u8 *rateset); +u8 rtw_setbasicrate_cmd(struct adapter *padapter, u8 *rateset); +u8 rtw_setbbreg_cmd(struct adapter * padapter, u8 offset, u8 val); +u8 rtw_setrfreg_cmd(struct adapter * padapter, u8 offset, u32 val); +u8 rtw_getbbreg_cmd(struct adapter * padapter, u8 offset, u8 * pval); +u8 rtw_getrfreg_cmd(struct adapter * padapter, u8 offset, u8 * pval); +u8 rtw_setrfintfs_cmd(struct adapter *padapter, u8 mode); +u8 rtw_setrttbl_cmd(struct adapter *padapter, struct setratable_parm *prate_table); +u8 rtw_getrttbl_cmd(struct adapter *padapter, struct getratable_rsp *pval); -extern u8 rtw_gettssi_cmd(struct adapter *padapter, u8 offset,u8 *pval); -extern u8 rtw_setfwdig_cmd(struct adapter*padapter, u8 type); -extern u8 rtw_setfwra_cmd(struct adapter*padapter, u8 type); +u8 rtw_gettssi_cmd(struct adapter *padapter, u8 offset,u8 *pval); +u8 rtw_setfwdig_cmd(struct adapter*padapter, u8 type); +u8 rtw_setfwra_cmd(struct adapter*padapter, u8 type); -extern u8 rtw_addbareq_cmd(struct adapter*padapter, u8 tid, u8 *addr); +u8 rtw_addbareq_cmd(struct adapter*padapter, u8 tid, u8 *addr); -extern u8 rtw_dynamic_chk_wk_cmd(struct adapter *adapter); +u8 rtw_dynamic_chk_wk_cmd(struct adapter *adapter); u8 rtw_lps_ctrl_wk_cmd(struct adapter*padapter, u8 lps_ctrl_type, u8 enqueue); u8 rtw_rpt_timer_cfg_cmd(struct adapter*padapter, u16 minRptTime); -extern u8 rtw_antenna_select_cmd(struct adapter*padapter, u8 antenna,u8 enqueue); -extern u8 rtw_ps_cmd(struct adapter*padapter); + u8 rtw_antenna_select_cmd(struct adapter*padapter, u8 antenna,u8 enqueue); +u8 rtw_ps_cmd(struct adapter*padapter); #ifdef CONFIG_AP_MODE u8 rtw_chk_hi_queue_cmd(struct adapter*padapter); #endif u8 rtw_set_ch_cmd(struct adapter*padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue); -extern u8 rtw_set_chplan_cmd(struct adapter*padapter, u8 chplan, u8 enqueue); -extern u8 rtw_led_blink_cmd(struct adapter*padapter, struct LED_871x * pLed); -extern u8 rtw_set_csa_cmd(struct adapter*padapter, u8 new_ch_no); -extern u8 rtw_tdls_cmd(struct adapter *padapter, u8 *addr, u8 option); +u8 rtw_set_chplan_cmd(struct adapter*padapter, u8 chplan, u8 enqueue); +u8 rtw_led_blink_cmd(struct adapter*padapter, struct LED_871x * pLed); +u8 rtw_set_csa_cmd(struct adapter*padapter, u8 new_ch_no); +u8 rtw_tdls_cmd(struct adapter *padapter, u8 *addr, u8 option); -extern u8 rtw_c2h_wk_cmd(struct adapter *padapter, u8 *c2h_evt); +u8 rtw_c2h_wk_cmd(struct adapter *padapter, u8 *c2h_evt); u8 rtw_drvextra_cmd_hdl(struct adapter *padapter, unsigned char *pbuf); -extern void rtw_survey_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd); -extern void rtw_disassoc_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd); -extern void rtw_joinbss_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd); -extern void rtw_createbss_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd); -extern void rtw_getbbrfreg_cmdrsp_callback(struct adapter *padapter, struct cmd_obj *pcmd); -extern void rtw_readtssi_cmdrsp_callback(struct adapter *padapter, struct cmd_obj *pcmd); +void rtw_survey_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd); +void rtw_disassoc_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd); +void rtw_joinbss_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd); +void rtw_createbss_cmd_callback(struct adapter *adapt, struct cmd_obj *pcmd); +void rtw_getbbrfreg_cmdrsp_callback(struct adapter *adapt, struct cmd_obj *cmd); +void rtw_readtssi_cmdrsp_callback(struct adapter *adapt, struct cmd_obj *cmd); -extern void rtw_setstaKey_cmdrsp_callback(struct adapter *padapter, struct cmd_obj *pcmd); -extern void rtw_setassocsta_cmdrsp_callback(struct adapter *padapter, struct cmd_obj *pcmd); -extern void rtw_getrttbl_cmdrsp_callback(struct adapter *padapter, struct cmd_obj *pcmd); +void rtw_setstaKey_cmdrsp_callback(struct adapter *adapt, struct cmd_obj *cmd); +void rtw_setassocsta_cmdrsp_callback(struct adapter *adapt, struct cmd_obj *cm); +void rtw_getrttbl_cmdrsp_callback(struct adapter *adapt, struct cmd_obj *cmd); struct _cmd_callback { u32 cmd_code; void (*callback)(struct adapter *padapter, struct cmd_obj *cmd); }; -enum rtw_h2c_cmd -{ - GEN_CMD_CODE(_Read_MACREG) , /*0*/ - GEN_CMD_CODE(_Write_MACREG) , - GEN_CMD_CODE(_Read_BBREG) , - GEN_CMD_CODE(_Write_BBREG) , - GEN_CMD_CODE(_Read_RFREG) , - GEN_CMD_CODE(_Write_RFREG) , /*5*/ - GEN_CMD_CODE(_Read_EEPROM) , - GEN_CMD_CODE(_Write_EEPROM) , - GEN_CMD_CODE(_Read_EFUSE) , - GEN_CMD_CODE(_Write_EFUSE) , +enum rtw_h2c_cmd { + GEN_CMD_CODE(_Read_MACREG), /*0*/ + GEN_CMD_CODE(_Write_MACREG), + GEN_CMD_CODE(_Read_BBREG), + GEN_CMD_CODE(_Write_BBREG), + GEN_CMD_CODE(_Read_RFREG), + GEN_CMD_CODE(_Write_RFREG), /*5*/ + GEN_CMD_CODE(_Read_EEPROM), + GEN_CMD_CODE(_Write_EEPROM), + GEN_CMD_CODE(_Read_EFUSE), + GEN_CMD_CODE(_Write_EFUSE), - GEN_CMD_CODE(_Read_CAM) , /*10*/ - GEN_CMD_CODE(_Write_CAM) , + GEN_CMD_CODE(_Read_CAM), /*10*/ + GEN_CMD_CODE(_Write_CAM), GEN_CMD_CODE(_setBCNITV), GEN_CMD_CODE(_setMBIDCFG), GEN_CMD_CODE(_JoinBss), /*14*/ - GEN_CMD_CODE(_DisConnect) , /*15*/ - GEN_CMD_CODE(_CreateBss) , - GEN_CMD_CODE(_SetOpMode) , + GEN_CMD_CODE(_DisConnect), /*15*/ + GEN_CMD_CODE(_CreateBss), + GEN_CMD_CODE(_SetOpMode), GEN_CMD_CODE(_SiteSurvey), /*18*/ - GEN_CMD_CODE(_SetAuth) , + GEN_CMD_CODE(_SetAuth), - GEN_CMD_CODE(_SetKey) , /*20*/ - GEN_CMD_CODE(_SetStaKey) , - GEN_CMD_CODE(_SetAssocSta) , - GEN_CMD_CODE(_DelAssocSta) , - GEN_CMD_CODE(_SetStaPwrState) , - GEN_CMD_CODE(_SetBasicRate) , /*25*/ - GEN_CMD_CODE(_GetBasicRate) , - GEN_CMD_CODE(_SetDataRate) , - GEN_CMD_CODE(_GetDataRate) , - GEN_CMD_CODE(_SetPhyInfo) , + GEN_CMD_CODE(_SetKey), /*20*/ + GEN_CMD_CODE(_SetStaKey), + GEN_CMD_CODE(_SetAssocSta), + GEN_CMD_CODE(_DelAssocSta), + GEN_CMD_CODE(_SetStaPwrState), + GEN_CMD_CODE(_SetBasicRate), /*25*/ + GEN_CMD_CODE(_GetBasicRate), + GEN_CMD_CODE(_SetDataRate), + GEN_CMD_CODE(_GetDataRate), + GEN_CMD_CODE(_SetPhyInfo), - GEN_CMD_CODE(_GetPhyInfo) , /*30*/ - GEN_CMD_CODE(_SetPhy) , - GEN_CMD_CODE(_GetPhy) , - GEN_CMD_CODE(_readRssi) , - GEN_CMD_CODE(_readGain) , - GEN_CMD_CODE(_SetAtim) , /*35*/ - GEN_CMD_CODE(_SetPwrMode) , + GEN_CMD_CODE(_GetPhyInfo), /*30*/ + GEN_CMD_CODE(_SetPhy), + GEN_CMD_CODE(_GetPhy), + GEN_CMD_CODE(_readRssi), + GEN_CMD_CODE(_readGain), + GEN_CMD_CODE(_SetAtim), /*35*/ + GEN_CMD_CODE(_SetPwrMode), GEN_CMD_CODE(_JoinbssRpt), - GEN_CMD_CODE(_SetRaTable) , - GEN_CMD_CODE(_GetRaTable) , + GEN_CMD_CODE(_SetRaTable), + GEN_CMD_CODE(_GetRaTable), GEN_CMD_CODE(_GetCCXReport), /*40*/ GEN_CMD_CODE(_GetDTMReport), GEN_CMD_CODE(_GetTXRateStatistics), GEN_CMD_CODE(_SetUsbSuspend), GEN_CMD_CODE(_SetH2cLbk), - GEN_CMD_CODE(_AddBAReq) , /*45*/ + GEN_CMD_CODE(_AddBAReq), /*45*/ GEN_CMD_CODE(_SetChannel), /*46*/ GEN_CMD_CODE(_SetTxPower), GEN_CMD_CODE(_SwitchAntenna), @@ -960,7 +957,7 @@ static struct _cmd_callback rtw_cmd_callback[] = {GEN_CMD_CODE(_SetPwrMode), NULL}, {GEN_CMD_CODE(_JoinbssRpt), NULL}, {GEN_CMD_CODE(_SetRaTable), NULL}, - {GEN_CMD_CODE(_GetRaTable) , NULL}, + {GEN_CMD_CODE(_GetRaTable), NULL}, {GEN_CMD_CODE(_GetCCXReport), NULL}, /*40*/ {GEN_CMD_CODE(_GetDTMReport), NULL}, diff --git a/include/rtw_debug.h b/include/rtw_debug.h index 0e46268..a223d55 100644 --- a/include/rtw_debug.h +++ b/include/rtw_debug.h @@ -78,9 +78,9 @@ extern u32 GlobalDebugLevel; -#define DBG_88E_LEVEL(_Level, fmt, arg...) \ +#define DBG_88E_LEVEL(_level, fmt, arg...) \ do { \ - if (_Level <= GlobalDebugLevel) \ + if (_level <= GlobalDebugLevel) \ _dbgdump(DRIVER_PREFIX"ERROR " fmt, ##arg); \ } while (0) @@ -96,12 +96,12 @@ extern u32 GlobalDebugLevel; _dbgdump(DRIVER_PREFIX __VA_ARGS__); \ } while (0) -#define RT_TRACE(_Comp, _Level, Fmt) \ +#define RT_TRACE(_comp, _level, fmt) \ do { \ - if (_Level <= GlobalDebugLevel) { \ + if (_level <= GlobalDebugLevel) { \ _dbgdump("%s [0x%08x,%d]", DRIVER_PREFIX, \ - (unsigned int)_Comp, _Level); \ - _dbgdump Fmt; \ + (unsigned int)_comp, _level); \ + _dbgdump fmt; \ } \ } while (0) @@ -119,14 +119,14 @@ extern u32 GlobalDebugLevel; DRIVER_PREFIX, __func__, __LINE__); \ } while (0) -#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)\ +#define RT_PRINT_DATA(_comp, _level, _titlestring, _hexdata, _hexdatalen)\ do { \ - if (_Level <= GlobalDebugLevel) { \ + if (_level <= GlobalDebugLevel) { \ int __i; \ - u8 *ptr = (u8 *)_HexData; \ + u8 *ptr = (u8 *)_hexdata; \ _dbgdump("%s", DRIVER_PREFIX); \ - _dbgdump(_TitleString); \ - for (__i = 0; __i < (int)_HexDataLen; __i++ ) { \ + _dbgdump(_titlestring); \ + for (__i = 0; __i < (int)_hexdatalen; __i++ ) { \ _dbgdump("%02X%s", ptr[__i], \ (((__i + 1) % 4) == 0) ? \ " " : " "); \ @@ -137,166 +137,159 @@ extern u32 GlobalDebugLevel; } \ } while (0) - int proc_get_drv_version(char *page, char **start, +int proc_get_drv_version(char *page, char **start, + off_t offset, int count, + int *eof, void *data); + +int proc_get_write_reg(char *page, char **start, + off_t offset, int count, + int *eof, void *data); + +int proc_set_write_reg(struct file *file, const char __user *buffer, + unsigned long count, void *data); +int proc_get_read_reg(char *page, char **start, + off_t offset, int count, + int *eof, void *data); + +int proc_set_read_reg(struct file *file, const char __user *buffer, + unsigned long count, void *data); + +int proc_get_fwstate(char *page, char **start, + off_t offset, int count, + int *eof, void *data); +int proc_get_sec_info(char *page, char **start, + off_t offset, int count, + int *eof, void *data); +int proc_get_mlmext_state(char *page, char **start, off_t offset, int count, int *eof, void *data); - int proc_get_write_reg(char *page, char **start, +int proc_get_qos_option(char *page, char **start, + off_t offset, int count, + int *eof, void *data); +int proc_get_ht_option(char *page, char **start, + off_t offset, int count, + int *eof, void *data); +int proc_get_rf_info(char *page, char **start, + off_t offset, int count, + int *eof, void *data); +int proc_get_ap_info(char *page, char **start, + off_t offset, int count, + int *eof, void *data); + +int proc_get_adapter_state(char *page, char **start, + off_t offset, int count, + int *eof, void *data); + +int proc_get_trx_info(char *page, char **start, + off_t offset, int count, + int *eof, void *data); + +int proc_get_mac_reg_dump1(char *page, char **start, + off_t offset, int count, + int *eof, void *data); + +int proc_get_mac_reg_dump2(char *page, char **start, + off_t offset, int count, + int *eof, void *data); + +int proc_get_mac_reg_dump3(char *page, char **start, + off_t offset, int count, + int *eof, void *data); + +int proc_get_bb_reg_dump1(char *page, char **start, off_t offset, int count, int *eof, void *data); - int proc_set_write_reg(struct file *file, const char __user *buffer, - unsigned long count, void *data); - - int proc_get_read_reg(char *page, char **start, +int proc_get_bb_reg_dump2(char *page, char **start, off_t offset, int count, int *eof, void *data); - int proc_set_read_reg(struct file *file, const char __user *buffer, - unsigned long count, void *data); - - - int proc_get_fwstate(char *page, char **start, +int proc_get_bb_reg_dump3(char *page, char **start, off_t offset, int count, int *eof, void *data); - int proc_get_sec_info(char *page, char **start, +int proc_get_rf_reg_dump1(char *page, char **start, off_t offset, int count, int *eof, void *data); - int proc_get_mlmext_state(char *page, char **start, +int proc_get_rf_reg_dump2(char *page, char **start, off_t offset, int count, int *eof, void *data); - int proc_get_qos_option(char *page, char **start, +int proc_get_rf_reg_dump3(char *page, char **start, off_t offset, int count, int *eof, void *data); - int proc_get_ht_option(char *page, char **start, - off_t offset, int count, - int *eof, void *data); - - int proc_get_rf_info(char *page, char **start, - off_t offset, int count, - int *eof, void *data); - - int proc_get_ap_info(char *page, char **start, - off_t offset, int count, - int *eof, void *data); - - int proc_get_adapter_state(char *page, char **start, - off_t offset, int count, - int *eof, void *data); - - int proc_get_trx_info(char *page, char **start, - off_t offset, int count, - int *eof, void *data); - - int proc_get_mac_reg_dump1(char *page, char **start, - off_t offset, int count, - int *eof, void *data); - - int proc_get_mac_reg_dump2(char *page, char **start, - off_t offset, int count, - int *eof, void *data); - - int proc_get_mac_reg_dump3(char *page, char **start, - off_t offset, int count, - int *eof, void *data); - - int proc_get_bb_reg_dump1(char *page, char **start, - off_t offset, int count, - int *eof, void *data); - - int proc_get_bb_reg_dump2(char *page, char **start, - off_t offset, int count, - int *eof, void *data); - - int proc_get_bb_reg_dump3(char *page, char **start, - off_t offset, int count, - int *eof, void *data); - - int proc_get_rf_reg_dump1(char *page, char **start, - off_t offset, int count, - int *eof, void *data); - - int proc_get_rf_reg_dump2(char *page, char **start, - off_t offset, int count, - int *eof, void *data); - - int proc_get_rf_reg_dump3(char *page, char **start, - off_t offset, int count, - int *eof, void *data); - - int proc_get_rf_reg_dump4(char *page, char **start, +int proc_get_rf_reg_dump4(char *page, char **start, off_t offset, int count, int *eof, void *data); #ifdef CONFIG_AP_MODE - int proc_get_all_sta_info(char *page, char **start, +int proc_get_all_sta_info(char *page, char **start, off_t offset, int count, int *eof, void *data); #endif - int proc_get_best_channel(char *page, char **start, +int proc_get_best_channel(char *page, char **start, off_t offset, int count, int *eof, void *data); - int proc_get_rx_signal(char *page, char **start, +int proc_get_rx_signal(char *page, char **start, + off_t offset, int count, + int *eof, void *data); + +int proc_set_rx_signal(struct file *file, const char __user *buffer, + unsigned long count, void *data); + +int proc_get_ht_enable(char *page, char **start, + off_t offset, int count, + int *eof, void *data); + +int proc_set_ht_enable(struct file *file, const char __user *buffer, + unsigned long count, void *data); + +int proc_get_cbw40_enable(char *page, char **start, off_t offset, int count, int *eof, void *data); - int proc_set_rx_signal(struct file *file, const char __user *buffer, - unsigned long count, void *data); +int proc_set_cbw40_enable(struct file *file, const char __user *buffer, + unsigned long count, void *data); - int proc_get_ht_enable(char *page, char **start, +int proc_get_ampdu_enable(char *page, char **start, off_t offset, int count, int *eof, void *data); - int proc_set_ht_enable(struct file *file, const char __user *buffer, - unsigned long count, void *data); +int proc_set_ampdu_enable(struct file *file, const char __user *buffer, + unsigned long count, void *data); - int proc_get_cbw40_enable(char *page, char **start, - off_t offset, int count, - int *eof, void *data); +int proc_get_rx_stbc(char *page, char **start, + off_t offset, int count, + int *eof, void *data); - int proc_set_cbw40_enable(struct file *file, const char __user *buffer, - unsigned long count, void *data); +int proc_set_rx_stbc(struct file *file, const char __user *buffer, + unsigned long count, void *data); - int proc_get_ampdu_enable(char *page, char **start, - off_t offset, int count, - int *eof, void *data); +int proc_get_two_path_rssi(char *page, char **start, + off_t offset, int count, + int *eof, void *data); - int proc_set_ampdu_enable(struct file *file, const char __user *buffer, - unsigned long count, void *data); +int proc_get_rssi_disp(char *page, char **start, + off_t offset, int count, + int *eof, void *data); - int proc_get_rx_stbc(char *page, char **start, - off_t offset, int count, - int *eof, void *data); - - int proc_set_rx_stbc(struct file *file, const char __user *buffer, - unsigned long count, void *data); - - int proc_get_two_path_rssi(char *page, char **start, - off_t offset, int count, - int *eof, void *data); - - int proc_get_rssi_disp(char *page, char **start, - off_t offset, int count, - int *eof, void *data); - - int proc_set_rssi_disp(struct file *file, const char __user *buffer, - unsigned long count, void *data); +int proc_set_rssi_disp(struct file *file, const char __user *buffer, + unsigned long count, void *data); #ifdef CONFIG_BT_COEXIST - int proc_get_btcoex_dbg(char *page, char **start, - off_t offset, int count, - int *eof, void *data); +int proc_get_btcoex_dbg(char *page, char **start, + off_t offset, int count, + int *eof, void *data); - int proc_set_btcoex_dbg(struct file *file, const char *buffer, - unsigned long count, void *data); +int proc_set_btcoex_dbg(struct file *file, const char *buffer, + signed long count, void *data); #endif /* CONFIG_BT_COEXIST */ diff --git a/include/rtw_eeprom.h b/include/rtw_eeprom.h index bbace71..b2672c3 100644 --- a/include/rtw_eeprom.h +++ b/include/rtw_eeprom.h @@ -23,12 +23,12 @@ #include #include -#define RTL8712_EEPROM_ID 0x8712 +#define RTL8712_EEPROM_ID 0x8712 #define HWSET_MAX_SIZE_512 512 #define EEPROM_MAX_SIZE HWSET_MAX_SIZE_512 -#define CLOCK_RATE 50 /* 100us */ +#define CLOCK_RATE 50 /* 100us */ /* EEPROM opcodes */ #define EEPROM_READ_OPCODE 06 @@ -38,32 +38,31 @@ #define EEPROM_EWDS_OPCODE 16 /* Erase/write disable */ /* Country codes */ -#define USA 0x555320 -#define EUROPE 0x1 /* temp, should be provided later */ -#define JAPAN 0x2 /* temp, should be provided later */ +#define USA 0x555320 +#define EUROPE 0x1 /* temp, should be provided later */ +#define JAPAN 0x2 /* temp, should be provided later */ -#define EEPROM_CID_DEFAULT 0x0 -#define EEPROM_CID_ALPHA 0x1 -#define EEPROM_CID_Senao 0x3 -#define EEPROM_CID_NetCore 0x5 -#define EEPROM_CID_CAMEO 0X8 -#define EEPROM_CID_SITECOM 0x9 -#define EEPROM_CID_COREGA 0xB +#define EEPROM_CID_DEFAULT 0x0 +#define EEPROM_CID_ALPHA 0x1 +#define EEPROM_CID_Senao 0x3 +#define EEPROM_CID_NetCore 0x5 +#define EEPROM_CID_CAMEO 0X8 +#define EEPROM_CID_SITECOM 0x9 +#define EEPROM_CID_COREGA 0xB #define EEPROM_CID_EDIMAX_BELK 0xC #define EEPROM_CID_SERCOMM_BELK 0xE -#define EEPROM_CID_CAMEO1 0xF +#define EEPROM_CID_CAMEO1 0xF #define EEPROM_CID_WNC_COREGA 0x12 -#define EEPROM_CID_CLEVO 0x13 -#define EEPROM_CID_WHQL 0xFE /* added by chiyoko for dtm, 20090108 */ +#define EEPROM_CID_CLEVO 0x13 +#define EEPROM_CID_WHQL 0xFE -/* */ /* Customer ID, note that: */ /* This variable is initiailzed through EEPROM or registry, */ /* however, its definition may be different with that in EEPROM for */ -/* EEPROM size consideration. So, we have to perform proper translation between them. */ +/* EEPROM size consideration. So, we have to perform proper translation + * between them. */ /* Besides, CustomerID of registry has precedence of that of EEPROM. */ /* defined below. 060703, by rcnjko. */ -/* */ enum RT_CUSTOMER_ID { RT_CID_DEFAULT = 0, RT_CID_8187_ALPHA0 = 1, @@ -83,7 +82,9 @@ enum RT_CUSTOMER_ID { RT_CID_CHINA_MOBILE = 15, RT_CID_819x_ALPHA = 16, RT_CID_819x_Sitecom = 17, - RT_CID_CCX = 18, /* It's set under CCX logo test and isn't demanded for CCX functions, but for test behavior like retry limit and tx report. By Bruce, 2009-02-17. */ + RT_CID_CCX = 18, /* It's set under CCX logo test and isn't demanded + * for CCX functions, but for test behavior like retry + * limit and tx report. By Bruce, 2009-02-17. */ RT_CID_819x_Lenovo = 19, RT_CID_819x_QMI = 20, RT_CID_819x_Edimax_Belkin = 21, @@ -92,7 +93,8 @@ enum RT_CUSTOMER_ID { RT_CID_819x_MSI = 24, RT_CID_819x_Acer = 25, RT_CID_819x_AzWave_ASUS = 26, - RT_CID_819x_AzWave = 27, /* For AzWave in PCIe, The ID is AzWave use and not only Asus */ + RT_CID_819x_AzWave = 27, /* For AzWave in PCIe,i + * The ID is AzWave use and not only Asus */ RT_CID_819x_HP = 28, RT_CID_819x_WNC_COREGA = 29, RT_CID_819x_Arcadyan_Belkin = 30, @@ -119,10 +121,10 @@ struct eeprom_priv { u8 efuse_eeprom_data[HWSET_MAX_SIZE_512]; }; -extern void eeprom_write16(struct adapter *padapter, u16 reg, u16 data); -extern u16 eeprom_read16(struct adapter *padapter, u16 reg); -extern void read_eeprom_content(struct adapter *padapter); -extern void eeprom_read_sz(struct adapter * padapter, u16 reg,u8* data, u32 sz); -extern void read_eeprom_content_by_attrib(struct adapter * padapter ); +void eeprom_write16(struct adapter *padapter, u16 reg, u16 data); +u16 eeprom_read16(struct adapter *padapter, u16 reg); +void read_eeprom_content(struct adapter *padapter); +void eeprom_read_sz(struct adapter *adapt, u16 reg, u8 *data, u32 sz); +void read_eeprom_content_by_attrib(struct adapter *padapter); #endif /* __RTL871X_EEPROM_H__ */