mirror of
https://github.com/lwfinger/rtl8188eu.git
synced 2024-11-22 04:23:39 +00:00
rtl8188eu: Fix checkpatch errors in hal/Hal8188EPwrSeq.c and hal/HalHWImg8188E_BB.c
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
parent
a153120e2e
commit
716a0e47ff
2 changed files with 199 additions and 273 deletions
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@ -25,70 +25,61 @@
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drivers should parse below arrays and do the corresponding actions
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drivers should parse below arrays and do the corresponding actions
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*/
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*/
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/* 3 Power on Array */
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/* 3 Power on Array */
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struct wl_pwr_cfg rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]=
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struct wl_pwr_cfg rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS] = {
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{
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RTL8188E_TRANS_CARDEMU_TO_ACT
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RTL8188E_TRANS_CARDEMU_TO_ACT
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RTL8188E_TRANS_END
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RTL8188E_TRANS_END
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};
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};
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/* 3Radio off Array */
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/* 3Radio off Array */
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struct wl_pwr_cfg rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS]=
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struct wl_pwr_cfg rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_END_STEPS] = {
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{
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RTL8188E_TRANS_ACT_TO_CARDEMU
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RTL8188E_TRANS_ACT_TO_CARDEMU
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RTL8188E_TRANS_END
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RTL8188E_TRANS_END
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};
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};
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/* 3Card Disable Array */
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/* 3Card Disable Array */
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struct wl_pwr_cfg rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]=
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struct wl_pwr_cfg rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS] = {
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{
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RTL8188E_TRANS_ACT_TO_CARDEMU
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RTL8188E_TRANS_ACT_TO_CARDEMU
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RTL8188E_TRANS_CARDEMU_TO_CARDDIS
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RTL8188E_TRANS_CARDEMU_TO_CARDDIS
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RTL8188E_TRANS_END
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RTL8188E_TRANS_END
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};
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};
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/* 3 Card Enable Array */
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/* 3 Card Enable Array */
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struct wl_pwr_cfg rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]=
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struct wl_pwr_cfg rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS] = {
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{
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RTL8188E_TRANS_CARDDIS_TO_CARDEMU
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RTL8188E_TRANS_CARDDIS_TO_CARDEMU
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RTL8188E_TRANS_CARDEMU_TO_ACT
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RTL8188E_TRANS_CARDEMU_TO_ACT
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RTL8188E_TRANS_END
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RTL8188E_TRANS_END
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};
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};
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/* 3Suspend Array */
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/* 3Suspend Array */
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struct wl_pwr_cfg rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]=
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struct wl_pwr_cfg rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188E_TRANS_END_STEPS] = {
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{
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RTL8188E_TRANS_ACT_TO_CARDEMU
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RTL8188E_TRANS_ACT_TO_CARDEMU
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RTL8188E_TRANS_CARDEMU_TO_SUS
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RTL8188E_TRANS_CARDEMU_TO_SUS
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RTL8188E_TRANS_END
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RTL8188E_TRANS_END
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};
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};
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/* 3 Resume Array */
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/* 3 Resume Array */
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struct wl_pwr_cfg rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]=
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struct wl_pwr_cfg rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188E_TRANS_END_STEPS] = {
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{
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RTL8188E_TRANS_SUS_TO_CARDEMU
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RTL8188E_TRANS_SUS_TO_CARDEMU
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RTL8188E_TRANS_CARDEMU_TO_ACT
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RTL8188E_TRANS_CARDEMU_TO_ACT
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RTL8188E_TRANS_END
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RTL8188E_TRANS_END
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};
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};
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/* 3HWPDN Array */
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/* 3HWPDN Array */
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struct wl_pwr_cfg rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]=
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struct wl_pwr_cfg rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS] = {
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{
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RTL8188E_TRANS_ACT_TO_CARDEMU
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RTL8188E_TRANS_ACT_TO_CARDEMU
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RTL8188E_TRANS_CARDEMU_TO_PDN
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RTL8188E_TRANS_CARDEMU_TO_PDN
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RTL8188E_TRANS_END
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RTL8188E_TRANS_END
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};
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};
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/* 3 Enter LPS */
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/* 3 Enter LPS */
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struct wl_pwr_cfg rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS]=
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struct wl_pwr_cfg rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS + RTL8188E_TRANS_END_STEPS] = {
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{
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/* FW behavior */
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/* FW behavior */
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RTL8188E_TRANS_ACT_TO_LPS
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RTL8188E_TRANS_ACT_TO_LPS
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RTL8188E_TRANS_END
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RTL8188E_TRANS_END
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};
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};
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/* 3 Leave LPS */
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/* 3 Leave LPS */
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struct wl_pwr_cfg rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS] = {
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struct wl_pwr_cfg rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS] = {
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/* FW behavior */
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/* FW behavior */
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RTL8188E_TRANS_LPS_TO_ACT
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RTL8188E_TRANS_LPS_TO_ACT
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RTL8188E_TRANS_END
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RTL8188E_TRANS_END
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@ -22,34 +22,37 @@
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#include <rtw_iol.h>
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#include <rtw_iol.h>
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static bool
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#define read_next_pair(array, v1, v2, i) \
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CheckCondition(
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do { \
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const u4Byte Condition,
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i += 2; \
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const u4Byte Hex
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v1 = array[i]; \
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)
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v2 = array[i+1]; \
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} while (0)
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static bool CheckCondition(const u4Byte condition, const u4Byte hex)
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{
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{
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u4Byte _board = (Hex & 0x000000FF);
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u4Byte _board = (hex & 0x000000FF);
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u4Byte _interface = (Hex & 0x0000FF00) >> 8;
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u4Byte _interface = (hex & 0x0000FF00) >> 8;
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u4Byte _platform = (Hex & 0x00FF0000) >> 16;
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u4Byte _platform = (hex & 0x00FF0000) >> 16;
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u4Byte cond = Condition;
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u4Byte cond = condition;
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if ( Condition == 0xCDCDCDCD )
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if (condition == 0xCDCDCDCD)
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return true;
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return true;
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cond = Condition & 0x000000FF;
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cond = condition & 0x000000FF;
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if ( (_board == cond) && cond != 0x00)
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if ((_board == cond) && cond != 0x00)
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return false;
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return false;
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cond = Condition & 0x0000FF00;
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cond = condition & 0x0000FF00;
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cond = cond >> 8;
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cond = cond >> 8;
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if ( (_interface & cond) == 0 && cond != 0x07)
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if ((_interface & cond) == 0 && cond != 0x07)
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return false;
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return false;
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cond = Condition & 0x00FF0000;
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cond = condition & 0x00FF0000;
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cond = cond >> 16;
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cond = cond >> 16;
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if ( (_platform & cond) == 0 && cond != 0x0F)
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if ((_platform & cond) == 0 && cond != 0x0F)
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return false;
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return false;
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return true;
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return true;
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}
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}
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@ -57,7 +60,7 @@ CheckCondition(
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* AGC_TAB_1T.TXT
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* AGC_TAB_1T.TXT
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******************************************************************************/
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******************************************************************************/
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static u4Byte Array_AGC_TAB_1T_8188E[] = {
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static u4Byte array_agc_tab_1t_8188e[] = {
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0xC78, 0xFB000001,
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0xC78, 0xFB000001,
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0xC78, 0xFB010001,
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0xC78, 0xFB010001,
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0xC78, 0xFB020001,
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0xC78, 0xFB020001,
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@ -188,103 +191,84 @@ static u4Byte Array_AGC_TAB_1T_8188E[] = {
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0xC78, 0x407F0001,
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0xC78, 0x407F0001,
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};
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};
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enum HAL_STATUS
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enum HAL_STATUS ODM_ReadAndConfig_AGC_TAB_1T_8188E(struct odm_dm_struct *dm_odm)
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ODM_ReadAndConfig_AGC_TAB_1T_8188E(
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struct odm_dm_struct * pDM_Odm
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)
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{
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{
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#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while (0)
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u4Byte hex = 0;
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u4Byte hex = 0;
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u4Byte i = 0;
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u4Byte i = 0;
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u2Byte count = 0;
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u2Byte count = 0;
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pu4Byte ptr_array = NULL;
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pu4Byte ptr_array = NULL;
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u1Byte platform = pDM_Odm->SupportPlatform;
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u1Byte platform = dm_odm->SupportPlatform;
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u1Byte interfaceValue = pDM_Odm->SupportInterface;
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u1Byte interfaceValue = dm_odm->SupportInterface;
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u1Byte board = pDM_Odm->BoardType;
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u1Byte board = dm_odm->BoardType;
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u4Byte ArrayLen = sizeof(Array_AGC_TAB_1T_8188E)/sizeof(u4Byte);
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u4Byte arraylen = sizeof(array_agc_tab_1t_8188e)/sizeof(u4Byte);
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pu4Byte Array = Array_AGC_TAB_1T_8188E;
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pu4Byte array = array_agc_tab_1t_8188e;
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bool biol = false;
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bool biol = false;
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struct adapter * Adapter = pDM_Odm->Adapter;
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struct adapter *adapter = dm_odm->Adapter;
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struct xmit_frame *pxmit_frame;
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struct xmit_frame *pxmit_frame;
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u8 bndy_cnt=1;
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u8 bndy_cnt = 1;
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enum HAL_STATUS rst =HAL_STATUS_SUCCESS;
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enum HAL_STATUS rst = HAL_STATUS_SUCCESS;
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hex += board;
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hex += board;
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hex += interfaceValue << 8;
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hex += interfaceValue << 8;
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hex += platform << 16;
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hex += platform << 16;
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hex += 0xFF000000;
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hex += 0xFF000000;
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biol = rtw_IOL_applied(Adapter);
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biol = rtw_IOL_applied(adapter);
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if (biol){
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if (biol) {
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if ((pxmit_frame= rtw_IOL_accquire_xmit_frame(Adapter)) == NULL){
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pxmit_frame = rtw_IOL_accquire_xmit_frame(adapter);
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printk("rtw_IOL_accquire_xmit_frame failed\n");
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if (pxmit_frame == NULL) {
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pr_info("rtw_IOL_accquire_xmit_frame failed\n");
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return HAL_STATUS_FAILURE;
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return HAL_STATUS_FAILURE;
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}
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}
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}
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}
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for (i = 0; i < ArrayLen; i += 2 )
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for (i = 0; i < arraylen; i += 2) {
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{
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u4Byte v1 = array[i];
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u4Byte v1 = Array[i];
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u4Byte v2 = array[i+1];
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u4Byte v2 = Array[i+1];
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/* This (offset, data) pair meets the condition. */
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/* This (offset, data) pair meets the condition. */
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if ( v1 < 0xCDCDCDCD )
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if (v1 < 0xCDCDCDCD) {
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{
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if (biol) {
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if (biol){
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if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
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if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
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bndy_cnt++;
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bndy_cnt++;
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rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord);
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rtw_IOL_append_WD_cmd(pxmit_frame, (u2Byte)v1, v2, bMaskDWord);
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}
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} else {
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else
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odm_ConfigBB_AGC_8188E(dm_odm, v1, bMaskDWord, v2);
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{
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odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2);
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}
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}
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continue;
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continue;
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}
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} else {
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else
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/* This line is the start line of branch. */
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{ /* This line is the start line of branch. */
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if (!CheckCondition(array[i], hex)) {
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if ( !CheckCondition(Array[i], hex) )
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/* Discard the following (offset, data) pairs. */
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{ /* Discard the following (offset, data) pairs. */
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read_next_pair(array, v1, v2, i);
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READ_NEXT_PAIR(v1, v2, i);
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while (v2 != 0xDEAD &&
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while ( v2 != 0xDEAD &&
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v2 != 0xCDEF &&
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v2 != 0xCDEF &&
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v2 != 0xCDCD && i < arraylen - 2)
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v2 != 0xCDCD && i < ArrayLen -2)
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read_next_pair(array, v1, v2, i);
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{
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READ_NEXT_PAIR(v1, v2, i);
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}
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i -= 2; /* prevent from for-loop += 2 */
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i -= 2; /* prevent from for-loop += 2 */
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}
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} else { /* Configure matched pairs and skip to end of if-else. */
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else /* Configure matched pairs and skip to end of if-else. */
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read_next_pair(array, v1, v2, i);
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{
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while (v2 != 0xDEAD &&
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READ_NEXT_PAIR(v1, v2, i);
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v2 != 0xCDEF &&
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while ( v2 != 0xDEAD &&
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v2 != 0xCDCD && i < arraylen - 2) {
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v2 != 0xCDEF &&
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if (biol) {
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v2 != 0xCDCD && i < ArrayLen -2)
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{
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if (biol){
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if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
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if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
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bndy_cnt++;
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bndy_cnt++;
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rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord);
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rtw_IOL_append_WD_cmd(pxmit_frame, (u2Byte)v1, v2, bMaskDWord);
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} else {
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odm_ConfigBB_AGC_8188E(dm_odm, v1, bMaskDWord, v2);
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}
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}
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else
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read_next_pair(array, v1, v2, i);
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{
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odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2);
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}
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READ_NEXT_PAIR(v1, v2, i);
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}
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while (v2 != 0xDEAD && i < ArrayLen -2)
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{
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READ_NEXT_PAIR(v1, v2, i);
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}
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}
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while (v2 != 0xDEAD && i < arraylen - 2)
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read_next_pair(array, v1, v2, i);
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}
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}
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}
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}
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}
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}
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if (biol){
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if (biol) {
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if (!rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt)) {
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if (!rtw_IOL_exec_cmds_sync(dm_odm->Adapter, pxmit_frame, 1000, bndy_cnt)) {
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printk("~~~ %s IOL_exec_cmds Failed !!!\n",__func__);
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printk("~~~ %s IOL_exec_cmds Failed !!!\n", __func__);
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rst = HAL_STATUS_FAILURE;
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rst = HAL_STATUS_FAILURE;
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}
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}
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}
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}
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@ -295,7 +279,7 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E(
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* PHY_REG_1T.TXT
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* PHY_REG_1T.TXT
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******************************************************************************/
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******************************************************************************/
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static u4Byte Array_PHY_REG_1T_8188E[] = {
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static u4Byte array_phy_reg_1t_8188e[] = {
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0x800, 0x80040000,
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0x800, 0x80040000,
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0x804, 0x00000003,
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0x804, 0x00000003,
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0x808, 0x0000FC00,
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0x808, 0x0000FC00,
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@ -489,155 +473,116 @@ static u4Byte Array_PHY_REG_1T_8188E[] = {
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0xF00, 0x00000300,
|
0xF00, 0x00000300,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
enum HAL_STATUS ODM_ReadAndConfig_PHY_REG_1T_8188E(struct odm_dm_struct *dm_odm)
|
||||||
enum HAL_STATUS
|
|
||||||
ODM_ReadAndConfig_PHY_REG_1T_8188E(
|
|
||||||
struct odm_dm_struct * pDM_Odm
|
|
||||||
)
|
|
||||||
{
|
{
|
||||||
#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while (0)
|
|
||||||
|
|
||||||
u4Byte hex = 0;
|
u4Byte hex = 0;
|
||||||
u4Byte i = 0;
|
u4Byte i = 0;
|
||||||
u2Byte count = 0;
|
u2Byte count = 0;
|
||||||
pu4Byte ptr_array = NULL;
|
pu4Byte ptr_array = NULL;
|
||||||
u1Byte platform = pDM_Odm->SupportPlatform;
|
u1Byte platform = dm_odm->SupportPlatform;
|
||||||
u1Byte interfaceValue = pDM_Odm->SupportInterface;
|
u1Byte interfaceValue = dm_odm->SupportInterface;
|
||||||
u1Byte board = pDM_Odm->BoardType;
|
u1Byte board = dm_odm->BoardType;
|
||||||
u4Byte ArrayLen = sizeof(Array_PHY_REG_1T_8188E)/sizeof(u4Byte);
|
u4Byte arraylen = sizeof(array_phy_reg_1t_8188e)/sizeof(u4Byte);
|
||||||
pu4Byte Array = Array_PHY_REG_1T_8188E;
|
pu4Byte array = array_phy_reg_1t_8188e;
|
||||||
bool biol = false;
|
bool biol = false;
|
||||||
struct adapter * Adapter = pDM_Odm->Adapter;
|
struct adapter *adapter = dm_odm->Adapter;
|
||||||
struct xmit_frame *pxmit_frame;
|
struct xmit_frame *pxmit_frame;
|
||||||
u8 bndy_cnt=1;
|
u8 bndy_cnt = 1;
|
||||||
enum HAL_STATUS rst =HAL_STATUS_SUCCESS;
|
enum HAL_STATUS rst = HAL_STATUS_SUCCESS;
|
||||||
hex += board;
|
hex += board;
|
||||||
hex += interfaceValue << 8;
|
hex += interfaceValue << 8;
|
||||||
hex += platform << 16;
|
hex += platform << 16;
|
||||||
hex += 0xFF000000;
|
hex += 0xFF000000;
|
||||||
biol = rtw_IOL_applied(Adapter);
|
biol = rtw_IOL_applied(adapter);
|
||||||
|
|
||||||
if (biol){
|
if (biol) {
|
||||||
if ((pxmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL)
|
pxmit_frame = rtw_IOL_accquire_xmit_frame(adapter);
|
||||||
{
|
if (pxmit_frame == NULL) {
|
||||||
printk("rtw_IOL_accquire_xmit_frame failed\n");
|
pr_info("rtw_IOL_accquire_xmit_frame failed\n");
|
||||||
return HAL_STATUS_FAILURE;
|
return HAL_STATUS_FAILURE;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
for (i = 0; i < ArrayLen; i += 2 )
|
for (i = 0; i < arraylen; i += 2) {
|
||||||
{
|
u4Byte v1 = array[i];
|
||||||
u4Byte v1 = Array[i];
|
u4Byte v2 = array[i+1];
|
||||||
u4Byte v2 = Array[i+1];
|
|
||||||
|
|
||||||
|
/* This (offset, data) pair meets the condition. */
|
||||||
/* This (offset, data) pair meets the condition. */
|
if (v1 < 0xCDCDCDCD) {
|
||||||
if ( v1 < 0xCDCDCDCD )
|
if (biol) {
|
||||||
{
|
|
||||||
if (biol){
|
|
||||||
if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
|
if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
|
||||||
bndy_cnt++;
|
bndy_cnt++;
|
||||||
|
if (v1 == 0xfe) {
|
||||||
|
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 50);
|
||||||
if (v1 == 0xfe){
|
} else if (v1 == 0xfd) {
|
||||||
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,50);
|
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 5);
|
||||||
}
|
} else if (v1 == 0xfc) {
|
||||||
else if (v1 == 0xfd){
|
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 1);
|
||||||
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,5);
|
} else if (v1 == 0xfb) {
|
||||||
}
|
rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 50);
|
||||||
else if (v1 == 0xfc){
|
} else if (v1 == 0xfa) {
|
||||||
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,1);
|
|
||||||
}
|
|
||||||
else if (v1 == 0xfb){
|
|
||||||
rtw_IOL_append_DELAY_US_cmd(pxmit_frame,50);
|
|
||||||
}
|
|
||||||
else if (v1 == 0xfa){
|
|
||||||
rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5);
|
rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5);
|
||||||
}
|
} else if (v1 == 0xf9) {
|
||||||
else if (v1 == 0xf9){
|
rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 1);
|
||||||
rtw_IOL_append_DELAY_US_cmd(pxmit_frame,1);
|
} else {
|
||||||
}
|
|
||||||
else{
|
|
||||||
if (v1 == 0xa24)
|
if (v1 == 0xa24)
|
||||||
pDM_Odm->RFCalibrateInfo.RegA24 = v2;
|
dm_odm->RFCalibrateInfo.RegA24 = v2;
|
||||||
|
rtw_IOL_append_WD_cmd(pxmit_frame, (u2Byte)v1, v2, bMaskDWord);
|
||||||
rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord);
|
|
||||||
}
|
}
|
||||||
}
|
} else {
|
||||||
else
|
odm_ConfigBB_PHY_8188E(dm_odm, v1, bMaskDWord, v2);
|
||||||
{
|
|
||||||
odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2);
|
|
||||||
}
|
}
|
||||||
continue;
|
continue;
|
||||||
}
|
} else { /* This line is the start line of branch. */
|
||||||
else
|
if (!CheckCondition(array[i], hex)) {
|
||||||
{ /* This line is the start line of branch. */
|
/* Discard the following (offset, data) pairs. */
|
||||||
if ( !CheckCondition(Array[i], hex) )
|
read_next_pair(array, v1, v2, i);
|
||||||
{ /* Discard the following (offset, data) pairs. */
|
while (v2 != 0xDEAD &&
|
||||||
READ_NEXT_PAIR(v1, v2, i);
|
v2 != 0xCDEF &&
|
||||||
while (v2 != 0xDEAD &&
|
v2 != 0xCDCD && i < arraylen - 2)
|
||||||
v2 != 0xCDEF &&
|
read_next_pair(array, v1, v2, i);
|
||||||
v2 != 0xCDCD && i < ArrayLen -2)
|
i -= 2; /* prevent from for-loop += 2 */
|
||||||
{
|
} else { /* Configure matched pairs and skip to end of if-else. */
|
||||||
READ_NEXT_PAIR(v1, v2, i);
|
read_next_pair(array, v1, v2, i);
|
||||||
}
|
while (v2 != 0xDEAD &&
|
||||||
i -= 2; /* prevent from for-loop += 2 */
|
v2 != 0xCDEF &&
|
||||||
}
|
v2 != 0xCDCD && i < arraylen - 2) {
|
||||||
else /* Configure matched pairs and skip to end of if-else. */
|
if (biol) {
|
||||||
{
|
if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
|
||||||
READ_NEXT_PAIR(v1, v2, i);
|
bndy_cnt++;
|
||||||
while (v2 != 0xDEAD &&
|
if (v1 == 0xfe) {
|
||||||
v2 != 0xCDEF &&
|
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 50);
|
||||||
v2 != 0xCDCD && i < ArrayLen -2)
|
} else if (v1 == 0xfd) {
|
||||||
{
|
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 5);
|
||||||
if (biol){
|
} else if (v1 == 0xfc) {
|
||||||
if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
|
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 1);
|
||||||
bndy_cnt++;
|
} else if (v1 == 0xfb) {
|
||||||
if (v1 == 0xfe){
|
rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 50);
|
||||||
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,50);
|
} else if (v1 == 0xfa) {
|
||||||
}
|
rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5);
|
||||||
else if (v1 == 0xfd){
|
} else if (v1 == 0xf9) {
|
||||||
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,5);
|
rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 1);
|
||||||
}
|
} else{
|
||||||
else if (v1 == 0xfc){
|
if (v1 == 0xa24)
|
||||||
rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,1);
|
dm_odm->RFCalibrateInfo.RegA24 = v2;
|
||||||
}
|
|
||||||
else if (v1 == 0xfb){
|
|
||||||
rtw_IOL_append_DELAY_US_cmd(pxmit_frame,50);
|
|
||||||
}
|
|
||||||
else if (v1 == 0xfa){
|
|
||||||
rtw_IOL_append_DELAY_US_cmd(pxmit_frame,5);
|
|
||||||
}
|
|
||||||
else if (v1 == 0xf9){
|
|
||||||
rtw_IOL_append_DELAY_US_cmd(pxmit_frame,1);
|
|
||||||
}
|
|
||||||
else{
|
|
||||||
if (v1 == 0xa24)
|
|
||||||
pDM_Odm->RFCalibrateInfo.RegA24 = v2;
|
|
||||||
|
|
||||||
rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord);
|
rtw_IOL_append_WD_cmd(pxmit_frame, (u2Byte)v1, v2, bMaskDWord);
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
odm_ConfigBB_PHY_8188E(dm_odm, v1, bMaskDWord, v2);
|
||||||
}
|
}
|
||||||
|
read_next_pair(array, v1, v2, i);
|
||||||
}
|
}
|
||||||
else
|
|
||||||
{
|
|
||||||
odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2);
|
|
||||||
}
|
|
||||||
READ_NEXT_PAIR(v1, v2, i);
|
|
||||||
}
|
|
||||||
|
|
||||||
while (v2 != 0xDEAD && i < ArrayLen -2)
|
while (v2 != 0xDEAD && i < arraylen - 2)
|
||||||
{
|
read_next_pair(array, v1, v2, i);
|
||||||
READ_NEXT_PAIR(v1, v2, i);
|
}
|
||||||
}
|
|
||||||
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if (biol){
|
if (biol) {
|
||||||
/* printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__func__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt); */
|
if (!rtw_IOL_exec_cmds_sync(dm_odm->Adapter, pxmit_frame, 1000, bndy_cnt)) {
|
||||||
if (!rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt)) {
|
|
||||||
rst = HAL_STATUS_FAILURE;
|
rst = HAL_STATUS_FAILURE;
|
||||||
printk("~~~ IOL Config %s Failed !!!\n",__func__);
|
pr_info("~~~ IOL Config %s Failed !!!\n", __func__);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
return rst;
|
return rst;
|
||||||
|
|
@ -647,7 +592,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
|
||||||
* PHY_REG_PG.TXT
|
* PHY_REG_PG.TXT
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
|
|
||||||
static u4Byte Array_PHY_REG_PG_8188E[] = {
|
static u4Byte array_phy_reg_pg_8188e[] = {
|
||||||
0xE00, 0xFFFFFFFF, 0x06070809,
|
0xE00, 0xFFFFFFFF, 0x06070809,
|
||||||
0xE04, 0xFFFFFFFF, 0x02020405,
|
0xE04, 0xFFFFFFFF, 0x02020405,
|
||||||
0xE08, 0x0000FF00, 0x00000006,
|
0xE08, 0x0000FF00, 0x00000006,
|
||||||
|
|
@ -739,55 +684,45 @@ static u4Byte Array_PHY_REG_PG_8188E[] = {
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
void
|
void ODM_ReadAndConfig_PHY_REG_PG_8188E(struct odm_dm_struct *dm_odm)
|
||||||
ODM_ReadAndConfig_PHY_REG_PG_8188E(
|
|
||||||
struct odm_dm_struct * pDM_Odm
|
|
||||||
)
|
|
||||||
{
|
{
|
||||||
u4Byte hex = 0;
|
u4Byte hex;
|
||||||
u4Byte i = 0;
|
u4Byte i = 0;
|
||||||
u2Byte count = 0;
|
u2Byte count = 0;
|
||||||
pu4Byte ptr_array = NULL;
|
pu4Byte ptr_array = NULL;
|
||||||
u1Byte platform = pDM_Odm->SupportPlatform;
|
u1Byte platform = dm_odm->SupportPlatform;
|
||||||
u1Byte interfaceValue = pDM_Odm->SupportInterface;
|
u1Byte interfaceValue = dm_odm->SupportInterface;
|
||||||
u1Byte board = pDM_Odm->BoardType;
|
u1Byte board = dm_odm->BoardType;
|
||||||
u4Byte ArrayLen = sizeof(Array_PHY_REG_PG_8188E)/sizeof(u4Byte);
|
u4Byte arraylen = sizeof(array_phy_reg_pg_8188e) / sizeof(u4Byte);
|
||||||
pu4Byte Array = Array_PHY_REG_PG_8188E;
|
pu4Byte array = array_phy_reg_pg_8188e;
|
||||||
bool biol = false;
|
bool biol = false;
|
||||||
|
|
||||||
hex += board;
|
hex = board + (interfaceValue << 8);
|
||||||
hex += interfaceValue << 8;
|
hex += (platform << 16) + 0xFF000000;
|
||||||
hex += platform << 16;
|
|
||||||
hex += 0xFF000000;
|
|
||||||
|
|
||||||
for (i = 0; i < ArrayLen; i += 3 )
|
for (i = 0; i < arraylen; i += 3) {
|
||||||
{
|
u4Byte v1 = array[i];
|
||||||
u4Byte v1 = Array[i];
|
u4Byte v2 = array[i+1];
|
||||||
u4Byte v2 = Array[i+1];
|
u4Byte v3 = array[i+2];
|
||||||
u4Byte v3 = Array[i+2];
|
|
||||||
|
|
||||||
/* this line is a line of pure_body */
|
/* this line is a line of pure_body */
|
||||||
if ( v1 < 0xCDCDCDCD ) {
|
if (v1 < 0xCDCDCDCD) {
|
||||||
|
odm_ConfigBB_PHY_REG_PG_8188E(dm_odm, v1, v2, v3);
|
||||||
odm_ConfigBB_PHY_REG_PG_8188E(pDM_Odm, v1, v2, v3);
|
continue;
|
||||||
|
} else { /* this line is the start of branch */
|
||||||
continue;
|
if (!CheckCondition(array[i], hex)) {
|
||||||
} else { /* this line is the start of branch */
|
/* don't need the hw_body */
|
||||||
if ( !CheckCondition(Array[i], hex) )
|
i += 2; /* skip the pair of expression */
|
||||||
{ /* don't need the hw_body */
|
v1 = array[i];
|
||||||
i += 2; /* skip the pair of expression */
|
v2 = array[i+1];
|
||||||
v1 = Array[i];
|
v3 = array[i+2];
|
||||||
v2 = Array[i+1];
|
while (v2 != 0xDEAD) {
|
||||||
v3 = Array[i+2];
|
i += 3;
|
||||||
while (v2 != 0xDEAD)
|
v1 = array[i];
|
||||||
{
|
v2 = array[i+1];
|
||||||
i += 3;
|
v3 = array[i+1];
|
||||||
v1 = Array[i];
|
}
|
||||||
v2 = Array[i+1];
|
}
|
||||||
v3 = Array[i+1];
|
}
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue