From 7449a3d03bb19952314dba86709f342fc9399ad9 Mon Sep 17 00:00:00 2001
From: Larry Finger <Larry.Finger@lwfinger.net>
Date: Fri, 26 Jul 2013 13:36:38 -0500
Subject: [PATCH] rtl8188eu: Convert typedef statements in
 include/Hal8188EPhyCfg.h

Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
---
 core/rtw_mp.c            |   8 +--
 hal/hal_intf.c           |   8 +--
 hal/odm_interface.c      |   7 +--
 hal/rtl8188e_mp.c        |  10 ++--
 hal/rtl8188e_phycfg.c    |  38 ++++++-------
 hal/rtl8188e_rf6052.c    |   4 +-
 hal/usb_halinit.c        |   4 +-
 include/Hal8188EPhyCfg.h | 118 ++++++++++++++++-----------------------
 include/hal_intf.h       |   8 +--
 include/rtl8188e_hal.h   |   4 +-
 include/rtw_mp.h         |   2 +-
 11 files changed, 92 insertions(+), 119 deletions(-)

diff --git a/core/rtw_mp.c b/core/rtw_mp.c
index 3c270c4..5671655 100644
--- a/core/rtw_mp.c
+++ b/core/rtw_mp.c
@@ -76,22 +76,22 @@ void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val)
 
 u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask)
 {
-	return rtw_hal_read_rfreg(padapter, (RF_RADIO_PATH_E)rfpath, addr, bitmask);
+	return rtw_hal_read_rfreg(padapter, (enum rf_radio_path)rfpath, addr, bitmask);
 }
 
 void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val)
 {
-	rtw_hal_write_rfreg(padapter, (RF_RADIO_PATH_E)rfpath, addr, bitmask, val);
+	rtw_hal_write_rfreg(padapter, (enum rf_radio_path)rfpath, addr, bitmask, val);
 }
 
 u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr)
 {
-	return _read_rfreg(padapter, (RF_RADIO_PATH_E)rfpath, addr, bRFRegOffsetMask);
+	return _read_rfreg(padapter, (enum rf_radio_path)rfpath, addr, bRFRegOffsetMask);
 }
 
 void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val)
 {
-	_write_rfreg(padapter, (RF_RADIO_PATH_E)rfpath, addr, bRFRegOffsetMask, val);
+	_write_rfreg(padapter, (enum rf_radio_path)rfpath, addr, bRFRegOffsetMask, val);
 }
 
 static void _init_mp_priv_(struct mp_priv *pmp_priv)
diff --git a/hal/hal_intf.c b/hal/hal_intf.c
index 76d8744..b8dcd91 100644
--- a/hal/hal_intf.c
+++ b/hal/hal_intf.c
@@ -306,17 +306,17 @@ void	rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
 		padapter->HalFunc.write_bbreg(padapter, RegAddr, BitMask, Data);
 }
 
-u32	rtw_hal_read_rfreg(_adapter *padapter, RF_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
+u32	rtw_hal_read_rfreg(_adapter *padapter, enum rf_radio_path rfpath, u32 RegAddr, u32 BitMask)
 {
 	u32 data = 0;
 	if ( padapter->HalFunc.read_rfreg)
-		data = padapter->HalFunc.read_rfreg(padapter, eRFPath, RegAddr, BitMask);
+		data = padapter->HalFunc.read_rfreg(padapter, rfpath, RegAddr, BitMask);
 	return data;
 }
-void	rtw_hal_write_rfreg(_adapter *padapter, RF_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
+void	rtw_hal_write_rfreg(_adapter *padapter, enum rf_radio_path rfpath, u32 RegAddr, u32 BitMask, u32 Data)
 {
 	if (padapter->HalFunc.write_rfreg)
-		padapter->HalFunc.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data);
+		padapter->HalFunc.write_rfreg(padapter, rfpath, RegAddr, BitMask, Data);
 }
 
 s32	rtw_hal_interrupt_handler(_adapter *padapter)
diff --git a/hal/odm_interface.c b/hal/odm_interface.c
index e5f73c1..463a0cd 100644
--- a/hal/odm_interface.c
+++ b/hal/odm_interface.c
@@ -114,7 +114,7 @@ ODM_SetRFReg(
 	)
 {
 	PADAPTER Adapter = pDM_Odm->Adapter;
-	PHY_SetRFReg(Adapter, (enum _RF_RADIO_PATH)eRFPath, RegAddr, BitMask, Data);
+	PHY_SetRFReg(Adapter, (enum rf_radio_path)eRFPath, RegAddr, BitMask, Data);
 }
 
 
@@ -127,12 +127,9 @@ ODM_GetRFReg(
 	)
 {
 	PADAPTER Adapter = pDM_Odm->Adapter;
-	return PHY_QueryRFReg(Adapter, (enum _RF_RADIO_PATH)eRFPath, RegAddr, BitMask);
+	return PHY_QueryRFReg(Adapter, (enum rf_radio_path)eRFPath, RegAddr, BitMask);
 }
 
-
-
-
 /*  */
 /*  ODM Memory relative API. */
 /*  */
diff --git a/hal/rtl8188e_mp.c b/hal/rtl8188e_mp.c
index a7890b5..c98fac5 100644
--- a/hal/rtl8188e_mp.c
+++ b/hal/rtl8188e_mp.c
@@ -308,7 +308,7 @@ void Hal_SetChannel(PADAPTER pAdapter)
 	for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)
 	{
 		if (IS_HARDWARE_TYPE_8192D(pAdapter))
-			_write_rfreg(pAdapter, (RF_RADIO_PATH_E)eRFPath, ODM_CHANNEL, 0xFF, channel);
+			_write_rfreg(pAdapter, (enum rf_radio_path)eRFPath, ODM_CHANNEL, 0xFF, channel);
 		else
 			_write_rfreg(pAdapter, eRFPath, ODM_CHANNEL, 0x3FF, channel);
 	}
@@ -482,16 +482,16 @@ void Hal_SetAntenna(PADAPTER pAdapter)
 {
 	struct hal_data_8188e	*pHalData = GET_HAL_DATA(pAdapter);
 
-	R_ANTENNA_SELECT_OFDM *p_ofdm_tx;	/* OFDM Tx register */
-	R_ANTENNA_SELECT_CCK *p_cck_txrx;
+	struct ant_sel_ofdm *p_ofdm_tx;	/* OFDM Tx register */
+	struct ant_sel_cck *p_cck_txrx;
 
 	u8	r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
 	u8	chgTx = 0, chgRx = 0;
 	u32	r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
 
 
-	p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;
-	p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
+	p_ofdm_tx = (struct ant_sel_ofdm *)&r_ant_select_ofdm_val;
+	p_cck_txrx = (struct ant_sel_cck *)&r_ant_select_cck_val;
 
 	p_ofdm_tx->r_ant_ht1	= 0x1;
 	p_ofdm_tx->r_ant_ht2	= 0x2;	/*  Second TX RF path is A */
diff --git a/hal/rtl8188e_phycfg.c b/hal/rtl8188e_phycfg.c
index 45a4c14..25e5a06 100644
--- a/hal/rtl8188e_phycfg.c
+++ b/hal/rtl8188e_phycfg.c
@@ -345,7 +345,7 @@ rtl8188e_PHY_SetBBReg(
 *
 * Input:
 *			PADAPTER		Adapter,
-*			RF_RADIO_PATH_E	eRFPath,	Radio path of A/B/C/D
+*			enum rf_radio_path eRFPath,	Radio path of A/B/C/D
 *			u4Byte			Offset,		The target address to be read
 *
 * Output:	None
@@ -360,13 +360,13 @@ rtl8188e_PHY_SetBBReg(
 static	u32
 phy_RFSerialRead(
 		PADAPTER			Adapter,
-		RF_RADIO_PATH_E	eRFPath,
+		enum rf_radio_path eRFPath,
 		u32				Offset
 	)
 {
 	u32						retValue = 0;
 	struct hal_data_8188e				*pHalData = GET_HAL_DATA(Adapter);
-	BB_REGISTER_DEFINITION_T	*pPhyReg = &pHalData->PHYRegDef[eRFPath];
+	struct bb_reg_def *pPhyReg = &pHalData->PHYRegDef[eRFPath];
 	u32						NewOffset;
 	u32						tmplong,tmplong2;
 	u8					RfPiEnable=0;
@@ -423,7 +423,7 @@ phy_RFSerialRead(
 *
 * Input:
 *			PADAPTER		Adapter,
-*			RF_RADIO_PATH_E	eRFPath,	Radio path of A/B/C/D
+*			enum rf_radio_path eRFPath,	Radio path of A/B/C/D
 *			u4Byte			Offset,		The target address to be read
 *			u4Byte			Data		The new register Data in the target bit position
 *									of the target to be read
@@ -462,14 +462,14 @@ phy_RFSerialRead(
 static	void
 phy_RFSerialWrite(
 		PADAPTER			Adapter,
-		RF_RADIO_PATH_E	eRFPath,
+		enum rf_radio_path eRFPath,
 		u32				Offset,
 		u32				Data
 	)
 {
 	u32						DataAndAddr = 0;
 	struct hal_data_8188e				*pHalData = GET_HAL_DATA(Adapter);
-	BB_REGISTER_DEFINITION_T	*pPhyReg = &pHalData->PHYRegDef[eRFPath];
+	struct bb_reg_def *pPhyReg = &pHalData->PHYRegDef[eRFPath];
 	u32						NewOffset;
 
 
@@ -500,7 +500,7 @@ phy_RFSerialWrite(
 *
 * Input:
 *			PADAPTER		Adapter,
-*			RF_RADIO_PATH_E	eRFPath,	Radio path of A/B/C/D
+*			enum rf_radio_path eRFPath,	Radio path of A/B/C/D
 *			u4Byte			RegAddr,	The target address to be read
 *			u4Byte			BitMask		The target bit position in the target address
 *									to be read
@@ -509,7 +509,7 @@ phy_RFSerialWrite(
 * Return:		u4Byte			Readback value
 * Note:		This function is equal to "GetRFRegSetting" in PHY programming guide
 */
-u32 rtl8188e_PHY_QueryRFReg(PADAPTER Adapter, RF_RADIO_PATH_E eRFPath,
+u32 rtl8188e_PHY_QueryRFReg(PADAPTER Adapter, enum rf_radio_path eRFPath,
 			    u32 RegAddr, u32 BitMask)
 {
 	u32 Original_Value, Readback_Value, BitShift;
@@ -532,7 +532,7 @@ u32 rtl8188e_PHY_QueryRFReg(PADAPTER Adapter, RF_RADIO_PATH_E eRFPath,
 *
 * Input:
 *			PADAPTER		Adapter,
-*			RF_RADIO_PATH_E	eRFPath,	Radio path of A/B/C/D
+*			enum rf_radio_path eRFPath,	Radio path of A/B/C/D
 *			u4Byte			RegAddr,	The target address to be modified
 *			u4Byte			BitMask		The target bit position in the target address
 *									to be modified
@@ -546,7 +546,7 @@ u32 rtl8188e_PHY_QueryRFReg(PADAPTER Adapter, RF_RADIO_PATH_E eRFPath,
 void
 rtl8188e_PHY_SetRFReg(
 		PADAPTER			Adapter,
-		RF_RADIO_PATH_E	eRFPath,
+		enum rf_radio_path eRFPath,
 		u32				RegAddr,
 		u32				BitMask,
 		u32				Data
@@ -1022,7 +1022,7 @@ PHY_RFConfig8188E(
  *
  * Input:	PADAPTER			Adapter
  *			ps1Byte					pFileName
- *			RF_RADIO_PATH_E	eRFPath
+ *			enum rf_radio_path eRFPath
  *
  * Output:      NONE
  *
@@ -1034,13 +1034,13 @@ int
 rtl8188e_PHY_ConfigRFWithParaFile(
 		PADAPTER			Adapter,
 		u8*				pFileName,
-	RF_RADIO_PATH_E		eRFPath
+	enum rf_radio_path eRFPath
 )
 {
 	return _SUCCESS;
 }
 
-static int PHY_ConfigRFExternalPA(PADAPTER Adapter, RF_RADIO_PATH_E eRFPath)
+static int PHY_ConfigRFExternalPA(PADAPTER Adapter, enum rf_radio_path eRFPath)
 {
 	int	rtStatus = _SUCCESS;
 	struct hal_data_8188e	*pHalData = GET_HAL_DATA(Adapter);
@@ -1082,7 +1082,7 @@ rtl8192c_PHY_GetHWRegOriginalValue(
 static	u8
 phy_DbmToTxPwrIdx(
 		PADAPTER		Adapter,
-		WIRELESS_MODE	WirelessMode,
+		enum wireless_mode WirelessMode,
 		int			PowerInDbm
 	)
 {
@@ -1131,7 +1131,7 @@ phy_DbmToTxPwrIdx(
 /* 		current wireless mode. */
 /* 	By Bruce, 2008-01-29. */
 /*  */
-static int phy_TxPwrIdxToDbm(PADAPTER Adapter, WIRELESS_MODE WirelessMode, u8 TxPwrIdx)
+static int phy_TxPwrIdxToDbm(PADAPTER Adapter, enum wireless_mode WirelessMode, u8 TxPwrIdx)
 {
 	int				Offset = 0;
 	int				PwrOutDbm = 0;
@@ -1550,7 +1550,7 @@ static void _PHY_SwChnl8192C(PADAPTER Adapter, u8 channel)
 	param2 = channel;
 	for (eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) {
 		pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2);
-		PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
+		PHY_SetRFReg(Adapter, (enum rf_radio_path)eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
 	}
 }
 
@@ -1618,16 +1618,16 @@ phy_SwChnlStepByStep(
 
 static	bool
 phy_SetSwChnlCmdArray(
-	SwChnlCmd*		CmdTable,
+	struct sw_chnl_cmd *CmdTable,
 	u32			CmdTableIdx,
 	u32			CmdTableSz,
-	SwChnlCmdID		CmdID,
+	enum sw_chnl_cmd_id	CmdID,
 	u32			Para1,
 	u32			Para2,
 	u32			msDelay
 	)
 {
-	SwChnlCmd* pCmd;
+	struct sw_chnl_cmd *pCmd;
 
 	if (CmdTable == NULL)
 		return false;
diff --git a/hal/rtl8188e_rf6052.c b/hal/rtl8188e_rf6052.c
index 8fa489f..db940a4 100644
--- a/hal/rtl8188e_rf6052.c
+++ b/hal/rtl8188e_rf6052.c
@@ -569,11 +569,9 @@ phy_RF6052_Config_ParaFile(
 {
 	u32					u4RegValue;
 	u8					eRFPath;
-	BB_REGISTER_DEFINITION_T	*pPhyReg;
-
+	struct bb_reg_def *pPhyReg;
 	int					rtStatus = _SUCCESS;
 	struct hal_data_8188e		*pHalData = GET_HAL_DATA(Adapter);
-
 	static char			sz88eRadioAFile[] = RTL8188E_PHY_RADIO_A;
 	static char			sz88eRadioBFile[] = RTL8188E_PHY_RADIO_B;
 
diff --git a/hal/usb_halinit.c b/hal/usb_halinit.c
index 2545e79..7dc279c 100644
--- a/hal/usb_halinit.c
+++ b/hal/usb_halinit.c
@@ -1341,8 +1341,8 @@ _func_enter_;
 	_InitHWLed(Adapter);
 
 	/* Keep RfRegChnlVal for later use. */
-	pHalData->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (RF_RADIO_PATH_E)0, RF_CHNLBW, bRFRegOffsetMask);
-	pHalData->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (RF_RADIO_PATH_E)1, RF_CHNLBW, bRFRegOffsetMask);
+	pHalData->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (enum rf_radio_path)0, RF_CHNLBW, bRFRegOffsetMask);
+	pHalData->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (enum rf_radio_path)1, RF_CHNLBW, bRFRegOffsetMask);
 
 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
 	_BBTurnOnBlock(Adapter);
diff --git a/include/Hal8188EPhyCfg.h b/include/Hal8188EPhyCfg.h
index 67d4c4e..a6c9677 100644
--- a/include/Hal8188EPhyCfg.h
+++ b/include/Hal8188EPhyCfg.h
@@ -40,7 +40,7 @@
 
 
 /*------------------------------Define structure----------------------------*/
-typedef enum _SwChnlCmdID{
+enum sw_chnl_cmd_id {
 	CmdID_End,
 	CmdID_SetTxPowerLevel,
 	CmdID_BBRegWrite10,
@@ -48,32 +48,31 @@ typedef enum _SwChnlCmdID{
 	CmdID_WritePortUshort,
 	CmdID_WritePortUchar,
 	CmdID_RF_WriteReg,
-}SwChnlCmdID;
-
+};
 
 /* 1. Switch channel related */
-typedef struct _SwChnlCmd{
-	SwChnlCmdID	CmdID;
+struct sw_chnl_cmd {
+	enum sw_chnl_cmd_id CmdID;
 	u32			Para1;
 	u32			Para2;
 	u32			msDelay;
-}SwChnlCmd;
+};
 
-typedef enum _HW90_BLOCK{
+enum hw90_block {
 	HW90_BLOCK_MAC = 0,
 	HW90_BLOCK_PHY0 = 1,
 	HW90_BLOCK_PHY1 = 2,
 	HW90_BLOCK_RF = 3,
 	HW90_BLOCK_MAXIMUM = 4, // Never use this
-}HW90_BLOCK_E, *PHW90_BLOCK_E;
+};
 
-typedef enum _RF_RADIO_PATH{
+enum rf_radio_path {
 	RF_PATH_A = 0,			//Radio Path A
 	RF_PATH_B = 1,			//Radio Path B
 	RF_PATH_C = 2,			//Radio Path C
 	RF_PATH_D = 3,			//Radio Path D
 	//RF_PATH_MAX				//Max RF number 90 support
-}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E;
+};
 
 #define MAX_PG_GROUP 13
 
@@ -85,7 +84,7 @@ typedef enum _RF_RADIO_PATH{
 #define MAX_CHNL_GROUP_24G		6	// ch1~2, ch3~5, ch6~8,ch9~11,ch12~13,CH 14 total three groups
 #define CHANNEL_GROUP_MAX_88E		6
 
-typedef enum _WIRELESS_MODE {
+enum wireless_mode {
 	WIRELESS_MODE_UNKNOWN = 0x00,
 	WIRELESS_MODE_A			= BIT2,
 	WIRELESS_MODE_B			= BIT0,
@@ -94,10 +93,9 @@ typedef enum _WIRELESS_MODE {
 	WIRELESS_MODE_N_24G	= BIT3,
 	WIRELESS_MODE_N_5G	= BIT4,
 	WIRELESS_MODE_AC		= BIT6
-} WIRELESS_MODE;
+};
 
-
-typedef enum _PHY_Rate_Tx_Power_Offset_Area{
+enum phy_rate_tx_offset_area {
 	RA_OFFSET_LEGACY_OFDM1,
 	RA_OFFSET_LEGACY_OFDM2,
 	RA_OFFSET_HT_OFDM1,
@@ -105,79 +103,59 @@ typedef enum _PHY_Rate_Tx_Power_Offset_Area{
 	RA_OFFSET_HT_OFDM3,
 	RA_OFFSET_HT_OFDM4,
 	RA_OFFSET_HT_CCK,
-}RA_OFFSET_AREA,*PRA_OFFSET_AREA;
-
+};
 
 /* BB/RF related */
-typedef	enum _RF_TYPE_8190P{
+enum RF_TYPE_8190P {
 	RF_TYPE_MIN,	// 0
 	RF_8225=1,			// 1 11b/g RF for verification only
 	RF_8256=2,			// 2 11b/g/n
 	RF_8258=3,			// 3 11a/b/g/n RF
 	RF_6052=4,		// 4 11b/g/n RF
 	//RF_6052=5,		// 4 11b/g/n RF
-	// TODO: We sholud remove this psudo PHY RF after we get new RF.
+	// TODO: We should remove this psudo PHY RF after we get new RF.
 	RF_PSEUDO_11N=5,	// 5, It is a temporality RF.
-}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
-
-
-typedef struct _BB_REGISTER_DEFINITION{
-	u32 rfintfs;			// set software control:
-							//		0x870~0x877[8 bytes]
-
-	u32 rfintfi;			// readback data:
-							//		0x8e0~0x8e7[8 bytes]
+};
 
+struct bb_reg_def {
+	u32 rfintfs;		// set software control:
+				//		0x870~0x877[8 bytes]
+	u32 rfintfi;		// readback data:
+				//		0x8e0~0x8e7[8 bytes]
 	u32 rfintfo;		// output data:
-							//		0x860~0x86f [16 bytes]
-
+				//		0x860~0x86f [16 bytes]
 	u32 rfintfe;		// output enable:
-							//		0x860~0x86f [16 bytes]
-
+				//		0x860~0x86f [16 bytes]
 	u32 rf3wireOffset;	// LSSI data:
-							//		0x840~0x84f [16 bytes]
-
+				//		0x840~0x84f [16 bytes]
 	u32 rfLSSI_Select;	// BB Band Select:
-							//		0x878~0x87f [8 bytes]
-
+				//		0x878~0x87f [8 bytes]
 	u32 rfTxGainStage;	// Tx gain stage:
-							//		0x80c~0x80f [4 bytes]
-
+				//		0x80c~0x80f [4 bytes]
 	u32 rfHSSIPara1;	// wire parameter control1 :
-							//		0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
-
+				//		0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
 	u32 rfHSSIPara2;	// wire parameter control2 :
-							//		0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
-
-	u32 rfSwitchControl; //Tx Rx antenna control :
-							//		0x858~0x85f [16 bytes]
-
+				//		0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
+	u32 rfSwitchControl; 	//Tx Rx antenna control :
+				//		0x858~0x85f [16 bytes]
 	u32 rfAGCControl1;	//AGC parameter control1 :
-							//		0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
-
+				//		0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
 	u32 rfAGCControl2;	//AGC parameter control2 :
-							//		0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
-
-	u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
-							//		0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
-
+				//		0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
+	u32 rfRxIQImbalance;	//OFDM Rx IQ imbalance matrix :
+				//		0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
 	u32 rfRxAFE;		//Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
-							//		0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
-
-	u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
-							//		0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
-
+				//		0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
+	u32 rfTxIQImbalance;	//OFDM Tx IQ imbalance matrix
+				//		0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
 	u32 rfTxAFE;		//Tx IQ DC Offset and Tx DFIR type
-							//		0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
-
+				//		0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
 	u32 rfLSSIReadBack;	//LSSI RF readback data SI mode
-								//		0x8a0~0x8af [16 bytes]
-
+				//		0x8a0~0x8af [16 bytes]
 	u32 rfLSSIReadBackPi;	//LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
+};
 
-}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
-
-typedef struct _R_ANTENNA_SELECT_OFDM{
+struct ant_sel_ofdm {
 	u32			r_tx_antenna:4;
 	u32			r_ant_l:4;
 	u32			r_ant_non_ht:4;
@@ -187,13 +165,13 @@ typedef struct _R_ANTENNA_SELECT_OFDM{
 	u32			r_ant_non_ht_s1:4;
 	u32			OFDM_TXSC:2;
 	u32			Reserved:2;
-}R_ANTENNA_SELECT_OFDM;
+};
 
-typedef struct _R_ANTENNA_SELECT_CCK{
+struct ant_sel_cck {
 	u8			r_cckrx_enable_2:2;
 	u8			r_cckrx_enable:2;
 	u8			r_ccktx_enable:4;
-}R_ANTENNA_SELECT_CCK;
+};
 
 /*------------------------------Define structure----------------------------*/
 
@@ -217,8 +195,8 @@ void	rtl8188e_PHY_SetBBReg(		PADAPTER	Adapter,
 									u32		RegAddr,
 									u32		BitMask,
 									u32		Data	);
-u32	rtl8188e_PHY_QueryRFReg(PADAPTER Adapter, RF_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
-void	rtl8188e_PHY_SetRFReg(PADAPTER Adapter, RF_RADIO_PATH_E	eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
+u32	rtl8188e_PHY_QueryRFReg(PADAPTER Adapter, enum rf_radio_path eRFPath, u32 RegAddr, u32 BitMask);
+void	rtl8188e_PHY_SetRFReg(PADAPTER Adapter, enum rf_radio_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
 
 //
 // Initialization related function
@@ -229,9 +207,9 @@ int	PHY_BBConfig8188E(	PADAPTER	Adapter	);
 int	PHY_RFConfig8188E(	PADAPTER	Adapter	);
 
 /* RF config */
-int	rtl8188e_PHY_ConfigRFWithParaFile(PADAPTER Adapter, u8 * pFileName, RF_RADIO_PATH_E eRFPath);
+int	rtl8188e_PHY_ConfigRFWithParaFile(PADAPTER Adapter, u8 * pFileName, enum rf_radio_path eRFPath);
 int	rtl8188e_PHY_ConfigRFWithHeaderFile(		PADAPTER			Adapter,
-														RF_RADIO_PATH_E		eRFPath);
+														enum rf_radio_path eRFPath);
 
 /* Read initi reg value for tx power setting. */
 void	rtl8192c_PHY_GetHWRegOriginalValue(		PADAPTER		Adapter	);
diff --git a/include/hal_intf.h b/include/hal_intf.h
index acd24de..d6a37df 100644
--- a/include/hal_intf.h
+++ b/include/hal_intf.h
@@ -212,8 +212,8 @@ struct hal_ops {
 
 	u32	(*read_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask);
 	void	(*write_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
-	u32	(*read_rfreg)(_adapter *padapter, RF_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
-	void	(*write_rfreg)(_adapter *padapter, RF_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
+	u32	(*read_rfreg)(_adapter *padapter, enum rf_radio_path eRFPath, u32 RegAddr, u32 BitMask);
+	void	(*write_rfreg)(_adapter *padapter, enum rf_radio_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
 
 	void (*EfusePowerSwitch)(_adapter *padapter, u8 bWrite, u8 PwrState);
 	void (*ReadEFuse)(_adapter *padapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, bool bPseudoTest);
@@ -405,8 +405,8 @@ void rtw_hal_bcn_related_reg_setting(_adapter *padapter);
 
 u32	rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask);
 void	rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
-u32	rtw_hal_read_rfreg(_adapter *padapter, RF_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
-void	rtw_hal_write_rfreg(_adapter *padapter, RF_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
+u32	rtw_hal_read_rfreg(_adapter *padapter, enum rf_radio_path eRFPath, u32 RegAddr, u32 BitMask);
+void	rtw_hal_write_rfreg(_adapter *padapter, enum rf_radio_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
 
 s32	rtw_hal_interrupt_handler(_adapter *padapter);
 
diff --git a/include/rtl8188e_hal.h b/include/rtl8188e_hal.h
index 122e62f..87e6f52 100644
--- a/include/rtl8188e_hal.h
+++ b/include/rtl8188e_hal.h
@@ -302,7 +302,7 @@ typedef struct hal_data_8188e
 	u8	PGMaxGroup;
 	//current WIFI_PHY values
 	u32	ReceiveConfig;
-	WIRELESS_MODE		CurrentWirelessMode;
+	enum wireless_mode CurrentWirelessMode;
 	HT_CHANNEL_WIDTH	CurrentChannelBW;
 	u8	CurrentChannel;
 	u8	nCur40MhzPrimeSC;// Control channel sub-carrier
@@ -390,7 +390,7 @@ typedef struct hal_data_8188e
 	//u8	bCurrentTurboEDCA;
 	u32	AcParam_BE; //Original parameter for BE, use for EDCA turbo.
 
-	BB_REGISTER_DEFINITION_T	PHYRegDef[4];	//Radio A/B/C/D
+	struct bb_reg_def PHYRegDef[4];	//Radio A/B/C/D
 
 	u32	RfRegChnlVal[2];
 
diff --git a/include/rtw_mp.h b/include/rtw_mp.h
index 5ed85c6..10a0723 100644
--- a/include/rtw_mp.h
+++ b/include/rtw_mp.h
@@ -233,7 +233,7 @@ typedef struct _MPT_CONTEXT
 	// The RfPath of IO operation is depend of MptActType.
 	ULONG			MptRfPath;
 
-	WIRELESS_MODE		MptWirelessModeToSw;	// Wireless mode to switch.
+	enum wireless_mode MptWirelessModeToSw;	// Wireless mode to switch.
 	u8			MptChannelToSw;		// Channel to switch.
 	u8			MptInitGainToSet;	// Initial gain to set.
 	//ULONG			bMptAntennaA;		// true if we want to use antenna A.