mirror of
https://github.com/lwfinger/rtl8188eu.git
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Initial commit of flattened driver to repo
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
commit
85df502f5b
241 changed files with 198795 additions and 0 deletions
374
include/rtw_pwrctrl.h
Executable file
374
include/rtw_pwrctrl.h
Executable file
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __RTW_PWRCTRL_H_
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#define __RTW_PWRCTRL_H_
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#include <drv_conf.h>
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#include <osdep_service.h>
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#include <drv_types.h>
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#ifdef CONFIG_HAS_EARLYSUSPEND
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#include <linux/earlysuspend.h>
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#endif //CONFIG_HAS_EARLYSUSPEND
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#define FW_PWR0 0
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#define FW_PWR1 1
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#define FW_PWR2 2
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#define FW_PWR3 3
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#define HW_PWR0 7
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#define HW_PWR1 6
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#define HW_PWR2 2
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#define HW_PWR3 0
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#define HW_PWR4 8
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#define FW_PWRMSK 0x7
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#define XMIT_ALIVE BIT(0)
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#define RECV_ALIVE BIT(1)
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#define CMD_ALIVE BIT(2)
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#define EVT_ALIVE BIT(3)
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enum Power_Mgnt
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{
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PS_MODE_ACTIVE = 0 ,
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PS_MODE_MIN ,
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PS_MODE_MAX ,
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PS_MODE_DTIM ,
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PS_MODE_VOIP ,
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PS_MODE_UAPSD_WMM ,
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PS_MODE_UAPSD ,
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PS_MODE_IBSS ,
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PS_MODE_WWLAN ,
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PM_Radio_Off ,
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PM_Card_Disable ,
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PS_MODE_NUM
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};
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/*
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BIT[2:0] = HW state
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BIT[3] = Protocol PS state, 0: register active state , 1: register sleep state
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BIT[4] = sub-state
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*/
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#define PS_DPS BIT(0)
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#define PS_LCLK (PS_DPS)
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#define PS_RF_OFF BIT(1)
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#define PS_ALL_ON BIT(2)
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#define PS_ST_ACTIVE BIT(3)
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#define PS_ISR_ENABLE BIT(4)
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#define PS_IMR_ENABLE BIT(5)
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#define PS_ACK BIT(6)
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#define PS_TOGGLE BIT(7)
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#define PS_STATE_MASK (0x0F)
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#define PS_STATE_HW_MASK (0x07)
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#define PS_SEQ_MASK (0xc0)
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#define PS_STATE(x) (PS_STATE_MASK & (x))
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#define PS_STATE_HW(x) (PS_STATE_HW_MASK & (x))
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#define PS_SEQ(x) (PS_SEQ_MASK & (x))
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#define PS_STATE_S0 (PS_DPS)
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#define PS_STATE_S1 (PS_LCLK)
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#define PS_STATE_S2 (PS_RF_OFF)
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#define PS_STATE_S3 (PS_ALL_ON)
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#define PS_STATE_S4 ((PS_ST_ACTIVE) | (PS_ALL_ON))
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#define PS_IS_RF_ON(x) ((x) & (PS_ALL_ON))
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#define PS_IS_ACTIVE(x) ((x) & (PS_ST_ACTIVE))
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#define CLR_PS_STATE(x) ((x) = ((x) & (0xF0)))
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struct reportpwrstate_parm {
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unsigned char mode;
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unsigned char state; //the CPWM value
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unsigned short rsvd;
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};
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typedef _sema _pwrlock;
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__inline static void _init_pwrlock(_pwrlock *plock)
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{
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_rtw_init_sema(plock, 1);
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}
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__inline static void _free_pwrlock(_pwrlock *plock)
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{
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_rtw_free_sema(plock);
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}
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__inline static void _enter_pwrlock(_pwrlock *plock)
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{
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_rtw_down_sema(plock);
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}
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__inline static void _exit_pwrlock(_pwrlock *plock)
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{
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_rtw_up_sema(plock);
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}
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#define LPS_DELAY_TIME 1*HZ // 1 sec
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#define EXE_PWR_NONE 0x01
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#define EXE_PWR_IPS 0x02
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#define EXE_PWR_LPS 0x04
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// RF state.
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typedef enum _rt_rf_power_state
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{
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rf_on, // RF is on after RFSleep or RFOff
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rf_sleep, // 802.11 Power Save mode
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rf_off, // HW/SW Radio OFF or Inactive Power Save
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//=====Add the new RF state above this line=====//
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rf_max
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}rt_rf_power_state;
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// RF Off Level for IPS or HW/SW radio off
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#define RT_RF_OFF_LEVL_ASPM BIT(0) // PCI ASPM
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#define RT_RF_OFF_LEVL_CLK_REQ BIT(1) // PCI clock request
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#define RT_RF_OFF_LEVL_PCI_D3 BIT(2) // PCI D3 mode
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#define RT_RF_OFF_LEVL_HALT_NIC BIT(3) // NIC halt, re-initialize hw parameters
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#define RT_RF_OFF_LEVL_FREE_FW BIT(4) // FW free, re-download the FW
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#define RT_RF_OFF_LEVL_FW_32K BIT(5) // FW in 32k
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#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) // Always enable ASPM and Clock Req in initialization.
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#define RT_RF_LPS_DISALBE_2R BIT(30) // When LPS is on, disable 2R if no packet is received or transmittd.
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#define RT_RF_LPS_LEVEL_ASPM BIT(31) // LPS with ASPM
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#define RT_IN_PS_LEVEL(ppsc, _PS_FLAG) ((ppsc->cur_ps_level & _PS_FLAG) ? _TRUE : _FALSE)
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#define RT_CLEAR_PS_LEVEL(ppsc, _PS_FLAG) (ppsc->cur_ps_level &= (~(_PS_FLAG)))
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#define RT_SET_PS_LEVEL(ppsc, _PS_FLAG) (ppsc->cur_ps_level |= _PS_FLAG)
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enum _PS_BBRegBackup_ {
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PSBBREG_RF0 = 0,
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PSBBREG_RF1,
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PSBBREG_RF2,
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PSBBREG_AFE0,
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PSBBREG_TOTALCNT
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};
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enum { // for ips_mode
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IPS_NONE=0,
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IPS_NORMAL,
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IPS_LEVEL_2,
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};
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struct pwrctrl_priv
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{
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_pwrlock lock;
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volatile u8 rpwm; // requested power state for fw
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volatile u8 cpwm; // fw current power state. updated when 1. read from HCPWM 2. driver lowers power level
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volatile u8 tog; // toggling
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volatile u8 cpwm_tog; // toggling
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u8 pwr_mode;
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u8 smart_ps;
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u8 bcn_ant_mode;
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u32 alives;
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_workitem cpwm_event;
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#ifdef CONFIG_LPS_RPWM_TIMER
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u8 brpwmtimeout;
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_workitem rpwmtimeoutwi;
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_timer pwr_rpwm_timer;
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#endif // CONFIG_LPS_RPWM_TIMER
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u8 bpower_saving;
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u8 b_hw_radio_off;
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u8 reg_rfoff;
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u8 reg_pdnmode; //powerdown mode
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u32 rfoff_reason;
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//RF OFF Level
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u32 cur_ps_level;
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u32 reg_rfps_level;
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#ifdef CONFIG_PCI_HCI
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//just for PCIE ASPM
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u8 b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00.
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u8 b_support_backdoor;
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//just for PCIE ASPM
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u8 const_amdpci_aspm;
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#endif
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uint ips_enter_cnts;
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uint ips_leave_cnts;
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u8 ips_mode;
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u8 ips_mode_req; // used to accept the mode setting request, will update to ipsmode later
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uint bips_processing;
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u32 ips_deny_time; /* will deny IPS when system time is smaller than this */
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u8 ps_processing; /* temporarily used to mark whether in rtw_ps_processor */
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u8 bLeisurePs;
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u8 LpsIdleCount;
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u8 power_mgnt;
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u8 bFwCurrentInPSMode;
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u32 DelayLPSLastTimeStamp;
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u8 btcoex_rfon;
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s32 pnp_current_pwr_state;
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u8 pnp_bstop_trx;
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u8 bInternalAutoSuspend;
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u8 bInSuspend;
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#ifdef CONFIG_BT_COEXIST
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u8 bAutoResume;
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u8 autopm_cnt;
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#endif
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u8 bSupportRemoteWakeup;
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#ifdef CONFIG_WOWLAN
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u8 wowlan_mode;
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u8 wowlan_pattern;
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u8 wowlan_magic;
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u8 wowlan_unicast;
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u8 wowlan_pattern_idx;
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u8 wowlan_wake_reason;
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u32 wowlan_pattern_context[8][5];
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#endif // CONFIG_WOWLAN
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_timer pwr_state_check_timer;
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int pwr_state_check_interval;
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u8 pwr_state_check_cnts;
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int ps_flag;
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rt_rf_power_state rf_pwrstate;//cur power state
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//rt_rf_power_state current_rfpwrstate;
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rt_rf_power_state change_rfpwrstate;
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u8 wepkeymask;
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u8 bHWPowerdown;//if support hw power down
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u8 bHWPwrPindetect;
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u8 bkeepfwalive;
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u8 brfoffbyhw;
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unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT];
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#ifdef CONFIG_RESUME_IN_WORKQUEUE
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struct workqueue_struct *rtw_workqueue;
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_workitem resume_work;
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#endif
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#ifdef CONFIG_HAS_EARLYSUSPEND
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struct early_suspend early_suspend;
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u8 do_late_resume;
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#endif //CONFIG_HAS_EARLYSUSPEND
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#ifdef CONFIG_ANDROID_POWER
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android_early_suspend_t early_suspend;
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u8 do_late_resume;
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#endif
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#ifdef CONFIG_INTEL_PROXIM
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u8 stored_power_mgnt;
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#endif
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};
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#define rtw_get_ips_mode_req(pwrctrlpriv) \
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(pwrctrlpriv)->ips_mode_req
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#define rtw_ips_mode_req(pwrctrlpriv, ips_mode) \
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(pwrctrlpriv)->ips_mode_req = (ips_mode)
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#define RTW_PWR_STATE_CHK_INTERVAL 2000
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#define _rtw_set_pwr_state_check_timer(pwrctrlpriv, ms) \
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do { \
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/*DBG_871X("%s _rtw_set_pwr_state_check_timer(%p, %d)\n", __FUNCTION__, (pwrctrlpriv), (ms));*/ \
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_set_timer(&(pwrctrlpriv)->pwr_state_check_timer, (ms)); \
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} while(0)
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#define rtw_set_pwr_state_check_timer(pwrctrlpriv) \
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_rtw_set_pwr_state_check_timer((pwrctrlpriv), (pwrctrlpriv)->pwr_state_check_interval)
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extern void rtw_init_pwrctrl_priv(_adapter *adapter);
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extern void rtw_free_pwrctrl_priv(_adapter * adapter);
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#ifdef CONFIG_LPS_LCLK
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extern s32 rtw_register_tx_alive(PADAPTER padapter);
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extern void rtw_unregister_tx_alive(PADAPTER padapter);
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extern s32 rtw_register_rx_alive(PADAPTER padapter);
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extern void rtw_unregister_rx_alive(PADAPTER padapter);
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extern s32 rtw_register_cmd_alive(PADAPTER padapter);
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extern void rtw_unregister_cmd_alive(PADAPTER padapter);
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extern s32 rtw_register_evt_alive(PADAPTER padapter);
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extern void rtw_unregister_evt_alive(PADAPTER padapter);
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extern void cpwm_int_hdl(PADAPTER padapter, struct reportpwrstate_parm *preportpwrstate);
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extern void LPS_Leave_check(PADAPTER padapter);
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#endif
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extern void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode);
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extern void rtw_set_rpwm(_adapter * padapter, u8 val8);
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extern void LeaveAllPowerSaveMode(PADAPTER Adapter);
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#ifdef CONFIG_IPS
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void ips_enter(_adapter * padapter);
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int ips_leave(_adapter * padapter);
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#endif
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void rtw_ps_processor(_adapter*padapter);
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#ifdef CONFIG_AUTOSUSPEND
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int autoresume_enter(_adapter* padapter);
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#endif
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#ifdef SUPPORT_HW_RFOFF_DETECTED
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rt_rf_power_state RfOnOffDetect(IN PADAPTER pAdapter );
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#endif
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#ifdef CONFIG_LPS
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s32 LPS_RF_ON_check(PADAPTER padapter, u32 delay_ms);
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void LPS_Enter(PADAPTER padapter);
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void LPS_Leave(PADAPTER padapter);
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#endif
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#ifdef CONFIG_RESUME_IN_WORKQUEUE
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void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv);
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#endif //CONFIG_RESUME_IN_WORKQUEUE
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#if defined(CONFIG_HAS_EARLYSUSPEND ) || defined(CONFIG_ANDROID_POWER)
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#define rtw_is_earlysuspend_registered(pwrpriv) (pwrpriv)->early_suspend.suspend
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void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv);
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void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv);
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#endif //CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER
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u8 rtw_interface_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id,u8* val);
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void rtw_set_ips_deny(_adapter *padapter, u32 ms);
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int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller);
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#define rtw_pwr_wakeup(adapter) _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __FUNCTION__)
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#define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms) _rtw_pwr_wakeup(adapter, ips_deffer_ms, __FUNCTION__)
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int rtw_pm_set_ips(_adapter *padapter, u8 mode);
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int rtw_pm_set_lps(_adapter *padapter, u8 mode);
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#endif //__RTL871X_PWRCTRL_H_
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