mirror of
https://github.com/lwfinger/rtl8188eu.git
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rtl8188eu: Convert u4Bytw to u32
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
parent
5f39818cb5
commit
8aad1f53ce
27 changed files with 482 additions and 488 deletions
160
hal/odm.h
160
hal/odm.h
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@ -138,8 +138,8 @@ typedef struct _Dynamic_Initial_Gain_Threshold_
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int RssiLowThresh;
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int RssiHighThresh;
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u4Byte FALowThresh;
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u4Byte FAHighThresh;
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u32 FALowThresh;
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u32 FAHighThresh;
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u1Byte CurSTAConnectState;
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u1Byte PreSTAConnectState;
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@ -164,15 +164,15 @@ typedef struct _Dynamic_Initial_Gain_Threshold_
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u1Byte LargeFAHit;
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u1Byte ForbiddenIGI;
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u4Byte Recover_cnt;
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u32 Recover_cnt;
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u1Byte DIG_Dynamic_MIN_0;
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u1Byte DIG_Dynamic_MIN_1;
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BOOLEAN bMediaConnect_0;
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BOOLEAN bMediaConnect_1;
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u4Byte AntDiv_RSSI_max;
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u4Byte RSSI_max;
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u32 AntDiv_RSSI_max;
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u32 RSSI_max;
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}DIG_T,*pDIG_T;
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typedef struct _Dynamic_Power_Saving_
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@ -186,25 +186,25 @@ typedef struct _Dynamic_Power_Saving_
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int Rssi_val_min;
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u1Byte initialize;
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u4Byte Reg874,RegC70,Reg85C,RegA74;
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u32 Reg874,RegC70,Reg85C,RegA74;
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}PS_T,*pPS_T;
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typedef struct false_ALARM_STATISTICS{
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u4Byte Cnt_Parity_Fail;
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u4Byte Cnt_Rate_Illegal;
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u4Byte Cnt_Crc8_fail;
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u4Byte Cnt_Mcs_fail;
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u4Byte Cnt_Ofdm_fail;
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u4Byte Cnt_Cck_fail;
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u4Byte Cnt_all;
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u4Byte Cnt_Fast_Fsync;
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u4Byte Cnt_SB_Search_fail;
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u4Byte Cnt_OFDM_CCA;
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u4Byte Cnt_CCK_CCA;
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u4Byte Cnt_CCA_all;
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u4Byte Cnt_BW_USC; //Gary
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u4Byte Cnt_BW_LSC; //Gary
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u32 Cnt_Parity_Fail;
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u32 Cnt_Rate_Illegal;
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u32 Cnt_Crc8_fail;
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u32 Cnt_Mcs_fail;
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u32 Cnt_Ofdm_fail;
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u32 Cnt_Cck_fail;
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u32 Cnt_all;
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u32 Cnt_Fast_Fsync;
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u32 Cnt_SB_Search_fail;
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u32 Cnt_OFDM_CCA;
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u32 Cnt_CCK_CCA;
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u32 Cnt_CCA_all;
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u32 Cnt_BW_USC; //Gary
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u32 Cnt_BW_LSC; //Gary
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}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
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typedef struct _Dynamic_Primary_CCA{
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@ -260,7 +260,7 @@ typedef struct _SW_Antenna_Switch_
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// Before link Antenna Switch check
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u1Byte SWAS_NoLink_State;
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u4Byte SWAS_NoLink_BK_Reg860;
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u32 SWAS_NoLink_BK_Reg860;
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BOOLEAN ANTA_ON; //To indicate Ant A is or not
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BOOLEAN ANTB_ON; //To indicate Ant B is on or not
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@ -279,12 +279,12 @@ typedef struct _SW_Antenna_Switch_
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RT_TIMER SwAntennaSwitchTimer;
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#ifdef CONFIG_HW_ANTENNA_DIVERSITY
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//Hybrid Antenna Diversity
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u4Byte CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
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u4Byte CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
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u4Byte OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
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u4Byte OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
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u4Byte RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM];
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u4Byte RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM];
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u32 CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
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u32 CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
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u32 OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
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u32 OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
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u32 RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM];
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u32 RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM];
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u1Byte TxAnt[ASSOCIATE_ENTRY_NUM];
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u1Byte TargetSTA;
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u1Byte antsel;
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@ -296,7 +296,7 @@ typedef struct _SW_Antenna_Switch_
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typedef struct _EDCA_TURBO_ {
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BOOLEAN bCurrentTurboEDCA;
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BOOLEAN bIsCurRDLState;
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u4Byte prv_traffic_idx; // edca turbo
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u32 prv_traffic_idx; // edca turbo
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}EDCA_T,*pEDCA_T;
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@ -306,7 +306,7 @@ typedef struct _ODM_RATE_ADAPTIVE
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u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH
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u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW
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u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW
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u4Byte LastRATR; // RATR Register Content
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u32 LastRATR; // RATR Register Content
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} ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE;
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@ -484,7 +484,7 @@ typedef enum _ODM_Common_Info_Definition
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ODM_CMNINFO_LINK,
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ODM_CMNINFO_RSSI_MIN,
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ODM_CMNINFO_DBG_COMP, // u8Byte
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ODM_CMNINFO_DBG_LEVEL, // u4Byte
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ODM_CMNINFO_DBG_LEVEL, // u32
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ODM_CMNINFO_RA_THRESHOLD_HIGH, // u1Byte
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ODM_CMNINFO_RA_THRESHOLD_LOW, // u1Byte
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ODM_CMNINFO_RF_ANTENNA_TYPE, // u1Byte
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@ -758,8 +758,8 @@ typedef enum tag_CCA_Path
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typedef struct _ODM_RA_Info_
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{
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u1Byte RateID;
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u4Byte RateMask;
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u4Byte RAUseRate;
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u32 RateMask;
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u32 RAUseRate;
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u1Byte RateSGI;
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u1Byte RssiStaRA;
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u1Byte PreRssiStaRA;
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@ -768,10 +768,10 @@ typedef struct _ODM_RA_Info_
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u1Byte PreRate;
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u1Byte HighestRate;
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u1Byte LowestRate;
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u4Byte NscUp;
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u4Byte NscDown;
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u32 NscUp;
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u32 NscDown;
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u16 RTY[5];
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u4Byte TOTAL;
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u32 TOTAL;
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u16 DROP;//Retry over or drop
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u16 DROP1;//LifeTime over
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u1Byte Active;
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@ -800,7 +800,7 @@ typedef struct ODM_RF_Calibration_Structure
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{
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//for tx power tracking
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u4Byte RegA24; // for TempCCK
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u32 RegA24; // for TempCCK
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s4Byte RegE94;
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s4Byte RegE9C;
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s4Byte RegEB4;
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@ -830,7 +830,7 @@ typedef struct ODM_RF_Calibration_Structure
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BOOLEAN bReloadtxpowerindex;
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u1Byte bRfPiEnable;
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u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug
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u32 TXPowerTrackingCallbackCnt; //cosa add for debug
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u1Byte bCCKinCH14;
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u1Byte CCK_index;
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@ -849,25 +849,25 @@ typedef struct ODM_RF_Calibration_Structure
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u1Byte Delta_LCK;
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//for IQK
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u4Byte RegC04;
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u4Byte Reg874;
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u4Byte RegC08;
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u4Byte RegB68;
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u4Byte RegB6C;
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u4Byte Reg870;
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u4Byte Reg860;
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u4Byte Reg864;
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u32 RegC04;
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u32 Reg874;
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u32 RegC08;
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u32 RegB68;
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u32 RegB6C;
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u32 Reg870;
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u32 Reg860;
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u32 Reg864;
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BOOLEAN bIQKInitialized;
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BOOLEAN bLCKInProgress;
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BOOLEAN bAntennaDetected;
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u4Byte ADDA_backup[IQK_ADDA_REG_NUM];
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u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM];
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u4Byte IQK_BB_backup_recover[9];
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u4Byte IQK_BB_backup[IQK_BB_REG_NUM];
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u32 ADDA_backup[IQK_ADDA_REG_NUM];
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u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
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u32 IQK_BB_backup_recover[9];
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u32 IQK_BB_backup[IQK_BB_REG_NUM];
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//for APK
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u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a
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u32 APKoutput[2][2]; //path A/B; output1_1a/output1_2a
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u1Byte bAPKdone;
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u1Byte bAPKThermalMeterIgnore;
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u1Byte bDPdone;
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@ -884,18 +884,18 @@ typedef struct _FAST_ANTENNA_TRAINNING_
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u1Byte antsel_rx_keep_0;
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u1Byte antsel_rx_keep_1;
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u1Byte antsel_rx_keep_2;
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u4Byte antSumRSSI[7];
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u4Byte antRSSIcnt[7];
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u4Byte antAveRSSI[7];
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u32 antSumRSSI[7];
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u32 antRSSIcnt[7];
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u32 antAveRSSI[7];
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u1Byte FAT_State;
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u4Byte TrainIdx;
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u32 TrainIdx;
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u1Byte antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
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u1Byte antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
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u1Byte antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
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u4Byte MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
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u4Byte AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
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u4Byte MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
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u4Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
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u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
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u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
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u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
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u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
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u1Byte RxIdleAnt;
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BOOLEAN bBecomeLinked;
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@ -946,7 +946,7 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
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rtl8192cd_priv fake_priv;
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u8Byte DebugComponents;
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u4Byte DebugLevel;
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u32 DebugLevel;
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//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//
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BOOLEAN bCckHighPower;
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@ -975,11 +975,11 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
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// ODM Platform info AP/ADSL/CE/MP = 1/2/3/4
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u1Byte SupportPlatform;
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// ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K
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u4Byte SupportAbility;
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u32 SupportAbility;
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// ODM PCIE/USB/SDIO/GSPI = 0/1/2/3
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u1Byte SupportInterface;
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// ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/...
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u4Byte SupportICType;
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u32 SupportICType;
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// Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/...
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u1Byte CutVersion;
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// Fab Version TSMC/UMC = 0/1
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@ -999,7 +999,7 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
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BOOLEAN bWIFITest;
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BOOLEAN bDualMacSmartConcurrent;
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u4Byte BK_SupportAbility;
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u32 BK_SupportAbility;
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u1Byte AntDivType;
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//-----------HOOK BEFORE REG INIT-----------//
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@ -1076,27 +1076,27 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
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u1Byte TxRate;
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u1Byte LinkedInterval;
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u1Byte preChannel;
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u4Byte TxagcOffsetValueA;
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u32 TxagcOffsetValueA;
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BOOLEAN IsTxagcOffsetPositiveA;
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u4Byte TxagcOffsetValueB;
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u32 TxagcOffsetValueB;
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BOOLEAN IsTxagcOffsetPositiveB;
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u8Byte lastTxOkCnt;
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u8Byte lastRxOkCnt;
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u4Byte BbSwingOffsetA;
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u32 BbSwingOffsetA;
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BOOLEAN IsBbSwingOffsetPositiveA;
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u4Byte BbSwingOffsetB;
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u32 BbSwingOffsetB;
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BOOLEAN IsBbSwingOffsetPositiveB;
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s1Byte TH_L2H_ini;
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s1Byte TH_EDCCA_HL_diff;
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u4Byte IGI_Base;
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u4Byte IGI_target;
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u32 IGI_Base;
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u32 IGI_target;
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BOOLEAN ForceEDCCA;
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u1Byte AdapEn_RSSI;
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u1Byte AntType;
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u1Byte antdiv_rssi;
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u1Byte antdiv_period;
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u4Byte Force_TH_H;
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u4Byte Force_TH_L;
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u32 Force_TH_H;
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u32 Force_TH_L;
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u1Byte IGI_LowerBound;
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//2 Define STA info.
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@ -1145,7 +1145,7 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
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BOOLEAN RSSI_test;
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EDCA_T DM_EDCA_Table;
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u4Byte WMMEDCA_BE;
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u32 WMMEDCA_BE;
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// Copy from SD4 structure
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//
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// ==================================================
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@ -1412,7 +1412,7 @@ typedef enum tag_SW_Antenna_Switch_Definition
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#define OFDM_TABLE_SIZE_92D 43
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#define CCK_TABLE_SIZE 33
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extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D];
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extern u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D];
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extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
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extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
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@ -1468,9 +1468,9 @@ void ODM_SwAntDivChkPerPktRssi(
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PODM_PHY_INFO_T pPhyInfo
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);
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u4Byte ConvertTo_dB(u4Byte Value);
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u32 ConvertTo_dB(u32 Value);
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u4Byte
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u32
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GetPSDData(
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PDM_ODM_T pDM_Odm,
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unsigned int point,
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@ -1481,10 +1481,10 @@ odm_DIGbyRSSI_LPS(
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PDM_ODM_T pDM_Odm
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);
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u4Byte ODM_Get_Rate_Bitmap(
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u32 ODM_Get_Rate_Bitmap(
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PDM_ODM_T pDM_Odm,
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u4Byte macid,
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u4Byte ra_mask,
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u32 macid,
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u32 ra_mask,
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u1Byte rssi_level);
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void ODM_DMInit(PDM_ODM_T pDM_Odm);
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@ -1498,7 +1498,7 @@ void
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ODM_CmnInfoInit(
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PDM_ODM_T pDM_Odm,
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ODM_CMNINFO_E CmnInfo,
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u4Byte Value
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u32 Value
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);
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void
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@ -1519,7 +1519,7 @@ ODM_CmnInfoPtrArrayHook(
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void
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ODM_CmnInfoUpdate(
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PDM_ODM_T pDM_Odm,
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u4Byte CmnInfo,
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u32 CmnInfo,
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u8Byte Value
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);
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@ -1547,7 +1547,7 @@ void
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ODM_AntselStatistics_88C(
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PDM_ODM_T pDM_Odm,
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u1Byte MacId,
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u4Byte PWDBAll,
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u32 PWDBAll,
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BOOLEAN isCCKrate
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);
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