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rtl8188eu: Make this code look exactly like the code in the kernel version

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2013-11-29 16:10:20 -06:00
parent 9ac6886fe0
commit 91938194fd
43 changed files with 182 additions and 845 deletions
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429
hal/HalPhyRf_8188e.c
View file

@ -819,7 +819,7 @@ void _PHY_SaveADDARegisters(struct adapter *adapt, u32 *ADDAReg, u32 *ADDABackup
struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt);
struct odm_dm_struct *dm_odm = &pHalData->odmpriv;
if (ODM_CheckPowerStatus(adapt) == false)
if (!ODM_CheckPowerStatus(adapt))
return;
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n"));
@ -888,7 +888,7 @@ _PHY_PathADDAOn(
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n"));
pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4;
if (false == is2t) {
if (!is2t) {
pathOn = 0x0bdb25a0;
ODM_SetBBReg(dm_odm, ADDAReg[0], bMaskDWord, 0x0b1b25a0);
} else {
@ -1276,407 +1276,6 @@ static void phy_LCCalibrate_8188E(struct adapter *adapt, bool is2t)
}
}
/* Analog Pre-distortion calibration */
#define APK_BB_REG_NUM 8
#define APK_CURVE_REG_NUM 4
#define PATH_NUM 2
static void phy_APCalibrate_8188E(struct adapter *adapt, s8 delta, bool is2t)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt);
struct odm_dm_struct *dm_odm = &pHalData->odmpriv;
u32 regD[PATH_NUM];
u32 tmpreg, index, offset, apkbound;
u8 path, i, pathbound = PATH_NUM;
u32 BB_backup[APK_BB_REG_NUM];
u32 BB_REG[APK_BB_REG_NUM] = {
rFPGA1_TxBlock, rOFDM0_TRxPathEnable,
rFPGA0_RFMOD, rOFDM0_TRMuxPar,
rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW,
rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE };
u32 BB_AP_MODE[APK_BB_REG_NUM] = {
0x00000020, 0x00a05430, 0x02040000,
0x000800e4, 0x00204000 };
u32 BB_normal_AP_MODE[APK_BB_REG_NUM] = {
0x00000020, 0x00a05430, 0x02040000,
0x000800e4, 0x22204000 };
u32 AFE_backup[IQK_ADDA_REG_NUM];
u32 AFE_REG[IQK_ADDA_REG_NUM] = {
rFPGA0_XCD_SwitchControl, rBlue_Tooth,
rRx_Wait_CCA, rTx_CCK_RFON,
rTx_CCK_BBON, rTx_OFDM_RFON,
rTx_OFDM_BBON, rTx_To_Rx,
rTx_To_Tx, rRx_CCK,
rRx_OFDM, rRx_Wait_RIFS,
rRx_TO_Rx, rStandby,
rSleep, rPMPD_ANAEN };
u32 MAC_backup[IQK_MAC_REG_NUM];
u32 MAC_REG[IQK_MAC_REG_NUM] = {
REG_TXPAUSE, REG_BCN_CTRL,
REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
u32 APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
{0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},
{0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}
};
u32 APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
{0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, /* path settings equal to path b settings */
{0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}
};
u32 APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
{0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},
{0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}
};
u32 APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
{0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, /* path settings equal to path b settings */
{0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
};
u32 AFE_on_off[PATH_NUM] = {
0x04db25a4, 0x0b1b25a4}; /* path A on path B off / path A off path B on */
u32 APK_offset[PATH_NUM] = {
rConfig_AntA, rConfig_AntB};
u32 APK_normal_offset[PATH_NUM] = {
rConfig_Pmpd_AntA, rConfig_Pmpd_AntB};
u32 APK_value[PATH_NUM] = {
0x92fc0000, 0x12fc0000};
u32 APK_normal_value[PATH_NUM] = {
0x92680000, 0x12680000};
s8 APK_delta_mapping[APK_BB_REG_NUM][13] = {
{-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
{-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
{-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
{-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},
{-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}
};
u32 APK_normal_setting_value_1[13] = {
0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,
0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,
0x12680000, 0x00880000, 0x00880000
};
u32 APK_normal_setting_value_2[16] = {
0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,
0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,
0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,
0x00050006
};
u32 APK_result[PATH_NUM][APK_BB_REG_NUM]; /* val_1_1a, val_1_2a, val_2a, val_3a, val_4a */
s32 BB_offset, delta_V, delta_offset;
if (*(dm_odm->mp_mode) == 1) {
struct mpt_context *pMptCtx = &(adapt->mppriv.MptCtx);
pMptCtx->APK_bound[0] = 45;
pMptCtx->APK_bound[1] = 52;
}
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta));
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2t ? "2T2R" : "1T1R")));
if (!is2t)
pathbound = 1;
/* 2 FOR NORMAL CHIP SETTINGS */
/* Temporarily do not allow normal driver to do the following settings
* because these offset and value will cause RF internal PA to be
* unpredictably disabled by HW, such that RF Tx signal will disappear
* after disable/enable card many times on 88CU. RF SD and DD have not
* find the root cause, so we remove these actions temporarily.
*/
if (*(dm_odm->mp_mode) != 1)
return;
/* settings adjust for normal chip */
for (index = 0; index < PATH_NUM; index++) {
APK_offset[index] = APK_normal_offset[index];
APK_value[index] = APK_normal_value[index];
AFE_on_off[index] = 0x6fdb25a4;
}
for (index = 0; index < APK_BB_REG_NUM; index++) {
for (path = 0; path < pathbound; path++) {
APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index];
APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index];
}
BB_AP_MODE[index] = BB_normal_AP_MODE[index];
}
apkbound = 6;
/* save BB default value */
for (index = 0; index < APK_BB_REG_NUM; index++) {
if (index == 0) /* skip */
continue;
BB_backup[index] = ODM_GetBBReg(dm_odm, BB_REG[index], bMaskDWord);
}
/* save MAC default value */
_PHY_SaveMACRegisters(adapt, MAC_REG, MAC_backup);
/* save AFE default value */
_PHY_SaveADDARegisters(adapt, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
for (path = 0; path < pathbound; path++) {
if (path == RF_PATH_A) {
/* path A APK */
/* load APK setting */
/* path-A */
offset = rPdp_AntA;
for (index = 0; index < 11; index++) {
ODM_SetBBReg(dm_odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n",
offset, ODM_GetBBReg(dm_odm, offset, bMaskDWord)));
offset += 0x04;
}
ODM_SetBBReg(dm_odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
offset = rConfig_AntA;
for (; index < 13; index++) {
ODM_SetBBReg(dm_odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n",
offset, ODM_GetBBReg(dm_odm, offset, bMaskDWord)));
offset += 0x04;
}
/* page-B1 */
ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x40000000);
/* path A */
offset = rPdp_AntA;
for (index = 0; index < 16; index++) {
ODM_SetBBReg(dm_odm, offset, bMaskDWord, APK_normal_setting_value_2[index]);
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n",
offset, ODM_GetBBReg(dm_odm, offset, bMaskDWord)));
offset += 0x04;
}
ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
} else if (path == RF_PATH_B) {
/* path B APK */
/* load APK setting */
/* path-B */
offset = rPdp_AntB;
for (index = 0; index < 10; index++) {
ODM_SetBBReg(dm_odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n",
offset, ODM_GetBBReg(dm_odm, offset, bMaskDWord)));
offset += 0x04;
}
ODM_SetBBReg(dm_odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000);
PHY_SetBBReg(adapt, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
offset = rConfig_AntA;
index = 11;
for (; index < 13; index++) { /* offset 0xb68, 0xb6c */
ODM_SetBBReg(dm_odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n",
offset, ODM_GetBBReg(dm_odm, offset, bMaskDWord)));
offset += 0x04;
}
/* page-B1 */
ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x40000000);
/* path B */
offset = 0xb60;
for (index = 0; index < 16; index++) {
ODM_SetBBReg(dm_odm, offset, bMaskDWord, APK_normal_setting_value_2[index]);
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n",
offset, ODM_GetBBReg(dm_odm, offset, bMaskDWord)));
offset += 0x04;
}
ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0);
}
/* save RF default value */
regD[path] = PHY_QueryRFReg(adapt, path, RF_TXBIAS_A, bMaskDWord);
/* Path A AFE all on, path B AFE All off or vise versa */
for (index = 0; index < IQK_ADDA_REG_NUM; index++)
ODM_SetBBReg(dm_odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]);
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
("phy_APCalibrate_8188E() offset 0xe70 %x\n",
ODM_GetBBReg(dm_odm, rRx_Wait_CCA, bMaskDWord)));
/* BB to AP mode */
if (path == 0) {
for (index = 0; index < APK_BB_REG_NUM; index++) {
if (index == 0) /* skip */
continue;
else if (index < 5)
ODM_SetBBReg(dm_odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]);
else if (BB_REG[index] == 0x870)
ODM_SetBBReg(dm_odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);
else
ODM_SetBBReg(dm_odm, BB_REG[index], BIT10, 0x0);
}
ODM_SetBBReg(dm_odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
ODM_SetBBReg(dm_odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
} else {
/* path B */
ODM_SetBBReg(dm_odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);
ODM_SetBBReg(dm_odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);
}
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
("phy_APCalibrate_8188E() offset 0x800 %x\n",
ODM_GetBBReg(dm_odm, 0x800, bMaskDWord)));
/* MAC settings */
_PHY_MACSettingCalibration(adapt, MAC_REG, MAC_backup);
if (path == RF_PATH_A) {
/* Path B to standby mode */
ODM_SetRFReg(dm_odm, RF_PATH_B, RF_AC, bMaskDWord, 0x10000);
} else {
/* Path A to standby mode */
ODM_SetRFReg(dm_odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000);
ODM_SetRFReg(dm_odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);
ODM_SetRFReg(dm_odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103);
}
delta_offset = ((delta+14)/2);
if (delta_offset < 0)
delta_offset = 0;
else if (delta_offset > 12)
delta_offset = 12;
/* AP calibration */
for (index = 0; index < APK_BB_REG_NUM; index++) {
if (index != 1) /* only DO PA11+PAD01001, AP RF setting */
continue;
tmpreg = APK_RF_init_value[path][index];
if (!dm_odm->RFCalibrateInfo.bAPKThermalMeterIgnore) {
BB_offset = (tmpreg & 0xF0000) >> 16;
if (!(tmpreg & BIT15)) /* sign bit 0 */
BB_offset = -BB_offset;
delta_V = APK_delta_mapping[index][delta_offset];
BB_offset += delta_V;
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
("phy_APCalibrate_8188E() APK index %d tmpreg 0x%x delta_V %d delta_offset %d\n",
index, tmpreg, delta_V, delta_offset));
if (BB_offset < 0) {
tmpreg = tmpreg & (~BIT15);
BB_offset = -BB_offset;
} else {
tmpreg = tmpreg | BIT15;
}
tmpreg = (tmpreg & 0xFFF0FFFF) | (BB_offset << 16);
}
ODM_SetRFReg(dm_odm, path, RF_IPA_A, bMaskDWord, 0x8992e);
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(adapt, path, RF_IPA_A, bMaskDWord)));
ODM_SetRFReg(dm_odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]);
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(adapt, path, RF_AC, bMaskDWord)));
ODM_SetRFReg(dm_odm, path, RF_TXBIAS_A, bMaskDWord, tmpreg);
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(adapt, path, RF_TXBIAS_A, bMaskDWord)));
/* PA11+PAD01111, one shot */
i = 0;
do {
ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x80000000);
ODM_SetBBReg(dm_odm, APK_offset[path], bMaskDWord, APK_value[0]);
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(dm_odm, APK_offset[path], bMaskDWord)));
ODM_delay_ms(3);
ODM_SetBBReg(dm_odm, APK_offset[path], bMaskDWord, APK_value[1]);
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(dm_odm, APK_offset[path], bMaskDWord)));
ODM_delay_ms(20);
ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
if (path == RF_PATH_A)
tmpreg = ODM_GetBBReg(dm_odm, rAPK, 0x03E00000);
else
tmpreg = ODM_GetBBReg(dm_odm, rAPK, 0xF8000000);
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpreg));
i++;
} while (tmpreg > apkbound && i < 4);
APK_result[path][index] = tmpreg;
}
}
/* reload MAC default value */
_PHY_ReloadMACRegisters(adapt, MAC_REG, MAC_backup);
/* reload BB default value */
for (index = 0; index < APK_BB_REG_NUM; index++) {
if (index == 0) /* skip */
continue;
ODM_SetBBReg(dm_odm, BB_REG[index], bMaskDWord, BB_backup[index]);
}
/* reload AFE default value */
reload_adda_reg(adapt, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
/* reload RF path default value */
for (path = 0; path < pathbound; path++) {
ODM_SetRFReg(dm_odm, path, 0xd, bMaskDWord, regD[path]);
if (path == RF_PATH_B) {
ODM_SetRFReg(dm_odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);
ODM_SetRFReg(dm_odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101);
}
/* note no index == 0 */
if (APK_result[path][1] > 6)
APK_result[path][1] = 6;
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1]));
}
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n"));
for (path = 0; path < pathbound; path++) {
ODM_SetRFReg(dm_odm, path, 0x3, bMaskDWord,
((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1]));
if (path == RF_PATH_A)
ODM_SetRFReg(dm_odm, path, 0x4, bMaskDWord,
((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05));
else
ODM_SetRFReg(dm_odm, path, 0x4, bMaskDWord,
((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05));
ODM_SetRFReg(dm_odm, path, RF_BS_PA_APSET_G9_G11, bMaskDWord,
((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08));
}
dm_odm->RFCalibrateInfo.bAPKdone = true;
ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n"));
}
#define DP_BB_REG_NUM 7
#define DP_RF_REG_NUM 1
#define DP_RETRY_LIMIT 10
#define DP_PATH_NUM 2
#define DP_DPK_NUM 3
#define DP_DPK_VALUE_NUM 2
void PHY_IQCalibrate_8188E(struct adapter *adapt, bool recovery)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt);
@ -1697,7 +1296,7 @@ void PHY_IQCalibrate_8188E(struct adapter *adapt, bool recovery)
bool is2t;
is2t = (dm_odm->RFType == ODM_2T2R) ? true : false;
if (ODM_CheckPowerStatus(adapt) == false)
if (!ODM_CheckPowerStatus(adapt))
return;
if (!(dm_odm->SupportAbility & ODM_RF_CALIBRATION))
@ -1867,28 +1466,6 @@ void PHY_LCCalibrate_8188E(struct adapter *adapt)
("LCK:Finish!!!interface %d\n", dm_odm->InterfaceIndex));
}
void PHY_APCalibrate_8188E(struct adapter *adapt, s8 delta)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt);
struct odm_dm_struct *dm_odm = &pHalData->odmpriv;
return;
if (!(dm_odm->SupportAbility & ODM_RF_CALIBRATION))
return;
#if FOR_BRAZIL_PRETEST != 1
if (dm_odm->RFCalibrateInfo.bAPKdone)
#endif
return;
if (dm_odm->RFType == ODM_2T2R) {
phy_APCalibrate_8188E(adapt, delta, true);
} else {
/* For 88C 1T1R */
phy_APCalibrate_8188E(adapt, delta, false);
}
}
static void phy_setrfpathswitch_8188e(struct adapter *adapt, bool main, bool is2t)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(adapt);

2
hal/HalPwrSeqCmd.c
View file

@ -85,7 +85,7 @@ u8 HalPwrSeqCmdParsing(struct adapter *padapter, u8 cut_vers, u8 fab_vers,
value &= ~(GET_PWR_CFG_MASK(pwrcfgcmd));
value |= (GET_PWR_CFG_VALUE(pwrcfgcmd) & GET_PWR_CFG_MASK(pwrcfgcmd));
/* Write the value back to sytem register */
/* Write the value back to system register */
rtw_write8(padapter, offset, value);
break;
case PWR_CMD_POLLING:

8
hal/rtl8188e_cmd.c
View file

@ -484,7 +484,7 @@ static void ConstructProbeRsp(struct adapter *adapt, u8 *pframe, u32 *pLength, u
*pLength = pktlen;
}
/* To check if reserved page content is destroyed by beacon beacuse beacon is too large. */
/* To check if reserved page content is destroyed by beacon because beacon is too large. */
/* 2010.06.23. Added by tynli. */
void CheckFwRsvdPageContent(struct adapter *Adapter)
{
@ -496,9 +496,9 @@ void CheckFwRsvdPageContent(struct adapter *Adapter)
/* (1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp. */
/* Input: */
/* bDLFinished - false: At the first time we will send all the packets as a large packet to Hw, */
/* so we need to set the packet length to total lengh. */
/* so we need to set the packet length to total length. */
/* true: At the second time, we should send the first packet (default:beacon) */
/* to Hw again and set the lengh in descriptor to the real beacon lengh. */
/* to Hw again and set the length in descriptor to the real beacon length. */
/* 2009.10.15 by tynli. */
static void SetFwRsvdPagePkt(struct adapter *adapt, bool bDLFinished)
{
@ -671,7 +671,7 @@ _func_enter_;
DBG_88E("%s: 1 Download RSVD success! DLBcnCount:%u, poll:%u\n", __func__, DLBcnCount, poll);
/* */
/* We just can send the reserved page twice during the time that Tx thread is stopped (e.g. pnpsetpower) */
/* becuase we need to free the Tx BCN Desc which is used by the first reserved page packet. */
/* because we need to free the Tx BCN Desc which is used by the first reserved page packet. */
/* At run time, we cannot get the Tx Desc until it is released in TxHandleInterrupt() so we will return */
/* the beacon TCB in the following code. 2011.11.23. by tynli. */
/* */

8
hal/rtl8188e_hal_init.c
View file

@ -1489,7 +1489,6 @@ static bool hal_EfusePgPacketWrite1ByteHeader(struct adapter *pAdapter, u8 efuse
static bool hal_EfusePgPacketWriteData(struct adapter *pAdapter, u8 efuseType, u16 *pAddr, struct pgpkt *pTargetPkt, bool bPseudoTest)
{
bool bRet = false;
u16 efuse_addr = *pAddr;
u8 badworden = 0;
u32 PgWriteSuccess = 0;
@ -1507,7 +1506,6 @@ static bool hal_EfusePgPacketWriteData(struct adapter *pAdapter, u8 efuseType, u
else
return true;
}
return bRet;
}
static bool
@ -1663,7 +1661,7 @@ hal_EfusePgCheckAvailableAddr(
{
u16 efuse_max_available_len = 0;
/* Change to check TYPE_EFUSE_MAP_LEN , beacuse 8188E raw 256, logic map over 256. */
/* Change to check TYPE_EFUSE_MAP_LEN , because 8188E raw 256, logic map over 256. */
EFUSE_GetEfuseDefinition(pAdapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&efuse_max_available_len, false);
if (Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest) >= efuse_max_available_len)
@ -2110,7 +2108,7 @@ static u8 Hal_GetChnlGroup88E(u8 chnl, u8 *pGroup)
if (chnl <= 14) {
bIn24G = true;
if (chnl < 3) /* Chanel 1-2 */
if (chnl < 3) /* Channel 1-2 */
*pGroup = 0;
else if (chnl < 6) /* Channel 3-5 */
*pGroup = 1;
@ -2192,7 +2190,7 @@ void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *PROMContent, bool Auto
pHalData->bTXPowerDataReadFromEEPORM = true;
for (rfPath = 0; rfPath < pHalData->NumTotalRFPath; rfPath++) {
for (ch = 0; ch <= CHANNEL_MAX_NUMBER; ch++) {
for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
bIn24G = Hal_GetChnlGroup88E(ch, &group);
if (bIn24G) {
pHalData->Index24G_CCK_Base[rfPath][ch] = pwrInfo24G.IndexCCK_Base[rfPath][group];

8
hal/rtl8188e_phycfg.c
View file

@ -559,7 +559,7 @@ static int phy_BB8188E_Config_ParaFile(struct adapter *Adapter)
/* */
/* 1. Read PHY_REG.TXT BB INIT!! */
/* We will seperate as 88C / 92C according to chip version */
/* We will separate as 88C / 92C according to chip version */
/* */
if (HAL_STATUS_FAILURE == ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
rtStatus = _FAIL;
@ -685,7 +685,7 @@ static u8 phy_DbmToTxPwrIdx(struct adapter *Adapter, enum wireless_mode Wireless
/* */
/* Tested by MP, we found that CCK Index 0 equals to 8dbm, OFDM legacy equals to */
/* 3dbm, and OFDM HT equals to 0dbm repectively. */
/* 3dbm, and OFDM HT equals to 0dbm respectively. */
/* Note: */
/* The mapping may be different by different NICs. Do not use this formula for what needs accurate result. */
/* By Bruce, 2008-01-29. */
@ -1006,12 +1006,12 @@ _PHY_SetBWMode92C(
switch (pHalData->CurrentChannelBW) {
case HT_CHANNEL_WIDTH_20:
regBwOpMode |= BW_OPMODE_20MHZ;
/* 2007/02/07 Mark by Emily becasue we have not verify whether this register works */
/* 2007/02/07 Mark by Emily because we have not verify whether this register works */
rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
break;
case HT_CHANNEL_WIDTH_40:
regBwOpMode &= ~BW_OPMODE_20MHZ;
/* 2007/02/07 Mark by Emily becasue we have not verify whether this register works */
/* 2007/02/07 Mark by Emily because we have not verify whether this register works */
rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
regRRSR_RSC = (regRRSR_RSC&0x90) | (pHalData->nCur40MhzPrimeSC<<5);
rtw_write8(Adapter, REG_RRSR+2, regRRSR_RSC);

10
hal/rtl8188e_rf6052.c
View file

@ -181,7 +181,7 @@ i * Currently, we cannot fully disable driver dynamic
* tx power mechanism because it is referenced by BT
* coexist mechanism.
* In the future, two mechanism shall be separated from
* each other and maintained independantly. */
* each other and maintained independently. */
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) {
TxAGC[RF_PATH_A] = 0x10101010;
TxAGC[RF_PATH_B] = 0x10101010;
@ -216,11 +216,11 @@ i * Currently, we cannot fully disable driver dynamic
ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 1, &direction, &pwrtrac_value);
if (direction == 1) {
/* Increase TX pwoer */
/* Increase TX power */
TxAGC[0] += pwrtrac_value;
TxAGC[1] += pwrtrac_value;
} else if (direction == 2) {
/* Decrease TX pwoer */
/* Decrease TX power */
TxAGC[0] -= pwrtrac_value;
TxAGC[1] -= pwrtrac_value;
}
@ -292,7 +292,7 @@ static void get_rx_power_val_by_reg(struct adapter *Adapter, u8 Channel,
if (pHalData->pwrGroupCnt == 1)
chnlGroup = 0;
if (pHalData->pwrGroupCnt >= pHalData->PGMaxGroup) {
if (Channel < 3) /* Chanel 1-2 */
if (Channel < 3) /* Channel 1-2 */
chnlGroup = 0;
else if (Channel < 6) /* Channel 3-5 */
chnlGroup = 1;
@ -349,7 +349,7 @@ static void get_rx_power_val_by_reg(struct adapter *Adapter, u8 Channel,
}
/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */
/* In the future, two mechanism shall be separated from each other and maintained independently. Thanks for Lanhsin's reminder. */
/* 92d do not need this */
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
writeVal = 0x14141414;

2
hal/rtl8188eu_xmit.c
View file

@ -332,7 +332,7 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz, u8 bag
/* 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS. */
/* (1) The sequence number of each non-Qos frame / broadcast / multicast / */
/* mgnt frame should be controled by Hw because Fw will also send null data */
/* mgnt frame should be controlled by Hw because Fw will also send null data */
/* which we cannot control when Fw LPS enable. */
/* --> default enable non-Qos data sequense number. 2010.06.23. by tynli. */
/* (2) Enable HW SEQ control for beacon packet, because we use Hw beacon. */

10
hal/usb_halinit.c
View file

@ -464,7 +464,7 @@ static void _InitRetryFunction(struct adapter *Adapter)
/*-----------------------------------------------------------------------------
* Function: usb_AggSettingTxUpdate()
*
* Overview: Seperate TX/RX parameters update independent for TP detection and
* Overview: Separate TX/RX parameters update independent for TP detection and
* dynamic TX/RX aggreagtion parameters update.
*
* Input: struct adapter *
@ -473,7 +473,7 @@ static void _InitRetryFunction(struct adapter *Adapter)
*
* Revised History:
* When Who Remark
* 12/10/2010 MHC Seperate to smaller function.
* 12/10/2010 MHC Separate to smaller function.
*
*---------------------------------------------------------------------------*/
static void usb_AggSettingTxUpdate(struct adapter *Adapter)
@ -496,7 +496,7 @@ static void usb_AggSettingTxUpdate(struct adapter *Adapter)
/*-----------------------------------------------------------------------------
* Function: usb_AggSettingRxUpdate()
*
* Overview: Seperate TX/RX parameters update independent for TP detection and
* Overview: Separate TX/RX parameters update independent for TP detection and
* dynamic TX/RX aggreagtion parameters update.
*
* Input: struct adapter *
@ -505,7 +505,7 @@ static void usb_AggSettingTxUpdate(struct adapter *Adapter)
*
* Revised History:
* When Who Remark
* 12/10/2010 MHC Seperate to smaller function.
* 12/10/2010 MHC Separate to smaller function.
*
*---------------------------------------------------------------------------*/
static void
@ -847,7 +847,7 @@ _func_enter_;
/* */
/* Init CR MACTXEN, MACRXEN after setting RxFF boundary REG_TRXFF_BNDY to patch */
/* Hw bug which Hw initials RxFF boundry size to a value which is larger than the real Rx buffer size in 88E. */
/* Hw bug which Hw initials RxFF boundary size to a value which is larger than the real Rx buffer size in 88E. */
/* */
/* Enable MACTXEN/MACRXEN block */
value16 = rtw_read16(Adapter, REG_CR);

72
hal/usb_ops_linux.c
View file

@ -267,54 +267,28 @@ static int usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val)
static int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata)
{
struct adapter *adapt = pintfhdl->padapter;
struct dvobj_priv *dvobjpriv = adapter_to_dvobj(adapt);
struct usb_device *udev = dvobjpriv->pusbdev;
u8 request = REALTEK_USB_VENQT_CMD_REQ;
u8 reqtype = REALTEK_USB_VENQT_WRITE;
u16 value = (u16)(addr & 0x0000ffff);
u16 index = REALTEK_USB_VENQT_CMD_IDX;
int pipe = usb_sndctrlpipe(udev, 0); /* write_out */
u8 *buffer;
u8 request;
u8 requesttype;
u16 wvalue;
u16 index;
u16 len;
u8 buf[VENDOR_CMD_MAX_DATA_LEN] = {0};
int ret;
int vendorreq_times = 0;
buffer = kmemdup(pdata, length, GFP_ATOMIC);
if (!buffer)
return -ENOMEM;
while (++vendorreq_times <= MAX_USBCTRL_VENDORREQ_TIMES) {
pipe = usb_sndctrlpipe(udev, 0);/* write_out */
_func_enter_;
ret = rtw_usb_control_msg(udev, pipe, request, reqtype,
value, index, buffer, length,
RTW_USB_CONTROL_MSG_TIMEOUT);
request = 0x05;
requesttype = 0x00;/* write_out */
index = 0;/* n/a */
if (ret == length) { /* Success this control transfer. */
rtw_reset_continual_urb_error(dvobjpriv);
} else { /* error cases */
DBG_88E("reg 0x%x, usb %u write fail, status:%d value=0x%x, vendorreq_times:%d\n",
value, length, ret, *(u32 *)pdata, vendorreq_times);
wvalue = (u16)(addr&0x0000ffff);
len = length;
memcpy(buf, pdata, len);
if (ret < 0) {
if (ret == (-ESHUTDOWN) || ret == -ENODEV) {
adapt->bSurpriseRemoved = true;
} else {
struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
haldata->srestpriv.Wifi_Error_Status = USB_VEN_REQ_CMD_FAIL;
}
}
if (rtw_inc_and_chk_continual_urb_error(dvobjpriv)) {
adapt->bSurpriseRemoved = true;
break;
}
}
ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, buf, len, requesttype);
_func_exit_;
/* firmware download is checksumed, don't retry */
if ((value >= FW_8188E_START_ADDRESS &&
value <= FW_8188E_END_ADDRESS) || ret == length)
break;
}
kfree(buffer);
return ret;
}
@ -573,6 +547,8 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs)
RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_read_port_complete : purb->status(%d) != 0\n", purb->status));
DBG_88E("###=> usb_read_port_complete => urb status(%d)\n", purb->status);
skb_put(precvbuf->pskb, purb->actual_length);
precvbuf->pskb = NULL;
if (rtw_inc_and_chk_continual_urb_error(adapter_to_dvobj(adapt)))
adapt->bSurpriseRemoved = true;
@ -631,13 +607,18 @@ _func_enter_;
return _FAIL;
}
if (!precvbuf) {
RT_TRACE(_module_hci_ops_os_c_, _drv_err_,
("usb_read_port:precvbuf==NULL\n"));
return _FAIL;
}
if ((!precvbuf->reuse) || (precvbuf->pskb == NULL)) {
precvbuf->pskb = skb_dequeue(&precvpriv->free_recv_skb_queue);
if (NULL != precvbuf->pskb)
precvbuf->reuse = true;
}
if (precvbuf != NULL) {
rtl8188eu_init_recvbuf(adapter, precvbuf);
/* re-assign for linux based on skb */
@ -690,11 +671,6 @@ _func_enter_;
err, purb->status);
ret = _FAIL;
}
} else {
RT_TRACE(_module_hci_ops_os_c_, _drv_err_,
("usb_read_port:precvbuf ==NULL\n"));
ret = _FAIL;
}
_func_exit_;
return ret;