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rtl8188eu: Fix most errors from smatch

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2015-03-10 11:18:03 -05:00
parent ee006634cb
commit 993b4435cb
40 changed files with 1508 additions and 2204 deletions
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16
hal/Hal8188ERateAdaptive.c
View file

@ -453,14 +453,14 @@ odm_ARFBRefresh_8188E(
}
#if POWER_TRAINING_ACTIVE == 1
if (pRaInfo->HighestRate >0x13)
pRaInfo->PTModeSS=3;
else if(pRaInfo->HighestRate >0x0b)
pRaInfo->PTModeSS=2;
else if(pRaInfo->HighestRate >0x0b)
pRaInfo->PTModeSS=1;
else
pRaInfo->PTModeSS=0;
if (pRaInfo->HighestRate >0x13)
pRaInfo->PTModeSS=3;
else if(pRaInfo->HighestRate >0x0b)
pRaInfo->PTModeSS=2;
else if(pRaInfo->HighestRate >0x0b)
pRaInfo->PTModeSS=1;
else
pRaInfo->PTModeSS=0;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD,
("ODM_ARFBRefresh_8188E(): PTModeSS=%d\n", pRaInfo->PTModeSS));

251
hal/HalHWImg8188E_BB.c
View file

@ -540,12 +540,12 @@ ODM_ReadAndConfig_AGC_TAB_1T_ICUT_8188E(
u32 hex = 0;
u32 i = 0;
u16 count = 0;
u32 * ptr_array = NULL;
u32 *ptr_array = NULL;
u8 platform = pDM_Odm->SupportPlatform;
u8 _interface = pDM_Odm->SupportInterface;
u8 board = pDM_Odm->BoardType;
u32 ArrayLen = sizeof(Array_MP_8188E_AGC_TAB_1T_ICUT)/sizeof(u32);
u32 * Array = Array_MP_8188E_AGC_TAB_1T_ICUT;
u32 *Array = Array_MP_8188E_AGC_TAB_1T_ICUT;
hex += board;
@ -554,50 +554,38 @@ ODM_ReadAndConfig_AGC_TAB_1T_ICUT_8188E(
hex += 0xFF000000;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ReadAndConfig_MP_8188E_AGC_TAB_1T_ICUT, hex = 0x%X\n", hex));
for (i = 0; i < ArrayLen; i += 2 )
{
u32 v1 = Array[i];
u32 v2 = Array[i+1];
for (i = 0; i < ArrayLen; i += 2 ) {
u32 v1 = Array[i];
u32 v2 = Array[i+1];
/* This (offset, data) pair meets the condition. */
if ( v1 < 0xCDCDCDCD )
{
odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2);
continue;
}
else
{ /* This line is the start line of branch. */
if ( !CheckCondition(Array[i], hex) )
{ /* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
{
READ_NEXT_PAIR(v1, v2, i);
}
i -= 2; /* prevent from for-loop += 2 */
}
else /* Configure matched pairs and skip to end of if-else. */
{
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
{
odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2);
READ_NEXT_PAIR(v1, v2, i);
}
/* This (offset, data) pair meets the condition. */
if ( v1 < 0xCDCDCDCD ) {
odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2);
continue;
} else { /* This line is the start line of branch. */
if ( !CheckCondition(Array[i], hex) )
{ /* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
READ_NEXT_PAIR(v1, v2, i);
i -= 2; /* prevent from for-loop += 2 */
} else /* Configure matched pairs and skip to end of if-else. */
{
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2) {
odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2);
READ_NEXT_PAIR(v1, v2, i);
}
while (v2 != 0xDEAD && i < ArrayLen -2)
{
READ_NEXT_PAIR(v1, v2, i);
}
}
while (v2 != 0xDEAD && i < ArrayLen -2)
READ_NEXT_PAIR(v1, v2, i);
}
}
}
}
/******************************************************************************
@ -845,53 +833,43 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
hex += platform << 16;
hex += 0xFF000000;
for (i = 0; i < ArrayLen; i += 2 ) {
u32 v1 = Array[i];
u32 v2 = Array[i+1];
u32 v1 = Array[i];
u32 v2 = Array[i+1];
/* This (offset, data) pair meets the condition. */
if ( v1 < 0xCDCDCDCD ) {
{
odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2);
}
/* This (offset, data) pair meets the condition. */
if ( v1 < 0xCDCDCDCD ) {
odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2);
continue;
}
else
{ /* This line is the start line of branch. */
if ( !CheckCondition(Array[i], hex) )
{ /* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
{
READ_NEXT_PAIR(v1, v2, i);
}
i -= 2; /* prevent from for-loop += 2 */
}
else /* Configure matched pairs and skip to end of if-else. */
{
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
{
{
if ( !CheckCondition(Array[i], hex) )
{ /* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
READ_NEXT_PAIR(v1, v2, i);
i -= 2; /* prevent from for-loop += 2 */
} else /* Configure matched pairs and skip to end of if-else. */
{
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2) {
odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2);
READ_NEXT_PAIR(v1, v2, i);
}
READ_NEXT_PAIR(v1, v2, i);
}
while (v2 != 0xDEAD && i < ArrayLen -2)
{
READ_NEXT_PAIR(v1, v2, i);
}
}
while (v2 != 0xDEAD && i < ArrayLen -2)
READ_NEXT_PAIR(v1, v2, i);
}
}
}
return rst;
}
/******************************************************************************
* PHY_REG_1T_ICUT.TXT
******************************************************************************/
@ -1115,50 +1093,37 @@ ODM_ReadAndConfig_PHY_REG_1T_ICUT_8188E(
hex += 0xFF000000;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ReadAndConfig_MP_8188E_PHY_REG_1T_ICUT, hex = 0x%X\n", hex));
for (i = 0; i < ArrayLen; i += 2 )
{
u32 v1 = Array[i];
u32 v2 = Array[i+1];
for (i = 0; i < ArrayLen; i += 2 ) {
u32 v1 = Array[i];
u32 v2 = Array[i+1];
/* This (offset, data) pair meets the condition. */
if ( v1 < 0xCDCDCDCD )
{
/* This (offset, data) pair meets the condition. */
if ( v1 < 0xCDCDCDCD ) {
odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2);
continue;
}
else
{ /* This line is the start line of branch. */
if ( !CheckCondition(Array[i], hex) )
{ /* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
{
READ_NEXT_PAIR(v1, v2, i);
}
i -= 2; /* prevent from for-loop += 2 */
}
else /* Configure matched pairs and skip to end of if-else. */
{
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
{
continue;
} else { /* This line is the start line of branch. */
if ( !CheckCondition(Array[i], hex) )
{ /* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
READ_NEXT_PAIR(v1, v2, i);
i -= 2; /* prevent from for-loop += 2 */
} else /* Configure matched pairs and skip to end of if-else. */ {
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2) {
odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2);
READ_NEXT_PAIR(v1, v2, i);
}
READ_NEXT_PAIR(v1, v2, i);
}
while (v2 != 0xDEAD && i < ArrayLen -2)
{
READ_NEXT_PAIR(v1, v2, i);
}
}
while (v2 != 0xDEAD && i < ArrayLen -2)
READ_NEXT_PAIR(v1, v2, i);
}
}
}
}
@ -1196,40 +1161,32 @@ ODM_ReadAndConfig_PHY_REG_PG_8188E(
hex += interfaceValue << 8;
hex += platform << 16;
hex += 0xFF000000;
for (i = 0; i < ArrayLen; i += 6 )
{
u32 v1 = Array[i];
u32 v2 = Array[i+1];
u32 v3 = Array[i+2];
u32 v4 = Array[i+3];
u32 v5 = Array[i+4];
u32 v6 = Array[i+5];
/* this line is a line of pure_body */
if ( v1 < 0xCDCDCDCD )
{
for (i = 0; i < ArrayLen; i += 6 ) {
u32 v1 = Array[i];
u32 v2 = Array[i+1];
u32 v3 = Array[i+2];
u32 v4 = Array[i+3];
u32 v5 = Array[i+4];
u32 v6 = Array[i+5];
/* this line is a line of pure_body */
if ( v1 < 0xCDCDCDCD ) {
odm_ConfigBB_PHY_REG_PG_8188E(pDM_Odm, v1, v2, v3);
continue;
}
else
{ /* this line is the start of branch */
if ( !CheckCondition(Array[i], hex) )
{ /* don't need the hw_body */
i += 2; /* skip the pair of expression */
v1 = Array[i];
v2 = Array[i+1];
v3 = Array[i+2];
while (v2 != 0xDEAD)
{
i += 3;
v1 = Array[i];
v2 = Array[i+1];
v3 = Array[i+1];
}
}
}
continue;
} else { /* this line is the start of branch */
if ( !CheckCondition(Array[i], hex) )
{ /* don't need the hw_body */
i += 2; /* skip the pair of expression */
v1 = Array[i];
v2 = Array[i+1];
v3 = Array[i+2];
while (v2 != 0xDEAD) {
i += 3;
v1 = Array[i];
v2 = Array[i+1];
v3 = Array[i+1];
}
}
}
}
}

63
hal/HalHWImg8188E_MAC.c
View file

@ -337,48 +337,37 @@ ODM_ReadAndConfig_MAC_REG_ICUT_8188E(
hex += 0xFF000000;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ReadAndConfig_MP_8188E_MAC_REG_ICUT, hex = 0x%X\n", hex));
for (i = 0; i < ArrayLen; i += 2 )
{
u32 v1 = Array[i];
u32 v2 = Array[i+1];
for (i = 0; i < ArrayLen; i += 2 ) {
u32 v1 = Array[i];
u32 v2 = Array[i+1];
/* This (offset, data) pair meets the condition. */
if ( v1 < 0xCDCDCDCD )
{
/* This (offset, data) pair meets the condition. */
if ( v1 < 0xCDCDCDCD ) {
odm_ConfigMAC_8188E(pDM_Odm, v1, (u8)v2);
continue;
}
else
continue;
} else
{ /* This line is the start line of branch. */
if ( !CheckCondition(Array[i], hex) )
{ /* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
{
READ_NEXT_PAIR(v1, v2, i);
}
i -= 2; /* prevent from for-loop += 2 */
}
else /* Configure matched pairs and skip to end of if-else. */
{
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
{
if ( !CheckCondition(Array[i], hex) )
{ /* Discard the following (offset, data) pairs. */
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
READ_NEXT_PAIR(v1, v2, i);
i -= 2; /* prevent from for-loop += 2 */
} else /* Configure matched pairs and skip to end of if-else. */
{
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2) {
odm_ConfigMAC_8188E(pDM_Odm, v1, (u8)v2);
READ_NEXT_PAIR(v1, v2, i);
}
READ_NEXT_PAIR(v1, v2, i);
}
while (v2 != 0xDEAD && i < ArrayLen -2)
{
READ_NEXT_PAIR(v1, v2, i);
}
}
while (v2 != 0xDEAD && i < ArrayLen -2)
READ_NEXT_PAIR(v1, v2, i);
}
}
}
}

2
hal/HalHWImg8188E_RF.c
View file

@ -399,7 +399,7 @@ ODM_ReadAndConfig_RadioA_1T_ICUT_8188E(
v2 != 0xCDCD && i < ArrayLen -2)
{
odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2);
READ_NEXT_PAIR(v1, v2, i);
READ_NEXT_PAIR(v1, v2, i);
}
while (v2 != 0xDEAD && i < ArrayLen -2)

169
hal/HalPhyRf_8188e.c
View file

@ -76,39 +76,35 @@ static void setIqkMatrix(
ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF;
if (RFPath == RF_PATH_A)
switch (RFPath)
{
case RF_PATH_A:
/* wirte new elements A, C, D to regC80 and regC94, element B is always 0 */
value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A;
ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32);
switch (RFPath) {
case RF_PATH_A:
/* wirte new elements A, C, D to regC80 and regC94, element B is always 0 */
value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A;
ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32);
value32 = (ele_C&0x000003C0)>>6;
ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32);
value32 = (ele_C&0x000003C0)>>6;
ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32);
value32 = ((IqkResult_X * ele_D)>>7)&0x01;
ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32);
break;
case RF_PATH_B:
/* wirte new elements A, C, D to regC88 and regC9C, element B is always 0 */
value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A;
ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32);
value32 = ((IqkResult_X * ele_D)>>7)&0x01;
ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32);
break;
case RF_PATH_B:
/* wirte new elements A, C, D to regC88 and regC9C, element B is always 0 */
value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A;
ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32);
value32 = (ele_C&0x000003C0)>>6;
ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32);
value32 = (ele_C&0x000003C0)>>6;
ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32);
value32 = ((IqkResult_X * ele_D)>>7)&0x01;
ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32);
value32 = ((IqkResult_X * ele_D)>>7)&0x01;
ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32);
break;
default:
break;
}
}
else
{
switch (RFPath)
{
break;
default:
break;
}
} else {
switch (RFPath) {
case RF_PATH_A:
ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[OFDM_index]);
ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00);
@ -126,8 +122,9 @@ static void setIqkMatrix(
}
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n",
(u32)IqkResult_X, (u32)IqkResult_Y, (u32)ele_A, (u32)ele_C, (u32)ele_D, (u32)IqkResult_X, (u32)IqkResult_Y));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n",
(u32)IqkResult_X, (u32)IqkResult_Y, (u32)ele_A, (u32)ele_C, (u32)ele_D, (u32)IqkResult_X, (u32)IqkResult_Y));
}
@ -358,7 +355,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
u8 OFDM_min_index = 6, rf = (is2T) ? 2 : 1; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
u8 Indexforchannel = 0;/*GetRightChnlPlaceforIQK(pHalData->CurrentChannel)*/
enum _POWER_DEC_INC { POWER_DEC, POWER_INC };
enum _POWER_DEC_INC { POWER_DEC, POWER_INC };
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct dm_priv *pdmpriv = &pHalData->dmpriv;
@ -384,8 +381,8 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>odm_TXPowerTrackingCallback_ThermalMeter_8188E, pDM_Odm->BbSwingIdxCckBase: %d, pDM_Odm->BbSwingIdxOfdmBase: %d \n", pDM_Odm->BbSwingIdxCckBase, pDM_Odm->BbSwingIdxOfdmBase));
ThermalValue = (u8)ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_T_METER_88E, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
if( ! ThermalValue || ! pDM_Odm->RFCalibrateInfo.TxPowerTrackControl)
return;
if (!ThermalValue || ! pDM_Odm->RFCalibrateInfo.TxPowerTrackControl)
return;
/* 4 3. Initialize ThermalValues of RFCalibrateInfo */
@ -462,8 +459,8 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
else
pDM_Odm->RFCalibrateInfo.PowerIndexOffset = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast;
for(i = 0; i < rf; i++)
pDM_Odm->RFCalibrateInfo.OFDM_index[i] = pDM_Odm->BbSwingIdxOfdmBase + pDM_Odm->RFCalibrateInfo.PowerIndexOffset;
for(i = 0; i < rf; i++)
pDM_Odm->RFCalibrateInfo.OFDM_index[i] = pDM_Odm->BbSwingIdxOfdmBase + pDM_Odm->RFCalibrateInfo.PowerIndexOffset;
pDM_Odm->RFCalibrateInfo.CCK_index = pDM_Odm->BbSwingIdxCckBase + pDM_Odm->RFCalibrateInfo.PowerIndexOffset;
pDM_Odm->BbSwingIdxCck = pDM_Odm->RFCalibrateInfo.CCK_index;
@ -475,8 +472,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
/* 4 7.1 Handle boundary conditions of index. */
for(i = 0; i < rf; i++)
{
for(i = 0; i < rf; i++) {
if(pDM_Odm->RFCalibrateInfo.OFDM_index[i] > OFDM_TABLE_SIZE_92D-1)
{
pDM_Odm->RFCalibrateInfo.OFDM_index[i] = OFDM_TABLE_SIZE_92D-1;
@ -489,11 +485,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
if(pDM_Odm->RFCalibrateInfo.CCK_index > CCK_TABLE_SIZE-1)
pDM_Odm->RFCalibrateInfo.CCK_index = CCK_TABLE_SIZE-1;
else if (pDM_Odm->RFCalibrateInfo.CCK_index < 0)
pDM_Odm->RFCalibrateInfo.CCK_index = 0;
}
else
{
} else {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("The thermal meter is unchanged or TxPowerTracking OFF: ThermalValue: %d , pDM_Odm->RFCalibrateInfo.ThermalValue: %d)\n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue));
pDM_Odm->RFCalibrateInfo.PowerIndexOffset = 0;
@ -1190,32 +1182,31 @@ phy_SimularityCompare_8188E(
else
{
if (!(SimularityBitMap & 0x03)) /* path A TX OK */
{
for(i = 0; i < 2; i++)
result[3][i] = result[c1][i];
}
if (!(SimularityBitMap & 0x03)) /* path A TX OK */
{
for(i = 0; i < 2; i++)
result[3][i] = result[c1][i];
}
if (!(SimularityBitMap & 0x0c)) /* path A RX OK */
{
for(i = 2; i < 4; i++)
result[3][i] = result[c1][i];
}
if (!(SimularityBitMap & 0x0c)) /* path A RX OK */
{
for(i = 2; i < 4; i++)
result[3][i] = result[c1][i];
}
if (!(SimularityBitMap & 0x30)) /* path B TX OK */
{
for(i = 4; i < 6; i++)
result[3][i] = result[c1][i];
if (!(SimularityBitMap & 0x30)) /* path B TX OK */
{
for(i = 4; i < 6; i++)
result[3][i] = result[c1][i];
}
}
if (!(SimularityBitMap & 0xc0)) /* path B RX OK */
{
for(i = 6; i < 8; i++)
result[3][i] = result[c1][i];
}
if (!(SimularityBitMap & 0xc0)) /* path B RX OK */
{
for(i = 6; i < 8; i++)
result[3][i] = result[c1][i];
}
return false;
return false;
}
}
@ -1258,15 +1249,14 @@ phy_IQCalibrate_8188E(
#else
u32 retryCount = 2;
#endif
if ( *(pDM_Odm->mp_mode) == 1)
retryCount = 9;
if ( *(pDM_Odm->mp_mode) == 1)
retryCount = 9;
else
retryCount = 2;
/* Note: IQ calibration must be performed after loading */
/* PHY_REG.txt , and radio_a, radio_b.txt */
if(t==0)
{
if(t==0) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));
/* Save ADDA parameters, turn Path A ADDA on */
@ -1605,22 +1595,17 @@ if ( *(pDM_Odm->mp_mode) == 1)
/* and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal */
/* will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the */
/* root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. */
/* if MP_DRIVER != 1 */
if (*(pDM_Odm->mp_mode) != 1)
return;
/* endif */
if (*(pDM_Odm->mp_mode) != 1)
return;
/* settings adjust for normal chip */
for(index = 0; index < PATH_NUM; index ++)
{
for(index = 0; index < PATH_NUM; index ++) {
APK_offset[index] = APK_normal_offset[index];
APK_value[index] = APK_normal_value[index];
AFE_on_off[index] = 0x6fdb25a4;
}
for(index = 0; index < APK_BB_REG_NUM; index ++)
{
for(path = 0; path < pathbound; path++)
{
for(index = 0; index < APK_BB_REG_NUM; index ++) {
for(path = 0; path < pathbound; path++) {
APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index];
APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index];
}
@ -1630,8 +1615,7 @@ if (*(pDM_Odm->mp_mode) != 1)
apkbound = 6;
/* save BB default value */
for(index = 0; index < APK_BB_REG_NUM ; index++)
{
for(index = 0; index < APK_BB_REG_NUM ; index++) {
if(index == 0) /* skip */
continue;
BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord);
@ -2089,7 +2073,7 @@ if (*(pDM_Odm->mp_mode) == 1)
_PHY_PathBFillIQKMatrix(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0));
}
Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel);
Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel);
/* To Fix BSOD when final_candidate is 0xff */
/* by sherry 20120321 */
@ -2178,29 +2162,6 @@ PHY_APCalibrate_8188E(
IN s8 delta
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
#if DISABLE_BB_RF
return;
#endif
return;
if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
return;
#if FOR_BRAZIL_PRETEST != 1
if(pDM_Odm->RFCalibrateInfo.bAPKdone)
#endif
return;
if(pDM_Odm->RFType == ODM_2T2R){
phy_APCalibrate_8188E(pAdapter, delta, true);
}
else
{
/* For 88C 1T1R */
phy_APCalibrate_8188E(pAdapter, delta, false);
}
}
static void phy_SetRFPathSwitch_8188E(

189
hal/odm.c
View file

@ -640,7 +640,7 @@ ODM_DMWatchdog(
else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
{
ODM_TXPowerTrackingCheck(pDM_Odm);
odm_EdcaTurboCheck(pDM_Odm);
odm_EdcaTurboCheck(pDM_Odm);
odm_DynamicTxPower(pDM_Odm);
}
@ -1167,32 +1167,28 @@ ODM_Write_DIG(
if(pDM_DigTable->CurIGValue != CurrentIGI)/* if(pDM_DigTable->PreIGValue != CurrentIGI) */
{
if(pDM_Odm->SupportPlatform & (ODM_CE|ODM_MP))
{
if(pDM_Odm->SupportPlatform & (ODM_CE|ODM_MP)) {
ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
if(pDM_Odm->SupportICType != ODM_RTL8188E)
if(pDM_Odm->SupportICType != ODM_RTL8188E)
ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
}
else if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
{
switch(*(pDM_Odm->pOnePathCCA))
{
} else if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) {
switch(*(pDM_Odm->pOnePathCCA)) {
case ODM_CCA_2R:
ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
if(pDM_Odm->SupportICType != ODM_RTL8188E)
if(pDM_Odm->SupportICType != ODM_RTL8188E)
ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
break;
case ODM_CCA_1R_A:
ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
if(pDM_Odm->SupportICType != ODM_RTL8188E)
if(pDM_Odm->SupportICType != ODM_RTL8188E)
ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI));
break;
case ODM_CCA_1R_B:
ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI));
if(pDM_Odm->SupportICType != ODM_RTL8188E)
if(pDM_Odm->SupportICType != ODM_RTL8188E)
ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
break;
}
break;
}
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x). \n",CurrentIGI));
/* pDM_DigTable->PreIGValue = pDM_DigTable->CurIGValue; */
@ -1250,9 +1246,9 @@ odm_DIGbyRSSI_LPS(
RSSI_Lower =DM_DIG_MIN_NIC;
/* Upper and Lower Bound checking */
if(CurrentIGI > DM_DIG_MAX_NIC)
if(CurrentIGI > DM_DIG_MAX_NIC)
CurrentIGI=DM_DIG_MAX_NIC;
else if(CurrentIGI < RSSI_Lower)
else if(CurrentIGI < RSSI_Lower)
CurrentIGI =RSSI_Lower;
ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */
@ -1904,51 +1900,47 @@ odm_FalseAlarmCounterStatistics(
if(!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))
return;
if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
{
/* hold ofdm counter */
if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
/* hold ofdm counter */
ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */
ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */
ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16);
FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16);
ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord);
FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff);
FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16);
FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff);
FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16);
ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord);
FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff);
FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16);
FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff);
FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16);
ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord);
FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff);
FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff);
FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal +
FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal +
FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail +
FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail;
if(pDM_Odm->SupportICType == ODM_RTL8188E)
{
if(pDM_Odm->SupportICType == ODM_RTL8188E)
{
ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_SC_CNT_11N, bMaskDWord);
FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff);
FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16);
}
FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff);
FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16);
}
{
/* hold cck counter */
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT12, 1);
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT14, 1);
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT12, 1);
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT14, 1);
ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
FalseAlmCnt->Cnt_Cck_fail = ret_value;
ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
FalseAlmCnt->Cnt_Cck_fail += (ret_value& 0xff)<<8;
ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) |((ret_value&0xFF00)>>8);
}
FalseAlmCnt->Cnt_all = ( FalseAlmCnt->Cnt_Fast_Fsync +
FalseAlmCnt->Cnt_all = ( FalseAlmCnt->Cnt_Fast_Fsync +
FalseAlmCnt->Cnt_SB_Search_fail +
FalseAlmCnt->Cnt_Parity_Fail +
FalseAlmCnt->Cnt_Rate_Illegal +
@ -1956,33 +1948,33 @@ odm_FalseAlarmCounterStatistics(
FalseAlmCnt->Cnt_Mcs_fail +
FalseAlmCnt->Cnt_Cck_fail);
FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
if(pDM_Odm->SupportICType >=ODM_RTL8723A)
{
/* reset false alarm counter registers */
if(pDM_Odm->SupportICType >=ODM_RTL8723A)
{
/* reset false alarm counter registers */
ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 1);
ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 0);
ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 1);
ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 0);
/* update ofdm counter */
/* update ofdm counter */
ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 0); /* update page C counter */
ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 0); /* update page D counter */
/* reset CCK CCA counter */
/* reset CCK CCA counter */
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 0);
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 2);
/* reset CCK FA counter */
/* reset CCK FA counter */
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 0);
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 2);
}
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n"));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n",
ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n"));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n",
FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n",
ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n",
FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n",
ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n",
FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail));
}
else /* FOR ODM_IC_11AC_SERIES */
@ -3180,28 +3172,24 @@ odm_SetRxIdleAnt(
{
SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
if(Ant != pDM_SWAT_Table->RxIdleAnt)
{
/* for path-A */
if(Ant==1)
if(Ant != pDM_SWAT_Table->RxIdleAnt) {
/* for path-A */
if(Ant==1)
ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF, 0x65a9); /* right-side antenna */
else
else
ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF, 0x569a); /* left-side antenna */
/* for path-B */
if(bDualPath){
/* for path-B */
if(bDualPath){
if(Ant==0)
ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF0000, 0x65a9); /* right-side antenna */
else
else
ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF0000, 0x569a); /* left-side antenna */
}
}
pDM_SWAT_Table->RxIdleAnt = Ant;
pDM_SWAT_Table->RxIdleAnt = Ant;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("RxIdleAnt: %s Reg858=0x%x\n",(Ant==1)?"Ant1":"Ant2",(Ant==1)?0x65a9:0x569a));
/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============odm_SetRxIdleAnt\n")); */
}
}
void
ODM_AntselStatistics_88C(
@ -3800,61 +3788,42 @@ ODM_SingleDualAntennaDetection(
if(pDM_Odm->SupportICType == ODM_RTL8723A)
{
/* 2 Test Ant B based on Ant A is ON */
if(mode==ANTTESTB)
{
if(AntA_report >= 100)
{
if(AntB_report > (AntA_report+1))
{
pDM_SWAT_Table->ANTB_ON=false;
if(mode==ANTTESTB) {
if(AntA_report >= 100) {
if(AntB_report > (AntA_report+1)) {
pDM_SWAT_Table->ANTB_ON=false;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
}
else
{
pDM_SWAT_Table->ANTB_ON=true;
} else {
pDM_SWAT_Table->ANTB_ON=true;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n"));
}
} else {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
pDM_SWAT_Table->ANTB_ON=false; /* Set Antenna B off as default */
bResult = false;
}
}
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
pDM_SWAT_Table->ANTB_ON=false; /* Set Antenna B off as default */
bResult = false;
}
}
/* 2 Test Ant A and B based on DPDT Open */
else if(mode==ANTTESTALL)
{
if((AntO_report >=100)&(AntO_report <118))
{
if(AntA_report > (AntO_report+1))
{
pDM_SWAT_Table->ANTA_ON=false;
/* RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna A is OFF\n")); */
/* 2 Test Ant A and B based on DPDT Open */
else if(mode==ANTTESTALL) {
if((AntO_report >=100)&(AntO_report <118)) {
if(AntA_report > (AntO_report+1)) {
pDM_SWAT_Table->ANTA_ON=false;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant A is OFF"));
}
else
{
pDM_SWAT_Table->ANTA_ON=true;
/* RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna A is ON\n")); */
} else {
pDM_SWAT_Table->ANTA_ON=true;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant A is ON"));
}
}
if(AntB_report > (AntO_report+2))
{
pDM_SWAT_Table->ANTB_ON=false;
/* RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna B is OFF\n")); */
if(AntB_report > (AntO_report+2)) {
pDM_SWAT_Table->ANTB_ON=false;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant B is OFF"));
}
else
{
pDM_SWAT_Table->ANTB_ON=true;
/* RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna B is ON\n")); */
} else {
pDM_SWAT_Table->ANTB_ON=true;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant B is ON"));
}
}
}
}
}
else if(pDM_Odm->SupportICType == ODM_RTL8192C)
{
if(AntA_report >= 100)

112
hal/odm_HWConfig.c
View file

@ -255,71 +255,63 @@ odm_RxPhyStatus92CSeries_Parsing(
PPHY_STATUS_RPT_8192CD_T pPhyStaRpt = (PPHY_STATUS_RPT_8192CD_T)pPhyStatus;
isCCKrate = ((pPktinfo->Rate >= DESC92C_RATE1M ) && (pPktinfo->Rate <= DESC92C_RATE11M ))?true :false;
isCCKrate = (pPktinfo->Rate <= DESC92C_RATE11M) ? true : false;
pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = -1;
pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1;
if(isCCKrate)
{
if(isCCKrate) {
u8 report;
u8 cck_agc_rpt;
pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK++;
/* */
/* (1)Hardware does not provide RSSI for CCK */
/* (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) */
/* */
/* if(pHalData->eRFPowerState == eRfOn) */
cck_highpwr = pDM_Odm->bCckHighPower;
/* else */
/* cck_highpwr = false; */
cck_highpwr = pDM_Odm->bCckHighPower;
cck_agc_rpt = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a ;
/* 2011.11.28 LukeLee: 88E use different LNA & VGA gain table */
/* The RSSI formula should be modified according to the gain table */
/* In 88E, cck_highpwr is always set to 1 */
if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8812))
{
if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8812)) {
LNA_idx = ((cck_agc_rpt & 0xE0) >>5);
VGA_idx = (cck_agc_rpt & 0x1F);
switch(LNA_idx)
{
case 7:
if(VGA_idx <= 27)
rx_pwr_all = -100 + 2*(27-VGA_idx); /* VGA_idx = 27~2 */
else
rx_pwr_all = -100;
break;
case 6:
rx_pwr_all = -48 + 2*(2-VGA_idx); /* VGA_idx = 2~0 */
break;
case 5:
rx_pwr_all = -42 + 2*(7-VGA_idx); /* VGA_idx = 7~5 */
break;
case 4:
rx_pwr_all = -36 + 2*(7-VGA_idx); /* VGA_idx = 7~4 */
break;
case 3:
rx_pwr_all = -24 + 2*(7-VGA_idx); /* VGA_idx = 7~0 */
break;
case 2:
if(cck_highpwr)
rx_pwr_all = -12 + 2*(5-VGA_idx); /* VGA_idx = 5~0 */
else
rx_pwr_all = -6+ 2*(5-VGA_idx);
break;
case 1:
rx_pwr_all = 8-2*VGA_idx;
break;
case 0:
rx_pwr_all = 14-2*VGA_idx;
break;
default:
break;
switch(LNA_idx) {
case 7:
if(VGA_idx <= 27)
rx_pwr_all = -100 + 2*(27-VGA_idx); /* VGA_idx = 27~2 */
else
rx_pwr_all = -100;
break;
case 6:
rx_pwr_all = -48 + 2*(2-VGA_idx); /* VGA_idx = 2~0 */
break;
case 5:
rx_pwr_all = -42 + 2*(7-VGA_idx); /* VGA_idx = 7~5 */
break;
case 4:
rx_pwr_all = -36 + 2*(7-VGA_idx); /* VGA_idx = 7~4 */
break;
case 3:
rx_pwr_all = -24 + 2*(7-VGA_idx); /* VGA_idx = 7~0 */
break;
case 2:
if(cck_highpwr)
rx_pwr_all = -12 + 2*(5-VGA_idx); /* VGA_idx = 5~0 */
else
rx_pwr_all = -6+ 2*(5-VGA_idx);
break;
case 1:
rx_pwr_all = 8-2*VGA_idx;
break;
case 0:
rx_pwr_all = 14-2*VGA_idx;
break;
default:
break;
}
rx_pwr_all += 6;
PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all);
@ -449,11 +441,8 @@ odm_RxPhyStatus92CSeries_Parsing(
{
pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++;
/* */
/* (1)Get RSSI for HT rate */
/* */
for(i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++)
for(i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++)
{
/* 2008/01/30 MH we will judge RF RX path now. */
if (pDM_Odm->RFPathRxEnable & BIT(i))
@ -601,15 +590,12 @@ odm_Process_RSSIForDM(
}
pEntry = pDM_Odm->pODM_StaInfo[pPktinfo->StationID];
if(!IS_STA_VALID(pEntry) ){
if(!IS_STA_VALID(pEntry))
return;
}
if((!pPktinfo->bPacketMatchBSSID) )
{
return;
}
isCCKrate = ((pPktinfo->Rate >= DESC92C_RATE1M ) && (pPktinfo->Rate <= DESC92C_RATE11M ))?true :false;
isCCKrate = (pPktinfo->Rate <= DESC92C_RATE11M) ? true : false;
if(pPktinfo->bPacketBeacon)
pDM_Odm->PhyDbgInfo.NumQryBeaconPkt++;
@ -877,25 +863,18 @@ ODM_ConfigBBWithHeaderFile(
IN ODM_BB_Config_Type ConfigType
)
{
if(pDM_Odm->SupportICType == ODM_RTL8188E)
{
if(ConfigType == CONFIG_BB_PHY_REG)
{
if(pDM_Odm->SupportICType == ODM_RTL8188E) {
if(ConfigType == CONFIG_BB_PHY_REG) {
if(IS_VENDOR_8188E_I_CUT_SERIES(pDM_Odm->Adapter))
READ_AND_CONFIG(8188E,_PHY_REG_1T_ICUT_);
else
READ_AND_CONFIG(8188E,_PHY_REG_1T_);
}
else if(ConfigType == CONFIG_BB_AGC_TAB)
{
} else if(ConfigType == CONFIG_BB_AGC_TAB) {
if(IS_VENDOR_8188E_I_CUT_SERIES(pDM_Odm->Adapter))
READ_AND_CONFIG(8188E,_AGC_TAB_1T_ICUT_);
else
READ_AND_CONFIG(8188E,_AGC_TAB_1T_);
}
else if(ConfigType == CONFIG_BB_PHY_REG_PG)
{
} else if(ConfigType == CONFIG_BB_PHY_REG_PG) {
READ_AND_CONFIG(8188E,_PHY_REG_PG_);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8188EPHY_REG_PGArray\n"));
}
@ -909,8 +888,7 @@ ODM_ConfigMACWithHeaderFile(
)
{
u8 result = HAL_STATUS_SUCCESS;
if (pDM_Odm->SupportICType == ODM_RTL8188E)
{
if (pDM_Odm->SupportICType == ODM_RTL8188E) {
if(IS_VENDOR_8188E_I_CUT_SERIES(pDM_Odm->Adapter))
READ_AND_CONFIG(8188E,_MAC_REG_ICUT_);
else

14
hal/odm_RTL8188E.c
View file

@ -140,18 +140,18 @@ odm_FastAntTrainingInit(
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
u32 AntCombination = 2;
struct adapter * Adapter = pDM_Odm->Adapter;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_FastAntTrainingInit() \n"));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_FastAntTrainingInit() \n"));
#if (MP_DRIVER == 1)
if (*(pDM_Odm->mp_mode) == 1)
{
if (*(pDM_Odm->mp_mode) == 1) {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("pDM_Odm->AntDivType: %d\n", pDM_Odm->AntDivType));
return;
return;
}
#endif
for(i=0; i<6; i++)
{
for(i=0; i<6; i++) {
pDM_FatTable->Bssid[i] = 0;
pDM_FatTable->antSumRSSI[i] = 0;
pDM_FatTable->antRSSIcnt[i] = 0;
@ -576,5 +576,5 @@ odm_DynamicPrimaryCCA(
u8 SecCHOffset;
u8 i;
return;
return;
}

8
hal/odm_RegConfig8188E.c
View file

@ -72,9 +72,9 @@ odm_ConfigRF_RadioA_8188E(
u32 content = 0x1000; /* RF_Content: radioa_txt */
u32 maskforPhySet= (u32)(content&0xE000);
odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet);
odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data));
}
void
@ -87,7 +87,7 @@ odm_ConfigRF_RadioB_8188E(
u32 content = 0x1001; /* RF_Content: radiob_txt */
u32 maskforPhySet= (u32)(content&0xE000);
odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet);
odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data));
@ -116,7 +116,7 @@ odm_ConfigBB_AGC_8188E(
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data));
}
void

17
hal/rtl8188e_hal_init.c
View file

@ -2762,16 +2762,15 @@ static u8 _LLTRead(struct adapter *padapter, u32 address)
void Read_LLT_Tab(struct adapter *padapter)
{
u32 addr,next_addr;
printk("############### %s ###################\n",__FUNCTION__);
for(addr=0;addr<176;addr++)
{
next_addr = _LLTRead(padapter,addr);
printk("%d->",next_addr);
if(((addr+1) %8) ==0)
printk("\n");
}
printk("\n##################################\n");
printk("############### %s ###################\n",__FUNCTION__);
for(addr=0;addr<176;addr++) {
next_addr = _LLTRead(padapter,addr);
printk("%d->",next_addr);
if(((addr+1) %8) ==0)
printk("\n");
}
printk("\n##################################\n");
}
s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy)

46
hal/rtl8188e_phycfg.c
View file

@ -1454,15 +1454,12 @@ phy_TxPwrIdxToDbm(
/* The mapping may be different by different NICs. Do not use this formula for what needs accurate result. */
/* By Bruce, 2008-01-29. */
/* */
switch(WirelessMode)
{
switch(WirelessMode) {
case WIRELESS_MODE_B:
Offset = -7;
break;
case WIRELESS_MODE_G:
case WIRELESS_MODE_N_24G:
Offset = -8;
default:
Offset = -8;
break;
@ -1577,47 +1574,6 @@ static void getTxPowerIndex88E(
/* 2. BW40 */
BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
}
else if(TxCount==RF_PATH_C)
{
/* 1. CCK */
cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index];
/* 2. OFDM */
ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+
pHalData->BW20_24G_Diff[RF_PATH_A][index]+
pHalData->BW20_24G_Diff[RF_PATH_B][index]+
pHalData->BW20_24G_Diff[TxCount][index];
/* 1. BW20 */
BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+
pHalData->BW20_24G_Diff[RF_PATH_A][index]+
pHalData->BW20_24G_Diff[RF_PATH_B][index]+
pHalData->BW20_24G_Diff[TxCount][index];
/* 2. BW40 */
BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
}
else if(TxCount==RF_PATH_D)
{
/* 1. CCK */
cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index];
/* 2. OFDM */
ofdmPowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+
pHalData->BW20_24G_Diff[RF_PATH_A][index]+
pHalData->BW20_24G_Diff[RF_PATH_B][index]+
pHalData->BW20_24G_Diff[RF_PATH_C][index]+
pHalData->BW20_24G_Diff[TxCount][index];
/* 1. BW20 */
BW20PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[RF_PATH_A][index]+
pHalData->BW20_24G_Diff[RF_PATH_A][index]+
pHalData->BW20_24G_Diff[RF_PATH_B][index]+
pHalData->BW20_24G_Diff[RF_PATH_C][index]+
pHalData->BW20_24G_Diff[TxCount][index];
/* 2. BW40 */
BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
}
else
{
}
}
}

22
hal/rtl8188eu_xmit.c
View file

@ -205,14 +205,13 @@ static void fill_txdesc_phy(struct pkt_attrib *pattrib, __le32 *pdw)
static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bagg_pkt)
{
int pull=0;
int pull=0;
uint qsel;
u8 data_rate,pwr_status,offset;
struct adapter *padapter = pxmitframe->padapter;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct pkt_attrib *pattrib = &pxmitframe->attrib;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
/* struct dm_priv *pdmpriv = &pHalData->dmpriv; */
struct tx_desc *ptxdesc = (struct tx_desc *)pmem;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
@ -249,17 +248,15 @@ if (padapter->registrypriv.mp_mode == 0)
if (bmcst) ptxdesc->txdw0 |= cpu_to_le32(BMC);
#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX
if (padapter->registrypriv.mp_mode == 0)
{
if(!bagg_pkt){
if((pull) && (pxmitframe->pkt_offset>0)) {
pxmitframe->pkt_offset = pxmitframe->pkt_offset -1;
if (padapter->registrypriv.mp_mode == 0)
{
if(!bagg_pkt){
if((pull) && (pxmitframe->pkt_offset>0)) {
pxmitframe->pkt_offset = pxmitframe->pkt_offset -1;
}
}
}
}
#endif
/* DBG_8192C("%s, pkt_offset=0x%02x\n",__FUNCTION__,pxmitframe->pkt_offset); */
/* pkt_offset, unit:8 bytes padding */
if (pxmitframe->pkt_offset > 0)
ptxdesc->txdw1 |= cpu_to_le32((pxmitframe->pkt_offset << 26) & 0x7c000000);
@ -538,10 +535,9 @@ static s32 rtw_dump_xframe(struct adapter *padapter, struct xmit_frame *pxmitfra
rtw_issue_addbareq_cmd(padapter, pxmitframe);
mem_addr = pxmitframe->buf_addr;
RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_dump_xframe()\n"));
RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_dump_xframe()\n"));
for (t = 0; t < pattrib->nr_frags; t++)
{
for (t = 0; t < pattrib->nr_frags; t++) {
if (inner_ret != _SUCCESS && ret == _SUCCESS)
ret = _FAIL;

130
hal/usb_halinit.c
View file

@ -1120,42 +1120,9 @@ HwSuspendModeEnable_88eu(
IN u8 Type
)
{
/* PRT_USB_DEVICE pDevice = GET_RT_USB_DEVICE(pAdapter); */
u16 reg = rtw_read16(pAdapter, REG_GPIO_MUXCFG);
/* if (!pDevice->RegUsbSS) */
{
return;
}
/* */
/* 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW */
/* to enter suspend mode automatically. Otherwise, it will shut down major power */
/* domain and 8051 will stop. When we try to enter selective suspend mode, we */
/* need to prevent HW to enter D2 mode aumotmatically. Another way, Host will */
/* issue a S10 signal to power domain. Then it will cleat SIC setting(from Yngli). */
/* We need to enable HW suspend mode when enter S3/S4 or disable. We need */
/* to disable HW suspend mode for IPS/radio_off. */
/* */
/* RT_TRACE(COMP_RF, DBG_LOUD, ("HwSuspendModeEnable92Cu = %d\n", Type)); */
if (Type == false)
{
reg |= BIT14;
/* RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg)); */
rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
reg |= BIT12;
/* RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg)); */
rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
}
else
{
reg &= (~BIT12);
rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
reg &= (~BIT14);
rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
}
return;
} /* HwSuspendModeEnable92Cu */
rt_rf_power_state RfOnOffDetect(IN struct adapter *pAdapter )
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
@ -1270,11 +1237,7 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter)
#define HAL_INIT_PROFILE_TAG(stage) do {} while(0)
#endif /* DBG_HAL_INIT_PROFILING */
;
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
if(pwrctrlpriv->bkeepfwalive)
{
@ -1296,7 +1259,7 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
}
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
status = InitPowerOn_rtl8188eu(Adapter);
if(status == _FAIL){
RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n"));
@ -1324,38 +1287,33 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_88E;
}
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
_InitQueueReservedPage(Adapter);
_InitQueuePriority(Adapter);
_InitPageBoundary(Adapter);
_InitTransferPageSize(Adapter);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
#if (MP_DRIVER == 1)
if (Adapter->registrypriv.mp_mode == 1)
{
_InitRxSetting(Adapter);
}
#endif /* MP_DRIVER == 1 */
{
status = rtl8188e_FirmwareDownload(Adapter);
if (status != _SUCCESS) {
DBG_871X("%s: Download Firmware failed!!\n", __FUNCTION__);
Adapter->bFWReady = false;
pHalData->fw_ractrl = false;
return status;
} else {
RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Download Firmware Success!!\n"));
Adapter->bFWReady = true;
pHalData->fw_ractrl = false;
}
status = rtl8188e_FirmwareDownload(Adapter);
if (status != _SUCCESS) {
DBG_871X("%s: Download Firmware failed!!\n", __FUNCTION__);
Adapter->bFWReady = false;
pHalData->fw_ractrl = false;
return status;
} else {
RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Download Firmware Success!!\n"));
Adapter->bFWReady = true;
pHalData->fw_ractrl = false;
}
rtl8188e_InitializeFirmwareVars(Adapter);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
#if (HAL_MAC_ENABLE == 1)
status = PHY_MACConfig8188E(Adapter);
if(status == _FAIL)
@ -1368,7 +1326,7 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
/* */
/* d. Initialize BB related configurations. */
/* */
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
#if (HAL_BB_ENABLE == 1)
status = PHY_BBConfig8188E(Adapter);
if(status == _FAIL)
@ -1379,7 +1337,7 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
#endif
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
#if (HAL_RF_ENABLE == 1)
status = PHY_RFConfig8188E(Adapter);
if(status == _FAIL)
@ -1389,7 +1347,7 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
}
#endif
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_EFUSE_PATCH);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_EFUSE_PATCH);
status = rtl8188e_iol_efuse_patch(Adapter);
if(status == _FAIL){
DBG_871X("%s rtl8188e_iol_efuse_patch failed \n",__FUNCTION__);
@ -1398,14 +1356,14 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_EFUSE_PATCH);
_InitTxBufferBoundary(Adapter, txpktbuf_bndy);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
status = InitLLTTable(Adapter, txpktbuf_bndy);
if(status == _FAIL){
RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n"));
goto exit;
}
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
/* Get Rx PHY status in order to report RSSI and others. */
_InitDriverInfoSize(Adapter, DRVINFO_SZ);
@ -1439,15 +1397,14 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
}
#if (RATE_ADAPTIVE_SUPPORT==1)
{/* Enable TX Report */
/* Enable Tx Report Timer */
value8 = rtw_read8(Adapter, REG_TX_RPT_CTRL);
rtw_write8(Adapter, REG_TX_RPT_CTRL, (value8|BIT1|BIT0));
/* Set MAX RPT MACID */
rtw_write8(Adapter, REG_TX_RPT_CTRL+1, 2);/* FOR sta mode ,0: bc/mc ,1:AP */
/* Tx RPT Timer. Unit: 32us */
rtw_write16(Adapter, REG_TX_RPT_TIME, 0xCdf0);
}
/* Enable TX Report */
/* Enable Tx Report Timer */
value8 = rtw_read8(Adapter, REG_TX_RPT_CTRL);
rtw_write8(Adapter, REG_TX_RPT_CTRL, (value8|BIT1|BIT0));
/* Set MAX RPT MACID */
rtw_write8(Adapter, REG_TX_RPT_CTRL+1, 2);/* FOR sta mode ,0: bc/mc ,1:AP */
/* Tx RPT Timer. Unit: 32us */
rtw_write16(Adapter, REG_TX_RPT_TIME, 0xCdf0);
#endif
rtw_write8(Adapter, REG_EARLY_MODE_CONTROL, 0);
@ -1467,14 +1424,14 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
pHalData->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (RF_RADIO_PATH_E)0, RF_CHNLBW, bRFRegOffsetMask);
pHalData->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (RF_RADIO_PATH_E)1, RF_CHNLBW, bRFRegOffsetMask);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
_BBTurnOnBlock(Adapter);
/* NicIFSetMacAddress(padapter, padapter->PermanentAddress); */
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
invalidate_cam_all(Adapter);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
/* 2010/12/17 MH We need to set TX power according to EFUSE content at first. */
PHY_SetTxPowerLevel8188E(Adapter, pHalData->CurrentChannel);
@ -1499,7 +1456,7 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
/* Nav limit , suggest by scott */
rtw_write8(Adapter, 0x652, 0x0);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
rtl8188e_InitHalDm(Adapter);
#if (MP_DRIVER == 1)
@ -1535,25 +1492,23 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
/* enable tx DMA to drop the redundate data of packet */
rtw_write16(Adapter,REG_TXDMA_OFFSET_CHK, (rtw_read16(Adapter,REG_TXDMA_OFFSET_CHK) | DROP_DATA_EN));
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
/* 2010/08/26 MH Merge from 8192CE. */
if(pwrctrlpriv->rf_pwrstate == rf_on)
{
if(pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized){
PHY_IQCalibrate_8188E(Adapter,true);
}
else
{
} else {
PHY_IQCalibrate_8188E(Adapter,false);
pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
}
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
ODM_TXPowerTrackingCheck(&pHalData->odmpriv );
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
PHY_LCCalibrate_8188E(Adapter);
}
}
@ -1566,7 +1521,7 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
rtw_write32(Adapter, REG_FWHW_TXQ_CTRL, rtw_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12));
exit:
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
DBG_871X("%s in %dms\n", __FUNCTION__, rtw_get_passing_time_ms(init_start_time));
@ -1582,10 +1537,6 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
);
}
#endif
;
return status;
}
@ -1598,11 +1549,10 @@ static void hal_poweroff_rtl8188eu(
IN struct adapter * Adapter
)
{
/* PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); */
u8 val8;
u16 val16;
u32 val32;
u8 bMacPwrCtrlOn=false;
u8 bMacPwrCtrlOn=false;
rtw_hal_get_hwreg(Adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
if(bMacPwrCtrlOn == false)

90
hal/usb_ops_linux.c
View file

@ -228,7 +228,7 @@ static int usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val)
data = val;
ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype);
ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype);
return ret;
}
@ -295,7 +295,7 @@ static int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata
wvalue = (u16)(addr&0x0000ffff);
len = length;
memcpy(buf, pdata, len );
memcpy(buf, pdata, len );
return usbctrl_vendorreq(pintfhdl, request, wvalue, index, buf, len, requesttype);
}
@ -779,9 +779,6 @@ static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem)
struct recv_priv *precvpriv = &adapter->recvpriv;
struct usb_device *pusbd = pdvobj->pusbdev;
;
if (adapter->bDriverStopped || adapter->bSurpriseRemoved ||dvobj_to_pwrctl(pdvobj)->pnp_bstop_trx)
{
RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved ||pwrctl->pnp_bstop_trx)!!!\n"));
@ -793,61 +790,56 @@ static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem)
precvbuf->reuse = true;
}
if (precvbuf != NULL) {
rtl8188eu_init_recvbuf(adapter, precvbuf);
rtl8188eu_init_recvbuf(adapter, precvbuf);
/* re-assign for linux based on skb */
if ((precvbuf->reuse == false) || (precvbuf->pskb == NULL)) {
precvbuf->pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
/* re-assign for linux based on skb */
if ((precvbuf->reuse == false) || (precvbuf->pskb == NULL)) {
precvbuf->pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
if (precvbuf->pskb == NULL) {
RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("init_recvbuf(): alloc_skb fail!\n"));
DBG_8192C("#### usb_read_port() alloc_skb fail!#####\n");
return _FAIL;
}
if (precvbuf->pskb == NULL) {
RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("init_recvbuf(): alloc_skb fail!\n"));
DBG_8192C("#### usb_read_port() alloc_skb fail!#####\n");
return _FAIL;
}
tmpaddr = (SIZE_PTR)precvbuf->pskb->data;
alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1);
skb_reserve(precvbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment));
tmpaddr = (SIZE_PTR)precvbuf->pskb->data;
alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1);
skb_reserve(precvbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment));
precvbuf->phead = precvbuf->pskb->head;
precvbuf->pdata = precvbuf->pskb->data;
precvbuf->ptail = skb_tail_pointer(precvbuf->pskb);
precvbuf->pend = skb_end_pointer(precvbuf->pskb);
precvbuf->pbuf = precvbuf->pskb->data;
} else/* reuse skb */
{
precvbuf->phead = precvbuf->pskb->head;
precvbuf->pdata = precvbuf->pskb->data;
precvbuf->ptail = skb_tail_pointer(precvbuf->pskb);
precvbuf->pend = skb_end_pointer(precvbuf->pskb);
precvbuf->phead = precvbuf->pskb->head;
precvbuf->pdata = precvbuf->pskb->data;
precvbuf->ptail = skb_tail_pointer(precvbuf->pskb);
precvbuf->pend = skb_end_pointer(precvbuf->pskb);
precvbuf->pbuf = precvbuf->pskb->data;
} else/* reuse skb */
{
precvbuf->phead = precvbuf->pskb->head;
precvbuf->pdata = precvbuf->pskb->data;
precvbuf->ptail = skb_tail_pointer(precvbuf->pskb);
precvbuf->pend = skb_end_pointer(precvbuf->pskb);
precvbuf->pbuf = precvbuf->pskb->data;
precvbuf->reuse = false;
}
precvbuf->reuse = false;
}
precvpriv->rx_pending_cnt++;
precvpriv->rx_pending_cnt++;
purb = precvbuf->purb;
purb = precvbuf->purb;
/* translate DMA FIFO addr to pipehandle */
pipe = ffaddr2pipehdl(pdvobj, addr);
/* translate DMA FIFO addr to pipehandle */
pipe = ffaddr2pipehdl(pdvobj, addr);
usb_fill_bulk_urb(purb, pusbd, pipe, precvbuf->pbuf,
MAX_RECVBUF_SZ, usb_read_port_complete,
precvbuf);/* context is precvbuf */
usb_fill_bulk_urb(purb, pusbd, pipe, precvbuf->pbuf,
MAX_RECVBUF_SZ, usb_read_port_complete,
precvbuf);/* context is precvbuf */
err = usb_submit_urb(purb, GFP_ATOMIC);
if ((err) && (err != (-EPERM))) {
RT_TRACE(_module_hci_ops_os_c_,_drv_err_,
("cannot submit rx in-token(err=0x%.8x), URB_STATUS =0x%.8x",
err, purb->status));
DBG_8192C("cannot submit rx in-token(err = 0x%08x),urb_status = %d\n",
err, purb->status);
ret = _FAIL;
}
} else {
RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:precvbuf ==NULL\n"));
err = usb_submit_urb(purb, GFP_ATOMIC);
if ((err) && (err != (-EPERM))) {
RT_TRACE(_module_hci_ops_os_c_,_drv_err_,
("cannot submit rx in-token(err=0x%.8x), URB_STATUS =0x%.8x",
err, purb->status));
DBG_8192C("cannot submit rx in-token(err = 0x%08x),urb_status = %d\n",
err, purb->status);
ret = _FAIL;
}
return ret;