mirror of
https://github.com/lwfinger/rtl8188eu.git
synced 2025-05-08 14:33:05 +00:00
rtl8188eu: Change "for(" to "for ("
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
parent
c818db1282
commit
9ee6ae40c3
40 changed files with 278 additions and 278 deletions
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@ -112,7 +112,7 @@ odm_SetTxRPTTiming_8188E(
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{
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u8 idx = 0;
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for(idx=0; idx<5; idx++)
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for (idx=0; idx<5; idx++)
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if (DynamicTxRPTTiming[idx] == pRaInfo->RptTime)
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break;
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@ -551,7 +551,7 @@ odm_PTDecision_8188E(
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stage_BUF=pRaInfo->PTStage;
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numsc = 0;
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num_total= pRaInfo->TOTAL* PT_PENALTY[5];
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for(j=0;j<=4;j++)
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for (j=0;j<=4;j++)
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{
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numsc += pRaInfo->RTY[j] * PT_PENALTY[j];
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if (numsc>num_total)
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@ -689,7 +689,7 @@ ODM_RAInfo_Init_all(
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>\n"));
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pDM_Odm->CurrminRptTime = 0;
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for(MacID=0; MacID<ODM_ASSOCIATE_ENTRY_NUM; MacID++)
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for (MacID=0; MacID<ODM_ASSOCIATE_ENTRY_NUM; MacID++)
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ODM_RAInfo_Init(pDM_Odm,MacID);
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return 0;
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@ -37,7 +37,7 @@ ODM_ResetIQKResult(
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("PHY_ResetIQKResult:: settings regs %d default regs %d\n", (u32)(sizeof(pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting)/sizeof(IQK_MATRIX_REGS_SETTING)), IQK_Matrix_Settings_NUM));
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/* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */
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for(i = 0; i < IQK_Matrix_Settings_NUM; i++)
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for (i = 0; i < IQK_Matrix_Settings_NUM; i++)
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{
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{
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pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][0] =
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@ -65,7 +65,7 @@ u8 ODM_GetRightChnlPlaceforIQK(u8 chnl)
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if (chnl > 14)
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{
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for(place = 14; place<sizeof(channel_all); place++)
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for (place = 14; place<sizeof(channel_all); place++)
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{
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if (channel_all[place] == chnl)
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{
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@ -29,7 +29,7 @@
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#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \
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do {\
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for(_offset = 0; _offset < _size; _offset++)\
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for (_offset = 0; _offset < _size; _offset++)\
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{\
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if (_deltaThermal < thermalThreshold[_direction][_offset])\
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{\
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@ -404,7 +404,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
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if (pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == AVG_THERMAL_NUM_88E)
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pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0;
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for(i = 0; i < AVG_THERMAL_NUM_88E; i++)
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for (i = 0; i < AVG_THERMAL_NUM_88E; i++)
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{
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if (pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i])
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{
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@ -459,7 +459,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
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else
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pDM_Odm->RFCalibrateInfo.PowerIndexOffset = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast;
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for(i = 0; i < rf; i++)
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for (i = 0; i < rf; i++)
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pDM_Odm->RFCalibrateInfo.OFDM_index[i] = pDM_Odm->BbSwingIdxOfdmBase + pDM_Odm->RFCalibrateInfo.PowerIndexOffset;
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pDM_Odm->RFCalibrateInfo.CCK_index = pDM_Odm->BbSwingIdxCckBase + pDM_Odm->RFCalibrateInfo.PowerIndexOffset;
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@ -472,7 +472,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
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/* 4 7.1 Handle boundary conditions of index. */
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for(i = 0; i < rf; i++) {
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for (i = 0; i < rf; i++) {
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if (pDM_Odm->RFCalibrateInfo.OFDM_index[i] > OFDM_TABLE_SIZE_92D-1)
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{
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pDM_Odm->RFCalibrateInfo.OFDM_index[i] = OFDM_TABLE_SIZE_92D-1;
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@ -942,7 +942,7 @@ _PHY_SaveADDARegisters(
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if (ODM_CheckPowerStatus(pAdapter) == false)
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return;
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n"));
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for( i = 0 ; i < RegisterNum ; i++){
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for ( i = 0 ; i < RegisterNum ; i++){
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ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord);
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}
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}
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@ -960,7 +960,7 @@ _PHY_SaveMACRegisters(
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PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n"));
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for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){
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for ( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){
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MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]);
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}
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MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]);
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@ -981,7 +981,7 @@ _PHY_ReloadADDARegisters(
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PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n"));
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for(i = 0 ; i < RegiesterNum; i++)
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for (i = 0 ; i < RegiesterNum; i++)
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{
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ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]);
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}
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@ -999,7 +999,7 @@ _PHY_ReloadMACRegisters(
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PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n"));
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for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){
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for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){
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ODM_Write1Byte(pDM_Odm, MACReg[i], (u8)MACBackup[i]);
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}
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ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]);
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@ -1030,7 +1030,7 @@ _PHY_PathADDAOn(
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ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn);
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}
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for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){
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for ( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){
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ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn);
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}
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@ -1051,7 +1051,7 @@ _PHY_MACSettingCalibration(
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ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F);
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for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){
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for (i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){
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ODM_Write1Byte(pDM_Odm, MACReg[i], (u8)(MACBackup[i]&(~BIT3)));
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}
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ODM_Write1Byte(pDM_Odm, MACReg[i], (u8)(MACBackup[i]&(~BIT5)));
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@ -1123,7 +1123,7 @@ phy_SimularityCompare_8188E(
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SimularityBitMap = 0;
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for( i = 0; i < bound; i++ )
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for ( i = 0; i < bound; i++ )
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{
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/* diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); */
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if ((i==1) || (i==3) || (i==5) || (i==7))
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@ -1168,11 +1168,11 @@ phy_SimularityCompare_8188E(
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if ( SimularityBitMap == 0)
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{
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for( i = 0; i < (bound/4); i++ )
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for ( i = 0; i < (bound/4); i++ )
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{
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if (final_candidate[i] != 0xFF)
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{
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for( j = i*4; j < (i+1)*4-2; j++)
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for ( j = i*4; j < (i+1)*4-2; j++)
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result[3][j] = result[final_candidate[i]][j];
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bResult = false;
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}
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@ -1184,25 +1184,25 @@ phy_SimularityCompare_8188E(
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if (!(SimularityBitMap & 0x03)) /* path A TX OK */
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{
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for(i = 0; i < 2; i++)
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for (i = 0; i < 2; i++)
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result[3][i] = result[c1][i];
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}
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if (!(SimularityBitMap & 0x0c)) /* path A RX OK */
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{
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for(i = 2; i < 4; i++)
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for (i = 2; i < 4; i++)
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result[3][i] = result[c1][i];
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}
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if (!(SimularityBitMap & 0x30)) /* path B TX OK */
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{
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for(i = 4; i < 6; i++)
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for (i = 4; i < 6; i++)
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result[3][i] = result[c1][i];
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}
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if (!(SimularityBitMap & 0xc0)) /* path B RX OK */
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{
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for(i = 6; i < 8; i++)
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for (i = 6; i < 8; i++)
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result[3][i] = result[c1][i];
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}
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@ -1314,7 +1314,7 @@ else
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ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
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ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800);
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for(i = 0 ; i < retryCount ; i++){
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for (i = 0 ; i < retryCount ; i++){
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PathAOK = phy_PathA_IQK_8188E(pAdapter, is2T);
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if (PathAOK == 0x01){
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n"));
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@ -1324,7 +1324,7 @@ else
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}
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}
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for(i = 0 ; i < retryCount ; i++){
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for (i = 0 ; i < retryCount ; i++){
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PathAOK = phy_PathA_RxIQK(pAdapter, is2T);
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if (PathAOK == 0x03){
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n"));
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@ -1346,7 +1346,7 @@ else
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/* Turn Path B ADDA on */
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_PHY_PathADDAOn(pAdapter, ADDA_REG, false, is2T);
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for(i = 0 ; i < retryCount ; i++){
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for (i = 0 ; i < retryCount ; i++){
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PathBOK = phy_PathB_IQK_8188E(pAdapter);
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if (PathBOK == 0x03){
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK Success!!\n"));
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@ -1598,14 +1598,14 @@ if ( *(pDM_Odm->mp_mode) == 1)
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if (*(pDM_Odm->mp_mode) != 1)
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return;
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/* settings adjust for normal chip */
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for(index = 0; index < PATH_NUM; index ++) {
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for (index = 0; index < PATH_NUM; index ++) {
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APK_offset[index] = APK_normal_offset[index];
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APK_value[index] = APK_normal_value[index];
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AFE_on_off[index] = 0x6fdb25a4;
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}
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for(index = 0; index < APK_BB_REG_NUM; index ++) {
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for(path = 0; path < pathbound; path++) {
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for (index = 0; index < APK_BB_REG_NUM; index ++) {
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for (path = 0; path < pathbound; path++) {
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APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index];
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APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index];
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}
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@ -1615,7 +1615,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
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apkbound = 6;
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/* save BB default value */
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for(index = 0; index < APK_BB_REG_NUM ; index++) {
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for (index = 0; index < APK_BB_REG_NUM ; index++) {
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if (index == 0) /* skip */
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continue;
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BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord);
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@ -1627,7 +1627,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
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/* save AFE default value */
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_PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
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for(path = 0; path < pathbound; path++)
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for (path = 0; path < pathbound; path++)
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{
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@ -1637,7 +1637,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
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/* load APK setting */
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/* path-A */
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offset = rPdp_AntA;
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for(index = 0; index < 11; index ++)
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for (index = 0; index < 11; index ++)
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{
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ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
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@ -1648,7 +1648,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
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ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
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offset = rConfig_AntA;
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for(; index < 13; index ++)
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for (; index < 13; index ++)
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{
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ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
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@ -1661,7 +1661,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
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/* path A */
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offset = rPdp_AntA;
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for(index = 0; index < 16; index++)
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for (index = 0; index < 16; index++)
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{
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ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
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@ -1676,7 +1676,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
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/* load APK setting */
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/* path-B */
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offset = rPdp_AntB;
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for(index = 0; index < 10; index ++)
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for (index = 0; index < 10; index ++)
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{
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ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
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@ -1688,7 +1688,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
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offset = rConfig_AntA;
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index = 11;
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for(; index < 13; index ++) /* offset 0xb68, 0xb6c */
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for (; index < 13; index ++) /* offset 0xb68, 0xb6c */
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{
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ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
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@ -1701,7 +1701,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
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/* path B */
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offset = 0xb60;
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for(index = 0; index < 16; index++)
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for (index = 0; index < 16; index++)
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{
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ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
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@ -1715,14 +1715,14 @@ if ( *(pDM_Odm->mp_mode) == 1)
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regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord);
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/* Path A AFE all on, path B AFE All off or vise versa */
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for(index = 0; index < IQK_ADDA_REG_NUM ; index++)
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for (index = 0; index < IQK_ADDA_REG_NUM ; index++)
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ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord)));
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/* BB to AP mode */
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if (path == 0)
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{
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for(index = 0; index < APK_BB_REG_NUM ; index++)
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for (index = 0; index < APK_BB_REG_NUM ; index++)
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{
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if (index == 0) /* skip */
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|
|
@ -1768,7 +1768,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
|
|||
delta_offset = 12;
|
||||
|
||||
/* AP calibration */
|
||||
for(index = 0; index < APK_BB_REG_NUM; index++)
|
||||
for (index = 0; index < APK_BB_REG_NUM; index++)
|
||||
{
|
||||
if (index != 1) /* only DO PA11+PAD01001, AP RF setting */
|
||||
continue;
|
||||
|
|
@ -1843,7 +1843,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
|
|||
_PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup);
|
||||
|
||||
/* reload BB default value */
|
||||
for(index = 0; index < APK_BB_REG_NUM ; index++)
|
||||
for (index = 0; index < APK_BB_REG_NUM ; index++)
|
||||
{
|
||||
|
||||
if (index == 0) /* skip */
|
||||
|
|
@ -1855,7 +1855,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
|
|||
_PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
|
||||
|
||||
/* reload RF path default value */
|
||||
for(path = 0; path < pathbound; path++)
|
||||
for (path = 0; path < pathbound; path++)
|
||||
{
|
||||
ODM_SetRFReg(pDM_Odm, path, 0xd, bMaskDWord, regD[path]);
|
||||
if (path == RF_PATH_B)
|
||||
|
|
@ -1873,7 +1873,7 @@ if ( *(pDM_Odm->mp_mode) == 1)
|
|||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n"));
|
||||
|
||||
|
||||
for(path = 0; path < pathbound; path++)
|
||||
for (path = 0; path < pathbound; path++)
|
||||
{
|
||||
ODM_SetRFReg(pDM_Odm, path, 0x3, bMaskDWord,
|
||||
((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1]));
|
||||
|
|
@ -1969,7 +1969,7 @@ if (*(pDM_Odm->mp_mode) == 1)
|
|||
}
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n"));
|
||||
|
||||
for(i = 0; i < 8; i++) {
|
||||
for (i = 0; i < 8; i++) {
|
||||
result[0][i] = 0;
|
||||
result[1][i] = 0;
|
||||
result[2][i] = 0;
|
||||
|
|
@ -2018,7 +2018,7 @@ if (*(pDM_Odm->mp_mode) == 1)
|
|||
else
|
||||
{
|
||||
/*
|
||||
for(i = 0; i < 8; i++)
|
||||
for (i = 0; i < 8; i++)
|
||||
RegTmp += result[3][i];
|
||||
|
||||
if (RegTmp != 0)
|
||||
|
|
@ -2079,7 +2079,7 @@ if (*(pDM_Odm->mp_mode) == 1)
|
|||
/* by sherry 20120321 */
|
||||
if (final_candidate < 4)
|
||||
{
|
||||
for(i = 0; i < IQK_Matrix_REG_NUM; i++)
|
||||
for (i = 0; i < IQK_Matrix_REG_NUM; i++)
|
||||
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i];
|
||||
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = true;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -146,7 +146,7 @@ void HalSetBrateCfg(
|
|||
{
|
||||
u8 i, is_brate, brate;
|
||||
|
||||
for(i=0;i<NDIS_802_11_LENGTH_RATES_EX;i++)
|
||||
for (i=0;i<NDIS_802_11_LENGTH_RATES_EX;i++)
|
||||
{
|
||||
is_brate = mBratesOS[i] & IEEE80211_BASIC_RATE_MASK;
|
||||
brate = mBratesOS[i] & 0x7f;
|
||||
|
|
|
|||
18
hal/odm.c
18
hal/odm.c
|
|
@ -2412,7 +2412,7 @@ odm_RefreshRateAdaptiveMaskCE(
|
|||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n"));
|
||||
return;
|
||||
}
|
||||
for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++){
|
||||
for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++){
|
||||
PSTA_INFO_T pstat = pDM_Odm->pODM_StaInfo[i];
|
||||
if (IS_STA_VALID(pstat) ) {
|
||||
if (IS_MCAST( pstat->hwaddr)) /* if (psta->mac_id ==1) */
|
||||
|
|
@ -2525,7 +2525,7 @@ odm_DynamicTxPowerSavePowerIndex(
|
|||
struct adapter *Adapter = pDM_Odm->Adapter;
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
struct dm_priv *pdmpriv = &pHalData->dmpriv;
|
||||
for(index = 0; index< 6; index++)
|
||||
for (index = 0; index< 6; index++)
|
||||
pdmpriv->PowerIndex_backup[index] = rtw_read8(Adapter, Power_Index_REG[index]);
|
||||
}
|
||||
|
||||
|
|
@ -2540,7 +2540,7 @@ odm_DynamicTxPowerRestorePowerIndex(
|
|||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
u32 Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
|
||||
struct dm_priv *pdmpriv = &pHalData->dmpriv;
|
||||
for(index = 0; index< 6; index++)
|
||||
for (index = 0; index< 6; index++)
|
||||
rtw_write8(Adapter, Power_Index_REG[index], pdmpriv->PowerIndex_backup[index]);
|
||||
}
|
||||
|
||||
|
|
@ -2553,7 +2553,7 @@ odm_DynamicTxPowerWritePowerIndex(
|
|||
u8 index;
|
||||
u32 Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
|
||||
|
||||
for(index = 0; index< 6; index++)
|
||||
for (index = 0; index< 6; index++)
|
||||
/* PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], Value); */
|
||||
ODM_Write1Byte(pDM_Odm, Power_Index_REG[index], Value);
|
||||
|
||||
|
|
@ -2761,7 +2761,7 @@ odm_RSSIMonitorCheckCE(
|
|||
{
|
||||
struct sta_info *psta;
|
||||
|
||||
for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++) {
|
||||
for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++) {
|
||||
if (IS_STA_VALID(psta = pDM_Odm->pODM_StaInfo[i])) {
|
||||
if (IS_MCAST( psta->hwaddr)) /* if (psta->mac_id ==1) */
|
||||
continue;
|
||||
|
|
@ -2778,7 +2778,7 @@ odm_RSSIMonitorCheckCE(
|
|||
}
|
||||
}
|
||||
|
||||
for(i=0; i< sta_cnt; i++)
|
||||
for (i=0; i< sta_cnt; i++)
|
||||
{
|
||||
if (PWDB_rssi[i] != (0)){
|
||||
if (pHalData->fw_ractrl == true)/* Report every sta's RSSI to FW */
|
||||
|
|
@ -3059,7 +3059,7 @@ odm_InitHybridAntDiv_88C_92D(
|
|||
|
||||
pDM_SWAT_Table->CurAntenna=0; /* choose left antenna as default antenna */
|
||||
pDM_SWAT_Table->PreAntenna=0;
|
||||
for(i=0; i<ASSOCIATE_ENTRY_NUM ; i++)
|
||||
for (i=0; i<ASSOCIATE_ENTRY_NUM ; i++)
|
||||
{
|
||||
pDM_SWAT_Table->CCK_Ant1_Cnt[i] = 0;
|
||||
pDM_SWAT_Table->CCK_Ant2_Cnt[i] = 0;
|
||||
|
|
@ -3566,7 +3566,7 @@ odm_PHY_SaveAFERegisters(
|
|||
u32 i;
|
||||
|
||||
/* RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n")); */
|
||||
for( i = 0 ; i < RegisterNum ; i++){
|
||||
for ( i = 0 ; i < RegisterNum ; i++){
|
||||
AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord);
|
||||
}
|
||||
}
|
||||
|
|
@ -3582,7 +3582,7 @@ odm_PHY_ReloadAFERegisters(
|
|||
u32 i;
|
||||
|
||||
/* RTPRINT(FINIT, INIT_IQK, ("Reload ADDA power saving parameters !\n")); */
|
||||
for(i = 0 ; i < RegiesterNum; i++)
|
||||
for (i = 0 ; i < RegiesterNum; i++)
|
||||
{
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, AFEReg[i], bMaskDWord, AFEBackup[i]);
|
||||
|
|
|
|||
|
|
@ -442,7 +442,7 @@ odm_RxPhyStatus92CSeries_Parsing(
|
|||
pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++;
|
||||
|
||||
/* (1)Get RSSI for HT rate */
|
||||
for(i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++)
|
||||
for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++)
|
||||
{
|
||||
/* 2008/01/30 MH we will judge RF RX path now. */
|
||||
if (pDM_Odm->RFPathRxEnable & BIT(i))
|
||||
|
|
@ -513,7 +513,7 @@ odm_RxPhyStatus92CSeries_Parsing(
|
|||
else
|
||||
Max_spatial_stream = 1; /* only spatial stream 1 makes sense */
|
||||
|
||||
for(i=0; i<Max_spatial_stream; i++) {
|
||||
for (i=0; i<Max_spatial_stream; i++) {
|
||||
/* Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment */
|
||||
/* fill most significant bit to "zero" when doing shifting operation which may change a negative */
|
||||
/* value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. */
|
||||
|
|
@ -731,7 +731,7 @@ odm_Process_RSSIForDM(
|
|||
else
|
||||
pEntry->rssi_stat.ValidBit++;
|
||||
|
||||
for(i=0; i<pEntry->rssi_stat.ValidBit; i++)
|
||||
for (i=0; i<pEntry->rssi_stat.ValidBit; i++)
|
||||
OFDM_pkt += (u8)(pEntry->rssi_stat.PacketMap>>i)&BIT0;
|
||||
|
||||
if (pEntry->rssi_stat.ValidBit == 64)
|
||||
|
|
|
|||
|
|
@ -151,7 +151,7 @@ odm_FastAntTrainingInit(
|
|||
}
|
||||
#endif
|
||||
|
||||
for(i=0; i<6; i++) {
|
||||
for (i=0; i<6; i++) {
|
||||
pDM_FatTable->Bssid[i] = 0;
|
||||
pDM_FatTable->antSumRSSI[i] = 0;
|
||||
pDM_FatTable->antRSSIcnt[i] = 0;
|
||||
|
|
|
|||
|
|
@ -146,7 +146,7 @@
|
|||
DbgPrint("[ODM] "); \
|
||||
DbgPrint(title_str); \
|
||||
DbgPrint(" "); \
|
||||
for( __i=0; __i<6; __i++ ) \
|
||||
for ( __i=0; __i<6; __i++ ) \
|
||||
DbgPrint("%02X%s", __ptr[__i], (__i==5)?"":"-"); \
|
||||
DbgPrint("\n"); \
|
||||
}
|
||||
|
|
|
|||
|
|
@ -128,7 +128,7 @@ static s32 FillH2CCmd_88E(struct adapter *padapter, u8 ElementID, u32 CmdLen, u8
|
|||
/* Write Ext command */
|
||||
msgbox_ex_addr = REG_HMEBOX_EXT_0 + (h2c_box_num *RTL88E_EX_MESSAGE_BOX_SIZE);
|
||||
#ifdef CONFIG_H2C_EF
|
||||
for(cmd_idx=0;cmd_idx<ext_cmd_len;cmd_idx++ ){
|
||||
for (cmd_idx=0;cmd_idx<ext_cmd_len;cmd_idx++ ){
|
||||
rtw_write8(padapter,msgbox_ex_addr+cmd_idx,*((u8*)(&h2c_cmd_ex)+cmd_idx));
|
||||
}
|
||||
#else
|
||||
|
|
@ -139,7 +139,7 @@ static s32 FillH2CCmd_88E(struct adapter *padapter, u8 ElementID, u32 CmdLen, u8
|
|||
/* Write command */
|
||||
msgbox_addr =REG_HMEBOX_0 + (h2c_box_num *RTL88E_MESSAGE_BOX_SIZE);
|
||||
#ifdef CONFIG_H2C_EF
|
||||
for(cmd_idx=0;cmd_idx<RTL88E_MESSAGE_BOX_SIZE;cmd_idx++ ){
|
||||
for (cmd_idx=0;cmd_idx<RTL88E_MESSAGE_BOX_SIZE;cmd_idx++ ){
|
||||
rtw_write8(padapter,msgbox_addr+cmd_idx,*((u8*)(&h2c_cmd)+cmd_idx));
|
||||
}
|
||||
#else
|
||||
|
|
@ -870,7 +870,7 @@ void rtl8188e_set_p2p_ps_offload_cmd(struct adapter* padapter, u8 p2p_ps_state)
|
|||
}
|
||||
|
||||
/* hw only support 2 set of NoA */
|
||||
for( i=0 ; i<pwdinfo->noa_num ; i++)
|
||||
for ( i=0 ; i<pwdinfo->noa_num ; i++)
|
||||
{
|
||||
/* To control the register setting for which NOA */
|
||||
rtw_write8(padapter, REG_NOA_DESC_SEL, (i << 4));
|
||||
|
|
|
|||
|
|
@ -235,7 +235,7 @@ static void Update_ODM_ComInfo_88E(struct adapter *Adapter)
|
|||
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_POWER_SAVING,&(pwrctrlpriv->bpower_saving));
|
||||
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);
|
||||
|
||||
for(i=0; i< NUM_STA; i++)
|
||||
for (i=0; i< NUM_STA; i++)
|
||||
{
|
||||
/* pDM_Odm->pODM_StaInfo[i] = NULL; */
|
||||
ODM_CmnInfoPtrArrayHook(pDM_Odm, ODM_CMNINFO_STA_STATUS,i,NULL);
|
||||
|
|
|
|||
|
|
@ -202,7 +202,7 @@ efuse_phymap_to_logical(u8 * phymap, u16 _offset, u16 _size_byte, u8 *pbuf)
|
|||
/* Get word enable value from PG header */
|
||||
/* RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Offset-%d Worden=%x\n", offset, wren)); */
|
||||
|
||||
for(i=0; i<EFUSE_MAX_WORD_UNIT; i++)
|
||||
for (i=0; i<EFUSE_MAX_WORD_UNIT; i++)
|
||||
{
|
||||
/* Check word enable condition in the section */
|
||||
if (!(wren & 0x01))
|
||||
|
|
@ -249,9 +249,9 @@ efuse_phymap_to_logical(u8 * phymap, u16 _offset, u16 _size_byte, u8 *pbuf)
|
|||
/* */
|
||||
/* 3. Collect 16 sections and 4 word unit into Efuse map. */
|
||||
/* */
|
||||
for(i=0; i<EFUSE_MAX_SECTION_88E; i++)
|
||||
for (i=0; i<EFUSE_MAX_SECTION_88E; i++)
|
||||
{
|
||||
for(j=0; j<EFUSE_MAX_WORD_UNIT; j++)
|
||||
for (j=0; j<EFUSE_MAX_WORD_UNIT; j++)
|
||||
{
|
||||
efuseTbl[(i*8)+(j*2)]=(eFuseWord[i][j] & 0xff);
|
||||
efuseTbl[(i*8)+((j*2)+1)]=((eFuseWord[i][j] >> 8) & 0xff);
|
||||
|
|
@ -262,7 +262,7 @@ efuse_phymap_to_logical(u8 * phymap, u16 _offset, u16 _size_byte, u8 *pbuf)
|
|||
/* */
|
||||
/* 4. Copy from Efuse map to output pointer memory!!! */
|
||||
/* */
|
||||
for(i=0; i<_size_byte; i++)
|
||||
for (i=0; i<_size_byte; i++)
|
||||
{
|
||||
pbuf[i] = efuseTbl[_offset+i];
|
||||
}
|
||||
|
|
@ -458,7 +458,7 @@ static int rtl8188e_IOL_exec_cmds_sync(struct adapter *adapter, struct xmit_fram
|
|||
|
||||
t1= rtw_get_current_time();
|
||||
iol_mode_enable(adapter, 1);
|
||||
for(i=0;i<bndy_cnt;i++){
|
||||
for (i=0;i<bndy_cnt;i++){
|
||||
u8 page_no = 0;
|
||||
page_no = i*2 ;
|
||||
/* printk(" i = %d, page_no = %d\n",i,page_no); */
|
||||
|
|
@ -487,7 +487,7 @@ void rtw_IOL_cmd_tx_pkt_buf_dump(struct adapter *Adapter,int data_len)
|
|||
|
||||
rtw_write8(Adapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT);
|
||||
if (pbuf){
|
||||
for(addr=0;addr< data_cnts;addr++){
|
||||
for (addr=0;addr< data_cnts;addr++){
|
||||
/* printk("==> addr:0x%02x\n",addr); */
|
||||
rtw_write32(Adapter,0x140,addr);
|
||||
rtw_usleep_os(2);
|
||||
|
|
@ -613,7 +613,7 @@ _BlockWrite(
|
|||
("_BlockWrite: [P3] buffSize_p3(%d) blockSize_p3(%d) blockCount_p3(%d)\n",
|
||||
(buffSize-offset), blockSize_p3, blockCount_p3));
|
||||
|
||||
for(i = 0 ; i < blockCount_p3 ; i++){
|
||||
for (i = 0 ; i < blockCount_p3 ; i++){
|
||||
ret =rtw_write8(padapter, (FW_8188E_START_ADDRESS + offset + i), *(bufferPtr + offset + i));
|
||||
|
||||
if (ret == _FAIL)
|
||||
|
|
@ -1162,7 +1162,7 @@ Hal_EfuseReadEFuse88E(
|
|||
/* Get word enable value from PG header */
|
||||
/* RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Offset-%d Worden=%x\n", offset, wren)); */
|
||||
|
||||
for(i=0; i<EFUSE_MAX_WORD_UNIT; i++)
|
||||
for (i=0; i<EFUSE_MAX_WORD_UNIT; i++)
|
||||
{
|
||||
/* Check word enable condition in the section */
|
||||
if (!(wren & 0x01))
|
||||
|
|
@ -1209,9 +1209,9 @@ Hal_EfuseReadEFuse88E(
|
|||
/* */
|
||||
/* 3. Collect 16 sections and 4 word unit into Efuse map. */
|
||||
/* */
|
||||
for(i=0; i<EFUSE_MAX_SECTION_88E; i++)
|
||||
for (i=0; i<EFUSE_MAX_SECTION_88E; i++)
|
||||
{
|
||||
for(j=0; j<EFUSE_MAX_WORD_UNIT; j++)
|
||||
for (j=0; j<EFUSE_MAX_WORD_UNIT; j++)
|
||||
{
|
||||
efuseTbl[(i*8)+(j*2)]=(eFuseWord[i][j] & 0xff);
|
||||
efuseTbl[(i*8)+((j*2)+1)]=((eFuseWord[i][j] >> 8) & 0xff);
|
||||
|
|
@ -1222,7 +1222,7 @@ Hal_EfuseReadEFuse88E(
|
|||
/* */
|
||||
/* 4. Copy from Efuse map to output pointer memory!!! */
|
||||
/* */
|
||||
for(i=0; i<_size_byte; i++)
|
||||
for (i=0; i<_size_byte; i++)
|
||||
{
|
||||
pbuf[i] = efuseTbl[_offset+i];
|
||||
}
|
||||
|
|
@ -1336,7 +1336,7 @@ exit:
|
|||
{
|
||||
int i;
|
||||
DBG_871X("%s compare first 0x130 byte fail\n", __FUNCTION__);
|
||||
for(i=0;i<512;i++)
|
||||
for (i=0;i<512;i++)
|
||||
{
|
||||
if (i%16==0)
|
||||
DBG_871X("0x%03x: ", i);
|
||||
|
|
@ -1817,7 +1817,7 @@ hal_EfusePgPacketRead_8188e(
|
|||
|
||||
if (hoffset==offset)
|
||||
{
|
||||
for(tmpidx = 0;tmpidx< word_cnts*2 ;tmpidx++)
|
||||
for (tmpidx = 0;tmpidx< word_cnts*2 ;tmpidx++)
|
||||
{
|
||||
if (efuse_OneByteRead(pAdapter, efuse_addr+1+tmpidx ,&efuse_data, bPseudoTest) )
|
||||
{
|
||||
|
|
@ -2206,7 +2206,7 @@ hal_EfuseCheckIfDatafollowed(
|
|||
bool bRet=false;
|
||||
u8 i, efuse_data;
|
||||
|
||||
for(i=0; i<(word_cnts*2) ; i++)
|
||||
for (i=0; i<(word_cnts*2) ; i++)
|
||||
{
|
||||
if (efuse_OneByteRead(pAdapter, (startAddr+i) ,&efuse_data, bPseudoTest)&&(efuse_data != 0xFF))
|
||||
bRet = true;
|
||||
|
|
@ -2316,7 +2316,7 @@ hal_EfusePartialWriteCheck(
|
|||
}
|
||||
}
|
||||
/* partial write ok, update the target packet for later use */
|
||||
for(i=0; i<4; i++)
|
||||
for (i=0; i<4; i++)
|
||||
{
|
||||
if ((matched_wden & (0x1<<i)) == 0) /* this word has been written */
|
||||
{
|
||||
|
|
@ -2740,7 +2740,7 @@ void Read_LLT_Tab(struct adapter *padapter)
|
|||
u32 addr,next_addr;
|
||||
|
||||
printk("############### %s ###################\n",__FUNCTION__);
|
||||
for(addr=0;addr<176;addr++) {
|
||||
for (addr=0;addr<176;addr++) {
|
||||
next_addr = _LLTRead(padapter,addr);
|
||||
printk("%d->",next_addr);
|
||||
if (((addr+1) %8) ==0)
|
||||
|
|
@ -2801,7 +2801,7 @@ Hal_InitPGData88E(struct adapter *padapter)
|
|||
if (is_boot_from_eeprom(padapter))
|
||||
{
|
||||
/* Read all Content from EEPROM or EFUSE. */
|
||||
for(i = 0; i < HWSET_MAX_SIZE_88E; i += 2)
|
||||
for (i = 0; i < HWSET_MAX_SIZE_88E; i += 2)
|
||||
{
|
||||
/* value16 = EF2Byte(ReadEEprom(pAdapter, (u16) (i>>1))); */
|
||||
/* *((u16*)(&PROMContent[i])) = value16; */
|
||||
|
|
@ -2892,15 +2892,15 @@ Hal_ReadPowerValueFromPROM_8188E(
|
|||
|
||||
if (AutoLoadFail)
|
||||
{
|
||||
for(rfPath = 0 ; rfPath < pHalData->NumTotalRFPath ; rfPath++)
|
||||
for (rfPath = 0 ; rfPath < pHalData->NumTotalRFPath ; rfPath++)
|
||||
{
|
||||
/* 2.4G default value */
|
||||
for(group = 0 ; group < MAX_CHNL_GROUP_24G; group++)
|
||||
for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++)
|
||||
{
|
||||
pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
|
||||
pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
|
||||
}
|
||||
for(TxCount=0;TxCount<MAX_TX_COUNT;TxCount++)
|
||||
for (TxCount=0;TxCount<MAX_TX_COUNT;TxCount++)
|
||||
{
|
||||
if (TxCount==0)
|
||||
{
|
||||
|
|
@ -2923,10 +2923,10 @@ Hal_ReadPowerValueFromPROM_8188E(
|
|||
return;
|
||||
}
|
||||
|
||||
for(rfPath = 0 ; rfPath < pHalData->NumTotalRFPath ; rfPath++)
|
||||
for (rfPath = 0 ; rfPath < pHalData->NumTotalRFPath ; rfPath++)
|
||||
{
|
||||
/* 2.4G default value */
|
||||
for(group = 0 ; group < MAX_CHNL_GROUP_24G; group++)
|
||||
for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++)
|
||||
{
|
||||
/* printk(" IndexCCK_Base rfPath:%d group:%d,eeAddr:0x%02x ",rfPath,group,eeAddr); */
|
||||
pwrInfo24G->IndexCCK_Base[rfPath][group] = PROMContent[eeAddr++];
|
||||
|
|
@ -2937,7 +2937,7 @@ Hal_ReadPowerValueFromPROM_8188E(
|
|||
/* pHalData->bNOPG = true; */
|
||||
}
|
||||
}
|
||||
for(group = 0 ; group < MAX_CHNL_GROUP_24G-1; group++)
|
||||
for (group = 0 ; group < MAX_CHNL_GROUP_24G-1; group++)
|
||||
{
|
||||
/* printk(" IndexBW40_Base rfPath:%d group:%d,eeAddr:0x%02x ",rfPath,group,eeAddr); */
|
||||
pwrInfo24G->IndexBW40_Base[rfPath][group] = PROMContent[eeAddr++];
|
||||
|
|
@ -2945,7 +2945,7 @@ Hal_ReadPowerValueFromPROM_8188E(
|
|||
if (pwrInfo24G->IndexBW40_Base[rfPath][group] == 0xFF)
|
||||
pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
|
||||
}
|
||||
for(TxCount=0;TxCount<MAX_TX_COUNT;TxCount++)
|
||||
for (TxCount=0;TxCount<MAX_TX_COUNT;TxCount++)
|
||||
{
|
||||
if (TxCount==0)
|
||||
{
|
||||
|
|
@ -3157,10 +3157,10 @@ Hal_ReadTxPowerInfo88E(
|
|||
if (!AutoLoadFail)
|
||||
pHalData->bTXPowerDataReadFromEEPORM = true;
|
||||
|
||||
/* for(rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) */
|
||||
for(rfPath = 0 ; rfPath < pHalData->NumTotalRFPath ; rfPath++)
|
||||
/* for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) */
|
||||
for (rfPath = 0 ; rfPath < pHalData->NumTotalRFPath ; rfPath++)
|
||||
{
|
||||
for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++)
|
||||
for (ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++)
|
||||
{
|
||||
bIn24G = Hal_GetChnlGroup88E(ch+1,&group);
|
||||
if (bIn24G)
|
||||
|
|
@ -3182,7 +3182,7 @@ Hal_ReadTxPowerInfo88E(
|
|||
}
|
||||
}
|
||||
|
||||
for(TxCount=0;TxCount<MAX_TX_COUNT;TxCount++)
|
||||
for (TxCount=0;TxCount<MAX_TX_COUNT;TxCount++)
|
||||
{
|
||||
pHalData->CCK_24G_Diff[rfPath][TxCount]=pwrInfo24G.CCK_Diff[rfPath][TxCount];
|
||||
pHalData->OFDM_24G_Diff[rfPath][TxCount]=pwrInfo24G.OFDM_Diff[rfPath][TxCount];
|
||||
|
|
|
|||
|
|
@ -68,7 +68,7 @@ phy_CalculateBitShift(
|
|||
{
|
||||
u32 i;
|
||||
|
||||
for(i=0; i<=31; i++)
|
||||
for (i=0; i<=31; i++)
|
||||
{
|
||||
if ( ((BitMask>>i) & 0x1 ) == 1)
|
||||
break;
|
||||
|
|
@ -1267,7 +1267,7 @@ PHY_CheckBBAndRFOK(
|
|||
WriteAddr[HW90_BLOCK_PHY1] = 0x800;
|
||||
WriteAddr[HW90_BLOCK_RF] = 0x3;
|
||||
|
||||
for(i=0 ; i < CheckTimes ; i++)
|
||||
for (i=0 ; i < CheckTimes ; i++)
|
||||
{
|
||||
|
||||
/* */
|
||||
|
|
@ -1512,7 +1512,7 @@ static void getTxPowerIndex88E(
|
|||
else
|
||||
path_nums = 2;
|
||||
|
||||
for(TxCount=0;TxCount< path_nums ;TxCount++)
|
||||
for (TxCount=0;TxCount< path_nums ;TxCount++)
|
||||
{
|
||||
if (TxCount==RF_PATH_A)
|
||||
{
|
||||
|
|
@ -1647,7 +1647,7 @@ PHY_UpdateTxPowerDbm8188E(
|
|||
|
||||
/* RT_TRACE(COMP_TXAGC, DBG_LOUD, ("PHY_UpdateTxPowerDbm8192S(): %ld dBm , CckTxPwrIdx = %d, OfdmTxPwrIdx = %d\n", powerInDbm, CckTxPwrIdx, OfdmTxPwrIdx)); */
|
||||
|
||||
for(idx = 0; idx < 14; idx++)
|
||||
for (idx = 0; idx < 14; idx++)
|
||||
{
|
||||
for (rf_path = 0; rf_path < 2; rf_path++)
|
||||
{
|
||||
|
|
@ -1881,7 +1881,7 @@ static void _PHY_SwChnl8192C(struct adapter *Adapter, u8 channel)
|
|||
/* s2. RF dependent command - CmdID_RF_WriteReg, param1=RF_CHNLBW, param2=channel */
|
||||
param1 = RF_CHNLBW;
|
||||
param2 = channel;
|
||||
for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
|
||||
for (eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
|
||||
{
|
||||
pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2);
|
||||
PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
|
||||
|
|
@ -2220,7 +2220,7 @@ _PHY_DumpRFReg(struct adapter *pAdapter)
|
|||
|
||||
/* RTPRINT(FINIT, INIT_RF, ("PHY_DumpRFReg()====>\n")); */
|
||||
|
||||
for(rfRegOffset = 0x00;rfRegOffset<=0x30;rfRegOffset++){
|
||||
for (rfRegOffset = 0x00;rfRegOffset<=0x30;rfRegOffset++){
|
||||
rfRegValue = PHY_QueryRFReg(pAdapter,RF_PATH_A, rfRegOffset, bMaskDWord);
|
||||
/* RTPRINT(FINIT, INIT_RF, (" 0x%02x = 0x%08x\n",rfRegOffset,rfRegValue)); */
|
||||
}
|
||||
|
|
|
|||
|
|
@ -182,7 +182,7 @@ rtl8188e_PHY_RF6052SetCckTxPower(
|
|||
|
||||
if (TurboScanOff)
|
||||
{
|
||||
for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
|
||||
for (idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
|
||||
{
|
||||
TxAGC[idx1] =
|
||||
pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
|
||||
|
|
@ -210,7 +210,7 @@ rtl8188e_PHY_RF6052SetCckTxPower(
|
|||
}
|
||||
else
|
||||
{
|
||||
for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
|
||||
for (idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
|
||||
{
|
||||
TxAGC[idx1] =
|
||||
pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
|
||||
|
|
@ -247,10 +247,10 @@ rtl8188e_PHY_RF6052SetCckTxPower(
|
|||
TxAGC[1] -= pwrtrac_value;
|
||||
}
|
||||
|
||||
for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
|
||||
for (idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
|
||||
{
|
||||
ptr = (u8*)(&(TxAGC[idx1]));
|
||||
for(idx2=0; idx2<4; idx2++)
|
||||
for (idx2=0; idx2<4; idx2++)
|
||||
{
|
||||
if (*ptr > RF6052_MAX_TX_PWR)
|
||||
*ptr = RF6052_MAX_TX_PWR;
|
||||
|
|
@ -289,7 +289,7 @@ static void getPowerBase88E(
|
|||
s8 HT20_pwrdiff=0;
|
||||
u8 i, powerlevel[2];
|
||||
|
||||
for(i=0; i<2; i++)
|
||||
for (i=0; i<2; i++)
|
||||
{
|
||||
powerBase0 = pPowerLevelOFDM[i];
|
||||
|
||||
|
|
@ -298,7 +298,7 @@ static void getPowerBase88E(
|
|||
/* DBG_871X(" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i)); */
|
||||
}
|
||||
|
||||
for(i=0; i<pHalData->NumTotalRFPath; i++)
|
||||
for (i=0; i<pHalData->NumTotalRFPath; i++)
|
||||
{
|
||||
/* Check HT20 to HT40 diff */
|
||||
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
|
||||
|
|
@ -336,7 +336,7 @@ static void getTxPowerWriteValByRegulatory88E(
|
|||
/* */
|
||||
/* Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */
|
||||
/* */
|
||||
for(rf=0; rf<2; rf++) {
|
||||
for (rf=0; rf<2; rf++) {
|
||||
switch (Regulatory) {
|
||||
case 0: /* Realtek better performance */
|
||||
/* increase power diff defined by Realtek for large power */
|
||||
|
|
@ -461,10 +461,10 @@ static void writeOFDMPowerReg88E(
|
|||
u32 writeVal;
|
||||
u16 RegOffset;
|
||||
|
||||
for(rf=0; rf<2; rf++)
|
||||
for (rf=0; rf<2; rf++)
|
||||
{
|
||||
writeVal = pValue[rf];
|
||||
for(i=0; i<4; i++)
|
||||
for (i=0; i<4; i++)
|
||||
{
|
||||
pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));
|
||||
if (pwr_val[i] > RF6052_MAX_TX_PWR)
|
||||
|
|
@ -491,7 +491,7 @@ static void writeOFDMPowerReg88E(
|
|||
RegOffset = 0xc90;
|
||||
if (RegOffset == rTxAGC_B_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs07_Mcs04)
|
||||
RegOffset = 0xc98;
|
||||
for(i=0; i<3; i++)
|
||||
for (i=0; i<3; i++)
|
||||
{
|
||||
if (i!=2)
|
||||
writeVal = (writeVal>8)?(writeVal-8):0;
|
||||
|
|
@ -551,7 +551,7 @@ rtl8188e_PHY_RF6052SetOFDMTxPower(
|
|||
/* */
|
||||
ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 0, &direction, &pwrtrac_value);
|
||||
|
||||
for(index=0; index<6; index++)
|
||||
for (index=0; index<6; index++)
|
||||
{
|
||||
getTxPowerWriteValByRegulatory88E(Adapter, Channel, index,
|
||||
&powerBase0[0], &powerBase1[0], &writeVal[0]);
|
||||
|
|
@ -610,8 +610,8 @@ phy_RF6052_Config_ParaFile(
|
|||
/* 3----------------------------------------------------------------- */
|
||||
/* 3 <2> Initialize RF */
|
||||
/* 3----------------------------------------------------------------- */
|
||||
/* for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) */
|
||||
for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
|
||||
/* for (eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) */
|
||||
for (eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
|
||||
{
|
||||
|
||||
pPhyReg = &pHalData->PHYRegDef[eRFPath];
|
||||
|
|
|
|||
|
|
@ -92,7 +92,7 @@ int rtl8188eu_init_recv_priv(struct adapter *padapter)
|
|||
|
||||
precvbuf = (struct recv_buf*)precvpriv->precv_buf;
|
||||
|
||||
for(i=0; i < NR_RECVBUFF ; i++) {
|
||||
for (i=0; i < NR_RECVBUFF ; i++) {
|
||||
_rtw_init_listhead(&precvbuf->list);
|
||||
|
||||
spin_lock_init(&precvbuf->recvbuf_lock);
|
||||
|
|
@ -126,7 +126,7 @@ int rtl8188eu_init_recv_priv(struct adapter *padapter)
|
|||
|
||||
skb_queue_head_init(&precvpriv->free_recv_skb_queue);
|
||||
|
||||
for(i=0; i<NR_PREALLOC_RECV_SKB; i++)
|
||||
for (i=0; i<NR_PREALLOC_RECV_SKB; i++)
|
||||
{
|
||||
pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
|
||||
|
||||
|
|
@ -158,7 +158,7 @@ void rtl8188eu_free_recv_priv (struct adapter *padapter)
|
|||
|
||||
precvbuf = (struct recv_buf *)precvpriv->precv_buf;
|
||||
|
||||
for(i=0; i < NR_RECVBUFF ; i++)
|
||||
for (i=0; i < NR_RECVBUFF ; i++)
|
||||
{
|
||||
rtw_os_recvbuf_resource_free(padapter, precvbuf);
|
||||
precvbuf++;
|
||||
|
|
|
|||
|
|
@ -62,7 +62,7 @@ static void rtl8188eu_cal_txdesc_chksum(struct tx_desc *ptxdesc)
|
|||
/* Clear first */
|
||||
ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
|
||||
|
||||
for(index = 0 ; index < count ; index++){
|
||||
for (index = 0 ; index < count ; index++){
|
||||
checksum = checksum ^ le16_to_cpu(*(__le16 *)(usPtr + index));
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -172,7 +172,7 @@ static void _dbg_dump_macreg(struct adapter *padapter)
|
|||
u32 offset = 0;
|
||||
u32 val32 = 0;
|
||||
u32 index =0 ;
|
||||
for(index=0;index<64;index++)
|
||||
for (index=0;index<64;index++)
|
||||
{
|
||||
offset = index*4;
|
||||
val32 = rtw_read32(padapter,offset);
|
||||
|
|
@ -285,7 +285,7 @@ _SetMacID(
|
|||
)
|
||||
{
|
||||
u32 i;
|
||||
for(i=0 ; i< MAC_ADDR_LEN ; i++){
|
||||
for (i=0 ; i< MAC_ADDR_LEN ; i++){
|
||||
rtw_write32(Adapter, REG_MACID+i, MacID[i]);
|
||||
}
|
||||
}
|
||||
|
|
@ -296,7 +296,7 @@ _SetBSSID(
|
|||
)
|
||||
{
|
||||
u32 i;
|
||||
for(i=0 ; i< MAC_ADDR_LEN ; i++){
|
||||
for (i=0 ; i< MAC_ADDR_LEN ; i++){
|
||||
rtw_write32(Adapter, REG_BSSID+i, BSSID[i]);
|
||||
}
|
||||
}
|
||||
|
|
@ -1228,7 +1228,7 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter)
|
|||
int hal_init_profiling_i;
|
||||
u32 hal_init_stages_timestamp[HAL_INIT_STAGES_NUM]; /* used to record the time of each stage's starting point */
|
||||
|
||||
for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM;hal_init_profiling_i++)
|
||||
for (hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM;hal_init_profiling_i++)
|
||||
hal_init_stages_timestamp[hal_init_profiling_i]=0;
|
||||
|
||||
#define HAL_INIT_PROFILE_TAG(stage) hal_init_stages_timestamp[(stage)]=rtw_get_current_time();
|
||||
|
|
@ -1527,7 +1527,7 @@ exit:
|
|||
#ifdef DBG_HAL_INIT_PROFILING
|
||||
hal_init_stages_timestamp[HAL_INIT_STAGES_END]=rtw_get_current_time();
|
||||
|
||||
for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM-1;hal_init_profiling_i++) {
|
||||
for (hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM-1;hal_init_profiling_i++) {
|
||||
DBG_871X("DBG_HAL_INIT_PROFILING: %35s, %u, %5u, %5u\n"
|
||||
, hal_init_stages_str[hal_init_profiling_i]
|
||||
, hal_init_stages_timestamp[hal_init_profiling_i]
|
||||
|
|
@ -1678,7 +1678,7 @@ static unsigned int rtl8188eu_inirp_init(struct adapter *Adapter)
|
|||
|
||||
/* issue Rx irp to receive data */
|
||||
precvbuf = (struct recv_buf *)precvpriv->precv_buf;
|
||||
for(i=0; i<NR_RECVBUFF; i++)
|
||||
for (i=0; i<NR_RECVBUFF; i++)
|
||||
{
|
||||
if (_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == false )
|
||||
{
|
||||
|
|
@ -2157,7 +2157,7 @@ static void hw_var_set_macaddr(struct adapter *Adapter, u8 variable, u8* val)
|
|||
|
||||
reg_macid = REG_MACID;
|
||||
|
||||
for(idx = 0 ; idx < 6; idx++)
|
||||
for (idx = 0 ; idx < 6; idx++)
|
||||
rtw_write8(Adapter, (reg_macid+idx), val[idx]);
|
||||
}
|
||||
|
||||
|
|
@ -2168,7 +2168,7 @@ static void hw_var_set_bssid(struct adapter *Adapter, u8 variable, u8* val)
|
|||
|
||||
reg_bssid = REG_BSSID;
|
||||
|
||||
for(idx = 0 ; idx < 6; idx++)
|
||||
for (idx = 0 ; idx < 6; idx++)
|
||||
rtw_write8(Adapter, (reg_bssid+idx), val[idx]);
|
||||
}
|
||||
|
||||
|
|
@ -2545,7 +2545,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
|
|||
u32 ulContent=0;
|
||||
u32 ulEncAlgo=CAM_AES;
|
||||
|
||||
for(i=0;i<CAM_CONTENT_COUNT;i++)
|
||||
for (i=0;i<CAM_CONTENT_COUNT;i++)
|
||||
{
|
||||
/* filled id in CAM config 2 byte */
|
||||
if ( i == 0)
|
||||
|
|
@ -2679,7 +2679,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
|
|||
if (FactorToSet>0xf)
|
||||
FactorToSet = 0xf;
|
||||
|
||||
for(index=0; index<4; index++)
|
||||
for (index=0; index<4; index++)
|
||||
{
|
||||
if ((pRegToSet[index] & 0xf0) > (FactorToSet<<4))
|
||||
pRegToSet[index] = (pRegToSet[index] & 0x0f) | (FactorToSet<<4);
|
||||
|
|
@ -3018,7 +3018,7 @@ static u8 GetHalDefVar8188EUsb(
|
|||
DBG_871X("============ RA status check ===================\n");
|
||||
if (Adapter->bRxRSSIDisplay >30)
|
||||
Adapter->bRxRSSIDisplay = 1;
|
||||
for(i=0;i< Adapter->bRxRSSIDisplay;i++){
|
||||
for (i=0;i< Adapter->bRxRSSIDisplay;i++){
|
||||
DBG_8192C("Mac_id:%d ,RSSI:%d,RateID = %d,RAUseRate = 0x%08x,RateSGI = %d, DecisionRate = 0x%02x ,PTStage = %d, RetryOver drop:%d, LifeTimeOver drop:%d\n",
|
||||
i,
|
||||
podmpriv->RAInfo[i].RssiStaRA,
|
||||
|
|
@ -3343,7 +3343,7 @@ static void rtl8188eu_init_default_value(struct adapter * padapter)
|
|||
pHalData->pwrGroupCnt = 0;
|
||||
pHalData->PGMaxGroup= 13;
|
||||
pHalData->odmpriv.RFCalibrateInfo.ThermalValue_HP_index = 0;
|
||||
for(i = 0; i < HP_THERMAL_NUM; i++)
|
||||
for (i = 0; i < HP_THERMAL_NUM; i++)
|
||||
pHalData->odmpriv.RFCalibrateInfo.ThermalValue_HP[i] = 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue