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https://github.com/lwfinger/rtl8188eu.git
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rtl8188eu: Remove code used only for Windows
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
parent
2caee63170
commit
a68c6cc26e
42 changed files with 9 additions and 1912 deletions
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@ -807,7 +807,6 @@ typedef enum tag_DBGP_Flag_Type_Definition
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// Please add new OS's print API by yourself
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//#if (RT_PLATFORM==PLATFORM_WINDOWS)
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#if (DEBUG_PRINT == 1) && DBG
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#define RTPRINT(dbgtype, dbgflag, printstr)\
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{\
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@ -2912,429 +2912,6 @@ phy_DigitalPredistortion(
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IN BOOLEAN is2T
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)
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{
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#if ( RT_PLATFORM == PLATFORM_WINDOWS)
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#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
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#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
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PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
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#endif
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#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
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PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
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#endif
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#endif
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u4Byte tmpReg, tmpReg2, index, i;
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u1Byte path, pathbound = PATH_NUM;
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u4Byte AFE_backup[IQK_ADDA_REG_NUM];
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u4Byte AFE_REG[IQK_ADDA_REG_NUM] = {
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rFPGA0_XCD_SwitchControl, rBlue_Tooth,
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rRx_Wait_CCA, rTx_CCK_RFON,
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rTx_CCK_BBON, rTx_OFDM_RFON,
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rTx_OFDM_BBON, rTx_To_Rx,
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rTx_To_Tx, rRx_CCK,
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rRx_OFDM, rRx_Wait_RIFS,
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rRx_TO_Rx, rStandby,
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rSleep, rPMPD_ANAEN };
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u4Byte BB_backup[DP_BB_REG_NUM];
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u4Byte BB_REG[DP_BB_REG_NUM] = {
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rOFDM0_TRxPathEnable, rFPGA0_RFMOD,
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rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW,
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rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
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rFPGA0_XB_RFInterfaceOE};
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u4Byte BB_settings[DP_BB_REG_NUM] = {
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0x00a05430, 0x02040000, 0x000800e4, 0x22208000,
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0x0, 0x0, 0x0};
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u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM];
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u4Byte RF_REG[DP_RF_REG_NUM] = {
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RF_TXBIAS_A};
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u4Byte MAC_backup[IQK_MAC_REG_NUM];
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u4Byte MAC_REG[IQK_MAC_REG_NUM] = {
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REG_TXPAUSE, REG_BCN_CTRL,
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REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
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u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = {
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{0x1e1e1e1e, 0x03901e1e},
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{0x18181818, 0x03901818},
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{0x0e0e0e0e, 0x03900e0e}
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};
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u4Byte AFE_on_off[PATH_NUM] = {
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0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on
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u1Byte RetryCount = 0;
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion()\n"));
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion for %s %s\n", (is2T ? "2T2R" : "1T1R")));
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//save BB default value
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for(index=0; index<DP_BB_REG_NUM; index++)
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BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord);
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//save MAC default value
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#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
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_PHY_SaveMACRegisters(pAdapter, BB_REG, MAC_backup);
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#else
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_PHY_SaveMACRegisters(pDM_Odm, BB_REG, MAC_backup);
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#endif
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//save RF default value
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for(path=0; path<DP_PATH_NUM; path++)
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{
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for(index=0; index<DP_RF_REG_NUM; index++)
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#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
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RF_backup[path][index] = PHY_QueryRFReg(pAdapter, path, RF_REG[index], bMaskDWord);
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#else
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RF_backup[path][index] = ODM_GetRFReg(pAdapter, path, RF_REG[index], bMaskDWord);
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#endif
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}
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//save AFE default value
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#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
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_PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
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#else
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RF_backup[path][index] = ODM_GetRFReg(pAdapter, path, RF_REG[index], bMaskDWord);
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#endif
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//Path A/B AFE all on
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for(index = 0; index < IQK_ADDA_REG_NUM ; index++)
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ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, 0x6fdb25a4);
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//BB register setting
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for(index = 0; index < DP_BB_REG_NUM; index++)
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{
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if(index < 4)
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ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_settings[index]);
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else if (index == 4)
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ODM_SetBBReg(pDM_Odm,BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);
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else
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ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x00);
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}
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//MAC register setting
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#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
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_PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup);
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#else
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_PHY_MACSettingCalibration(pDM_Odm, MAC_REG, MAC_backup);
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#endif
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//PAGE-E IQC setting
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ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
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ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
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ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);
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ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);
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//path_A DPK
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//Path B to standby mode
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ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x10000);
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// PA gain = 11 & PAD1 => tx_agc 1f ~11
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// PA gain = 11 & PAD2 => tx_agc 10~0e
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// PA gain = 01 => tx_agc 0b~0d
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// PA gain = 00 => tx_agc 0a~00
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ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000);
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ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f);
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ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
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//do inner loopback DPK 3 times
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for(i = 0; i < 3; i++)
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{
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//PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07
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for(index = 0; index < 3; index++)
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ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]);
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ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]);
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for(index = 0; index < 4; index++)
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ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]);
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// PAGE_B for Path-A inner loopback DPK setting
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ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098);
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ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84);
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ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);
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ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000);
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//----send one shot signal----//
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// Path A
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ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788);
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ODM_delay_ms(1);
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ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788);
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ODM_delay_ms(50);
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}
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//PA gain = 11 => tx_agc = 1a
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for(index = 0; index < 3; index++)
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ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434);
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ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434);
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for(index = 0; index < 4; index++)
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ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434);
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//====================================
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// PAGE_B for Path-A DPK setting
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//====================================
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// open inner loopback @ b00[19]:10 od 0xb00 0x01097018
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ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098);
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ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84);
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ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);
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ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000);
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//rf_lpbk_setup
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//1.rf 00:5205a, rf 0d:0e52c
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ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0c, bMaskDWord, 0x8992b);
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ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c);
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ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bMaskDWord, 0x5205a );
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//----send one shot signal----//
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// Path A
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ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0);
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ODM_delay_ms(1);
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ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0);
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ODM_delay_ms(50);
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while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK)
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{
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//----read back measurement results----//
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ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018);
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tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord);
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ODM_delay_ms(10);
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ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f);
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tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord);
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ODM_delay_ms(10);
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tmpReg = (tmpReg & bMaskHWord) >> 16;
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tmpReg2 = (tmpReg2 & bMaskHWord) >> 16;
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if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff )
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{
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ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098);
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ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000);
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ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
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ODM_delay_ms(1);
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ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0);
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ODM_delay_ms(1);
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ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0);
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ODM_delay_ms(50);
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RetryCount++;
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2));
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}
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else
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{
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n"));
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pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE;
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break;
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}
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}
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RetryCount = 0;
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//DPP path A
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if(pDM_Odm->RFCalibrateInfo.bDPPathAOK)
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{
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// DP settings
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ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098);
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ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84);
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ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);
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ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000);
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ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000);
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for(i=rPdp_AntA; i<=0xb3c; i+=4)
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{
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ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i));
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}
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//pwsf
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ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040);
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ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040);
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ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920);
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for(i=0xb4c; i<=0xb5c; i+=4)
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{
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ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c);
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}
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//TX_AGC boundary
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ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f);
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ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
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}
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else
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{
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ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000);
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ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000);
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}
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//DPK path B
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if(is2T)
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{
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//Path A to standby mode
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ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000);
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// LUTs => tx_agc
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// PA gain = 11 & PAD1, => tx_agc 1f ~11
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// PA gain = 11 & PAD2, => tx_agc 10 ~0e
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// PA gain = 01 => tx_agc 0b ~0d
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// PA gain = 00 => tx_agc 0a ~00
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ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000);
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ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f);
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ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
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//do inner loopback DPK 3 times
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for(i = 0; i < 3; i++)
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{
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//PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07
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for(index = 0; index < 4; index++)
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ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]);
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for(index = 0; index < 2; index++)
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ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]);
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for(index = 0; index < 2; index++)
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ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]);
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// PAGE_B for Path-A inner loopback DPK setting
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ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098);
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ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84);
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ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);
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ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);
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//----send one shot signal----//
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// Path B
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ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788);
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ODM_delay_ms(1);
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ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788);
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ODM_delay_ms(50);
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}
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// PA gain = 11 => tx_agc = 1a
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for(index = 0; index < 4; index++)
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ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434);
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for(index = 0; index < 2; index++)
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ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434);
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for(index = 0; index < 2; index++)
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ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434);
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// PAGE_B for Path-B DPK setting
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ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098);
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ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84);
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ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);
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ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);
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// RF lpbk switches on
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ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f);
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ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103);
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//Path-B RF lpbk
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ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x0c, bMaskDWord, 0x8992b);
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ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c);
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ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x5205a);
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//----send one shot signal----//
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ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0);
|
||||
ODM_delay_ms(1);
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0);
|
||||
ODM_delay_ms(50);
|
||||
|
||||
while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK)
|
||||
{
|
||||
//----read back measurement results----//
|
||||
ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018);
|
||||
tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord);
|
||||
ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f);
|
||||
tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord);
|
||||
|
||||
tmpReg = (tmpReg & bMaskHWord) >> 16;
|
||||
tmpReg2 = (tmpReg2 & bMaskHWord) >> 16;
|
||||
|
||||
if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff)
|
||||
{
|
||||
ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098);
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000);
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
|
||||
ODM_delay_ms(1);
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0);
|
||||
ODM_delay_ms(1);
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0);
|
||||
ODM_delay_ms(50);
|
||||
RetryCount++;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2));
|
||||
}
|
||||
else
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n"));
|
||||
pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
//DPP path B
|
||||
if(pDM_Odm->RFCalibrateInfo.bDPPathBOK)
|
||||
{
|
||||
// DP setting
|
||||
// LUT by SRAM
|
||||
ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098);
|
||||
ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84);
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);
|
||||
ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);
|
||||
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000);
|
||||
for(i=0xb60; i<=0xb9c; i+=4)
|
||||
{
|
||||
ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000);
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i));
|
||||
}
|
||||
|
||||
// PWSF
|
||||
ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040);
|
||||
ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050);
|
||||
ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920);
|
||||
|
||||
for(i=0xbac; i<=0xbbc; i+=4)
|
||||
{
|
||||
ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c);
|
||||
}
|
||||
|
||||
// tx_agc boundary
|
||||
ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f);
|
||||
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000);
|
||||
ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000);
|
||||
}
|
||||
}
|
||||
|
||||
//reload BB default value
|
||||
for(index=0; index<DP_BB_REG_NUM; index++)
|
||||
ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]);
|
||||
|
||||
//reload RF default value
|
||||
for(path = 0; path<DP_PATH_NUM; path++)
|
||||
{
|
||||
for( i = 0 ; i < DP_RF_REG_NUM ; i++){
|
||||
ODM_SetRFReg(pDM_Odm, path, RF_REG[i], bMaskDWord, RF_backup[path][i]);
|
||||
}
|
||||
}
|
||||
ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); //standby mode
|
||||
ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); //RF lpbk switches off
|
||||
|
||||
//reload AFE default value
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
_PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
|
||||
|
||||
//reload MAC default value
|
||||
_PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup);
|
||||
#else
|
||||
_PHY_ReloadADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
|
||||
|
||||
//reload MAC default value
|
||||
_PHY_ReloadMACRegisters(pDM_Odm, MAC_REG, MAC_backup);
|
||||
#endif
|
||||
|
||||
pDM_Odm->RFCalibrateInfo.bDPdone = TRUE;
|
||||
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion()\n"));
|
||||
#endif
|
||||
}
|
||||
|
||||
VOID
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue