skyfall/rtl8188eu
1
0
Fork 0
mirror of https://github.com/lwfinger/rtl8188eu.git synced 2025-05-08 22:43:04 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

rtl8188eu: Remove C90 comments from include/*.h

Browse source 
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2015-03-16 09:43:53 -05:00
parent e2285839e9
commit b2720d8002
73 changed files with 3323 additions and 3402 deletions
Download patch file Download diff file Expand all files Collapse all files

62
include/HalPwrSeqCmd.h
View file

@ -23,51 +23,51 @@
#include <drv_types.h>
/*---------------------------------------------*/
//3 The value of cmd: 4 bits
/* 3 The value of cmd: 4 bits */
/*---------------------------------------------*/
#define PWR_CMD_READ 0x00
// offset: the read register offset
// msk: the mask of the read value
// value: N/A, left by 0
// note: dirver shall implement this function by read & msk
/* offset: the read register offset */
/* msk: the mask of the read value */
/* value: N/A, left by 0 */
/* note: dirver shall implement this function by read & msk */
#define PWR_CMD_WRITE 0x01
// offset: the read register offset
// msk: the mask of the write bits
// value: write value
// note: driver shall implement this cmd by read & msk after write
/* offset: the read register offset */
/* msk: the mask of the write bits */
/* value: write value */
/* note: driver shall implement this cmd by read & msk after write */
#define PWR_CMD_POLLING 0x02
// offset: the read register offset
// msk: the mask of the polled value
// value: the value to be polled, masked by the msd field.
// note: driver shall implement this cmd by
// do{
// if( (Read(offset) & msk) == (value & msk) )
// break;
// } while(not timeout);
/* offset: the read register offset */
/* msk: the mask of the polled value */
/* value: the value to be polled, masked by the msd field. */
/* note: driver shall implement this cmd by */
/* do{ */
/* if( (Read(offset) & msk) == (value & msk) ) */
/* break; */
/* } while(not timeout); */
#define PWR_CMD_DELAY 0x03
// offset: the value to delay
// msk: N/A
// value: the unit of delay, 0: us, 1: ms
/* offset: the value to delay */
/* msk: N/A */
/* value: the unit of delay, 0: us, 1: ms */
#define PWR_CMD_END 0x04
// offset: N/A
// msk: N/A
// value: N/A
/* offset: N/A */
/* msk: N/A */
/* value: N/A */
/*---------------------------------------------*/
//3 The value of base: 4 bits
/* 3 The value of base: 4 bits */
/*---------------------------------------------*/
// define the base address of each block
/* define the base address of each block */
#define PWR_BASEADDR_MAC 0x00
#define PWR_BASEADDR_USB 0x01
#define PWR_BASEADDR_PCIE 0x02
#define PWR_BASEADDR_SDIO 0x03
/*---------------------------------------------*/
//3 The value of interface_msk: 4 bits
/* 3 The value of interface_msk: 4 bits */
/*---------------------------------------------*/
#define PWR_INTF_SDIO_MSK BIT(0)
#define PWR_INTF_USB_MSK BIT(1)
@ -75,14 +75,14 @@
#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
/*---------------------------------------------*/
//3 The value of fab_msk: 4 bits
/* 3 The value of fab_msk: 4 bits */
/*---------------------------------------------*/
#define PWR_FAB_TSMC_MSK BIT(0)
#define PWR_FAB_UMC_MSK BIT(1)
#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
/*---------------------------------------------*/
//3 The value of cut_msk: 8 bits
/* 3 The value of cut_msk: 8 bits */
/*---------------------------------------------*/
#define PWR_CUT_TESTCHIP_MSK BIT(0)
#define PWR_CUT_A_MSK BIT(1)
@ -122,9 +122,9 @@ struct wl_pwr_cfg {
#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
//================================================================================
// Prototype of protected function.
//================================================================================
/* */
/* Prototype of protected function. */
/* */
u8 HalPwrSeqCmdParsing(
struct adapter * padapter,
u8 CutVersion,