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rtl8188eu: Remove C90 comments from include/*.h

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2015-03-16 09:43:53 -05:00
parent e2285839e9
commit b2720d8002
73 changed files with 3323 additions and 3402 deletions
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186
include/Hal8188EPhyCfg.h
View file

@ -23,8 +23,8 @@
/*--------------------------Define Parameters-------------------------------*/ /*--------------------------Define Parameters-------------------------------*/
#define LOOP_LIMIT 5 #define LOOP_LIMIT 5
#define MAX_STALL_TIME 50 //us #define MAX_STALL_TIME 50 /* us */
#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80) #define AntennaDiversityValue 0x80 /* Adapter->bSoftwareAntennaDiversity ? 0x00:0x80) */
#define MAX_TXPWR_IDX_NMODE_92S 63 #define MAX_TXPWR_IDX_NMODE_92S 63
#define Reset_Cnt_Limit 3 #define Reset_Cnt_Limit 3
@ -64,37 +64,36 @@ typedef enum _HW90_BLOCK{
HW90_BLOCK_PHY0 = 1, HW90_BLOCK_PHY0 = 1,
HW90_BLOCK_PHY1 = 2, HW90_BLOCK_PHY1 = 2,
HW90_BLOCK_RF = 3, HW90_BLOCK_RF = 3,
HW90_BLOCK_MAXIMUM = 4, // Never use this HW90_BLOCK_MAXIMUM = 4, /* Never use this */
}HW90_BLOCK_E, *PHW90_BLOCK_E; }HW90_BLOCK_E, *PHW90_BLOCK_E;
typedef enum _RF_RADIO_PATH{ typedef enum _RF_RADIO_PATH{
RF_PATH_A = 0, //Radio Path A RF_PATH_A = 0, /* Radio Path A */
RF_PATH_B = 1, //Radio Path B RF_PATH_B = 1, /* Radio Path B */
RF_PATH_C = 2, //Radio Path C RF_PATH_C = 2, /* Radio Path C */
RF_PATH_D = 3, //Radio Path D RF_PATH_D = 3, /* Radio Path D */
//RF_PATH_MAX //Max RF number 90 support
}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E; }RF_RADIO_PATH_E, *PRF_RADIO_PATH_E;
#define MAX_PG_GROUP 13 #define MAX_PG_GROUP 13
#define RF_PATH_MAX 2 #define RF_PATH_MAX 2
#define MAX_RF_PATH RF_PATH_MAX #define MAX_RF_PATH RF_PATH_MAX
#define MAX_TX_COUNT_88E 1 #define MAX_TX_COUNT_88E 1
#define MAX_TX_COUNT MAX_TX_COUNT_88E // 4 //path numbers #define MAX_TX_COUNT MAX_TX_COUNT_88E /* 4 path numbers */
#define CHANNEL_MAX_NUMBER 14 // 14 is the max channel number #define CHANNEL_MAX_NUMBER 14 /* 14 is the max channel number */
#define MAX_CHNL_GROUP_24G 6 // ch1~2, ch3~5, ch6~8,ch9~11,ch12~13,CH 14 total six groups #define MAX_CHNL_GROUP_24G 6 /* ch1~2, ch3~5, ch6~8,ch9~11,ch12~13,CH 14 total six groups */
#define CHANNEL_GROUP_MAX_88E 6 #define CHANNEL_GROUP_MAX_88E 6
typedef enum _WIRELESS_MODE { typedef enum _WIRELESS_MODE {
WIRELESS_MODE_UNKNOWN = 0x00, WIRELESS_MODE_UNKNOWN = 0x00,
WIRELESS_MODE_A = BIT2, WIRELESS_MODE_A = BIT2,
WIRELESS_MODE_B = BIT0, WIRELESS_MODE_B = BIT0,
WIRELESS_MODE_G = BIT1, WIRELESS_MODE_G = BIT1,
WIRELESS_MODE_AUTO = BIT5, WIRELESS_MODE_AUTO = BIT5,
WIRELESS_MODE_N_24G = BIT3, WIRELESS_MODE_N_24G = BIT3,
WIRELESS_MODE_N_5G = BIT4, WIRELESS_MODE_N_5G = BIT4,
WIRELESS_MODE_AC = BIT6 WIRELESS_MODE_AC = BIT6
} WIRELESS_MODE; } WIRELESS_MODE;
@ -111,70 +110,69 @@ typedef enum _PHY_Rate_Tx_Power_Offset_Area{
/* BB/RF related */ /* BB/RF related */
typedef enum _RF_TYPE_8190P{ typedef enum _RF_TYPE_8190P{
RF_TYPE_MIN, // 0 RF_TYPE_MIN, /* 0 */
RF_8225=1, // 1 11b/g RF for verification only RF_8225=1, /* 1 11b/g RF for verification only */
RF_8256=2, // 2 11b/g/n RF_8256=2, /* 2 11b/g/n */
RF_8258=3, // 3 11a/b/g/n RF RF_8258=3, /* 3 11a/b/g/n RF */
RF_6052=4, // 4 11b/g/n RF RF_6052=4, /* 4 11b/g/n RF */
//RF_6052=5, // 4 11b/g/n RF /* TODO: We sholud remove this psudo PHY RF after we get new RF. */
// TODO: We sholud remove this psudo PHY RF after we get new RF. RF_PSEUDO_11N=5, /* 5, It is a temporality RF. */
RF_PSEUDO_11N=5, // 5, It is a temporality RF.
}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E; }RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
typedef struct _BB_REGISTER_DEFINITION{ typedef struct _BB_REGISTER_DEFINITION{
u32 rfintfs; // set software control: u32 rfintfs; /* set software control: */
// 0x870~0x877[8 bytes] /* 0x870~0x877[8 bytes] */
u32 rfintfi; // readback data: u32 rfintfi; /* readback data: */
// 0x8e0~0x8e7[8 bytes] /* 0x8e0~0x8e7[8 bytes] */
u32 rfintfo; // output data: u32 rfintfo; /* output data: */
// 0x860~0x86f [16 bytes] /* 0x860~0x86f [16 bytes] */
u32 rfintfe; // output enable: u32 rfintfe; /* output enable: */
// 0x860~0x86f [16 bytes] /* 0x860~0x86f [16 bytes] */
u32 rf3wireOffset; // LSSI data: u32 rf3wireOffset; /* LSSI data: */
// 0x840~0x84f [16 bytes] /* 0x840~0x84f [16 bytes] */
u32 rfLSSI_Select; // BB Band Select: u32 rfLSSI_Select; /* BB Band Select: */
// 0x878~0x87f [8 bytes] /* 0x878~0x87f [8 bytes] */
u32 rfTxGainStage; // Tx gain stage: u32 rfTxGainStage; /* Tx gain stage: */
// 0x80c~0x80f [4 bytes] /* 0x80c~0x80f [4 bytes] */
u32 rfHSSIPara1; // wire parameter control1 : u32 rfHSSIPara1; /* wire parameter control1 : */
// 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] /* 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] */
u32 rfHSSIPara2; // wire parameter control2 : u32 rfHSSIPara2; /* wire parameter control2 : */
// 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] /* 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] */
u32 rfSwitchControl; //Tx Rx antenna control : u32 rfSwitchControl; /* Tx Rx antenna control : */
// 0x858~0x85f [16 bytes] /* 0x858~0x85f [16 bytes] */
u32 rfAGCControl1; //AGC parameter control1 : u32 rfAGCControl1; /* AGC parameter control1 : */
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] /* 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] */
u32 rfAGCControl2; //AGC parameter control2 : u32 rfAGCControl2; /* AGC parameter control2 : */
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] /* 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] */
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : u32 rfRxIQImbalance; /* OFDM Rx IQ imbalance matrix : */
// 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] /* 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] */
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : u32 rfRxAFE; /* Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : */
// 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] /* 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] */
u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */
// 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] /* 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] */
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type u32 rfTxAFE; /* Tx IQ DC Offset and Tx DFIR type */
// 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] /* 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] */
u32 rfLSSIReadBack; //LSSI RF readback data SI mode u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */
// 0x8a0~0x8af [16 bytes] /* 0x8a0~0x8af [16 bytes] */
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for Path A and B */
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T; }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
@ -208,9 +206,9 @@ typedef struct _R_ANTENNA_SELECT_CCK{
/*--------------------------Exported Function prototype---------------------*/ /*--------------------------Exported Function prototype---------------------*/
// /* */
// BB and RF register read/write /* BB and RF register read/write */
// /* */
u32 rtl8188e_PHY_QueryBBReg( struct adapter *Adapter, u32 rtl8188e_PHY_QueryBBReg( struct adapter *Adapter,
u32 RegAddr, u32 RegAddr,
u32 BitMask ); u32 BitMask );
@ -228,9 +226,9 @@ void rtl8188e_PHY_SetRFReg( struct adapter * Adapter,
u32 BitMask, u32 BitMask,
u32 Data ); u32 Data );
// /* */
// Initialization related function /* Initialization related function */
// /* */
/* MAC/BB/RF HAL config */ /* MAC/BB/RF HAL config */
int PHY_MACConfig8188E(struct adapter *Adapter ); int PHY_MACConfig8188E(struct adapter *Adapter );
int PHY_BBConfig8188E(struct adapter *Adapter ); int PHY_BBConfig8188E(struct adapter *Adapter );
@ -244,44 +242,44 @@ int rtl8188e_PHY_ConfigRFWithHeaderFile(struct adapter *Adapter,
/* Read initi reg value for tx power setting. */ /* Read initi reg value for tx power setting. */
void rtl8192c_PHY_GetHWRegOriginalValue(struct adapter * Adapter ); void rtl8192c_PHY_GetHWRegOriginalValue(struct adapter * Adapter );
// /* */
// BB TX Power R/W /* BB TX Power R/W */
// /* */
void PHY_GetTxPowerLevel8188E(struct adapter *Adapter, u32 *powerlevel); void PHY_GetTxPowerLevel8188E(struct adapter *Adapter, u32 *powerlevel);
void PHY_SetTxPowerLevel8188E(struct adapter *Adapter, u8 channel); void PHY_SetTxPowerLevel8188E(struct adapter *Adapter, u8 channel);
bool PHY_UpdateTxPowerDbm8188E(struct adapter *Adapter, int powerInDbm); bool PHY_UpdateTxPowerDbm8188E(struct adapter *Adapter, int powerInDbm);
// /* */
void void
PHY_ScanOperationBackup8188E(struct adapter *Adapter, u8 Operation); PHY_ScanOperationBackup8188E(struct adapter *Adapter, u8 Operation);
// /* */
// Switch bandwidth for 8192S /* Switch bandwidth for 8192S */
// /* */
void PHY_SetBWMode8188E(struct adapter *pAdapter, enum HT_CHANNEL_WIDTH ChnlWidth, unsigned char Offset); void PHY_SetBWMode8188E(struct adapter *pAdapter, enum HT_CHANNEL_WIDTH ChnlWidth, unsigned char Offset);
// /* */
// Set A2 entry to fw for 8192S /* Set A2 entry to fw for 8192S */
// /* */
extern void FillA2Entry8192C( struct adapter * Adapter, extern void FillA2Entry8192C( struct adapter * Adapter,
u8 index, u8 index,
u8* val); u8* val);
// /* */
// channel switch related funciton /* channel switch related funciton */
// /* */
void PHY_SwChnl8188E( struct adapter * pAdapter, void PHY_SwChnl8188E( struct adapter * pAdapter,
u8 channel ); u8 channel );
// Call after initialization /* Call after initialization */
void PHY_SwChnlPhy8192C( struct adapter * pAdapter, void PHY_SwChnlPhy8192C( struct adapter * pAdapter,
u8 channel ); u8 channel );
void ChkFwCmdIoDone( struct adapter *Adapter); void ChkFwCmdIoDone( struct adapter *Adapter);
// /* */
// BB/MAC/RF other monitor API /* BB/MAC/RF other monitor API */
// /* */
void PHY_SetMonitorMode8192C(struct adapter *pAdapter, void PHY_SetMonitorMode8192C(struct adapter *pAdapter,
bool bEnableMonitorMode ); bool bEnableMonitorMode );
@ -324,10 +322,10 @@ storePwrIndexDiffRateOffset(
#define PHY_SetMacReg PHY_SetBBReg #define PHY_SetMacReg PHY_SetBBReg
#define PHY_QueryMacReg PHY_QueryBBReg #define PHY_QueryMacReg PHY_QueryBBReg
//================================================================== /* */
#define SIC_ENABLE 0 #define SIC_ENABLE 0
#define SIC_HW_SUPPORT 0 #define SIC_HW_SUPPORT 0
//================================================================== /* */
#define SIC_MAX_POLL_CNT 5 #define SIC_MAX_POLL_CNT 5
@ -342,21 +340,21 @@ storePwrIndexDiffRateOffset(
#define SIC_INIT_VAL 0xff #define SIC_INIT_VAL 0xff
#define SIC_INIT_REG 0x1b7 #define SIC_INIT_REG 0x1b7
#define SIC_CMD_REG 0x1EB // 1byte #define SIC_CMD_REG 0x1EB /* 1byte */
#define SIC_ADDR_REG 0x1E8 // 1b4~1b5, 2 bytes #define SIC_ADDR_REG 0x1E8 /* 1b4~1b5, 2 bytes */
#define SIC_DATA_REG 0x1EC // 1b0~1b3 #define SIC_DATA_REG 0x1EC /* 1b0~1b3 */
#else #else
#define SIC_CMD_READY 0 #define SIC_CMD_READY 0
#define SIC_CMD_WRITE 1 #define SIC_CMD_WRITE 1
#define SIC_CMD_READ 2 #define SIC_CMD_READ 2
#define SIC_CMD_REG 0x1EB // 1byte #define SIC_CMD_REG 0x1EB /* 1byte */
#define SIC_ADDR_REG 0x1E8 // 1b9~1ba, 2 bytes #define SIC_ADDR_REG 0x1E8 /* 1b9~1ba, 2 bytes */
#define SIC_DATA_REG 0x1EC // 1bc~1bf #define SIC_DATA_REG 0x1EC /* 1bc~1bf */
#endif #endif
#if(SIC_ENABLE == 1) #if(SIC_ENABLE == 1)
void SIC_Init(IN struct adapter *Adapter); void SIC_Init(IN struct adapter *Adapter);
#endif #endif
#endif // __INC_HAL8192CPHYCFG_H #endif /* __INC_HAL8192CPHYCFG_H */

488
include/Hal8188EPhyReg.h
View file

@ -20,20 +20,20 @@
#ifndef __INC_HAL8188EPHYREG_H__ #ifndef __INC_HAL8188EPHYREG_H__
#define __INC_HAL8188EPHYREG_H__ #define __INC_HAL8188EPHYREG_H__
/*--------------------------Define Parameters-------------------------------*/ /*--------------------------Define Parameters-------------------------------*/
// /* */
// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */
// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
// 3. RF register 0x00-2E /* 3. RF register 0x00-2E */
// 4. Bit Mask for BB/RF register /* 4. Bit Mask for BB/RF register */
// 5. Other defintion for BB/RF R/W /* 5. Other defintion for BB/RF R/W */
// /* */
// /* */
// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */
// 1. Page1(0x100) /* 1. Page1(0x100) */
// /* */
#define rPMAC_Reset 0x100 #define rPMAC_Reset 0x100
#define rPMAC_TxStart 0x104 #define rPMAC_TxStart 0x104
#define rPMAC_TxLegacySIG 0x108 #define rPMAC_TxLegacySIG 0x108
@ -62,27 +62,27 @@
#define rPMAC_CCKCRxRC32OK 0x188 #define rPMAC_CCKCRxRC32OK 0x188
#define rPMAC_TxStatus 0x18c #define rPMAC_TxStatus 0x18c
// /* */
// 2. Page2(0x200) /* 2. Page2(0x200) */
// /* */
// The following two definition are only used for USB interface. /* The following two definition are only used for USB interface. */
#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address. #define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */
#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data. #define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */
// /* */
// 3. Page8(0x800) /* 3. Page8(0x800) */
// /* */
#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */
#define rFPGA0_TxInfo 0x804 // Status report?? #define rFPGA0_TxInfo 0x804 /* Status report?? */
#define rFPGA0_PSDFunction 0x808 #define rFPGA0_PSDFunction 0x808
#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
#define rFPGA0_RFTiming1 0x810 // Useless now #define rFPGA0_RFTiming1 0x810 /* Useless now */
#define rFPGA0_RFTiming2 0x814 #define rFPGA0_RFTiming2 0x814
#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
#define rFPGA0_XA_HSSIParameter2 0x824 #define rFPGA0_XA_HSSIParameter2 0x824
#define rFPGA0_XB_HSSIParameter1 0x828 #define rFPGA0_XB_HSSIParameter1 0x828
#define rFPGA0_XB_HSSIParameter2 0x82c #define rFPGA0_XB_HSSIParameter2 0x82c
@ -90,76 +90,76 @@
#define rFPGA0_XA_LSSIParameter 0x840 #define rFPGA0_XA_LSSIParameter 0x840
#define rFPGA0_XB_LSSIParameter 0x844 #define rFPGA0_XB_LSSIParameter 0x844
#define rFPGA0_RFWakeUpParameter 0x850 // Useless now #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */
#define rFPGA0_RFSleepUpParameter 0x854 #define rFPGA0_RFSleepUpParameter 0x854
#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */
#define rFPGA0_XCD_SwitchControl 0x85c #define rFPGA0_XCD_SwitchControl 0x85c
#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */
#define rFPGA0_XB_RFInterfaceOE 0x864 #define rFPGA0_XB_RFInterfaceOE 0x864
#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */
#define rFPGA0_XCD_RFInterfaceSW 0x874 #define rFPGA0_XCD_RFInterfaceSW 0x874
#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */
#define rFPGA0_XCD_RFParameter 0x87c #define rFPGA0_XCD_RFParameter 0x87c
#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */
#define rFPGA0_AnalogParameter2 0x884 #define rFPGA0_AnalogParameter2 0x884
#define rFPGA0_AnalogParameter3 0x888 #define rFPGA0_AnalogParameter3 0x888
#define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy #define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */
#define rFPGA0_AnalogParameter4 0x88c #define rFPGA0_AnalogParameter4 0x88c
#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */
#define rFPGA0_XB_LSSIReadBack 0x8a4 #define rFPGA0_XB_LSSIReadBack 0x8a4
#define rFPGA0_XC_LSSIReadBack 0x8a8 #define rFPGA0_XC_LSSIReadBack 0x8a8
#define rFPGA0_XD_LSSIReadBack 0x8ac #define rFPGA0_XD_LSSIReadBack 0x8ac
#define rFPGA0_PSDReport 0x8b4 // Useless now #define rFPGA0_PSDReport 0x8b4 /* Useless now */
#define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */
#define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */
#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now // RF Interface Readback Value */
#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */
// /* */
// 4. Page9(0x900) /* 4. Page9(0x900) */
// /* */
#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC // RF BW Setting?? */
#define rFPGA1_TxBlock 0x904 // Useless now #define rFPGA1_TxBlock 0x904 /* Useless now */
#define rFPGA1_DebugSelect 0x908 // Useless now #define rFPGA1_DebugSelect 0x908 /* Useless now */
#define rFPGA1_TxInfo 0x90c // Useless now // Status report?? #define rFPGA1_TxInfo 0x90c /* Useless now // Status report?? */
// /* */
// 5. PageA(0xA00) /* 5. PageA(0xA00) */
// /* */
// Set Control channel to upper or lower. These settings are required only for 40MHz /* Set Control channel to upper or lower. These settings are required only for 40MHz */
#define rCCK0_System 0xa00 #define rCCK0_System 0xa00
#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI #define rCCK0_AFESetting 0xa04 /* Disable init gain now // Select RX path by RSSI */
#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain #define rCCK0_CCA 0xa08 /* Disable init gain now // Init gain */
#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series #define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
#define rCCK0_RxAGC2 0xa10 //AGC & DAGC #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */
#define rCCK0_RxHP 0xa14 #define rCCK0_RxHP 0xa14
#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold #define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */
#define rCCK0_DSPParameter2 0xa1c //SQ threshold #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
#define rCCK0_TxFilter1 0xa20 #define rCCK0_TxFilter1 0xa20
#define rCCK0_TxFilter2 0xa24 #define rCCK0_TxFilter2 0xa24
#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */
#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */
#define rCCK0_TRSSIReport 0xa50 #define rCCK0_TRSSIReport 0xa50
#define rCCK0_RxReport 0xa54 //0xa57 #define rCCK0_RxReport 0xa54 /* 0xa57 */
#define rCCK0_FACounterLower 0xa5c //0xa5b #define rCCK0_FACounterLower 0xa5c /* 0xa5b */
#define rCCK0_FACounterUpper 0xa58 //0xa5c #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */
// /* */
// PageB(0xB00) /* PageB(0xB00) */
// /* */
#define rPdp_AntA 0xb00 #define rPdp_AntA 0xb00
#define rPdp_AntA_4 0xb04 #define rPdp_AntA_4 0xb04
#define rConfig_Pmpd_AntA 0xb28 #define rConfig_Pmpd_AntA 0xb28
@ -172,17 +172,17 @@
// /* */
// 6. PageC(0xC00) /* 6. PageC(0xC00) */
// /* */
#define rOFDM0_LSTF 0xc00 #define rOFDM0_LSTF 0xc00
#define rOFDM0_TRxPathEnable 0xc04 #define rOFDM0_TRxPathEnable 0xc04
#define rOFDM0_TRMuxPar 0xc08 #define rOFDM0_TRMuxPar 0xc08
#define rOFDM0_TRSWIsolation 0xc0c #define rOFDM0_TRSWIsolation 0xc0c
#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */
#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */
#define rOFDM0_XBRxAFE 0xc18 #define rOFDM0_XBRxAFE 0xc18
#define rOFDM0_XBRxIQImbalance 0xc1c #define rOFDM0_XBRxIQImbalance 0xc1c
#define rOFDM0_XCRxAFE 0xc20 #define rOFDM0_XCRxAFE 0xc20
@ -190,17 +190,17 @@
#define rOFDM0_XDRxAFE 0xc28 #define rOFDM0_XDRxAFE 0xc28
#define rOFDM0_XDRxIQImbalance 0xc2c #define rOFDM0_XDRxIQImbalance 0xc2c
#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain #define rOFDM0_RxDetector1 0xc30 /* PD,BW & SBD // DM tune init gain */
#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */
#define rOFDM0_RxDetector3 0xc38 //Frame Sync. #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */
#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */
#define rOFDM0_RxDSP 0xc40 //Rx Sync Path #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */
#define rOFDM0_ECCAThreshold 0xc4c // energy CCA #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
#define rOFDM0_XAAGCCore1 0xc50 // DIG #define rOFDM0_XAAGCCore1 0xc50 /* DIG */
#define rOFDM0_XAAGCCore2 0xc54 #define rOFDM0_XAAGCCore2 0xc54
#define rOFDM0_XBAGCCore1 0xc58 #define rOFDM0_XBAGCCore1 0xc58
#define rOFDM0_XBAGCCore2 0xc5c #define rOFDM0_XBAGCCore2 0xc5c
@ -214,7 +214,7 @@
#define rOFDM0_AGCRSSITable 0xc78 #define rOFDM0_AGCRSSITable 0xc78
#define rOFDM0_HTSTFAGC 0xc7c #define rOFDM0_HTSTFAGC 0xc7c
#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */
#define rOFDM0_XATxAFE 0xc84 #define rOFDM0_XATxAFE 0xc84
#define rOFDM0_XBTxIQImbalance 0xc88 #define rOFDM0_XBTxIQImbalance 0xc88
#define rOFDM0_XBTxAFE 0xc8c #define rOFDM0_XBTxAFE 0xc8c
@ -236,13 +236,13 @@
#define rOFDM0_DFSReport 0xcf4 #define rOFDM0_DFSReport 0xcf4
// /* */
// 7. PageD(0xD00) /* 7. PageD(0xD00) */
// /* */
#define rOFDM1_LSTF 0xd00 #define rOFDM1_LSTF 0xd00
#define rOFDM1_TRxPathEnable 0xd04 #define rOFDM1_TRxPathEnable 0xd04
#define rOFDM1_CFO 0xd08 // No setting now #define rOFDM1_CFO 0xd08 /* No setting now */
#define rOFDM1_CSI1 0xd10 #define rOFDM1_CSI1 0xd10
#define rOFDM1_SBD 0xd14 #define rOFDM1_SBD 0xd14
#define rOFDM1_CSI2 0xd18 #define rOFDM1_CSI2 0xd18
@ -254,11 +254,11 @@
#define rOFDM1_PseudoNoiseStateCD 0xd54 #define rOFDM1_PseudoNoiseStateCD 0xd54
#define rOFDM1_RxPseudoNoiseWgt 0xd58 #define rOFDM1_RxPseudoNoiseWgt 0xd58
#define rOFDM_PHYCounter1 0xda0 //cca, parity fail #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */
#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */
#define rOFDM_PHYCounter3 0xda8 //MCS not support #define rOFDM_PHYCounter3 0xda8 /* MCS not support */
#define rOFDM_ShortCFOAB 0xdac // No setting now #define rOFDM_ShortCFOAB 0xdac /* No setting now */
#define rOFDM_ShortCFOCD 0xdb0 #define rOFDM_ShortCFOCD 0xdb0
#define rOFDM_LongCFOAB 0xdb4 #define rOFDM_LongCFOAB 0xdb4
#define rOFDM_LongCFOCD 0xdb8 #define rOFDM_LongCFOCD 0xdb8
@ -273,9 +273,9 @@
#define rOFDM_SIGReport 0xddc #define rOFDM_SIGReport 0xddc
// /* */
// 8. PageE(0xE00) /* 8. PageE(0xE00) */
// /* */
#define rTxAGC_A_Rate18_06 0xe00 #define rTxAGC_A_Rate18_06 0xe00
#define rTxAGC_A_Rate54_24 0xe04 #define rTxAGC_A_Rate54_24 0xe04
#define rTxAGC_A_CCK1_Mcs32 0xe08 #define rTxAGC_A_CCK1_Mcs32 0xe08
@ -342,108 +342,108 @@
#define rSleep 0xee0 #define rSleep 0xee0
#define rPMPD_ANAEN 0xeec #define rPMPD_ANAEN 0xeec
// /* */
// 7. RF Register 0x00-0x2E (RF 8256) /* 7. RF Register 0x00-0x2E (RF 8256) */
// RF-0222D 0x00-3F /* RF-0222D 0x00-3F */
// /* */
//Zebra1 /* Zebra1 */
#define rZebra1_HSSIEnable 0x0 // Useless now #define rZebra1_HSSIEnable 0x0 /* Useless now */
#define rZebra1_TRxEnable1 0x1 #define rZebra1_TRxEnable1 0x1
#define rZebra1_TRxEnable2 0x2 #define rZebra1_TRxEnable2 0x2
#define rZebra1_AGC 0x4 #define rZebra1_AGC 0x4
#define rZebra1_ChargePump 0x5 #define rZebra1_ChargePump 0x5
#define rZebra1_Channel 0x7 // RF channel switch #define rZebra1_Channel 0x7 /* RF channel switch */
//#endif /* endif */
#define rZebra1_TxGain 0x8 // Useless now #define rZebra1_TxGain 0x8 /* Useless now */
#define rZebra1_TxLPF 0x9 #define rZebra1_TxLPF 0x9
#define rZebra1_RxLPF 0xb #define rZebra1_RxLPF 0xb
#define rZebra1_RxHPFCorner 0xc #define rZebra1_RxHPFCorner 0xc
//Zebra4 /* Zebra4 */
#define rGlobalCtrl 0 // Useless now #define rGlobalCtrl 0 /* Useless now */
#define rRTL8256_TxLPF 19 #define rRTL8256_TxLPF 19
#define rRTL8256_RxLPF 11 #define rRTL8256_RxLPF 11
//RTL8258 /* RTL8258 */
#define rRTL8258_TxLPF 0x11 // Useless now #define rRTL8258_TxLPF 0x11 /* Useless now */
#define rRTL8258_RxLPF 0x13 #define rRTL8258_RxLPF 0x13
#define rRTL8258_RSSILPF 0xa #define rRTL8258_RSSILPF 0xa
// /* */
// RL6052 Register definition /* RL6052 Register definition */
// /* */
#define RF_AC 0x00 // #define RF_AC 0x00 /* */
#define RF_IQADJ_G1 0x01 // #define RF_IQADJ_G1 0x01 /* */
#define RF_IQADJ_G2 0x02 // #define RF_IQADJ_G2 0x02 /* */
#define RF_POW_TRSW 0x05 // #define RF_POW_TRSW 0x05 /* */
#define RF_GAIN_RX 0x06 // #define RF_GAIN_RX 0x06 /* */
#define RF_GAIN_TX 0x07 // #define RF_GAIN_TX 0x07 /* */
#define RF_TXM_IDAC 0x08 // #define RF_TXM_IDAC 0x08 /* */
#define RF_IPA_G 0x09 // #define RF_IPA_G 0x09 /* */
#define RF_TXBIAS_G 0x0A #define RF_TXBIAS_G 0x0A
#define RF_TXPA_AG 0x0B #define RF_TXPA_AG 0x0B
#define RF_IPA_A 0x0C // #define RF_IPA_A 0x0C /* */
#define RF_TXBIAS_A 0x0D #define RF_TXBIAS_A 0x0D
#define RF_BS_PA_APSET_G9_G11 0x0E #define RF_BS_PA_APSET_G9_G11 0x0E
#define RF_BS_IQGEN 0x0F // #define RF_BS_IQGEN 0x0F /* */
#define RF_MODE1 0x10 // #define RF_MODE1 0x10 /* */
#define RF_MODE2 0x11 // #define RF_MODE2 0x11 /* */
#define RF_RX_AGC_HP 0x12 // #define RF_RX_AGC_HP 0x12 /* */
#define RF_TX_AGC 0x13 // #define RF_TX_AGC 0x13 /* */
#define RF_BIAS 0x14 // #define RF_BIAS 0x14 /* */
#define RF_IPA 0x15 // #define RF_IPA 0x15 /* */
#define RF_TXBIAS 0x16 #define RF_TXBIAS 0x16
#define RF_POW_ABILITY 0x17 // #define RF_POW_ABILITY 0x17 /* */
#define RF_CHNLBW 0x18 // RF channel and BW switch #define RF_CHNLBW 0x18 /* RF channel and BW switch */
#define RF_TOP 0x19 // #define RF_TOP 0x19 /* */
#define RF_RX_G1 0x1A // #define RF_RX_G1 0x1A /* */
#define RF_RX_G2 0x1B // #define RF_RX_G2 0x1B /* */
#define RF_RX_BB2 0x1C // #define RF_RX_BB2 0x1C /* */
#define RF_RX_BB1 0x1D // #define RF_RX_BB1 0x1D /* */
#define RF_RCK1 0x1E // #define RF_RCK1 0x1E /* */
#define RF_RCK2 0x1F // #define RF_RCK2 0x1F /* */
#define RF_TX_G1 0x20 // #define RF_TX_G1 0x20 /* */
#define RF_TX_G2 0x21 // #define RF_TX_G2 0x21 /* */
#define RF_TX_G3 0x22 // #define RF_TX_G3 0x22 /* */
#define RF_TX_BB1 0x23 // #define RF_TX_BB1 0x23 /* */
//#if HARDWARE_TYPE_IS_RTL8192D == 1 /* if HARDWARE_TYPE_IS_RTL8192D == 1 */
#define RF_T_METER_92D 0x42 // #define RF_T_METER_92D 0x42 /* */
//#else /* else */
#define RF_T_METER_88E 0x42 // #define RF_T_METER_88E 0x42 /* */
#define RF_T_METER 0x24 // #define RF_T_METER 0x24 /* */
//#endif /* endif */
#define RF_SYN_G1 0x25 // RF TX Power control #define RF_SYN_G1 0x25 /* RF TX Power control */
#define RF_SYN_G2 0x26 // RF TX Power control #define RF_SYN_G2 0x26 /* RF TX Power control */
#define RF_SYN_G3 0x27 // RF TX Power control #define RF_SYN_G3 0x27 /* RF TX Power control */
#define RF_SYN_G4 0x28 // RF TX Power control #define RF_SYN_G4 0x28 /* RF TX Power control */
#define RF_SYN_G5 0x29 // RF TX Power control #define RF_SYN_G5 0x29 /* RF TX Power control */
#define RF_SYN_G6 0x2A // RF TX Power control #define RF_SYN_G6 0x2A /* RF TX Power control */
#define RF_SYN_G7 0x2B // RF TX Power control #define RF_SYN_G7 0x2B /* RF TX Power control */
#define RF_SYN_G8 0x2C // RF TX Power control #define RF_SYN_G8 0x2C /* RF TX Power control */
#define RF_RCK_OS 0x30 // RF TX PA control #define RF_RCK_OS 0x30 /* RF TX PA control */
#define RF_TXPA_G1 0x31 // RF TX PA control #define RF_TXPA_G1 0x31 /* RF TX PA control */
#define RF_TXPA_G2 0x32 // RF TX PA control #define RF_TXPA_G2 0x32 /* RF TX PA control */
#define RF_TXPA_G3 0x33 // RF TX PA control #define RF_TXPA_G3 0x33 /* RF TX PA control */
#define RF_TX_BIAS_A 0x35 #define RF_TX_BIAS_A 0x35
#define RF_TX_BIAS_D 0x36 #define RF_TX_BIAS_D 0x36
#define RF_LOBF_9 0x38 #define RF_LOBF_9 0x38
#define RF_RXRF_A3 0x3C // #define RF_RXRF_A3 0x3C /* */
#define RF_TRSW 0x3F #define RF_TRSW 0x3F
#define RF_TXRF_A2 0x41 #define RF_TXRF_A2 0x41
@ -453,11 +453,11 @@
#define RF_WE_LUT 0xEF #define RF_WE_LUT 0xEF
// /* */
//Bit Mask /* Bit Mask */
// /* */
// 1. Page1(0x100) /* 1. Page1(0x100) */
#define bBBResetB 0x100 // Useless now? #define bBBResetB 0x100 /* Useless now? */
#define bGlobalResetB 0x200 #define bGlobalResetB 0x200
#define bOFDMTxStart 0x4 #define bOFDMTxStart 0x4
#define bCCKTxStart 0x8 #define bCCKTxStart 0x8
@ -504,36 +504,36 @@
#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
// 2. Page8(0x800) /* 2. Page8(0x800) */
#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */
#define bJapanMode 0x2 #define bJapanMode 0x2
#define bCCKTxSC 0x30 #define bCCKTxSC 0x30
#define bCCKEn 0x1000000 #define bCCKEn 0x1000000
#define bOFDMEn 0x2000000 #define bOFDMEn 0x2000000
#define bOFDMRxADCPhase 0x10000 // Useless now #define bOFDMRxADCPhase 0x10000 /* Useless now */
#define bOFDMTxDACPhase 0x40000 #define bOFDMTxDACPhase 0x40000
#define bXATxAGC 0x3f #define bXATxAGC 0x3f
#define bAntennaSelect 0x0300 #define bAntennaSelect 0x0300
#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */
#define bXCTxAGC 0xf000 #define bXCTxAGC 0xf000
#define bXDTxAGC 0xf0000 #define bXDTxAGC 0xf0000
#define bPAStart 0xf0000000 // Useless now #define bPAStart 0xf0000000 /* Useless now */
#define bTRStart 0x00f00000 #define bTRStart 0x00f00000
#define bRFStart 0x0000f000 #define bRFStart 0x0000f000
#define bBBStart 0x000000f0 #define bBBStart 0x000000f0
#define bBBCCKStart 0x0000000f #define bBBCCKStart 0x0000000f
#define bPAEnd 0xf //Reg0x814 #define bPAEnd 0xf /* Reg0x814 */
#define bTREnd 0x0f000000 #define bTREnd 0x0f000000
#define bRFEnd 0x000f0000 #define bRFEnd 0x000f0000
#define bCCAMask 0x000000f0 //T2R #define bCCAMask 0x000000f0 /* T2R */
#define bR2RCCAMask 0x00000f00 #define bR2RCCAMask 0x00000f00
#define bHSSI_R2TDelay 0xf8000000 #define bHSSI_R2TDelay 0xf8000000
#define bHSSI_T2RDelay 0xf80000 #define bHSSI_T2RDelay 0xf80000
#define bContTxHSSI 0x400 //chane gain at continue Tx #define bContTxHSSI 0x400 /* chane gain at continue Tx */
#define bIGFromCCK 0x200 #define bIGFromCCK 0x200
#define bAGCAddress 0x3f #define bAGCAddress 0x3f
#define bRxHPTx 0x7000 #define bRxHPTx 0x7000
@ -542,11 +542,11 @@
#define bAGCTxCode 0xc00000 #define bAGCTxCode 0xc00000
#define bAGCRxCode 0x300000 #define bAGCRxCode 0x300000
#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
#define b3WireAddressLength 0x400 #define b3WireAddressLength 0x400
#define b3WireRFPowerDown 0x1 // Useless now #define b3WireRFPowerDown 0x1 /* Useless now */
//#define bHWSISelect 0x8 /* define bHWSISelect 0x8 */
#define b5GPAPEPolarity 0x40000000 #define b5GPAPEPolarity 0x40000000
#define b2GPAPEPolarity 0x80000000 #define b2GPAPEPolarity 0x80000000
#define bRFSW_TxDefaultAnt 0x3 #define bRFSW_TxDefaultAnt 0x3
@ -559,9 +559,9 @@
#define bRFSI_3WireRW 0x8 #define bRFSI_3WireRW 0x8
#define bRFSI_3Wire 0xf #define bRFSI_3Wire 0xf
#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
#define bRFSI_TRSW 0x20 // Useless now #define bRFSI_TRSW 0x20 /* Useless now */
#define bRFSI_TRSWB 0x40 #define bRFSI_TRSWB 0x40
#define bRFSI_ANTSW 0x100 #define bRFSI_ANTSW 0x100
#define bRFSI_ANTSWB 0x200 #define bRFSI_ANTSWB 0x200
@ -585,14 +585,14 @@
#define bLSIG_Parity 0x20 #define bLSIG_Parity 0x20
#define bCCKRxPhase 0x4 #define bCCKRxPhase 0x4
#define bLSSIReadAddress 0x7f800000 // T65 RF #define bLSSIReadAddress 0x7f800000 /* T65 RF */
#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */
#define bLSSIReadBackData 0xfffff // T65 RF #define bLSSIReadBackData 0xfffff /* T65 RF */
#define bLSSIReadOKFlag 0x1000 // Useless now #define bLSSIReadOKFlag 0x1000 /* Useless now */
#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */
#define bRegulator0Standby 0x1 #define bRegulator0Standby 0x1
#define bRegulatorPLLStandby 0x2 #define bRegulatorPLLStandby 0x2
#define bRegulator1Standby 0x4 #define bRegulator1Standby 0x4
@ -606,17 +606,17 @@
#define bDA6DebugMode 0x20000 #define bDA6DebugMode 0x20000
#define bDA6Swing 0x380000 #define bDA6Swing 0x380000
#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ #define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
#define b80MClkDelay 0x18000000 // Useless #define b80MClkDelay 0x18000000 /* Useless */
#define bAFEWatchDogEnable 0x20000000 #define bAFEWatchDogEnable 0x20000000
#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap #define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
#define bXtalCap23 0x3 #define bXtalCap23 0x3
#define bXtalCap92x 0x0f000000 #define bXtalCap92x 0x0f000000
#define bXtalCap 0x0f000000 #define bXtalCap 0x0f000000
#define bIntDifClkEnable 0x400 // Useless #define bIntDifClkEnable 0x400 /* Useless */
#define bExtSigClkEnable 0x800 #define bExtSigClkEnable 0x800
#define bBandgapMbiasPowerUp 0x10000 #define bBandgapMbiasPowerUp 0x10000
#define bAD11SHGain 0xc0000 #define bAD11SHGain 0xc0000
@ -650,12 +650,12 @@
#define bPSDSineToneScale 0x7f000000 #define bPSDSineToneScale 0x7f000000
#define bPSDReport 0xffff #define bPSDReport 0xffff
// 3. Page9(0x900) /* 3. Page9(0x900) */
#define bOFDMTxSC 0x30000000 // Useless #define bOFDMTxSC 0x30000000 /* Useless */
#define bCCKTxOn 0x1 #define bCCKTxOn 0x1
#define bOFDMTxOn 0x2 #define bOFDMTxOn 0x2
#define bDebugPage 0xfff //reset debug page and also HWord, LWord #define bDebugPage 0xfff /* reset debug page and also HWord, LWord */
#define bDebugItem 0xff //reset debug page and LWord #define bDebugItem 0xff /* reset debug page and LWord */
#define bAntL 0x10 #define bAntL 0x10
#define bAntNonHT 0x100 #define bAntNonHT 0x100
#define bAntHT1 0x1000 #define bAntHT1 0x1000
@ -663,14 +663,14 @@
#define bAntHT1S1 0x100000 #define bAntHT1S1 0x100000
#define bAntNonHTS1 0x1000000 #define bAntNonHTS1 0x1000000
// 4. PageA(0xA00) /* 4. PageA(0xA00) */
#define bCCKBBMode 0x3 // Useless #define bCCKBBMode 0x3 /* Useless */
#define bCCKTxPowerSaving 0x80 #define bCCKTxPowerSaving 0x80
#define bCCKRxPowerSaving 0x40 #define bCCKRxPowerSaving 0x40
#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */
#define bCCKScramble 0x8 // Useless #define bCCKScramble 0x8 /* Useless */
#define bCCKAntDiversity 0x8000 #define bCCKAntDiversity 0x8000
#define bCCKCarrierRecovery 0x4000 #define bCCKCarrierRecovery 0x4000
#define bCCKTxRate 0x3000 #define bCCKTxRate 0x3000
@ -686,7 +686,7 @@
#define bCCKBistMode 0x80000000 #define bCCKBistMode 0x80000000
#define bCCKCCAMask 0x40000000 #define bCCKCCAMask 0x40000000
#define bCCKTxDACPhase 0x4 #define bCCKTxDACPhase 0x4
#define bCCKRxADCPhase 0x20000000 //r_rx_clk #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
#define bCCKr_cp_mode0 0x0100 #define bCCKr_cp_mode0 0x0100
#define bCCKTxDCOffset 0xf0 #define bCCKTxDCOffset 0xf0
#define bCCKRxDCOffset 0xf #define bCCKRxDCOffset 0xf
@ -700,12 +700,12 @@
#define bCCKRxIG 0x7f00 #define bCCKRxIG 0x7f00
#define bCCKLNAPolarity 0x800000 #define bCCKLNAPolarity 0x800000
#define bCCKRx1stGain 0x7f0000 #define bCCKRx1stGain 0x7f0000
#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */
#define bCCKRxAGCSatLevel 0x1f000000 #define bCCKRxAGCSatLevel 0x1f000000
#define bCCKRxAGCSatCount 0xe0 #define bCCKRxAGCSatCount 0xe0
#define bCCKRxRFSettle 0x1f //AGCsamp_dly #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */
#define bCCKFixedRxAGC 0x8000 #define bCCKFixedRxAGC 0x8000
//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 /* define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 */
#define bCCKAntennaPolarity 0x2000 #define bCCKAntennaPolarity 0x2000
#define bCCKTxFilterType 0x0c00 #define bCCKTxFilterType 0x0c00
#define bCCKRxAGCReportType 0x0300 #define bCCKRxAGCReportType 0x0300
@ -744,8 +744,8 @@
#define bCCKDefaultRxPath 0xc000000 #define bCCKDefaultRxPath 0xc000000
#define bCCKOptionRxPath 0x3000000 #define bCCKOptionRxPath 0x3000000
// 5. PageC(0xC00) /* 5. PageC(0xC00) */
#define bNumOfSTF 0x3 // Useless #define bNumOfSTF 0x3 /* Useless */
#define bShift_L 0xc0 #define bShift_L 0xc0
#define bGI_TH 0xc #define bGI_TH 0xc
#define bRxPathA 0x1 #define bRxPathA 0x1
@ -846,8 +846,8 @@
#define bRxHP_BBP1 0x7000 #define bRxHP_BBP1 0x7000
#define bRxHP_BBP2 0x70000 #define bRxHP_BBP2 0x70000
#define bRxHP_BBP3 0x700000 #define bRxHP_BBP3 0x700000
#define bRSSI_H 0x7f0000 //the threshold for high power #define bRSSI_H 0x7f0000 /* the threshold for high power */
#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity #define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */
#define bRxSettle_TRSW 0x7 #define bRxSettle_TRSW 0x7
#define bRxSettle_LNA 0x38 #define bRxSettle_LNA 0x38
#define bRxSettle_RSSI 0x1c0 #define bRxSettle_RSSI 0x1c0
@ -881,7 +881,7 @@
#define bRxPD_Delay_TH1 0x38 #define bRxPD_Delay_TH1 0x38
#define bRxPD_Delay_TH2 0x1c0 #define bRxPD_Delay_TH2 0x1c0
#define bRxPD_DC_COUNT_MAX 0x600 #define bRxPD_DC_COUNT_MAX 0x600
//#define bRxMF_Hold 0x3800 /* define bRxMF_Hold 0x3800 */
#define bRxPD_Delay_TH 0x8000 #define bRxPD_Delay_TH 0x8000
#define bRxProcess_Delay 0xf0000 #define bRxProcess_Delay 0xf0000
#define bRxSearchrange_GI2_Early 0x700000 #define bRxSearchrange_GI2_Early 0x700000
@ -902,8 +902,8 @@
#define bTRSWIsolation_D 0x7f000000 #define bTRSWIsolation_D 0x7f000000
#define bExtLNAGain 0x7c00 #define bExtLNAGain 0x7c00
// 6. PageE(0xE00) /* 6. PageE(0xE00) */
#define bSTBCEn 0x4 // Useless #define bSTBCEn 0x4 /* Useless */
#define bAntennaMapping 0x10 #define bAntennaMapping 0x10
#define bNss 0x20 #define bNss 0x20
#define bCFOAntSumD 0x200 #define bCFOAntSumD 0x200
@ -912,12 +912,12 @@
#define bOFDMContinueTx 0x10000000 #define bOFDMContinueTx 0x10000000
#define bOFDMSingleCarrier 0x20000000 #define bOFDMSingleCarrier 0x20000000
#define bOFDMSingleTone 0x40000000 #define bOFDMSingleTone 0x40000000
//#define bRxPath1 0x01 /* define bRxPath1 0x01 */
//#define bRxPath2 0x02 /* define bRxPath2 0x02 */
//#define bRxPath3 0x04 /* define bRxPath3 0x04 */
//#define bRxPath4 0x08 /* define bRxPath4 0x08 */
//#define bTxPath1 0x10 /* define bTxPath1 0x10 */
//#define bTxPath2 0x20 /* define bTxPath2 0x20 */
#define bHTDetect 0x100 #define bHTDetect 0x100
#define bCFOEn 0x10000 #define bCFOEn 0x10000
#define bCFOValue 0xfff00000 #define bCFOValue 0xfff00000
@ -930,8 +930,8 @@
#define bCounter_MCSNoSupport 0xffff #define bCounter_MCSNoSupport 0xffff
#define bCounter_FastSync 0xffff #define bCounter_FastSync 0xffff
#define bShortCFO 0xfff #define bShortCFO 0xfff
#define bShortCFOTLength 12 //total #define bShortCFOTLength 12 /* total */
#define bShortCFOFLength 11 //fraction #define bShortCFOFLength 11 /* fraction */
#define bLongCFO 0x7ff #define bLongCFO 0x7ff
#define bLongCFOTLength 11 #define bLongCFOTLength 11
#define bLongCFOFLength 11 #define bLongCFOFLength 11
@ -966,7 +966,7 @@
#define bPWDB 0xff00 #define bPWDB 0xff00
#define bSGIEN 0x10000 #define bSGIEN 0x10000
#define bSFactorQAM1 0xf // Useless #define bSFactorQAM1 0xf /* Useless */
#define bSFactorQAM2 0xf0 #define bSFactorQAM2 0xf0
#define bSFactorQAM3 0xf00 #define bSFactorQAM3 0xf00
#define bSFactorQAM4 0xf000 #define bSFactorQAM4 0xf000
@ -977,7 +977,7 @@
#define bSFactorQAM9 0xf0000000 #define bSFactorQAM9 0xf0000000
#define bCSIScheme 0x100000 #define bCSIScheme 0x100000
#define bNoiseLvlTopSet 0x3 // Useless #define bNoiseLvlTopSet 0x3 /* Useless */
#define bChSmooth 0x4 #define bChSmooth 0x4
#define bChSmoothCfg1 0x38 #define bChSmoothCfg1 0x38
#define bChSmoothCfg2 0x1c0 #define bChSmoothCfg2 0x1c0
@ -986,7 +986,7 @@
#define bMRCMode 0x800000 #define bMRCMode 0x800000
#define bTHEVMCfg 0x7000000 #define bTHEVMCfg 0x7000000
#define bLoopFitType 0x1 // Useless #define bLoopFitType 0x1 /* Useless */
#define bUpdCFO 0x40 #define bUpdCFO 0x40
#define bUpdCFOOffData 0x80 #define bUpdCFOOffData 0x80
#define bAdvUpdCFO 0x100 #define bAdvUpdCFO 0x100
@ -1002,8 +1002,8 @@
#define bUChCfg 0x7000000 #define bUChCfg 0x7000000
#define bUpdEqz 0x8000000 #define bUpdEqz 0x8000000
//Rx Pseduo noise /* Rx Pseduo noise */
#define bRxPesudoNoiseOn 0x20000000 // Useless #define bRxPesudoNoiseOn 0x20000000 /* Useless */
#define bRxPesudoNoise_A 0xff #define bRxPesudoNoise_A 0xff
#define bRxPesudoNoise_B 0xff00 #define bRxPesudoNoise_B 0xff00
#define bRxPesudoNoise_C 0xff0000 #define bRxPesudoNoise_C 0xff0000
@ -1013,9 +1013,9 @@
#define bPesudoNoiseState_C 0xffff #define bPesudoNoiseState_C 0xffff
#define bPesudoNoiseState_D 0xffff0000 #define bPesudoNoiseState_D 0xffff0000
//7. RF Register /* 7. RF Register */
//Zebra1 /* Zebra1 */
#define bZebra1_HSSIEnable 0x8 // Useless #define bZebra1_HSSIEnable 0x8 /* Useless */
#define bZebra1_TRxControl 0xc00 #define bZebra1_TRxControl 0xc00
#define bZebra1_TRxGainSetting 0x07f #define bZebra1_TRxGainSetting 0x07f
#define bZebra1_RxCorner 0xc00 #define bZebra1_RxCorner 0xc00
@ -1025,24 +1025,24 @@
#define bZebra1_TxLPFBW 0x400 #define bZebra1_TxLPFBW 0x400
#define bZebra1_RxLPFBW 0x600 #define bZebra1_RxLPFBW 0x600
//Zebra4 /* Zebra4 */
#define bRTL8256RegModeCtrl1 0x100 // Useless #define bRTL8256RegModeCtrl1 0x100 /* Useless */
#define bRTL8256RegModeCtrl0 0x40 #define bRTL8256RegModeCtrl0 0x40
#define bRTL8256_TxLPFBW 0x18 #define bRTL8256_TxLPFBW 0x18
#define bRTL8256_RxLPFBW 0x600 #define bRTL8256_RxLPFBW 0x600
//RTL8258 /* RTL8258 */
#define bRTL8258_TxLPFBW 0xc // Useless #define bRTL8258_TxLPFBW 0xc /* Useless */
#define bRTL8258_RxLPFBW 0xc00 #define bRTL8258_RxLPFBW 0xc00
#define bRTL8258_RSSILPFBW 0xc0 #define bRTL8258_RSSILPFBW 0xc0
// /* */
// Other Definition /* Other Definition */
// /* */
//byte endable for sb_write /* byte endable for sb_write */
#define bByte0 0x1 // Useless #define bByte0 0x1 /* Useless */
#define bByte1 0x2 #define bByte1 0x2
#define bByte2 0x4 #define bByte2 0x4
#define bByte3 0x8 #define bByte3 0x8
@ -1050,8 +1050,8 @@
#define bWord1 0xc #define bWord1 0xc
#define bDWord 0xf #define bDWord 0xf
//for PutRegsetting & GetRegSetting BitMask /* for PutRegsetting & GetRegSetting BitMask */
#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
#define bMaskByte1 0xff00 #define bMaskByte1 0xff00
#define bMaskByte2 0xff0000 #define bMaskByte2 0xff0000
#define bMaskByte3 0xff000000 #define bMaskByte3 0xff000000
@ -1063,44 +1063,44 @@
#define bMaskOFDM_D 0xffc00000 #define bMaskOFDM_D 0xffc00000
#define bMaskCCK 0x3f3f3f3f #define bMaskCCK 0x3f3f3f3f
//for PutRFRegsetting & GetRFRegSetting BitMask /* for PutRFRegsetting & GetRFRegSetting BitMask */
//#define bMask12Bits 0xfffff // RF Reg mask bits /* define bMask12Bits 0xfffff // RF Reg mask bits */
//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF /* define bMask20Bits 0xfffff // RF Reg mask bits T65 RF */
#define bRFRegOffsetMask 0xfffff #define bRFRegOffsetMask 0xfffff
#define bEnable 0x1 // Useless #define bEnable 0x1 /* Useless */
#define bDisable 0x0 #define bDisable 0x0
#define LeftAntenna 0x0 // Useless #define LeftAntenna 0x0 /* Useless */
#define RightAntenna 0x1 #define RightAntenna 0x1
#define tCheckTxStatus 500 //500ms // Useless #define tCheckTxStatus 500 /* 500ms // Useless */
#define tUpdateRxCounter 100 //100ms #define tUpdateRxCounter 100 /* 100ms */
#define rateCCK 0 // Useless #define rateCCK 0 /* Useless */
#define rateOFDM 1 #define rateOFDM 1
#define rateHT 2 #define rateHT 2
//define Register-End /* define Register-End */
#define bPMAC_End 0x1ff // Useless #define bPMAC_End 0x1ff /* Useless */
#define bFPGAPHY0_End 0x8ff #define bFPGAPHY0_End 0x8ff
#define bFPGAPHY1_End 0x9ff #define bFPGAPHY1_End 0x9ff
#define bCCKPHY0_End 0xaff #define bCCKPHY0_End 0xaff
#define bOFDMPHY0_End 0xcff #define bOFDMPHY0_End 0xcff
#define bOFDMPHY1_End 0xdff #define bOFDMPHY1_End 0xdff
//define max debug item in each debug page /* define max debug item in each debug page */
//#define bMaxItem_FPGA_PHY0 0x9 /* define bMaxItem_FPGA_PHY0 0x9 */
//#define bMaxItem_FPGA_PHY1 0x3 /* define bMaxItem_FPGA_PHY1 0x3 */
//#define bMaxItem_PHY_11B 0x16 /* define bMaxItem_PHY_11B 0x16 */
//#define bMaxItem_OFDM_PHY0 0x29 /* define bMaxItem_OFDM_PHY0 0x29 */
//#define bMaxItem_OFDM_PHY1 0x0 //#define bMaxItem_OFDM_PHY1 0x0
#define bPMACControl 0x0 // Useless #define bPMACControl 0x0 /* Useless */
#define bWMACControl 0x1 #define bWMACControl 0x1
#define bWNICControl 0x2 #define bWNICControl 0x2
#define PathA 0x0 // Useless #define PathA 0x0 /* Useless */
#define PathB 0x1 #define PathB 0x1
#define PathC 0x2 #define PathC 0x2
#define PathD 0x3 #define PathD 0x3

30
include/Hal8188EPwrSeq.h
View file

@ -60,7 +60,7 @@
#define RTL8188E_TRANS_CARDEMU_TO_ACT \ #define RTL8188E_TRANS_CARDEMU_TO_ACT \
/* format */ \ /* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0|BIT1, 0}, /* 0x02[1:0] = 0 reset BB*/ \ {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0|BIT1, 0}, /* 0x02[1:0] = 0 reset BB*/ \
{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */ \ {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */ \
@ -72,8 +72,8 @@
{0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*SDIO Driving*/ \ {0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*SDIO Driving*/ \
#define RTL8188E_TRANS_ACT_TO_CARDEMU \ #define RTL8188E_TRANS_ACT_TO_CARDEMU \
/* format */ \ /* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*LDO Sleep mode*/ \ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*LDO Sleep mode*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
@ -81,7 +81,7 @@
#define RTL8188E_TRANS_CARDEMU_TO_SUS \ #define RTL8188E_TRANS_CARDEMU_TO_SUS \
/* format */ \ /* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01enable WL suspend*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, BIT7}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, BIT7}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \
@ -92,14 +92,14 @@
#define RTL8188E_TRANS_SUS_TO_CARDEMU \ #define RTL8188E_TRANS_SUS_TO_CARDEMU \
/* format */ \ /* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \ #define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \ /* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */ \ {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \
@ -110,26 +110,26 @@
#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \ #define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \ /* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8188E_TRANS_CARDEMU_TO_PDN \ #define RTL8188E_TRANS_CARDEMU_TO_PDN \
/* format */ \ /* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
#define RTL8188E_TRANS_PDN_TO_CARDEMU \ #define RTL8188E_TRANS_PDN_TO_CARDEMU \
/* format */ \ /* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
//This is used by driver for LPSRadioOff Procedure, not for FW LPS Step /* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */
#define RTL8188E_TRANS_ACT_TO_LPS \ #define RTL8188E_TRANS_ACT_TO_LPS \
/* format */ \ /* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \ {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
@ -144,7 +144,7 @@
#define RTL8188E_TRANS_LPS_TO_ACT \ #define RTL8188E_TRANS_LPS_TO_ACT \
/* format */ \ /* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
@ -159,8 +159,8 @@
#define RTL8188E_TRANS_END \ #define RTL8188E_TRANS_END \
/* format */ \ /* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0},
extern struct wl_pwr_cfg rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]; extern struct wl_pwr_cfg rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS];
@ -173,4 +173,4 @@ extern struct wl_pwr_cfg rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS
extern struct wl_pwr_cfg rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS]; extern struct wl_pwr_cfg rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS];
extern struct wl_pwr_cfg rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]; extern struct wl_pwr_cfg rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS];
#endif //__HAL8188EPWRSEQ_H__ #endif /* __HAL8188EPWRSEQ_H__ */

187
include/Hal8192CPhyCfg.h
View file

@ -41,8 +41,8 @@
/*--------------------------Define Parameters-------------------------------*/ /*--------------------------Define Parameters-------------------------------*/
#define LOOP_LIMIT 5 #define LOOP_LIMIT 5
#define MAX_STALL_TIME 50 //us #define MAX_STALL_TIME 50 /* us */
#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80) #define AntennaDiversityValue 0x80 /* Adapter->bSoftwareAntennaDiversity ? 0x00:0x80) */
#define MAX_TXPWR_IDX_NMODE_92S 63 #define MAX_TXPWR_IDX_NMODE_92S 63
#define Reset_Cnt_Limit 3 #define Reset_Cnt_Limit 3
@ -77,21 +77,21 @@ typedef enum _HW90_BLOCK{
HW90_BLOCK_PHY0 = 1, HW90_BLOCK_PHY0 = 1,
HW90_BLOCK_PHY1 = 2, HW90_BLOCK_PHY1 = 2,
HW90_BLOCK_RF = 3, HW90_BLOCK_RF = 3,
HW90_BLOCK_MAXIMUM = 4, // Never use this HW90_BLOCK_MAXIMUM = 4, /* Never use this */
}HW90_BLOCK_E, *PHW90_BLOCK_E; }HW90_BLOCK_E, *PHW90_BLOCK_E;
typedef enum _RF_RADIO_PATH{ typedef enum _RF_RADIO_PATH{
RF_PATH_A = 0, //Radio Path A RF_PATH_A = 0, /* Radio Path A */
RF_PATH_B = 1, //Radio Path B RF_PATH_B = 1, /* Radio Path B */
RF_PATH_C = 2, //Radio Path C RF_PATH_C = 2, /* Radio Path C */
RF_PATH_D = 3, //Radio Path D RF_PATH_D = 3, /* Radio Path D */
//RF_PATH_MAX //Max RF number 90 support /* RF_PATH_MAX Max RF number 90 support */
}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E; }RF_RADIO_PATH_E, *PRF_RADIO_PATH_E;
#define RF_PATH_MAX 2 #define RF_PATH_MAX 2
#define CHANNEL_MAX_NUMBER 14 // 14 is the max channel number #define CHANNEL_MAX_NUMBER 14 /* 14 is the max channel number */
#define CHANNEL_GROUP_MAX 3 // ch1~3, ch4~9, ch10~14 total three groups #define CHANNEL_GROUP_MAX 3 /* ch1~3, ch4~9, ch10~14 total three groups */
typedef enum _WIRELESS_MODE { typedef enum _WIRELESS_MODE {
WIRELESS_MODE_UNKNOWN = 0x00, WIRELESS_MODE_UNKNOWN = 0x00,
@ -105,8 +105,8 @@ typedef enum _WIRELESS_MODE {
} WIRELESS_MODE; } WIRELESS_MODE;
typedef enum _BaseBand_Config_Type{ typedef enum _BaseBand_Config_Type{
BaseBand_Config_PHY_REG = 0, //Radio Path A BaseBand_Config_PHY_REG = 0, /* Radio Path A */
BaseBand_Config_AGC_TAB = 1, //Radio Path B BaseBand_Config_AGC_TAB = 1, /* Radio Path B */
}BaseBand_Config_Type, *PBaseBand_Config_Type; }BaseBand_Config_Type, *PBaseBand_Config_Type;
@ -123,70 +123,69 @@ typedef enum _PHY_Rate_Tx_Power_Offset_Area{
/* BB/RF related */ /* BB/RF related */
typedef enum _RF_TYPE_8190P{ typedef enum _RF_TYPE_8190P{
RF_TYPE_MIN, // 0 RF_TYPE_MIN, /* 0 */
RF_8225=1, // 1 11b/g RF for verification only RF_8225=1, /* 1 11b/g RF for verification only */
RF_8256=2, // 2 11b/g/n RF_8256=2, /* 2 11b/g/n */
RF_8258=3, // 3 11a/b/g/n RF RF_8258=3, /* 3 11a/b/g/n RF */
RF_6052=4, // 4 11b/g/n RF RF_6052=4, /* 4 11b/g/n RF */
//RF_6052=5, // 4 11b/g/n RF /* TODO: We should remove this psudo PHY RF after we get new RF. */
// TODO: We sholud remove this psudo PHY RF after we get new RF. RF_PSEUDO_11N=5, /* 5, It is a temporality RF. */
RF_PSEUDO_11N=5, // 5, It is a temporality RF.
}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E; }RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
typedef struct _BB_REGISTER_DEFINITION{ typedef struct _BB_REGISTER_DEFINITION{
u32 rfintfs; // set software control: u32 rfintfs; /* set software control: */
// 0x870~0x877[8 bytes] /* 0x870~0x877[8 bytes] */
u32 rfintfi; // readback data: u32 rfintfi; /* readback data: */
// 0x8e0~0x8e7[8 bytes] /* 0x8e0~0x8e7[8 bytes] */
u32 rfintfo; // output data: u32 rfintfo; /* output data: */
// 0x860~0x86f [16 bytes] /* 0x860~0x86f [16 bytes] */
u32 rfintfe; // output enable: u32 rfintfe; /* output enable: */
// 0x860~0x86f [16 bytes] /* 0x860~0x86f [16 bytes] */
u32 rf3wireOffset; // LSSI data: u32 rf3wireOffset; /* LSSI data: */
// 0x840~0x84f [16 bytes] /* 0x840~0x84f [16 bytes] */
u32 rfLSSI_Select; // BB Band Select: u32 rfLSSI_Select; /* BB Band Select: */
// 0x878~0x87f [8 bytes] /* 0x878~0x87f [8 bytes] */
u32 rfTxGainStage; // Tx gain stage: u32 rfTxGainStage; /* Tx gain stage: */
// 0x80c~0x80f [4 bytes] /* 0x80c~0x80f [4 bytes] */
u32 rfHSSIPara1; // wire parameter control1 : u32 rfHSSIPara1; /* wire parameter control1 : */
// 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] /* 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] */
u32 rfHSSIPara2; // wire parameter control2 : u32 rfHSSIPara2; /* wire parameter control2 : */
// 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] /* 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] */
u32 rfSwitchControl; //Tx Rx antenna control : u32 rfSwitchControl; /* Tx Rx antenna control : */
// 0x858~0x85f [16 bytes] /* 0x858~0x85f [16 bytes] */
u32 rfAGCControl1; //AGC parameter control1 : u32 rfAGCControl1; /* AGC parameter control1 : */
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] /* 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] */
u32 rfAGCControl2; //AGC parameter control2 : u32 rfAGCControl2; /* AGC parameter control2 : */
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] /* 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] */
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : u32 rfRxIQImbalance; /* OFDM Rx IQ imbalance matrix : */
// 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] /* 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] */
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : u32 rfRxAFE; /* Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : */
// 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] /* 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] */
u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */
// 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] /* 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] */
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type u32 rfTxAFE; /* Tx IQ DC Offset and Tx DFIR type */
// 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] /* 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] */
u32 rfLSSIReadBack; //LSSI RF readback data SI mode u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */
// 0x8a0~0x8af [16 bytes] /* 0x8a0~0x8af [16 bytes] */
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for Path A and B */
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T; }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
@ -220,9 +219,9 @@ typedef struct _R_ANTENNA_SELECT_CCK{
/*--------------------------Exported Function prototype---------------------*/ /*--------------------------Exported Function prototype---------------------*/
// /* */
// BB and RF register read/write /* BB and RF register read/write */
// /* */
u32 rtl8192c_PHY_QueryBBReg( IN struct adapter *Adapter, u32 rtl8192c_PHY_QueryBBReg( IN struct adapter *Adapter,
IN u32 RegAddr, IN u32 RegAddr,
IN u32 BitMask ); IN u32 BitMask );
@ -240,9 +239,9 @@ void rtl8192c_PHY_SetRFReg( IN struct adapter * Adapter,
IN u32 BitMask, IN u32 BitMask,
IN u32 Data ); IN u32 Data );
// /* */
// Initialization related function /* Initialization related function */
// /* */
/* MAC/BB/RF HAL config */ /* MAC/BB/RF HAL config */
int PHY_MACConfig8192C( IN struct adapter *Adapter ); int PHY_MACConfig8192C( IN struct adapter *Adapter );
int PHY_BBConfig8192C( IN struct adapter *Adapter ); int PHY_BBConfig8192C( IN struct adapter *Adapter );
@ -261,15 +260,15 @@ int rtl8192c_PHY_CheckBBAndRFOK( IN struct adapter * Adapter,
/* Read initi reg value for tx power setting. */ /* Read initi reg value for tx power setting. */
void rtl8192c_PHY_GetHWRegOriginalValue( IN struct adapter * Adapter ); void rtl8192c_PHY_GetHWRegOriginalValue( IN struct adapter * Adapter );
// /* */
// RF Power setting /* RF Power setting */
// /* */
//extern bool PHY_SetRFPowerState(IN struct adapter * Adapter, /* extern bool PHY_SetRFPowerState(IN struct adapter * Adapter, */
// IN RT_RF_POWER_STATE eRFPowerState); /* IN RT_RF_POWER_STATE eRFPowerState); */
// /* */
// BB TX Power R/W /* BB TX Power R/W */
// /* */
void PHY_GetTxPowerLevel8192C( IN struct adapter * Adapter, void PHY_GetTxPowerLevel8192C( IN struct adapter * Adapter,
OUT u32* powerlevel ); OUT u32* powerlevel );
void PHY_SetTxPowerLevel8192C( IN struct adapter * Adapter, void PHY_SetTxPowerLevel8192C( IN struct adapter * Adapter,
@ -277,48 +276,48 @@ void PHY_SetTxPowerLevel8192C( IN struct adapter * Adapter,
bool PHY_UpdateTxPowerDbm8192C( IN struct adapter *Adapter, bool PHY_UpdateTxPowerDbm8192C( IN struct adapter *Adapter,
IN int powerInDbm ); IN int powerInDbm );
// /* */
void void
PHY_ScanOperationBackup8192C(IN struct adapter *Adapter, PHY_ScanOperationBackup8192C(IN struct adapter *Adapter,
IN u8 Operation ); IN u8 Operation );
// /* */
// Switch bandwidth for 8192S /* Switch bandwidth for 8192S */
// /* */
//extern void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer ); /* extern void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer ); */
void PHY_SetBWMode8192C( IN struct adapter * pAdapter, void PHY_SetBWMode8192C( IN struct adapter * pAdapter,
IN HT_CHANNEL_WIDTH ChnlWidth, IN HT_CHANNEL_WIDTH ChnlWidth,
IN unsigned char Offset ); IN unsigned char Offset );
// /* */
// Set FW CMD IO for 8192S. /* Set FW CMD IO for 8192S. */
// /* */
//extern bool HalSetIO8192C( IN struct adapter * Adapter, /* extern bool HalSetIO8192C( IN struct adapter * Adapter, */
// IN IO_TYPE IOType); /* IN IO_TYPE IOType); */
// /* */
// Set A2 entry to fw for 8192S /* Set A2 entry to fw for 8192S */
// /* */
extern void FillA2Entry8192C( IN struct adapter * Adapter, extern void FillA2Entry8192C( IN struct adapter * Adapter,
IN u8 index, IN u8 index,
IN u8* val); IN u8* val);
// /* */
// channel switch related funciton /* channel switch related funciton */
// /* */
//extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer ); /* extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer ); */
void PHY_SwChnl8192C( IN struct adapter * pAdapter, void PHY_SwChnl8192C( IN struct adapter * pAdapter,
IN u8 channel ); IN u8 channel );
// Call after initialization /* Call after initialization */
void PHY_SwChnlPhy8192C( IN struct adapter * pAdapter, void PHY_SwChnlPhy8192C( IN struct adapter * pAdapter,
IN u8 channel ); IN u8 channel );
void ChkFwCmdIoDone( IN struct adapter *Adapter); void ChkFwCmdIoDone( IN struct adapter *Adapter);
// /* */
// BB/MAC/RF other monitor API /* BB/MAC/RF other monitor API */
// /* */
void PHY_SetMonitorMode8192C(IN struct adapter *pAdapter, void PHY_SetMonitorMode8192C(IN struct adapter *pAdapter,
IN bool bEnableMonitorMode ); IN bool bEnableMonitorMode );
@ -328,9 +327,9 @@ bool PHY_CheckIsLegalRfPath8192C(IN struct adapter *pAdapter,
void rtl8192c_PHY_SetRFPathSwitch(IN struct adapter *pAdapter, IN bool bMain); void rtl8192c_PHY_SetRFPathSwitch(IN struct adapter *pAdapter, IN bool bMain);
// /* */
// Modify the value of the hw register when beacon interval be changed. /* Modify the value of the hw register when beacon interval be changed. */
// /* */
void void
rtl8192c_PHY_SetBeaconHwReg( IN struct adapter * Adapter, rtl8192c_PHY_SetBeaconHwReg( IN struct adapter * Adapter,
IN u16 BeaconInterval ); IN u16 BeaconInterval );
@ -362,4 +361,4 @@ SetAntennaConfig92C(
#define PHY_SetMacReg PHY_SetBBReg #define PHY_SetMacReg PHY_SetBBReg
#define PHY_QueryMacReg PHY_QueryBBReg #define PHY_QueryMacReg PHY_QueryBBReg
#endif // __INC_HAL8192CPHYCFG_H #endif /* __INC_HAL8192CPHYCFG_H */

490
include/Hal8192CPhyReg.h
View file

@ -46,24 +46,24 @@
/*--------------------------Define Parameters-------------------------------*/ /*--------------------------Define Parameters-------------------------------*/
//============================================================ /* */
// 8192S Regsiter offset definition /* 8192S Regsiter offset definition */
//============================================================ /* */
// /* */
// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */
// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
// 3. RF register 0x00-2E /* 3. RF register 0x00-2E */
// 4. Bit Mask for BB/RF register /* 4. Bit Mask for BB/RF register */
// 5. Other defintion for BB/RF R/W /* 5. Other defintion for BB/RF R/W */
// /* */
// /* */
// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */
// 1. Page1(0x100) /* 1. Page1(0x100) */
// /* */
#define rPMAC_Reset 0x100 #define rPMAC_Reset 0x100
#define rPMAC_TxStart 0x104 #define rPMAC_TxStart 0x104
#define rPMAC_TxLegacySIG 0x108 #define rPMAC_TxLegacySIG 0x108
@ -92,27 +92,27 @@
#define rPMAC_CCKCRxRC32OK 0x188 #define rPMAC_CCKCRxRC32OK 0x188
#define rPMAC_TxStatus 0x18c #define rPMAC_TxStatus 0x18c
// /* */
// 2. Page2(0x200) /* 2. Page2(0x200) */
// /* */
// The following two definition are only used for USB interface. /* The following two definition are only used for USB interface. */
#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address. #define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */
#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data. #define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */
// /* */
// 3. Page8(0x800) /* 3. Page8(0x800) */
// /* */
#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */
#define rFPGA0_TxInfo 0x804 // Status report?? #define rFPGA0_TxInfo 0x804 /* Status report?? */
#define rFPGA0_PSDFunction 0x808 #define rFPGA0_PSDFunction 0x808
#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
#define rFPGA0_RFTiming1 0x810 // Useless now #define rFPGA0_RFTiming1 0x810 /* Useless now */
#define rFPGA0_RFTiming2 0x814 #define rFPGA0_RFTiming2 0x814
#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
#define rFPGA0_XA_HSSIParameter2 0x824 #define rFPGA0_XA_HSSIParameter2 0x824
#define rFPGA0_XB_HSSIParameter1 0x828 #define rFPGA0_XB_HSSIParameter1 0x828
#define rFPGA0_XB_HSSIParameter2 0x82c #define rFPGA0_XB_HSSIParameter2 0x82c
@ -127,77 +127,77 @@
#define rFPGA0_XA_LSSIParameter 0x840 #define rFPGA0_XA_LSSIParameter 0x840
#define rFPGA0_XB_LSSIParameter 0x844 #define rFPGA0_XB_LSSIParameter 0x844
#define rFPGA0_RFWakeUpParameter 0x850 // Useless now #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */
#define rFPGA0_RFSleepUpParameter 0x854 #define rFPGA0_RFSleepUpParameter 0x854
#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */
#define rFPGA0_XCD_SwitchControl 0x85c #define rFPGA0_XCD_SwitchControl 0x85c
#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */
#define rFPGA0_XB_RFInterfaceOE 0x864 #define rFPGA0_XB_RFInterfaceOE 0x864
#define rTxAGC_B_Mcs15_Mcs12 0x868 #define rTxAGC_B_Mcs15_Mcs12 0x868
#define rTxAGC_B_CCK11_A_CCK2_11 0x86c #define rTxAGC_B_CCK11_A_CCK2_11 0x86c
#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */
#define rFPGA0_XCD_RFInterfaceSW 0x874 #define rFPGA0_XCD_RFInterfaceSW 0x874
#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */
#define rFPGA0_XCD_RFParameter 0x87c #define rFPGA0_XCD_RFParameter 0x87c
#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */
#define rFPGA0_AnalogParameter2 0x884 #define rFPGA0_AnalogParameter2 0x884
#define rFPGA0_AnalogParameter3 0x888 // Useless now #define rFPGA0_AnalogParameter3 0x888 /* Useless now */
#define rFPGA0_AnalogParameter4 0x88c #define rFPGA0_AnalogParameter4 0x88c
#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */
#define rFPGA0_XB_LSSIReadBack 0x8a4 #define rFPGA0_XB_LSSIReadBack 0x8a4
#define rFPGA0_XC_LSSIReadBack 0x8a8 #define rFPGA0_XC_LSSIReadBack 0x8a8
#define rFPGA0_XD_LSSIReadBack 0x8ac #define rFPGA0_XD_LSSIReadBack 0x8ac
#define rFPGA0_PSDReport 0x8b4 // Useless now #define rFPGA0_PSDReport 0x8b4 /* Useless now */
#define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */
#define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */
#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now RF Interface Readback Value */
#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */
// /* */
// 4. Page9(0x900) /* 4. Page9(0x900) */
// /* */
#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC RF BW Setting?? */
#define rFPGA1_TxBlock 0x904 // Useless now #define rFPGA1_TxBlock 0x904 /* Useless now */
#define rFPGA1_DebugSelect 0x908 // Useless now #define rFPGA1_DebugSelect 0x908 /* Useless now */
#define rFPGA1_TxInfo 0x90c // Useless now // Status report?? #define rFPGA1_TxInfo 0x90c /* Useless now Status report?? */
// /* */
// 5. PageA(0xA00) /* 5. PageA(0xA00) */
// /* */
// Set Control channel to upper or lower. These settings are required only for 40MHz /* Set Control channel to upper or lower. These settings are required only for 40MHz */
#define rCCK0_System 0xa00 #define rCCK0_System 0xa00
#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI #define rCCK0_AFESetting 0xa04 /* Disable init gain now Select RX path by RSSI */
#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain #define rCCK0_CCA 0xa08 /* Disable init gain now Init gain */
#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series #define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
#define rCCK0_RxAGC2 0xa10 //AGC & DAGC #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */
#define rCCK0_RxHP 0xa14 #define rCCK0_RxHP 0xa14
#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold #define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */
#define rCCK0_DSPParameter2 0xa1c //SQ threshold #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
#define rCCK0_TxFilter1 0xa20 #define rCCK0_TxFilter1 0xa20
#define rCCK0_TxFilter2 0xa24 #define rCCK0_TxFilter2 0xa24
#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */
#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */
#define rCCK0_TRSSIReport 0xa50 #define rCCK0_TRSSIReport 0xa50
#define rCCK0_RxReport 0xa54 //0xa57 #define rCCK0_RxReport 0xa54 /* 0xa57 */
#define rCCK0_FACounterLower 0xa5c //0xa5b #define rCCK0_FACounterLower 0xa5c /* 0xa5b */
#define rCCK0_FACounterUpper 0xa58 //0xa5c #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */
// /* */
// PageB(0xB00) /* PageB(0xB00) */
// /* */
#define rPdp_AntA 0xb00 #define rPdp_AntA 0xb00
#define rPdp_AntA_4 0xb04 #define rPdp_AntA_4 0xb04
#define rConfig_Pmpd_AntA 0xb28 #define rConfig_Pmpd_AntA 0xb28
@ -208,17 +208,17 @@
#define rConfig_Pmpd_AntB 0xb98 #define rConfig_Pmpd_AntB 0xb98
#define rAPK 0xbd8 #define rAPK 0xbd8
// /* */
// 6. PageC(0xC00) /* 6. PageC(0xC00) */
// /* */
#define rOFDM0_LSTF 0xc00 #define rOFDM0_LSTF 0xc00
#define rOFDM0_TRxPathEnable 0xc04 #define rOFDM0_TRxPathEnable 0xc04
#define rOFDM0_TRMuxPar 0xc08 #define rOFDM0_TRMuxPar 0xc08
#define rOFDM0_TRSWIsolation 0xc0c #define rOFDM0_TRSWIsolation 0xc0c
#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */
#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */
#define rOFDM0_XBRxAFE 0xc18 #define rOFDM0_XBRxAFE 0xc18
#define rOFDM0_XBRxIQImbalance 0xc1c #define rOFDM0_XBRxIQImbalance 0xc1c
#define rOFDM0_XCRxAFE 0xc20 #define rOFDM0_XCRxAFE 0xc20
@ -226,17 +226,17 @@
#define rOFDM0_XDRxAFE 0xc28 #define rOFDM0_XDRxAFE 0xc28
#define rOFDM0_XDRxIQImbalance 0xc2c #define rOFDM0_XDRxIQImbalance 0xc2c
#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain #define rOFDM0_RxDetector1 0xc30 /* PD,BW & SBD DM tune init gain */
#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */
#define rOFDM0_RxDetector3 0xc38 //Frame Sync. #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */
#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */
#define rOFDM0_RxDSP 0xc40 //Rx Sync Path #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */
#define rOFDM0_ECCAThreshold 0xc4c // energy CCA #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
#define rOFDM0_XAAGCCore1 0xc50 // DIG #define rOFDM0_XAAGCCore1 0xc50 /* DIG */
#define rOFDM0_XAAGCCore2 0xc54 #define rOFDM0_XAAGCCore2 0xc54
#define rOFDM0_XBAGCCore1 0xc58 #define rOFDM0_XBAGCCore1 0xc58
#define rOFDM0_XBAGCCore2 0xc5c #define rOFDM0_XBAGCCore2 0xc5c
@ -250,7 +250,7 @@
#define rOFDM0_AGCRSSITable 0xc78 #define rOFDM0_AGCRSSITable 0xc78
#define rOFDM0_HTSTFAGC 0xc7c #define rOFDM0_HTSTFAGC 0xc7c
#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */
#define rOFDM0_XATxAFE 0xc84 #define rOFDM0_XATxAFE 0xc84
#define rOFDM0_XBTxIQImbalance 0xc88 #define rOFDM0_XBTxIQImbalance 0xc88
#define rOFDM0_XBTxAFE 0xc8c #define rOFDM0_XBTxAFE 0xc8c
@ -271,13 +271,13 @@
#define rOFDM0_FrameSync 0xcf0 #define rOFDM0_FrameSync 0xcf0
#define rOFDM0_DFSReport 0xcf4 #define rOFDM0_DFSReport 0xcf4
// /* */
// 7. PageD(0xD00) /* 7. PageD(0xD00) */
// /* */
#define rOFDM1_LSTF 0xd00 #define rOFDM1_LSTF 0xd00
#define rOFDM1_TRxPathEnable 0xd04 #define rOFDM1_TRxPathEnable 0xd04
#define rOFDM1_CFO 0xd08 // No setting now #define rOFDM1_CFO 0xd08 /* No setting now */
#define rOFDM1_CSI1 0xd10 #define rOFDM1_CSI1 0xd10
#define rOFDM1_SBD 0xd14 #define rOFDM1_SBD 0xd14
#define rOFDM1_CSI2 0xd18 #define rOFDM1_CSI2 0xd18
@ -288,11 +288,11 @@
#define rOFDM1_PseudoNoiseStateCD 0xd54 #define rOFDM1_PseudoNoiseStateCD 0xd54
#define rOFDM1_RxPseudoNoiseWgt 0xd58 #define rOFDM1_RxPseudoNoiseWgt 0xd58
#define rOFDM_PHYCounter1 0xda0 //cca, parity fail #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */
#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */
#define rOFDM_PHYCounter3 0xda8 //MCS not support #define rOFDM_PHYCounter3 0xda8 /* MCS not support */
#define rOFDM_ShortCFOAB 0xdac // No setting now #define rOFDM_ShortCFOAB 0xdac /* No setting now */
#define rOFDM_ShortCFOCD 0xdb0 #define rOFDM_ShortCFOCD 0xdb0
#define rOFDM_LongCFOAB 0xdb4 #define rOFDM_LongCFOAB 0xdb4
#define rOFDM_LongCFOCD 0xdb8 #define rOFDM_LongCFOCD 0xdb8
@ -307,9 +307,9 @@
#define rOFDM_SIGReport 0xddc #define rOFDM_SIGReport 0xddc
// /* */
// 8. PageE(0xE00) /* 8. PageE(0xE00) */
// /* */
#define rTxAGC_A_Rate18_06 0xe00 #define rTxAGC_A_Rate18_06 0xe00
#define rTxAGC_A_Rate54_24 0xe04 #define rTxAGC_A_Rate54_24 0xe04
#define rTxAGC_A_CCK1_Mcs32 0xe08 #define rTxAGC_A_CCK1_Mcs32 0xe08
@ -367,108 +367,108 @@
#define rSleep 0xee0 #define rSleep 0xee0
#define rPMPD_ANAEN 0xeec #define rPMPD_ANAEN 0xeec
// /* */
// 7. RF Register 0x00-0x2E (RF 8256) /* 7. RF Register 0x00-0x2E (RF 8256) */
// RF-0222D 0x00-3F /* RF-0222D 0x00-3F */
// /* */
//Zebra1 /* Zebra1 */
#define rZebra1_HSSIEnable 0x0 // Useless now #define rZebra1_HSSIEnable 0x0 /* Useless now */
#define rZebra1_TRxEnable1 0x1 #define rZebra1_TRxEnable1 0x1
#define rZebra1_TRxEnable2 0x2 #define rZebra1_TRxEnable2 0x2
#define rZebra1_AGC 0x4 #define rZebra1_AGC 0x4
#define rZebra1_ChargePump 0x5 #define rZebra1_ChargePump 0x5
#define rZebra1_Channel 0x7 // RF channel switch #define rZebra1_Channel 0x7 /* RF channel switch */
//#endif /* endif */
#define rZebra1_TxGain 0x8 // Useless now #define rZebra1_TxGain 0x8 /* Useless now */
#define rZebra1_TxLPF 0x9 #define rZebra1_TxLPF 0x9
#define rZebra1_RxLPF 0xb #define rZebra1_RxLPF 0xb
#define rZebra1_RxHPFCorner 0xc #define rZebra1_RxHPFCorner 0xc
//Zebra4 /* Zebra4 */
#define rGlobalCtrl 0 // Useless now #define rGlobalCtrl 0 /* Useless now */
#define rRTL8256_TxLPF 19 #define rRTL8256_TxLPF 19
#define rRTL8256_RxLPF 11 #define rRTL8256_RxLPF 11
//RTL8258 /* RTL8258 */
#define rRTL8258_TxLPF 0x11 // Useless now #define rRTL8258_TxLPF 0x11 /* Useless now */
#define rRTL8258_RxLPF 0x13 #define rRTL8258_RxLPF 0x13
#define rRTL8258_RSSILPF 0xa #define rRTL8258_RSSILPF 0xa
// /* */
// RL6052 Register definition /* RL6052 Register definition */
// /* */
#define RF_AC 0x00 // #define RF_AC 0x00 /* */
#define RF_IQADJ_G1 0x01 // #define RF_IQADJ_G1 0x01 /* */
#define RF_IQADJ_G2 0x02 // #define RF_IQADJ_G2 0x02 /* */
#define RF_BS_PA_APSET_G1_G4 0x03 #define RF_BS_PA_APSET_G1_G4 0x03
#define RF_BS_PA_APSET_G5_G8 0x04 #define RF_BS_PA_APSET_G5_G8 0x04
#define RF_POW_TRSW 0x05 // #define RF_POW_TRSW 0x05 /* */
#define RF_GAIN_RX 0x06 // #define RF_GAIN_RX 0x06 /* */
#define RF_GAIN_TX 0x07 // #define RF_GAIN_TX 0x07 /* */
#define RF_TXM_IDAC 0x08 // #define RF_TXM_IDAC 0x08 /* */
#define RF_IPA_G 0x09 // #define RF_IPA_G 0x09 /* */
#define RF_TXBIAS_G 0x0A #define RF_TXBIAS_G 0x0A
#define RF_TXPA_AG 0x0B #define RF_TXPA_AG 0x0B
#define RF_IPA_A 0x0C // #define RF_IPA_A 0x0C /* */
#define RF_TXBIAS_A 0x0D #define RF_TXBIAS_A 0x0D
#define RF_BS_PA_APSET_G9_G11 0x0E #define RF_BS_PA_APSET_G9_G11 0x0E
#define RF_BS_IQGEN 0x0F // #define RF_BS_IQGEN 0x0F /* */
#define RF_MODE1 0x10 // #define RF_MODE1 0x10 /* */
#define RF_MODE2 0x11 // #define RF_MODE2 0x11 /* */
#define RF_RX_AGC_HP 0x12 // #define RF_RX_AGC_HP 0x12 /* */
#define RF_TX_AGC 0x13 // #define RF_TX_AGC 0x13 /* */
#define RF_BIAS 0x14 // #define RF_BIAS 0x14 /* */
#define RF_IPA 0x15 // #define RF_IPA 0x15 /* */
#define RF_TXBIAS 0x16 // #define RF_TXBIAS 0x16 /* */
#define RF_POW_ABILITY 0x17 // #define RF_POW_ABILITY 0x17 /* */
#define RF_MODE_AG 0x18 // #define RF_MODE_AG 0x18 /* */
#define rRfChannel 0x18 // RF channel and BW switch #define rRfChannel 0x18 /* RF channel and BW switch */
#define RF_CHNLBW 0x18 // RF channel and BW switch #define RF_CHNLBW 0x18 /* RF channel and BW switch */
#define RF_TOP 0x19 // #define RF_TOP 0x19 /* */
#define RF_RX_G1 0x1A // #define RF_RX_G1 0x1A /* */
#define RF_RX_G2 0x1B // #define RF_RX_G2 0x1B /* */
#define RF_RX_BB2 0x1C // #define RF_RX_BB2 0x1C /* */
#define RF_RX_BB1 0x1D // #define RF_RX_BB1 0x1D /* */
#define RF_RCK1 0x1E // #define RF_RCK1 0x1E /* */
#define RF_RCK2 0x1F // #define RF_RCK2 0x1F /* */
#define RF_TX_G1 0x20 // #define RF_TX_G1 0x20 /* */
#define RF_TX_G2 0x21 // #define RF_TX_G2 0x21 /* */
#define RF_TX_G3 0x22 // #define RF_TX_G3 0x22 /* */
#define RF_TX_BB1 0x23 // #define RF_TX_BB1 0x23 /* */
#define RF_T_METER 0x24 // #define RF_T_METER 0x24 /* */
#define RF_SYN_G1 0x25 // RF TX Power control #define RF_SYN_G1 0x25 /* RF TX Power control */
#define RF_SYN_G2 0x26 // RF TX Power control #define RF_SYN_G2 0x26 /* RF TX Power control */
#define RF_SYN_G3 0x27 // RF TX Power control #define RF_SYN_G3 0x27 /* RF TX Power control */
#define RF_SYN_G4 0x28 // RF TX Power control #define RF_SYN_G4 0x28 /* RF TX Power control */
#define RF_SYN_G5 0x29 // RF TX Power control #define RF_SYN_G5 0x29 /* RF TX Power control */
#define RF_SYN_G6 0x2A // RF TX Power control #define RF_SYN_G6 0x2A /* RF TX Power control */
#define RF_SYN_G7 0x2B // RF TX Power control #define RF_SYN_G7 0x2B /* RF TX Power control */
#define RF_SYN_G8 0x2C // RF TX Power control #define RF_SYN_G8 0x2C /* RF TX Power control */
#define RF_RCK_OS 0x30 // RF TX PA control #define RF_RCK_OS 0x30 /* RF TX PA control */
#define RF_TXPA_G1 0x31 // RF TX PA control #define RF_TXPA_G1 0x31 /* RF TX PA control */
#define RF_TXPA_G2 0x32 // RF TX PA control #define RF_TXPA_G2 0x32 /* RF TX PA control */
#define RF_TXPA_G3 0x33 // RF TX PA control #define RF_TXPA_G3 0x33 /* RF TX PA control */
// /* */
//Bit Mask /* Bit Mask */
// /* */
// 1. Page1(0x100) /* 1. Page1(0x100) */
#define bBBResetB 0x100 // Useless now? #define bBBResetB 0x100 /* Useless now? */
#define bGlobalResetB 0x200 #define bGlobalResetB 0x200
#define bOFDMTxStart 0x4 #define bOFDMTxStart 0x4
#define bCCKTxStart 0x8 #define bCCKTxStart 0x8
@ -515,36 +515,36 @@
#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
// 2. Page8(0x800) /* 2. Page8(0x800) */
#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */
#define bJapanMode 0x2 #define bJapanMode 0x2
#define bCCKTxSC 0x30 #define bCCKTxSC 0x30
#define bCCKEn 0x1000000 #define bCCKEn 0x1000000
#define bOFDMEn 0x2000000 #define bOFDMEn 0x2000000
#define bOFDMRxADCPhase 0x10000 // Useless now #define bOFDMRxADCPhase 0x10000 /* Useless now */
#define bOFDMTxDACPhase 0x40000 #define bOFDMTxDACPhase 0x40000
#define bXATxAGC 0x3f #define bXATxAGC 0x3f
#define bAntennaSelect 0x0300 #define bAntennaSelect 0x0300
#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */
#define bXCTxAGC 0xf000 #define bXCTxAGC 0xf000
#define bXDTxAGC 0xf0000 #define bXDTxAGC 0xf0000
#define bPAStart 0xf0000000 // Useless now #define bPAStart 0xf0000000 /* Useless now */
#define bTRStart 0x00f00000 #define bTRStart 0x00f00000
#define bRFStart 0x0000f000 #define bRFStart 0x0000f000
#define bBBStart 0x000000f0 #define bBBStart 0x000000f0
#define bBBCCKStart 0x0000000f #define bBBCCKStart 0x0000000f
#define bPAEnd 0xf //Reg0x814 #define bPAEnd 0xf /* Reg0x814 */
#define bTREnd 0x0f000000 #define bTREnd 0x0f000000
#define bRFEnd 0x000f0000 #define bRFEnd 0x000f0000
#define bCCAMask 0x000000f0 //T2R #define bCCAMask 0x000000f0 /* T2R */
#define bR2RCCAMask 0x00000f00 #define bR2RCCAMask 0x00000f00
#define bHSSI_R2TDelay 0xf8000000 #define bHSSI_R2TDelay 0xf8000000
#define bHSSI_T2RDelay 0xf80000 #define bHSSI_T2RDelay 0xf80000
#define bContTxHSSI 0x400 //chane gain at continue Tx #define bContTxHSSI 0x400 /* chane gain at continue Tx */
#define bIGFromCCK 0x200 #define bIGFromCCK 0x200
#define bAGCAddress 0x3f #define bAGCAddress 0x3f
#define bRxHPTx 0x7000 #define bRxHPTx 0x7000
@ -553,11 +553,11 @@
#define bAGCTxCode 0xc00000 #define bAGCTxCode 0xc00000
#define bAGCRxCode 0x300000 #define bAGCRxCode 0x300000
#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
#define b3WireAddressLength 0x400 #define b3WireAddressLength 0x400
#define b3WireRFPowerDown 0x1 // Useless now #define b3WireRFPowerDown 0x1 /* Useless now */
//#define bHWSISelect 0x8 /* define bHWSISelect 0x8 */
#define b5GPAPEPolarity 0x40000000 #define b5GPAPEPolarity 0x40000000
#define b2GPAPEPolarity 0x80000000 #define b2GPAPEPolarity 0x80000000
#define bRFSW_TxDefaultAnt 0x3 #define bRFSW_TxDefaultAnt 0x3
@ -570,9 +570,9 @@
#define bRFSI_3WireRW 0x8 #define bRFSI_3WireRW 0x8
#define bRFSI_3Wire 0xf #define bRFSI_3Wire 0xf
#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
#define bRFSI_TRSW 0x20 // Useless now #define bRFSI_TRSW 0x20 /* Useless now */
#define bRFSI_TRSWB 0x40 #define bRFSI_TRSWB 0x40
#define bRFSI_ANTSW 0x100 #define bRFSI_ANTSW 0x100
#define bRFSI_ANTSWB 0x200 #define bRFSI_ANTSWB 0x200
@ -596,14 +596,14 @@
#define bLSIG_Parity 0x20 #define bLSIG_Parity 0x20
#define bCCKRxPhase 0x4 #define bCCKRxPhase 0x4
#define bLSSIReadAddress 0x7f800000 // T65 RF #define bLSSIReadAddress 0x7f800000 /* T65 RF */
#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */
#define bLSSIReadBackData 0xfffff // T65 RF #define bLSSIReadBackData 0xfffff /* T65 RF */
#define bLSSIReadOKFlag 0x1000 // Useless now #define bLSSIReadOKFlag 0x1000 /* Useless now */
#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */
#define bRegulator0Standby 0x1 #define bRegulator0Standby 0x1
#define bRegulatorPLLStandby 0x2 #define bRegulatorPLLStandby 0x2
#define bRegulator1Standby 0x4 #define bRegulator1Standby 0x4
@ -617,17 +617,17 @@
#define bDA6DebugMode 0x20000 #define bDA6DebugMode 0x20000
#define bDA6Swing 0x380000 #define bDA6Swing 0x380000
#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ #define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
#define b80MClkDelay 0x18000000 // Useless #define b80MClkDelay 0x18000000 /* Useless */
#define bAFEWatchDogEnable 0x20000000 #define bAFEWatchDogEnable 0x20000000
#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap #define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
#define bXtalCap23 0x3 #define bXtalCap23 0x3
#define bXtalCap92x 0x0f000000 #define bXtalCap92x 0x0f000000
#define bXtalCap 0x0f000000 #define bXtalCap 0x0f000000
#define bIntDifClkEnable 0x400 // Useless #define bIntDifClkEnable 0x400 /* Useless */
#define bExtSigClkEnable 0x800 #define bExtSigClkEnable 0x800
#define bBandgapMbiasPowerUp 0x10000 #define bBandgapMbiasPowerUp 0x10000
#define bAD11SHGain 0xc0000 #define bAD11SHGain 0xc0000
@ -661,12 +661,12 @@
#define bPSDSineToneScale 0x7f000000 #define bPSDSineToneScale 0x7f000000
#define bPSDReport 0xffff #define bPSDReport 0xffff
// 3. Page9(0x900) /* 3. Page9(0x900) */
#define bOFDMTxSC 0x30000000 // Useless #define bOFDMTxSC 0x30000000 /* Useless */
#define bCCKTxOn 0x1 #define bCCKTxOn 0x1
#define bOFDMTxOn 0x2 #define bOFDMTxOn 0x2
#define bDebugPage 0xfff //reset debug page and also HWord, LWord #define bDebugPage 0xfff /* reset debug page and also HWord, LWord */
#define bDebugItem 0xff //reset debug page and LWord #define bDebugItem 0xff /* reset debug page and LWord */
#define bAntL 0x10 #define bAntL 0x10
#define bAntNonHT 0x100 #define bAntNonHT 0x100
#define bAntHT1 0x1000 #define bAntHT1 0x1000
@ -674,14 +674,14 @@
#define bAntHT1S1 0x100000 #define bAntHT1S1 0x100000
#define bAntNonHTS1 0x1000000 #define bAntNonHTS1 0x1000000
// 4. PageA(0xA00) /* 4. PageA(0xA00) */
#define bCCKBBMode 0x3 // Useless #define bCCKBBMode 0x3 /* Useless */
#define bCCKTxPowerSaving 0x80 #define bCCKTxPowerSaving 0x80
#define bCCKRxPowerSaving 0x40 #define bCCKRxPowerSaving 0x40
#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */
#define bCCKScramble 0x8 // Useless #define bCCKScramble 0x8 /* Useless */
#define bCCKAntDiversity 0x8000 #define bCCKAntDiversity 0x8000
#define bCCKCarrierRecovery 0x4000 #define bCCKCarrierRecovery 0x4000
#define bCCKTxRate 0x3000 #define bCCKTxRate 0x3000
@ -697,7 +697,7 @@
#define bCCKBistMode 0x80000000 #define bCCKBistMode 0x80000000
#define bCCKCCAMask 0x40000000 #define bCCKCCAMask 0x40000000
#define bCCKTxDACPhase 0x4 #define bCCKTxDACPhase 0x4
#define bCCKRxADCPhase 0x20000000 //r_rx_clk #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
#define bCCKr_cp_mode0 0x0100 #define bCCKr_cp_mode0 0x0100
#define bCCKTxDCOffset 0xf0 #define bCCKTxDCOffset 0xf0
#define bCCKRxDCOffset 0xf #define bCCKRxDCOffset 0xf
@ -711,12 +711,12 @@
#define bCCKRxIG 0x7f00 #define bCCKRxIG 0x7f00
#define bCCKLNAPolarity 0x800000 #define bCCKLNAPolarity 0x800000
#define bCCKRx1stGain 0x7f0000 #define bCCKRx1stGain 0x7f0000
#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */
#define bCCKRxAGCSatLevel 0x1f000000 #define bCCKRxAGCSatLevel 0x1f000000
#define bCCKRxAGCSatCount 0xe0 #define bCCKRxAGCSatCount 0xe0
#define bCCKRxRFSettle 0x1f //AGCsamp_dly #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */
#define bCCKFixedRxAGC 0x8000 #define bCCKFixedRxAGC 0x8000
//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 /* define bCCKRxAGCFormat 0x4000 remove to HSSI register 0x824 */
#define bCCKAntennaPolarity 0x2000 #define bCCKAntennaPolarity 0x2000
#define bCCKTxFilterType 0x0c00 #define bCCKTxFilterType 0x0c00
#define bCCKRxAGCReportType 0x0300 #define bCCKRxAGCReportType 0x0300
@ -755,8 +755,8 @@
#define bCCKDefaultRxPath 0xc000000 #define bCCKDefaultRxPath 0xc000000
#define bCCKOptionRxPath 0x3000000 #define bCCKOptionRxPath 0x3000000
// 5. PageC(0xC00) /* 5. PageC(0xC00) */
#define bNumOfSTF 0x3 // Useless #define bNumOfSTF 0x3 /* Useless */
#define bShift_L 0xc0 #define bShift_L 0xc0
#define bGI_TH 0xc #define bGI_TH 0xc
#define bRxPathA 0x1 #define bRxPathA 0x1
@ -857,8 +857,8 @@
#define bRxHP_BBP1 0x7000 #define bRxHP_BBP1 0x7000
#define bRxHP_BBP2 0x70000 #define bRxHP_BBP2 0x70000
#define bRxHP_BBP3 0x700000 #define bRxHP_BBP3 0x700000
#define bRSSI_H 0x7f0000 //the threshold for high power #define bRSSI_H 0x7f0000 /* the threshold for high power */
#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity #define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */
#define bRxSettle_TRSW 0x7 #define bRxSettle_TRSW 0x7
#define bRxSettle_LNA 0x38 #define bRxSettle_LNA 0x38
#define bRxSettle_RSSI 0x1c0 #define bRxSettle_RSSI 0x1c0
@ -892,7 +892,7 @@
#define bRxPD_Delay_TH1 0x38 #define bRxPD_Delay_TH1 0x38
#define bRxPD_Delay_TH2 0x1c0 #define bRxPD_Delay_TH2 0x1c0
#define bRxPD_DC_COUNT_MAX 0x600 #define bRxPD_DC_COUNT_MAX 0x600
//#define bRxMF_Hold 0x3800 /* define bRxMF_Hold 0x3800 */
#define bRxPD_Delay_TH 0x8000 #define bRxPD_Delay_TH 0x8000
#define bRxProcess_Delay 0xf0000 #define bRxProcess_Delay 0xf0000
#define bRxSearchrange_GI2_Early 0x700000 #define bRxSearchrange_GI2_Early 0x700000
@ -913,8 +913,8 @@
#define bTRSWIsolation_D 0x7f000000 #define bTRSWIsolation_D 0x7f000000
#define bExtLNAGain 0x7c00 #define bExtLNAGain 0x7c00
// 6. PageE(0xE00) /* 6. PageE(0xE00) */
#define bSTBCEn 0x4 // Useless #define bSTBCEn 0x4 /* Useless */
#define bAntennaMapping 0x10 #define bAntennaMapping 0x10
#define bNss 0x20 #define bNss 0x20
#define bCFOAntSumD 0x200 #define bCFOAntSumD 0x200
@ -923,12 +923,12 @@
#define bOFDMContinueTx 0x10000000 #define bOFDMContinueTx 0x10000000
#define bOFDMSingleCarrier 0x20000000 #define bOFDMSingleCarrier 0x20000000
#define bOFDMSingleTone 0x40000000 #define bOFDMSingleTone 0x40000000
//#define bRxPath1 0x01 /* define bRxPath1 0x01 */
//#define bRxPath2 0x02 /* define bRxPath2 0x02 */
//#define bRxPath3 0x04 /* define bRxPath3 0x04 */
//#define bRxPath4 0x08 /* define bRxPath4 0x08 */
//#define bTxPath1 0x10 /* define bTxPath1 0x10 */
//#define bTxPath2 0x20 /* define bTxPath2 0x20 */
#define bHTDetect 0x100 #define bHTDetect 0x100
#define bCFOEn 0x10000 #define bCFOEn 0x10000
#define bCFOValue 0xfff00000 #define bCFOValue 0xfff00000
@ -941,8 +941,8 @@
#define bCounter_MCSNoSupport 0xffff #define bCounter_MCSNoSupport 0xffff
#define bCounter_FastSync 0xffff #define bCounter_FastSync 0xffff
#define bShortCFO 0xfff #define bShortCFO 0xfff
#define bShortCFOTLength 12 //total #define bShortCFOTLength 12 /* total */
#define bShortCFOFLength 11 //fraction #define bShortCFOFLength 11 /* fraction */
#define bLongCFO 0x7ff #define bLongCFO 0x7ff
#define bLongCFOTLength 11 #define bLongCFOTLength 11
#define bLongCFOFLength 11 #define bLongCFOFLength 11
@ -977,7 +977,7 @@
#define bPWDB 0xff00 #define bPWDB 0xff00
#define bSGIEN 0x10000 #define bSGIEN 0x10000
#define bSFactorQAM1 0xf // Useless #define bSFactorQAM1 0xf /* Useless */
#define bSFactorQAM2 0xf0 #define bSFactorQAM2 0xf0
#define bSFactorQAM3 0xf00 #define bSFactorQAM3 0xf00
#define bSFactorQAM4 0xf000 #define bSFactorQAM4 0xf000
@ -988,7 +988,7 @@
#define bSFactorQAM9 0xf0000000 #define bSFactorQAM9 0xf0000000
#define bCSIScheme 0x100000 #define bCSIScheme 0x100000
#define bNoiseLvlTopSet 0x3 // Useless #define bNoiseLvlTopSet 0x3 /* Useless */
#define bChSmooth 0x4 #define bChSmooth 0x4
#define bChSmoothCfg1 0x38 #define bChSmoothCfg1 0x38
#define bChSmoothCfg2 0x1c0 #define bChSmoothCfg2 0x1c0
@ -997,7 +997,7 @@
#define bMRCMode 0x800000 #define bMRCMode 0x800000
#define bTHEVMCfg 0x7000000 #define bTHEVMCfg 0x7000000
#define bLoopFitType 0x1 // Useless #define bLoopFitType 0x1 /* Useless */
#define bUpdCFO 0x40 #define bUpdCFO 0x40
#define bUpdCFOOffData 0x80 #define bUpdCFOOffData 0x80
#define bAdvUpdCFO 0x100 #define bAdvUpdCFO 0x100
@ -1013,8 +1013,8 @@
#define bUChCfg 0x7000000 #define bUChCfg 0x7000000
#define bUpdEqz 0x8000000 #define bUpdEqz 0x8000000
//Rx Pseduo noise /* Rx Pseduo noise */
#define bRxPesudoNoiseOn 0x20000000 // Useless #define bRxPesudoNoiseOn 0x20000000 /* Useless */
#define bRxPesudoNoise_A 0xff #define bRxPesudoNoise_A 0xff
#define bRxPesudoNoise_B 0xff00 #define bRxPesudoNoise_B 0xff00
#define bRxPesudoNoise_C 0xff0000 #define bRxPesudoNoise_C 0xff0000
@ -1024,9 +1024,9 @@
#define bPesudoNoiseState_C 0xffff #define bPesudoNoiseState_C 0xffff
#define bPesudoNoiseState_D 0xffff0000 #define bPesudoNoiseState_D 0xffff0000
//7. RF Register /* 7. RF Register */
//Zebra1 /* Zebra1 */
#define bZebra1_HSSIEnable 0x8 // Useless #define bZebra1_HSSIEnable 0x8 /* Useless */
#define bZebra1_TRxControl 0xc00 #define bZebra1_TRxControl 0xc00
#define bZebra1_TRxGainSetting 0x07f #define bZebra1_TRxGainSetting 0x07f
#define bZebra1_RxCorner 0xc00 #define bZebra1_RxCorner 0xc00
@ -1036,24 +1036,24 @@
#define bZebra1_TxLPFBW 0x400 #define bZebra1_TxLPFBW 0x400
#define bZebra1_RxLPFBW 0x600 #define bZebra1_RxLPFBW 0x600
//Zebra4 /* Zebra4 */
#define bRTL8256RegModeCtrl1 0x100 // Useless #define bRTL8256RegModeCtrl1 0x100 /* Useless */
#define bRTL8256RegModeCtrl0 0x40 #define bRTL8256RegModeCtrl0 0x40
#define bRTL8256_TxLPFBW 0x18 #define bRTL8256_TxLPFBW 0x18
#define bRTL8256_RxLPFBW 0x600 #define bRTL8256_RxLPFBW 0x600
//RTL8258 /* RTL8258 */
#define bRTL8258_TxLPFBW 0xc // Useless #define bRTL8258_TxLPFBW 0xc /* Useless */
#define bRTL8258_RxLPFBW 0xc00 #define bRTL8258_RxLPFBW 0xc00
#define bRTL8258_RSSILPFBW 0xc0 #define bRTL8258_RSSILPFBW 0xc0
// /* */
// Other Definition /* Other Definition */
// /* */
//byte endable for sb_write /* byte endable for sb_write */
#define bByte0 0x1 // Useless #define bByte0 0x1 /* Useless */
#define bByte1 0x2 #define bByte1 0x2
#define bByte2 0x4 #define bByte2 0x4
#define bByte3 0x8 #define bByte3 0x8
@ -1061,8 +1061,8 @@
#define bWord1 0xc #define bWord1 0xc
#define bDWord 0xf #define bDWord 0xf
//for PutRegsetting & GetRegSetting BitMask /* for PutRegsetting & GetRegSetting BitMask */
#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
#define bMaskByte1 0xff00 #define bMaskByte1 0xff00
#define bMaskByte2 0xff0000 #define bMaskByte2 0xff0000
#define bMaskByte3 0xff000000 #define bMaskByte3 0xff000000
@ -1074,44 +1074,42 @@
#define bMaskOFDM_D 0xffc00000 #define bMaskOFDM_D 0xffc00000
#define bMaskCCK 0x3f3f3f3f #define bMaskCCK 0x3f3f3f3f
//for PutRFRegsetting & GetRFRegSetting BitMask /* for PutRFRegsetting & GetRFRegSetting BitMask */
//#define bMask12Bits 0xfffff // RF Reg mask bits
//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF
#define bRFRegOffsetMask 0xfffff #define bRFRegOffsetMask 0xfffff
#define bEnable 0x1 // Useless #define bEnable 0x1 /* Useless */
#define bDisable 0x0 #define bDisable 0x0
#define LeftAntenna 0x0 // Useless #define LeftAntenna 0x0 /* Useless */
#define RightAntenna 0x1 #define RightAntenna 0x1
#define tCheckTxStatus 500 //500ms // Useless #define tCheckTxStatus 500 /* 500ms Useless */
#define tUpdateRxCounter 100 //100ms #define tUpdateRxCounter 100 /* 100ms */
#define rateCCK 0 // Useless #define rateCCK 0 /* Useless */
#define rateOFDM 1 #define rateOFDM 1
#define rateHT 2 #define rateHT 2
//define Register-End /* define Register-End */
#define bPMAC_End 0x1ff // Useless #define bPMAC_End 0x1ff /* Useless */
#define bFPGAPHY0_End 0x8ff #define bFPGAPHY0_End 0x8ff
#define bFPGAPHY1_End 0x9ff #define bFPGAPHY1_End 0x9ff
#define bCCKPHY0_End 0xaff #define bCCKPHY0_End 0xaff
#define bOFDMPHY0_End 0xcff #define bOFDMPHY0_End 0xcff
#define bOFDMPHY1_End 0xdff #define bOFDMPHY1_End 0xdff
//define max debug item in each debug page /* define max debug item in each debug page */
//#define bMaxItem_FPGA_PHY0 0x9 /* define bMaxItem_FPGA_PHY0 0x9 */
//#define bMaxItem_FPGA_PHY1 0x3 /* define bMaxItem_FPGA_PHY1 0x3 */
//#define bMaxItem_PHY_11B 0x16 /* define bMaxItem_PHY_11B 0x16 */
//#define bMaxItem_OFDM_PHY0 0x29 /* define bMaxItem_OFDM_PHY0 0x29 */
//#define bMaxItem_OFDM_PHY1 0x0 /* define bMaxItem_OFDM_PHY1 0x0 */
#define bPMACControl 0x0 // Useless #define bPMACControl 0x0 /* Useless */
#define bWMACControl 0x1 #define bWMACControl 0x1
#define bWNICControl 0x2 #define bWNICControl 0x2
#define PathA 0x0 // Useless #define PathA 0x0 /* Useless */
#define PathB 0x1 #define PathB 0x1
#define PathC 0x2 #define PathC 0x2
#define PathD 0x3 #define PathD 0x3
@ -1119,4 +1117,4 @@
/*--------------------------Define Parameters-------------------------------*/ /*--------------------------Define Parameters-------------------------------*/
#endif //__INC_HAL8192SPHYREG_H #endif /* __INC_HAL8192SPHYREG_H */

199
include/Hal8192DPhyCfg.h
View file

@ -42,8 +42,8 @@
/*--------------------------Define Parameters-------------------------------*/ /*--------------------------Define Parameters-------------------------------*/
#define LOOP_LIMIT 5 #define LOOP_LIMIT 5
#define MAX_STALL_TIME 50 //us #define MAX_STALL_TIME 50 /* us */
#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80) #define AntennaDiversityValue 0x80 /* Adapter->bSoftwareAntennaDiversity ? 0x00:0x80) */
#define MAX_TXPWR_IDX_NMODE_92S 63 #define MAX_TXPWR_IDX_NMODE_92S 63
#define Reset_Cnt_Limit 3 #define Reset_Cnt_Limit 3
@ -76,10 +76,10 @@ typedef enum _HW90_BLOCK{
HW90_BLOCK_PHY0 = 1, HW90_BLOCK_PHY0 = 1,
HW90_BLOCK_PHY1 = 2, HW90_BLOCK_PHY1 = 2,
HW90_BLOCK_RF = 3, HW90_BLOCK_RF = 3,
HW90_BLOCK_MAXIMUM = 4, // Never use this HW90_BLOCK_MAXIMUM = 4, /* Never use this */
}HW90_BLOCK_E, *PHW90_BLOCK_E; }HW90_BLOCK_E, *PHW90_BLOCK_E;
//vivi added this for read parameter from header, 20100908 /* vivi added this for read parameter from header, 20100908 */
typedef enum _RF_CONTENT{ typedef enum _RF_CONTENT{
radioa_txt = 0x1000, radioa_txt = 0x1000,
radiob_txt = 0x1001, radiob_txt = 0x1001,
@ -88,11 +88,11 @@ typedef enum _RF_CONTENT{
} RF_CONTENT; } RF_CONTENT;
typedef enum _RF_RADIO_PATH{ typedef enum _RF_RADIO_PATH{
RF_PATH_A = 0, //Radio Path A RF_PATH_A = 0, /* Radio Path A */
RF_PATH_B = 1, //Radio Path B RF_PATH_B = 1, /* Radio Path B */
RF_PATH_C = 2, //Radio Path C RF_PATH_C = 2, /* Radio Path C */
RF_PATH_D = 3, //Radio Path D RF_PATH_D = 3, /* Radio Path D */
//RF_PATH_MAX //Max RF number 90 support /* RF_PATH_MAX Max RF number 90 support */
}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E; }RF_RADIO_PATH_E, *PRF_RADIO_PATH_E;
#define RF_PATH_MAX 2 #define RF_PATH_MAX 2
@ -110,12 +110,12 @@ typedef enum _WIRELESS_MODE {
#if(TX_POWER_FOR_5G_BAND == 1) #if(TX_POWER_FOR_5G_BAND == 1)
#define CHANNEL_MAX_NUMBER 14+24+21 // 14 is the max channel number #define CHANNEL_MAX_NUMBER 14+24+21 /* 14 is the max channel number */
#define CHANNEL_GROUP_MAX 3+9 // ch1~3, ch4~9, ch10~14 total three groups #define CHANNEL_GROUP_MAX 3+9 /* ch1~3, ch4~9, ch10~14 total three groups */
#define MAX_PG_GROUP 13 #define MAX_PG_GROUP 13
#else #else
#define CHANNEL_MAX_NUMBER 14 // 14 is the max channel number #define CHANNEL_MAX_NUMBER 14 /* 14 is the max channel number */
#define CHANNEL_GROUP_MAX 3 // ch1~3, ch4~9, ch10~14 total three groups #define CHANNEL_GROUP_MAX 3 /* ch1~3, ch4~9, ch10~14 total three groups */
#define MAX_PG_GROUP 7 #define MAX_PG_GROUP 7
#endif #endif
#define CHANNEL_GROUP_MAX_2G 3 #define CHANNEL_GROUP_MAX_2G 3
@ -134,16 +134,16 @@ typedef enum _BaseBand_Config_Type{
}BaseBand_Config_Type, *PBaseBand_Config_Type; }BaseBand_Config_Type, *PBaseBand_Config_Type;
#else #else
typedef enum _BaseBand_Config_Type{ typedef enum _BaseBand_Config_Type{
BaseBand_Config_PHY_REG = 0, //Radio Path A BaseBand_Config_PHY_REG = 0, /* Radio Path A */
BaseBand_Config_AGC_TAB = 1, //Radio Path B BaseBand_Config_AGC_TAB = 1, /* Radio Path B */
}BaseBand_Config_Type, *PBaseBand_Config_Type; }BaseBand_Config_Type, *PBaseBand_Config_Type;
#endif #endif
typedef enum _MACPHY_MODE_8192D{ typedef enum _MACPHY_MODE_8192D{
SINGLEMAC_SINGLEPHY, //SMSP SINGLEMAC_SINGLEPHY, /* SMSP */
DUALMAC_DUALPHY, //DMDP DUALMAC_DUALPHY, /* DMDP */
DUALMAC_SINGLEPHY, //DMSP DUALMAC_SINGLEPHY, /* DMSP */
}MACPHY_MODE_8192D,*PMACPHY_MODE_8192D; }MACPHY_MODE_8192D,*PMACPHY_MODE_8192D;
typedef enum _MACPHY_MODE_CHANGE_ACTION{ typedef enum _MACPHY_MODE_CHANGE_ACTION{
@ -176,71 +176,70 @@ typedef enum _PHY_Rate_Tx_Power_Offset_Area{
/* BB/RF related */ /* BB/RF related */
typedef enum _RF_TYPE_8190P{ typedef enum _RF_TYPE_8190P{
RF_TYPE_MIN, // 0 RF_TYPE_MIN, /* 0 */
RF_8225=1, // 1 11b/g RF for verification only RF_8225=1, /* 1 11b/g RF for verification only */
RF_8256=2, // 2 11b/g/n RF_8256=2, /* 2 11b/g/n */
RF_8258=3, // 3 11a/b/g/n RF RF_8258=3, /* 3 11a/b/g/n RF */
RF_6052=4, // 4 11b/g/n RF RF_6052=4, /* 4 11b/g/n RF */
//RF_6052=5, // 4 11b/g/n RF /* TODO: We sholud remove this psudo PHY RF after we get new RF. */
// TODO: We sholud remove this psudo PHY RF after we get new RF. RF_PSEUDO_11N=5, /* 5, It is a temporality RF. */
RF_PSEUDO_11N=5, // 5, It is a temporality RF.
}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E; }RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
typedef struct _BB_REGISTER_DEFINITION{ typedef struct _BB_REGISTER_DEFINITION{
u32 rfintfs; // set software control: u32 rfintfs; /* set software control: */
// 0x870~0x877[8 bytes] /* 0x870~0x877[8 bytes] */
u32 rfintfi; // readback data: u32 rfintfi; /* readback data: */
// 0x8e0~0x8e7[8 bytes] /* 0x8e0~0x8e7[8 bytes] */
u32 rfintfo; // output data: u32 rfintfo; /* output data: */
// 0x860~0x86f [16 bytes] /* 0x860~0x86f [16 bytes] */
u32 rfintfe; // output enable: u32 rfintfe; /* output enable: */
// 0x860~0x86f [16 bytes] /* 0x860~0x86f [16 bytes] */
u32 rf3wireOffset; // LSSI data: u32 rf3wireOffset; /* LSSI data: */
// 0x840~0x84f [16 bytes] /* 0x840~0x84f [16 bytes] */
u32 rfLSSI_Select; // BB Band Select: u32 rfLSSI_Select; /* BB Band Select: */
// 0x878~0x87f [8 bytes] /* 0x878~0x87f [8 bytes] */
u32 rfTxGainStage; // Tx gain stage: u32 rfTxGainStage; /* Tx gain stage: */
// 0x80c~0x80f [4 bytes] /* 0x80c~0x80f [4 bytes] */
u32 rfHSSIPara1; // wire parameter control1 : u32 rfHSSIPara1; /* wire parameter control1 : */
// 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] /* 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] */
u32 rfHSSIPara2; // wire parameter control2 : u32 rfHSSIPara2; /* wire parameter control2 : */
// 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] /* 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] */
u32 rfSwitchControl; //Tx Rx antenna control : u32 rfSwitchControl; /* Tx Rx antenna control : */
// 0x858~0x85f [16 bytes] /* 0x858~0x85f [16 bytes] */
u32 rfAGCControl1; //AGC parameter control1 : u32 rfAGCControl1; /* AGC parameter control1 : */
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] /* 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] */
u32 rfAGCControl2; //AGC parameter control2 : u32 rfAGCControl2; /* AGC parameter control2 : */
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] /* 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] */
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : u32 rfRxIQImbalance; /* OFDM Rx IQ imbalance matrix : */
// 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] /* 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] */
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : u32 rfRxAFE; /* Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : */
// 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] /* 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] */
u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */
// 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] /* 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] */
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type u32 rfTxAFE; /* Tx IQ DC Offset and Tx DFIR type */
// 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] /* 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] */
u32 rfLSSIReadBack; //LSSI RF readback data SI mode u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */
// 0x8a0~0x8af [16 bytes] /* 0x8a0~0x8af [16 bytes] */
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for Path A and B */
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T; }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
@ -273,9 +272,9 @@ typedef struct _R_ANTENNA_SELECT_CCK{
/*------------------------Export Marco Definition---------------------------*/ /*------------------------Export Marco Definition---------------------------*/
/*--------------------------Exported Function prototype---------------------*/ /*--------------------------Exported Function prototype---------------------*/
// /* */
// BB and RF register read/write /* BB and RF register read/write */
// /* */
void rtl8192d_PHY_SetBBReg1Byte( IN struct adapter *Adapter, void rtl8192d_PHY_SetBBReg1Byte( IN struct adapter *Adapter,
IN u32 RegAddr, IN u32 RegAddr,
IN u32 BitMask, IN u32 BitMask,
@ -297,9 +296,9 @@ void rtl8192d_PHY_SetRFReg( IN struct adapter * Adapter,
IN u32 BitMask, IN u32 BitMask,
IN u32 Data ); IN u32 Data );
// /* */
// Initialization related function /* Initialization related function */
// /* */
/* MAC/BB/RF HAL config */ /* MAC/BB/RF HAL config */
extern int PHY_MACConfig8192D( IN struct adapter *Adapter ); extern int PHY_MACConfig8192D( IN struct adapter *Adapter );
extern int PHY_BBConfig8192D( IN struct adapter *Adapter ); extern int PHY_BBConfig8192D( IN struct adapter *Adapter );
@ -318,15 +317,15 @@ int rtl8192d_PHY_CheckBBAndRFOK( IN struct adapter * Adapter,
/* Read initi reg value for tx power setting. */ /* Read initi reg value for tx power setting. */
void rtl8192d_PHY_GetHWRegOriginalValue( IN struct adapter * Adapter ); void rtl8192d_PHY_GetHWRegOriginalValue( IN struct adapter * Adapter );
// /* */
// RF Power setting /* RF Power setting */
// /* */
//extern bool PHY_SetRFPowerState(IN struct adapter * Adapter, /* extern bool PHY_SetRFPowerState(IN struct adapter * Adapter, */
// IN RT_RF_POWER_STATE eRFPowerState); /* IN RT_RF_POWER_STATE eRFPowerState); */
// /* */
// BB TX Power R/W /* BB TX Power R/W */
// /* */
void PHY_GetTxPowerLevel8192D( IN struct adapter * Adapter, void PHY_GetTxPowerLevel8192D( IN struct adapter * Adapter,
OUT u32* powerlevel ); OUT u32* powerlevel );
void PHY_SetTxPowerLevel8192D( IN struct adapter * Adapter, void PHY_SetTxPowerLevel8192D( IN struct adapter * Adapter,
@ -334,49 +333,49 @@ void PHY_SetTxPowerLevel8192D( IN struct adapter * Adapter,
bool PHY_UpdateTxPowerDbm8192D( IN struct adapter *Adapter, bool PHY_UpdateTxPowerDbm8192D( IN struct adapter *Adapter,
IN int powerInDbm ); IN int powerInDbm );
// /* */
void void
PHY_ScanOperationBackup8192D(IN struct adapter *Adapter, PHY_ScanOperationBackup8192D(IN struct adapter *Adapter,
IN u8 Operation ); IN u8 Operation );
// /* */
// Switch bandwidth for 8192S /* Switch bandwidth for 8192S */
// /* */
//void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer ); /* void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer ); */
void PHY_SetBWMode8192D( IN struct adapter * pAdapter, void PHY_SetBWMode8192D( IN struct adapter * pAdapter,
IN HT_CHANNEL_WIDTH ChnlWidth, IN HT_CHANNEL_WIDTH ChnlWidth,
IN unsigned char Offset ); IN unsigned char Offset );
// /* */
// Set FW CMD IO for 8192S. /* Set FW CMD IO for 8192S. */
// /* */
//extern bool HalSetIO8192C( IN struct adapter * Adapter, /* extern bool HalSetIO8192C( IN struct adapter * Adapter, */
// IN IO_TYPE IOType); /* IN IO_TYPE IOType); */
// /* */
// Set A2 entry to fw for 8192S /* Set A2 entry to fw for 8192S */
// /* */
extern void FillA2Entry8192C( IN struct adapter * Adapter, extern void FillA2Entry8192C( IN struct adapter * Adapter,
IN u8 index, IN u8 index,
IN u8* val); IN u8* val);
// /* */
// channel switch related funciton /* channel switch related funciton */
// /* */
//extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer ); /* extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer ); */
void PHY_SwChnl8192D( IN struct adapter * pAdapter, void PHY_SwChnl8192D( IN struct adapter * pAdapter,
IN u8 channel ); IN u8 channel );
// Call after initialization /* Call after initialization */
void PHY_SwChnlPhy8192D( IN struct adapter * pAdapter, void PHY_SwChnlPhy8192D( IN struct adapter * pAdapter,
IN u8 channel ); IN u8 channel );
extern void ChkFwCmdIoDone( IN struct adapter *Adapter); extern void ChkFwCmdIoDone( IN struct adapter *Adapter);
// /* */
// BB/MAC/RF other monitor API /* BB/MAC/RF other monitor API */
// /* */
void PHY_SetMonitorMode8192D(IN struct adapter *pAdapter, void PHY_SetMonitorMode8192D(IN struct adapter *pAdapter,
IN bool bEnableMonitorMode ); IN bool bEnableMonitorMode );
@ -384,9 +383,9 @@ bool PHY_CheckIsLegalRfPath8192D(IN struct adapter *pAdapter,
IN u32 eRFPath ); IN u32 eRFPath );
// /* */
// Modify the value of the hw register when beacon interval be changed. /* Modify the value of the hw register when beacon interval be changed. */
// /* */
void void
rtl8192d_PHY_SetBeaconHwReg( IN struct adapter * Adapter, rtl8192d_PHY_SetBeaconHwReg( IN struct adapter * Adapter,
IN u16 BeaconInterval ); IN u16 BeaconInterval );
@ -460,4 +459,4 @@ PHY_InitPABias92D(IN struct adapter *Adapter);
#define PHY_SetMacReg PHY_SetBBReg #define PHY_SetMacReg PHY_SetBBReg
#define PHY_QueryMacReg PHY_QueryBBReg #define PHY_QueryMacReg PHY_QueryBBReg
#endif // __INC_HAL8192SPHYCFG_H #endif /* __INC_HAL8192SPHYCFG_H */

496
include/Hal8192DPhyReg.h
View file

@ -46,24 +46,24 @@
/*--------------------------Define Parameters-------------------------------*/ /*--------------------------Define Parameters-------------------------------*/
//============================================================ /* */
// 8192S Regsiter offset definition /* 8192S Regsiter offset definition */
//============================================================ /* */
// /* */
// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */
// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
// 3. RF register 0x00-2E /* 3. RF register 0x00-2E */
// 4. Bit Mask for BB/RF register /* 4. Bit Mask for BB/RF register */
// 5. Other defintion for BB/RF R/W /* 5. Other defintion for BB/RF R/W */
// /* */
// /* */
// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */
// 1. Page1(0x100) /* 1. Page1(0x100) */
// /* */
#define rPMAC_Reset 0x100 #define rPMAC_Reset 0x100
#define rPMAC_TxStart 0x104 #define rPMAC_TxStart 0x104
#define rPMAC_TxLegacySIG 0x108 #define rPMAC_TxLegacySIG 0x108
@ -92,27 +92,27 @@
#define rPMAC_CCKCRxRC32OK 0x188 #define rPMAC_CCKCRxRC32OK 0x188
#define rPMAC_TxStatus 0x18c #define rPMAC_TxStatus 0x18c
// /* */
// 2. Page2(0x200) /* 2. Page2(0x200) */
// /* */
// The following two definition are only used for USB interface. /* The following two definition are only used for USB interface. */
#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address. #define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */
#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data. #define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */
// /* */
// 3. Page8(0x800) /* 3. Page8(0x800) */
// /* */
#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */
#define rFPGA0_TxInfo 0x804 // Status report?? #define rFPGA0_TxInfo 0x804 /* Status report?? */
#define rFPGA0_PSDFunction 0x808 #define rFPGA0_PSDFunction 0x808
#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
#define rFPGA0_RFTiming1 0x810 // Useless now #define rFPGA0_RFTiming1 0x810 /* Useless now */
#define rFPGA0_RFTiming2 0x814 #define rFPGA0_RFTiming2 0x814
#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
#define rFPGA0_XA_HSSIParameter2 0x824 #define rFPGA0_XA_HSSIParameter2 0x824
#define rFPGA0_XB_HSSIParameter1 0x828 #define rFPGA0_XB_HSSIParameter1 0x828
#define rFPGA0_XB_HSSIParameter2 0x82c #define rFPGA0_XB_HSSIParameter2 0x82c
@ -120,76 +120,76 @@
#define rFPGA0_XA_LSSIParameter 0x840 #define rFPGA0_XA_LSSIParameter 0x840
#define rFPGA0_XB_LSSIParameter 0x844 #define rFPGA0_XB_LSSIParameter 0x844
#define rFPGA0_RFWakeUpParameter 0x850 // Useless now #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */
#define rFPGA0_RFSleepUpParameter 0x854 #define rFPGA0_RFSleepUpParameter 0x854
#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */
#define rFPGA0_XCD_SwitchControl 0x85c #define rFPGA0_XCD_SwitchControl 0x85c
#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */
#define rFPGA0_XB_RFInterfaceOE 0x864 #define rFPGA0_XB_RFInterfaceOE 0x864
#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */
#define rFPGA0_XCD_RFInterfaceSW 0x874 #define rFPGA0_XCD_RFInterfaceSW 0x874
#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */
#define rFPGA0_XCD_RFParameter 0x87c #define rFPGA0_XCD_RFParameter 0x87c
#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */
#define rFPGA0_AnalogParameter2 0x884 #define rFPGA0_AnalogParameter2 0x884
#define rFPGA0_AnalogParameter3 0x888 #define rFPGA0_AnalogParameter3 0x888
#define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy #define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */
#define rFPGA0_AnalogParameter4 0x88c #define rFPGA0_AnalogParameter4 0x88c
#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */
#define rFPGA0_XB_LSSIReadBack 0x8a4 #define rFPGA0_XB_LSSIReadBack 0x8a4
#define rFPGA0_XC_LSSIReadBack 0x8a8 #define rFPGA0_XC_LSSIReadBack 0x8a8
#define rFPGA0_XD_LSSIReadBack 0x8ac #define rFPGA0_XD_LSSIReadBack 0x8ac
#define rFPGA0_PSDReport 0x8b4 // Useless now #define rFPGA0_PSDReport 0x8b4 /* Useless now */
#define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */
#define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */
#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now RF Interface Readback Value */
#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */
// /* */
// 4. Page9(0x900) /* 4. Page9(0x900) */
// /* */
#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC RF BW Setting?? */
#define rFPGA1_TxBlock 0x904 // Useless now #define rFPGA1_TxBlock 0x904 /* Useless now */
#define rFPGA1_DebugSelect 0x908 // Useless now #define rFPGA1_DebugSelect 0x908 /* Useless now */
#define rFPGA1_TxInfo 0x90c // Useless now // Status report?? #define rFPGA1_TxInfo 0x90c /* Useless now Status report?? */
// /* */
// 5. PageA(0xA00) /* 5. PageA(0xA00) */
// /* */
// Set Control channel to upper or lower. These settings are required only for 40MHz /* Set Control channel to upper or lower. These settings are required only for 40MHz */
#define rCCK0_System 0xa00 #define rCCK0_System 0xa00
#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI #define rCCK0_AFESetting 0xa04 /* Disable init gain now Select RX path by RSSI */
#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain #define rCCK0_CCA 0xa08 /* Disable init gain now Init gain */
#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series #define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
#define rCCK0_RxAGC2 0xa10 //AGC & DAGC #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */
#define rCCK0_RxHP 0xa14 #define rCCK0_RxHP 0xa14
#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold #define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */
#define rCCK0_DSPParameter2 0xa1c //SQ threshold #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
#define rCCK0_TxFilter1 0xa20 #define rCCK0_TxFilter1 0xa20
#define rCCK0_TxFilter2 0xa24 #define rCCK0_TxFilter2 0xa24
#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */
#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */
#define rCCK0_TRSSIReport 0xa50 #define rCCK0_TRSSIReport 0xa50
#define rCCK0_RxReport 0xa54 //0xa57 #define rCCK0_RxReport 0xa54 /* 0xa57 */
#define rCCK0_FACounterLower 0xa5c //0xa5b #define rCCK0_FACounterLower 0xa5c /* 0xa5b */
#define rCCK0_FACounterUpper 0xa58 //0xa5c #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */
// /* */
// PageB(0xB00) /* PageB(0xB00) */
// /* */
#define rPdp_AntA 0xb00 #define rPdp_AntA 0xb00
#define rPdp_AntA_4 0xb04 #define rPdp_AntA_4 0xb04
#define rPdp_AntA_8 0xb08 #define rPdp_AntA_8 0xb08
@ -235,17 +235,17 @@
#define rPm_Rx2_AntB 0xbf4 #define rPm_Rx2_AntB 0xbf4
#define rPm_Rx3_AntB 0xbf8 #define rPm_Rx3_AntB 0xbf8
// /* */
// 6. PageC(0xC00) /* 6. PageC(0xC00) */
// /* */
#define rOFDM0_LSTF 0xc00 #define rOFDM0_LSTF 0xc00
#define rOFDM0_TRxPathEnable 0xc04 #define rOFDM0_TRxPathEnable 0xc04
#define rOFDM0_TRMuxPar 0xc08 #define rOFDM0_TRMuxPar 0xc08
#define rOFDM0_TRSWIsolation 0xc0c #define rOFDM0_TRSWIsolation 0xc0c
#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */
#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */
#define rOFDM0_XBRxAFE 0xc18 #define rOFDM0_XBRxAFE 0xc18
#define rOFDM0_XBRxIQImbalance 0xc1c #define rOFDM0_XBRxIQImbalance 0xc1c
#define rOFDM0_XCRxAFE 0xc20 #define rOFDM0_XCRxAFE 0xc20
@ -253,17 +253,17 @@
#define rOFDM0_XDRxAFE 0xc28 #define rOFDM0_XDRxAFE 0xc28
#define rOFDM0_XDRxIQImbalance 0xc2c #define rOFDM0_XDRxIQImbalance 0xc2c
#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain #define rOFDM0_RxDetector1 0xc30 /* PD,BW & SBD DM tune init gain */
#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */
#define rOFDM0_RxDetector3 0xc38 //Frame Sync. #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */
#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */
#define rOFDM0_RxDSP 0xc40 //Rx Sync Path #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */
#define rOFDM0_ECCAThreshold 0xc4c // energy CCA #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
#define rOFDM0_XAAGCCore1 0xc50 // DIG #define rOFDM0_XAAGCCore1 0xc50 /* DIG */
#define rOFDM0_XAAGCCore2 0xc54 #define rOFDM0_XAAGCCore2 0xc54
#define rOFDM0_XBAGCCore1 0xc58 #define rOFDM0_XBAGCCore1 0xc58
#define rOFDM0_XBAGCCore2 0xc5c #define rOFDM0_XBAGCCore2 0xc5c
@ -277,7 +277,7 @@
#define rOFDM0_AGCRSSITable 0xc78 #define rOFDM0_AGCRSSITable 0xc78
#define rOFDM0_HTSTFAGC 0xc7c #define rOFDM0_HTSTFAGC 0xc7c
#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */
#define rOFDM0_XATxAFE 0xc84 #define rOFDM0_XATxAFE 0xc84
#define rOFDM0_XBTxIQImbalance 0xc88 #define rOFDM0_XBTxIQImbalance 0xc88
#define rOFDM0_XBTxAFE 0xc8c #define rOFDM0_XBTxAFE 0xc8c
@ -298,13 +298,13 @@
#define rOFDM0_FrameSync 0xcf0 #define rOFDM0_FrameSync 0xcf0
#define rOFDM0_DFSReport 0xcf4 #define rOFDM0_DFSReport 0xcf4
// /* */
// 7. PageD(0xD00) /* 7. PageD(0xD00) */
// /* */
#define rOFDM1_LSTF 0xd00 #define rOFDM1_LSTF 0xd00
#define rOFDM1_TRxPathEnable 0xd04 #define rOFDM1_TRxPathEnable 0xd04
#define rOFDM1_CFO 0xd08 // No setting now #define rOFDM1_CFO 0xd08 /* No setting now */
#define rOFDM1_CSI1 0xd10 #define rOFDM1_CSI1 0xd10
#define rOFDM1_SBD 0xd14 #define rOFDM1_SBD 0xd14
#define rOFDM1_CSI2 0xd18 #define rOFDM1_CSI2 0xd18
@ -315,11 +315,11 @@
#define rOFDM1_PseudoNoiseStateCD 0xd54 #define rOFDM1_PseudoNoiseStateCD 0xd54
#define rOFDM1_RxPseudoNoiseWgt 0xd58 #define rOFDM1_RxPseudoNoiseWgt 0xd58
#define rOFDM_PHYCounter1 0xda0 //cca, parity fail #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */
#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */
#define rOFDM_PHYCounter3 0xda8 //MCS not support #define rOFDM_PHYCounter3 0xda8 /* MCS not support */
#define rOFDM_ShortCFOAB 0xdac // No setting now #define rOFDM_ShortCFOAB 0xdac /* No setting now */
#define rOFDM_ShortCFOCD 0xdb0 #define rOFDM_ShortCFOCD 0xdb0
#define rOFDM_LongCFOAB 0xdb4 #define rOFDM_LongCFOAB 0xdb4
#define rOFDM_LongCFOCD 0xdb8 #define rOFDM_LongCFOCD 0xdb8
@ -334,9 +334,9 @@
#define rOFDM_SIGReport 0xddc #define rOFDM_SIGReport 0xddc
// /* */
// 8. PageE(0xE00) /* 8. PageE(0xE00) */
// /* */
#define rTxAGC_A_Rate18_06 0xe00 #define rTxAGC_A_Rate18_06 0xe00
#define rTxAGC_A_Rate54_24 0xe04 #define rTxAGC_A_Rate54_24 0xe04
#define rTxAGC_A_CCK1_Mcs32 0xe08 #define rTxAGC_A_CCK1_Mcs32 0xe08
@ -403,115 +403,115 @@
#define rSleep 0xee0 #define rSleep 0xee0
#define rPMPD_ANAEN 0xeec #define rPMPD_ANAEN 0xeec
// /* */
// 7. RF Register 0x00-0x2E (RF 8256) /* 7. RF Register 0x00-0x2E (RF 8256) */
// RF-0222D 0x00-3F /* RF-0222D 0x00-3F */
// /* */
//Zebra1 /* Zebra1 */
#define rZebra1_HSSIEnable 0x0 // Useless now #define rZebra1_HSSIEnable 0x0 /* Useless now */
#define rZebra1_TRxEnable1 0x1 #define rZebra1_TRxEnable1 0x1
#define rZebra1_TRxEnable2 0x2 #define rZebra1_TRxEnable2 0x2
#define rZebra1_AGC 0x4 #define rZebra1_AGC 0x4
#define rZebra1_ChargePump 0x5 #define rZebra1_ChargePump 0x5
#define rZebra1_Channel 0x7 // RF channel switch #define rZebra1_Channel 0x7 /* RF channel switch */
//#endif /* endif */
#define rZebra1_TxGain 0x8 // Useless now #define rZebra1_TxGain 0x8 /* Useless now */
#define rZebra1_TxLPF 0x9 #define rZebra1_TxLPF 0x9
#define rZebra1_RxLPF 0xb #define rZebra1_RxLPF 0xb
#define rZebra1_RxHPFCorner 0xc #define rZebra1_RxHPFCorner 0xc
//Zebra4 /* Zebra4 */
#define rGlobalCtrl 0 // Useless now #define rGlobalCtrl 0 /* Useless now */
#define rRTL8256_TxLPF 19 #define rRTL8256_TxLPF 19
#define rRTL8256_RxLPF 11 #define rRTL8256_RxLPF 11
//RTL8258 /* RTL8258 */
#define rRTL8258_TxLPF 0x11 // Useless now #define rRTL8258_TxLPF 0x11 /* Useless now */
#define rRTL8258_RxLPF 0x13 #define rRTL8258_RxLPF 0x13
#define rRTL8258_RSSILPF 0xa #define rRTL8258_RSSILPF 0xa
// /* */
// RL6052 Register definition /* RL6052 Register definition */
// /* */
#define RF_AC 0x00 // #define RF_AC 0x00 /* */
#define RF_IQADJ_G1 0x01 // #define RF_IQADJ_G1 0x01 /* */
#define RF_IQADJ_G2 0x02 // #define RF_IQADJ_G2 0x02 /* */
#define RF_BS_PA_APSET_G1_G4 0x03 #define RF_BS_PA_APSET_G1_G4 0x03
#define RF_BS_PA_APSET_G5_G8 0x04 #define RF_BS_PA_APSET_G5_G8 0x04
#define RF_POW_TRSW 0x05 // #define RF_POW_TRSW 0x05 /* */
#define RF_GAIN_RX 0x06 // #define RF_GAIN_RX 0x06 /* */
#define RF_GAIN_TX 0x07 // #define RF_GAIN_TX 0x07 /* */
#define RF_TXM_IDAC 0x08 // #define RF_TXM_IDAC 0x08 /* */
#define RF_IPA_G 0x09 // #define RF_IPA_G 0x09 /* */
#define RF_TXBIAS_G 0x0A #define RF_TXBIAS_G 0x0A
#define RF_TXPA_AG 0x0B #define RF_TXPA_AG 0x0B
#define RF_IPA_A 0x0C // #define RF_IPA_A 0x0C /* */
#define RF_TXBIAS_A 0x0D #define RF_TXBIAS_A 0x0D
#define RF_BS_PA_APSET_G9_G11 0x0E #define RF_BS_PA_APSET_G9_G11 0x0E
#define RF_BS_IQGEN 0x0F // #define RF_BS_IQGEN 0x0F /* */
#define RF_MODE1 0x10 // #define RF_MODE1 0x10 /* */
#define RF_MODE2 0x11 // #define RF_MODE2 0x11 /* */
#define RF_RX_AGC_HP 0x12 // #define RF_RX_AGC_HP 0x12 /* */
#define RF_TX_AGC 0x13 // #define RF_TX_AGC 0x13 /* */
#define RF_BIAS 0x14 // #define RF_BIAS 0x14 /* */
#define RF_IPA 0x15 // #define RF_IPA 0x15 /* */
#define RF_TXBIAS 0x16 // #define RF_TXBIAS 0x16 /* */
#define RF_POW_ABILITY 0x17 // #define RF_POW_ABILITY 0x17 /* */
#define RF_MODE_AG 0x18 // #define RF_MODE_AG 0x18 /* */
#define rRfChannel 0x18 // RF channel and BW switch #define rRfChannel 0x18 /* RF channel and BW switch */
#define RF_CHNLBW 0x18 // RF channel and BW switch #define RF_CHNLBW 0x18 /* RF channel and BW switch */
#define RF_TOP 0x19 // #define RF_TOP 0x19 /* */
#define RF_RX_G1 0x1A // #define RF_RX_G1 0x1A /* */
#define RF_RX_G2 0x1B // #define RF_RX_G2 0x1B /* */
#define RF_RX_BB2 0x1C // #define RF_RX_BB2 0x1C /* */
#define RF_RX_BB1 0x1D // #define RF_RX_BB1 0x1D /* */
#define RF_RCK1 0x1E // #define RF_RCK1 0x1E /* */
#define RF_RCK2 0x1F // #define RF_RCK2 0x1F /* */
#define RF_TX_G1 0x20 // #define RF_TX_G1 0x20 /* */
#define RF_TX_G2 0x21 // #define RF_TX_G2 0x21 /* */
#define RF_TX_G3 0x22 // #define RF_TX_G3 0x22 /* */
#define RF_TX_BB1 0x23 // #define RF_TX_BB1 0x23 /* */
#define RF_T_METER 0x42 // #define RF_T_METER 0x42 /* */
#define RF_SYN_G1 0x25 // RF TX Power control #define RF_SYN_G1 0x25 /* RF TX Power control */
#define RF_SYN_G2 0x26 // RF TX Power control #define RF_SYN_G2 0x26 /* RF TX Power control */
#define RF_SYN_G3 0x27 // RF TX Power control #define RF_SYN_G3 0x27 /* RF TX Power control */
#define RF_SYN_G4 0x28 // RF TX Power control #define RF_SYN_G4 0x28 /* RF TX Power control */
#define RF_SYN_G5 0x29 // RF TX Power control #define RF_SYN_G5 0x29 /* RF TX Power control */
#define RF_SYN_G6 0x2A // RF TX Power control #define RF_SYN_G6 0x2A /* RF TX Power control */
#define RF_SYN_G7 0x2B // RF TX Power control #define RF_SYN_G7 0x2B /* RF TX Power control */
#define RF_SYN_G8 0x2C // RF TX Power control #define RF_SYN_G8 0x2C /* RF TX Power control */
#define RF_RCK_OS 0x30 // RF TX PA control #define RF_RCK_OS 0x30 /* RF TX PA control */
#define RF_TXPA_G1 0x31 // RF TX PA control #define RF_TXPA_G1 0x31 /* RF TX PA control */
#define RF_TXPA_G2 0x32 // RF TX PA control #define RF_TXPA_G2 0x32 /* RF TX PA control */
#define RF_TXPA_G3 0x33 // RF TX PA control #define RF_TXPA_G3 0x33 /* RF TX PA control */
#define RF_LOBF_9 0x38 #define RF_LOBF_9 0x38
#define RF_RXRF_A3 0x3C // #define RF_RXRF_A3 0x3C /* */
#define RF_TRSW 0x3F #define RF_TRSW 0x3F
#define RF_TXRF_A2 0x41 #define RF_TXRF_A2 0x41
#define RF_TXPA_G4 0x46 #define RF_TXPA_G4 0x46
#define RF_TXPA_A4 0x4B #define RF_TXPA_A4 0x4B
// /* */
//Bit Mask /* Bit Mask */
// /* */
// 1. Page1(0x100) /* 1. Page1(0x100) */
#define bBBResetB 0x100 // Useless now? #define bBBResetB 0x100 /* Useless now? */
#define bGlobalResetB 0x200 #define bGlobalResetB 0x200
#define bOFDMTxStart 0x4 #define bOFDMTxStart 0x4
#define bCCKTxStart 0x8 #define bCCKTxStart 0x8
@ -558,36 +558,36 @@
#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
// 2. Page8(0x800) /* 2. Page8(0x800) */
#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */
#define bJapanMode 0x2 #define bJapanMode 0x2
#define bCCKTxSC 0x30 #define bCCKTxSC 0x30
#define bCCKEn 0x1000000 #define bCCKEn 0x1000000
#define bOFDMEn 0x2000000 #define bOFDMEn 0x2000000
#define bOFDMRxADCPhase 0x10000 // Useless now #define bOFDMRxADCPhase 0x10000 /* Useless now */
#define bOFDMTxDACPhase 0x40000 #define bOFDMTxDACPhase 0x40000
#define bXATxAGC 0x3f #define bXATxAGC 0x3f
#define bAntennaSelect 0x0300 #define bAntennaSelect 0x0300
#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */
#define bXCTxAGC 0xf000 #define bXCTxAGC 0xf000
#define bXDTxAGC 0xf0000 #define bXDTxAGC 0xf0000
#define bPAStart 0xf0000000 // Useless now #define bPAStart 0xf0000000 /* Useless now */
#define bTRStart 0x00f00000 #define bTRStart 0x00f00000
#define bRFStart 0x0000f000 #define bRFStart 0x0000f000
#define bBBStart 0x000000f0 #define bBBStart 0x000000f0
#define bBBCCKStart 0x0000000f #define bBBCCKStart 0x0000000f
#define bPAEnd 0xf //Reg0x814 #define bPAEnd 0xf /* Reg0x814 */
#define bTREnd 0x0f000000 #define bTREnd 0x0f000000
#define bRFEnd 0x000f0000 #define bRFEnd 0x000f0000
#define bCCAMask 0x000000f0 //T2R #define bCCAMask 0x000000f0 /* T2R */
#define bR2RCCAMask 0x00000f00 #define bR2RCCAMask 0x00000f00
#define bHSSI_R2TDelay 0xf8000000 #define bHSSI_R2TDelay 0xf8000000
#define bHSSI_T2RDelay 0xf80000 #define bHSSI_T2RDelay 0xf80000
#define bContTxHSSI 0x400 //chane gain at continue Tx #define bContTxHSSI 0x400 /* chane gain at continue Tx */
#define bIGFromCCK 0x200 #define bIGFromCCK 0x200
#define bAGCAddress 0x3f #define bAGCAddress 0x3f
#define bRxHPTx 0x7000 #define bRxHPTx 0x7000
@ -596,11 +596,11 @@
#define bAGCTxCode 0xc00000 #define bAGCTxCode 0xc00000
#define bAGCRxCode 0x300000 #define bAGCRxCode 0x300000
#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
#define b3WireAddressLength 0x400 #define b3WireAddressLength 0x400
#define b3WireRFPowerDown 0x1 // Useless now #define b3WireRFPowerDown 0x1 /* Useless now */
//#define bHWSISelect 0x8 /* define bHWSISelect 0x8 */
#define b5GPAPEPolarity 0x40000000 #define b5GPAPEPolarity 0x40000000
#define b2GPAPEPolarity 0x80000000 #define b2GPAPEPolarity 0x80000000
#define bRFSW_TxDefaultAnt 0x3 #define bRFSW_TxDefaultAnt 0x3
@ -613,9 +613,9 @@
#define bRFSI_3WireRW 0x8 #define bRFSI_3WireRW 0x8
#define bRFSI_3Wire 0xf #define bRFSI_3Wire 0xf
#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
#define bRFSI_TRSW 0x20 // Useless now #define bRFSI_TRSW 0x20 /* Useless now */
#define bRFSI_TRSWB 0x40 #define bRFSI_TRSWB 0x40
#define bRFSI_ANTSW 0x100 #define bRFSI_ANTSW 0x100
#define bRFSI_ANTSWB 0x200 #define bRFSI_ANTSWB 0x200
@ -639,14 +639,14 @@
#define bLSIG_Parity 0x20 #define bLSIG_Parity 0x20
#define bCCKRxPhase 0x4 #define bCCKRxPhase 0x4
#define bLSSIReadAddress 0x7f800000 // T65 RF #define bLSSIReadAddress 0x7f800000 /* T65 RF */
#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */
#define bLSSIReadBackData 0xfffff // T65 RF #define bLSSIReadBackData 0xfffff /* T65 RF */
#define bLSSIReadOKFlag 0x1000 // Useless now #define bLSSIReadOKFlag 0x1000 /* Useless now */
#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */
#define bRegulator0Standby 0x1 #define bRegulator0Standby 0x1
#define bRegulatorPLLStandby 0x2 #define bRegulatorPLLStandby 0x2
#define bRegulator1Standby 0x4 #define bRegulator1Standby 0x4
@ -660,17 +660,17 @@
#define bDA6DebugMode 0x20000 #define bDA6DebugMode 0x20000
#define bDA6Swing 0x380000 #define bDA6Swing 0x380000
#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ #define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
#define b80MClkDelay 0x18000000 // Useless #define b80MClkDelay 0x18000000 /* Useless */
#define bAFEWatchDogEnable 0x20000000 #define bAFEWatchDogEnable 0x20000000
#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap #define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
#define bXtalCap23 0x3 #define bXtalCap23 0x3
#define bXtalCap92x 0x0f000000 #define bXtalCap92x 0x0f000000
#define bXtalCap 0x0f000000 #define bXtalCap 0x0f000000
#define bIntDifClkEnable 0x400 // Useless #define bIntDifClkEnable 0x400 /* Useless */
#define bExtSigClkEnable 0x800 #define bExtSigClkEnable 0x800
#define bBandgapMbiasPowerUp 0x10000 #define bBandgapMbiasPowerUp 0x10000
#define bAD11SHGain 0xc0000 #define bAD11SHGain 0xc0000
@ -704,12 +704,12 @@
#define bPSDSineToneScale 0x7f000000 #define bPSDSineToneScale 0x7f000000
#define bPSDReport 0xffff #define bPSDReport 0xffff
// 3. Page9(0x900) /* 3. Page9(0x900) */
#define bOFDMTxSC 0x30000000 // Useless #define bOFDMTxSC 0x30000000 /* Useless */
#define bCCKTxOn 0x1 #define bCCKTxOn 0x1
#define bOFDMTxOn 0x2 #define bOFDMTxOn 0x2
#define bDebugPage 0xfff //reset debug page and also HWord, LWord #define bDebugPage 0xfff /* reset debug page and also HWord, LWord */
#define bDebugItem 0xff //reset debug page and LWord #define bDebugItem 0xff /* reset debug page and LWord */
#define bAntL 0x10 #define bAntL 0x10
#define bAntNonHT 0x100 #define bAntNonHT 0x100
#define bAntHT1 0x1000 #define bAntHT1 0x1000
@ -717,14 +717,14 @@
#define bAntHT1S1 0x100000 #define bAntHT1S1 0x100000
#define bAntNonHTS1 0x1000000 #define bAntNonHTS1 0x1000000
// 4. PageA(0xA00) /* 4. PageA(0xA00) */
#define bCCKBBMode 0x3 // Useless #define bCCKBBMode 0x3 /* Useless */
#define bCCKTxPowerSaving 0x80 #define bCCKTxPowerSaving 0x80
#define bCCKRxPowerSaving 0x40 #define bCCKRxPowerSaving 0x40
#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */
#define bCCKScramble 0x8 // Useless #define bCCKScramble 0x8 /* Useless */
#define bCCKAntDiversity 0x8000 #define bCCKAntDiversity 0x8000
#define bCCKCarrierRecovery 0x4000 #define bCCKCarrierRecovery 0x4000
#define bCCKTxRate 0x3000 #define bCCKTxRate 0x3000
@ -740,7 +740,7 @@
#define bCCKBistMode 0x80000000 #define bCCKBistMode 0x80000000
#define bCCKCCAMask 0x40000000 #define bCCKCCAMask 0x40000000
#define bCCKTxDACPhase 0x4 #define bCCKTxDACPhase 0x4
#define bCCKRxADCPhase 0x20000000 //r_rx_clk #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
#define bCCKr_cp_mode0 0x0100 #define bCCKr_cp_mode0 0x0100
#define bCCKTxDCOffset 0xf0 #define bCCKTxDCOffset 0xf0
#define bCCKRxDCOffset 0xf #define bCCKRxDCOffset 0xf
@ -754,12 +754,11 @@
#define bCCKRxIG 0x7f00 #define bCCKRxIG 0x7f00
#define bCCKLNAPolarity 0x800000 #define bCCKLNAPolarity 0x800000
#define bCCKRx1stGain 0x7f0000 #define bCCKRx1stGain 0x7f0000
#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */
#define bCCKRxAGCSatLevel 0x1f000000 #define bCCKRxAGCSatLevel 0x1f000000
#define bCCKRxAGCSatCount 0xe0 #define bCCKRxAGCSatCount 0xe0
#define bCCKRxRFSettle 0x1f //AGCsamp_dly #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */
#define bCCKFixedRxAGC 0x8000 #define bCCKFixedRxAGC 0x8000
//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
#define bCCKAntennaPolarity 0x2000 #define bCCKAntennaPolarity 0x2000
#define bCCKTxFilterType 0x0c00 #define bCCKTxFilterType 0x0c00
#define bCCKRxAGCReportType 0x0300 #define bCCKRxAGCReportType 0x0300
@ -798,8 +797,8 @@
#define bCCKDefaultRxPath 0xc000000 #define bCCKDefaultRxPath 0xc000000
#define bCCKOptionRxPath 0x3000000 #define bCCKOptionRxPath 0x3000000
// 5. PageC(0xC00) /* 5. PageC(0xC00) */
#define bNumOfSTF 0x3 // Useless #define bNumOfSTF 0x3 /* Useless */
#define bShift_L 0xc0 #define bShift_L 0xc0
#define bGI_TH 0xc #define bGI_TH 0xc
#define bRxPathA 0x1 #define bRxPathA 0x1
@ -900,8 +899,8 @@
#define bRxHP_BBP1 0x7000 #define bRxHP_BBP1 0x7000
#define bRxHP_BBP2 0x70000 #define bRxHP_BBP2 0x70000
#define bRxHP_BBP3 0x700000 #define bRxHP_BBP3 0x700000
#define bRSSI_H 0x7f0000 //the threshold for high power #define bRSSI_H 0x7f0000 /* the threshold for high power */
#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity #define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */
#define bRxSettle_TRSW 0x7 #define bRxSettle_TRSW 0x7
#define bRxSettle_LNA 0x38 #define bRxSettle_LNA 0x38
#define bRxSettle_RSSI 0x1c0 #define bRxSettle_RSSI 0x1c0
@ -935,7 +934,7 @@
#define bRxPD_Delay_TH1 0x38 #define bRxPD_Delay_TH1 0x38
#define bRxPD_Delay_TH2 0x1c0 #define bRxPD_Delay_TH2 0x1c0
#define bRxPD_DC_COUNT_MAX 0x600 #define bRxPD_DC_COUNT_MAX 0x600
//#define bRxMF_Hold 0x3800 /* define bRxMF_Hold 0x3800 */
#define bRxPD_Delay_TH 0x8000 #define bRxPD_Delay_TH 0x8000
#define bRxProcess_Delay 0xf0000 #define bRxProcess_Delay 0xf0000
#define bRxSearchrange_GI2_Early 0x700000 #define bRxSearchrange_GI2_Early 0x700000
@ -956,8 +955,8 @@
#define bTRSWIsolation_D 0x7f000000 #define bTRSWIsolation_D 0x7f000000
#define bExtLNAGain 0x7c00 #define bExtLNAGain 0x7c00
// 6. PageE(0xE00) /* 6. PageE(0xE00) */
#define bSTBCEn 0x4 // Useless #define bSTBCEn 0x4 /* Useless */
#define bAntennaMapping 0x10 #define bAntennaMapping 0x10
#define bNss 0x20 #define bNss 0x20
#define bCFOAntSumD 0x200 #define bCFOAntSumD 0x200
@ -966,12 +965,12 @@
#define bOFDMContinueTx 0x10000000 #define bOFDMContinueTx 0x10000000
#define bOFDMSingleCarrier 0x20000000 #define bOFDMSingleCarrier 0x20000000
#define bOFDMSingleTone 0x40000000 #define bOFDMSingleTone 0x40000000
//#define bRxPath1 0x01 /* define bRxPath1 0x01 */
//#define bRxPath2 0x02 /* define bRxPath2 0x02 */
//#define bRxPath3 0x04 /* define bRxPath3 0x04 */
//#define bRxPath4 0x08 /* define bRxPath4 0x08 */
//#define bTxPath1 0x10 /* define bTxPath1 0x10 */
//#define bTxPath2 0x20 /* define bTxPath2 0x20 */
#define bHTDetect 0x100 #define bHTDetect 0x100
#define bCFOEn 0x10000 #define bCFOEn 0x10000
#define bCFOValue 0xfff00000 #define bCFOValue 0xfff00000
@ -984,8 +983,8 @@
#define bCounter_MCSNoSupport 0xffff #define bCounter_MCSNoSupport 0xffff
#define bCounter_FastSync 0xffff #define bCounter_FastSync 0xffff
#define bShortCFO 0xfff #define bShortCFO 0xfff
#define bShortCFOTLength 12 //total #define bShortCFOTLength 12 /* total */
#define bShortCFOFLength 11 //fraction #define bShortCFOFLength 11 /* fraction */
#define bLongCFO 0x7ff #define bLongCFO 0x7ff
#define bLongCFOTLength 11 #define bLongCFOTLength 11
#define bLongCFOFLength 11 #define bLongCFOFLength 11
@ -1020,7 +1019,7 @@
#define bPWDB 0xff00 #define bPWDB 0xff00
#define bSGIEN 0x10000 #define bSGIEN 0x10000
#define bSFactorQAM1 0xf // Useless #define bSFactorQAM1 0xf /* Useless */
#define bSFactorQAM2 0xf0 #define bSFactorQAM2 0xf0
#define bSFactorQAM3 0xf00 #define bSFactorQAM3 0xf00
#define bSFactorQAM4 0xf000 #define bSFactorQAM4 0xf000
@ -1031,7 +1030,7 @@
#define bSFactorQAM9 0xf0000000 #define bSFactorQAM9 0xf0000000
#define bCSIScheme 0x100000 #define bCSIScheme 0x100000
#define bNoiseLvlTopSet 0x3 // Useless #define bNoiseLvlTopSet 0x3 /* Useless */
#define bChSmooth 0x4 #define bChSmooth 0x4
#define bChSmoothCfg1 0x38 #define bChSmoothCfg1 0x38
#define bChSmoothCfg2 0x1c0 #define bChSmoothCfg2 0x1c0
@ -1040,7 +1039,7 @@
#define bMRCMode 0x800000 #define bMRCMode 0x800000
#define bTHEVMCfg 0x7000000 #define bTHEVMCfg 0x7000000
#define bLoopFitType 0x1 // Useless #define bLoopFitType 0x1 /* Useless */
#define bUpdCFO 0x40 #define bUpdCFO 0x40
#define bUpdCFOOffData 0x80 #define bUpdCFOOffData 0x80
#define bAdvUpdCFO 0x100 #define bAdvUpdCFO 0x100
@ -1056,8 +1055,8 @@
#define bUChCfg 0x7000000 #define bUChCfg 0x7000000
#define bUpdEqz 0x8000000 #define bUpdEqz 0x8000000
//Rx Pseduo noise /* Rx Pseduo noise */
#define bRxPesudoNoiseOn 0x20000000 // Useless #define bRxPesudoNoiseOn 0x20000000 /* Useless */
#define bRxPesudoNoise_A 0xff #define bRxPesudoNoise_A 0xff
#define bRxPesudoNoise_B 0xff00 #define bRxPesudoNoise_B 0xff00
#define bRxPesudoNoise_C 0xff0000 #define bRxPesudoNoise_C 0xff0000
@ -1067,9 +1066,9 @@
#define bPesudoNoiseState_C 0xffff #define bPesudoNoiseState_C 0xffff
#define bPesudoNoiseState_D 0xffff0000 #define bPesudoNoiseState_D 0xffff0000
//7. RF Register /* 7. RF Register */
//Zebra1 /* Zebra1 */
#define bZebra1_HSSIEnable 0x8 // Useless #define bZebra1_HSSIEnable 0x8 /* Useless */
#define bZebra1_TRxControl 0xc00 #define bZebra1_TRxControl 0xc00
#define bZebra1_TRxGainSetting 0x07f #define bZebra1_TRxGainSetting 0x07f
#define bZebra1_RxCorner 0xc00 #define bZebra1_RxCorner 0xc00
@ -1079,24 +1078,24 @@
#define bZebra1_TxLPFBW 0x400 #define bZebra1_TxLPFBW 0x400
#define bZebra1_RxLPFBW 0x600 #define bZebra1_RxLPFBW 0x600
//Zebra4 /* Zebra4 */
#define bRTL8256RegModeCtrl1 0x100 // Useless #define bRTL8256RegModeCtrl1 0x100 /* Useless */
#define bRTL8256RegModeCtrl0 0x40 #define bRTL8256RegModeCtrl0 0x40
#define bRTL8256_TxLPFBW 0x18 #define bRTL8256_TxLPFBW 0x18
#define bRTL8256_RxLPFBW 0x600 #define bRTL8256_RxLPFBW 0x600
//RTL8258 /* RTL8258 */
#define bRTL8258_TxLPFBW 0xc // Useless #define bRTL8258_TxLPFBW 0xc /* Useless */
#define bRTL8258_RxLPFBW 0xc00 #define bRTL8258_RxLPFBW 0xc00
#define bRTL8258_RSSILPFBW 0xc0 #define bRTL8258_RSSILPFBW 0xc0
// /* */
// Other Definition /* Other Definition */
// /* */
//byte endable for sb_write /* byte endable for sb_write */
#define bByte0 0x1 // Useless #define bByte0 0x1 /* Useless */
#define bByte1 0x2 #define bByte1 0x2
#define bByte2 0x4 #define bByte2 0x4
#define bByte3 0x8 #define bByte3 0x8
@ -1104,8 +1103,8 @@
#define bWord1 0xc #define bWord1 0xc
#define bDWord 0xf #define bDWord 0xf
//for PutRegsetting & GetRegSetting BitMask /* for PutRegsetting & GetRegSetting BitMask */
#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
#define bMaskByte1 0xff00 #define bMaskByte1 0xff00
#define bMaskByte2 0xff0000 #define bMaskByte2 0xff0000
#define bMaskByte3 0xff000000 #define bMaskByte3 0xff000000
@ -1117,50 +1116,47 @@
#define bMaskOFDM_D 0xffc00000 #define bMaskOFDM_D 0xffc00000
#define bMaskCCK 0x3f3f3f3f #define bMaskCCK 0x3f3f3f3f
//for PutRFRegsetting & GetRFRegSetting BitMask /* for PutRFRegsetting & GetRFRegSetting BitMask */
//#define bMask12Bits 0xfffff // RF Reg mask bits
//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF
#define bRFRegOffsetMask 0xfffff #define bRFRegOffsetMask 0xfffff
//#define bRFRegOffsetMask 0xfff
//MAC0 will wirte PHY1 /* MAC0 will wirte PHY1 */
#define MAC0_ACCESS_PHY1 0x4000 #define MAC0_ACCESS_PHY1 0x4000
//MAC1 will wirte PHY0 /* MAC1 will wirte PHY0 */
#define MAC1_ACCESS_PHY0 0x2000 #define MAC1_ACCESS_PHY0 0x2000
#define bEnable 0x1 // Useless #define bEnable 0x1 /* Useless */
#define bDisable 0x0 #define bDisable 0x0
#define LeftAntenna 0x0 // Useless #define LeftAntenna 0x0 /* Useless */
#define RightAntenna 0x1 #define RightAntenna 0x1
#define tCheckTxStatus 500 //500ms // Useless #define tCheckTxStatus 500 /* 500ms Useless */
#define tUpdateRxCounter 100 //100ms #define tUpdateRxCounter 100 /* 100ms */
#define rateCCK 0 // Useless #define rateCCK 0 /* Useless */
#define rateOFDM 1 #define rateOFDM 1
#define rateHT 2 #define rateHT 2
//define Register-End /* define Register-End */
#define bPMAC_End 0x1ff // Useless #define bPMAC_End 0x1ff /* Useless */
#define bFPGAPHY0_End 0x8ff #define bFPGAPHY0_End 0x8ff
#define bFPGAPHY1_End 0x9ff #define bFPGAPHY1_End 0x9ff
#define bCCKPHY0_End 0xaff #define bCCKPHY0_End 0xaff
#define bOFDMPHY0_End 0xcff #define bOFDMPHY0_End 0xcff
#define bOFDMPHY1_End 0xdff #define bOFDMPHY1_End 0xdff
//define max debug item in each debug page /* define max debug item in each debug page */
//#define bMaxItem_FPGA_PHY0 0x9 /* define bMaxItem_FPGA_PHY0 0x9 */
//#define bMaxItem_FPGA_PHY1 0x3 /* define bMaxItem_FPGA_PHY1 0x3 */
//#define bMaxItem_PHY_11B 0x16 /* define bMaxItem_PHY_11B 0x16 */
//#define bMaxItem_OFDM_PHY0 0x29 /* define bMaxItem_OFDM_PHY0 0x29 */
//#define bMaxItem_OFDM_PHY1 0x0 /* define bMaxItem_OFDM_PHY1 0x0 */
#define bPMACControl 0x0 // Useless #define bPMACControl 0x0 /* Useless */
#define bWMACControl 0x1 #define bWMACControl 0x1
#define bWNICControl 0x2 #define bWNICControl 0x2
#define PathA 0x0 // Useless #define PathA 0x0 /* Useless */
#define PathB 0x1 #define PathB 0x1
#define PathC 0x2 #define PathC 0x2
#define PathD 0x3 #define PathD 0x3
@ -1168,4 +1164,4 @@
/*--------------------------Define Parameters-------------------------------*/ /*--------------------------Define Parameters-------------------------------*/
#endif //__INC_HAL8192SPHYREG_H #endif /* __INC_HAL8192SPHYREG_H */

6
include/Hal8723APhyReg.h
View file

@ -22,9 +22,9 @@
#include <Hal8192CPhyReg.h> #include <Hal8192CPhyReg.h>
// /* */
// PageB(0xB00) /* PageB(0xB00) */
// /* */
#define rPdp_AntA 0xb00 #define rPdp_AntA 0xb00
#define rPdp_AntA_4 0xb04 #define rPdp_AntA_4 0xb04
#define rPdp_AntA_8 0xb08 #define rPdp_AntA_8 0xb08

24
include/Hal8723PwrSeq.h
View file

@ -37,7 +37,7 @@
#define RTL8723A_TRANS_CARDEMU_TO_ACT \ #define RTL8723A_TRANS_CARDEMU_TO_ACT \
/* format */ \ /* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \ {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \ {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
@ -53,7 +53,7 @@
#define RTL8723A_TRANS_ACT_TO_CARDEMU \ #define RTL8723A_TRANS_ACT_TO_CARDEMU \
/* format */ \ /* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\ {0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
@ -64,7 +64,7 @@
#define RTL8723A_TRANS_CARDEMU_TO_SUS \ #define RTL8723A_TRANS_CARDEMU_TO_SUS \
/* format */ \ /* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
@ -75,7 +75,7 @@
#define RTL8723A_TRANS_SUS_TO_CARDEMU \ #define RTL8723A_TRANS_SUS_TO_CARDEMU \
/* format */ \ /* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
@ -84,7 +84,7 @@
#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS \ #define RTL8723A_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \ /* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
@ -95,7 +95,7 @@
#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU \ #define RTL8723A_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \ /* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
@ -107,7 +107,7 @@
#define RTL8723A_TRANS_CARDEMU_TO_PDN \ #define RTL8723A_TRANS_CARDEMU_TO_PDN \
/* format */ \ /* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
@ -115,12 +115,12 @@
#define RTL8723A_TRANS_PDN_TO_CARDEMU \ #define RTL8723A_TRANS_PDN_TO_CARDEMU \
/* format */ \ /* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
#define RTL8723A_TRANS_ACT_TO_LPS \ #define RTL8723A_TRANS_ACT_TO_LPS \
/* format */ \ /* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
@ -138,7 +138,7 @@
#define RTL8723A_TRANS_LPS_TO_ACT \ #define RTL8723A_TRANS_LPS_TO_ACT \
/* format */ \ /* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
@ -153,8 +153,8 @@
#define RTL8723A_TRANS_END \ #define RTL8723A_TRANS_END \
/* format */ \ /* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0},
extern struct wl_pwr_cfg rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS]; extern struct wl_pwr_cfg rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS];

62
include/HalPwrSeqCmd.h
View file

@ -23,51 +23,51 @@
#include <drv_types.h> #include <drv_types.h>
/*---------------------------------------------*/ /*---------------------------------------------*/
//3 The value of cmd: 4 bits /* 3 The value of cmd: 4 bits */
/*---------------------------------------------*/ /*---------------------------------------------*/
#define PWR_CMD_READ 0x00 #define PWR_CMD_READ 0x00
// offset: the read register offset /* offset: the read register offset */
// msk: the mask of the read value /* msk: the mask of the read value */
// value: N/A, left by 0 /* value: N/A, left by 0 */
// note: dirver shall implement this function by read & msk /* note: dirver shall implement this function by read & msk */
#define PWR_CMD_WRITE 0x01 #define PWR_CMD_WRITE 0x01
// offset: the read register offset /* offset: the read register offset */
// msk: the mask of the write bits /* msk: the mask of the write bits */
// value: write value /* value: write value */
// note: driver shall implement this cmd by read & msk after write /* note: driver shall implement this cmd by read & msk after write */
#define PWR_CMD_POLLING 0x02 #define PWR_CMD_POLLING 0x02
// offset: the read register offset /* offset: the read register offset */
// msk: the mask of the polled value /* msk: the mask of the polled value */
// value: the value to be polled, masked by the msd field. /* value: the value to be polled, masked by the msd field. */
// note: driver shall implement this cmd by /* note: driver shall implement this cmd by */
// do{ /* do{ */
// if( (Read(offset) & msk) == (value & msk) ) /* if( (Read(offset) & msk) == (value & msk) ) */
// break; /* break; */
// } while(not timeout); /* } while(not timeout); */
#define PWR_CMD_DELAY 0x03 #define PWR_CMD_DELAY 0x03
// offset: the value to delay /* offset: the value to delay */
// msk: N/A /* msk: N/A */
// value: the unit of delay, 0: us, 1: ms /* value: the unit of delay, 0: us, 1: ms */
#define PWR_CMD_END 0x04 #define PWR_CMD_END 0x04
// offset: N/A /* offset: N/A */
// msk: N/A /* msk: N/A */
// value: N/A /* value: N/A */
/*---------------------------------------------*/ /*---------------------------------------------*/
//3 The value of base: 4 bits /* 3 The value of base: 4 bits */
/*---------------------------------------------*/ /*---------------------------------------------*/
// define the base address of each block /* define the base address of each block */
#define PWR_BASEADDR_MAC 0x00 #define PWR_BASEADDR_MAC 0x00
#define PWR_BASEADDR_USB 0x01 #define PWR_BASEADDR_USB 0x01
#define PWR_BASEADDR_PCIE 0x02 #define PWR_BASEADDR_PCIE 0x02
#define PWR_BASEADDR_SDIO 0x03 #define PWR_BASEADDR_SDIO 0x03
/*---------------------------------------------*/ /*---------------------------------------------*/
//3 The value of interface_msk: 4 bits /* 3 The value of interface_msk: 4 bits */
/*---------------------------------------------*/ /*---------------------------------------------*/
#define PWR_INTF_SDIO_MSK BIT(0) #define PWR_INTF_SDIO_MSK BIT(0)
#define PWR_INTF_USB_MSK BIT(1) #define PWR_INTF_USB_MSK BIT(1)
@ -75,14 +75,14 @@
#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) #define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
/*---------------------------------------------*/ /*---------------------------------------------*/
//3 The value of fab_msk: 4 bits /* 3 The value of fab_msk: 4 bits */
/*---------------------------------------------*/ /*---------------------------------------------*/
#define PWR_FAB_TSMC_MSK BIT(0) #define PWR_FAB_TSMC_MSK BIT(0)
#define PWR_FAB_UMC_MSK BIT(1) #define PWR_FAB_UMC_MSK BIT(1)
#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) #define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
/*---------------------------------------------*/ /*---------------------------------------------*/
//3 The value of cut_msk: 8 bits /* 3 The value of cut_msk: 8 bits */
/*---------------------------------------------*/ /*---------------------------------------------*/
#define PWR_CUT_TESTCHIP_MSK BIT(0) #define PWR_CUT_TESTCHIP_MSK BIT(0)
#define PWR_CUT_A_MSK BIT(1) #define PWR_CUT_A_MSK BIT(1)
@ -122,9 +122,9 @@ struct wl_pwr_cfg {
#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value #define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
//================================================================================ /* */
// Prototype of protected function. /* Prototype of protected function. */
//================================================================================ /* */
u8 HalPwrSeqCmdParsing( u8 HalPwrSeqCmdParsing(
struct adapter * padapter, struct adapter * padapter,
u8 CutVersion, u8 CutVersion,

38
include/HalVerDef.h
View file

@ -23,7 +23,7 @@
#define true true #define true true
#define false false #define false false
// HAL_IC_TYPE_E /* HAL_IC_TYPE_E */
typedef enum tag_HAL_IC_Type_Definition typedef enum tag_HAL_IC_Type_Definition
{ {
CHIP_8192S = 0, CHIP_8192S = 0,
@ -39,7 +39,7 @@ typedef enum tag_HAL_IC_Type_Definition
CHIP_8192E = 10, CHIP_8192E = 10,
}HAL_IC_TYPE_E; }HAL_IC_TYPE_E;
//HAL_CHIP_TYPE_E /* HAL_CHIP_TYPE_E */
typedef enum tag_HAL_CHIP_Type_Definition typedef enum tag_HAL_CHIP_Type_Definition
{ {
TEST_CHIP = 0, TEST_CHIP = 0,
@ -47,7 +47,7 @@ typedef enum tag_HAL_CHIP_Type_Definition
FPGA = 2, FPGA = 2,
}HAL_CHIP_TYPE_E; }HAL_CHIP_TYPE_E;
//HAL_CUT_VERSION_E /* HAL_CUT_VERSION_E */
typedef enum tag_HAL_Cut_Version_Definition typedef enum tag_HAL_Cut_Version_Definition
{ {
A_CUT_VERSION = 0, A_CUT_VERSION = 0,
@ -63,7 +63,7 @@ typedef enum tag_HAL_Cut_Version_Definition
K_CUT_VERSION = 10, K_CUT_VERSION = 10,
}HAL_CUT_VERSION_E; }HAL_CUT_VERSION_E;
// HAL_Manufacturer /* HAL_Manufacturer */
typedef enum tag_HAL_Manufacturer_Version_Definition typedef enum tag_HAL_Manufacturer_Version_Definition
{ {
CHIP_VENDOR_TSMC = 0, CHIP_VENDOR_TSMC = 0,
@ -92,10 +92,10 @@ typedef struct tag_HAL_VERSION
u8 ROMVer; u8 ROMVer;
}HAL_VERSION,*PHAL_VERSION; }HAL_VERSION,*PHAL_VERSION;
//VERSION_8192C VersionID; /* VERSION_8192C VersionID; */
//HAL_VERSION VersionID; /* HAL_VERSION VersionID; */
// Get element /* Get element */
#define GET_CVID_IC_TYPE(version) (((version).ICType)) #define GET_CVID_IC_TYPE(version) (((version).ICType))
#define GET_CVID_CHIP_TYPE(version) (((version).ChipType)) #define GET_CVID_CHIP_TYPE(version) (((version).ChipType))
#define GET_CVID_RF_TYPE(version) (((version).RFType)) #define GET_CVID_RF_TYPE(version) (((version).RFType))
@ -103,22 +103,22 @@ typedef struct tag_HAL_VERSION
#define GET_CVID_CUT_VERSION(version) (((version).CUTVersion)) #define GET_CVID_CUT_VERSION(version) (((version).CUTVersion))
#define GET_CVID_ROM_VERSION(version) (((version).ROMVer) & ROM_VERSION_MASK) #define GET_CVID_ROM_VERSION(version) (((version).ROMVer) & ROM_VERSION_MASK)
//---------------------------------------------------------------------------- /* */
//Common Macro. -- /* Common Macro. -- */
//---------------------------------------------------------------------------- /* */
//HAL_VERSION VersionID /* HAL_VERSION VersionID */
// HAL_IC_TYPE_E /* HAL_IC_TYPE_E */
#define IS_81XXC(version) (((GET_CVID_IC_TYPE(version) == CHIP_8192C)||(GET_CVID_IC_TYPE(version) == CHIP_8188C))? true : false) #define IS_81XXC(version) (((GET_CVID_IC_TYPE(version) == CHIP_8192C)||(GET_CVID_IC_TYPE(version) == CHIP_8188C))? true : false)
#define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723A)? true : false) #define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723A)? true : false)
#define IS_92D(version) ((GET_CVID_IC_TYPE(version) == CHIP_8192D)? true : false) #define IS_92D(version) ((GET_CVID_IC_TYPE(version) == CHIP_8192D)? true : false)
#define IS_8188E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188E)? true : false) #define IS_8188E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188E)? true : false)
//HAL_CHIP_TYPE_E /* HAL_CHIP_TYPE_E */
#define IS_TEST_CHIP(version) ((GET_CVID_CHIP_TYPE(version)==TEST_CHIP)? true: false) #define IS_TEST_CHIP(version) ((GET_CVID_CHIP_TYPE(version)==TEST_CHIP)? true: false)
#define IS_NORMAL_CHIP(version) ((GET_CVID_CHIP_TYPE(version)==NORMAL_CHIP)? true: false) #define IS_NORMAL_CHIP(version) ((GET_CVID_CHIP_TYPE(version)==NORMAL_CHIP)? true: false)
//HAL_CUT_VERSION_E /* HAL_CUT_VERSION_E */
#define IS_A_CUT(version) ((GET_CVID_CUT_VERSION(version) == A_CUT_VERSION) ? true : false) #define IS_A_CUT(version) ((GET_CVID_CUT_VERSION(version) == A_CUT_VERSION) ? true : false)
#define IS_B_CUT(version) ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? true : false) #define IS_B_CUT(version) ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? true : false)
#define IS_C_CUT(version) ((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? true : false) #define IS_C_CUT(version) ((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? true : false)
@ -130,19 +130,19 @@ typedef struct tag_HAL_VERSION
#define IS_VENDOR_8188E_I_CUT_SERIES(_Adapter) ((IS_8188E(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) >= I_CUT_VERSION) ? true : false) : false) #define IS_VENDOR_8188E_I_CUT_SERIES(_Adapter) ((IS_8188E(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) >= I_CUT_VERSION) ? true : false) : false)
//HAL_VENDOR_E /* HAL_VENDOR_E */
#define IS_CHIP_VENDOR_TSMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_TSMC)? true: false) #define IS_CHIP_VENDOR_TSMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_TSMC)? true: false)
#define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_UMC)? true: false) #define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_UMC)? true: false)
//HAL_RF_TYPE_E /* HAL_RF_TYPE_E */
#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T1R)? true : false ) #define IS_1T1R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T1R)? true : false )
#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)? true : false) #define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)? true : false)
#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)? true : false) #define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)? true : false)
//---------------------------------------------------------------------------- /* */
//Chip version Macro. -- /* Chip version Macro. -- */
//---------------------------------------------------------------------------- /* */
#define IS_81XXC_TEST_CHIP(version) ((IS_81XXC(version) && (!IS_NORMAL_CHIP(version)))? true: false) #define IS_81XXC_TEST_CHIP(version) ((IS_81XXC(version) && (!IS_NORMAL_CHIP(version)))? true: false)
#define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? true : false) #define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? true : false)

4
include/autoconf.h
View file

@ -34,10 +34,10 @@
#define RTW_NOTCH_FILTER 0 /* 0:Disable, 1:Enable, */ #define RTW_NOTCH_FILTER 0 /* 0:Disable, 1:Enable, */
#define CONFIG_BR_EXT // Enable NAT2.5 support for STA mode interface with a L2 Bridge #define CONFIG_BR_EXT /* Enable NAT2.5 support for STA mode interface with a L2 Bridge */
#ifdef CONFIG_BR_EXT #ifdef CONFIG_BR_EXT
#define CONFIG_BR_EXT_BRNAME "br0" #define CONFIG_BR_EXT_BRNAME "br0"
#endif // CONFIG_BR_EXT #endif /* CONFIG_BR_EXT */
/* /*
* HAL Related Config * HAL Related Config

8
include/basic_types.h
View file

@ -47,8 +47,8 @@
#define SIZE_PTR SIZE_T #define SIZE_PTR SIZE_T
#define SSIZE_PTR SSIZE_T #define SSIZE_PTR SSIZE_T
//port from fw by thomas /* port from fw by thomas */
// TODO: Belows are Sync from SD7-Driver. It is necessary to check correctness /* TODO: Belows are Sync from SD7-Driver. It is necessary to check correctness */
/* /*
* Call endian free function when * Call endian free function when
@ -190,7 +190,7 @@ value to host byte ordering.*/
((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \ ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
) )
// Get the N-bytes aligment offset from the current length /* Get the N-bytes aligment offset from the current length */
#define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment)) #define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment))
#endif //__BASIC_TYPES_H__ #endif /* __BASIC_TYPES_H__ */

2
include/circ_buf.h
View file

@ -24,4 +24,4 @@
#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size)) #define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size))
#endif //_CIRC_BUF_H_ #endif /* _CIRC_BUF_H_ */

2
include/drv_conf.h
View file

@ -21,4 +21,4 @@
#define __DRV_CONF_H__ #define __DRV_CONF_H__
#include "autoconf.h" #include "autoconf.h"
#endif // __DRV_CONF_H__ #endif /* __DRV_CONF_H__ */

111
include/drv_types.h
View file

@ -72,7 +72,7 @@ enum _NIC_VERSION {
#ifdef CONFIG_BR_EXT #ifdef CONFIG_BR_EXT
#include <rtw_br_ext.h> #include <rtw_br_ext.h>
#endif // CONFIG_BR_EXT #endif /* CONFIG_BR_EXT */
#include "ioctl_cfg80211.h" #include "ioctl_cfg80211.h"
@ -98,14 +98,14 @@ struct registry_priv {
u8 lbkmode; u8 lbkmode;
u8 hci; u8 hci;
struct ndis_802_11_ssid ssid; struct ndis_802_11_ssid ssid;
u8 network_mode; //infra, ad-hoc, auto u8 network_mode; /* infra, ad-hoc, auto */
u8 channel;//ad-hoc support requirement u8 channel;/* ad-hoc support requirement */
u8 wireless_mode;//A, B, G, auto u8 wireless_mode;/* A, B, G, auto */
u8 scan_mode;//active, passive u8 scan_mode;/* active, passive */
u8 radio_enable; u8 radio_enable;
u8 preamble;//long, short, auto u8 preamble;/* long, short, auto */
u8 vrtl_carrier_sense;//Enable, Disable, Auto u8 vrtl_carrier_sense;/* Enable, Disable, Auto */
u8 vcs_type;//RTS/CTS, CTS-to-self u8 vcs_type;/* RTS/CTS, CTS-to-self */
u16 rts_thresh; u16 rts_thresh;
u16 frag_thresh; u16 frag_thresh;
u8 adhoc_tx_pwr; u8 adhoc_tx_pwr;
@ -121,7 +121,7 @@ struct registry_priv {
u8 software_encrypt; u8 software_encrypt;
u8 software_decrypt; u8 software_decrypt;
u8 acm_method; u8 acm_method;
//UAPSD /* UAPSD */
u8 wmm_enable; u8 wmm_enable;
u8 uapsd_enable; u8 uapsd_enable;
u8 uapsd_max_sp; u8 uapsd_max_sp;
@ -132,13 +132,13 @@ struct registry_priv {
struct wlan_bssid_ex dev_network; struct wlan_bssid_ex dev_network;
u8 ht_enable; u8 ht_enable;
u8 cbw40_enable; u8 cbw40_enable;
u8 ampdu_enable;//for tx u8 ampdu_enable;/* for tx */
u8 rx_stbc; u8 rx_stbc;
u8 ampdu_amsdu;//A-MPDU Supports A-MSDU is permitted u8 ampdu_amsdu;/* A-MPDU Supports A-MSDU is permitted */
u8 lowrate_two_xmit; u8 lowrate_two_xmit;
u8 rf_config ; u8 rf_config ;
u8 low_power ; u8 low_power ;
u8 wifi_spec;// !turbo_mode u8 wifi_spec;/* !turbo_mode */
u8 channel_plan; u8 channel_plan;
#ifdef CONFIG_BT_COEXIST #ifdef CONFIG_BT_COEXIST
u8 btcoex; u8 btcoex;
@ -149,12 +149,12 @@ struct registry_priv {
bool bAcceptAddbaReq; bool bAcceptAddbaReq;
u8 antdiv_cfg; u8 antdiv_cfg;
u8 antdiv_type; u8 antdiv_type;
u8 usbss_enable;//0:disable,1:enable u8 usbss_enable;/* 0:disable,1:enable */
u8 hwpdn_mode;//0:disable,1:enable,2:decide by EFUSE config u8 hwpdn_mode;/* 0:disable,1:enable,2:decide by EFUSE config */
u8 hwpwrp_detect;//0:disable,1:enable u8 hwpwrp_detect;/* 0:disable,1:enable */
u8 hw_wps_pbc;//0:disable,1:enable u8 hw_wps_pbc;/* 0:disable,1:enable */
u8 max_roaming_times; // the max number driver will try to roaming u8 max_roaming_times; /* the max number driver will try to roaming */
u8 fw_iol; //enable iol without other concern u8 fw_iol; /* enable iol without other concern */
#ifdef CONFIG_80211D #ifdef CONFIG_80211D
u8 enable80211d; u8 enable80211d;
#endif #endif
@ -166,7 +166,7 @@ struct registry_priv {
}; };
//For registry parameters /* For registry parameters */
#define RGTRY_OFT(field) ((ULONG)FIELD_OFFSET(struct registry_priv,field)) #define RGTRY_OFT(field) ((ULONG)FIELD_OFFSET(struct registry_priv,field))
#define RGTRY_SZ(field) sizeof(((struct registry_priv*) 0)->field) #define RGTRY_SZ(field) sizeof(((struct registry_priv*) 0)->field)
#define BSSID_OFT(field) ((ULONG)FIELD_OFFSET(struct wlan_bssid_ex,field)) #define BSSID_OFT(field) ((ULONG)FIELD_OFFSET(struct wlan_bssid_ex,field))
@ -179,8 +179,8 @@ struct registry_priv {
#define GET_ADAPTER(padapter, iface_id) (((struct adapter *)padapter)->dvobj->padapters[iface_id]) #define GET_ADAPTER(padapter, iface_id) (((struct adapter *)padapter)->dvobj->padapters[iface_id])
enum _IFACE_ID { enum _IFACE_ID {
IFACE_ID0, //maping to PRIMARY_ADAPTER IFACE_ID0, /* maping to PRIMARY_ADAPTER */
IFACE_ID1, //maping to SECONDARY_ADAPTER IFACE_ID1, /* maping to SECONDARY_ADAPTER */
IFACE_ID2, IFACE_ID2,
IFACE_ID3, IFACE_ID3,
IFACE_ID_MAX, IFACE_ID_MAX,
@ -192,33 +192,33 @@ struct rt_firmware {
}; };
struct dvobj_priv { struct dvobj_priv {
struct adapter *if1; //PRIMARY_ADAPTER struct adapter *if1; /* PRIMARY_ADAPTER */
struct adapter *if2; //SECONDARY_ADAPTER struct adapter *if2; /* SECONDARY_ADAPTER */
s32 processing_dev_remove; s32 processing_dev_remove;
//for local/global synchronization /* for local/global synchronization */
_mutex hw_init_mutex; _mutex hw_init_mutex;
_mutex h2c_fwcmd_mutex; _mutex h2c_fwcmd_mutex;
_mutex setch_mutex; _mutex setch_mutex;
_mutex setbw_mutex; _mutex setbw_mutex;
unsigned char oper_channel; //saved channel info when call set_channel_bw unsigned char oper_channel; /* saved channel info when call set_channel_bw */
unsigned char oper_bwmode; unsigned char oper_bwmode;
unsigned char oper_ch_offset;//PRIME_CHNL_OFFSET unsigned char oper_ch_offset;/* PRIME_CHNL_OFFSET */
u32 on_oper_ch_time; u32 on_oper_ch_time;
struct adapter *padapters[IFACE_ID_MAX]; struct adapter *padapters[IFACE_ID_MAX];
u8 iface_nums; // total number of ifaces used runtime u8 iface_nums; /* total number of ifaces used runtime */
//For 92D, DMDP have 2 interface. /* For 92D, DMDP have 2 interface. */
u8 InterfaceNumber; u8 InterfaceNumber;
u8 NumInterfaces; u8 NumInterfaces;
//In /Out Pipe information /* In /Out Pipe information */
int RtInPipe[2]; int RtInPipe[2];
int RtOutPipe[3]; int RtOutPipe[3];
u8 Queue2Pipe[HW_QUEUE_ENTRY];//for out pipe mapping u8 Queue2Pipe[HW_QUEUE_ENTRY];/* for out pipe mapping */
u8 irq_alloc; u8 irq_alloc;
ATOMIC_T continual_io_error; ATOMIC_T continual_io_error;
@ -238,7 +238,7 @@ struct dvobj_priv {
u8 ishighspeed; u8 ishighspeed;
u8 RtNumInPipes; u8 RtNumInPipes;
u8 RtNumOutPipes; u8 RtNumOutPipes;
int ep_num[5]; //endpoint number int ep_num[5]; /* endpoint number */
int RegUsbSS; int RegUsbSS;
@ -264,8 +264,8 @@ static struct device *dvobj_to_dev(struct dvobj_priv *dvobj)
} }
enum _IFACE_TYPE { enum _IFACE_TYPE {
IFACE_PORT0, //mapping to port0 for C/D series chips IFACE_PORT0, /* mapping to port0 for C/D series chips */
IFACE_PORT1, //mapping to port1 for C/D series chip IFACE_PORT1, /* mapping to port1 for C/D series chip */
MAX_IFACE_PORT, MAX_IFACE_PORT,
}; };
@ -291,7 +291,7 @@ struct proxim {
union recv_frame *precv_frame); union recv_frame *precv_frame);
u8 (*proxim_get_var)(struct adapter* padapter, u8 type); u8 (*proxim_get_var)(struct adapter* padapter, u8 type);
}; };
#endif //CONFIG_INTEL_PROXIM #endif /* CONFIG_INTEL_PROXIM */
#ifdef CONFIG_MAC_LOOPBACK_DRIVER #ifdef CONFIG_MAC_LOOPBACK_DRIVER
typedef struct loopbackdata typedef struct loopbackdata
@ -311,30 +311,30 @@ typedef struct loopbackdata
#endif #endif
struct adapter { struct adapter {
int DriverState;// for disable driver using module, use dongle to replace module. int DriverState;/* for disable driver using module, use dongle to replace module. */
int pid[3];//process id from UI, 0:wps, 1:hostapd, 2:dhcpcd int pid[3];/* process id from UI, 0:wps, 1:hostapd, 2:dhcpcd */
int bDongle;//build-in module or external dongle int bDongle;/* build-in module or external dongle */
u16 chip_type; u16 chip_type;
u16 HardwareType; u16 HardwareType;
u16 interface_type;//USB,SDIO,SPI,PCI u16 interface_type;/* USB,SDIO,SPI,PCI */
struct dvobj_priv *dvobj; struct dvobj_priv *dvobj;
struct mlme_priv mlmepriv; struct mlme_priv mlmepriv;
struct mlme_ext_priv mlmeextpriv; struct mlme_ext_priv mlmeextpriv;
struct cmd_priv cmdpriv; struct cmd_priv cmdpriv;
struct evt_priv evtpriv; struct evt_priv evtpriv;
//struct io_queue *pio_queue; /* struct io_queue *pio_queue; */
struct io_priv iopriv; struct io_priv iopriv;
struct xmit_priv xmitpriv; struct xmit_priv xmitpriv;
struct recv_priv recvpriv; struct recv_priv recvpriv;
struct sta_priv stapriv; struct sta_priv stapriv;
struct security_priv securitypriv; struct security_priv securitypriv;
spinlock_t security_key_mutex; // add for CONFIG_IEEE80211W, none 11w also can use spinlock_t security_key_mutex; /* add for CONFIG_IEEE80211W, none 11w also can use */
struct registry_priv registrypriv; struct registry_priv registrypriv;
struct eeprom_priv eeprompriv; struct eeprom_priv eeprompriv;
struct led_priv ledpriv; struct led_priv ledpriv;
#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST) #if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
//Check BT status for BT Hung. /* Check BT status for BT Hung. */
struct workqueue_struct *priv_checkbt_wq; struct workqueue_struct *priv_checkbt_wq;
struct delayed_work checkbt_work; struct delayed_work checkbt_work;
#endif #endif
@ -348,13 +348,13 @@ struct adapter {
#endif #endif
#ifdef CONFIG_P2P #ifdef CONFIG_P2P
struct cfg80211_wifidirect_info cfg80211_wdinfo; struct cfg80211_wifidirect_info cfg80211_wdinfo;
#endif //CONFIG_P2P #endif /* CONFIG_P2P */
u32 setband; u32 setband;
struct wifidirect_info wdinfo; struct wifidirect_info wdinfo;
#ifdef CONFIG_P2P #ifdef CONFIG_P2P
struct wifi_display_info wfd_info; struct wifi_display_info wfd_info;
#endif //CONFIG_P2P #endif /* CONFIG_P2P */
void * HalData; void * HalData;
u32 hal_data_sz; u32 hal_data_sz;
@ -383,7 +383,7 @@ struct adapter {
struct net_device * pnetdev; struct net_device * pnetdev;
// used by rtw_rereg_nd_name related function /* used by rtw_rereg_nd_name related function */
struct rereg_nd_name_data { struct rereg_nd_name_data {
struct net_device * old_pnetdev; struct net_device * old_pnetdev;
char old_ifname[IFNAMSIZ]; char old_ifname[IFNAMSIZ];
@ -394,7 +394,7 @@ struct adapter {
int bup; int bup;
struct net_device_stats stats; struct net_device_stats stats;
struct iw_statistics iwstats; struct iw_statistics iwstats;
struct proc_dir_entry *dir_dev;// for proc directory struct proc_dir_entry *dir_dev;/* for proc directory */
struct proc_dir_entry *dir_odm; struct proc_dir_entry *dir_odm;
struct wireless_dev *rtw_wdev; struct wireless_dev *rtw_wdev;
@ -406,12 +406,12 @@ struct adapter {
u8 bReadPortCancel; u8 bReadPortCancel;
u8 bWritePortCancel; u8 bWritePortCancel;
u8 bRxRSSIDisplay; u8 bRxRSSIDisplay;
// Added by Albert 2012/10/26 /* Added by Albert 2012/10/26 */
// The driver will show up the desired channel number when this flag is 1. /* The driver will show up the desired channel number when this flag is 1. */
u8 bNotifyChannelChange; u8 bNotifyChannelChange;
#ifdef CONFIG_P2P #ifdef CONFIG_P2P
// Added by Albert 2012/12/06 /* Added by Albert 2012/12/06 */
// The driver will show the current P2P status when the upper application reads it. /* The driver will show the current P2P status when the upper application reads it. */
u8 bShowGetP2PState; u8 bShowGetP2PState;
#endif #endif
#ifdef CONFIG_AUTOSUSPEND #ifdef CONFIG_AUTOSUSPEND
@ -420,14 +420,13 @@ struct adapter {
struct adapter *pbuddy_adapter; struct adapter *pbuddy_adapter;
//extend to support multi interface /* extend to support multi interface */
//IFACE_ID0 is equals to PRIMARY_ADAPTER /* IFACE_ID0 is equals to PRIMARY_ADAPTER */
//IFACE_ID1 is equals to SECONDARY_ADAPTER /* IFACE_ID1 is equals to SECONDARY_ADAPTER */
u8 iface_id; u8 iface_id;
#ifdef CONFIG_BR_EXT #ifdef CONFIG_BR_EXT
spinlock_t br_ext_lock; spinlock_t br_ext_lock;
//unsigned int macclone_completed;
struct nat25_network_db_entry *nethash[NAT25_HASH_SIZE]; struct nat25_network_db_entry *nethash[NAT25_HASH_SIZE];
int pppoe_connection_in_progress; int pppoe_connection_in_progress;
unsigned char pppoe_addr[MACADDRLEN]; unsigned char pppoe_addr[MACADDRLEN];
@ -438,14 +437,14 @@ struct adapter {
unsigned char br_ip[4]; unsigned char br_ip[4];
struct br_ext_info ethBrExtInfo; struct br_ext_info ethBrExtInfo;
#endif // CONFIG_BR_EXT #endif /* CONFIG_BR_EXT */
#ifdef CONFIG_INTEL_PROXIM #ifdef CONFIG_INTEL_PROXIM
/* intel Proximity, should be alloc mem /* intel Proximity, should be alloc mem
* in intel Proximity module and can only * in intel Proximity module and can only
* be used in intel Proximity mode */ * be used in intel Proximity mode */
struct proxim proximity; struct proxim proximity;
#endif //CONFIG_INTEL_PROXIM #endif /* CONFIG_INTEL_PROXIM */
#ifdef CONFIG_MAC_LOOPBACK_DRIVER #ifdef CONFIG_MAC_LOOPBACK_DRIVER
PLOOPBACKDATA ploopback; PLOOPBACKDATA ploopback;
@ -468,4 +467,4 @@ __inline static u8 *myid(struct eeprom_priv *peepriv)
} }
#endif //__DRV_TYPES_H__ #endif /* __DRV_TYPES_H__ */

28
include/ethernet.h
View file

@ -21,21 +21,21 @@
#ifndef __INC_ETHERNET_H #ifndef __INC_ETHERNET_H
#define __INC_ETHERNET_H #define __INC_ETHERNET_H
#define ETHERNET_ADDRESS_LENGTH 6 //!< Ethernet Address Length #define ETHERNET_ADDRESS_LENGTH 6 /* Ethernet Address Length */
#define ETHERNET_HEADER_SIZE 14 //!< Ethernet Header Length #define ETHERNET_HEADER_SIZE 14 /* Ethernet Header Length */
#define LLC_HEADER_SIZE 6 //!< LLC Header Length #define LLC_HEADER_SIZE 6 /* LLC Header Length */
#define TYPE_LENGTH_FIELD_SIZE 2 //!< Type/Length Size #define TYPE_LENGTH_FIELD_SIZE 2 /* Type/Length Size */
#define MINIMUM_ETHERNET_PACKET_SIZE 60 //!< Minimum Ethernet Packet Size #define MINIMUM_ETHERNET_PACKET_SIZE 60 /* Minimum Ethernet Packet Size */
#define MAXIMUM_ETHERNET_PACKET_SIZE 1514 //!< Maximum Ethernet Packet Size #define MAXIMUM_ETHERNET_PACKET_SIZE 1514 /* Maximum Ethernet Packet Size */
#define RT_ETH_IS_MULTICAST(_pAddr) ((((u8 *)(_pAddr))[0]&0x01)!=0) //!< Is Multicast Address? #define RT_ETH_IS_MULTICAST(_pAddr) ((((u8 *)(_pAddr))[0]&0x01)!=0) /* Is Multicast Address? */
#define RT_ETH_IS_BROADCAST(_pAddr) ( \ #define RT_ETH_IS_BROADCAST(_pAddr) ( \
((u8 *)(_pAddr))[0]==0xff && \ ((u8 *)(_pAddr))[0]==0xff && \
((u8 *)(_pAddr))[1]==0xff && \ ((u8 *)(_pAddr))[1]==0xff && \
((u8 *)(_pAddr))[2]==0xff && \ ((u8 *)(_pAddr))[2]==0xff && \
((u8 *)(_pAddr))[3]==0xff && \ ((u8 *)(_pAddr))[3]==0xff && \
((u8 *)(_pAddr))[4]==0xff && \ ((u8 *)(_pAddr))[4]==0xff && \
((u8 *)(_pAddr))[5]==0xff ) //!< Is Broadcast Address? ((u8 *)(_pAddr))[5]==0xff ) /* Is Broadcast Address? */
#endif // #ifndef __INC_ETHERNET_H #endif /* #ifndef __INC_ETHERNET_H */

52
include/hal_com.h
View file

@ -20,15 +20,15 @@
#ifndef __HAL_COMMON_H__ #ifndef __HAL_COMMON_H__
#define __HAL_COMMON_H__ #define __HAL_COMMON_H__
//---------------------------------------------------------------------------- /* */
// Rate Definition /* Rate Definition */
//---------------------------------------------------------------------------- /* */
//CCK /* CCK */
#define RATR_1M 0x00000001 #define RATR_1M 0x00000001
#define RATR_2M 0x00000002 #define RATR_2M 0x00000002
#define RATR_55M 0x00000004 #define RATR_55M 0x00000004
#define RATR_11M 0x00000008 #define RATR_11M 0x00000008
//OFDM /* OFDM */
#define RATR_6M 0x00000010 #define RATR_6M 0x00000010
#define RATR_9M 0x00000020 #define RATR_9M 0x00000020
#define RATR_12M 0x00000040 #define RATR_12M 0x00000040
@ -37,7 +37,7 @@
#define RATR_36M 0x00000200 #define RATR_36M 0x00000200
#define RATR_48M 0x00000400 #define RATR_48M 0x00000400
#define RATR_54M 0x00000800 #define RATR_54M 0x00000800
//MCS 1 Spatial Stream /* MCS 1 Spatial Stream */
#define RATR_MCS0 0x00001000 #define RATR_MCS0 0x00001000
#define RATR_MCS1 0x00002000 #define RATR_MCS1 0x00002000
#define RATR_MCS2 0x00004000 #define RATR_MCS2 0x00004000
@ -46,7 +46,7 @@
#define RATR_MCS5 0x00020000 #define RATR_MCS5 0x00020000
#define RATR_MCS6 0x00040000 #define RATR_MCS6 0x00040000
#define RATR_MCS7 0x00080000 #define RATR_MCS7 0x00080000
//MCS 2 Spatial Stream /* MCS 2 Spatial Stream */
#define RATR_MCS8 0x00100000 #define RATR_MCS8 0x00100000
#define RATR_MCS9 0x00200000 #define RATR_MCS9 0x00200000
#define RATR_MCS10 0x00400000 #define RATR_MCS10 0x00400000
@ -56,12 +56,12 @@
#define RATR_MCS14 0x04000000 #define RATR_MCS14 0x04000000
#define RATR_MCS15 0x08000000 #define RATR_MCS15 0x08000000
//CCK /* CCK */
#define RATE_1M BIT(0) #define RATE_1M BIT(0)
#define RATE_2M BIT(1) #define RATE_2M BIT(1)
#define RATE_5_5M BIT(2) #define RATE_5_5M BIT(2)
#define RATE_11M BIT(3) #define RATE_11M BIT(3)
//OFDM /* OFDM */
#define RATE_6M BIT(4) #define RATE_6M BIT(4)
#define RATE_9M BIT(5) #define RATE_9M BIT(5)
#define RATE_12M BIT(6) #define RATE_12M BIT(6)
@ -70,7 +70,7 @@
#define RATE_36M BIT(9) #define RATE_36M BIT(9)
#define RATE_48M BIT(10) #define RATE_48M BIT(10)
#define RATE_54M BIT(11) #define RATE_54M BIT(11)
//MCS 1 Spatial Stream /* MCS 1 Spatial Stream */
#define RATE_MCS0 BIT(12) #define RATE_MCS0 BIT(12)
#define RATE_MCS1 BIT(13) #define RATE_MCS1 BIT(13)
#define RATE_MCS2 BIT(14) #define RATE_MCS2 BIT(14)
@ -79,7 +79,7 @@
#define RATE_MCS5 BIT(17) #define RATE_MCS5 BIT(17)
#define RATE_MCS6 BIT(18) #define RATE_MCS6 BIT(18)
#define RATE_MCS7 BIT(19) #define RATE_MCS7 BIT(19)
//MCS 2 Spatial Stream /* MCS 2 Spatial Stream */
#define RATE_MCS8 BIT(20) #define RATE_MCS8 BIT(20)
#define RATE_MCS9 BIT(21) #define RATE_MCS9 BIT(21)
#define RATE_MCS10 BIT(22) #define RATE_MCS10 BIT(22)
@ -89,7 +89,7 @@
#define RATE_MCS14 BIT(26) #define RATE_MCS14 BIT(26)
#define RATE_MCS15 BIT(27) #define RATE_MCS15 BIT(27)
// ALL CCK Rate /* ALL CCK Rate */
#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M #define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M
#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\ #define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\
RATR_36M|RATR_48M|RATR_54M RATR_36M|RATR_48M|RATR_54M
@ -99,18 +99,18 @@
RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
/*------------------------------ Tx Desc definition Macro ------------------------*/ /*------------------------------ Tx Desc definition Macro ------------------------*/
//#pragma mark -- Tx Desc related definition. -- /* pragma mark -- Tx Desc related definition. -- */
//---------------------------------------------------------------------------- /* */
//----------------------------------------------------------- /* */
// Rate /* Rate */
//----------------------------------------------------------- /* */
// CCK Rates, TxHT = 0 /* CCK Rates, TxHT = 0 */
#define DESC_RATE1M 0x00 #define DESC_RATE1M 0x00
#define DESC_RATE2M 0x01 #define DESC_RATE2M 0x01
#define DESC_RATE5_5M 0x02 #define DESC_RATE5_5M 0x02
#define DESC_RATE11M 0x03 #define DESC_RATE11M 0x03
// OFDM Rates, TxHT = 0 /* OFDM Rates, TxHT = 0 */
#define DESC_RATE6M 0x04 #define DESC_RATE6M 0x04
#define DESC_RATE9M 0x05 #define DESC_RATE9M 0x05
#define DESC_RATE12M 0x06 #define DESC_RATE12M 0x06
@ -120,7 +120,7 @@
#define DESC_RATE48M 0x0a #define DESC_RATE48M 0x0a
#define DESC_RATE54M 0x0b #define DESC_RATE54M 0x0b
// MCS Rates, TxHT = 1 /* MCS Rates, TxHT = 1 */
#define DESC_RATEMCS0 0x0c #define DESC_RATEMCS0 0x0c
#define DESC_RATEMCS1 0x0d #define DESC_RATEMCS1 0x0d
#define DESC_RATEMCS2 0x0e #define DESC_RATEMCS2 0x0e
@ -140,7 +140,7 @@
#define DESC_RATEMCS15_SG 0x1c #define DESC_RATEMCS15_SG 0x1c
#define DESC_RATEMCS32 0x20 #define DESC_RATEMCS32 0x20
#define REG_P2P_CTWIN 0x0572 // 1 Byte long (in unit of TU) #define REG_P2P_CTWIN 0x0572 /* 1 Byte long (in unit of TU) */
#define REG_NOA_DESC_SEL 0x05CF #define REG_NOA_DESC_SEL 0x05CF
#define REG_NOA_DESC_DURATION 0x05E0 #define REG_NOA_DESC_DURATION 0x05E0
#define REG_NOA_DESC_INTERVAL 0x05E4 #define REG_NOA_DESC_INTERVAL 0x05E4
@ -151,12 +151,12 @@
void dump_chip_info(HAL_VERSION ChipVersion); void dump_chip_info(HAL_VERSION ChipVersion);
u8 //return the final channel plan decision u8 /* return the final channel plan decision */
hal_com_get_channel_plan( hal_com_get_channel_plan(
struct adapter *padapter, struct adapter *padapter,
u8 hw_channel_plan, //channel plan from HW (efuse/eeprom) u8 hw_channel_plan, /* channel plan from HW (efuse/eeprom) */
u8 sw_channel_plan, //channel plan from SW (registry/module param) u8 sw_channel_plan, /* channel plan from SW (registry/module param) */
u8 def_channel_plan, //channel plan used when the former two is invalid u8 def_channel_plan, /* channel plan used when the former two is invalid */
bool AutoLoadFail bool AutoLoadFail
); );
@ -181,4 +181,4 @@ s32 c2h_evt_read(struct adapter *adapter, u8 *buf);
u8 SetHalDefVar(struct adapter *adapter, HAL_DEF_VARIABLE variable, void *value); u8 SetHalDefVar(struct adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
u8 GetHalDefVar(struct adapter *adapter, HAL_DEF_VARIABLE variable, void *value); u8 GetHalDefVar(struct adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
#endif //__HAL_COMMON_H__ #endif /* __HAL_COMMON_H__ */

36
include/hal_intf.h
View file

@ -106,9 +106,9 @@ typedef enum _HW_VARIABLES{
HW_VAR_EFUSE_BT_BYTES, HW_VAR_EFUSE_BT_BYTES,
HW_VAR_FIFO_CLEARN_UP, HW_VAR_FIFO_CLEARN_UP,
HW_VAR_CHECK_TXBUF, HW_VAR_CHECK_TXBUF,
HW_VAR_APFM_ON_MAC, //Auto FSM to Turn On, include clock, isolation, power control for MAC only HW_VAR_APFM_ON_MAC, /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
// The valid upper nav range for the HW updating, if the true value is larger than the upper range, the HW won't update it. /* The valid upper nav range for the HW updating, if the true value is larger than the upper range, the HW won't update it. */
// Unit in microsecond. 0 means disable this function. /* Unit in microsecond. 0 means disable this function. */
HW_VAR_SYS_CLKR, HW_VAR_SYS_CLKR,
HW_VAR_NAV_UPPER, HW_VAR_NAV_UPPER,
HW_VAR_RPT_TIMER_SETTING, HW_VAR_RPT_TIMER_SETTING,
@ -127,8 +127,8 @@ typedef enum _HAL_DEF_VARIABLE{
HAL_DEF_DRVINFO_SZ, HAL_DEF_DRVINFO_SZ,
HAL_DEF_MAX_RECVBUF_SZ, HAL_DEF_MAX_RECVBUF_SZ,
HAL_DEF_RX_PACKET_OFFSET, HAL_DEF_RX_PACKET_OFFSET,
HAL_DEF_DBG_DUMP_RXPKT,//for dbg HAL_DEF_DBG_DUMP_RXPKT,/* for dbg */
HAL_DEF_DBG_DM_FUNC,//for dbg HAL_DEF_DBG_DM_FUNC,/* for dbg */
HAL_DEF_RA_DECISION_RATE, HAL_DEF_RA_DECISION_RATE,
HAL_DEF_RA_SGI, HAL_DEF_RA_SGI,
HAL_DEF_PT_PWR_STATUS, HAL_DEF_PT_PWR_STATUS,
@ -292,34 +292,34 @@ typedef enum _HARDWARE_TYPE{
HARDWARE_TYPE_MAX, HARDWARE_TYPE_MAX,
}HARDWARE_TYPE; }HARDWARE_TYPE;
// /* */
// RTL8192C Series /* RTL8192C Series */
// /* */
#define IS_HARDWARE_TYPE_8192CE(_Adapter) (((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192CE) #define IS_HARDWARE_TYPE_8192CE(_Adapter) (((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192CE)
#define IS_HARDWARE_TYPE_8192CU(_Adapter) (((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192CU) #define IS_HARDWARE_TYPE_8192CU(_Adapter) (((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192CU)
#define IS_HARDWARE_TYPE_8192C(_Adapter) \ #define IS_HARDWARE_TYPE_8192C(_Adapter) \
(IS_HARDWARE_TYPE_8192CE(_Adapter) || IS_HARDWARE_TYPE_8192CU(_Adapter)) (IS_HARDWARE_TYPE_8192CE(_Adapter) || IS_HARDWARE_TYPE_8192CU(_Adapter))
// /* */
// RTL8192D Series /* RTL8192D Series */
// /* */
#define IS_HARDWARE_TYPE_8192DE(_Adapter) (((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192DE) #define IS_HARDWARE_TYPE_8192DE(_Adapter) (((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192DE)
#define IS_HARDWARE_TYPE_8192DU(_Adapter) (((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192DU) #define IS_HARDWARE_TYPE_8192DU(_Adapter) (((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192DU)
#define IS_HARDWARE_TYPE_8192D(_Adapter) \ #define IS_HARDWARE_TYPE_8192D(_Adapter) \
(IS_HARDWARE_TYPE_8192DE(_Adapter) || IS_HARDWARE_TYPE_8192DU(_Adapter)) (IS_HARDWARE_TYPE_8192DE(_Adapter) || IS_HARDWARE_TYPE_8192DU(_Adapter))
// /* */
// RTL8723A Series /* RTL8723A Series */
// /* */
#define IS_HARDWARE_TYPE_8723AE(_Adapter) (((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AE) #define IS_HARDWARE_TYPE_8723AE(_Adapter) (((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AE)
#define IS_HARDWARE_TYPE_8723AU(_Adapter) (((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AU) #define IS_HARDWARE_TYPE_8723AU(_Adapter) (((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AU)
#define IS_HARDWARE_TYPE_8723AS(_Adapter) (((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AS) #define IS_HARDWARE_TYPE_8723AS(_Adapter) (((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723AS)
#define IS_HARDWARE_TYPE_8723A(_Adapter) \ #define IS_HARDWARE_TYPE_8723A(_Adapter) \
(IS_HARDWARE_TYPE_8723AE(_Adapter) || IS_HARDWARE_TYPE_8723AU(_Adapter) || IS_HARDWARE_TYPE_8723AS(_Adapter)) (IS_HARDWARE_TYPE_8723AE(_Adapter) || IS_HARDWARE_TYPE_8723AU(_Adapter) || IS_HARDWARE_TYPE_8723AS(_Adapter))
// /* */
// RTL8188E Series /* RTL8188E Series */
// /* */
#define IS_HARDWARE_TYPE_8188EE(_Adapter) (((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188EE) #define IS_HARDWARE_TYPE_8188EE(_Adapter) (((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188EE)
#define IS_HARDWARE_TYPE_8188EU(_Adapter) (((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188EU) #define IS_HARDWARE_TYPE_8188EU(_Adapter) (((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188EU)
#define IS_HARDWARE_TYPE_8188ES(_Adapter) (((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188ES) #define IS_HARDWARE_TYPE_8188ES(_Adapter) (((struct adapter *)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8188ES)
@ -417,4 +417,4 @@ void rtw_hal_reset_security_engine(struct adapter * adapter);
s32 rtw_hal_c2h_handler(struct adapter *adapter, struct c2h_evt_hdr *c2h_evt); s32 rtw_hal_c2h_handler(struct adapter *adapter, struct c2h_evt_hdr *c2h_evt);
c2h_id_filter rtw_hal_c2h_id_filter_ccx(struct adapter *adapter); c2h_id_filter rtw_hal_c2h_id_filter_ccx(struct adapter *adapter);
#endif //__HAL_INTF_H__ #endif /* __HAL_INTF_H__ */

87
include/ieee80211.h
View file

@ -151,9 +151,9 @@ extern u8 RSN_CIPHER_SUITE_CCMP[];
extern u8 RSN_CIPHER_SUITE_WEP104[]; extern u8 RSN_CIPHER_SUITE_WEP104[];
typedef enum _RATR_TABLE_MODE{ typedef enum _RATR_TABLE_MODE{
RATR_INX_WIRELESS_NGB = 0, // BGN 40 Mhz 2SS 1SS RATR_INX_WIRELESS_NGB = 0, /* BGN 40 Mhz 2SS 1SS */
RATR_INX_WIRELESS_NG = 1, // GN or N RATR_INX_WIRELESS_NG = 1, /* GN or N */
RATR_INX_WIRELESS_NB = 2, // BGN 20 Mhz 2SS 1SS or BN RATR_INX_WIRELESS_NB = 2, /* BGN 20 Mhz 2SS 1SS or BN */
RATR_INX_WIRELESS_N = 3, RATR_INX_WIRELESS_N = 3,
RATR_INX_WIRELESS_GB = 4, RATR_INX_WIRELESS_GB = 4,
RATR_INX_WIRELESS_G = 5, RATR_INX_WIRELESS_G = 5,
@ -165,21 +165,21 @@ typedef enum _RATR_TABLE_MODE{
enum NETWORK_TYPE enum NETWORK_TYPE
{ {
WIRELESS_INVALID = 0, WIRELESS_INVALID = 0,
//Sub-Element /* Sub-Element */
WIRELESS_11B = BIT(0), // tx: cck only , rx: cck only, hw: cck WIRELESS_11B = BIT(0), /* tx: cck only , rx: cck only, hw: cck */
WIRELESS_11G = BIT(1), // tx: ofdm only, rx: ofdm & cck, hw: cck & ofdm WIRELESS_11G = BIT(1), /* tx: ofdm only, rx: ofdm & cck, hw: cck & ofdm */
WIRELESS_11A = BIT(2), // tx: ofdm only, rx: ofdm only, hw: ofdm only WIRELESS_11A = BIT(2), /* tx: ofdm only, rx: ofdm only, hw: ofdm only */
WIRELESS_11_24N = BIT(3), // tx: MCS only, rx: MCS & cck, hw: MCS & cck WIRELESS_11_24N = BIT(3), /* tx: MCS only, rx: MCS & cck, hw: MCS & cck */
WIRELESS_11_5N = BIT(4), // tx: MCS only, rx: MCS & ofdm, hw: ofdm only WIRELESS_11_5N = BIT(4), /* tx: MCS only, rx: MCS & ofdm, hw: ofdm only */
//WIRELESS_AUTO = BIT(5), /* WIRELESS_AUTO = BIT(5), */
WIRELESS_AC = BIT(6), WIRELESS_AC = BIT(6),
//Combination /* Combination */
WIRELESS_11BG = (WIRELESS_11B|WIRELESS_11G), // tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm WIRELESS_11BG = (WIRELESS_11B|WIRELESS_11G), /* tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm */
WIRELESS_11G_24N = (WIRELESS_11G|WIRELESS_11_24N), // tx: ofdm & MCS, rx: ofdm & cck & MCS, hw: cck & ofdm WIRELESS_11G_24N = (WIRELESS_11G|WIRELESS_11_24N), /* tx: ofdm & MCS, rx: ofdm & cck & MCS, hw: cck & ofdm */
WIRELESS_11A_5N = (WIRELESS_11A|WIRELESS_11_5N), // tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only WIRELESS_11A_5N = (WIRELESS_11A|WIRELESS_11_5N), /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */
WIRELESS_11BG_24N = (WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N), // tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck WIRELESS_11BG_24N = (WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N), /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */
WIRELESS_11AGN = (WIRELESS_11A|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N), // tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only WIRELESS_11AGN = (WIRELESS_11A|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N), /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */
WIRELESS_11ABGN = (WIRELESS_11A|WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N), WIRELESS_11ABGN = (WIRELESS_11A|WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N),
}; };
@ -236,7 +236,7 @@ typedef struct ieee_param {
struct rtw_ieee80211_ht_cap ht_cap; struct rtw_ieee80211_ht_cap ht_cap;
} add_sta; } add_sta;
struct { struct {
u8 reserved[2];//for set max_num_sta u8 reserved[2];/* for set max_num_sta */
u8 buf[0]; u8 buf[0];
} bcn_ie; } bcn_ie;
#endif #endif
@ -644,13 +644,13 @@ struct ieee80211_snap_hdr {
* information for frames received. Not setting these will not cause * information for frames received. Not setting these will not cause
* any adverse affects. */ * any adverse affects. */
struct ieee80211_rx_stats { struct ieee80211_rx_stats {
//u32 mac_time[2]; /* u32 mac_time[2]; */
s8 rssi; s8 rssi;
u8 signal; u8 signal;
u8 noise; u8 noise;
u8 received_channel; u8 received_channel;
u16 rate; /* in 100 kbps */ u16 rate; /* in 100 kbps */
//u8 control; /* u8 control; */
u8 mask; u8 mask;
u8 freq; u8 freq;
u16 len; u16 len;
@ -666,8 +666,8 @@ struct ieee80211_frag_entry {
u32 first_frag_time; u32 first_frag_time;
uint seq; uint seq;
uint last_frag; uint last_frag;
uint qos; //jackson uint qos; /* jackson */
uint tid; //jackson uint tid; /* jackson */
struct sk_buff *skb; struct sk_buff *skb;
u8 src_addr[ETH_ALEN]; u8 src_addr[ETH_ALEN];
u8 dst_addr[ETH_ALEN]; u8 dst_addr[ETH_ALEN];
@ -739,7 +739,7 @@ struct ieee80211_softmac_stats{
#ifdef CONFIG_IEEE80211W #ifdef CONFIG_IEEE80211W
#define BIP_MAX_KEYID 5 #define BIP_MAX_KEYID 5
#define BIP_AAD_SIZE 20 #define BIP_AAD_SIZE 20
#endif //CONFIG_IEEE80211W #endif /* CONFIG_IEEE80211W */
struct ieee80211_security { struct ieee80211_security {
u16 active_key:2, u16 active_key:2,
@ -830,7 +830,7 @@ struct ieee80211_authentication {
u16 algorithm; u16 algorithm;
u16 transaction; u16 transaction;
u16 status; u16 status;
//struct ieee80211_info_element_hdr info_element; /* struct ieee80211_info_element_hdr info_element; */
} __attribute__ ((packed)); } __attribute__ ((packed));
struct ieee80211_probe_response { struct ieee80211_probe_response {
@ -850,7 +850,7 @@ struct ieee80211_assoc_request_frame {
struct rtw_ieee80211_hdr_3addr header; struct rtw_ieee80211_hdr_3addr header;
u16 capability; u16 capability;
u16 listen_interval; u16 listen_interval;
//u8 current_ap[ETH_ALEN]; /* u8 current_ap[ETH_ALEN]; */
struct ieee80211_info_element_hdr info_element; struct ieee80211_info_element_hdr info_element;
} __attribute__ ((packed)); } __attribute__ ((packed));
@ -859,7 +859,6 @@ struct ieee80211_assoc_response_frame {
u16 capability; u16 capability;
u16 status; u16 status;
u16 aid; u16 aid;
// struct ieee80211_info_element info_element; /* supported rates */
} __attribute__ ((packed)); } __attribute__ ((packed));
struct ieee80211_txb { struct ieee80211_txb {
@ -883,7 +882,7 @@ struct ieee80211_txb {
#define MAX_NETWORK_COUNT 128 #define MAX_NETWORK_COUNT 128
#define MAX_CHANNEL_NUMBER 161 #define MAX_CHANNEL_NUMBER 161
#define IEEE80211_SOFTMAC_SCAN_TIME 400 #define IEEE80211_SOFTMAC_SCAN_TIME 400
//(HZ / 2) /* HZ / 2) */
#define IEEE80211_SOFTMAC_ASSOC_RETRY_TIME (HZ * 2) #define IEEE80211_SOFTMAC_ASSOC_RETRY_TIME (HZ * 2)
#define CRC_LENGTH 4U #define CRC_LENGTH 4U
@ -993,7 +992,7 @@ typedef struct tx_pending_t{
#define IEEE_G (1<<2) #define IEEE_G (1<<2)
#define IEEE_MODE_MASK (IEEE_A|IEEE_B|IEEE_G) #define IEEE_MODE_MASK (IEEE_A|IEEE_B|IEEE_G)
//Baron move to ieee80211.c /* Baron move to ieee80211.c */
int ieee80211_is_empty_essid(const char *essid, int essid_len); int ieee80211_is_empty_essid(const char *essid, int essid_len);
int ieee80211_get_hdrlen(u16 fc); int ieee80211_get_hdrlen(u16 fc);
@ -1003,16 +1002,16 @@ enum rtw_ieee80211_category {
RTW_WLAN_CATEGORY_QOS = 1, RTW_WLAN_CATEGORY_QOS = 1,
RTW_WLAN_CATEGORY_DLS = 2, RTW_WLAN_CATEGORY_DLS = 2,
RTW_WLAN_CATEGORY_BACK = 3, RTW_WLAN_CATEGORY_BACK = 3,
RTW_WLAN_CATEGORY_PUBLIC = 4, //IEEE 802.11 public action frames RTW_WLAN_CATEGORY_PUBLIC = 4, /* IEEE 802.11 public action frames */
RTW_WLAN_CATEGORY_RADIO_MEASUREMENT = 5, RTW_WLAN_CATEGORY_RADIO_MEASUREMENT = 5,
RTW_WLAN_CATEGORY_FT = 6, RTW_WLAN_CATEGORY_FT = 6,
RTW_WLAN_CATEGORY_HT = 7, RTW_WLAN_CATEGORY_HT = 7,
RTW_WLAN_CATEGORY_SA_QUERY = 8, RTW_WLAN_CATEGORY_SA_QUERY = 8,
RTW_WLAN_CATEGORY_UNPROTECTED_WNM = 11, // add for CONFIG_IEEE80211W, none 11w also can use RTW_WLAN_CATEGORY_UNPROTECTED_WNM = 11, /* add for CONFIG_IEEE80211W, none 11w also can use */
RTW_WLAN_CATEGORY_TDLS = 12, RTW_WLAN_CATEGORY_TDLS = 12,
RTW_WLAN_CATEGORY_SELF_PROTECTED = 15, // add for CONFIG_IEEE80211W, none 11w also can use RTW_WLAN_CATEGORY_SELF_PROTECTED = 15, /* add for CONFIG_IEEE80211W, none 11w also can use */
RTW_WLAN_CATEGORY_WMM = 17, RTW_WLAN_CATEGORY_WMM = 17,
RTW_WLAN_CATEGORY_P2P = 0x7f,//P2P action frames RTW_WLAN_CATEGORY_P2P = 0x7f,/* P2P action frames */
}; };
/* SPECTRUM_MGMT action code */ /* SPECTRUM_MGMT action code */
@ -1026,16 +1025,16 @@ enum rtw_ieee80211_spectrum_mgmt_actioncode {
}; };
enum _PUBLIC_ACTION{ enum _PUBLIC_ACTION{
ACT_PUBLIC_BSSCOEXIST = 0, // 20/40 BSS Coexistence ACT_PUBLIC_BSSCOEXIST = 0, /* 20/40 BSS Coexistence */
ACT_PUBLIC_DSE_ENABLE = 1, ACT_PUBLIC_DSE_ENABLE = 1,
ACT_PUBLIC_DSE_DEENABLE = 2, ACT_PUBLIC_DSE_DEENABLE = 2,
ACT_PUBLIC_DSE_REG_LOCATION = 3, ACT_PUBLIC_DSE_REG_LOCATION = 3,
ACT_PUBLIC_EXT_CHL_SWITCH = 4, ACT_PUBLIC_EXT_CHL_SWITCH = 4,
ACT_PUBLIC_DSE_MSR_REQ = 5, ACT_PUBLIC_DSE_MSR_REQ = 5,
ACT_PUBLIC_DSE_MSR_RPRT = 6, ACT_PUBLIC_DSE_MSR_RPRT = 6,
ACT_PUBLIC_MP = 7, // Measurement Pilot ACT_PUBLIC_MP = 7, /* Measurement Pilot */
ACT_PUBLIC_DSE_PWR_CONSTRAINT = 8, ACT_PUBLIC_DSE_PWR_CONSTRAINT = 8,
ACT_PUBLIC_VENDOR = 9, // for WIFI_DIRECT ACT_PUBLIC_VENDOR = 9, /* for WIFI_DIRECT */
ACT_PUBLIC_GAS_INITIAL_REQ = 10, ACT_PUBLIC_GAS_INITIAL_REQ = 10,
ACT_PUBLIC_GAS_INITIAL_RSP = 11, ACT_PUBLIC_GAS_INITIAL_RSP = 11,
ACT_PUBLIC_GAS_COMEBACK_REQ = 12, ACT_PUBLIC_GAS_COMEBACK_REQ = 12,
@ -1127,17 +1126,17 @@ enum rtw_ieee80211_back_parties {
/* Represent channel details, subset of ieee80211_channel */ /* Represent channel details, subset of ieee80211_channel */
struct rtw_ieee80211_channel { struct rtw_ieee80211_channel {
//enum ieee80211_band band; /* enum ieee80211_band band; */
//u16 center_freq; /* u16 center_freq; */
u16 hw_value; u16 hw_value;
u32 flags; u32 flags;
//int max_antenna_gain; /* int max_antenna_gain; */
//int max_power; /* int max_power; */
//int max_reg_power; /* int max_reg_power; */
//bool beacon_found; /* bool beacon_found; */
//u32 orig_flags; /* u32 orig_flags; */
//int orig_mag; /* int orig_mag; */
//int orig_mpwr; /* int orig_mpwr; */
}; };
#define CHAN_FMT \ #define CHAN_FMT \
@ -1287,7 +1286,7 @@ void dump_wfd_ie(u8 *ie, u32 ie_len);
int rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen); int rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen);
int rtw_get_wfd_ie_from_scan_queue(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen, u8 frame_type); int rtw_get_wfd_ie_from_scan_queue(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen, u8 frame_type);
int rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id ,u8 *attr_content, uint *attr_contentlen); int rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id ,u8 *attr_content, uint *attr_contentlen);
#endif // CONFIG_P2P #endif /* CONFIG_P2P */
uint rtw_get_rateset_len(u8 *rateset); uint rtw_get_rateset_len(u8 *rateset);

2
include/ieee80211_ext.h
View file

@ -125,7 +125,7 @@ struct wme_parameter_element {
} while (0) } while (0)
#define RSN_SELECTOR_PUT(a, val) WPA_PUT_BE32((u8 *) (a), (val)) #define RSN_SELECTOR_PUT(a, val) WPA_PUT_BE32((u8 *) (a), (val))
//#define RSN_SELECTOR_PUT(a, val) WPA_PUT_LE32((u8 *) (a), (val)) /* define RSN_SELECTOR_PUT(a, val) WPA_PUT_LE32((u8 *) (a), (val)) */

2
include/if_ether.h
View file

@ -98,7 +98,7 @@ struct ethhdr
}; };
struct _vlan { struct _vlan {
unsigned short h_vlan_TCI; // Encapsulates priority and VLAN ID unsigned short h_vlan_TCI; /* Encapsulates priority and VLAN ID */
unsigned short h_vlan_encapsulated_proto; unsigned short h_vlan_encapsulated_proto;
}; };

10
include/ioctl_cfg80211.h
View file

@ -81,8 +81,8 @@ struct rtw_wdev_priv
struct cfg80211_scan_request *scan_request; struct cfg80211_scan_request *scan_request;
spinlock_t scan_req_lock; spinlock_t scan_req_lock;
struct net_device *pmon_ndev;//for monitor interface struct net_device *pmon_ndev;/* for monitor interface */
char ifname_mon[IFNAMSIZ + 1]; //interface name for monitor interface char ifname_mon[IFNAMSIZ + 1]; /* interface name for monitor interface */
u8 p2p_enabled; u8 p2p_enabled;
@ -119,7 +119,7 @@ void rtw_cfg80211_indicate_scan_done(struct rtw_wdev_priv *pwdev_priv, bool abor
#ifdef CONFIG_AP_MODE #ifdef CONFIG_AP_MODE
void rtw_cfg80211_indicate_sta_assoc(struct adapter *padapter, u8 *pmgmt_frame, uint frame_len); void rtw_cfg80211_indicate_sta_assoc(struct adapter *padapter, u8 *pmgmt_frame, uint frame_len);
void rtw_cfg80211_indicate_sta_disassoc(struct adapter *padapter, unsigned char *da, unsigned short reason); void rtw_cfg80211_indicate_sta_disassoc(struct adapter *padapter, unsigned char *da, unsigned short reason);
#endif //CONFIG_AP_MODE #endif /* CONFIG_AP_MODE */
void rtw_cfg80211_issue_p2p_provision_request(struct adapter *padapter, const u8 *buf, size_t len); void rtw_cfg80211_issue_p2p_provision_request(struct adapter *padapter, const u8 *buf, size_t len);
void rtw_cfg80211_rx_p2p_action_public(struct adapter *padapter, u8 *pmgmt_frame, uint frame_len); void rtw_cfg80211_rx_p2p_action_public(struct adapter *padapter, u8 *pmgmt_frame, uint frame_len);
@ -138,7 +138,7 @@ bool rtw_cfg80211_pwr_mgmt(struct adapter *adapter);
#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->rtw_wdev, freq, sig_dbm, buf, len, gfp) #define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->rtw_wdev, freq, sig_dbm, buf, len, gfp)
#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3,18,0)) #elif (LINUX_VERSION_CODE < KERNEL_VERSION(3,18,0))
#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->rtw_wdev, freq, sig_dbm, buf, len, 0, gfp) #define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->rtw_wdev, freq, sig_dbm, buf, len, 0, gfp)
#else // kernel >= 3.18 #else /* kernel >= 3.18 */
#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->rtw_wdev, freq, sig_dbm, buf, len, 0) #define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->rtw_wdev, freq, sig_dbm, buf, len, 0)
#endif #endif
@ -165,4 +165,4 @@ bool rtw_cfg80211_pwr_mgmt(struct adapter *adapter);
#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->rtw_wdev, cookie, chan, gfp) #define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->rtw_wdev, cookie, chan, gfp)
#endif #endif
#endif //__IOCTL_CFG80211_H__ #endif /* __IOCTL_CFG80211_H__ */

2
include/mlme_osdep.h
View file

@ -39,4 +39,4 @@ void rtw_indicate_wx_assoc_event(struct adapter *padapter);
void rtw_indicate_wx_disassoc_event(struct adapter *padapter); void rtw_indicate_wx_disassoc_event(struct adapter *padapter);
void indicate_wx_scan_complete_event(struct adapter *padapter); void indicate_wx_scan_complete_event(struct adapter *padapter);
#endif //_MLME_OSDEP_H_ #endif /* _MLME_OSDEP_H_ */

240
include/mp_custom_oid.h
View file

@ -20,20 +20,20 @@
#ifndef __CUSTOM_OID_H #ifndef __CUSTOM_OID_H
#define __CUSTOM_OID_H #define __CUSTOM_OID_H
// by Owen /* by Owen */
// 0xFF818000 - 0xFF81802F RTL8180 Mass Production Kit /* 0xFF818000 - 0xFF81802F RTL8180 Mass Production Kit */
// 0xFF818500 - 0xFF81850F RTL8185 Setup Utility /* 0xFF818500 - 0xFF81850F RTL8185 Setup Utility */
// 0xFF818580 - 0xFF81858F RTL8185 Phy Status Utility /* 0xFF818580 - 0xFF81858F RTL8185 Phy Status Utility */
// /* */
// by Owen for Production Kit /* by Owen for Production Kit */
// For Production Kit with Agilent Equipments /* For Production Kit with Agilent Equipments */
// in order to make our custom oids hopefully somewhat unique /* in order to make our custom oids hopefully somewhat unique */
// we will use 0xFF (indicating implementation specific OID) /* we will use 0xFF (indicating implementation specific OID) */
// 81(first byte of non zero Realtek unique identifier) /* 81(first byte of non zero Realtek unique identifier) */
// 80 (second byte of non zero Realtek unique identifier) /* 80 (second byte of non zero Realtek unique identifier) */
// XX (the custom OID number - providing 255 possible custom oids) /* XX (the custom OID number - providing 255 possible custom oids) */
#define OID_RT_PRO_RESET_DUT 0xFF818000 #define OID_RT_PRO_RESET_DUT 0xFF818000
#define OID_RT_PRO_SET_DATA_RATE 0xFF818001 #define OID_RT_PRO_SET_DATA_RATE 0xFF818001
@ -78,26 +78,26 @@
#define OID_RT_PRO_QUERY_PERMANENT_ADDRESS 0xFF818029 #define OID_RT_PRO_QUERY_PERMANENT_ADDRESS 0xFF818029
#define OID_RT_PRO_SET_PHILIPS_RF_PARAMETERS 0xFF81802A #define OID_RT_PRO_SET_PHILIPS_RF_PARAMETERS 0xFF81802A
#define OID_RT_PRO_RECEIVE_PACKET 0xFF81802C #define OID_RT_PRO_RECEIVE_PACKET 0xFF81802C
// added by Owen on 04/08/03 for Cameo's request /* added by Owen on 04/08/03 for Cameo's request */
#define OID_RT_PRO_WRITE_EEPROM_BYTE 0xFF81802D #define OID_RT_PRO_WRITE_EEPROM_BYTE 0xFF81802D
#define OID_RT_PRO_READ_EEPROM_BYTE 0xFF81802E #define OID_RT_PRO_READ_EEPROM_BYTE 0xFF81802E
#define OID_RT_PRO_SET_MODULATION 0xFF81802F #define OID_RT_PRO_SET_MODULATION 0xFF81802F
// /* */
//Sean /* Sean */
#define OID_RT_DRIVER_OPTION 0xFF818080 #define OID_RT_DRIVER_OPTION 0xFF818080
#define OID_RT_RF_OFF 0xFF818081 #define OID_RT_RF_OFF 0xFF818081
#define OID_RT_AUTH_STATUS 0xFF818082 #define OID_RT_AUTH_STATUS 0xFF818082
//======================================================================== /* */
#define OID_RT_PRO_SET_CONTINUOUS_TX 0xFF81800B #define OID_RT_PRO_SET_CONTINUOUS_TX 0xFF81800B
#define OID_RT_PRO_SET_SINGLE_CARRIER_TX 0xFF81800C #define OID_RT_PRO_SET_SINGLE_CARRIER_TX 0xFF81800C
#define OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX 0xFF81802B #define OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX 0xFF81802B
#define OID_RT_PRO_SET_SINGLE_TONE_TX 0xFF818043 #define OID_RT_PRO_SET_SINGLE_TONE_TX 0xFF818043
//======================================================================== /* */
// by Owen for RTL8185 Phy Status Report Utility /* by Owen for RTL8185 Phy Status Report Utility */
#define OID_RT_UTILITYfalse_ALARM_COUNTERS 0xFF818580 #define OID_RT_UTILITYfalse_ALARM_COUNTERS 0xFF818580
#define OID_RT_UTILITY_SELECT_DEBUG_MODE 0xFF818581 #define OID_RT_UTILITY_SELECT_DEBUG_MODE 0xFF818581
#define OID_RT_UTILITY_SELECT_SUBCARRIER_NUMBER 0xFF818582 #define OID_RT_UTILITY_SELECT_SUBCARRIER_NUMBER 0xFF818582
@ -105,14 +105,14 @@
#define OID_RT_UTILITY_GET_FRAME_DETECTION_STATUS 0xFF818584 #define OID_RT_UTILITY_GET_FRAME_DETECTION_STATUS 0xFF818584
#define OID_RT_UTILITY_GET_AGC_AND_FREQUENCY_OFFSET_ESTIMATION_STATUS 0xFF818585 #define OID_RT_UTILITY_GET_AGC_AND_FREQUENCY_OFFSET_ESTIMATION_STATUS 0xFF818585
#define OID_RT_UTILITY_GET_CHANNEL_ESTIMATION_STATUS 0xFF818586 #define OID_RT_UTILITY_GET_CHANNEL_ESTIMATION_STATUS 0xFF818586
// /* */
// by Owen on 03/09/19-03/09/22 for RTL8185 /* by Owen on 03/09/19-03/09/22 for RTL8185 */
#define OID_RT_WIRELESS_MODE 0xFF818500 #define OID_RT_WIRELESS_MODE 0xFF818500
#define OID_RT_SUPPORTED_RATES 0xFF818501 #define OID_RT_SUPPORTED_RATES 0xFF818501
#define OID_RT_DESIRED_RATES 0xFF818502 #define OID_RT_DESIRED_RATES 0xFF818502
#define OID_RT_WIRELESS_MODE_STARTING_ADHOC 0xFF818503 #define OID_RT_WIRELESS_MODE_STARTING_ADHOC 0xFF818503
// /* */
#define OID_RT_GET_CONNECT_STATE 0xFF030001 #define OID_RT_GET_CONNECT_STATE 0xFF030001
#define OID_RT_RESCAN 0xFF030002 #define OID_RT_RESCAN 0xFF030002
@ -127,8 +127,8 @@
#define OID_RT_GET_LARGE_PACKET_CRC 0xFF010187 #define OID_RT_GET_LARGE_PACKET_CRC 0xFF010187
#define OID_RT_GET_TX_RETRY 0xFF010188 #define OID_RT_GET_TX_RETRY 0xFF010188
#define OID_RT_GET_RX_RETRY 0xFF010189 #define OID_RT_GET_RX_RETRY 0xFF010189
#define OID_RT_PRO_SET_FW_DIG_STATE 0xFF01018A//S #define OID_RT_PRO_SET_FW_DIG_STATE 0xFF01018A/* S */
#define OID_RT_PRO_SET_FW_RA_STATE 0xFF01018B//S #define OID_RT_PRO_SET_FW_RA_STATE 0xFF01018B/* S */
#define OID_RT_GET_RX_TOTAL_PACKET 0xFF010190 #define OID_RT_GET_RX_TOTAL_PACKET 0xFF010190
#define OID_RT_GET_TX_BEACON_OK 0xFF010191 #define OID_RT_GET_TX_BEACON_OK 0xFF010191
@ -155,9 +155,9 @@
#define OID_RT_GET_CCA_UPGRADE_EVALUATE_TIMES 0xFF0101A3 #define OID_RT_GET_CCA_UPGRADE_EVALUATE_TIMES 0xFF0101A3
#define OID_RT_GET_CCA_FALLBACK_EVALUATE_TIMES 0xFF0101A4 #define OID_RT_GET_CCA_FALLBACK_EVALUATE_TIMES 0xFF0101A4
// by Owen on 03/31/03 for Cameo's request /* by Owen on 03/31/03 for Cameo's request */
#define OID_RT_SET_RATE_ADAPTIVE 0xFF0101A5 #define OID_RT_SET_RATE_ADAPTIVE 0xFF0101A5
// /* */
#define OID_RT_GET_DCST_EVALUATE_PERIOD 0xFF0101A5 #define OID_RT_GET_DCST_EVALUATE_PERIOD 0xFF0101A5
#define OID_RT_GET_DCST_TIME_UNIT_INDEX 0xFF0101A6 #define OID_RT_GET_DCST_TIME_UNIT_INDEX 0xFF0101A6
#define OID_RT_GET_TOTAL_TX_BYTES 0xFF0101A7 #define OID_RT_GET_TOTAL_TX_BYTES 0xFF0101A7
@ -188,20 +188,20 @@
#define OID_RT_RF_READ_WRITE_OFFSET 0xFF0101BF #define OID_RT_RF_READ_WRITE_OFFSET 0xFF0101BF
#define OID_RT_RF_READ_WRITE 0xFF0101C0 #define OID_RT_RF_READ_WRITE 0xFF0101C0
// For Netgear request. 2005.01.13, by rcnjko. /* For Netgear request. 2005.01.13, by rcnjko. */
#define OID_RT_FORCED_DATA_RATE 0xFF0101C1 #define OID_RT_FORCED_DATA_RATE 0xFF0101C1
#define OID_RT_WIRELESS_MODE_FOR_SCAN_LIST 0xFF0101C2 #define OID_RT_WIRELESS_MODE_FOR_SCAN_LIST 0xFF0101C2
// For Netgear request. 2005.02.17, by rcnjko. /* For Netgear request. 2005.02.17, by rcnjko. */
#define OID_RT_GET_BSS_WIRELESS_MODE 0xFF0101C3 #define OID_RT_GET_BSS_WIRELESS_MODE 0xFF0101C3
// For AZ project. 2005.06.27, by rcnjko. /* For AZ project. 2005.06.27, by rcnjko. */
#define OID_RT_SCAN_WITH_MAGIC_PACKET 0xFF0101C4 #define OID_RT_SCAN_WITH_MAGIC_PACKET 0xFF0101C4
// Vincent 8185MP /* Vincent 8185MP */
#define OID_RT_PRO_RX_FILTER 0xFF0111C0 #define OID_RT_PRO_RX_FILTER 0xFF0111C0
//Andy TEST /* Andy TEST */
//#define OID_RT_PRO_WRITE_REGISTRY 0xFF0111C1 /* define OID_RT_PRO_WRITE_REGISTRY 0xFF0111C1 */
//#define OID_RT_PRO_READ_REGISTRY 0xFF0111C2 /* define OID_RT_PRO_READ_REGISTRY 0xFF0111C2 */
#define OID_CE_USB_WRITE_REGISTRY 0xFF0111C1 #define OID_CE_USB_WRITE_REGISTRY 0xFF0111C1
#define OID_CE_USB_READ_REGISTRY 0xFF0111C2 #define OID_CE_USB_READ_REGISTRY 0xFF0111C2
@ -215,139 +215,139 @@
#define OID_RT_PRO_RF_READ_REGISTRY 0xFF0111C9 #define OID_RT_PRO_RF_READ_REGISTRY 0xFF0111C9
#define OID_RT_PRO_QUERY_RF_TYPE 0xFF0111CA #define OID_RT_PRO_QUERY_RF_TYPE 0xFF0111CA
// AP OID /* AP OID */
#define OID_RT_AP_GET_ASSOCIATED_STATION_LIST 0xFF010300 #define OID_RT_AP_GET_ASSOCIATED_STATION_LIST 0xFF010300
#define OID_RT_AP_GET_CURRENT_TIME_STAMP 0xFF010301 #define OID_RT_AP_GET_CURRENT_TIME_STAMP 0xFF010301
#define OID_RT_AP_SWITCH_INTO_AP_MODE 0xFF010302 #define OID_RT_AP_SWITCH_INTO_AP_MODE 0xFF010302
#define OID_RT_AP_SET_DTIM_PERIOD 0xFF010303 #define OID_RT_AP_SET_DTIM_PERIOD 0xFF010303
#define OID_RT_AP_SUPPORTED 0xFF010304 // Determine if driver supports AP mode. 2004.08.27, by rcnjko. #define OID_RT_AP_SUPPORTED 0xFF010304 /* Determine if driver supports AP mode. 2004.08.27, by rcnjko. */
#define OID_RT_AP_SET_PASSPHRASE 0xFF010305 // Set WPA-PSK passphrase into authenticator. 2005.07.08, byrcnjko. #define OID_RT_AP_SET_PASSPHRASE 0xFF010305 /* Set WPA-PSK passphrase into authenticator. 2005.07.08, byrcnjko. */
// 8187MP. 2004.09.06, by rcnjko. /* 8187MP. 2004.09.06, by rcnjko. */
#define OID_RT_PRO8187_WI_POLL 0xFF818780 #define OID_RT_PRO8187_WI_POLL 0xFF818780
#define OID_RT_PRO_WRITE_BB_REG 0xFF818781 #define OID_RT_PRO_WRITE_BB_REG 0xFF818781
#define OID_RT_PRO_READ_BB_REG 0xFF818782 #define OID_RT_PRO_READ_BB_REG 0xFF818782
#define OID_RT_PRO_WRITE_RF_REG 0xFF818783 #define OID_RT_PRO_WRITE_RF_REG 0xFF818783
#define OID_RT_PRO_READ_RF_REG 0xFF818784 #define OID_RT_PRO_READ_RF_REG 0xFF818784
// Meeting House. added by Annie, 2005-07-20. /* Meeting House. added by Annie, 2005-07-20. */
#define OID_RT_MH_VENDER_ID 0xFFEDC100 #define OID_RT_MH_VENDER_ID 0xFFEDC100
//8711 MP OID added 20051230. /* 8711 MP OID added 20051230. */
#define OID_RT_PRO8711_JOIN_BSS 0xFF871100//S #define OID_RT_PRO8711_JOIN_BSS 0xFF871100/* S */
#define OID_RT_PRO_READ_REGISTER 0xFF871101 //Q #define OID_RT_PRO_READ_REGISTER 0xFF871101 /* Q */
#define OID_RT_PRO_WRITE_REGISTER 0xFF871102 //S #define OID_RT_PRO_WRITE_REGISTER 0xFF871102 /* S */
#define OID_RT_PRO_BURST_READ_REGISTER 0xFF871103 //Q #define OID_RT_PRO_BURST_READ_REGISTER 0xFF871103 /* Q */
#define OID_RT_PRO_BURST_WRITE_REGISTER 0xFF871104 //S #define OID_RT_PRO_BURST_WRITE_REGISTER 0xFF871104 /* S */
#define OID_RT_PRO_WRITE_TXCMD 0xFF871105 //S #define OID_RT_PRO_WRITE_TXCMD 0xFF871105 /* S */
#define OID_RT_PRO_READ16_EEPROM 0xFF871106 //Q #define OID_RT_PRO_READ16_EEPROM 0xFF871106 /* Q */
#define OID_RT_PRO_WRITE16_EEPROM 0xFF871107 //S #define OID_RT_PRO_WRITE16_EEPROM 0xFF871107 /* S */
#define OID_RT_PRO_H2C_SET_COMMAND 0xFF871108 //S #define OID_RT_PRO_H2C_SET_COMMAND 0xFF871108 /* S */
#define OID_RT_PRO_H2C_QUERY_RESULT 0xFF871109 //Q #define OID_RT_PRO_H2C_QUERY_RESULT 0xFF871109 /* Q */
#define OID_RT_PRO8711_WI_POLL 0xFF87110A //Q #define OID_RT_PRO8711_WI_POLL 0xFF87110A /* Q */
#define OID_RT_PRO8711_PKT_LOSS 0xFF87110B //Q #define OID_RT_PRO8711_PKT_LOSS 0xFF87110B /* Q */
#define OID_RT_RD_ATTRIB_MEM 0xFF87110C//Q #define OID_RT_RD_ATTRIB_MEM 0xFF87110C/* Q */
#define OID_RT_WR_ATTRIB_MEM 0xFF87110D//S #define OID_RT_WR_ATTRIB_MEM 0xFF87110D/* S */
//Method 2 for H2C/C2H /* Method 2 for H2C/C2H */
#define OID_RT_PRO_H2C_CMD_MODE 0xFF871110 //S #define OID_RT_PRO_H2C_CMD_MODE 0xFF871110 /* S */
#define OID_RT_PRO_H2C_CMD_RSP_MODE 0xFF871111 //Q #define OID_RT_PRO_H2C_CMD_RSP_MODE 0xFF871111 /* Q */
#define OID_RT_PRO_H2C_CMD_EVENT_MODE 0xFF871112 //S #define OID_RT_PRO_H2C_CMD_EVENT_MODE 0xFF871112 /* S */
#define OID_RT_PRO_WAIT_C2H_EVENT 0xFF871113 //Q #define OID_RT_PRO_WAIT_C2H_EVENT 0xFF871113 /* Q */
#define OID_RT_PRO_RW_ACCESS_PROTOCOL_TEST 0xFF871114//Q #define OID_RT_PRO_RW_ACCESS_PROTOCOL_TEST 0xFF871114/* Q */
#define OID_RT_PRO_SCSI_ACCESS_TEST 0xFF871115 //Q, S #define OID_RT_PRO_SCSI_ACCESS_TEST 0xFF871115 /* Q, S */
#define OID_RT_PRO_SCSI_TCPIPOFFLOAD_OUT 0xFF871116 //S #define OID_RT_PRO_SCSI_TCPIPOFFLOAD_OUT 0xFF871116 /* S */
#define OID_RT_PRO_SCSI_TCPIPOFFLOAD_IN 0xFF871117 //Q,S #define OID_RT_PRO_SCSI_TCPIPOFFLOAD_IN 0xFF871117 /* Q,S */
#define OID_RT_RRO_RX_PKT_VIA_IOCTRL 0xFF871118 //Q #define OID_RT_RRO_RX_PKT_VIA_IOCTRL 0xFF871118 /* Q */
#define OID_RT_RRO_RX_PKTARRAY_VIA_IOCTRL 0xFF871119 //Q #define OID_RT_RRO_RX_PKTARRAY_VIA_IOCTRL 0xFF871119 /* Q */
#define OID_RT_RPO_SET_PWRMGT_TEST 0xFF87111A //S #define OID_RT_RPO_SET_PWRMGT_TEST 0xFF87111A /* S */
#define OID_RT_PRO_QRY_PWRMGT_TEST 0XFF87111B //Q #define OID_RT_PRO_QRY_PWRMGT_TEST 0XFF87111B /* Q */
#define OID_RT_RPO_ASYNC_RWIO_TEST 0xFF87111C //S #define OID_RT_RPO_ASYNC_RWIO_TEST 0xFF87111C /* S */
#define OID_RT_RPO_ASYNC_RWIO_POLL 0xFF87111D //Q #define OID_RT_RPO_ASYNC_RWIO_POLL 0xFF87111D /* Q */
#define OID_RT_PRO_SET_RF_INTFS 0xFF87111E //S #define OID_RT_PRO_SET_RF_INTFS 0xFF87111E /* S */
#define OID_RT_POLL_RX_STATUS 0xFF87111F //Q #define OID_RT_POLL_RX_STATUS 0xFF87111F /* Q */
#define OID_RT_PRO_CFG_DEBUG_MESSAGE 0xFF871120 //Q,S #define OID_RT_PRO_CFG_DEBUG_MESSAGE 0xFF871120 /* Q,S */
#define OID_RT_PRO_SET_DATA_RATE_EX 0xFF871121//S #define OID_RT_PRO_SET_DATA_RATE_EX 0xFF871121/* S */
#define OID_RT_PRO_SET_BASIC_RATE 0xFF871122//S #define OID_RT_PRO_SET_BASIC_RATE 0xFF871122/* S */
#define OID_RT_PRO_READ_TSSI 0xFF871123//S #define OID_RT_PRO_READ_TSSI 0xFF871123/* S */
#define OID_RT_PRO_SET_POWER_TRACKING 0xFF871124//S #define OID_RT_PRO_SET_POWER_TRACKING 0xFF871124/* S */
#define OID_RT_PRO_QRY_PWRSTATE 0xFF871150 //Q #define OID_RT_PRO_QRY_PWRSTATE 0xFF871150 /* Q */
#define OID_RT_PRO_SET_PWRSTATE 0xFF871151 //S #define OID_RT_PRO_SET_PWRSTATE 0xFF871151 /* S */
//Method 2 , using workitem /* Method 2 , using workitem */
#define OID_RT_SET_READ_REG 0xFF871181 //S #define OID_RT_SET_READ_REG 0xFF871181 /* S */
#define OID_RT_SET_WRITE_REG 0xFF871182 //S #define OID_RT_SET_WRITE_REG 0xFF871182 /* S */
#define OID_RT_SET_BURST_READ_REG 0xFF871183 //S #define OID_RT_SET_BURST_READ_REG 0xFF871183 /* S */
#define OID_RT_SET_BURST_WRITE_REG 0xFF871184 //S #define OID_RT_SET_BURST_WRITE_REG 0xFF871184 /* S */
#define OID_RT_SET_WRITE_TXCMD 0xFF871185 //S #define OID_RT_SET_WRITE_TXCMD 0xFF871185 /* S */
#define OID_RT_SET_READ16_EEPROM 0xFF871186 //S #define OID_RT_SET_READ16_EEPROM 0xFF871186 /* S */
#define OID_RT_SET_WRITE16_EEPROM 0xFF871187 //S #define OID_RT_SET_WRITE16_EEPROM 0xFF871187 /* S */
#define OID_RT_QRY_POLL_WKITEM 0xFF871188 //Q #define OID_RT_QRY_POLL_WKITEM 0xFF871188 /* Q */
//For SDIO INTERFACE only /* For SDIO INTERFACE only */
#define OID_RT_PRO_SYNCPAGERW_SRAM 0xFF8711A0 //Q, S #define OID_RT_PRO_SYNCPAGERW_SRAM 0xFF8711A0 /* Q, S */
#define OID_RT_PRO_871X_DRV_EXT 0xFF8711A1 #define OID_RT_PRO_871X_DRV_EXT 0xFF8711A1
//For USB INTERFACE only /* For USB INTERFACE only */
#define OID_RT_PRO_USB_VENDOR_REQ 0xFF8711B0 //Q, S #define OID_RT_PRO_USB_VENDOR_REQ 0xFF8711B0 /* Q, S */
#define OID_RT_PRO_SCSI_AUTO_TEST 0xFF8711B1 //S #define OID_RT_PRO_SCSI_AUTO_TEST 0xFF8711B1 /* S */
#define OID_RT_PRO_USB_MAC_AC_FIFO_WRITE 0xFF8711B2 //S #define OID_RT_PRO_USB_MAC_AC_FIFO_WRITE 0xFF8711B2 /* S */
#define OID_RT_PRO_USB_MAC_RX_FIFO_READ 0xFF8711B3 //Q #define OID_RT_PRO_USB_MAC_RX_FIFO_READ 0xFF8711B3 /* Q */
#define OID_RT_PRO_USB_MAC_RX_FIFO_POLLING 0xFF8711B4 //Q #define OID_RT_PRO_USB_MAC_RX_FIFO_POLLING 0xFF8711B4 /* Q */
#define OID_RT_PRO_H2C_SET_RATE_TABLE 0xFF8711FB //S #define OID_RT_PRO_H2C_SET_RATE_TABLE 0xFF8711FB /* S */
#define OID_RT_PRO_H2C_GET_RATE_TABLE 0xFF8711FC //S #define OID_RT_PRO_H2C_GET_RATE_TABLE 0xFF8711FC /* S */
#define OID_RT_PRO_H2C_C2H_LBK_TEST 0xFF8711FE #define OID_RT_PRO_H2C_C2H_LBK_TEST 0xFF8711FE
#define OID_RT_PRO_ENCRYPTION_CTRL 0xFF871200 //Q, S #define OID_RT_PRO_ENCRYPTION_CTRL 0xFF871200 /* Q, S */
#define OID_RT_PRO_ADD_STA_INFO 0xFF871201 //S #define OID_RT_PRO_ADD_STA_INFO 0xFF871201 /* S */
#define OID_RT_PRO_DELE_STA_INFO 0xFF871202 //S #define OID_RT_PRO_DELE_STA_INFO 0xFF871202 /* S */
#define OID_RT_PRO_QUERY_DR_VARIABLE 0xFF871203 //Q #define OID_RT_PRO_QUERY_DR_VARIABLE 0xFF871203 /* Q */
#define OID_RT_PRO_RX_PACKET_TYPE 0xFF871204 //Q, S #define OID_RT_PRO_RX_PACKET_TYPE 0xFF871204 /* Q, S */
#define OID_RT_PRO_READ_EFUSE 0xFF871205 //Q #define OID_RT_PRO_READ_EFUSE 0xFF871205 /* Q */
#define OID_RT_PRO_WRITE_EFUSE 0xFF871206 //S #define OID_RT_PRO_WRITE_EFUSE 0xFF871206 /* S */
#define OID_RT_PRO_RW_EFUSE_PGPKT 0xFF871207 //Q, S #define OID_RT_PRO_RW_EFUSE_PGPKT 0xFF871207 /* Q, S */
#define OID_RT_GET_EFUSE_CURRENT_SIZE 0xFF871208 //Q #define OID_RT_GET_EFUSE_CURRENT_SIZE 0xFF871208 /* Q */
#define OID_RT_SET_BANDWIDTH 0xFF871209 //S #define OID_RT_SET_BANDWIDTH 0xFF871209 /* S */
#define OID_RT_SET_CRYSTAL_CAP 0xFF87120A //S #define OID_RT_SET_CRYSTAL_CAP 0xFF87120A /* S */
#define OID_RT_SET_RX_PACKET_TYPE 0xFF87120B //S #define OID_RT_SET_RX_PACKET_TYPE 0xFF87120B /* S */
#define OID_RT_GET_EFUSE_MAX_SIZE 0xFF87120C //Q #define OID_RT_GET_EFUSE_MAX_SIZE 0xFF87120C /* Q */
#define OID_RT_PRO_SET_TX_AGC_OFFSET 0xFF87120D //S #define OID_RT_PRO_SET_TX_AGC_OFFSET 0xFF87120D /* S */
#define OID_RT_PRO_SET_PKT_TEST_MODE 0xFF87120E //S #define OID_RT_PRO_SET_PKT_TEST_MODE 0xFF87120E /* S */
#define OID_RT_PRO_FOR_EVM_TEST_SETTING 0xFF87120F //S #define OID_RT_PRO_FOR_EVM_TEST_SETTING 0xFF87120F /* S */
#define OID_RT_PRO_GET_THERMAL_METER 0xFF871210 //Q #define OID_RT_PRO_GET_THERMAL_METER 0xFF871210 /* Q */
#define OID_RT_RESET_PHY_RX_PACKET_COUNT 0xFF871211 //S #define OID_RT_RESET_PHY_RX_PACKET_COUNT 0xFF871211 /* S */
#define OID_RT_GET_PHY_RX_PACKET_RECEIVED 0xFF871212 //Q #define OID_RT_GET_PHY_RX_PACKET_RECEIVED 0xFF871212 /* Q */
#define OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR 0xFF871213 //Q #define OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR 0xFF871213 /* Q */
#define OID_RT_SET_POWER_DOWN 0xFF871214 //S #define OID_RT_SET_POWER_DOWN 0xFF871214 /* S */
#define OID_RT_GET_POWER_MODE 0xFF871215 //Q #define OID_RT_GET_POWER_MODE 0xFF871215 /* Q */
#define OID_RT_PRO_EFUSE 0xFF871216 //Q, S #define OID_RT_PRO_EFUSE 0xFF871216 /* Q, S */
#define OID_RT_PRO_EFUSE_MAP 0xFF871217 //Q, S #define OID_RT_PRO_EFUSE_MAP 0xFF871217 /* Q, S */
#endif //#ifndef __CUSTOM_OID_H #endif /* ifndef __CUSTOM_OID_H */

2
include/nic_spec.h
View file

@ -43,4 +43,4 @@
#include <rtl8711_bitdef.h> #include <rtl8711_bitdef.h>
#endif // __RTL8711_SPEC_H__ #endif /* __RTL8711_SPEC_H__ */

18
include/osdep_intf.h
View file

@ -28,14 +28,14 @@
struct intf_priv { struct intf_priv {
u8 *intf_dev; u8 *intf_dev;
u32 max_iosz; //USB2.0: 128, USB1.1: 64, SDIO:64 u32 max_iosz; /* USB2.0: 128, USB1.1: 64, SDIO:64 */
u32 max_xmitsz; //USB2.0: unlimited, SDIO:512 u32 max_xmitsz; /* USB2.0: unlimited, SDIO:512 */
u32 max_recvsz; //USB2.0: unlimited, SDIO:512 u32 max_recvsz; /* USB2.0: unlimited, SDIO:512 */
volatile u8 *io_rwmem; volatile u8 *io_rwmem;
volatile u8 *allocated_io_rwmem; volatile u8 *allocated_io_rwmem;
u32 io_wsz; //unit: 4bytes u32 io_wsz; /* unit: 4bytes */
u32 io_rsz;//unit: 4bytes u32 io_rsz;/* unit: 4bytes */
u8 intf_status; u8 intf_status;
void (*_bus_io)(u8 *priv); void (*_bus_io)(u8 *priv);
@ -51,7 +51,7 @@ The protection mechanism is through the pending queue.
_mutex ioctl_mutex; _mutex ioctl_mutex;
// when in USB, IO is through interrupt in/out endpoints /* when in USB, IO is through interrupt in/out endpoints */
struct usb_device *udev; struct usb_device *udev;
struct urb *piorw_urb; struct urb *piorw_urb;
u8 io_irp_cnt; u8 io_irp_cnt;
@ -91,10 +91,10 @@ u16 rtw_recv_select_queue(struct sk_buff *skb,
#ifdef CONFIG_PROC_DEBUG #ifdef CONFIG_PROC_DEBUG
void rtw_proc_init_one(struct net_device *dev); void rtw_proc_init_one(struct net_device *dev);
void rtw_proc_remove_one(struct net_device *dev); void rtw_proc_remove_one(struct net_device *dev);
#else //!CONFIG_PROC_DEBUG #else /* CONFIG_PROC_DEBUG */
static void rtw_proc_init_one(struct net_device *dev){} static void rtw_proc_init_one(struct net_device *dev){}
static void rtw_proc_remove_one(struct net_device *dev){} static void rtw_proc_remove_one(struct net_device *dev){}
#endif //!CONFIG_PROC_DEBUG #endif /* CONFIG_PROC_DEBUG */
void rtw_ips_dev_unload(struct adapter *padapter); void rtw_ips_dev_unload(struct adapter *padapter);
@ -111,4 +111,4 @@ int rtw_resume_common(struct adapter *padapter);
int rtw_gw_addr_query(struct adapter *padapter); int rtw_gw_addr_query(struct adapter *padapter);
#endif #endif
#endif //_OSDEP_INTF_H_ #endif /* _OSDEP_INTF_H_ */

36
include/osdep_service.h
View file

@ -26,7 +26,7 @@
#define _FAIL 0 #define _FAIL 0
#define _SUCCESS 1 #define _SUCCESS 1
#define RTW_RX_HANDLED 2 #define RTW_RX_HANDLED 2
//#define RTW_STATUS_TIMEDOUT -110 /* define RTW_STATUS_TIMEDOUT -110 */
#include <linux/version.h> #include <linux/version.h>
#include <linux/spinlock.h> #include <linux/spinlock.h>
@ -39,7 +39,7 @@
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,5)) #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,5))
#include <linux/kref.h> #include <linux/kref.h>
#endif #endif
//#include <linux/smp_lock.h> /* include <linux/smp_lock.h> */
#include <linux/netdevice.h> #include <linux/netdevice.h>
#include <linux/skbuff.h> #include <linux/skbuff.h>
#include <linux/circ_buf.h> #include <linux/circ_buf.h>
@ -59,8 +59,8 @@
#include <linux/if_arp.h> #include <linux/if_arp.h>
#include <linux/rtnetlink.h> #include <linux/rtnetlink.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/proc_fs.h> // Necessary because we use the proc fs #include <linux/proc_fs.h> /* Necessary because we use the proc fs */
#include <linux/interrupt.h> // for struct tasklet_struct #include <linux/interrupt.h> /* for struct tasklet_struct */
#include <linux/ip.h> #include <linux/ip.h>
#include <linux/kthread.h> #include <linux/kthread.h>
#include <linux/in.h> #include <linux/in.h>
@ -82,7 +82,7 @@ extern char* rtw_initmac;
extern int rtw_ht_enable; extern int rtw_ht_enable;
extern int rtw_cbw40_enable; extern int rtw_cbw40_enable;
extern int rtw_ampdu_enable;//for enable tx_ampdu extern int rtw_ampdu_enable;/* for enable tx_ampdu */
extern int ui_pid[3]; extern int ui_pid[3];
@ -119,7 +119,7 @@ int pm_netdev_open(struct net_device *pnetdev,u8 bnormal);
#endif #endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22)) #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22))
// Porting from linux kernel, for compatible with old kernel. /* Porting from linux kernel, for compatible with old kernel. */
static inline unsigned char *skb_tail_pointer(const struct sk_buff *skb) static inline unsigned char *skb_tail_pointer(const struct sk_buff *skb)
{ {
return skb->tail; return skb->tail;
@ -217,7 +217,7 @@ __inline static void _set_timer(struct timer_list *ptimer,u32 delay_time)
__inline static void _cancel_timer(struct timer_list *ptimer,u8 *bcancelled) __inline static void _cancel_timer(struct timer_list *ptimer,u8 *bcancelled)
{ {
del_timer_sync(ptimer); del_timer_sync(ptimer);
*bcancelled= true;//true ==1; false==0 *bcancelled= true;/* true ==1; false==0 */
} }
#define RTW_TIMER_HDL_ARGS void *FunctionContext #define RTW_TIMER_HDL_ARGS void *FunctionContext
@ -248,9 +248,9 @@ __inline static void _cancel_workitem_sync(struct work_struct *pwork)
flush_scheduled_work(); flush_scheduled_work();
#endif #endif
} }
// /* */
// Global Mutex: can only be used at PASSIVE level. /* Global Mutex: can only be used at PASSIVE level. */
// /* */
#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ #define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
{ \ { \
@ -349,7 +349,7 @@ static inline void rtw_netif_stop_queue(struct net_device *pnetdev)
int RTW_STATUS_CODE(int error_code); int RTW_STATUS_CODE(int error_code);
//#define CONFIG_USE_VMALLOC /* define CONFIG_USE_VMALLOC */
/* flags used for rtw_mstat_update() */ /* flags used for rtw_mstat_update() */
enum mstat_f { enum mstat_f {
@ -667,14 +667,14 @@ __inline static u32 bitshift(u32 bitmask)
#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] #define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5]
#endif #endif
//#ifdef __GNUC__ /* ifdef __GNUC__ */
#define STRUCT_PACKED __attribute__ ((packed)) #define STRUCT_PACKED __attribute__ ((packed))
// limitation of path length /* limitation of path length */
#define PATH_LENGTH_MAX PATH_MAX #define PATH_LENGTH_MAX PATH_MAX
// Suspend lock prevent system from going suspend /* Suspend lock prevent system from going suspend */
#ifdef CONFIG_WAKELOCK #ifdef CONFIG_WAKELOCK
#include <linux/wakelock.h> #include <linux/wakelock.h>
#elif defined(CONFIG_ANDROID_POWER) #elif defined(CONFIG_ANDROID_POWER)
@ -689,7 +689,7 @@ void rtw_lock_suspend_timeout(u32 timeout_ms);
void rtw_lock_ext_suspend_timeout(u32 timeout_ms); void rtw_lock_ext_suspend_timeout(u32 timeout_ms);
//Atomic integer operations /* Atomic integer operations */
#define ATOMIC_T atomic_t #define ATOMIC_T atomic_t
void ATOMIC_SET(ATOMIC_T *v, int i); void ATOMIC_SET(ATOMIC_T *v, int i);
@ -703,7 +703,7 @@ int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i);
int ATOMIC_INC_RETURN(ATOMIC_T *v); int ATOMIC_INC_RETURN(ATOMIC_T *v);
int ATOMIC_DEC_RETURN(ATOMIC_T *v); int ATOMIC_DEC_RETURN(ATOMIC_T *v);
//File operation APIs, just for linux now /* File operation APIs, just for linux now */
int rtw_is_file_readable(char *path); int rtw_is_file_readable(char *path);
int rtw_retrive_from_file(char *path, u8* buf, u32 sz); int rtw_retrive_from_file(char *path, u8* buf, u32 sz);
int rtw_store_to_file(char *path, u8* buf, u32 sz); int rtw_store_to_file(char *path, u8* buf, u32 sz);
@ -731,9 +731,9 @@ void rtw_free_netdev(struct net_device * netdev);
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)) #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27))
#define rtw_signal_process(pid, sig) kill_pid(find_vpid((pid)),(sig), 1) #define rtw_signal_process(pid, sig) kill_pid(find_vpid((pid)),(sig), 1)
#else //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)) #else /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)) */
#define rtw_signal_process(pid, sig) kill_proc((pid), (sig), 1) #define rtw_signal_process(pid, sig) kill_proc((pid), (sig), 1)
#endif //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)) #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)) */
u64 rtw_modular64(u64 x, u64 y); u64 rtw_modular64(u64 x, u64 y);
u64 rtw_division64(u64 x, u64 y); u64 rtw_division64(u64 x, u64 y);

2
include/recv_osdep.h
View file

@ -57,4 +57,4 @@ void rtw_os_read_port(struct adapter *padapter, struct recv_buf *precvbuf);
void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl); void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl);
#endif // #endif /* */

57
include/rtl8188e_cmd.h
View file

@ -22,7 +22,7 @@
typedef enum _RTL8188E_H2C_CMD_ID typedef enum _RTL8188E_H2C_CMD_ID
{ {
//Class Common /* Class Common */
H2C_COM_RSVD_PAGE =0x00, H2C_COM_RSVD_PAGE =0x00,
H2C_COM_MEDIA_STATUS_RPT =0x01, H2C_COM_MEDIA_STATUS_RPT =0x01,
H2C_COM_SCAN =0x02, H2C_COM_SCAN =0x02,
@ -34,30 +34,30 @@ typedef enum _RTL8188E_H2C_CMD_ID
H2C_COM_BCN_RSVD_PAGE =0x09, H2C_COM_BCN_RSVD_PAGE =0x09,
H2C_COM_PROB_RSP_RSVD_PAGE =0x0A, H2C_COM_PROB_RSP_RSVD_PAGE =0x0A,
//Class PS /* Class PS */
H2C_PS_PWR_MODE =0x20, H2C_PS_PWR_MODE =0x20,
H2C_PS_TUNE_PARA =0x21, H2C_PS_TUNE_PARA =0x21,
H2C_PS_TUNE_PARA_2 =0x22, H2C_PS_TUNE_PARA_2 =0x22,
H2C_PS_LPS_PARA =0x23, H2C_PS_LPS_PARA =0x23,
H2C_PS_P2P_OFFLOAD =0x24, H2C_PS_P2P_OFFLOAD =0x24,
//Class DM /* Class DM */
H2C_DM_MACID_CFG =0x40, H2C_DM_MACID_CFG =0x40,
H2C_DM_TXBF =0x41, H2C_DM_TXBF =0x41,
//Class BT /* Class BT */
H2C_BT_COEX_MASK =0x60, H2C_BT_COEX_MASK =0x60,
H2C_BT_COEX_GPIO_MODE =0x61, H2C_BT_COEX_GPIO_MODE =0x61,
H2C_BT_DAC_SWING_VAL =0x62, H2C_BT_DAC_SWING_VAL =0x62,
H2C_BT_PSD_RST =0x63, H2C_BT_PSD_RST =0x63,
//Class /* Class */
H2C_RESET_TSF =0xc0, H2C_RESET_TSF =0xc0,
}RTL8188E_H2C_CMD_ID; }RTL8188E_H2C_CMD_ID;
struct cmd_msg_parm { struct cmd_msg_parm {
u8 eid; //element id u8 eid; /* element id */
u8 sz; // sz u8 sz; /* sz */
u8 buf[6]; u8 buf[6];
}; };
@ -66,21 +66,20 @@ enum{
}; };
typedef struct _SETPWRMODE_PARM { typedef struct _SETPWRMODE_PARM {
u8 Mode;//0:Active,1:LPS,2:WMMPS u8 Mode;/* 0:Active,1:LPS,2:WMMPS */
//u8 RLBM:4;//0:Min,1:Max,2: User define u8 SmartPS_RLBM;/* LPS=0:PS_Poll,1:PS_Poll,2:NullData,WMM=0:PS_Poll,1:NullData */
u8 SmartPS_RLBM;//LPS=0:PS_Poll,1:PS_Poll,2:NullData,WMM=0:PS_Poll,1:NullData u8 AwakeInterval; /* unit: beacon interval */
u8 AwakeInterval; // unit: beacon interval
u8 bAllQueueUAPSD; u8 bAllQueueUAPSD;
u8 PwrState;//AllON(0x0c),RFON(0x04),RFOFF(0x00) u8 PwrState;/* AllON(0x0c),RFON(0x04),RFOFF(0x00) */
} SETPWRMODE_PARM, *PSETPWRMODE_PARM; } SETPWRMODE_PARM, *PSETPWRMODE_PARM;
struct H2C_SS_RFOFF_PARAM{ struct H2C_SS_RFOFF_PARAM{
u8 ROFOn; // 1: on, 0:off u8 ROFOn; /* 1: on, 0:off */
u16 gpio_period; // unit: 1024 us u16 gpio_period; /* unit: 1024 us */
}__attribute__ ((packed)); }__attribute__ ((packed));
typedef struct JOINBSSRPT_PARM{ typedef struct JOINBSSRPT_PARM{
u8 OpMode; // RT_MEDIA_STATUS u8 OpMode; /* RT_MEDIA_STATUS */
}JOINBSSRPT_PARM, *PJOINBSSRPT_PARM; }JOINBSSRPT_PARM, *PJOINBSSRPT_PARM;
typedef struct _RSVDPAGE_LOC { typedef struct _RSVDPAGE_LOC {
@ -93,55 +92,55 @@ typedef struct _RSVDPAGE_LOC {
struct P2P_PS_Offload_t { struct P2P_PS_Offload_t {
u8 Offload_En:1; u8 Offload_En:1;
u8 role:1; // 1: Owner, 0: Client u8 role:1; /* 1: Owner, 0: Client */
u8 CTWindow_En:1; u8 CTWindow_En:1;
u8 NoA0_En:1; u8 NoA0_En:1;
u8 NoA1_En:1; u8 NoA1_En:1;
u8 AllStaSleep:1; // Only valid in Owner u8 AllStaSleep:1; /* Only valid in Owner */
u8 discovery:1; u8 discovery:1;
u8 rsvd:1; u8 rsvd:1;
}; };
struct P2P_PS_CTWPeriod_t { struct P2P_PS_CTWPeriod_t {
u8 CTWPeriod; //TU u8 CTWPeriod; /* TU */
}; };
// host message to firmware cmd /* host message to firmware cmd */
void rtl8188e_set_FwPwrMode_cmd(struct adapter *padapter, u8 Mode); void rtl8188e_set_FwPwrMode_cmd(struct adapter *padapter, u8 Mode);
void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus); void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *padapter, u8 mstatus);
u8 rtl8188e_set_rssi_cmd(struct adapter *padapter, u8 *param); u8 rtl8188e_set_rssi_cmd(struct adapter *padapter, u8 *param);
u8 rtl8188e_set_raid_cmd(struct adapter *padapter, u32 mask); u8 rtl8188e_set_raid_cmd(struct adapter *padapter, u32 mask);
void rtl8188e_Add_RateATid(struct adapter *padapter, u32 bitmap, u8 arg, u8 rssi_level); void rtl8188e_Add_RateATid(struct adapter *padapter, u32 bitmap, u8 arg, u8 rssi_level);
//u8 rtl8192c_set_FwSelectSuspend_cmd(struct adapter *padapter, u8 bfwpoll, u16 period); /* u8 rtl8192c_set_FwSelectSuspend_cmd(struct adapter *padapter, u8 bfwpoll, u16 period); */
#ifdef CONFIG_P2P #ifdef CONFIG_P2P
void rtl8188e_set_p2p_ps_offload_cmd(struct adapter *padapter, u8 p2p_ps_state); void rtl8188e_set_p2p_ps_offload_cmd(struct adapter *padapter, u8 p2p_ps_state);
#endif //CONFIG_P2P #endif /* CONFIG_P2P */
void CheckFwRsvdPageContent(struct adapter *padapter); void CheckFwRsvdPageContent(struct adapter *padapter);
void rtl8188e_set_FwMediaStatus_cmd(struct adapter *padapter, __le16 mstatus_rpt ); void rtl8188e_set_FwMediaStatus_cmd(struct adapter *padapter, __le16 mstatus_rpt );
#ifdef CONFIG_TSF_RESET_OFFLOAD #ifdef CONFIG_TSF_RESET_OFFLOAD
//u8 rtl8188e_reset_tsf(struct adapter *padapter, u8 reset_port); /* u8 rtl8188e_reset_tsf(struct adapter *padapter, u8 reset_port); */
int reset_tsf(struct adapter *Adapter, u8 reset_port ); int reset_tsf(struct adapter *Adapter, u8 reset_port );
#endif // CONFIG_TSF_RESET_OFFLOAD #endif /* CONFIG_TSF_RESET_OFFLOAD */
#define H2C_8188E_RSVDPAGE_LOC_LEN 5 #define H2C_8188E_RSVDPAGE_LOC_LEN 5
#define H2C_8188E_AOAC_RSVDPAGE_LOC_LEN 7 #define H2C_8188E_AOAC_RSVDPAGE_LOC_LEN 7
//---------------------------------------------------------------------------------------------------------// /* */
//---------------------------------- H2C CMD CONTENT --------------------------------------------------// /* H2C CMD CONTENT -------------------------------------------------- */
//---------------------------------------------------------------------------------------------------------// /* */
//_RSVDPAGE_LOC_CMD_0x00 /* _RSVDPAGE_LOC_CMD_0x00 */
#define SET_8188E_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) #define SET_8188E_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8188E_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) #define SET_8188E_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#define SET_8188E_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) #define SET_8188E_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8188E_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) #define SET_8188E_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
// AOAC_RSVDPAGE_LOC_0x83 /* AOAC_RSVDPAGE_LOC_0x83 */
#define SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value) #define SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)
#define SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) #define SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#endif//__RTL8188E_CMD_H__ #endif/* __RTL8188E_CMD_H__ */

16
include/rtl8188e_dm.h
View file

@ -19,16 +19,16 @@
******************************************************************************/ ******************************************************************************/
#ifndef __RTL8188E_DM_H__ #ifndef __RTL8188E_DM_H__
#define __RTL8188E_DM_H__ #define __RTL8188E_DM_H__
enum{ enum {
UP_LINK, UP_LINK,
DOWN_LINK, DOWN_LINK,
}; };
//###### duplicate code,will move to ODM ######### /* duplicate code,will move to ODM ######### */
#define IQK_MAC_REG_NUM 4 #define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16 #define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM 9 #define IQK_BB_REG_NUM 9
#define HP_THERMAL_NUM 8 #define HP_THERMAL_NUM 8
//###### duplicate code,will move to ODM ######### /* duplicate code,will move to ODM ######### */
struct dm_priv struct dm_priv
{ {
u8 DM_Type; u8 DM_Type;
@ -36,7 +36,7 @@ struct dm_priv
u8 InitDMFlag; u8 InitDMFlag;
u32 InitODMFlag; u32 InitODMFlag;
//* Upper and Lower Signal threshold for Rate Adaptive*/ /* Upper and Lower Signal threshold for Rate Adaptive*/
int UndecoratedSmoothedPWDB; int UndecoratedSmoothedPWDB;
int UndecoratedSmoothedCCK; int UndecoratedSmoothedCCK;
int EntryMinUndecoratedSmoothedPWDB; int EntryMinUndecoratedSmoothedPWDB;
@ -44,13 +44,13 @@ struct dm_priv
int MinUndecoratedPWDBForDM; int MinUndecoratedPWDBForDM;
int LastMinUndecoratedPWDBForDM; int LastMinUndecoratedPWDBForDM;
//###### duplicate code,will move to ODM ######### /* duplicate code,will move to ODM ######### */
//for High Power /* for High Power */
u8 bDynamicTxPowerEnable; u8 bDynamicTxPowerEnable;
u8 LastDTPLvl; u8 LastDTPLvl;
u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06 u8 DynamicTxHighPowerLvl;/* Add by Jacken Tx Power Control for Near/Far Range 2008/03/06 */
u8 PowerIndex_backup[6]; u8 PowerIndex_backup[6];
u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */
}; };

230
include/rtl8188e_hal.h
View file

@ -21,7 +21,7 @@
#define __RTL8188E_HAL_H__ #define __RTL8188E_HAL_H__
//include HAL Related header after HAL Related compiling flags /* include HAL Related header after HAL Related compiling flags */
#include "rtl8188e_spec.h" #include "rtl8188e_spec.h"
#include "Hal8188EPhyReg.h" #include "Hal8188EPhyReg.h"
#include "Hal8188EPhyCfg.h" #include "Hal8188EPhyCfg.h"
@ -36,7 +36,7 @@
#include "../hal/odm_precomp.h" #include "../hal/odm_precomp.h"
// Fw Array /* Fw Array */
#define Rtl8188E_FwImageArray Rtl8188EFwImgArray #define Rtl8188E_FwImageArray Rtl8188EFwImgArray
#define Rtl8188E_FWImgArrayLength Rtl8188EFWImgArrayLength #define Rtl8188E_FWImgArrayLength Rtl8188EFWImgArrayLength
#define RTL8188E_FW_UMC_IMG "rtl8188E\\rtl8188efw.bin" #define RTL8188E_FW_UMC_IMG "rtl8188E\\rtl8188efw.bin"
@ -48,9 +48,9 @@
#define RTL8188E_PHY_REG_PG "rtl8188E\\PHY_REG_PG.txt" #define RTL8188E_PHY_REG_PG "rtl8188E\\PHY_REG_PG.txt"
#define RTL8188E_PHY_REG_MP "rtl8188E\\PHY_REG_MP.txt" #define RTL8188E_PHY_REG_MP "rtl8188E\\PHY_REG_MP.txt"
//--------------------------------------------------------------------- /* */
// RTL8188E Power Configuration CMDs for USB/SDIO interfaces /* RTL8188E Power Configuration CMDs for USB/SDIO interfaces */
//--------------------------------------------------------------------- /* */
#define Rtl8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow #define Rtl8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow
#define Rtl8188E_NIC_RF_OFF_FLOW rtl8188E_radio_off_flow #define Rtl8188E_NIC_RF_OFF_FLOW rtl8188E_radio_off_flow
#define Rtl8188E_NIC_DISABLE_FLOW rtl8188E_card_disable_flow #define Rtl8188E_NIC_DISABLE_FLOW rtl8188E_card_disable_flow
@ -61,21 +61,21 @@
#define Rtl8188E_NIC_LPS_ENTER_FLOW rtl8188E_enter_lps_flow #define Rtl8188E_NIC_LPS_ENTER_FLOW rtl8188E_enter_lps_flow
#define Rtl8188E_NIC_LPS_LEAVE_FLOW rtl8188E_leave_lps_flow #define Rtl8188E_NIC_LPS_LEAVE_FLOW rtl8188E_leave_lps_flow
#define DRVINFO_SZ 4 // unit is 8bytes #define DRVINFO_SZ 4 /* unit is 8bytes */
#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0)) #define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
#define FW_8188E_SIZE 0x4000 //16384,16k #define FW_8188E_SIZE 0x4000 /* 16384,16k */
#define FW_8188E_START_ADDRESS 0x1000 #define FW_8188E_START_ADDRESS 0x1000
#define FW_8188E_END_ADDRESS 0x1FFF //0x5FFF #define FW_8188E_END_ADDRESS 0x1FFF /* 0x5FFF */
#define MAX_PAGE_SIZE 4096 // @ page : 4k bytes #define MAX_PAGE_SIZE 4096 /* @ page : 4k bytes */
#define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\ #define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\ (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300 ||\ (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300 ||\
(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88E0) (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88E0)
// This structure must be careful with byte-ordering /* This structure must be careful with byte-ordering */
struct rt_firmware_hdr { struct rt_firmware_hdr {
/* 8-byte alinment required */ /* 8-byte alinment required */
@ -122,41 +122,41 @@ typedef enum _USB_RX_AGG_MODE{
}USB_RX_AGG_MODE; }USB_RX_AGG_MODE;
#define MAX_RX_DMA_BUFFER_SIZE_88E 0x2400 //9k for 88E nornal chip , //MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) #define MAX_RX_DMA_BUFFER_SIZE_88E 0x2400 /* 9k for 88E nornal chip , MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) */
#define MAX_TX_REPORT_BUFFER_SIZE 0x0400 // 1k #define MAX_TX_REPORT_BUFFER_SIZE 0x0400 /* 1k */
// BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. /* BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */
#define MAX_TX_QUEUE 9 #define MAX_TX_QUEUE 9
#define TX_SELE_HQ BIT(0) // High Queue #define TX_SELE_HQ BIT(0) /* High Queue */
#define TX_SELE_LQ BIT(1) // Low Queue #define TX_SELE_LQ BIT(1) /* Low Queue */
#define TX_SELE_NQ BIT(2) // Normal Queue #define TX_SELE_NQ BIT(2) /* Normal Queue */
// Note: We will divide number of page equally for each queue other than public queue! /* Note: We will divide number of page equally for each queue other than public queue! */
// 22k = 22528 bytes = 176 pages (@page = 128 bytes) /* 22k = 22528 bytes = 176 pages (@page = 128 bytes) */
// must reserved about 7 pages for LPS => 176-7 = 169 (0xA9) /* must reserved about 7 pages for LPS => 176-7 = 169 (0xA9) */
// 2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS null-data /* 2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS null-data */
#define TX_TOTAL_PAGE_NUMBER_88E 0xA9// 169 (21632=> 21k) #define TX_TOTAL_PAGE_NUMBER_88E 0xA9/* 169 (21632=> 21k) */
#ifdef RTL8188ES_MAC_LOOPBACK #ifdef RTL8188ES_MAC_LOOPBACK
#define TX_PAGE_BOUNDARY_88E 0x48 //72 #define TX_PAGE_BOUNDARY_88E 0x48 /* 72 */
#else //TX_PAGE_BOUNDARY_LOOPBACK_MODE #else /* TX_PAGE_BOUNDARY_LOOPBACK_MODE */
#define TX_PAGE_BOUNDARY_88E (TX_TOTAL_PAGE_NUMBER_88E + 1) #define TX_PAGE_BOUNDARY_88E (TX_TOTAL_PAGE_NUMBER_88E + 1)
#endif #endif
//Note: For Normal Chip Setting ,modify later /* Note: For Normal Chip Setting ,modify later */
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER TX_TOTAL_PAGE_NUMBER_88E //0xA9 , 0xb0=>176=>22k #define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER TX_TOTAL_PAGE_NUMBER_88E /* 0xA9 , 0xb0=>176=>22k */
#define WMM_NORMAL_TX_PAGE_BOUNDARY_88E (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1) //0xA9 #define WMM_NORMAL_TX_PAGE_BOUNDARY_88E (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1) /* 0xA9 */
//------------------------------------------------------------------------- /* */
// Chip specific /* Chip specific */
//------------------------------------------------------------------------- /* */
#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3) #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
#define CHIP_BONDING_92C_1T2R 0x1 #define CHIP_BONDING_92C_1T2R 0x1
#define CHIP_BONDING_88C_USB_MCARD 0x2 #define CHIP_BONDING_88C_USB_MCARD 0x2
@ -164,9 +164,9 @@ typedef enum _USB_RX_AGG_MODE{
#include "HalVerDef.h" #include "HalVerDef.h"
#include "hal_com.h" #include "hal_com.h"
//------------------------------------------------------------------------- /* */
// Channel Plan /* Channel Plan */
//------------------------------------------------------------------------- /* */
enum ChannelPlan enum ChannelPlan
{ {
CHPL_FCC = 0, CHPL_FCC = 0,
@ -193,14 +193,14 @@ typedef struct _TxPowerInfo
u8 HT20MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX_88E]; u8 HT20MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX_88E];
u8 TSSI_A[3]; u8 TSSI_A[3];
u8 TSSI_B[3]; u8 TSSI_B[3];
u8 TSSI_A_5G[3]; //5GL/5GM/5GH u8 TSSI_A_5G[3]; /* 5GL/5GM/5GH */
u8 TSSI_B_5G[3]; u8 TSSI_B_5G[3];
} TxPowerInfo, *PTxPowerInfo; } TxPowerInfo, *PTxPowerInfo;
typedef struct _TxPowerInfo24G{ typedef struct _TxPowerInfo24G{
u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G-1]; u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G-1];
//If only one tx, only BW20 and OFDM are used. /* If only one tx, only BW20 and OFDM are used. */
s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT]; s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT]; s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT]; s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
@ -210,18 +210,18 @@ typedef struct _TxPowerInfo24G{
#define EFUSE_REAL_CONTENT_LEN 512 #define EFUSE_REAL_CONTENT_LEN 512
#define EFUSE_MAP_LEN 128 #define EFUSE_MAP_LEN 128
#define EFUSE_MAX_SECTION 16 #define EFUSE_MAX_SECTION 16
#define EFUSE_IC_ID_OFFSET 506 //For some inferiority IC purpose. added by Roger, 2009.09.02. #define EFUSE_IC_ID_OFFSET 506 /* For some inferiority IC purpose. added by Roger, 2009.09.02. */
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN) #define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN)
// /* */
// <Roger_Notes> /* <Roger_Notes> */
// To prevent out of boundary programming case, /* To prevent out of boundary programming case, */
// leave 1byte and program full section /* leave 1byte and program full section */
// 9bytes + 1byt + 5bytes and pre 1byte. /* 9bytes + 1byt + 5bytes and pre 1byte. */
// For worst case: /* For worst case: */
// | 1byte|----8bytes----|1byte|--5bytes--| /* | 1byte|----8bytes----|1byte|--5bytes--| */
// | | Reserved(14bytes) | /* | | Reserved(14bytes) | */
// /* */
#define EFUSE_OOB_PROTECT_BYTES 15 // PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. #define EFUSE_OOB_PROTECT_BYTES 15 /* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */
#define HWSET_MAX_SIZE_88E 512 #define HWSET_MAX_SIZE_88E 512
@ -229,28 +229,28 @@ typedef struct _TxPowerInfo24G{
#define EFUSE_MAP_LEN_88E 512 #define EFUSE_MAP_LEN_88E 512
#define EFUSE_MAX_SECTION_88E 64 #define EFUSE_MAX_SECTION_88E 64
#define EFUSE_MAX_WORD_UNIT_88E 4 #define EFUSE_MAX_WORD_UNIT_88E 4
#define EFUSE_IC_ID_OFFSET_88E 506 //For some inferiority IC purpose. added by Roger, 2009.09.02. #define EFUSE_IC_ID_OFFSET_88E 506 /* For some inferiority IC purpose. added by Roger, 2009.09.02. */
#define AVAILABLE_EFUSE_ADDR_88E(addr) (addr < EFUSE_REAL_CONTENT_LEN_88E) #define AVAILABLE_EFUSE_ADDR_88E(addr) (addr < EFUSE_REAL_CONTENT_LEN_88E)
// <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section /* <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section */
// 9bytes + 1byt + 5bytes and pre 1byte. /* 9bytes + 1byt + 5bytes and pre 1byte. */
// For worst case: /* For worst case: */
// | 2byte|----8bytes----|1byte|--7bytes--| //92D /* | 2byte|----8bytes----|1byte|--7bytes--| 92D */
#define EFUSE_OOB_PROTECT_BYTES_88E 18 // PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. #define EFUSE_OOB_PROTECT_BYTES_88E 18 /* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */
#define EFUSE_PROTECT_BYTES_BANK_88E 16 #define EFUSE_PROTECT_BYTES_BANK_88E 16
//======================================================== /* */
// EFUSE for BT definition /* EFUSE for BT definition */
//======================================================== /* */
#define EFUSE_BT_REAL_CONTENT_LEN 1536 // 512*3 #define EFUSE_BT_REAL_CONTENT_LEN 1536 /* 512*3 */
#define EFUSE_BT_MAP_LEN 1024 // 1k bytes #define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */
#define EFUSE_BT_MAX_SECTION 128 // 1024/8 #define EFUSE_BT_MAX_SECTION 128 /* 1024/8 */
#define EFUSE_PROTECT_BYTES_BANK 16 #define EFUSE_PROTECT_BYTES_BANK 16
// /* */
// <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. /* <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. */
// /* */
typedef enum _RT_MULTI_FUNC { typedef enum _RT_MULTI_FUNC {
RT_MULTI_FUNC_NONE = 0x00, RT_MULTI_FUNC_NONE = 0x00,
RT_MULTI_FUNC_WIFI = 0x01, RT_MULTI_FUNC_WIFI = 0x01,
@ -258,15 +258,15 @@ typedef enum _RT_MULTI_FUNC {
RT_MULTI_FUNC_GPS = 0x04, RT_MULTI_FUNC_GPS = 0x04,
} RT_MULTI_FUNC, *PRT_MULTI_FUNC; } RT_MULTI_FUNC, *PRT_MULTI_FUNC;
// /* */
// <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. /* <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. */
// /* */
typedef enum _RT_POLARITY_CTL { typedef enum _RT_POLARITY_CTL {
RT_POLARITY_LOW_ACT = 0, RT_POLARITY_LOW_ACT = 0,
RT_POLARITY_HIGH_ACT = 1, RT_POLARITY_HIGH_ACT = 1,
} RT_POLARITY_CTL, *PRT_POLARITY_CTL; } RT_POLARITY_CTL, *PRT_POLARITY_CTL;
// For RTL8723 regulator mode. by tynli. 2011.01.14. /* For RTL8723 regulator mode. by tynli. 2011.01.14. */
typedef enum _RT_REGULATOR_MODE { typedef enum _RT_REGULATOR_MODE {
RT_SWITCHING_REGULATOR = 0, RT_SWITCHING_REGULATOR = 0,
RT_LDO_REGULATOR = 1, RT_LDO_REGULATOR = 1,
@ -276,9 +276,9 @@ typedef enum _RT_REGULATOR_MODE {
typedef struct hal_data_8188e typedef struct hal_data_8188e
{ {
HAL_VERSION VersionID; HAL_VERSION VersionID;
RT_MULTI_FUNC MultiFunc; // For multi-function consideration. RT_MULTI_FUNC MultiFunc; /* For multi-function consideration. */
RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control. RT_POLARITY_CTL PolarityCtl; /* For Wifi PDn Polarity control. */
RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO RT_REGULATOR_MODE RegulatorMode; /* switching regulator or LDO */
u16 CustomerID; u16 CustomerID;
u16 FirmwareVersion; u16 FirmwareVersion;
@ -286,25 +286,25 @@ typedef struct hal_data_8188e
u16 FirmwareSubVersion; u16 FirmwareSubVersion;
u16 FirmwareSignature; u16 FirmwareSignature;
u8 PGMaxGroup; u8 PGMaxGroup;
//current WIFI_PHY values /* current WIFI_PHY values */
u32 ReceiveConfig; u32 ReceiveConfig;
WIRELESS_MODE CurrentWirelessMode; WIRELESS_MODE CurrentWirelessMode;
enum HT_CHANNEL_WIDTH CurrentChannelBW; enum HT_CHANNEL_WIDTH CurrentChannelBW;
u8 CurrentChannel; u8 CurrentChannel;
u8 nCur40MhzPrimeSC;// Control channel sub-carrier u8 nCur40MhzPrimeSC;/* Control channel sub-carrier */
u16 BasicRateSet; u16 BasicRateSet;
//rf_ctrl /* rf_ctrl */
u8 rf_chip; u8 rf_chip;
u8 rf_type; u8 rf_type;
u8 NumTotalRFPath; u8 NumTotalRFPath;
u8 BoardType; u8 BoardType;
// /* */
// EEPROM setting. /* EEPROM setting. */
// /* */
u16 EEPROMVID; u16 EEPROMVID;
u16 EEPROMPID; u16 EEPROMPID;
u16 EEPROMSVID; u16 EEPROMSVID;
@ -319,39 +319,39 @@ typedef struct hal_data_8188e
u8 bAPKThermalMeterIgnore; u8 bAPKThermalMeterIgnore;
bool EepromOrEfuse; bool EepromOrEfuse;
u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes) u8 EfuseMap[2][HWSET_MAX_SIZE_512]; /* 92C:256bytes, 88E:512bytes, we use union set (512bytes) */
u8 EfuseUsedPercentage; u8 EfuseUsedPercentage;
EFUSE_HAL EfuseHal; EFUSE_HAL EfuseHal;
//u8 bIQKInitialized; /* u8 bIQKInitialized; */
u8 Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; u8 Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
u8 Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; u8 Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
//If only one tx, only BW20 and OFDM are used. /* If only one tx, only BW20 and OFDM are used. */
s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; /* For HT 40MHZ pwr */
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; /* For HT 40MHZ pwr */
u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];/* HT 20<->40 Pwr diff */
u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];/* For HT<->legacy pwr diff */
// For power group /* For power group */
u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff u8 LegacyHTTxPowerDiff;/* Legacy to HT rate power diff */
// The current Tx Power Level /* The current Tx Power Level */
u8 CurrentCckTxPwrIdx; u8 CurrentCckTxPwrIdx;
u8 CurrentOfdm24GTxPwrIdx; u8 CurrentOfdm24GTxPwrIdx;
u8 CurrentBW2024GTxPwrIdx; u8 CurrentBW2024GTxPwrIdx;
u8 CurrentBW4024GTxPwrIdx; u8 CurrentBW4024GTxPwrIdx;
// Read/write are allow for following hardware information variables /* Read/write are allow for following hardware information variables */
u8 framesync; u8 framesync;
u32 framesyncC34; u32 framesyncC34;
u8 framesyncMonitor; u8 framesyncMonitor;
@ -361,34 +361,34 @@ typedef struct hal_data_8188e
u32 CCKTxPowerLevelOriginalOffset; u32 CCKTxPowerLevelOriginalOffset;
u8 CrystalCap; u8 CrystalCap;
u32 AntennaTxPath; // Antenna path Tx u32 AntennaTxPath; /* Antenna path Tx */
u32 AntennaRxPath; // Antenna path Rx u32 AntennaRxPath; /* Antenna path Rx */
u8 BluetoothCoexist; u8 BluetoothCoexist;
u8 ExternalPA; u8 ExternalPA;
u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */
//u32 LedControlNum; /* u32 LedControlNum; */
//u32 LedControlMode; /* u32 LedControlMode; */
//u32 TxPowerTrackControl; /* u32 TxPowerTrackControl; */
u8 b1x1RecvCombine; // for 1T1R receive combining u8 b1x1RecvCombine; /* for 1T1R receive combining */
//u8 bCurrentTurboEDCA; /* u8 bCurrentTurboEDCA; */
u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo. u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D BB_REGISTER_DEFINITION_T PHYRegDef[4]; /* Radio A/B/C/D */
u32 RfRegChnlVal[2]; u32 RfRegChnlVal[2];
//RDG enable /* RDG enable */
bool bRDGEnable; bool bRDGEnable;
//for host message to fw /* for host message to fw */
u8 LastHMEBoxNum; u8 LastHMEBoxNum;
u8 fw_ractrl; u8 fw_ractrl;
u8 RegTxPause; u8 RegTxPause;
// Beacon function related global variable. /* Beacon function related global variable. */
u32 RegBcnCtrlVal; u32 RegBcnCtrlVal;
u8 RegFwHwTxQCtrl; u8 RegFwHwTxQCtrl;
u8 RegReg542; u8 RegReg542;
@ -407,24 +407,24 @@ typedef struct hal_data_8188e
u8 TRxAntDivType; u8 TRxAntDivType;
u8 bDumpRxPkt;//for debug u8 bDumpRxPkt;/* for debug */
u8 bDumpTxPkt;//for debug u8 bDumpTxPkt;/* for debug */
u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. u8 FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. */
// 2010/08/09 MH Add CU power down mode. /* 2010/08/09 MH Add CU power down mode. */
bool pwrdown; bool pwrdown;
// Add for dual MAC 0--Mac0 1--Mac1 /* Add for dual MAC 0--Mac0 1--Mac1 */
u32 interfaceIndex; u32 interfaceIndex;
u8 OutEpQueueSel; u8 OutEpQueueSel;
u8 OutEpNumber; u8 OutEpNumber;
// 2010/12/10 MH Add for USB aggreation mode dynamic shceme. /* 2010/12/10 MH Add for USB aggreation mode dynamic shceme. */
bool UsbRxHighSpeedMode; bool UsbRxHighSpeedMode;
// 2010/11/22 MH Add for slim combo debug mode selective. /* 2010/11/22 MH Add for slim combo debug mode selective. */
// This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock. /* This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock. */
bool SlimComboDbg; bool SlimComboDbg;
u16 EfuseUsedBytes; u16 EfuseUsedBytes;
@ -433,24 +433,24 @@ typedef struct hal_data_8188e
struct P2P_PS_Offload_t p2p_ps_offload; struct P2P_PS_Offload_t p2p_ps_offload;
#endif #endif
// Auto FSM to Turn On, include clock, isolation, power control for MAC only /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
u8 bMacPwrCtrlOn; u8 bMacPwrCtrlOn;
u32 UsbBulkOutSize; u32 UsbBulkOutSize;
// Interrupt relatd register information. /* Interrupt relatd register information. */
u32 IntArray[3];//HISR0,HISR1,HSISR u32 IntArray[3];/* HISR0,HISR1,HSISR */
u32 IntrMask[3]; u32 IntrMask[3];
u8 C2hArray[16]; u8 C2hArray[16];
u8 UsbTxAggMode; u8 UsbTxAggMode;
u8 UsbTxAggDescNum; u8 UsbTxAggDescNum;
u16 HwRxPageSize; // Hardware setting u16 HwRxPageSize; /* Hardware setting */
u32 MaxUsbRxAggBlock; u32 MaxUsbRxAggBlock;
USB_RX_AGG_MODE UsbRxAggMode; USB_RX_AGG_MODE UsbRxAggMode;
u8 UsbRxAggBlockCount; // USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed u8 UsbRxAggBlockCount; /* USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed */
u8 UsbRxAggBlockTimeout; u8 UsbRxAggBlockTimeout;
u8 UsbRxAggPageCount; // 8192C DMA page count u8 UsbRxAggPageCount; /* 8192C DMA page count */
u8 UsbRxAggPageTimeout; u8 UsbRxAggPageTimeout;
} HAL_DATA_8188E, *PHAL_DATA_8188E; } HAL_DATA_8188E, *PHAL_DATA_8188E;
@ -463,7 +463,7 @@ typedef struct hal_data_8188e HAL_DATA_TYPE, *PHAL_DATA_TYPE;
#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT) #define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) #define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
// rtl8188e_hal_init.c /* rtl8188e_hal_init.c */
s32 rtl8188e_FirmwareDownload(struct adapter *padapter); s32 rtl8188e_FirmwareDownload(struct adapter *padapter);
void _8051Reset88E(struct adapter *padapter); void _8051Reset88E(struct adapter *padapter);
void rtl8188e_InitializeFirmwareVars(struct adapter *padapter); void rtl8188e_InitializeFirmwareVars(struct adapter *padapter);
@ -472,7 +472,7 @@ void rtl8188e_InitializeFirmwareVars(struct adapter *padapter);
s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy); s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy);
void Read_LLT_Tab(struct adapter *padapter); void Read_LLT_Tab(struct adapter *padapter);
// EFuse /* EFuse */
u8 GetEEPROMSize8188E(struct adapter *padapter); u8 GetEEPROMSize8188E(struct adapter *padapter);
void Hal_InitPGData88E(struct adapter *padapter); void Hal_InitPGData88E(struct adapter *padapter);
void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo); void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo);
@ -493,7 +493,7 @@ void Hal_InitChannelPlan(struct adapter *padapter);
void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc); void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc);
// register /* register */
void SetBcnCtrlReg(struct adapter *padapter, u8 SetBits, u8 ClearBits); void SetBcnCtrlReg(struct adapter *padapter, u8 SetBits, u8 ClearBits);
void rtl8188e_start_thread(struct adapter *padapter); void rtl8188e_start_thread(struct adapter *padapter);
@ -501,4 +501,4 @@ void rtl8188e_stop_thread(struct adapter *padapter);
void rtw_IOL_cmd_tx_pkt_buf_dump(struct adapter *Adapter,int data_len); void rtw_IOL_cmd_tx_pkt_buf_dump(struct adapter *Adapter,int data_len);
s32 rtl8188e_iol_efuse_patch(struct adapter *padapter); s32 rtl8188e_iol_efuse_patch(struct adapter *padapter);
#endif //__RTL8188E_HAL_H__ #endif /* __RTL8188E_HAL_H__ */

6
include/rtl8188e_led.h
View file

@ -25,9 +25,9 @@
#include <drv_types.h> #include <drv_types.h>
//================================================================================ /* */
// Interface to manipulate LED objects. /* Interface to manipulate LED objects. */
//================================================================================ /* */
void rtl8188eu_InitSwLeds(struct adapter *padapter); void rtl8188eu_InitSwLeds(struct adapter *padapter);
void rtl8188eu_DeInitSwLeds(struct adapter *padapter); void rtl8188eu_DeInitSwLeds(struct adapter *padapter);

22
include/rtl8188e_recv.h
View file

@ -25,15 +25,15 @@
#define TX_RPT1_PKT_LEN 8 #define TX_RPT1_PKT_LEN 8
typedef enum _RX_PACKET_TYPE{ typedef enum _RX_PACKET_TYPE{
NORMAL_RX,//Normal rx packet NORMAL_RX,/* Normal rx packet */
TX_REPORT1,//CCX TX_REPORT1,/* CCX */
TX_REPORT2,//TX RPT TX_REPORT2,/* TX RPT */
HIS_REPORT,// USB HISR RPT HIS_REPORT,/* USB HISR RPT */
}RX_PACKET_TYPE, *PRX_PACKET_TYPE; }RX_PACKET_TYPE, *PRX_PACKET_TYPE;
typedef struct rxreport_8188e typedef struct rxreport_8188e
{ {
//Offset 0 /* Offset 0 */
u32 pktlen:14; u32 pktlen:14;
u32 crc32:1; u32 crc32:1;
u32 icverr:1; u32 icverr:1;
@ -48,7 +48,7 @@ typedef struct rxreport_8188e
u32 eor:1; u32 eor:1;
u32 own:1; u32 own:1;
//Offset 4 /* Offset 4 */
u32 macid:5; u32 macid:5;
u32 tid:4; u32 tid:4;
u32 hwrsvd:4; u32 hwrsvd:4;
@ -65,14 +65,14 @@ typedef struct rxreport_8188e
u32 mc:1; u32 mc:1;
u32 bc:1; u32 bc:1;
//Offset 8 /* Offset 8 */
u32 seq:12; u32 seq:12;
u32 frag:4; u32 frag:4;
u32 nextpktlen:14; u32 nextpktlen:14;
u32 nextind:1; u32 nextind:1;
u32 rsvd0831:1; u32 rsvd0831:1;
//Offset 12 /* Offset 12 */
u32 rxmcs:6; u32 rxmcs:6;
u32 rxht:1; u32 rxht:1;
u32 gf:1; u32 gf:1;
@ -87,7 +87,7 @@ typedef struct rxreport_8188e
u32 unicastwake:1; u32 unicastwake:1;
u32 magicwake:1; u32 magicwake:1;
//Offset 16 /* Offset 16 */
/* /*
u32 pattern0match:1; u32 pattern0match:1;
u32 pattern1match:1; u32 pattern1match:1;
@ -106,10 +106,10 @@ typedef struct rxreport_8188e
*/ */
u32 rsvd16; u32 rsvd16;
//Offset 20 /* Offset 20 */
u32 tsfl; u32 tsfl;
//Offset 24 /* Offset 24 */
u32 bassn:12; u32 bassn:12;
u32 bavld:1; u32 bavld:1;
u32 rsvd2413:19; u32 rsvd2413:19;

2
include/rtl8188e_rf.h
View file

@ -34,4 +34,4 @@ void rtl8188e_PHY_RF6052SetOFDMTxPower(struct adapter *Adapter, u8 *pPowerLevelO
u8 *pPowerLevelBW20, u8 *pPowerLevelBW40, u8 *pPowerLevelBW20, u8 *pPowerLevelBW40,
u8 Channel); u8 Channel);
#endif//__RTL8188E_RF_H__ #endif/* __RTL8188E_RF_H__ */

1004
include/rtl8188e_spec.h
View file

File diff suppressed because it is too large Load diff

56
include/rtl8188e_xmit.h
View file

@ -21,19 +21,19 @@
#define __RTL8188E_XMIT_H__ #define __RTL8188E_XMIT_H__
#define MAX_TX_AGG_PACKET_NUMBER 0xFF #define MAX_TX_AGG_PACKET_NUMBER 0xFF
// /* */
// Queue Select Value in TxDesc /* Queue Select Value in TxDesc */
// /* */
#define QSLT_BK 0x2//0x01 #define QSLT_BK 0x2/* 0x01 */
#define QSLT_BE 0x0 #define QSLT_BE 0x0
#define QSLT_VI 0x5//0x4 #define QSLT_VI 0x5/* 0x4 */
#define QSLT_VO 0x7//0x6 #define QSLT_VO 0x7/* 0x6 */
#define QSLT_BEACON 0x10 #define QSLT_BEACON 0x10
#define QSLT_HIGH 0x11 #define QSLT_HIGH 0x11
#define QSLT_MGNT 0x12 #define QSLT_MGNT 0x12
#define QSLT_CMD 0x13 #define QSLT_CMD 0x13
//For 88e early mode /* For 88e early mode */
#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value) #define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value) #define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value) #define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
@ -42,13 +42,13 @@
#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value) #define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value) #define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
// /* */
//defined for TX DESC Operation /* defined for TX DESC Operation */
// /* */
#define MAX_TID (15) #define MAX_TID (15)
//OFFSET 0 /* OFFSET 0 */
#define OFFSET_SZ 0 #define OFFSET_SZ 0
#define OFFSET_SHT 16 #define OFFSET_SHT 16
#define BMC BIT(24) #define BMC BIT(24)
@ -57,7 +57,7 @@
#define OWN BIT(31) #define OWN BIT(31)
//OFFSET 4 /* OFFSET 4 */
#define PKT_OFFSET_SZ 0 #define PKT_OFFSET_SZ 0
#define QSEL_SHT 8 #define QSEL_SHT 8
#define RATE_ID_SHT 16 #define RATE_ID_SHT 16
@ -65,7 +65,7 @@
#define SEC_TYPE_SHT 22 #define SEC_TYPE_SHT 22
#define PKT_OFFSET_SHT 26 #define PKT_OFFSET_SHT 26
//OFFSET 8 /* OFFSET 8 */
#define AGG_EN BIT(12) #define AGG_EN BIT(12)
#define AGG_BK BIT(16) #define AGG_BK BIT(16)
#define AMPDU_DENSITY_SHT 20 #define AMPDU_DENSITY_SHT 20
@ -75,11 +75,11 @@
#define TX_ANTL_SHT 28 #define TX_ANTL_SHT 28
#define TX_ANT_HT_SHT 30 #define TX_ANT_HT_SHT 30
//OFFSET 12 /* OFFSET 12 */
#define SEQ_SHT 16 #define SEQ_SHT 16
#define EN_HWSEQ BIT(31) #define EN_HWSEQ BIT(31)
//OFFSET 16 /* OFFSET 16 */
#define QOS BIT(6) #define QOS BIT(6)
#define HW_SSN BIT(7) #define HW_SSN BIT(7)
#define USERATE BIT(8) #define USERATE BIT(8)
@ -92,7 +92,7 @@
#define DATA_SC_SHT 20 #define DATA_SC_SHT 20
#define DATA_BW BIT(25) #define DATA_BW BIT(25)
//OFFSET 20 /* OFFSET 20 */
#define RTY_LMT_EN BIT(17) #define RTY_LMT_EN BIT(17)
enum TXDESC_SC{ enum TXDESC_SC{
@ -101,13 +101,13 @@ enum TXDESC_SC{
SC_LOWER=0x02, SC_LOWER=0x02,
SC_DUPLICATE=0x03 SC_DUPLICATE=0x03
}; };
//OFFSET 20 /* OFFSET 20 */
#define SGI BIT(6) #define SGI BIT(6)
#define USB_TXAGG_NUM_SHT 24 #define USB_TXAGG_NUM_SHT 24
typedef struct txdesc_88e typedef struct txdesc_88e
{ {
//Offset 0 /* Offset 0 */
u32 pktlen:16; u32 pktlen:16;
u32 offset:8; u32 offset:8;
u32 bmc:1; u32 bmc:1;
@ -119,7 +119,7 @@ typedef struct txdesc_88e
u32 gf:1; u32 gf:1;
u32 own:1; u32 own:1;
//Offset 4 /* Offset 4 */
u32 macid:6; u32 macid:6;
u32 rsvd0406:2; u32 rsvd0406:2;
u32 qsel:5; u32 qsel:5;
@ -131,10 +131,10 @@ typedef struct txdesc_88e
u32 en_desc_id:1; u32 en_desc_id:1;
u32 sectype:2; u32 sectype:2;
u32 rsvd0424:2; u32 rsvd0424:2;
u32 pkt_offset:5; // unit: 8 bytes u32 pkt_offset:5; /* unit: 8 bytes */
u32 rsvd0431:1; u32 rsvd0431:1;
//Offset 8 /* Offset 8 */
u32 rts_rc:6; u32 rts_rc:6;
u32 data_rc:6; u32 data_rc:6;
u32 agg_en:1; u32 agg_en:1;
@ -152,7 +152,7 @@ typedef struct txdesc_88e
u32 tx_antl:2; u32 tx_antl:2;
u32 tx_ant_ht:2; u32 tx_ant_ht:2;
//Offset 12 /* Offset 12 */
u32 nextheadpage:8; u32 nextheadpage:8;
u32 tailpage:8; u32 tailpage:8;
u32 seq:12; u32 seq:12;
@ -161,7 +161,7 @@ typedef struct txdesc_88e
u32 trigger_int:1; u32 trigger_int:1;
u32 hwseq_en:1; u32 hwseq_en:1;
//Offset 16 /* Offset 16 */
u32 rtsrate:5; u32 rtsrate:5;
u32 ap_dcfe:1; u32 ap_dcfe:1;
u32 hwseq_sel:2; u32 hwseq_sel:2;
@ -184,7 +184,7 @@ typedef struct txdesc_88e
u32 rts_sc:2; u32 rts_sc:2;
u32 vcs_stbc:2; u32 vcs_stbc:2;
//Offset 20 /* Offset 20 */
u32 datarate:6; u32 datarate:6;
u32 sgi:1; u32 sgi:1;
u32 try_rate:1; u32 try_rate:1;
@ -194,7 +194,7 @@ typedef struct txdesc_88e
u32 data_rt_lmt:6; u32 data_rt_lmt:6;
u32 usb_txagg_num:8; u32 usb_txagg_num:8;
//Offset 24 /* Offset 24 */
u32 txagg_a:5; u32 txagg_a:5;
u32 txagg_b:5; u32 txagg_b:5;
u32 use_max_len:1; u32 use_max_len:1;
@ -204,8 +204,8 @@ typedef struct txdesc_88e
u32 mcsg3_max_len:4; u32 mcsg3_max_len:4;
u32 mcs7_sgi_max_len:4; u32 mcs7_sgi_max_len:4;
//Offset 28 /* Offset 28 */
u32 checksum:16; // TxBuffSize(PCIe)/CheckSum(USB) u32 checksum:16; /* TxBuffSize(PCIe)/CheckSum(USB) */
u32 sw0:8; /* offset 30 */ u32 sw0:8; /* offset 30 */
u32 sw1:4; u32 sw1:4;
u32 mcs15_sgi_max_len:4; u32 mcs15_sgi_max_len:4;
@ -270,4 +270,4 @@ void handle_txrpt_ccx_88e(struct adapter *adapter, u8 *buf);
void _dbg_dump_tx_info(struct adapter *padapter,int frame_tag,struct tx_desc *ptxdesc); void _dbg_dump_tx_info(struct adapter *padapter,int frame_tag,struct tx_desc *ptxdesc);
#endif //__RTL8188E_XMIT_H__ #endif /* __RTL8188E_XMIT_H__ */

10
include/rtl8192c_recv.h
View file

@ -35,7 +35,7 @@
#define NR_RECVBUFF (1) #define NR_RECVBUFF (1)
#else #else
#define NR_RECVBUFF (4) #define NR_RECVBUFF (4)
#endif //CONFIG_SINGLE_RECV_BUF #endif /* CONFIG_SINGLE_RECV_BUF */
#define NR_PREALLOC_RECV_SKB (8) #define NR_PREALLOC_RECV_SKB (8)
#endif #endif
@ -45,7 +45,7 @@
#define RECV_BLK_CNT 16 #define RECV_BLK_CNT 16
#define RECV_BLK_TH RECV_BLK_CNT #define RECV_BLK_TH RECV_BLK_CNT
#define MAX_RECVBUF_SZ (15360) // 15k < 16k #define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
#define RECV_BULK_IN_ADDR 0x80 #define RECV_BULK_IN_ADDR 0x80
#define RECV_INT_IN_ADDR 0x81 #define RECV_INT_IN_ADDR 0x81
@ -73,7 +73,7 @@ struct phy_stat
unsigned int phydw7; unsigned int phydw7;
}; };
// Rx smooth factor /* Rx smooth factor */
#define Rx_Smooth_Factor (20) #define Rx_Smooth_Factor (20)
typedef struct _INTERRUPT_MSG_FORMAT_EX{ typedef struct _INTERRUPT_MSG_FORMAT_EX{
@ -81,8 +81,8 @@ typedef struct _INTERRUPT_MSG_FORMAT_EX{
unsigned int C2H_MSG1; unsigned int C2H_MSG1;
unsigned int C2H_MSG2; unsigned int C2H_MSG2;
unsigned int C2H_MSG3; unsigned int C2H_MSG3;
unsigned int HISR; // from HISR Reg0x124, read to clear unsigned int HISR; /* from HISR Reg0x124, read to clear */
unsigned int HISRE;// from HISRE Reg0x12c, read to clear unsigned int HISRE;/* from HISRE Reg0x12c, read to clear */
unsigned int MSG_EX; unsigned int MSG_EX;
}INTERRUPT_MSG_FORMAT_EX,*PINTERRUPT_MSG_FORMAT_EX; }INTERRUPT_MSG_FORMAT_EX,*PINTERRUPT_MSG_FORMAT_EX;

2
include/rtw_android.h
View file

@ -86,4 +86,4 @@ static int rtw_android_wifictrl_func_add(void) { return 0; }
static void rtw_android_wifictrl_func_del(void) {} static void rtw_android_wifictrl_func_del(void) {}
#endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */ #endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */
#endif //__RTW_ANDROID_H__ #endif /* __RTW_ANDROID_H__ */

2
include/rtw_ap.h
View file

@ -54,7 +54,7 @@ int rtw_ap_inform_ch_switch(struct adapter *padapter, u8 new_ch, u8 ch_offset);
void start_ap_mode(struct adapter *padapter); void start_ap_mode(struct adapter *padapter);
void stop_ap_mode(struct adapter *padapter); void stop_ap_mode(struct adapter *padapter);
#endif //end of CONFIG_AP_MODE #endif /* end of CONFIG_AP_MODE */
void update_bmc_sta(struct adapter *padapter); void update_bmc_sta(struct adapter *padapter);

4
include/rtw_br_ext.h
View file

@ -62,7 +62,7 @@ struct br_ext_info {
unsigned int nat25_disable; unsigned int nat25_disable;
unsigned int macclone_enable; unsigned int macclone_enable;
unsigned int dhcp_bcst_disable; unsigned int dhcp_bcst_disable;
int addPPPoETag; // 1: Add PPPoE relay-SID, 0: disable int addPPPoETag; /* 1: Add PPPoE relay-SID, 0: disable */
unsigned char nat25_dmzMac[MACADDRLEN]; unsigned char nat25_dmzMac[MACADDRLEN];
unsigned int nat25sc_disable; unsigned int nat25sc_disable;
}; };
@ -72,4 +72,4 @@ void netdev_br_init(struct net_device *netdev);
void *scdb_findEntry(struct adapter *priv, unsigned char *macAddr, void *scdb_findEntry(struct adapter *priv, unsigned char *macAddr,
unsigned char *ipAddr); unsigned char *ipAddr);
#endif // _RTW_BR_EXT_H_ #endif /* _RTW_BR_EXT_H_ */

77
include/rtw_cmd.h
View file

@ -28,7 +28,7 @@
#define C2H_MEM_SZ (16*1024) #define C2H_MEM_SZ (16*1024)
#include <osdep_service.h> #include <osdep_service.h>
#include <ieee80211.h> // <ieee80211/ieee80211.h> #include <ieee80211.h> /* <ieee80211/ieee80211.h> */
#define FREE_CMDOBJ_SZ 128 #define FREE_CMDOBJ_SZ 128
@ -55,9 +55,9 @@
struct semaphore terminate_cmdthread_sema; struct semaphore terminate_cmdthread_sema;
struct __queue cmd_queue; struct __queue cmd_queue;
u8 cmd_seq; u8 cmd_seq;
u8 *cmd_buf; //shall be non-paged, and 4 bytes aligned u8 *cmd_buf; /* shall be non-paged, and 4 bytes aligned */
u8 *cmd_allocated_buf; u8 *cmd_allocated_buf;
u8 *rsp_buf; //shall be non-paged, and 4 bytes aligned u8 *rsp_buf; /* shall be non-paged, and 4 bytes aligned */
u8 *rsp_allocated_buf; u8 *rsp_allocated_buf;
u32 cmd_issued_cnt; u32 cmd_issued_cnt;
u32 cmd_done_cnt; u32 cmd_done_cnt;
@ -83,7 +83,7 @@
u8 *cmdevt_parm; u8 *cmdevt_parm;
#endif #endif
ATOMIC_T event_seq; ATOMIC_T event_seq;
u8 *evt_buf; //shall be non-paged, and 4 bytes aligned u8 *evt_buf; /* shall be non-paged, and 4 bytes aligned */
u8 *evt_allocated_buf; u8 *evt_allocated_buf;
u32 evt_done_cnt; u32 evt_done_cnt;
}; };
@ -123,7 +123,7 @@ void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv);
void rtw_evt_notify_isr(struct evt_priv *pevtpriv); void rtw_evt_notify_isr(struct evt_priv *pevtpriv);
#ifdef CONFIG_P2P #ifdef CONFIG_P2P
u8 p2p_protocol_wk_cmd(struct adapter*padapter, int intCmdType ); u8 p2p_protocol_wk_cmd(struct adapter*padapter, int intCmdType );
#endif //CONFIG_P2P #endif /* CONFIG_P2P */
enum rtw_drvextra_cmd_id enum rtw_drvextra_cmd_id
{ {
@ -131,17 +131,17 @@ enum rtw_drvextra_cmd_id
DYNAMIC_CHK_WK_CID, DYNAMIC_CHK_WK_CID,
DM_CTRL_WK_CID, DM_CTRL_WK_CID,
PBC_POLLING_WK_CID, PBC_POLLING_WK_CID,
POWER_SAVING_CTRL_WK_CID,//IPS,AUTOSuspend POWER_SAVING_CTRL_WK_CID,/* IPS,AUTOSuspend */
LPS_CTRL_WK_CID, LPS_CTRL_WK_CID,
ANT_SELECT_WK_CID, ANT_SELECT_WK_CID,
P2P_PS_WK_CID, P2P_PS_WK_CID,
P2P_PROTO_WK_CID, P2P_PROTO_WK_CID,
CHECK_HIQ_WK_CID,//for softap mode, check hi queue if empty CHECK_HIQ_WK_CID,/* for softap mode, check hi queue if empty */
INTEl_WIDI_WK_CID, INTEl_WIDI_WK_CID,
C2H_WK_CID, C2H_WK_CID,
RTP_TIMER_CFG_WK_CID, RTP_TIMER_CFG_WK_CID,
RESET_SECURITYPRIV, // add for CONFIG_IEEE80211W, none 11w also can use RESET_SECURITYPRIV, /* add for CONFIG_IEEE80211W, none 11w also can use */
FREE_ASSOC_RESOURCES, // add for CONFIG_IEEE80211W, none 11w also can use FREE_ASSOC_RESOURCES, /* add for CONFIG_IEEE80211W, none 11w also can use */
MAX_WK_CID MAX_WK_CID
}; };
@ -170,7 +170,7 @@ Command Mode
*/ */
struct usb_suspend_parm { struct usb_suspend_parm {
u32 action;// 1: sleep, 0:resume u32 action;/* 1: sleep, 0:resume */
}; };
/* /*
@ -217,24 +217,6 @@ struct createbss_parm {
struct wlan_bssid_ex network; struct wlan_bssid_ex network;
}; };
/*
Caller Mode: AP, Ad-HoC, Infra
Notes: To set the NIC mode of RTL8711
Command Mode
The definition of mode:
#define IW_MODE_AUTO 0 // Let the driver decides which AP to join
#define IW_MODE_ADHOC 1 // Single cell network (Ad-Hoc Clients)
#define IW_MODE_INFRA 2 // Multi cell network, roaming, ..
#define IW_MODE_MASTER 3 // Synchronisation master or Access Point
#define IW_MODE_REPEAT 4 // Wireless Repeater (forwarder)
#define IW_MODE_SECOND 5 // Secondary master/repeater (backup)
#define IW_MODE_MONITOR 6 // Passive monitor (listen only)
*/
struct setopmode_parm { struct setopmode_parm {
u8 mode; u8 mode;
u8 rsvd[3]; u8 rsvd[3];
@ -249,11 +231,10 @@ Command-Event Mode
*/ */
#define RTW_SSID_SCAN_AMOUNT 9 // for WEXT_CSCAN_AMOUNT 9 #define RTW_SSID_SCAN_AMOUNT 9 /* for WEXT_CSCAN_AMOUNT 9 */
#define RTW_CHANNEL_SCAN_AMOUNT (14+37) #define RTW_CHANNEL_SCAN_AMOUNT (14+37)
struct sitesurvey_parm { struct sitesurvey_parm {
sint scan_mode; //active: 1, passive: 0 sint scan_mode; /* active: 1, passive: 0 */
/* sint bsslimit; // 1 ~ 48 */
u8 ssid_num; u8 ssid_num;
u8 ch_num; u8 ch_num;
struct ndis_802_11_ssid ssid[RTW_SSID_SCAN_AMOUNT]; struct ndis_802_11_ssid ssid[RTW_SSID_SCAN_AMOUNT];
@ -269,8 +250,8 @@ Command Mode
*/ */
struct setauth_parm { struct setauth_parm {
u8 mode; //0: legacy open, 1: legacy shared 2: 802.1x u8 mode; /* 0: legacy open, 1: legacy shared 2: 802.1x */
u8 _1x; //0: PSK, 1: TLS u8 _1x; /* 0: PSK, 1: TLS */
u8 rsvd[2]; u8 rsvd[2];
}; };
@ -287,11 +268,11 @@ when 802.1x ==> keyid > 2 ==> unicast key
*/ */
struct setkey_parm { struct setkey_parm {
u8 algorithm; // encryption algorithm, could be none, wep40, TKIP, CCMP, wep104 u8 algorithm; /* encryption algorithm, could be none, wep40, TKIP, CCMP, wep104 */
u8 keyid; u8 keyid;
u8 grpkey; // 1: this is the grpkey for 802.1x. 0: this is the unicast key for 802.1x u8 grpkey; /* 1: this is the grpkey for 802.1x. 0: this is the unicast key for 802.1x */
u8 set_tx; // 1: main tx key for wep. 0: other key. u8 set_tx; /* 1: main tx key for wep. 0: other key. */
u8 key[16]; // this could be 40 or 104 u8 key[16]; /* this could be 40 or 104 */
}; };
/* /*
@ -306,7 +287,7 @@ when shared key ==> algorithm/keyid
struct set_stakey_parm { struct set_stakey_parm {
u8 addr[ETH_ALEN]; u8 addr[ETH_ALEN];
u8 algorithm; u8 algorithm;
u8 id;// currently for erasing cam entry if algorithm == _NO_PRIVACY_ u8 id;/* currently for erasing cam entry if algorithm == _NO_PRIVACY_ */
u8 key[16]; u8 key[16];
}; };
@ -609,10 +590,10 @@ struct geth2clbk_rsp {
#endif /* CONFIG_H2CLBK */ #endif /* CONFIG_H2CLBK */
// CMD param Formart for driver extra cmd handler /* CMD param Formart for driver extra cmd handler */
struct drvextra_cmd_parm { struct drvextra_cmd_parm {
int ec_id; //extra cmd id int ec_id; /* extra cmd id */
int type_size; // Can use this field as the type id or command size int type_size; /* Can use this field as the type id or command size */
unsigned char *pbuf; unsigned char *pbuf;
}; };
@ -641,7 +622,7 @@ struct gettxagctbl_rsp {
}; };
struct setagcctrl_parm { struct setagcctrl_parm {
u32 agcctrl; // 0: pure hw, 1: fw u32 agcctrl; /* 0: pure hw, 1: fw */
}; };
@ -710,7 +691,7 @@ struct getratable_rsp {
}; };
//to get TX,RX retry count /* to get TX,RX retry count */
struct gettxretrycnt_parm{ struct gettxretrycnt_parm{
unsigned int rsvd; unsigned int rsvd;
}; };
@ -725,7 +706,7 @@ struct getrxretrycnt_rsp{
unsigned long rx_retrycnt; unsigned long rx_retrycnt;
}; };
//to get BCNOK,BCNERR count /* to get BCNOK,BCNERR count */
struct getbcnokcnt_parm{ struct getbcnokcnt_parm{
unsigned int rsvd; unsigned int rsvd;
}; };
@ -740,7 +721,7 @@ struct getbcnerrcnt_rsp{
unsigned long bcnerrcnt; unsigned long bcnerrcnt;
}; };
// to get current TX power level /* to get current TX power level */
struct getcurtxpwrlevel_parm{ struct getcurtxpwrlevel_parm{
unsigned int rsvd; unsigned int rsvd;
}; };
@ -798,7 +779,7 @@ struct SwitchAntenna_parm
{ {
u16 antenna_tx; u16 antenna_tx;
u16 antenna_rx; u16 antenna_rx;
// R_ANTENNA_SELECT_CCK cck_txrx; /* R_ANTENNA_SELECT_CCK cck_txrx; */
u8 cck_txrx; u8 cck_txrx;
}; };
@ -920,7 +901,7 @@ u8 rtw_setfwdig_cmd(struct adapter*padapter, u8 type);
u8 rtw_setfwra_cmd(struct adapter*padapter, u8 type); u8 rtw_setfwra_cmd(struct adapter*padapter, u8 type);
u8 rtw_addbareq_cmd(struct adapter*padapter, u8 tid, u8 *addr); u8 rtw_addbareq_cmd(struct adapter*padapter, u8 tid, u8 *addr);
// add for CONFIG_IEEE80211W, none 11w also can use /* add for CONFIG_IEEE80211W, none 11w also can use */
u8 rtw_reset_securitypriv_cmd(struct adapter*padapter); u8 rtw_reset_securitypriv_cmd(struct adapter*padapter);
u8 rtw_free_assoc_resources_cmd(struct adapter *padapter); u8 rtw_free_assoc_resources_cmd(struct adapter *padapter);
u8 rtw_dynamic_chk_wk_cmd(struct adapter *adapter); u8 rtw_dynamic_chk_wk_cmd(struct adapter *adapter);
@ -1118,4 +1099,4 @@ static struct _cmd_callback rtw_cmd_callback[] =
}; };
#endif #endif
#endif // _CMD_H_ #endif /* _CMD_H_ */

8
include/rtw_debug.h
View file

@ -64,7 +64,7 @@
#define _module_hci_ops_os_c_ BIT(24) #define _module_hci_ops_os_c_ BIT(24)
#define _module_rtl871x_ioctl_os_c BIT(25) #define _module_rtl871x_ioctl_os_c BIT(25)
#define _module_rtl8712_cmd_c_ BIT(26) #define _module_rtl8712_cmd_c_ BIT(26)
//#define _module_efuse_ BIT(27) /* define _module_efuse_ BIT(27) */
#define _module_rtl8192c_xmit_c_ BIT(28) #define _module_rtl8192c_xmit_c_ BIT(28)
#define _module_hal_xmit_c_ BIT(28) #define _module_hal_xmit_c_ BIT(28)
#define _module_efuse_ BIT(29) #define _module_efuse_ BIT(29)
@ -376,7 +376,7 @@ extern u32 GlobalDebugLevel;
int proc_set_btcoex_dbg(struct file *file, const char __user *buffer, int proc_set_btcoex_dbg(struct file *file, const char __user *buffer,
unsigned long count, void *data); unsigned long count, void *data);
#endif //CONFIG_BT_COEXIST #endif /* CONFIG_BT_COEXIST */
int proc_get_sreset(char *page, char **start, off_t offset, int count, int *eof, void *data); int proc_get_sreset(char *page, char **start, off_t offset, int count, int *eof, void *data);
int proc_set_sreset(struct file *file, const char __user *buffer, unsigned long count, void *data); int proc_set_sreset(struct file *file, const char __user *buffer, unsigned long count, void *data);
@ -387,6 +387,6 @@ int proc_set_odm_dbg_level(struct file *file, const char __user *buffer, unsigne
int proc_get_odm_adaptivity(char *page, char **start, off_t offset, int count, int *eof, void *data); int proc_get_odm_adaptivity(char *page, char **start, off_t offset, int count, int *eof, void *data);
int proc_set_odm_adaptivity(struct file *file, const char __user *buffer, unsigned long count, void *data); int proc_set_odm_adaptivity(struct file *file, const char __user *buffer, unsigned long count, void *data);
#endif //CONFIG_PROC_DEBUG #endif /* CONFIG_PROC_DEBUG */
#endif //__RTW_DEBUG_H__ #endif /* __RTW_DEBUG_H__ */

60
include/rtw_eeprom.h
View file

@ -25,24 +25,24 @@
#include <drv_types.h> #include <drv_types.h>
#define RTL8712_EEPROM_ID 0x8712 #define RTL8712_EEPROM_ID 0x8712
//#define EEPROM_MAX_SIZE 256 /* define EEPROM_MAX_SIZE 256 */
#define HWSET_MAX_SIZE_512 512 #define HWSET_MAX_SIZE_512 512
#define EEPROM_MAX_SIZE HWSET_MAX_SIZE_512 #define EEPROM_MAX_SIZE HWSET_MAX_SIZE_512
#define CLOCK_RATE 50 //100us #define CLOCK_RATE 50 /* 100us */
//- EEPROM opcodes /* EEPROM opcodes */
#define EEPROM_READ_OPCODE 06 #define EEPROM_READ_OPCODE 06
#define EEPROM_WRITE_OPCODE 05 #define EEPROM_WRITE_OPCODE 05
#define EEPROM_ERASE_OPCODE 07 #define EEPROM_ERASE_OPCODE 07
#define EEPROM_EWEN_OPCODE 19 // Erase/write enable #define EEPROM_EWEN_OPCODE 19 /* Erase/write enable */
#define EEPROM_EWDS_OPCODE 16 // Erase/write disable #define EEPROM_EWDS_OPCODE 16 /* Erase/write disable */
//Country codes /* Country codes */
#define USA 0x555320 #define USA 0x555320
#define EUROPE 0x1 //temp, should be provided later #define EUROPE 0x1 /* temp, should be provided later */
#define JAPAN 0x2 //temp, should be provided later #define JAPAN 0x2 /* temp, should be provided later */
#define EEPROM_CID_DEFAULT 0x0 #define EEPROM_CID_DEFAULT 0x0
#define EEPROM_CID_ALPHA 0x1 #define EEPROM_CID_ALPHA 0x1
@ -56,16 +56,16 @@
#define EEPROM_CID_CAMEO1 0xF #define EEPROM_CID_CAMEO1 0xF
#define EEPROM_CID_WNC_COREGA 0x12 #define EEPROM_CID_WNC_COREGA 0x12
#define EEPROM_CID_CLEVO 0x13 #define EEPROM_CID_CLEVO 0x13
#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108 #define EEPROM_CID_WHQL 0xFE /* added by chiyoko for dtm, 20090108 */
// /* */
// Customer ID, note that: /* Customer ID, note that: */
// This variable is initiailzed through EEPROM or registry, /* This variable is initiailzed through EEPROM or registry, */
// however, its definition may be different with that in EEPROM for /* however, its definition may be different with that in EEPROM for */
// EEPROM size consideration. So, we have to perform proper translation between them. /* EEPROM size consideration. So, we have to perform proper translation between them. */
// Besides, CustomerID of registry has precedence of that of EEPROM. /* Besides, CustomerID of registry has precedence of that of EEPROM. */
// defined below. 060703, by rcnjko. /* defined below. 060703, by rcnjko. */
// /* */
typedef enum _RT_CUSTOMER_ID typedef enum _RT_CUSTOMER_ID
{ {
RT_CID_DEFAULT = 0, RT_CID_DEFAULT = 0,
@ -77,7 +77,7 @@ typedef enum _RT_CUSTOMER_ID
RT_CID_819x_CAMEO = 6, RT_CID_819x_CAMEO = 6,
RT_CID_819x_RUNTOP = 7, RT_CID_819x_RUNTOP = 7,
RT_CID_819x_Senao = 8, RT_CID_819x_Senao = 8,
RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31. RT_CID_TOSHIBA = 9, /* Merge by Jacken, 2008/01/31. */
RT_CID_819x_Netcore = 10, RT_CID_819x_Netcore = 10,
RT_CID_Nettronix = 11, RT_CID_Nettronix = 11,
RT_CID_DLINK = 12, RT_CID_DLINK = 12,
@ -86,7 +86,7 @@ typedef enum _RT_CUSTOMER_ID
RT_CID_CHINA_MOBILE = 15, RT_CID_CHINA_MOBILE = 15,
RT_CID_819x_ALPHA = 16, RT_CID_819x_ALPHA = 16,
RT_CID_819x_Sitecom = 17, RT_CID_819x_Sitecom = 17,
RT_CID_CCX = 18, // It's set under CCX logo test and isn't demanded for CCX functions, but for test behavior like retry limit and tx report. By Bruce, 2009-02-17. RT_CID_CCX = 18, /* It's set under CCX logo test and isn't demanded for CCX functions, but for test behavior like retry limit and tx report. By Bruce, 2009-02-17. */
RT_CID_819x_Lenovo = 19, RT_CID_819x_Lenovo = 19,
RT_CID_819x_QMI = 20, RT_CID_819x_QMI = 20,
RT_CID_819x_Edimax_Belkin = 21, RT_CID_819x_Edimax_Belkin = 21,
@ -95,7 +95,7 @@ typedef enum _RT_CUSTOMER_ID
RT_CID_819x_MSI = 24, RT_CID_819x_MSI = 24,
RT_CID_819x_Acer = 25, RT_CID_819x_Acer = 25,
RT_CID_819x_AzWave_ASUS = 26, RT_CID_819x_AzWave_ASUS = 26,
RT_CID_819x_AzWave = 27, // For AzWave in PCIe, The ID is AzWave use and not only Asus RT_CID_819x_AzWave = 27, /* For AzWave in PCIe, The ID is AzWave use and not only Asus */
RT_CID_819x_HP = 28, RT_CID_819x_HP = 28,
RT_CID_819x_WNC_COREGA = 29, RT_CID_819x_WNC_COREGA = 29,
RT_CID_819x_Arcadyan_Belkin = 30, RT_CID_819x_Arcadyan_Belkin = 30,
@ -117,19 +117,19 @@ struct eeprom_priv
u8 bautoload_fail_flag; u8 bautoload_fail_flag;
u8 bloadfile_fail_flag; u8 bloadfile_fail_flag;
u8 bloadmac_fail_flag; u8 bloadmac_fail_flag;
//u8 bempty; /* u8 bempty; */
//u8 sys_config; /* u8 sys_config; */
u8 mac_addr[6]; //PermanentAddress u8 mac_addr[6]; /* PermanentAddress */
//u8 config0; /* u8 config0; */
u16 channel_plan; u16 channel_plan;
//u8 country_string[3]; /* u8 country_string[3]; */
//u8 tx_power_b[15]; /* u8 tx_power_b[15]; */
//u8 tx_power_g[15]; /* u8 tx_power_g[15]; */
//u8 tx_power_a[201]; /* u8 tx_power_a[201]; */
u8 EepromOrEfuse; u8 EepromOrEfuse;
u8 efuse_eeprom_data[HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes) u8 efuse_eeprom_data[HWSET_MAX_SIZE_512]; /* 92C:256bytes, 88E:512bytes, we use union set (512bytes) */
}; };
void eeprom_write16(struct adapter *padapter, u16 reg, u16 data); void eeprom_write16(struct adapter *padapter, u16 reg, u16 data);
@ -139,4 +139,4 @@ void eeprom_read_sz(struct adapter *padapter, u16 reg,u8 *data, u32 sz);
void read_eeprom_content_by_attrib(struct adapter *padapter); void read_eeprom_content_by_attrib(struct adapter *padapter);
#endif //__RTL871X_EEPROM_H__ #endif /* __RTL871X_EEPROM_H__ */

8
include/rtw_efuse.h
View file

@ -66,13 +66,13 @@ enum _EFUSE_DEF_TYPE {
#define EFUSE_REPEAT_THRESHOLD_ 3 #define EFUSE_REPEAT_THRESHOLD_ 3
//============================================= /* */
// The following is for BT Efuse definition /* The following is for BT Efuse definition */
//============================================= /* */
#define EFUSE_BT_MAX_MAP_LEN 1024 #define EFUSE_BT_MAX_MAP_LEN 1024
#define EFUSE_MAX_BANK 4 #define EFUSE_MAX_BANK 4
#define EFUSE_MAX_BT_BANK (EFUSE_MAX_BANK-1) #define EFUSE_MAX_BT_BANK (EFUSE_MAX_BANK-1)
//============================================= /* */
/*--------------------------Define Parameters-------------------------------*/ /*--------------------------Define Parameters-------------------------------*/
#define EFUSE_MAX_WORD_UNIT 4 #define EFUSE_MAX_WORD_UNIT 4

6
include/rtw_event.h
View file

@ -83,7 +83,7 @@ struct stassoc_event {
struct stadel_event { struct stadel_event {
unsigned char macaddr[6]; unsigned char macaddr[6];
unsigned char rsvd[2]; //for reason unsigned char rsvd[2]; /* for reason */
int mac_id; int mac_id;
}; };
@ -104,7 +104,7 @@ struct c2hlbk_event{
unsigned char b1; unsigned char b1;
unsigned int w1; unsigned int w1;
}; };
#endif//CONFIG_H2CLBK #endif/* CONFIG_H2CLBK */
#define GEN_EVT_CODE(event) event ## _EVT_ #define GEN_EVT_CODE(event) event ## _EVT_
@ -142,4 +142,4 @@ struct network_queue {
}; };
#endif // _WLANEVENT_H_ #endif /* _WLANEVENT_H_ */

22
include/rtw_ht.h
View file

@ -27,23 +27,23 @@
struct ht_priv struct ht_priv
{ {
u32 ht_option; u32 ht_option;
u32 ampdu_enable;//for enable Tx A-MPDU u32 ampdu_enable;/* for enable Tx A-MPDU */
//u8 baddbareq_issued[16]; /* u8 baddbareq_issued[16]; */
u32 tx_amsdu_enable;//for enable Tx A-MSDU u32 tx_amsdu_enable;/* for enable Tx A-MSDU */
u32 tx_amdsu_maxlen; // 1: 8k, 0:4k ; default:8k, for tx u32 tx_amdsu_maxlen; /* 1: 8k, 0:4k ; default:8k, for tx */
u32 rx_ampdu_maxlen; //for rx reordering ctrl win_sz, updated when join_callback. u32 rx_ampdu_maxlen; /* for rx reordering ctrl win_sz, updated when join_callback. */
u8 bwmode;// u8 bwmode;/* */
u8 ch_offset;//PRIME_CHNL_OFFSET u8 ch_offset;/* PRIME_CHNL_OFFSET */
u8 sgi;//short GI u8 sgi;/* short GI */
//for processing Tx A-MPDU /* for processing Tx A-MPDU */
u8 agg_enable_bitmap; u8 agg_enable_bitmap;
//u8 ADDBA_retry_count; /* u8 ADDBA_retry_count; */
u8 candidate_tid_bitmap; u8 candidate_tid_bitmap;
struct rtw_ieee80211_ht_cap ht_cap; struct rtw_ieee80211_ht_cap ht_cap;
}; };
#endif //_RTL871X_HT_H_ #endif /* _RTL871X_HT_H_ */

66
include/rtw_io.h
View file

@ -50,7 +50,7 @@
#define _IO_WAIT_COMPLETE 1 #define _IO_WAIT_COMPLETE 1
#define _IO_WAIT_RSP 2 #define _IO_WAIT_RSP 2
// IO COMMAND TYPE /* IO COMMAND TYPE */
#define _IOSZ_MASK_ (0x7F) #define _IOSZ_MASK_ (0x7F)
#define _IO_WRITE_ BIT(7) #define _IO_WRITE_ BIT(7)
#define _IO_FIXED_ BIT(8) #define _IO_FIXED_ BIT(8)
@ -69,7 +69,7 @@
// IO STATUS TYPE /* IO STATUS TYPE */
#define _IO_ERR_ BIT(2) #define _IO_ERR_ BIT(2)
#define _IO_SUCCESS_ BIT(1) #define _IO_SUCCESS_ BIT(1)
#define _IO_DONE_ BIT(0) #define _IO_DONE_ BIT(0)
@ -102,9 +102,9 @@
//below is for the intf_option bit defition... /* below is for the intf_option bit defition... */
#define _INTF_ASYNC_ BIT(0) //support async io #define _INTF_ASYNC_ BIT(0) /* support async io */
struct intf_priv; struct intf_priv;
struct intf_hdl; struct intf_hdl;
@ -158,7 +158,7 @@ struct io_req {
struct intf_hdl { struct intf_hdl {
struct adapter *padapter; struct adapter *padapter;
struct dvobj_priv *pintf_dev;// pointer to &(padapter->dvobjpriv); struct dvobj_priv *pintf_dev;/* pointer to &(padapter->dvobjpriv); */
struct _io_ops io_ops; struct _io_ops io_ops;
@ -168,34 +168,34 @@ struct reg_protocol_rd {
#ifdef __LITTLE_ENDIAN #ifdef __LITTLE_ENDIAN
//DW1 /* DW1 */
u32 NumOfTrans:4; u32 NumOfTrans:4;
u32 Reserved1:4; u32 Reserved1:4;
u32 Reserved2:24; u32 Reserved2:24;
//DW2 /* DW2 */
u32 ByteCount:7; u32 ByteCount:7;
u32 WriteEnable:1; //0:read, 1:write u32 WriteEnable:1; /* 0:read, 1:write */
u32 FixOrContinuous:1; //0:continuous, 1: Fix u32 FixOrContinuous:1; /* 0:continuous, 1: Fix */
u32 BurstMode:1; u32 BurstMode:1;
u32 Byte1Access:1; u32 Byte1Access:1;
u32 Byte2Access:1; u32 Byte2Access:1;
u32 Byte4Access:1; u32 Byte4Access:1;
u32 Reserved3:3; u32 Reserved3:3;
u32 Reserved4:16; u32 Reserved4:16;
//DW3 /* DW3 */
u32 BusAddress; u32 BusAddress;
//DW4 /* DW4 */
//u32 Value; /* u32 Value; */
#else #else
//DW1 /* DW1 */
u32 Reserved1 :4; u32 Reserved1 :4;
u32 NumOfTrans :4; u32 NumOfTrans :4;
u32 Reserved2 :24; u32 Reserved2 :24;
//DW2 /* DW2 */
u32 WriteEnable : 1; u32 WriteEnable : 1;
u32 ByteCount :7; u32 ByteCount :7;
@ -210,11 +210,11 @@ struct reg_protocol_rd {
u32 Reserved4 : 16; u32 Reserved4 : 16;
//DW3 /* DW3 */
u32 BusAddress; u32 BusAddress;
//DW4 /* DW4 */
//u32 Value; /* u32 Value; */
#endif #endif
@ -226,33 +226,33 @@ struct reg_protocol_wt {
#ifdef __LITTLE_ENDIAN #ifdef __LITTLE_ENDIAN
//DW1 /* DW1 */
u32 NumOfTrans:4; u32 NumOfTrans:4;
u32 Reserved1:4; u32 Reserved1:4;
u32 Reserved2:24; u32 Reserved2:24;
//DW2 /* DW2 */
u32 ByteCount:7; u32 ByteCount:7;
u32 WriteEnable:1; //0:read, 1:write u32 WriteEnable:1; /* 0:read, 1:write */
u32 FixOrContinuous:1; //0:continuous, 1: Fix u32 FixOrContinuous:1; /* 0:continuous, 1: Fix */
u32 BurstMode:1; u32 BurstMode:1;
u32 Byte1Access:1; u32 Byte1Access:1;
u32 Byte2Access:1; u32 Byte2Access:1;
u32 Byte4Access:1; u32 Byte4Access:1;
u32 Reserved3:3; u32 Reserved3:3;
u32 Reserved4:16; u32 Reserved4:16;
//DW3 /* DW3 */
u32 BusAddress; u32 BusAddress;
//DW4 /* DW4 */
u32 Value; u32 Value;
#else #else
//DW1 /* DW1 */
u32 Reserved1 :4; u32 Reserved1 :4;
u32 NumOfTrans :4; u32 NumOfTrans :4;
u32 Reserved2 :24; u32 Reserved2 :24;
//DW2 /* DW2 */
u32 WriteEnable : 1; u32 WriteEnable : 1;
u32 ByteCount :7; u32 ByteCount :7;
@ -266,10 +266,10 @@ struct reg_protocol_wt {
u32 Reserved4 : 16; u32 Reserved4 : 16;
//DW3 /* DW3 */
u32 BusAddress; u32 BusAddress;
//DW4 /* DW4 */
u32 Value; u32 Value;
#endif #endif
@ -288,9 +288,9 @@ Below is the data structure used by _io_handler
struct io_queue { struct io_queue {
spinlock_t lock; spinlock_t lock;
struct list_head free_ioreqs; struct list_head free_ioreqs;
struct list_head pending; //The io_req list that will be served in the single protocol read/write. struct list_head pending; /* The io_req list that will be served in the single protocol read/write. */
struct list_head processing; struct list_head processing;
u8 *free_ioreqs_buf; // 4-byte aligned u8 *free_ioreqs_buf; /* 4-byte aligned */
u8 *pallocated_free_ioreqs_buf; u8 *pallocated_free_ioreqs_buf;
struct intf_hdl intf; struct intf_hdl intf;
}; };
@ -372,7 +372,7 @@ extern int dbg_rtw_writeN(struct adapter *adapter, u32 addr ,u32 length , u8 *da
#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port(adapter, addr, cnt, mem) #define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port(adapter, addr, cnt, mem)
#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms)) #define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms))
#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel(adapter) #define rtw_write_port_cancel(adapter) _rtw_write_port_cancel(adapter)
#else //DBG_IO #else /* DBG_IO */
#define rtw_read8(adapter, addr) _rtw_read8((adapter), (addr)) #define rtw_read8(adapter, addr) _rtw_read8((adapter), (addr))
#define rtw_read16(adapter, addr) _rtw_read16((adapter), (addr)) #define rtw_read16(adapter, addr) _rtw_read16((adapter), (addr))
#define rtw_read32(adapter, addr) _rtw_read32((adapter), (addr)) #define rtw_read32(adapter, addr) _rtw_read32((adapter), (addr))
@ -393,11 +393,11 @@ extern int dbg_rtw_writeN(struct adapter *adapter, u32 addr ,u32 length , u8 *da
#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port((adapter), (addr), (cnt), (mem)) #define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port((adapter), (addr), (cnt), (mem))
#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms)) #define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms))
#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel((adapter)) #define rtw_write_port_cancel(adapter) _rtw_write_port_cancel((adapter))
#endif //DBG_IO #endif /* DBG_IO */
extern void rtw_write_scsi(struct adapter *adapter, u32 cnt, u8 *pmem); extern void rtw_write_scsi(struct adapter *adapter, u32 cnt, u8 *pmem);
//ioreq /* ioreq */
extern void ioreq_read8(struct adapter *adapter, u32 addr, u8 *pval); extern void ioreq_read8(struct adapter *adapter, u32 addr, u8 *pval);
extern void ioreq_read16(struct adapter *adapter, u32 addr, u16 *pval); extern void ioreq_read16(struct adapter *adapter, u32 addr, u16 *pval);
extern void ioreq_read32(struct adapter *adapter, u32 addr, u32 *pval); extern void ioreq_read32(struct adapter *adapter, u32 addr, u32 *pval);
@ -469,4 +469,4 @@ extern void dev_power_down(struct adapter * Adapter, u8 bpwrup);
#define PlatformEFIORead4Byte(_a,_b) \ #define PlatformEFIORead4Byte(_a,_b) \
rtw_read32(_a,_b) rtw_read32(_a,_b)
#endif //_RTL8711_IO_H_ #endif /* _RTL8711_IO_H_ */

18
include/rtw_ioctl.h
View file

@ -34,7 +34,7 @@
#endif #endif
// For DDK-defined OIDs /* For DDK-defined OIDs */
#define OID_NDIS_SEG1 0x00010100 #define OID_NDIS_SEG1 0x00010100
#define OID_NDIS_SEG2 0x00010200 #define OID_NDIS_SEG2 0x00010200
#define OID_NDIS_SEG3 0x00020100 #define OID_NDIS_SEG3 0x00020100
@ -57,7 +57,7 @@
#define SZ_OID_NDIS_SEG9 24 #define SZ_OID_NDIS_SEG9 24
#define SZ_OID_NDIS_SEG10 19 #define SZ_OID_NDIS_SEG10 19
// For Realtek-defined OIDs /* For Realtek-defined OIDs */
#define OID_MP_SEG1 0xFF871100 #define OID_MP_SEG1 0xFF871100
#define OID_MP_SEG2 0xFF818000 #define OID_MP_SEG2 0xFF818000
@ -78,12 +78,12 @@ enum oid_type
}; };
struct oid_funs_node { struct oid_funs_node {
unsigned int oid_start; //the starting number for OID unsigned int oid_start; /* the starting number for OID */
unsigned int oid_end; //the ending number for OID unsigned int oid_end; /* the ending number for OID */
struct oid_obj_priv *node_array; struct oid_obj_priv *node_array;
unsigned int array_sz; //the size of node_array unsigned int array_sz; /* the size of node_array */
int query_counter; //count the number of query hits for this segment int query_counter; /* count the number of query hits for this segment */
int set_counter; //count the number of set hits for this segment int set_counter; /* count the number of set hits for this segment */
}; };
struct oid_par_priv struct oid_par_priv
@ -99,7 +99,7 @@ struct oid_par_priv
}; };
struct oid_obj_priv { struct oid_obj_priv {
unsigned char dbg; // 0: without OID debug message 1: with OID debug message unsigned char dbg; /* 0: without OID debug message 1: with OID debug message */
NDIS_STATUS (*oidfuns)(struct oid_par_priv *poid_par_priv); NDIS_STATUS (*oidfuns)(struct oid_par_priv *poid_par_priv);
}; };
@ -125,4 +125,4 @@ extern NDIS_STATUS drv_set_info(
u32* BytesNeeded u32* BytesNeeded
); );
#endif // #ifndef __INC_CEINFO_ #endif /* #ifndef __INC_CEINFO_ */

16
include/rtw_ioctl_rtl.h
View file

@ -24,8 +24,8 @@
#include <osdep_service.h> #include <osdep_service.h>
#include <drv_types.h> #include <drv_types.h>
//************** oid_rtl_seg_01_01 ************** /* oid_rtl_seg_01_01 ************** */
NDIS_STATUS oid_rt_get_signal_quality_hdl(struct oid_par_priv* poid_par_priv);//84 NDIS_STATUS oid_rt_get_signal_quality_hdl(struct oid_par_priv* poid_par_priv);/* 84 */
NDIS_STATUS oid_rt_get_small_packet_crc_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_get_small_packet_crc_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_get_middle_packet_crc_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_get_middle_packet_crc_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_get_large_packet_crc_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_get_large_packet_crc_hdl(struct oid_par_priv* poid_par_priv);
@ -35,10 +35,10 @@ NDIS_STATUS oid_rt_get_rx_total_packet_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_get_tx_beacon_ok_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_get_tx_beacon_ok_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_get_tx_beacon_err_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_get_tx_beacon_err_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_set_fw_dig_state_hdl(struct oid_par_priv* poid_par_priv); //8a NDIS_STATUS oid_rt_pro_set_fw_dig_state_hdl(struct oid_par_priv* poid_par_priv); /* 8a */
NDIS_STATUS oid_rt_pro_set_fw_ra_state_hdl(struct oid_par_priv* poid_par_priv); //8b NDIS_STATUS oid_rt_pro_set_fw_ra_state_hdl(struct oid_par_priv* poid_par_priv); /* 8b */
NDIS_STATUS oid_rt_get_rx_icv_err_hdl(struct oid_par_priv* poid_par_priv);//93 NDIS_STATUS oid_rt_get_rx_icv_err_hdl(struct oid_par_priv* poid_par_priv);/* 93 */
NDIS_STATUS oid_rt_set_encryption_algorithm_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_set_encryption_algorithm_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_get_preamble_mode_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_get_preamble_mode_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_get_ap_ip_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_get_ap_ip_hdl(struct oid_par_priv* poid_par_priv);
@ -63,17 +63,17 @@ NDIS_STATUS oid_rt_wireless_mode_for_scan_list_hdl(struct oid_par_priv* poid_par
NDIS_STATUS oid_rt_get_bss_wireless_mode_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_get_bss_wireless_mode_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_scan_with_magic_packet_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_scan_with_magic_packet_hdl(struct oid_par_priv* poid_par_priv);
//************** oid_rtl_seg_01_03 section start ************** /* oid_rtl_seg_01_03 section start ************** */
NDIS_STATUS oid_rt_ap_get_associated_station_list_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_ap_get_associated_station_list_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_ap_switch_into_ap_mode_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_ap_switch_into_ap_mode_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_ap_supported_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_ap_supported_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_ap_set_passphrase_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_ap_set_passphrase_hdl(struct oid_par_priv* poid_par_priv);
// oid_rtl_seg_01_11 /* oid_rtl_seg_01_11 */
NDIS_STATUS oid_rt_pro_rf_write_registry_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_rf_write_registry_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_rf_read_registry_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_rf_read_registry_hdl(struct oid_par_priv* poid_par_priv);
//************** oid_rtl_seg_03_00 section start ************** /* oid_rtl_seg_03_00 section start ************** */
NDIS_STATUS oid_rt_get_connect_state_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_get_connect_state_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_set_default_key_id_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_set_default_key_id_hdl(struct oid_par_priv* poid_par_priv);

2
include/rtw_iol.h
View file

@ -68,4 +68,4 @@ int _rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, u16 addr,
u8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame); u8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame);
void rtw_IOL_cmd_buf_dump(struct adapter *Adapter,int buf_len,u8 *pbuf); void rtw_IOL_cmd_buf_dump(struct adapter *Adapter,int buf_len,u8 *pbuf);
#endif //__RTW_IOL_H_ #endif /* __RTW_IOL_H_ */

82
include/rtw_led.h
View file

@ -31,8 +31,8 @@
#define LED_BLINK_LONG_INTERVAL 400 #define LED_BLINK_LONG_INTERVAL 400
#define LED_BLINK_NO_LINK_INTERVAL_ALPHA 1000 #define LED_BLINK_NO_LINK_INTERVAL_ALPHA 1000
#define LED_BLINK_LINK_INTERVAL_ALPHA 500 //500 #define LED_BLINK_LINK_INTERVAL_ALPHA 500 /* 500 */
#define LED_BLINK_SCAN_INTERVAL_ALPHA 180 //150 #define LED_BLINK_SCAN_INTERVAL_ALPHA 180 /* 150 */
#define LED_BLINK_FASTER_INTERVAL_ALPHA 50 #define LED_BLINK_FASTER_INTERVAL_ALPHA 50
#define LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA 5000 #define LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA 5000
@ -44,17 +44,17 @@
#define LED_BLINK_FAST_INTERVAL_BITLAND 30 #define LED_BLINK_FAST_INTERVAL_BITLAND 30
// 060403, rcnjko: Customized for AzWave. /* 060403, rcnjko: Customized for AzWave. */
#define LED_CM2_BLINK_ON_INTERVAL 250 #define LED_CM2_BLINK_ON_INTERVAL 250
#define LED_CM2_BLINK_OFF_INTERVAL 4750 #define LED_CM2_BLINK_OFF_INTERVAL 4750
#define LED_CM8_BLINK_INTERVAL 500 //for QMI #define LED_CM8_BLINK_INTERVAL 500 /* for QMI */
#define LED_CM8_BLINK_OFF_INTERVAL 3750 //for QMI #define LED_CM8_BLINK_OFF_INTERVAL 3750 /* for QMI */
// 080124, lanhsin: Customized for RunTop /* 080124, lanhsin: Customized for RunTop */
#define LED_RunTop_BLINK_INTERVAL 300 #define LED_RunTop_BLINK_INTERVAL 300
// 060421, rcnjko: Customized for Sercomm Printer Server case. /* 060421, rcnjko: Customized for Sercomm Printer Server case. */
#define LED_CM3_BLINK_INTERVAL 1500 #define LED_CM3_BLINK_INTERVAL 1500
typedef enum _LED_CTL_MODE{ typedef enum _LED_CTL_MODE{
@ -68,9 +68,9 @@ typedef enum _LED_CTL_MODE{
LED_CTL_START_TO_LINK = 8, LED_CTL_START_TO_LINK = 8,
LED_CTL_START_WPS = 9, LED_CTL_START_WPS = 9,
LED_CTL_STOP_WPS = 10, LED_CTL_STOP_WPS = 10,
LED_CTL_START_WPS_BOTTON = 11, //added for runtop LED_CTL_START_WPS_BOTTON = 11, /* added for runtop */
LED_CTL_STOP_WPS_FAIL = 12, //added for ALPHA LED_CTL_STOP_WPS_FAIL = 12, /* added for ALPHA */
LED_CTL_STOP_WPS_FAIL_OVERLAP = 13, //added for BELKIN LED_CTL_STOP_WPS_FAIL_OVERLAP = 13, /* added for BELKIN */
LED_CTL_CONNECTION_NO_TRANSFER = 14, LED_CTL_CONNECTION_NO_TRANSFER = 14,
}LED_CTL_MODE; }LED_CTL_MODE;
@ -81,14 +81,14 @@ typedef enum _LED_STATE_871x{
LED_BLINK_NORMAL = 3, LED_BLINK_NORMAL = 3,
LED_BLINK_SLOWLY = 4, LED_BLINK_SLOWLY = 4,
LED_BLINK_POWER_ON = 5, LED_BLINK_POWER_ON = 5,
LED_BLINK_SCAN = 6, // LED is blinking during scanning period, the # of times to blink is depend on time for scanning. LED_BLINK_SCAN = 6, /* LED is blinking during scanning period, the # of times to blink is depend on time for scanning. */
LED_BLINK_NO_LINK = 7, // LED is blinking during no link state. LED_BLINK_NO_LINK = 7, /* LED is blinking during no link state. */
LED_BLINK_StartToBlink = 8,// Customzied for Sercomm Printer Server case LED_BLINK_StartToBlink = 8,/* Customzied for Sercomm Printer Server case */
LED_BLINK_TXRX = 9, LED_BLINK_TXRX = 9,
LED_BLINK_WPS = 10, // LED is blinkg during WPS communication LED_BLINK_WPS = 10, /* LED is blinkg during WPS communication */
LED_BLINK_WPS_STOP = 11, //for ALPHA LED_BLINK_WPS_STOP = 11, /* for ALPHA */
LED_BLINK_WPS_STOP_OVERLAP = 12, //for BELKIN LED_BLINK_WPS_STOP_OVERLAP = 12, /* for BELKIN */
LED_BLINK_RUNTOP = 13, // Customized for RunTop LED_BLINK_RUNTOP = 13, /* Customized for RunTop */
LED_BLINK_CAMEO = 14, LED_BLINK_CAMEO = 14,
LED_BLINK_XAVI = 15, LED_BLINK_XAVI = 15,
LED_BLINK_ALWAYS_ON = 16, LED_BLINK_ALWAYS_ON = 16,
@ -105,30 +105,30 @@ typedef enum _LED_PIN_871x{
typedef struct _LED_871x{ typedef struct _LED_871x{
struct adapter *padapter; struct adapter *padapter;
LED_PIN_871x LedPin; // Identify how to implement this SW led. LED_PIN_871x LedPin; /* Identify how to implement this SW led. */
LED_STATE_871x CurrLedState; // Current LED state. LED_STATE_871x CurrLedState; /* Current LED state. */
LED_STATE_871x BlinkingLedState; // Next state for blinking, either RTW_LED_ON or RTW_LED_OFF are. LED_STATE_871x BlinkingLedState; /* Next state for blinking, either RTW_LED_ON or RTW_LED_OFF are. */
u8 bLedOn; // true if LED is ON, false if LED is OFF. u8 bLedOn; /* true if LED is ON, false if LED is OFF. */
u8 bLedBlinkInProgress; // true if it is blinking, false o.w.. u8 bLedBlinkInProgress; /* true if it is blinking, false o.w.. */
u8 bLedWPSBlinkInProgress; u8 bLedWPSBlinkInProgress;
u32 BlinkTimes; // Number of times to toggle led state for blinking. u32 BlinkTimes; /* Number of times to toggle led state for blinking. */
struct timer_list BlinkTimer; // Timer object for led blinking. struct timer_list BlinkTimer; /* Timer object for led blinking. */
u8 bSWLedCtrl; u8 bSWLedCtrl;
// ALPHA, added by chiyoko, 20090106 /* ALPHA, added by chiyoko, 20090106 */
u8 bLedNoLinkBlinkInProgress; u8 bLedNoLinkBlinkInProgress;
u8 bLedLinkBlinkInProgress; u8 bLedLinkBlinkInProgress;
u8 bLedStartToLinkBlinkInProgress; u8 bLedStartToLinkBlinkInProgress;
u8 bLedScanBlinkInProgress; u8 bLedScanBlinkInProgress;
#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
struct work_struct BlinkWorkItem; // Workitem used by BlinkTimer to manipulate H/W to blink LED. struct work_struct BlinkWorkItem; /* Workitem used by BlinkTimer to manipulate H/W to blink LED. */
#endif #endif
} LED_871x, *PLED_871x; } LED_871x, *PLED_871x;
@ -139,19 +139,19 @@ typedef struct _LED_871x{
#define IS_LED_BLINKING(_LED_871x) (((PLED_871x)_LED_871x)->bLedWPSBlinkInProgress \ #define IS_LED_BLINKING(_LED_871x) (((PLED_871x)_LED_871x)->bLedWPSBlinkInProgress \
||((PLED_871x)_LED_871x)->bLedScanBlinkInProgress) ||((PLED_871x)_LED_871x)->bLedScanBlinkInProgress)
//================================================================================ /* */
// LED customization. /* LED customization. */
//================================================================================ /* */
typedef enum _LED_STRATEGY_871x{ typedef enum _LED_STRATEGY_871x{
SW_LED_MODE0 = 0, // SW control 1 LED via GPIO0. It is default option. SW_LED_MODE0 = 0, /* SW control 1 LED via GPIO0. It is default option. */
SW_LED_MODE1= 1, // 2 LEDs, through LED0 and LED1. For ALPHA. SW_LED_MODE1= 1, /* 2 LEDs, through LED0 and LED1. For ALPHA. */
SW_LED_MODE2 = 2, // SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. SW_LED_MODE2 = 2, /* SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. */
SW_LED_MODE3 = 3, // SW control 1 LED via GPIO0, customized for Sercomm Printer Server case. SW_LED_MODE3 = 3, /* SW control 1 LED via GPIO0, customized for Sercomm Printer Server case. */
SW_LED_MODE4 = 4, //for Edimax / Belkin SW_LED_MODE4 = 4, /* for Edimax / Belkin */
SW_LED_MODE5 = 5, //for Sercomm / Belkin SW_LED_MODE5 = 5, /* for Sercomm / Belkin */
SW_LED_MODE6 = 6, //for 88CU minicard, porting from ce SW_LED_MODE7 SW_LED_MODE6 = 6, /* for 88CU minicard, porting from ce SW_LED_MODE7 */
HW_LED = 50, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes, see MAC.CONFIG1 for details.) HW_LED = 50, /* HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes, see MAC.CONFIG1 for details.) */
LED_ST_NONE = 99, LED_ST_NONE = 99,
}LED_STRATEGY_871x, *PLED_STRATEGY_871x; }LED_STRATEGY_871x, *PLED_STRATEGY_871x;
@ -177,9 +177,9 @@ struct led_priv{
if((adapter)->ledpriv.LedControlHandler) \ if((adapter)->ledpriv.LedControlHandler) \
(adapter)->ledpriv.LedControlHandler((adapter), (LedAction)); \ (adapter)->ledpriv.LedControlHandler((adapter), (LedAction)); \
} while(0) } while(0)
#else //CONFIG_SW_LED #else /* CONFIG_SW_LED */
#define rtw_led_control(adapter, LedAction) #define rtw_led_control(adapter, LedAction)
#endif //CONFIG_SW_LED #endif /* CONFIG_SW_LED */
void BlinkTimerCallback(void *data); void BlinkTimerCallback(void *data);
void BlinkWorkItemCallback(struct work_struct *work); void BlinkWorkItemCallback(struct work_struct *work);
@ -198,7 +198,7 @@ DeInitLed871x(
PLED_871x pLed PLED_871x pLed
); );
//hal... /* hal... */
struct adapter; struct adapter;
void BlinkHandler(PLED_871x pLed); void BlinkHandler(PLED_871x pLed);
@ -206,4 +206,4 @@ void SwLedOn(struct adapter *padapter, PLED_871x pLed);
void SwLedOff(struct adapter *padapter, PLED_871x pLed); void SwLedOff(struct adapter *padapter, PLED_871x pLed);
#endif //__RTW_LED_H_ #endif /* __RTW_LED_H_ */

301
include/rtw_mlme.h
View file

@ -29,22 +29,22 @@
#define MAX_BSS_CNT 128 #define MAX_BSS_CNT 128
#define MAX_JOIN_TIMEOUT 6500 #define MAX_JOIN_TIMEOUT 6500
// Commented by Albert 20101105 /* Commented by Albert 20101105 */
// Increase the scanning timeout because of increasing the SURVEY_TO value. /* Increase the scanning timeout because of increasing the SURVEY_TO value. */
#define SCANNING_TIMEOUT 8000 #define SCANNING_TIMEOUT 8000
#define SCAN_INTERVAL (30) // unit:2sec, 30*2=60sec #define SCAN_INTERVAL (30) /* unit:2sec, 30*2=60sec */
#ifdef PALTFORM_OS_WINCE #ifdef PALTFORM_OS_WINCE
#define SCANQUEUE_LIFETIME 12000000 // unit:us #define SCANQUEUE_LIFETIME 12000000 /* unit:us */
#else #else
#define SCANQUEUE_LIFETIME 20 // unit:sec #define SCANQUEUE_LIFETIME 20 /* unit:sec */
#endif #endif
#define WIFI_NULL_STATE 0x00000000 #define WIFI_NULL_STATE 0x00000000
#define WIFI_ASOC_STATE 0x00000001 // Under Linked state... #define WIFI_ASOC_STATE 0x00000001 /* Under Linked state... */
#define WIFI_REASOC_STATE 0x00000002 #define WIFI_REASOC_STATE 0x00000002
#define WIFI_SLEEP_STATE 0x00000004 #define WIFI_SLEEP_STATE 0x00000004
#define WIFI_STATION_STATE 0x00000008 #define WIFI_STATION_STATE 0x00000008
@ -55,38 +55,29 @@
#define WIFI_UNDER_LINKING 0x00000080 #define WIFI_UNDER_LINKING 0x00000080
#define WIFI_UNDER_WPS 0x00000100 #define WIFI_UNDER_WPS 0x00000100
//#define WIFI_UNDER_CMD 0x00000200 /* define WIFI_UNDER_CMD 0x00000200 */
//#define WIFI_UNDER_P2P 0x00000400 /* define WIFI_UNDER_P2P 0x00000400 */
#define WIFI_STA_ALIVE_CHK_STATE 0x00000400 #define WIFI_STA_ALIVE_CHK_STATE 0x00000400
#define WIFI_SITE_MONITOR 0x00000800 //to indicate the station is under site surveying #define WIFI_SITE_MONITOR 0x00000800 /* to indicate the station is under site surveying */
#ifdef WDS #ifdef WDS
#define WIFI_WDS 0x00001000 #define WIFI_WDS 0x00001000
#define WIFI_WDS_RX_BEACON 0x00002000 // already rx WDS AP beacon #define WIFI_WDS_RX_BEACON 0x00002000 /* already rx WDS AP beacon */
#endif #endif
#ifdef AUTO_CONFIG #ifdef AUTO_CONFIG
#define WIFI_AUTOCONF 0x00004000 #define WIFI_AUTOCONF 0x00004000
#define WIFI_AUTOCONF_IND 0x00008000 #define WIFI_AUTOCONF_IND 0x00008000
#endif #endif
/*
// ========== P2P Section Start ===============
#define WIFI_P2P_LISTEN_STATE 0x00010000
#define WIFI_P2P_GROUP_FORMATION_STATE 0x00020000
// ========== P2P Section End ===============
*/
//#ifdef UNDER_MPTEST
#define WIFI_MP_STATE 0x00010000 #define WIFI_MP_STATE 0x00010000
#define WIFI_MP_CTX_BACKGROUND 0x00020000 // in continous tx background #define WIFI_MP_CTX_BACKGROUND 0x00020000 /* in continous tx background */
#define WIFI_MP_CTX_ST 0x00040000 // in continous tx with single-tone #define WIFI_MP_CTX_ST 0x00040000 /* in continous tx with single-tone */
#define WIFI_MP_CTX_BACKGROUND_PENDING 0x00080000 // pending in continous tx background due to out of skb #define WIFI_MP_CTX_BACKGROUND_PENDING 0x00080000 /* pending in continous tx background due to out of skb */
#define WIFI_MP_CTX_CCK_HW 0x00100000 // in continous tx #define WIFI_MP_CTX_CCK_HW 0x00100000 /* in continous tx */
#define WIFI_MP_CTX_CCK_CS 0x00200000 // in continous tx with carrier suppression #define WIFI_MP_CTX_CCK_CS 0x00200000 /* in continous tx with carrier suppression */
#define WIFI_MP_LPBK_STATE 0x00400000 #define WIFI_MP_LPBK_STATE 0x00400000
//#endif
//#define _FW_UNDER_CMD WIFI_UNDER_CMD /* define _FW_UNDER_CMD WIFI_UNDER_CMD */
#define _FW_UNDER_LINKING WIFI_UNDER_LINKING #define _FW_UNDER_LINKING WIFI_UNDER_LINKING
#define _FW_LINKED WIFI_ASOC_STATE #define _FW_LINKED WIFI_ASOC_STATE
#define _FW_UNDER_SURVEY WIFI_SITE_MONITOR #define _FW_UNDER_SURVEY WIFI_SITE_MONITOR
@ -101,7 +92,7 @@ enum dot11AuthAlgrthmNum {
dot11AuthAlgrthm_MaxNum dot11AuthAlgrthm_MaxNum
}; };
// Scan type including active and passive scan. /* Scan type including active and passive scan. */
typedef enum _RT_SCAN_TYPE typedef enum _RT_SCAN_TYPE
{ {
SCAN_PASSIVE, SCAN_PASSIVE,
@ -123,10 +114,10 @@ enum DriverInterface {
enum SCAN_RESULT_TYPE enum SCAN_RESULT_TYPE
{ {
SCAN_RESULT_P2P_ONLY = 0, // Will return all the P2P devices. SCAN_RESULT_P2P_ONLY = 0, /* Will return all the P2P devices. */
SCAN_RESULT_ALL = 1, // Will return all the scanned device, include AP. SCAN_RESULT_ALL = 1, /* Will return all the scanned device, include AP. */
SCAN_RESULT_WFD_TYPE = 2 // Will just return the correct WFD device. SCAN_RESULT_WFD_TYPE = 2 /* Will just return the correct WFD device. */
// If this device is Miracast sink device, it will just return all the Miracast source devices. /* If this device is Miracast sink device, it will just return all the Miracast source devices. */
}; };
/* /*
@ -162,9 +153,9 @@ typedef struct _RT_LINK_DETECT_T{
bool bBusyTraffic; bool bBusyTraffic;
bool bTxBusyTraffic; bool bTxBusyTraffic;
bool bRxBusyTraffic; bool bRxBusyTraffic;
bool bHigherBusyTraffic; // For interrupt migration purpose. bool bHigherBusyTraffic; /* For interrupt migration purpose. */
bool bHigherBusyRxTraffic; // We may disable Tx interrupt according as Rx traffic. bool bHigherBusyRxTraffic; /* We may disable Tx interrupt according as Rx traffic. */
bool bHigherBusyTxTraffic; // We may disable Tx interrupt according as Tx traffic. bool bHigherBusyTxTraffic; /* We may disable Tx interrupt according as Tx traffic. */
}RT_LINK_DETECT_T, *PRT_LINK_DETECT_T; }RT_LINK_DETECT_T, *PRT_LINK_DETECT_T;
struct profile_info { struct profile_info {
@ -180,72 +171,72 @@ struct tx_invite_req_info{
u8 ssidlen; u8 ssidlen;
u8 go_bssid[ ETH_ALEN ]; u8 go_bssid[ ETH_ALEN ];
u8 peer_macaddr[ ETH_ALEN ]; u8 peer_macaddr[ ETH_ALEN ];
u8 operating_ch; // This information will be set by using the p2p_set op_ch=x u8 operating_ch; /* This information will be set by using the p2p_set op_ch=x */
u8 peer_ch; // The listen channel for peer P2P device u8 peer_ch; /* The listen channel for peer P2P device */
}; };
struct tx_invite_resp_info{ struct tx_invite_resp_info{
u8 token; // Used to record the dialog token of p2p invitation request frame. u8 token; /* Used to record the dialog token of p2p invitation request frame. */
}; };
#ifdef CONFIG_P2P #ifdef CONFIG_P2P
struct wifi_display_info{ struct wifi_display_info{
u16 wfd_enable; // Eanble/Disable the WFD function. u16 wfd_enable; /* Eanble/Disable the WFD function. */
u16 rtsp_ctrlport; // TCP port number at which the this WFD device listens for RTSP messages u16 rtsp_ctrlport; /* TCP port number at which the this WFD device listens for RTSP messages */
u16 peer_rtsp_ctrlport; // TCP port number at which the peer WFD device listens for RTSP messages u16 peer_rtsp_ctrlport; /* TCP port number at which the peer WFD device listens for RTSP messages */
// This filed should be filled when receiving the gropu negotiation request /* This filed should be filled when receiving the gropu negotiation request */
u8 peer_session_avail; // WFD session is available or not for the peer wfd device. u8 peer_session_avail; /* WFD session is available or not for the peer wfd device. */
// This variable will be set when sending the provisioning discovery request to peer WFD device. /* This variable will be set when sending the provisioning discovery request to peer WFD device. */
// And this variable will be reset when it is read by using the iwpriv p2p_get wfd_sa command. /* And this variable will be reset when it is read by using the iwpriv p2p_get wfd_sa command. */
u8 ip_address[4]; u8 ip_address[4];
u8 peer_ip_address[4]; u8 peer_ip_address[4];
u8 wfd_pc; // WFD preferred connection u8 wfd_pc; /* WFD preferred connection */
// 0 -> Prefer to use the P2P for WFD connection on peer side. /* 0 -> Prefer to use the P2P for WFD connection on peer side. */
// 1 -> Prefer to use the TDLS for WFD connection on peer side. /* 1 -> Prefer to use the TDLS for WFD connection on peer side. */
u8 wfd_device_type; // WFD Device Type u8 wfd_device_type; /* WFD Device Type */
// 0 -> WFD Source Device /* 0 -> WFD Source Device */
// 1 -> WFD Primary Sink Device /* 1 -> WFD Primary Sink Device */
enum SCAN_RESULT_TYPE scan_result_type; // Used when P2P is enable. This parameter will impact the scan result. enum SCAN_RESULT_TYPE scan_result_type; /* Used when P2P is enable. This parameter will impact the scan result. */
}; };
#endif //CONFIG_P2P #endif /* CONFIG_P2P */
struct tx_provdisc_req_info{ struct tx_provdisc_req_info{
u16 wps_config_method_request; // Used when sending the provisioning request frame u16 wps_config_method_request; /* Used when sending the provisioning request frame */
u16 peer_channel_num[2]; // The channel number which the receiver stands. u16 peer_channel_num[2]; /* The channel number which the receiver stands. */
struct ndis_802_11_ssid ssid; struct ndis_802_11_ssid ssid;
u8 peerDevAddr[ ETH_ALEN ]; // Peer device address u8 peerDevAddr[ ETH_ALEN ]; /* Peer device address */
u8 peerIFAddr[ ETH_ALEN ]; // Peer interface address u8 peerIFAddr[ ETH_ALEN ]; /* Peer interface address */
u8 benable; // This provision discovery request frame is trigger to send or not u8 benable; /* This provision discovery request frame is trigger to send or not */
}; };
struct rx_provdisc_req_info{ //When peer device issue prov_disc_req first, we should store the following informations struct rx_provdisc_req_info{ /* When peer device issue prov_disc_req first, we should store the following informations */
u8 peerDevAddr[ ETH_ALEN ]; // Peer device address u8 peerDevAddr[ ETH_ALEN ]; /* Peer device address */
u8 strconfig_method_desc_of_prov_disc_req[4]; // description for the config method located in the provisioning discovery request frame. u8 strconfig_method_desc_of_prov_disc_req[4]; /* description for the config method located in the provisioning discovery request frame. */
// The UI must know this information to know which config method the remote p2p device is requiring. /* The UI must know this information to know which config method the remote p2p device is requiring. */
}; };
struct tx_nego_req_info{ struct tx_nego_req_info{
u16 peer_channel_num[2]; // The channel number which the receiver stands. u16 peer_channel_num[2]; /* The channel number which the receiver stands. */
u8 peerDevAddr[ ETH_ALEN ]; // Peer device address u8 peerDevAddr[ ETH_ALEN ]; /* Peer device address */
u8 benable; // This negoitation request frame is trigger to send or not u8 benable; /* This negoitation request frame is trigger to send or not */
}; };
struct group_id_info{ struct group_id_info{
u8 go_device_addr[ ETH_ALEN ]; // The GO's device address of this P2P group u8 go_device_addr[ ETH_ALEN ]; /* The GO's device address of this P2P group */
u8 ssid[ WLAN_SSID_MAXLEN ]; // The SSID of this P2P group u8 ssid[ WLAN_SSID_MAXLEN ]; /* The SSID of this P2P group */
}; };
struct scan_limit_info{ struct scan_limit_info{
u8 scan_op_ch_only; // When this flag is set, the driver should just scan the operation channel u8 scan_op_ch_only; /* When this flag is set, the driver should just scan the operation channel */
#ifndef CONFIG_P2P #ifndef CONFIG_P2P
u8 operation_ch[2]; // Store the operation channel of invitation request frame u8 operation_ch[2]; /* Store the operation channel of invitation request frame */
#else #else
u8 operation_ch[5]; // Store additional channel 1,6,11 for Android 4.2 IOT & Nexus 4 u8 operation_ch[5]; /* Store additional channel 1,6,11 for Android 4.2 IOT & Nexus 4 */
#endif //CONFIG_P2P #endif /* CONFIG_P2P */
}; };
struct cfg80211_wifidirect_info{ struct cfg80211_wifidirect_info{
@ -262,105 +253,105 @@ struct wifidirect_info{
struct timer_list find_phase_timer; struct timer_list find_phase_timer;
struct timer_list restore_p2p_state_timer; struct timer_list restore_p2p_state_timer;
// Used to do the scanning. After confirming the peer is availalble, the driver transmits the P2P frame to peer. /* Used to do the scanning. After confirming the peer is availalble, the driver transmits the P2P frame to peer. */
struct timer_list pre_tx_scan_timer; struct timer_list pre_tx_scan_timer;
struct timer_list reset_ch_sitesurvey; struct timer_list reset_ch_sitesurvey;
struct timer_list reset_ch_sitesurvey2; // Just for resetting the scan limit function by using p2p nego struct timer_list reset_ch_sitesurvey2; /* Just for resetting the scan limit function by using p2p nego */
struct tx_provdisc_req_info tx_prov_disc_info; struct tx_provdisc_req_info tx_prov_disc_info;
struct rx_provdisc_req_info rx_prov_disc_info; struct rx_provdisc_req_info rx_prov_disc_info;
struct tx_invite_req_info invitereq_info; struct tx_invite_req_info invitereq_info;
struct profile_info profileinfo[ P2P_MAX_PERSISTENT_GROUP_NUM ]; // Store the profile information of persistent group struct profile_info profileinfo[ P2P_MAX_PERSISTENT_GROUP_NUM ]; /* Store the profile information of persistent group */
struct tx_invite_resp_info inviteresp_info; struct tx_invite_resp_info inviteresp_info;
struct tx_nego_req_info nego_req_info; struct tx_nego_req_info nego_req_info;
struct group_id_info groupid_info; // Store the group id information when doing the group negotiation handshake. struct group_id_info groupid_info; /* Store the group id information when doing the group negotiation handshake. */
struct scan_limit_info rx_invitereq_info; // Used for get the limit scan channel from the Invitation procedure struct scan_limit_info rx_invitereq_info; /* Used for get the limit scan channel from the Invitation procedure */
struct scan_limit_info p2p_info; // Used for get the limit scan channel from the P2P negotiation handshake struct scan_limit_info p2p_info; /* Used for get the limit scan channel from the P2P negotiation handshake */
#ifdef CONFIG_P2P #ifdef CONFIG_P2P
struct wifi_display_info *wfd_info; struct wifi_display_info *wfd_info;
#endif #endif
enum P2P_ROLE role; enum P2P_ROLE role;
enum P2P_STATE pre_p2p_state; enum P2P_STATE pre_p2p_state;
enum P2P_STATE p2p_state; enum P2P_STATE p2p_state;
u8 device_addr[ETH_ALEN]; // The device address should be the mac address of this device. u8 device_addr[ETH_ALEN]; /* The device address should be the mac address of this device. */
u8 interface_addr[ETH_ALEN]; u8 interface_addr[ETH_ALEN];
u8 social_chan[4]; u8 social_chan[4];
u8 listen_channel; u8 listen_channel;
u8 operating_channel; u8 operating_channel;
u8 listen_dwell; // This value should be between 1 and 3 u8 listen_dwell; /* This value should be between 1 and 3 */
u8 support_rate[8]; u8 support_rate[8];
u8 p2p_wildcard_ssid[P2P_WILDCARD_SSID_LEN]; u8 p2p_wildcard_ssid[P2P_WILDCARD_SSID_LEN];
u8 intent; // should only include the intent value. u8 intent; /* should only include the intent value. */
u8 p2p_peer_interface_addr[ ETH_ALEN ]; u8 p2p_peer_interface_addr[ ETH_ALEN ];
u8 p2p_peer_device_addr[ ETH_ALEN ]; u8 p2p_peer_device_addr[ ETH_ALEN ];
u8 peer_intent; // Included the intent value and tie breaker value. u8 peer_intent; /* Included the intent value and tie breaker value. */
u8 device_name[ WPS_MAX_DEVICE_NAME_LEN ]; // Device name for displaying on searching device screen u8 device_name[ WPS_MAX_DEVICE_NAME_LEN ]; /* Device name for displaying on searching device screen */
u8 device_name_len; u8 device_name_len;
u8 profileindex; // Used to point to the index of profileinfo array u8 profileindex; /* Used to point to the index of profileinfo array */
u8 peer_operating_ch; u8 peer_operating_ch;
u8 find_phase_state_exchange_cnt; u8 find_phase_state_exchange_cnt;
u16 device_password_id_for_nego; // The device password ID for group negotation u16 device_password_id_for_nego; /* The device password ID for group negotation */
u8 negotiation_dialog_token; u8 negotiation_dialog_token;
u8 nego_ssid[ WLAN_SSID_MAXLEN ]; // SSID information for group negotitation u8 nego_ssid[ WLAN_SSID_MAXLEN ]; /* SSID information for group negotitation */
u8 nego_ssidlen; u8 nego_ssidlen;
u8 p2p_group_ssid[WLAN_SSID_MAXLEN]; u8 p2p_group_ssid[WLAN_SSID_MAXLEN];
u8 p2p_group_ssid_len; u8 p2p_group_ssid_len;
u8 persistent_supported; // Flag to know the persistent function should be supported or not. u8 persistent_supported; /* Flag to know the persistent function should be supported or not. */
// In the Sigma test, the Sigma will provide this enable from the sta_set_p2p CAPI. /* In the Sigma test, the Sigma will provide this enable from the sta_set_p2p CAPI. */
// 0: disable /* 0: disable */
// 1: enable /* 1: enable */
u8 session_available; // Flag to set the WFD session available to enable or disable "by Sigma" u8 session_available; /* Flag to set the WFD session available to enable or disable "by Sigma" */
// In the Sigma test, the Sigma will disable the session available by using the sta_preset CAPI. /* In the Sigma test, the Sigma will disable the session available by using the sta_preset CAPI. */
// 0: disable /* 0: disable */
// 1: enable /* 1: enable */
u8 wfd_tdls_enable; // Flag to enable or disable the TDLS by WFD Sigma u8 wfd_tdls_enable; /* Flag to enable or disable the TDLS by WFD Sigma */
// 0: disable /* 0: disable */
// 1: enable /* 1: enable */
u8 wfd_tdls_weaksec; // Flag to enable or disable the weak security function for TDLS by WFD Sigma u8 wfd_tdls_weaksec; /* Flag to enable or disable the weak security function for TDLS by WFD Sigma */
// 0: disable /* 0: disable */
// In this case, the driver can't issue the tdsl setup request frame. /* In this case, the driver can't issue the tdsl setup request frame. */
// 1: enable /* 1: enable */
// In this case, the driver can issue the tdls setup request frame /* In this case, the driver can issue the tdls setup request frame */
// even the current security is weak security. /* even the current security is weak security. */
enum P2P_WPSINFO ui_got_wps_info; // This field will store the WPS value (PIN value or PBC) that UI had got from the user. enum P2P_WPSINFO ui_got_wps_info; /* This field will store the WPS value (PIN value or PBC) that UI had got from the user. */
u16 supported_wps_cm; // This field describes the WPS config method which this driver supported. u16 supported_wps_cm; /* This field describes the WPS config method which this driver supported. */
// The value should be the combination of config method defined in page104 of WPS v2.0 spec. /* The value should be the combination of config method defined in page104 of WPS v2.0 spec. */
u8 external_uuid; // UUID flag u8 external_uuid; /* UUID flag */
u8 uuid[16]; // UUID u8 uuid[16]; /* UUID */
uint channel_list_attr_len; // This field will contain the length of body of P2P Channel List attribute of group negotitation response frame. uint channel_list_attr_len; /* This field will contain the length of body of P2P Channel List attribute of group negotitation response frame. */
u8 channel_list_attr[100]; // This field will contain the body of P2P Channel List attribute of group negotitation response frame. u8 channel_list_attr[100]; /* This field will contain the body of P2P Channel List attribute of group negotitation response frame. */
// We will use the channel_cnt and channel_list fields when constructing the group negotitation confirm frame. /* We will use the channel_cnt and channel_list fields when constructing the group negotitation confirm frame. */
u8 driver_interface; // Indicate DRIVER_WEXT or DRIVER_CFG80211 u8 driver_interface; /* Indicate DRIVER_WEXT or DRIVER_CFG80211 */
#ifdef CONFIG_P2P #ifdef CONFIG_P2P
enum P2P_PS_MODE p2p_ps_mode; // indicate p2p ps mode enum P2P_PS_MODE p2p_ps_mode; /* indicate p2p ps mode */
enum P2P_PS_STATE p2p_ps_state; // indicate p2p ps state enum P2P_PS_STATE p2p_ps_state; /* indicate p2p ps state */
u8 noa_index; // Identifies and instance of Notice of Absence timing. u8 noa_index; /* Identifies and instance of Notice of Absence timing. */
u8 ctwindow; // Client traffic window. A period of time in TU after TBTT. u8 ctwindow; /* Client traffic window. A period of time in TU after TBTT. */
u8 opp_ps; // opportunistic power save. u8 opp_ps; /* opportunistic power save. */
u8 noa_num; // number of NoA descriptor in P2P IE. u8 noa_num; /* number of NoA descriptor in P2P IE. */
u8 noa_count[P2P_MAX_NOA_NUM]; // Count for owner, Type of client. u8 noa_count[P2P_MAX_NOA_NUM]; /* Count for owner, Type of client. */
u32 noa_duration[P2P_MAX_NOA_NUM]; // Max duration for owner, preferred or min acceptable duration for client. u32 noa_duration[P2P_MAX_NOA_NUM]; /* Max duration for owner, preferred or min acceptable duration for client. */
u32 noa_interval[P2P_MAX_NOA_NUM]; // Length of interval for owner, preferred or max acceptable interval of client. u32 noa_interval[P2P_MAX_NOA_NUM]; /* Length of interval for owner, preferred or max acceptable interval of client. */
u32 noa_start_time[P2P_MAX_NOA_NUM]; // schedule expressed in terms of the lower 4 bytes of the TSF timer. u32 noa_start_time[P2P_MAX_NOA_NUM]; /* schedule expressed in terms of the lower 4 bytes of the TSF timer. */
#endif // CONFIG_P2P #endif /* CONFIG_P2P */
}; };
struct tdls_ss_record{ //signal strength record struct tdls_ss_record{ /* signal strength record */
u8 macaddr[ETH_ALEN]; u8 macaddr[ETH_ALEN];
u8 RxPWDBAll; u8 RxPWDBAll;
u8 is_tdls_sta; // true: direct link sta, false: else u8 is_tdls_sta; /* true: direct link sta, false: else */
}; };
struct tdls_info{ struct tdls_info{
u8 ap_prohibited; u8 ap_prohibited;
uint setup_state; uint setup_state;
u8 sta_cnt; u8 sta_cnt;
u8 sta_maximum; // 1:tdls sta is equal (NUM_STA-1), reach max direct link number; 0: else; u8 sta_maximum; /* 1:tdls sta is equal (NUM_STA-1), reach max direct link number; 0: else; */
struct tdls_ss_record ss_record; struct tdls_ss_record ss_record;
u8 macid_index; //macid entry that is ready to write u8 macid_index; /* macid entry that is ready to write */
u8 clear_cam; //cam entry that is trying to clear, using it in direct link teardown u8 clear_cam; /* cam entry that is trying to clear, using it in direct link teardown */
u8 ch_sensing; u8 ch_sensing;
u8 cur_channel; u8 cur_channel;
u8 candidate_ch; u8 candidate_ch;
@ -368,7 +359,7 @@ struct tdls_info{
spinlock_t cmd_lock; spinlock_t cmd_lock;
spinlock_t hdl_lock; spinlock_t hdl_lock;
u8 watchdog_count; u8 watchdog_count;
u8 dev_discovered; //WFD_TDLS: for sigma test u8 dev_discovered; /* WFD_TDLS: for sigma test */
u8 enable; u8 enable;
#ifdef CONFIG_P2P #ifdef CONFIG_P2P
struct wifi_display_info *wfd_info; struct wifi_display_info *wfd_info;
@ -378,10 +369,10 @@ struct tdls_info{
struct mlme_priv { struct mlme_priv {
spinlock_t lock; spinlock_t lock;
sint fw_state; //shall we protect this variable? maybe not necessarily... sint fw_state; /* shall we protect this variable? maybe not necessarily... */
u8 bScanInProcess; u8 bScanInProcess;
u8 to_join; //flag u8 to_join; /* flag */
u8 to_roaming; // roaming trying times u8 to_roaming; /* roaming trying times */
u8 *nic_hdl; u8 *nic_hdl;
@ -398,12 +389,12 @@ struct mlme_priv {
struct wlan_network cur_network; struct wlan_network cur_network;
struct wlan_network *cur_network_scanned; struct wlan_network *cur_network_scanned;
#ifdef CONFIG_ARP_KEEP_ALIVE #ifdef CONFIG_ARP_KEEP_ALIVE
// for arp offload keep alive /* for arp offload keep alive */
u8 gw_mac_addr[6]; u8 gw_mac_addr[6];
u8 gw_ip[4]; u8 gw_ip[4];
#endif #endif
//uint wireless_mode; no used, remove it /* uint wireless_mode; no used, remove it */
u32 scan_interval; u32 scan_interval;
@ -412,11 +403,11 @@ struct mlme_priv {
uint assoc_by_bssid; uint assoc_by_bssid;
uint assoc_by_rssi; uint assoc_by_rssi;
struct timer_list scan_to_timer; // driver itself handles scan_timeout status. struct timer_list scan_to_timer; /* driver itself handles scan_timeout status. */
u32 scan_start_time; // used to evaluate the time spent in scanning u32 scan_start_time; /* used to evaluate the time spent in scanning */
struct timer_list set_scan_deny_timer; struct timer_list set_scan_deny_timer;
ATOMIC_T set_scan_deny; //0: allowed, 1: deny ATOMIC_T set_scan_deny; /* 0: allowed, 1: deny */
struct qos_priv qospriv; struct qos_priv qospriv;
@ -424,7 +415,7 @@ struct mlme_priv {
int num_sta_no_ht; int num_sta_no_ht;
/* Number of HT AP/stations 20 MHz */ /* Number of HT AP/stations 20 MHz */
//int num_sta_ht_20mhz; /* int num_sta_ht_20mhz; */
int num_FortyMHzIntolerant; int num_FortyMHzIntolerant;
@ -432,14 +423,12 @@ struct mlme_priv {
struct ht_priv htpriv; struct ht_priv htpriv;
RT_LINK_DETECT_T LinkDetectInfo; RT_LINK_DETECT_T LinkDetectInfo;
struct timer_list dynamic_chk_timer; //dynamic/periodic check timer struct timer_list dynamic_chk_timer; /* dynamic/periodic check timer */
u8 acm_mask; // for wmm acm mask u8 acm_mask; /* for wmm acm mask */
u8 ChannelPlan; u8 ChannelPlan;
RT_SCAN_TYPE scan_mode; // active: 1, passive: 0 RT_SCAN_TYPE scan_mode; /* active: 1, passive: 0 */
//u8 probereq_wpsie[MAX_WPS_IE_LEN];//added in probe req
//int probereq_wpsie_len;
u8 *wps_probe_req_ie; u8 *wps_probe_req_ie;
u32 wps_probe_req_ie_len; u32 wps_probe_req_ie_len;
@ -460,7 +449,7 @@ struct mlme_priv {
int num_sta_ht_no_gf; int num_sta_ht_no_gf;
/* Number of associated non-HT stations */ /* Number of associated non-HT stations */
//int num_sta_no_ht; /* int num_sta_no_ht; */
/* Number of HT associated stations 20 MHz */ /* Number of HT associated stations 20 MHz */
int num_sta_ht_20mhz; int num_sta_ht_20mhz;
@ -477,42 +466,42 @@ struct mlme_priv {
u8 *wps_beacon_ie; u8 *wps_beacon_ie;
u8 *wps_probe_resp_ie; u8 *wps_probe_resp_ie;
u8 *wps_assoc_resp_ie; // this IE includes p2p ie / wfd ie u8 *wps_assoc_resp_ie; /* this IE includes p2p ie / wfd ie */
u32 wps_beacon_ie_len; u32 wps_beacon_ie_len;
//u32 wps_probe_req_ie_len; /* u32 wps_probe_req_ie_len; */
u32 wps_probe_resp_ie_len; u32 wps_probe_resp_ie_len;
u32 wps_assoc_resp_ie_len; // this IE len includes p2p ie / wfd ie u32 wps_assoc_resp_ie_len; /* this IE len includes p2p ie / wfd ie */
u8 *p2p_beacon_ie; u8 *p2p_beacon_ie;
u8 *p2p_probe_req_ie; u8 *p2p_probe_req_ie;
u8 *p2p_probe_resp_ie; u8 *p2p_probe_resp_ie;
u8 *p2p_go_probe_resp_ie; //for GO u8 *p2p_go_probe_resp_ie; /* for GO */
u8 *p2p_assoc_req_ie; u8 *p2p_assoc_req_ie;
u32 p2p_beacon_ie_len; u32 p2p_beacon_ie_len;
u32 p2p_probe_req_ie_len; u32 p2p_probe_req_ie_len;
u32 p2p_probe_resp_ie_len; u32 p2p_probe_resp_ie_len;
u32 p2p_go_probe_resp_ie_len; //for GO u32 p2p_go_probe_resp_ie_len; /* for GO */
u32 p2p_assoc_req_ie_len; u32 p2p_assoc_req_ie_len;
spinlock_t bcn_update_lock; spinlock_t bcn_update_lock;
u8 update_bcn; u8 update_bcn;
#endif //#if defined (CONFIG_AP_MODE) #endif /* if defined (CONFIG_AP_MODE) */
#if defined(CONFIG_P2P) #if defined(CONFIG_P2P)
u8 *wfd_beacon_ie; u8 *wfd_beacon_ie;
u8 *wfd_probe_req_ie; u8 *wfd_probe_req_ie;
u8 *wfd_probe_resp_ie; u8 *wfd_probe_resp_ie;
u8 *wfd_go_probe_resp_ie; //for GO u8 *wfd_go_probe_resp_ie; /* for GO */
u8 *wfd_assoc_req_ie; u8 *wfd_assoc_req_ie;
u32 wfd_beacon_ie_len; u32 wfd_beacon_ie_len;
u32 wfd_probe_req_ie_len; u32 wfd_probe_req_ie_len;
u32 wfd_probe_resp_ie_len; u32 wfd_probe_resp_ie_len;
u32 wfd_go_probe_resp_ie_len; //for GO u32 wfd_go_probe_resp_ie_len; /* for GO */
u32 wfd_assoc_req_ie_len; u32 wfd_assoc_req_ie_len;
#endif #endif
}; };
@ -549,7 +538,7 @@ extern void rtw_join_timeout_handler(void* FunctionContext);
extern void _rtw_scan_timeout_handler(void* FunctionContext); extern void _rtw_scan_timeout_handler(void* FunctionContext);
extern void rtw_free_network_queue(struct adapter *adapter,u8 isfreeall); extern void rtw_free_network_queue(struct adapter *adapter,u8 isfreeall);
extern int rtw_init_mlme_priv(struct adapter *adapter);// (struct mlme_priv *pmlmepriv); extern int rtw_init_mlme_priv(struct adapter *adapter);/* (struct mlme_priv *pmlmepriv); */
extern void rtw_free_mlme_priv (struct mlme_priv *pmlmepriv); extern void rtw_free_mlme_priv (struct mlme_priv *pmlmepriv);
@ -559,8 +548,8 @@ extern sint rtw_set_key(struct adapter *adapter,struct security_priv *psecurityp
extern sint rtw_set_auth(struct adapter *adapter,struct security_priv *psecuritypriv); extern sint rtw_set_auth(struct adapter *adapter,struct security_priv *psecuritypriv);
__inline static u8 *get_bssid(struct mlme_priv *pmlmepriv) __inline static u8 *get_bssid(struct mlme_priv *pmlmepriv)
{ //if sta_mode:pmlmepriv->cur_network.network.MacAddress=> bssid { /* if sta_mode:pmlmepriv->cur_network.network.MacAddress=> bssid */
// if adhoc_mode:pmlmepriv->cur_network.network.MacAddress=> ibss mac address /* if adhoc_mode:pmlmepriv->cur_network.network.MacAddress=> ibss mac address */
return pmlmepriv->cur_network.network.MacAddress; return pmlmepriv->cur_network.network.MacAddress;
} }
@ -587,7 +576,7 @@ __inline static sint get_fwstate(struct mlme_priv *pmlmepriv)
__inline static void set_fwstate(struct mlme_priv *pmlmepriv, sint state) __inline static void set_fwstate(struct mlme_priv *pmlmepriv, sint state)
{ {
pmlmepriv->fw_state |= state; pmlmepriv->fw_state |= state;
//FOR HW integration /* FOR HW integration */
if(_FW_UNDER_SURVEY==state){ if(_FW_UNDER_SURVEY==state){
pmlmepriv->bScanInProcess = true; pmlmepriv->bScanInProcess = true;
} }
@ -596,7 +585,7 @@ __inline static void set_fwstate(struct mlme_priv *pmlmepriv, sint state)
__inline static void _clr_fwstate_(struct mlme_priv *pmlmepriv, sint state) __inline static void _clr_fwstate_(struct mlme_priv *pmlmepriv, sint state)
{ {
pmlmepriv->fw_state &= ~state; pmlmepriv->fw_state &= ~state;
//FOR HW integration /* FOR HW integration */
if(_FW_UNDER_SURVEY==state){ if(_FW_UNDER_SURVEY==state){
pmlmepriv->bScanInProcess = false; pmlmepriv->bScanInProcess = false;
} }
@ -722,6 +711,6 @@ void rtw_sta_media_status_rpt(struct adapter *adapter,struct sta_info *psta, u32
void rtw_proxim_enable(struct adapter *padapter); void rtw_proxim_enable(struct adapter *padapter);
void rtw_proxim_disable(struct adapter *padapter); void rtw_proxim_disable(struct adapter *padapter);
void rtw_proxim_send_packet(struct adapter *padapter,u8 *pbuf,u16 len,u8 hw_rate); void rtw_proxim_send_packet(struct adapter *padapter,u8 *pbuf,u16 len,u8 hw_rate);
#endif //CONFIG_INTEL_PROXIM #endif /* CONFIG_INTEL_PROXIM */
#endif //__RTL871X_MLME_H_ #endif /* __RTL871X_MLME_H_ */

178
include/rtw_mlme_ext.h
View file

@ -26,19 +26,19 @@
#include <wlan_bssdef.h> #include <wlan_bssdef.h>
// Commented by Albert 20101105 /* Commented by Albert 20101105 */
// Increase the SURVEY_TO value from 100 to 150 ( 100ms to 150ms ) /* Increase the SURVEY_TO value from 100 to 150 ( 100ms to 150ms ) */
// The Realtek 8188CE SoftAP will spend around 100ms to send the probe response after receiving the probe request. /* The Realtek 8188CE SoftAP will spend around 100ms to send the probe response after receiving the probe request. */
// So, this driver tried to extend the dwell time for each scanning channel. /* So, this driver tried to extend the dwell time for each scanning channel. */
// This will increase the chance to receive the probe response from SoftAP. /* This will increase the chance to receive the probe response from SoftAP. */
#define SURVEY_TO (100) #define SURVEY_TO (100)
#define REAUTH_TO (300) //(50) #define REAUTH_TO (300) /* 50) */
#define REASSOC_TO (300) //(50) #define REASSOC_TO (300) /* 50) */
//#define DISCONNECT_TO (3000) /* define DISCONNECT_TO (3000) */
#define ADDBA_TO (2000) #define ADDBA_TO (2000)
#define LINKED_TO (1) //unit:2 sec, 1x2=2 sec #define LINKED_TO (1) /* unit:2 sec, 1x2=2 sec */
#define REAUTH_LIMIT (4) #define REAUTH_LIMIT (4)
#define REASSOC_LIMIT (4) #define REASSOC_LIMIT (4)
@ -48,8 +48,8 @@
#define DYNAMIC_FUNC_DISABLE (0x0) #define DYNAMIC_FUNC_DISABLE (0x0)
// ====== ODM_ABILITY_E ======== /* ====== ODM_ABILITY_E ======== */
// BB ODM section BIT 0-15 /* BB ODM section BIT 0-15 */
#define DYNAMIC_BB_DIG BIT(0) #define DYNAMIC_BB_DIG BIT(0)
#define DYNAMIC_BB_RA_MASK BIT(1) #define DYNAMIC_BB_RA_MASK BIT(1)
#define DYNAMIC_BB_DYNAMIC_TXPWR BIT(2) #define DYNAMIC_BB_DYNAMIC_TXPWR BIT(2)
@ -64,11 +64,11 @@
#define DYNAMIC_BB_PATH_DIV BIT(10) #define DYNAMIC_BB_PATH_DIV BIT(10)
#define DYNAMIC_BB_PSD BIT(11) #define DYNAMIC_BB_PSD BIT(11)
// MAC DM section BIT 16-23 /* MAC DM section BIT 16-23 */
#define DYNAMIC_MAC_EDCA_TURBO BIT(16) #define DYNAMIC_MAC_EDCA_TURBO BIT(16)
#define DYNAMIC_MAC_EARLY_MODE BIT(17) #define DYNAMIC_MAC_EARLY_MODE BIT(17)
// RF ODM section BIT 24-31 /* RF ODM section BIT 24-31 */
#define DYNAMIC_RF_TX_PWR_TRACK BIT(24) #define DYNAMIC_RF_TX_PWR_TRACK BIT(24)
#define DYNAMIC_RF_RX_GAIN_TRACK BIT(25) #define DYNAMIC_RF_RX_GAIN_TRACK BIT(25)
#define DYNAMIC_RF_CALIBRATION BIT(26) #define DYNAMIC_RF_CALIBRATION BIT(26)
@ -105,16 +105,16 @@ extern unsigned char WMM_INFO_OUI[];
extern unsigned char WMM_PARA_OUI[]; extern unsigned char WMM_PARA_OUI[];
extern unsigned char REALTEK_96B_IE[]; extern unsigned char REALTEK_96B_IE[];
// /* */
// Channel Plan Type. /* Channel Plan Type. */
// Note: /* Note: */
// We just add new channel plan when the new channel plan is different from any of the following /* We just add new channel plan when the new channel plan is different from any of the following */
// channel plan. /* channel plan. */
// If you just wnat to customize the acitions(scan period or join actions) about one of the channel plan, /* If you just wnat to customize the acitions(scan period or join actions) about one of the channel plan, */
// customize them in struct rt_channel_info in the RT_CHANNEL_LIST. /* customize them in struct rt_channel_info in the RT_CHANNEL_LIST. */
// /* */
enum rt_channel_domain { enum rt_channel_domain {
//===== old channel plan mapping =====// /* old channel plan mapping ===== */
RT_CHANNEL_DOMAIN_FCC = 0x00, RT_CHANNEL_DOMAIN_FCC = 0x00,
RT_CHANNEL_DOMAIN_IC = 0x01, RT_CHANNEL_DOMAIN_IC = 0x01,
RT_CHANNEL_DOMAIN_ETSI = 0x02, RT_CHANNEL_DOMAIN_ETSI = 0x02,
@ -137,7 +137,7 @@ enum rt_channel_domain {
RT_CHANNEL_DOMAIN_WORLD_WIDE_5G = 0x13, RT_CHANNEL_DOMAIN_WORLD_WIDE_5G = 0x13,
RT_CHANNEL_DOMAIN_TAIWAN_NO_DFS = 0x14, RT_CHANNEL_DOMAIN_TAIWAN_NO_DFS = 0x14,
//===== new channel plan mapping, (2GDOMAIN_5GDOMAIN) =====// /* new channel plan mapping, (2GDOMAIN_5GDOMAIN) ===== */
RT_CHANNEL_DOMAIN_WORLD_NULL = 0x20, RT_CHANNEL_DOMAIN_WORLD_NULL = 0x20,
RT_CHANNEL_DOMAIN_ETSI1_NULL = 0x21, RT_CHANNEL_DOMAIN_ETSI1_NULL = 0x21,
RT_CHANNEL_DOMAIN_FCC1_NULL = 0x22, RT_CHANNEL_DOMAIN_FCC1_NULL = 0x22,
@ -160,42 +160,42 @@ enum rt_channel_domain {
RT_CHANNEL_DOMAIN_FCC1_NCC1 = 0x39, RT_CHANNEL_DOMAIN_FCC1_NCC1 = 0x39,
RT_CHANNEL_DOMAIN_FCC1_NCC2 = 0x40, RT_CHANNEL_DOMAIN_FCC1_NCC2 = 0x40,
RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN_2G = 0x41, RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN_2G = 0x41,
//===== Add new channel plan above this line===============// /* Add new channel plan above this line=============== */
RT_CHANNEL_DOMAIN_MAX, RT_CHANNEL_DOMAIN_MAX,
RT_CHANNEL_DOMAIN_REALTEK_DEFINE = 0x7F, RT_CHANNEL_DOMAIN_REALTEK_DEFINE = 0x7F,
}; };
enum RT_CHANNEL_DOMAIN_2G { enum RT_CHANNEL_DOMAIN_2G {
RT_CHANNEL_DOMAIN_2G_WORLD = 0x00, //Worldwird 13 RT_CHANNEL_DOMAIN_2G_WORLD = 0x00, /* Worldwird 13 */
RT_CHANNEL_DOMAIN_2G_ETSI1 = 0x01, //Europe RT_CHANNEL_DOMAIN_2G_ETSI1 = 0x01, /* Europe */
RT_CHANNEL_DOMAIN_2G_FCC1 = 0x02, //US RT_CHANNEL_DOMAIN_2G_FCC1 = 0x02, /* US */
RT_CHANNEL_DOMAIN_2G_MKK1 = 0x03, //Japan RT_CHANNEL_DOMAIN_2G_MKK1 = 0x03, /* Japan */
RT_CHANNEL_DOMAIN_2G_ETSI2 = 0x04, //France RT_CHANNEL_DOMAIN_2G_ETSI2 = 0x04, /* France */
RT_CHANNEL_DOMAIN_2G_NULL = 0x05, RT_CHANNEL_DOMAIN_2G_NULL = 0x05,
//===== Add new channel plan above this line===============// /* Add new channel plan above this line=============== */
RT_CHANNEL_DOMAIN_2G_MAX, RT_CHANNEL_DOMAIN_2G_MAX,
}; };
enum RT_CHANNEL_DOMAIN_5G { enum RT_CHANNEL_DOMAIN_5G {
RT_CHANNEL_DOMAIN_5G_NULL = 0x00, RT_CHANNEL_DOMAIN_5G_NULL = 0x00,
RT_CHANNEL_DOMAIN_5G_ETSI1 = 0x01, //Europe RT_CHANNEL_DOMAIN_5G_ETSI1 = 0x01, /* Europe */
RT_CHANNEL_DOMAIN_5G_ETSI2 = 0x02, //Australia, New Zealand RT_CHANNEL_DOMAIN_5G_ETSI2 = 0x02, /* Australia, New Zealand */
RT_CHANNEL_DOMAIN_5G_ETSI3 = 0x03, //Russia RT_CHANNEL_DOMAIN_5G_ETSI3 = 0x03, /* Russia */
RT_CHANNEL_DOMAIN_5G_FCC1 = 0x04, //US RT_CHANNEL_DOMAIN_5G_FCC1 = 0x04, /* US */
RT_CHANNEL_DOMAIN_5G_FCC2 = 0x05, //FCC o/w DFS Channels RT_CHANNEL_DOMAIN_5G_FCC2 = 0x05, /* FCC o/w DFS Channels */
RT_CHANNEL_DOMAIN_5G_FCC3 = 0x06, //India, Mexico RT_CHANNEL_DOMAIN_5G_FCC3 = 0x06, /* India, Mexico */
RT_CHANNEL_DOMAIN_5G_FCC4 = 0x07, //Venezuela RT_CHANNEL_DOMAIN_5G_FCC4 = 0x07, /* Venezuela */
RT_CHANNEL_DOMAIN_5G_FCC5 = 0x08, //China RT_CHANNEL_DOMAIN_5G_FCC5 = 0x08, /* China */
RT_CHANNEL_DOMAIN_5G_FCC6 = 0x09, //Israel RT_CHANNEL_DOMAIN_5G_FCC6 = 0x09, /* Israel */
RT_CHANNEL_DOMAIN_5G_FCC7_IC1 = 0x0A, //US, Canada RT_CHANNEL_DOMAIN_5G_FCC7_IC1 = 0x0A, /* US, Canada */
RT_CHANNEL_DOMAIN_5G_KCC1 = 0x0B, //Korea RT_CHANNEL_DOMAIN_5G_KCC1 = 0x0B, /* Korea */
RT_CHANNEL_DOMAIN_5G_MKK1 = 0x0C, //Japan RT_CHANNEL_DOMAIN_5G_MKK1 = 0x0C, /* Japan */
RT_CHANNEL_DOMAIN_5G_MKK2 = 0x0D, //Japan (W52, W53) RT_CHANNEL_DOMAIN_5G_MKK2 = 0x0D, /* Japan (W52, W53) */
RT_CHANNEL_DOMAIN_5G_MKK3 = 0x0E, //Japan (W56) RT_CHANNEL_DOMAIN_5G_MKK3 = 0x0E, /* Japan (W56) */
RT_CHANNEL_DOMAIN_5G_NCC1 = 0x0F, //Taiwan RT_CHANNEL_DOMAIN_5G_NCC1 = 0x0F, /* Taiwan */
RT_CHANNEL_DOMAIN_5G_NCC2 = 0x10, //Taiwan o/w DFS RT_CHANNEL_DOMAIN_5G_NCC2 = 0x10, /* Taiwan o/w DFS */
//===== Add new channel plan above this line===============// /* Add new channel plan above this line=============== */
//===== Driver Self Defined =====// /* Driver Self Defined ===== */
RT_CHANNEL_DOMAIN_5G_FCC = 0x11, RT_CHANNEL_DOMAIN_5G_FCC = 0x11,
RT_CHANNEL_DOMAIN_5G_JAPAN_NO_DFS = 0x12, RT_CHANNEL_DOMAIN_5G_JAPAN_NO_DFS = 0x12,
RT_CHANNEL_DOMAIN_5G_FCC4_NO_DFS = 0x13, RT_CHANNEL_DOMAIN_5G_FCC4_NO_DFS = 0x13,
@ -247,8 +247,8 @@ enum HT_IOT_PEER {
HT_IOT_PEER_CISCO = 6, HT_IOT_PEER_CISCO = 6,
HT_IOT_PEER_MERU = 7, HT_IOT_PEER_MERU = 7,
HT_IOT_PEER_MARVELL = 8, HT_IOT_PEER_MARVELL = 8,
HT_IOT_PEER_REALTEK_SOFTAP = 9,// peer is RealTek SOFT_AP, by Bohn, 2009.12.17 HT_IOT_PEER_REALTEK_SOFTAP = 9,/* peer is RealTek SOFT_AP, by Bohn, 2009.12.17 */
HT_IOT_PEER_SELF_SOFTAP = 10, // Self is SoftAP HT_IOT_PEER_SELF_SOFTAP = 10, /* Self is SoftAP */
HT_IOT_PEER_AIRGO = 11, HT_IOT_PEER_AIRGO = 11,
HT_IOT_PEER_INTEL = 12, HT_IOT_PEER_INTEL = 12,
HT_IOT_PEER_RTK_APCLIENT = 13, HT_IOT_PEER_RTK_APCLIENT = 13,
@ -339,10 +339,10 @@ struct mlme_ext_info {
u32 reassoc_count; u32 reassoc_count;
u32 link_count; u32 link_count;
u32 auth_seq; u32 auth_seq;
u32 auth_algo; // 802.11 auth, could be open, shared, auto u32 auth_algo; /* 802.11 auth, could be open, shared, auto */
u32 authModeToggle; u32 authModeToggle;
u32 enc_algo;//encrypt algorithm; u32 enc_algo;/* encrypt algorithm; */
u32 key_index; // this is only valid for legendary wep, 0~3 for key id. u32 key_index; /* this is only valid for legendary wep, 0~3 for key id. */
u32 iv; u32 iv;
u8 chg_txt[128]; u8 chg_txt[128];
u16 aid; u16 aid;
@ -365,7 +365,7 @@ struct mlme_ext_info {
u8 ADDBA_retry_count; u8 ADDBA_retry_count;
u8 candidate_tid_bitmap; u8 candidate_tid_bitmap;
u8 dialogToken; u8 dialogToken;
// Accept ADDBA Request /* Accept ADDBA Request */
bool bAcceptAddbaReq; bool bAcceptAddbaReq;
u8 bwmode_updated; u8 bwmode_updated;
u8 hidden_ssid_mode; u8 hidden_ssid_mode;
@ -374,14 +374,14 @@ struct mlme_ext_info {
struct WMM_para_element WMM_param; struct WMM_para_element WMM_param;
struct HT_caps_element HT_caps; struct HT_caps_element HT_caps;
struct HT_info_element HT_info; struct HT_info_element HT_info;
struct wlan_bssid_ex network;//join network or bss_network, if in ap mode, it is the same to cur_network.network struct wlan_bssid_ex network;/* join network or bss_network, if in ap mode, it is the same to cur_network.network */
struct FW_Sta_Info FW_sta_info[NUM_STA]; struct FW_Sta_Info FW_sta_info[NUM_STA];
}; };
// The channel information about this channel including joining, scanning, and power constraints. /* The channel information about this channel including joining, scanning, and power constraints. */
struct rt_channel_info { struct rt_channel_info {
u8 ChannelNum; // The channel number. u8 ChannelNum; /* The channel number. */
RT_SCAN_TYPE ScanType; // Scan type such as passive or active scan. RT_SCAN_TYPE ScanType; /* Scan type such as passive or active scan. */
#ifdef CONFIG_AP_MODE #ifdef CONFIG_AP_MODE
u32 rx_count; u32 rx_count;
#endif #endif
@ -389,27 +389,27 @@ struct rt_channel_info {
int rtw_ch_set_search_ch(struct rt_channel_info *ch_set, const u32 ch); int rtw_ch_set_search_ch(struct rt_channel_info *ch_set, const u32 ch);
// P2P_MAX_REG_CLASSES - Maximum number of regulatory classes /* P2P_MAX_REG_CLASSES - Maximum number of regulatory classes */
#define P2P_MAX_REG_CLASSES 10 #define P2P_MAX_REG_CLASSES 10
// P2P_MAX_REG_CLASS_CHANNELS - Maximum number of channels per regulatory class /* P2P_MAX_REG_CLASS_CHANNELS - Maximum number of channels per regulatory class */
#define P2P_MAX_REG_CLASS_CHANNELS 20 #define P2P_MAX_REG_CLASS_CHANNELS 20
// struct p2p_channels - List of supported channels /* struct p2p_channels - List of supported channels */
struct p2p_channels { struct p2p_channels {
// struct p2p_reg_class - Supported regulatory class /* struct p2p_reg_class - Supported regulatory class */
struct p2p_reg_class { struct p2p_reg_class {
// reg_class - Regulatory class (IEEE 802.11-2007, Annex J) /* reg_class - Regulatory class (IEEE 802.11-2007, Annex J) */
u8 reg_class; u8 reg_class;
// channel - Supported channels /* channel - Supported channels */
u8 channel[P2P_MAX_REG_CLASS_CHANNELS]; u8 channel[P2P_MAX_REG_CLASS_CHANNELS];
// channels - Number of channel entries in use /* channels - Number of channel entries in use */
size_t channels; size_t channels;
} reg_class[P2P_MAX_REG_CLASSES]; } reg_class[P2P_MAX_REG_CLASSES];
// reg_classes - Number of reg_class entries in use /* reg_classes - Number of reg_class entries in use */
size_t reg_classes; size_t reg_classes;
}; };
@ -432,11 +432,11 @@ struct mlme_ext_priv
u16 sa_query_seq; u16 sa_query_seq;
u64 mgnt_80211w_IPN; u64 mgnt_80211w_IPN;
u64 mgnt_80211w_IPN_rx; u64 mgnt_80211w_IPN_rx;
#endif //CONFIG_IEEE80211W #endif /* CONFIG_IEEE80211W */
unsigned char cur_channel; unsigned char cur_channel;
unsigned char cur_bwmode; unsigned char cur_bwmode;
unsigned char cur_ch_offset;//PRIME_CHNL_OFFSET unsigned char cur_ch_offset;/* PRIME_CHNL_OFFSET */
unsigned char cur_wireless_mode; // NETWORK_TYPE unsigned char cur_wireless_mode; /* NETWORK_TYPE */
unsigned char max_chan_nums; unsigned char max_chan_nums;
struct rt_channel_info channel_set[MAX_CHANNEL_NUM]; struct rt_channel_info channel_set[MAX_CHANNEL_NUM];
@ -445,19 +445,19 @@ struct mlme_ext_priv
unsigned char datarate[NumRates]; unsigned char datarate[NumRates];
struct ss_res sitesurvey_res; struct ss_res sitesurvey_res;
struct mlme_ext_info mlmext_info;//for sta/adhoc mode, including current scanning/connecting/connected related info. struct mlme_ext_info mlmext_info;/* for sta/adhoc mode, including current scanning/connecting/connected related info. */
//for ap mode, network includes ap's cap_info /* for ap mode, network includes ap's cap_info */
struct timer_list survey_timer; struct timer_list survey_timer;
struct timer_list link_timer; struct timer_list link_timer;
#ifdef CONFIG_IEEE80211W #ifdef CONFIG_IEEE80211W
struct timer_list sa_query_timer; struct timer_list sa_query_timer;
#endif //CONFIG_IEEE80211W #endif /* CONFIG_IEEE80211W */
u16 chan_scan_time; u16 chan_scan_time;
u8 scan_abort; u8 scan_abort;
u8 tx_rate; // TXRATE when USERATE is set. u8 tx_rate; /* TXRATE when USERATE is set. */
u32 retry; //retry for issue probereq u32 retry; /* retry for issue probereq */
u64 TSFValue; u64 TSFValue;
@ -468,7 +468,7 @@ struct mlme_ext_priv
#ifdef CONFIG_80211D #ifdef CONFIG_80211D
u8 update_channel_plan_by_ap_done; u8 update_channel_plan_by_ap_done;
#endif #endif
//recv_decache check for Action_public frame /* recv_decache check for Action_public frame */
u8 action_public_dialog_token; u8 action_public_dialog_token;
u16 action_public_rxseq; u16 action_public_rxseq;
@ -486,7 +486,7 @@ extern void init_addba_retry_timer(struct adapter *padapter, struct sta_info *ps
extern struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv); extern struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv);
struct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv); struct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv);
//void fill_fwpriv(struct adapter * padapter, struct fw_priv *pfwpriv); /* void fill_fwpriv(struct adapter * padapter, struct fw_priv *pfwpriv); */
unsigned char networktype_to_raid(unsigned char network_type); unsigned char networktype_to_raid(unsigned char network_type);
u8 judge_network_type(struct adapter *padapter, unsigned char *rate, int ratelen); u8 judge_network_type(struct adapter *padapter, unsigned char *rate, int ratelen);
@ -498,8 +498,8 @@ void Save_DM_Func_Flag(struct adapter *padapter);
void Restore_DM_Func_Flag(struct adapter *padapter); void Restore_DM_Func_Flag(struct adapter *padapter);
void Switch_DM_Func(struct adapter *padapter, u32 mode, u8 enable); void Switch_DM_Func(struct adapter *padapter, u32 mode, u8 enable);
//void Set_NETYPE1_MSR(struct adapter *padapter, u8 type); /* void Set_NETYPE1_MSR(struct adapter *padapter, u8 type); */
//void Set_NETYPE0_MSR(struct adapter *padapter, u8 type); /* void Set_NETYPE0_MSR(struct adapter *padapter, u8 type); */
void Set_MSR(struct adapter *padapter, u8 type); void Set_MSR(struct adapter *padapter, u8 type);
u8 rtw_get_oper_ch(struct adapter *adapter); u8 rtw_get_oper_ch(struct adapter *adapter);
@ -560,7 +560,7 @@ void update_beacon_info(struct adapter *padapter, u8 *pframe, uint len, struct s
int rtw_check_bcn_info(struct adapter *Adapter, u8 *pframe, u32 packet_len); int rtw_check_bcn_info(struct adapter *Adapter, u8 *pframe, u32 packet_len);
#ifdef CONFIG_DFS #ifdef CONFIG_DFS
void process_csa_ie(struct adapter *padapter, u8 *pframe, uint len); void process_csa_ie(struct adapter *padapter, u8 *pframe, uint len);
#endif //CONFIG_DFS #endif /* CONFIG_DFS */
void update_IOT_info(struct adapter *padapter); void update_IOT_info(struct adapter *padapter);
void update_capinfo(struct adapter *Adapter, u16 updateCap); void update_capinfo(struct adapter *Adapter, u16 updateCap);
void update_wireless_mode(struct adapter * padapter); void update_wireless_mode(struct adapter * padapter);
@ -568,7 +568,7 @@ void update_tx_basic_rate(struct adapter *padapter, u8 modulation);
void update_bmc_sta_support_rate(struct adapter *padapter, u32 mac_id); void update_bmc_sta_support_rate(struct adapter *padapter, u32 mac_id);
int update_sta_support_rate(struct adapter *padapter, u8* pvar_ie, uint var_ie_len, int cam_idx); int update_sta_support_rate(struct adapter *padapter, u8* pvar_ie, uint var_ie_len, int cam_idx);
//for sta/adhoc mode /* for sta/adhoc mode */
void update_sta_info(struct adapter *padapter, struct sta_info *psta); void update_sta_info(struct adapter *padapter, struct sta_info *psta);
unsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz); unsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz);
unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz); unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz);
@ -607,7 +607,7 @@ void issue_probereq_p2p(struct adapter *padapter, u8 *da);
int issue_probereq_p2p_ex(struct adapter *adapter, u8 *da, int try_cnt, int wait_ms); int issue_probereq_p2p_ex(struct adapter *adapter, u8 *da, int try_cnt, int wait_ms);
void issue_p2p_invitation_response(struct adapter *padapter, u8* raddr, u8 dialogToken, u8 success); void issue_p2p_invitation_response(struct adapter *padapter, u8* raddr, u8 dialogToken, u8 success);
void issue_p2p_invitation_request(struct adapter *padapter, u8* raddr ); void issue_p2p_invitation_request(struct adapter *padapter, u8* raddr );
#endif //CONFIG_P2P #endif /* CONFIG_P2P */
void issue_beacon(struct adapter *padapter, int timeout_ms); void issue_beacon(struct adapter *padapter, int timeout_ms);
void issue_probersp(struct adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq); void issue_probersp(struct adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq);
void issue_assocreq(struct adapter *padapter); void issue_assocreq(struct adapter *padapter);
@ -622,7 +622,7 @@ int issue_deauth_ex(struct adapter *padapter, u8 *da, unsigned short reason, int
void issue_action_spct_ch_switch(struct adapter *padapter, u8 *ra, u8 new_ch, u8 ch_offset); void issue_action_spct_ch_switch(struct adapter *padapter, u8 *ra, u8 new_ch, u8 ch_offset);
#ifdef CONFIG_IEEE80211W #ifdef CONFIG_IEEE80211W
void issue_action_SA_Query(struct adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short tid); void issue_action_SA_Query(struct adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short tid);
#endif //CONFIG_IEEE80211W #endif /* CONFIG_IEEE80211W */
unsigned int send_delba(struct adapter *padapter, u8 initiator, u8 *addr); unsigned int send_delba(struct adapter *padapter, u8 initiator, u8 *addr);
unsigned int send_beacon(struct adapter *padapter); unsigned int send_beacon(struct adapter *padapter);
@ -652,7 +652,7 @@ unsigned int on_action_public(struct adapter *padapter, union recv_frame *precv_
unsigned int OnAction_ht(struct adapter *padapter, union recv_frame *precv_frame); unsigned int OnAction_ht(struct adapter *padapter, union recv_frame *precv_frame);
#ifdef CONFIG_IEEE80211W #ifdef CONFIG_IEEE80211W
unsigned int OnAction_sa_query(struct adapter *padapter, union recv_frame *precv_frame); unsigned int OnAction_sa_query(struct adapter *padapter, union recv_frame *precv_frame);
#endif //CONFIG_IEEE80211W #endif /* CONFIG_IEEE80211W */
unsigned int OnAction_wmm(struct adapter *padapter, union recv_frame *precv_frame); unsigned int OnAction_wmm(struct adapter *padapter, union recv_frame *precv_frame);
unsigned int OnAction_p2p(struct adapter *padapter, union recv_frame *precv_frame); unsigned int OnAction_p2p(struct adapter *padapter, union recv_frame *precv_frame);
@ -668,7 +668,7 @@ void link_timer_hdl (struct adapter *padapter);
void addba_timer_hdl(struct sta_info *psta); void addba_timer_hdl(struct sta_info *psta);
#ifdef CONFIG_IEEE80211W #ifdef CONFIG_IEEE80211W
void sa_query_timer_hdl(struct adapter *padapter); void sa_query_timer_hdl(struct adapter *padapter);
#endif //CONFIG_IEEE80211W #endif /* CONFIG_IEEE80211W */
#define set_survey_timer(mlmeext, ms) \ #define set_survey_timer(mlmeext, ms) \
do { \ do { \
@ -685,7 +685,7 @@ void sa_query_timer_hdl(struct adapter *padapter);
DBG_871X("%s set_sa_query_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms)); \ DBG_871X("%s set_sa_query_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms)); \
_set_timer(&(mlmeext)->sa_query_timer, (ms)); \ _set_timer(&(mlmeext)->sa_query_timer, (ms)); \
} while(0) } while(0)
#endif //CONFIG_IEEE80211W #endif /* CONFIG_IEEE80211W */
extern int cckrates_included(unsigned char *rate, int ratelen); extern int cckrates_included(unsigned char *rate, int ratelen);
extern int cckratesonly_included(unsigned char *rate, int ratelen); extern int cckratesonly_included(unsigned char *rate, int ratelen);
@ -730,7 +730,7 @@ u8 tx_beacon_hdl(struct adapter *padapter, unsigned char *pbuf);
u8 set_ch_hdl(struct adapter *padapter, u8 *pbuf); u8 set_ch_hdl(struct adapter *padapter, u8 *pbuf);
u8 set_chplan_hdl(struct adapter *padapter, unsigned char *pbuf); u8 set_chplan_hdl(struct adapter *padapter, unsigned char *pbuf);
u8 led_blink_hdl(struct adapter *padapter, unsigned char *pbuf); u8 led_blink_hdl(struct adapter *padapter, unsigned char *pbuf);
u8 set_csa_hdl(struct adapter *padapter, unsigned char *pbuf); //Kurt: Handling DFS channel switch announcement ie. u8 set_csa_hdl(struct adapter *padapter, unsigned char *pbuf); /* Kurt: Handling DFS channel switch announcement ie. */
u8 tdls_hdl(struct adapter *padapter, unsigned char *pbuf); u8 tdls_hdl(struct adapter *padapter, unsigned char *pbuf);
@ -864,8 +864,8 @@ enum rtw_c2h_event
GEN_EVT_CODE(_C2HFEEDBACK), /*20*/ GEN_EVT_CODE(_C2HFEEDBACK), /*20*/
GEN_EVT_CODE(_ADDBA), GEN_EVT_CODE(_ADDBA),
GEN_EVT_CODE(_C2HBCN), GEN_EVT_CODE(_C2HBCN),
GEN_EVT_CODE(_ReportPwrState), //filen: only for PCIE, USB GEN_EVT_CODE(_ReportPwrState), /* filen: only for PCIE, USB */
GEN_EVT_CODE(_CloseRF), //filen: only for PCIE, work around ASPM GEN_EVT_CODE(_CloseRF), /* filen: only for PCIE, work around ASPM */
MAX_C2HEVT MAX_C2HEVT
}; };
@ -901,6 +901,6 @@ static struct fwevent wlanevents[] =
{0, &rtw_cpwm_event_callback}, {0, &rtw_cpwm_event_callback},
}; };
#endif//_RTL8192C_CMD_C_ #endif/* _RTL8192C_CMD_C_ */
#endif #endif

147
include/rtw_mp.h
View file

@ -20,8 +20,8 @@
#ifndef _RTW_MP_H_ #ifndef _RTW_MP_H_
#define _RTW_MP_H_ #define _RTW_MP_H_
// 00 - Success /* 00 - Success */
// 11 - Error /* 11 - Error */
#define STATUS_SUCCESS (0x00000000L) #define STATUS_SUCCESS (0x00000000L)
#define STATUS_PENDING (0x00000103L) #define STATUS_PENDING (0x00000103L)
@ -73,12 +73,12 @@
#define NDIS_STATUS_SAP_IN_USE ((NDIS_STATUS)0xC0010021L) #define NDIS_STATUS_SAP_IN_USE ((NDIS_STATUS)0xC0010021L)
#define NDIS_STATUS_INVALID_ADDRESS ((NDIS_STATUS)0xC0010022L) #define NDIS_STATUS_INVALID_ADDRESS ((NDIS_STATUS)0xC0010022L)
#define NDIS_STATUS_VC_NOT_ACTIVATED ((NDIS_STATUS)0xC0010023L) #define NDIS_STATUS_VC_NOT_ACTIVATED ((NDIS_STATUS)0xC0010023L)
#define NDIS_STATUS_DEST_OUT_OF_ORDER ((NDIS_STATUS)0xC0010024L) // cause 27 #define NDIS_STATUS_DEST_OUT_OF_ORDER ((NDIS_STATUS)0xC0010024L) /* cause 27 */
#define NDIS_STATUS_VC_NOT_AVAILABLE ((NDIS_STATUS)0xC0010025L) // cause 35,45 #define NDIS_STATUS_VC_NOT_AVAILABLE ((NDIS_STATUS)0xC0010025L) /* cause 35,45 */
#define NDIS_STATUS_CELLRATE_NOT_AVAILABLE ((NDIS_STATUS)0xC0010026L) // cause 37 #define NDIS_STATUS_CELLRATE_NOT_AVAILABLE ((NDIS_STATUS)0xC0010026L) /* cause 37 */
#define NDIS_STATUS_INCOMPATABLE_QOS ((NDIS_STATUS)0xC0010027L) // cause 49 #define NDIS_STATUS_INCOMPATABLE_QOS ((NDIS_STATUS)0xC0010027L) /* cause 49 */
#define NDIS_STATUS_AAL_PARAMS_UNSUPPORTED ((NDIS_STATUS)0xC0010028L) // cause 93 #define NDIS_STATUS_AAL_PARAMS_UNSUPPORTED ((NDIS_STATUS)0xC0010028L) /* cause 93 */
#define NDIS_STATUS_NO_ROUTE_TO_DESTINATION ((NDIS_STATUS)0xC0010029L) // cause 3 #define NDIS_STATUS_NO_ROUTE_TO_DESTINATION ((NDIS_STATUS)0xC0010029L) /* cause 3 */
typedef enum _ANTENNA_PATH{ typedef enum _ANTENNA_PATH{
ANTENNA_NONE = 0x00, ANTENNA_NONE = 0x00,
@ -115,8 +115,8 @@ struct mp_xmit_frame
struct adapter *padapter; struct adapter *padapter;
//insert urb, irp, and irpcnt info below... /* insert urb, irp, and irpcnt info below... */
//max frag_cnt = 8 /* max frag_cnt = 8 */
u8 *mem_addr; u8 *mem_addr;
u32 sz[8]; u32 sz[8];
@ -168,88 +168,87 @@ struct mp_tx
typedef void (*MPT_WORK_ITEM_HANDLER)(void * Adapter); typedef void (*MPT_WORK_ITEM_HANDLER)(void * Adapter);
typedef struct _MPT_CONTEXT typedef struct _MPT_CONTEXT
{ {
// Indicate if we have started Mass Production Test. /* Indicate if we have started Mass Production Test. */
bool bMassProdTest; bool bMassProdTest;
// Indicate if the driver is unloading or unloaded. /* Indicate if the driver is unloading or unloaded. */
bool bMptDrvUnload; bool bMptDrvUnload;
struct semaphore MPh2c_Sema; struct semaphore MPh2c_Sema;
struct timer_list MPh2c_timeout_timer; struct timer_list MPh2c_timeout_timer;
// Event used to sync H2c for BT control /* Event used to sync H2c for BT control */
bool MptH2cRspEvent; bool MptH2cRspEvent;
bool MptBtC2hEvent; bool MptBtC2hEvent;
bool bMPh2c_timeout; bool bMPh2c_timeout;
/* 8190 PCI does not support NDIS_WORK_ITEM. */ /* 8190 PCI does not support NDIS_WORK_ITEM. */
// Work Item for Mass Production Test. /* Work Item for Mass Production Test. */
//NDIS_WORK_ITEM MptWorkItem; /* NDIS_WORK_ITEM MptWorkItem; */
// RT_WORK_ITEM MptWorkItem; /* RT_WORK_ITEM MptWorkItem; */
// Event used to sync the case unloading driver and MptWorkItem is still in progress. /* Event used to sync the case unloading driver and MptWorkItem is still in progress. */
// NDIS_EVENT MptWorkItemEvent; /* NDIS_EVENT MptWorkItemEvent; */
// To protect the following variables. /* To protect the following variables. */
// NDIS_SPIN_LOCK MptWorkItemSpinLock; /* NDIS_SPIN_LOCK MptWorkItemSpinLock; */
// Indicate a MptWorkItem is scheduled and not yet finished. /* Indicate a MptWorkItem is scheduled and not yet finished. */
bool bMptWorkItemInProgress; bool bMptWorkItemInProgress;
// An instance which implements function and context of MptWorkItem. /* An instance which implements function and context of MptWorkItem. */
MPT_WORK_ITEM_HANDLER CurrMptAct; MPT_WORK_ITEM_HANDLER CurrMptAct;
// 1=Start, 0=Stop from UI. /* 1=Start, 0=Stop from UI. */
ULONG MptTestStart; ULONG MptTestStart;
// _TEST_MODE, defined in MPT_Req2.h /* _TEST_MODE, defined in MPT_Req2.h */
ULONG MptTestItem; ULONG MptTestItem;
// Variable needed in each implementation of CurrMptAct. /* Variable needed in each implementation of CurrMptAct. */
ULONG MptActType; // Type of action performed in CurrMptAct. ULONG MptActType; /* Type of action performed in CurrMptAct. */
// The Offset of IO operation is depend of MptActType. /* The Offset of IO operation is depend of MptActType. */
ULONG MptIoOffset; ULONG MptIoOffset;
// The Value of IO operation is depend of MptActType. /* The Value of IO operation is depend of MptActType. */
ULONG MptIoValue; ULONG MptIoValue;
// The RfPath of IO operation is depend of MptActType. /* The RfPath of IO operation is depend of MptActType. */
ULONG MptRfPath; ULONG MptRfPath;
WIRELESS_MODE MptWirelessModeToSw; // Wireless mode to switch. WIRELESS_MODE MptWirelessModeToSw; /* Wireless mode to switch. */
u8 MptChannelToSw; // Channel to switch. u8 MptChannelToSw; /* Channel to switch. */
u8 MptInitGainToSet; // Initial gain to set. u8 MptInitGainToSet; /* Initial gain to set. */
//ULONG bMptAntennaA; // true if we want to use antenna A. ULONG MptBandWidth; /* bandwidth to switch. */
ULONG MptBandWidth; // bandwidth to switch. ULONG MptRateIndex; /* rate index. */
ULONG MptRateIndex; // rate index. /* Register value kept for Single Carrier Tx test. */
// Register value kept for Single Carrier Tx test.
u8 btMpCckTxPower; u8 btMpCckTxPower;
// Register value kept for Single Carrier Tx test. /* Register value kept for Single Carrier Tx test. */
u8 btMpOfdmTxPower; u8 btMpOfdmTxPower;
// For MP Tx Power index /* For MP Tx Power index */
u8 TxPwrLevel[2]; // rf-A, rf-B u8 TxPwrLevel[2]; /* rf-A, rf-B */
// Content of RCR Regsiter for Mass Production Test. /* Content of RCR Regsiter for Mass Production Test. */
ULONG MptRCR; ULONG MptRCR;
// true if we only receive packets with specific pattern. /* true if we only receive packets with specific pattern. */
bool bMptFilterPattern; bool bMptFilterPattern;
// Rx OK count, statistics used in Mass Production Test. /* Rx OK count, statistics used in Mass Production Test. */
ULONG MptRxOkCnt; ULONG MptRxOkCnt;
// Rx CRC32 error count, statistics used in Mass Production Test. /* Rx CRC32 error count, statistics used in Mass Production Test. */
ULONG MptRxCrcErrCnt; ULONG MptRxCrcErrCnt;
bool bCckContTx; // true if we are in CCK Continuous Tx test. bool bCckContTx; /* true if we are in CCK Continuous Tx test. */
bool bOfdmContTx; // true if we are in OFDM Continuous Tx test. bool bOfdmContTx; /* true if we are in OFDM Continuous Tx test. */
bool bStartContTx; // true if we have start Continuous Tx test. bool bStartContTx; /* true if we have start Continuous Tx test. */
// true if we are in Single Carrier Tx test. /* true if we are in Single Carrier Tx test. */
bool bSingleCarrier; bool bSingleCarrier;
// true if we are in Carrier Suppression Tx Test. /* true if we are in Carrier Suppression Tx Test. */
bool bCarrierSuppression; bool bCarrierSuppression;
//true if we are in Single Tone Tx test. /* true if we are in Single Tone Tx test. */
bool bSingleTone; bool bSingleTone;
// ACK counter asked by K.Y.. /* ACK counter asked by K.Y.. */
bool bMptEnableAckCounter; bool bMptEnableAckCounter;
ULONG MptAckCounter; ULONG MptAckCounter;
// SD3 Willis For 8192S to save 1T/2T RF table for ACUT Only fro ACUT delete later ~~~! /* SD3 Willis For 8192S to save 1T/2T RF table for ACUT Only fro ACUT delete later ~~~! */
//s8 BufOfLines[2][MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; /* s8 BufOfLines[2][MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; */
//s8 BufOfLines[2][MP_MAX_LINES][MP_MAX_LINES_BYTES]; /* s8 BufOfLines[2][MP_MAX_LINES][MP_MAX_LINES_BYTES]; */
//s32 RfReadLine[2]; /* s32 RfReadLine[2]; */
u8 APK_bound[2]; //for APK path A/path B u8 APK_bound[2]; /* for APK path A/path B */
bool bMptIndexEven; bool bMptIndexEven;
u8 backup0xc50; u8 backup0xc50;
@ -304,28 +303,28 @@ enum {
struct mp_priv { struct mp_priv {
struct adapter *papdater; struct adapter *papdater;
//Testing Flag /* Testing Flag */
u32 mode;//0 for normal type packet, 1 for loopback packet (16bytes TXCMD) u32 mode;/* 0 for normal type packet, 1 for loopback packet (16bytes TXCMD) */
u32 prev_fw_state; u32 prev_fw_state;
//OID cmd handler /* OID cmd handler */
struct mp_wiparam workparam; struct mp_wiparam workparam;
// u8 act_in_progress; /* u8 act_in_progress; */
//Tx Section /* Tx Section */
u8 TID; u8 TID;
u32 tx_pktcount; u32 tx_pktcount;
struct mp_tx tx; struct mp_tx tx;
//Rx Section /* Rx Section */
u32 rx_pktcount; u32 rx_pktcount;
u32 rx_crcerrpktcount; u32 rx_crcerrpktcount;
u32 rx_pktloss; u32 rx_pktloss;
struct recv_stat rxstat; struct recv_stat rxstat;
//RF/BB relative /* RF/BB relative */
u8 channel; u8 channel;
u8 bandwidth; u8 bandwidth;
u8 prime_channel_offset; u8 prime_channel_offset;
@ -364,7 +363,7 @@ struct bb_reg_param {
u32 offset; u32 offset;
u32 value; u32 value;
}; };
//======================================================================= /* */
#define LOWER true #define LOWER true
#define RAISE false #define RAISE false
@ -430,7 +429,7 @@ typedef enum _MPT_RATE_INDEX
MPT_RATE_LAST MPT_RATE_LAST
}MPT_RATE_E, *PMPT_RATE_E; }MPT_RATE_E, *PMPT_RATE_E;
#define MAX_TX_PWR_INDEX_N_MODE 64 // 0x3F #define MAX_TX_PWR_INDEX_N_MODE 64 /* 0x3F */
typedef enum _POWER_MODE_ { typedef enum _POWER_MODE_ {
POWER_LOW = 0, POWER_LOW = 0,
@ -443,10 +442,10 @@ typedef enum _POWER_MODE_ {
#define RX_PKT_PHY_MATCH 3 #define RX_PKT_PHY_MATCH 3
typedef enum _ENCRY_CTRL_STATE_ { typedef enum _ENCRY_CTRL_STATE_ {
HW_CONTROL, //hw encryption& decryption HW_CONTROL, /* hw encryption& decryption */
SW_CONTROL, //sw encryption& decryption SW_CONTROL, /* sw encryption& decryption */
HW_ENCRY_SW_DECRY, //hw encryption & sw decryption HW_ENCRY_SW_DECRY, /* hw encryption & sw decryption */
SW_ENCRY_HW_DECRY //sw encryption & hw decryption SW_ENCRY_HW_DECRY /* sw encryption & hw decryption */
}ENCRY_CTRL_STATE; }ENCRY_CTRL_STATE;
#define Mac_OFDM_OK 0x00000000 #define Mac_OFDM_OK 0x00000000
@ -460,9 +459,9 @@ typedef enum _ENCRY_CTRL_STATE_ {
#define Mac_HT_FasleAlarm 0x90000000 #define Mac_HT_FasleAlarm 0x90000000
#define Mac_DropPacket 0xA0000000 #define Mac_DropPacket 0xA0000000
//======================================================================= /* */
//struct mp_xmit_frame *alloc_mp_xmitframe(struct mp_priv *pmp_priv); /* struct mp_xmit_frame *alloc_mp_xmitframe(struct mp_priv *pmp_priv); */
//int free_mp_xmitframe(struct xmit_priv *pxmitpriv, struct mp_xmit_frame *pmp_xmitframe); /* int free_mp_xmitframe(struct xmit_priv *pxmitpriv, struct mp_xmit_frame *pmp_xmitframe); */
s32 init_mp_priv(struct adapter *padapter); s32 init_mp_priv(struct adapter *padapter);
void free_mp_priv(struct mp_priv *pmp_priv); void free_mp_priv(struct mp_priv *pmp_priv);
@ -471,7 +470,7 @@ void MPT_DeInitAdapter(struct adapter *padapter);
s32 mp_start_test(struct adapter *padapter); s32 mp_start_test(struct adapter *padapter);
void mp_stop_test(struct adapter *padapter); void mp_stop_test(struct adapter *padapter);
//======================================================================= /* */
u32 _read_rfreg(struct adapter *padapter, u8 rfpath, u32 addr, u32 bitmask); u32 _read_rfreg(struct adapter *padapter, u8 rfpath, u32 addr, u32 bitmask);
void _write_rfreg(struct adapter *padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val); void _write_rfreg(struct adapter *padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val);
@ -492,7 +491,7 @@ void SetDataRate(struct adapter *pAdapter);
void SetAntenna(struct adapter *pAdapter); void SetAntenna(struct adapter *pAdapter);
//void SetCrystalCap(struct adapter *pAdapter); /* void SetCrystalCap(struct adapter *pAdapter); */
s32 SetThermalMeter(struct adapter *pAdapter, u8 target_ther); s32 SetThermalMeter(struct adapter *pAdapter, u8 target_ther);
void GetThermalMeter(struct adapter *pAdapter, u8 *value); void GetThermalMeter(struct adapter *pAdapter, u8 *value);
@ -550,4 +549,4 @@ void _rtw_mp_xmit_priv(struct xmit_priv *pxmitpriv);
void MP_PHY_SetRFPathSwitch(struct adapter *pAdapter ,bool bMain); void MP_PHY_SetRFPathSwitch(struct adapter *pAdapter ,bool bMain);
void MPT_PwrCtlDM(struct adapter *padapter, u32 bstart); void MPT_PwrCtlDM(struct adapter *padapter, u32 bstart);
#endif //_RTW_MP_H_ #endif /* _RTW_MP_H_ */

316
include/rtw_mp_ioctl.h
View file

@ -20,8 +20,8 @@
#ifndef _RTW_MP_IOCTL_H_ #ifndef _RTW_MP_IOCTL_H_
#define _RTW_MP_IOCTL_H_ #define _RTW_MP_IOCTL_H_
//#include <drv_conf.h> /* include <drv_conf.h> */
//#include <osdep_service.h> /* include <osdep_service.h> */
#include <drv_types.h> #include <drv_types.h>
#include <mp_custom_oid.h> #include <mp_custom_oid.h>
#include <rtw_ioctl.h> #include <rtw_ioctl.h>
@ -29,7 +29,7 @@
#include <rtw_efuse.h> #include <rtw_efuse.h>
#include <rtw_mp.h> #include <rtw_mp.h>
//------------------------------------------------------------------------------ /* */
typedef struct CFG_DBG_MSG_STRUCT { typedef struct CFG_DBG_MSG_STRUCT {
u32 DebugLevel; u32 DebugLevel;
u32 DebugComponent_H32; u32 DebugComponent_H32;
@ -42,7 +42,7 @@ typedef struct _RW_REG {
u32 value; u32 value;
}mp_rw_reg,RW_Reg, *pRW_Reg; }mp_rw_reg,RW_Reg, *pRW_Reg;
//for OID_RT_PRO_READ16_EEPROM & OID_RT_PRO_WRITE16_EEPROM /* for OID_RT_PRO_READ16_EEPROM & OID_RT_PRO_WRITE16_EEPROM */
typedef struct _EEPROM_RW_PARAM { typedef struct _EEPROM_RW_PARAM {
u32 offset; u32 offset;
u16 value; u16 value;
@ -65,7 +65,7 @@ typedef struct _USB_VendorReq{
u16 wValue; u16 wValue;
u16 wIndex; u16 wIndex;
u16 wLength; u16 wLength;
u8 u8Dir;//0:OUT, 1:IN u8 u8Dir;/* 0:OUT, 1:IN */
u8 u8InData; u8 u8InData;
}usb_vendor_req, USB_VendorReq, *pUSB_VendorReq; }usb_vendor_req, USB_VendorReq, *pUSB_VendorReq;
@ -74,18 +74,18 @@ typedef struct _DR_VARIABLE_STRUCT_ {
u32 variable; u32 variable;
}DR_VARIABLE_STRUCT; }DR_VARIABLE_STRUCT;
//int mp_start_joinbss(struct adapter *padapter, NDIS_802_11_SSID *pssid); /* int mp_start_joinbss(struct adapter *padapter, NDIS_802_11_SSID *pssid); */
#define _irqlevel_changed_(a,b) #define _irqlevel_changed_(a,b)
//oid_rtl_seg_81_80_00 /* oid_rtl_seg_81_80_00 */
NDIS_STATUS oid_rt_pro_set_data_rate_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_set_data_rate_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_start_test_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_start_test_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_stop_test_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_stop_test_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_set_channel_direct_call_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_set_channel_direct_call_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_set_antenna_bb_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_set_antenna_bb_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_set_tx_power_control_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_set_tx_power_control_hdl(struct oid_par_priv* poid_par_priv);
//oid_rtl_seg_81_80_20 /* oid_rtl_seg_81_80_20 */
NDIS_STATUS oid_rt_pro_query_tx_packet_sent_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_query_tx_packet_sent_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_query_rx_packet_received_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_query_rx_packet_received_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_query_rx_packet_crc32_error_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_query_rx_packet_crc32_error_hdl(struct oid_par_priv* poid_par_priv);
@ -100,7 +100,7 @@ NDIS_STATUS oid_rt_pro_set_carrier_suppression_tx_hdl(struct oid_par_priv* poid_
NDIS_STATUS oid_rt_pro_set_single_tone_tx_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_set_single_tone_tx_hdl(struct oid_par_priv* poid_par_priv);
//oid_rtl_seg_81_87 /* oid_rtl_seg_81_87 */
NDIS_STATUS oid_rt_pro_write_bb_reg_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_write_bb_reg_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_read_bb_reg_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_read_bb_reg_hdl(struct oid_par_priv* poid_par_priv);
@ -108,11 +108,11 @@ NDIS_STATUS oid_rt_pro_write_rf_reg_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_read_rf_reg_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_read_rf_reg_hdl(struct oid_par_priv* poid_par_priv);
//oid_rtl_seg_81_85 /* oid_rtl_seg_81_85 */
NDIS_STATUS oid_rt_wireless_mode_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_wireless_mode_hdl(struct oid_par_priv* poid_par_priv);
// oid_rtl_seg_87_11_00 /* oid_rtl_seg_87_11_00 */
NDIS_STATUS oid_rt_pro8711_join_bss_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro8711_join_bss_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_read_register_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_read_register_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_write_register_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_write_register_hdl(struct oid_par_priv* poid_par_priv);
@ -127,21 +127,21 @@ NDIS_STATUS oid_rt_rd_attrib_mem_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_wr_attrib_mem_hdl (struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_wr_attrib_mem_hdl (struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_set_rf_intfs_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_set_rf_intfs_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_poll_rx_status_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_poll_rx_status_hdl(struct oid_par_priv* poid_par_priv);
// oid_rtl_seg_87_11_20 /* oid_rtl_seg_87_11_20 */
NDIS_STATUS oid_rt_pro_cfg_debug_message_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_cfg_debug_message_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_set_data_rate_ex_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_set_data_rate_ex_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_set_basic_rate_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_set_basic_rate_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_read_tssi_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_read_tssi_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_set_power_tracking_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_set_power_tracking_hdl(struct oid_par_priv* poid_par_priv);
//oid_rtl_seg_87_11_50 /* oid_rtl_seg_87_11_50 */
NDIS_STATUS oid_rt_pro_qry_pwrstate_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_qry_pwrstate_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_set_pwrstate_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_set_pwrstate_hdl(struct oid_par_priv* poid_par_priv);
//oid_rtl_seg_87_11_F0 /* oid_rtl_seg_87_11_F0 */
NDIS_STATUS oid_rt_pro_h2c_set_rate_table_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_h2c_set_rate_table_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_h2c_get_rate_table_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_h2c_get_rate_table_hdl(struct oid_par_priv* poid_par_priv);
//oid_rtl_seg_87_12_00 /* oid_rtl_seg_87_12_00 */
NDIS_STATUS oid_rt_pro_encryption_ctrl_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_encryption_ctrl_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_add_sta_info_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_add_sta_info_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_dele_sta_info_hdl(struct oid_par_priv* poid_par_priv); NDIS_STATUS oid_rt_pro_dele_sta_info_hdl(struct oid_par_priv* poid_par_priv);
@ -179,201 +179,201 @@ NDIS_STATUS oid_rt_pro_trigger_gpio_hdl(struct oid_par_priv *poid_par_priv);
static const struct oid_obj_priv oid_rtl_seg_81_80_00[] = static const struct oid_obj_priv oid_rtl_seg_81_80_00[] =
{ {
{1, &oid_null_function}, //0x00 OID_RT_PRO_RESET_DUT {1, &oid_null_function}, /* 0x00 OID_RT_PRO_RESET_DUT */
{1, &oid_rt_pro_set_data_rate_hdl}, //0x01 {1, &oid_rt_pro_set_data_rate_hdl}, /* 0x01 */
{1, &oid_rt_pro_start_test_hdl}, //0x02 {1, &oid_rt_pro_start_test_hdl}, /* 0x02 */
{1, &oid_rt_pro_stop_test_hdl}, //0x03 {1, &oid_rt_pro_stop_test_hdl}, /* 0x03 */
{1, &oid_null_function}, //0x04 OID_RT_PRO_SET_PREAMBLE {1, &oid_null_function}, /* 0x04 OID_RT_PRO_SET_PREAMBLE */
{1, &oid_null_function}, //0x05 OID_RT_PRO_SET_SCRAMBLER {1, &oid_null_function}, /* 0x05 OID_RT_PRO_SET_SCRAMBLER */
{1, &oid_null_function}, //0x06 OID_RT_PRO_SET_FILTER_BB {1, &oid_null_function}, /* 0x06 OID_RT_PRO_SET_FILTER_BB */
{1, &oid_null_function}, //0x07 OID_RT_PRO_SET_MANUAL_DIVERSITY_BB {1, &oid_null_function}, /* 0x07 OID_RT_PRO_SET_MANUAL_DIVERSITY_BB */
{1, &oid_rt_pro_set_channel_direct_call_hdl}, //0x08 {1, &oid_rt_pro_set_channel_direct_call_hdl}, /* 0x08 */
{1, &oid_null_function}, //0x09 OID_RT_PRO_SET_SLEEP_MODE_DIRECT_CALL {1, &oid_null_function}, /* 0x09 OID_RT_PRO_SET_SLEEP_MODE_DIRECT_CALL */
{1, &oid_null_function}, //0x0A OID_RT_PRO_SET_WAKE_MODE_DIRECT_CALL {1, &oid_null_function}, /* 0x0A OID_RT_PRO_SET_WAKE_MODE_DIRECT_CALL */
{1, &oid_rt_pro_set_continuous_tx_hdl}, //0x0B OID_RT_PRO_SET_TX_CONTINUOUS_DIRECT_CALL {1, &oid_rt_pro_set_continuous_tx_hdl}, /* 0x0B OID_RT_PRO_SET_TX_CONTINUOUS_DIRECT_CALL */
{1, &oid_rt_pro_set_single_carrier_tx_hdl}, //0x0C OID_RT_PRO_SET_SINGLE_CARRIER_TX_CONTINUOUS {1, &oid_rt_pro_set_single_carrier_tx_hdl}, /* 0x0C OID_RT_PRO_SET_SINGLE_CARRIER_TX_CONTINUOUS */
{1, &oid_null_function}, //0x0D OID_RT_PRO_SET_TX_ANTENNA_BB {1, &oid_null_function}, /* 0x0D OID_RT_PRO_SET_TX_ANTENNA_BB */
{1, &oid_rt_pro_set_antenna_bb_hdl}, //0x0E {1, &oid_rt_pro_set_antenna_bb_hdl}, /* 0x0E */
{1, &oid_null_function}, //0x0F OID_RT_PRO_SET_CR_SCRAMBLER {1, &oid_null_function}, /* 0x0F OID_RT_PRO_SET_CR_SCRAMBLER */
{1, &oid_null_function}, //0x10 OID_RT_PRO_SET_CR_NEW_FILTER {1, &oid_null_function}, /* 0x10 OID_RT_PRO_SET_CR_NEW_FILTER */
{1, &oid_rt_pro_set_tx_power_control_hdl}, //0x11 OID_RT_PRO_SET_TX_POWER_CONTROL {1, &oid_rt_pro_set_tx_power_control_hdl}, /* 0x11 OID_RT_PRO_SET_TX_POWER_CONTROL */
{1, &oid_null_function}, //0x12 OID_RT_PRO_SET_CR_TX_CONFIG {1, &oid_null_function}, /* 0x12 OID_RT_PRO_SET_CR_TX_CONFIG */
{1, &oid_null_function}, //0x13 OID_RT_PRO_GET_TX_POWER_CONTROL {1, &oid_null_function}, /* 0x13 OID_RT_PRO_GET_TX_POWER_CONTROL */
{1, &oid_null_function}, //0x14 OID_RT_PRO_GET_CR_SIGNAL_QUALITY {1, &oid_null_function}, /* 0x14 OID_RT_PRO_GET_CR_SIGNAL_QUALITY */
{1, &oid_null_function}, //0x15 OID_RT_PRO_SET_CR_SETPOINT {1, &oid_null_function}, /* 0x15 OID_RT_PRO_SET_CR_SETPOINT */
{1, &oid_null_function}, //0x16 OID_RT_PRO_SET_INTEGRATOR {1, &oid_null_function}, /* 0x16 OID_RT_PRO_SET_INTEGRATOR */
{1, &oid_null_function}, //0x17 OID_RT_PRO_SET_SIGNAL_QUALITY {1, &oid_null_function}, /* 0x17 OID_RT_PRO_SET_SIGNAL_QUALITY */
{1, &oid_null_function}, //0x18 OID_RT_PRO_GET_INTEGRATOR {1, &oid_null_function}, /* 0x18 OID_RT_PRO_GET_INTEGRATOR */
{1, &oid_null_function}, //0x19 OID_RT_PRO_GET_SIGNAL_QUALITY {1, &oid_null_function}, /* 0x19 OID_RT_PRO_GET_SIGNAL_QUALITY */
{1, &oid_null_function}, //0x1A OID_RT_PRO_QUERY_EEPROM_TYPE {1, &oid_null_function}, /* 0x1A OID_RT_PRO_QUERY_EEPROM_TYPE */
{1, &oid_null_function}, //0x1B OID_RT_PRO_WRITE_MAC_ADDRESS {1, &oid_null_function}, /* 0x1B OID_RT_PRO_WRITE_MAC_ADDRESS */
{1, &oid_null_function}, //0x1C OID_RT_PRO_READ_MAC_ADDRESS {1, &oid_null_function}, /* 0x1C OID_RT_PRO_READ_MAC_ADDRESS */
{1, &oid_null_function}, //0x1D OID_RT_PRO_WRITE_CIS_DATA {1, &oid_null_function}, /* 0x1D OID_RT_PRO_WRITE_CIS_DATA */
{1, &oid_null_function}, //0x1E OID_RT_PRO_READ_CIS_DATA {1, &oid_null_function}, /* 0x1E OID_RT_PRO_READ_CIS_DATA */
{1, &oid_null_function} //0x1F OID_RT_PRO_WRITE_POWER_CONTROL {1, &oid_null_function} /* 0x1F OID_RT_PRO_WRITE_POWER_CONTROL */
}; };
static const struct oid_obj_priv oid_rtl_seg_81_80_20[] = static const struct oid_obj_priv oid_rtl_seg_81_80_20[] =
{ {
{1, &oid_null_function}, //0x20 OID_RT_PRO_READ_POWER_CONTROL {1, &oid_null_function}, /* 0x20 OID_RT_PRO_READ_POWER_CONTROL */
{1, &oid_null_function}, //0x21 OID_RT_PRO_WRITE_EEPROM {1, &oid_null_function}, /* 0x21 OID_RT_PRO_WRITE_EEPROM */
{1, &oid_null_function}, //0x22 OID_RT_PRO_READ_EEPROM {1, &oid_null_function}, /* 0x22 OID_RT_PRO_READ_EEPROM */
{1, &oid_rt_pro_reset_tx_packet_sent_hdl}, //0x23 {1, &oid_rt_pro_reset_tx_packet_sent_hdl}, /* 0x23 */
{1, &oid_rt_pro_query_tx_packet_sent_hdl}, //0x24 {1, &oid_rt_pro_query_tx_packet_sent_hdl}, /* 0x24 */
{1, &oid_rt_pro_reset_rx_packet_received_hdl}, //0x25 {1, &oid_rt_pro_reset_rx_packet_received_hdl}, /* 0x25 */
{1, &oid_rt_pro_query_rx_packet_received_hdl}, //0x26 {1, &oid_rt_pro_query_rx_packet_received_hdl}, /* 0x26 */
{1, &oid_rt_pro_query_rx_packet_crc32_error_hdl}, //0x27 {1, &oid_rt_pro_query_rx_packet_crc32_error_hdl}, /* 0x27 */
{1, &oid_null_function}, //0x28 OID_RT_PRO_QUERY_CURRENT_ADDRESS {1, &oid_null_function}, /* 0x28 OID_RT_PRO_QUERY_CURRENT_ADDRESS */
{1, &oid_null_function}, //0x29 OID_RT_PRO_QUERY_PERMANENT_ADDRESS {1, &oid_null_function}, /* 0x29 OID_RT_PRO_QUERY_PERMANENT_ADDRESS */
{1, &oid_null_function}, //0x2A OID_RT_PRO_SET_PHILIPS_RF_PARAMETERS {1, &oid_null_function}, /* 0x2A OID_RT_PRO_SET_PHILIPS_RF_PARAMETERS */
{1, &oid_rt_pro_set_carrier_suppression_tx_hdl},//0x2B OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX {1, &oid_rt_pro_set_carrier_suppression_tx_hdl},/* 0x2B OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX */
{1, &oid_null_function}, //0x2C OID_RT_PRO_RECEIVE_PACKET {1, &oid_null_function}, /* 0x2C OID_RT_PRO_RECEIVE_PACKET */
{1, &oid_null_function}, //0x2D OID_RT_PRO_WRITE_EEPROM_BYTE {1, &oid_null_function}, /* 0x2D OID_RT_PRO_WRITE_EEPROM_BYTE */
{1, &oid_null_function}, //0x2E OID_RT_PRO_READ_EEPROM_BYTE {1, &oid_null_function}, /* 0x2E OID_RT_PRO_READ_EEPROM_BYTE */
{1, &oid_rt_pro_set_modulation_hdl} //0x2F {1, &oid_rt_pro_set_modulation_hdl} /* 0x2F */
}; };
static const struct oid_obj_priv oid_rtl_seg_81_80_40[] = static const struct oid_obj_priv oid_rtl_seg_81_80_40[] =
{ {
{1, &oid_null_function}, //0x40 {1, &oid_null_function}, /* 0x40 */
{1, &oid_null_function}, //0x41 {1, &oid_null_function}, /* 0x41 */
{1, &oid_null_function}, //0x42 {1, &oid_null_function}, /* 0x42 */
{1, &oid_rt_pro_set_single_tone_tx_hdl}, //0x43 {1, &oid_rt_pro_set_single_tone_tx_hdl}, /* 0x43 */
{1, &oid_null_function}, //0x44 {1, &oid_null_function}, /* 0x44 */
{1, &oid_null_function} //0x45 {1, &oid_null_function} /* 0x45 */
}; };
static const struct oid_obj_priv oid_rtl_seg_81_80_80[] = static const struct oid_obj_priv oid_rtl_seg_81_80_80[] =
{ {
{1, &oid_null_function}, //0x80 OID_RT_DRIVER_OPTION {1, &oid_null_function}, /* 0x80 OID_RT_DRIVER_OPTION */
{1, &oid_null_function}, //0x81 OID_RT_RF_OFF {1, &oid_null_function}, /* 0x81 OID_RT_RF_OFF */
{1, &oid_null_function} //0x82 OID_RT_AUTH_STATUS {1, &oid_null_function} /* 0x82 OID_RT_AUTH_STATUS */
}; };
static const struct oid_obj_priv oid_rtl_seg_81_85[] = static const struct oid_obj_priv oid_rtl_seg_81_85[] =
{ {
{1, &oid_rt_wireless_mode_hdl} //0x00 OID_RT_WIRELESS_MODE {1, &oid_rt_wireless_mode_hdl} /* 0x00 OID_RT_WIRELESS_MODE */
}; };
static struct oid_obj_priv oid_rtl_seg_81_87[] = static struct oid_obj_priv oid_rtl_seg_81_87[] =
{ {
{1, &oid_null_function}, //0x80 OID_RT_PRO8187_WI_POLL {1, &oid_null_function}, /* 0x80 OID_RT_PRO8187_WI_POLL */
{1, &oid_rt_pro_write_bb_reg_hdl}, //0x81 {1, &oid_rt_pro_write_bb_reg_hdl}, /* 0x81 */
{1, &oid_rt_pro_read_bb_reg_hdl}, //0x82 {1, &oid_rt_pro_read_bb_reg_hdl}, /* 0x82 */
{1, &oid_rt_pro_write_rf_reg_hdl}, //0x82 {1, &oid_rt_pro_write_rf_reg_hdl}, /* 0x82 */
{1, &oid_rt_pro_read_rf_reg_hdl} //0x83 {1, &oid_rt_pro_read_rf_reg_hdl} /* 0x83 */
}; };
static struct oid_obj_priv oid_rtl_seg_87_11_00[] = static struct oid_obj_priv oid_rtl_seg_87_11_00[] =
{ {
{1, &oid_rt_pro8711_join_bss_hdl}, //0x00 //S {1, &oid_rt_pro8711_join_bss_hdl}, /* 0x00 S */
{1, &oid_rt_pro_read_register_hdl}, //0x01 {1, &oid_rt_pro_read_register_hdl}, /* 0x01 */
{1, &oid_rt_pro_write_register_hdl}, //0x02 {1, &oid_rt_pro_write_register_hdl}, /* 0x02 */
{1, &oid_rt_pro_burst_read_register_hdl}, //0x03 {1, &oid_rt_pro_burst_read_register_hdl}, /* 0x03 */
{1, &oid_rt_pro_burst_write_register_hdl}, //0x04 {1, &oid_rt_pro_burst_write_register_hdl}, /* 0x04 */
{1, &oid_rt_pro_write_txcmd_hdl}, //0x05 {1, &oid_rt_pro_write_txcmd_hdl}, /* 0x05 */
{1, &oid_rt_pro_read16_eeprom_hdl}, //0x06 {1, &oid_rt_pro_read16_eeprom_hdl}, /* 0x06 */
{1, &oid_rt_pro_write16_eeprom_hdl}, //0x07 {1, &oid_rt_pro_write16_eeprom_hdl}, /* 0x07 */
{1, &oid_null_function}, //0x08 OID_RT_PRO_H2C_SET_COMMAND {1, &oid_null_function}, /* 0x08 OID_RT_PRO_H2C_SET_COMMAND */
{1, &oid_null_function}, //0x09 OID_RT_PRO_H2C_QUERY_RESULT {1, &oid_null_function}, /* 0x09 OID_RT_PRO_H2C_QUERY_RESULT */
{1, &oid_rt_pro8711_wi_poll_hdl}, //0x0A {1, &oid_rt_pro8711_wi_poll_hdl}, /* 0x0A */
{1, &oid_rt_pro8711_pkt_loss_hdl}, //0x0B {1, &oid_rt_pro8711_pkt_loss_hdl}, /* 0x0B */
{1, &oid_rt_rd_attrib_mem_hdl}, //0x0C {1, &oid_rt_rd_attrib_mem_hdl}, /* 0x0C */
{1, &oid_rt_wr_attrib_mem_hdl}, //0x0D {1, &oid_rt_wr_attrib_mem_hdl}, /* 0x0D */
{1, &oid_null_function}, //0x0E {1, &oid_null_function}, /* 0x0E */
{1, &oid_null_function}, //0x0F {1, &oid_null_function}, /* 0x0F */
{1, &oid_null_function}, //0x10 OID_RT_PRO_H2C_CMD_MODE {1, &oid_null_function}, /* 0x10 OID_RT_PRO_H2C_CMD_MODE */
{1, &oid_null_function}, //0x11 OID_RT_PRO_H2C_CMD_RSP_MODE {1, &oid_null_function}, /* 0x11 OID_RT_PRO_H2C_CMD_RSP_MODE */
{1, &oid_null_function}, //0X12 OID_RT_PRO_WAIT_C2H_EVENT {1, &oid_null_function}, /* 0X12 OID_RT_PRO_WAIT_C2H_EVENT */
{1, &oid_null_function}, //0X13 OID_RT_PRO_RW_ACCESS_PROTOCOL_TEST {1, &oid_null_function}, /* 0X13 OID_RT_PRO_RW_ACCESS_PROTOCOL_TEST */
{1, &oid_null_function}, //0X14 OID_RT_PRO_SCSI_ACCESS_TEST {1, &oid_null_function}, /* 0X14 OID_RT_PRO_SCSI_ACCESS_TEST */
{1, &oid_null_function}, //0X15 OID_RT_PRO_SCSI_TCPIPOFFLOAD_OUT {1, &oid_null_function}, /* 0X15 OID_RT_PRO_SCSI_TCPIPOFFLOAD_OUT */
{1, &oid_null_function}, //0X16 OID_RT_PRO_SCSI_TCPIPOFFLOAD_IN {1, &oid_null_function}, /* 0X16 OID_RT_PRO_SCSI_TCPIPOFFLOAD_IN */
{1, &oid_null_function}, //0X17 OID_RT_RRO_RX_PKT_VIA_IOCTRL {1, &oid_null_function}, /* 0X17 OID_RT_RRO_RX_PKT_VIA_IOCTRL */
{1, &oid_null_function}, //0X18 OID_RT_RRO_RX_PKTARRAY_VIA_IOCTRL {1, &oid_null_function}, /* 0X18 OID_RT_RRO_RX_PKTARRAY_VIA_IOCTRL */
{1, &oid_null_function}, //0X19 OID_RT_RPO_SET_PWRMGT_TEST {1, &oid_null_function}, /* 0X19 OID_RT_RPO_SET_PWRMGT_TEST */
{1, &oid_null_function}, //0X1A {1, &oid_null_function}, /* 0X1A */
{1, &oid_null_function}, //0X1B OID_RT_PRO_QRY_PWRMGT_TEST {1, &oid_null_function}, /* 0X1B OID_RT_PRO_QRY_PWRMGT_TEST */
{1, &oid_null_function}, //0X1C OID_RT_RPO_ASYNC_RWIO_TEST {1, &oid_null_function}, /* 0X1C OID_RT_RPO_ASYNC_RWIO_TEST */
{1, &oid_null_function}, //0X1D OID_RT_RPO_ASYNC_RWIO_POLL {1, &oid_null_function}, /* 0X1D OID_RT_RPO_ASYNC_RWIO_POLL */
{1, &oid_rt_pro_set_rf_intfs_hdl}, //0X1E {1, &oid_rt_pro_set_rf_intfs_hdl}, /* 0X1E */
{1, &oid_rt_poll_rx_status_hdl} //0X1F {1, &oid_rt_poll_rx_status_hdl} /* 0X1F */
}; };
static struct oid_obj_priv oid_rtl_seg_87_11_20[] = static struct oid_obj_priv oid_rtl_seg_87_11_20[] =
{ {
{1, &oid_rt_pro_cfg_debug_message_hdl}, //0x20 {1, &oid_rt_pro_cfg_debug_message_hdl}, /* 0x20 */
{1, &oid_rt_pro_set_data_rate_ex_hdl}, //0x21 {1, &oid_rt_pro_set_data_rate_ex_hdl}, /* 0x21 */
{1, &oid_rt_pro_set_basic_rate_hdl}, //0x22 {1, &oid_rt_pro_set_basic_rate_hdl}, /* 0x22 */
{1, &oid_rt_pro_read_tssi_hdl}, //0x23 {1, &oid_rt_pro_read_tssi_hdl}, /* 0x23 */
{1, &oid_rt_pro_set_power_tracking_hdl} //0x24 {1, &oid_rt_pro_set_power_tracking_hdl} /* 0x24 */
}; };
static struct oid_obj_priv oid_rtl_seg_87_11_50[] = static struct oid_obj_priv oid_rtl_seg_87_11_50[] =
{ {
{1, &oid_rt_pro_qry_pwrstate_hdl}, //0x50 {1, &oid_rt_pro_qry_pwrstate_hdl}, /* 0x50 */
{1, &oid_rt_pro_set_pwrstate_hdl} //0x51 {1, &oid_rt_pro_set_pwrstate_hdl} /* 0x51 */
}; };
static struct oid_obj_priv oid_rtl_seg_87_11_80[] = static struct oid_obj_priv oid_rtl_seg_87_11_80[] =
{ {
{1, &oid_null_function} //0x80 {1, &oid_null_function} /* 0x80 */
}; };
static struct oid_obj_priv oid_rtl_seg_87_11_B0[] = static struct oid_obj_priv oid_rtl_seg_87_11_B0[] =
{ {
{1, &oid_null_function} //0xB0 {1, &oid_null_function} /* 0xB0 */
}; };
static struct oid_obj_priv oid_rtl_seg_87_11_F0[] = static struct oid_obj_priv oid_rtl_seg_87_11_F0[] =
{ {
{1, &oid_null_function}, //0xF0 {1, &oid_null_function}, /* 0xF0 */
{1, &oid_null_function}, //0xF1 {1, &oid_null_function}, /* 0xF1 */
{1, &oid_null_function}, //0xF2 {1, &oid_null_function}, /* 0xF2 */
{1, &oid_null_function}, //0xF3 {1, &oid_null_function}, /* 0xF3 */
{1, &oid_null_function}, //0xF4 {1, &oid_null_function}, /* 0xF4 */
{1, &oid_null_function}, //0xF5 {1, &oid_null_function}, /* 0xF5 */
{1, &oid_null_function}, //0xF6 {1, &oid_null_function}, /* 0xF6 */
{1, &oid_null_function}, //0xF7 {1, &oid_null_function}, /* 0xF7 */
{1, &oid_null_function}, //0xF8 {1, &oid_null_function}, /* 0xF8 */
{1, &oid_null_function}, //0xF9 {1, &oid_null_function}, /* 0xF9 */
{1, &oid_null_function}, //0xFA {1, &oid_null_function}, /* 0xFA */
{1, &oid_rt_pro_h2c_set_rate_table_hdl}, //0xFB {1, &oid_rt_pro_h2c_set_rate_table_hdl}, /* 0xFB */
{1, &oid_rt_pro_h2c_get_rate_table_hdl}, //0xFC {1, &oid_rt_pro_h2c_get_rate_table_hdl}, /* 0xFC */
{1, &oid_null_function}, //0xFD {1, &oid_null_function}, /* 0xFD */
{1, &oid_null_function}, //0xFE OID_RT_PRO_H2C_C2H_LBK_TEST {1, &oid_null_function}, /* 0xFE OID_RT_PRO_H2C_C2H_LBK_TEST */
{1, &oid_null_function} //0xFF {1, &oid_null_function} /* 0xFF */
}; };
static struct oid_obj_priv oid_rtl_seg_87_12_00[]= static struct oid_obj_priv oid_rtl_seg_87_12_00[]=
{ {
{1, &oid_rt_pro_encryption_ctrl_hdl}, //0x00 Q&S {1, &oid_rt_pro_encryption_ctrl_hdl}, /* 0x00 Q&S */
{1, &oid_rt_pro_add_sta_info_hdl}, //0x01 S {1, &oid_rt_pro_add_sta_info_hdl}, /* 0x01 S */
{1, &oid_rt_pro_dele_sta_info_hdl}, //0x02 S {1, &oid_rt_pro_dele_sta_info_hdl}, /* 0x02 S */
{1, &oid_rt_pro_query_dr_variable_hdl}, //0x03 Q {1, &oid_rt_pro_query_dr_variable_hdl}, /* 0x03 Q */
{1, &oid_rt_pro_rx_packet_type_hdl}, //0x04 Q,S {1, &oid_rt_pro_rx_packet_type_hdl}, /* 0x04 Q,S */
{1, &oid_rt_pro_read_efuse_hdl}, //0x05 Q OID_RT_PRO_READ_EFUSE {1, &oid_rt_pro_read_efuse_hdl}, /* 0x05 Q OID_RT_PRO_READ_EFUSE */
{1, &oid_rt_pro_write_efuse_hdl}, //0x06 S OID_RT_PRO_WRITE_EFUSE {1, &oid_rt_pro_write_efuse_hdl}, /* 0x06 S OID_RT_PRO_WRITE_EFUSE */
{1, &oid_rt_pro_rw_efuse_pgpkt_hdl}, //0x07 Q,S {1, &oid_rt_pro_rw_efuse_pgpkt_hdl}, /* 0x07 Q,S */
{1, &oid_rt_get_efuse_current_size_hdl}, //0x08 Q {1, &oid_rt_get_efuse_current_size_hdl}, /* 0x08 Q */
{1, &oid_rt_set_bandwidth_hdl}, //0x09 {1, &oid_rt_set_bandwidth_hdl}, /* 0x09 */
{1, &oid_rt_set_crystal_cap_hdl}, //0x0a {1, &oid_rt_set_crystal_cap_hdl}, /* 0x0a */
{1, &oid_rt_set_rx_packet_type_hdl}, //0x0b S {1, &oid_rt_set_rx_packet_type_hdl}, /* 0x0b S */
{1, &oid_rt_get_efuse_max_size_hdl}, //0x0c {1, &oid_rt_get_efuse_max_size_hdl}, /* 0x0c */
{1, &oid_rt_pro_set_tx_agc_offset_hdl}, //0x0d {1, &oid_rt_pro_set_tx_agc_offset_hdl}, /* 0x0d */
{1, &oid_rt_pro_set_pkt_test_mode_hdl}, //0x0e {1, &oid_rt_pro_set_pkt_test_mode_hdl}, /* 0x0e */
{1, &oid_null_function}, //0x0f OID_RT_PRO_FOR_EVM_TEST_SETTING {1, &oid_null_function}, /* 0x0f OID_RT_PRO_FOR_EVM_TEST_SETTING */
{1, &oid_rt_get_thermal_meter_hdl}, //0x10 Q OID_RT_PRO_GET_THERMAL_METER {1, &oid_rt_get_thermal_meter_hdl}, /* 0x10 Q OID_RT_PRO_GET_THERMAL_METER */
{1, &oid_rt_reset_phy_rx_packet_count_hdl}, //0x11 S OID_RT_RESET_PHY_RX_PACKET_COUNT {1, &oid_rt_reset_phy_rx_packet_count_hdl}, /* 0x11 S OID_RT_RESET_PHY_RX_PACKET_COUNT */
{1, &oid_rt_get_phy_rx_packet_received_hdl}, //0x12 Q OID_RT_GET_PHY_RX_PACKET_RECEIVED {1, &oid_rt_get_phy_rx_packet_received_hdl}, /* 0x12 Q OID_RT_GET_PHY_RX_PACKET_RECEIVED */
{1, &oid_rt_get_phy_rx_packet_crc32_error_hdl}, //0x13 Q OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR {1, &oid_rt_get_phy_rx_packet_crc32_error_hdl}, /* 0x13 Q OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR */
{1, &oid_rt_set_power_down_hdl}, //0x14 Q OID_RT_SET_POWER_DOWN {1, &oid_rt_set_power_down_hdl}, /* 0x14 Q OID_RT_SET_POWER_DOWN */
{1, &oid_rt_get_power_mode_hdl} //0x15 Q OID_RT_GET_POWER_MODE {1, &oid_rt_get_power_mode_hdl} /* 0x15 Q OID_RT_GET_POWER_MODE */
}; };
#else /* _RTL871X_MP_IOCTL_C_ */ #else /* _RTL871X_MP_IOCTL_C_ */
@ -446,7 +446,7 @@ struct psmode_param {
u32 smart_ps; u32 smart_ps;
}; };
//for OID_RT_PRO_READ16_EEPROM & OID_RT_PRO_WRITE16_EEPROM /* for OID_RT_PRO_READ16_EEPROM & OID_RT_PRO_WRITE16_EEPROM */
struct eeprom_rw_param { struct eeprom_rw_param {
u32 offset; u32 offset;
u16 value; u16 value;

518
include/rtw_mp_phy_regdef.h
View file

@ -46,24 +46,24 @@
/*--------------------------Define Parameters-------------------------------*/ /*--------------------------Define Parameters-------------------------------*/
//============================================================ /* */
// 8192S Regsiter offset definition /* 8192S Regsiter offset definition */
//============================================================ /* */
// /* */
// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */
// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
// 3. RF register 0x00-2E /* 3. RF register 0x00-2E */
// 4. Bit Mask for BB/RF register /* 4. Bit Mask for BB/RF register */
// 5. Other defintion for BB/RF R/W /* 5. Other defintion for BB/RF R/W */
// /* */
// /* */
// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */
// 1. Page1(0x100) /* 1. Page1(0x100) */
// /* */
#define rPMAC_Reset 0x100 #define rPMAC_Reset 0x100
#define rPMAC_TxStart 0x104 #define rPMAC_TxStart 0x104
#define rPMAC_TxLegacySIG 0x108 #define rPMAC_TxLegacySIG 0x108
@ -92,29 +92,22 @@
#define rPMAC_CCKCRxRC32OK 0x188 #define rPMAC_CCKCRxRC32OK 0x188
#define rPMAC_TxStatus 0x18c #define rPMAC_TxStatus 0x18c
// /* */
// 2. Page2(0x200) /* 3. Page8(0x800) */
// /* */
// The following two definition are only used for USB interface. #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */
//#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address.
//#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data.
// #define rFPGA0_TxInfo 0x804 /* Status report?? */
// 3. Page8(0x800)
//
#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting??
#define rFPGA0_TxInfo 0x804 // Status report??
#define rFPGA0_PSDFunction 0x808 #define rFPGA0_PSDFunction 0x808
#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
#define rFPGA0_RFTiming1 0x810 // Useless now #define rFPGA0_RFTiming1 0x810 /* Useless now */
#define rFPGA0_RFTiming2 0x814 #define rFPGA0_RFTiming2 0x814
//#define rFPGA0_XC_RFTiming 0x818 /* define rFPGA0_XC_RFTiming 0x818 */
//#define rFPGA0_XD_RFTiming 0x81c /* define rFPGA0_XD_RFTiming 0x81c */
#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
#define rFPGA0_XA_HSSIParameter2 0x824 #define rFPGA0_XA_HSSIParameter2 0x824
#define rFPGA0_XB_HSSIParameter1 0x828 #define rFPGA0_XB_HSSIParameter1 0x828
#define rFPGA0_XB_HSSIParameter2 0x82c #define rFPGA0_XB_HSSIParameter2 0x82c
@ -127,83 +120,83 @@
#define rFPGA0_XC_LSSIParameter 0x848 #define rFPGA0_XC_LSSIParameter 0x848
#define rFPGA0_XD_LSSIParameter 0x84c #define rFPGA0_XD_LSSIParameter 0x84c
#define rFPGA0_RFWakeUpParameter 0x850 // Useless now #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */
#define rFPGA0_RFSleepUpParameter 0x854 #define rFPGA0_RFSleepUpParameter 0x854
#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */
#define rFPGA0_XCD_SwitchControl 0x85c #define rFPGA0_XCD_SwitchControl 0x85c
#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */
#define rFPGA0_XB_RFInterfaceOE 0x864 #define rFPGA0_XB_RFInterfaceOE 0x864
#define rFPGA0_XC_RFInterfaceOE 0x868 #define rFPGA0_XC_RFInterfaceOE 0x868
#define rFPGA0_XD_RFInterfaceOE 0x86c #define rFPGA0_XD_RFInterfaceOE 0x86c
#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */
#define rFPGA0_XCD_RFInterfaceSW 0x874 #define rFPGA0_XCD_RFInterfaceSW 0x874
#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */
#define rFPGA0_XCD_RFParameter 0x87c #define rFPGA0_XCD_RFParameter 0x87c
#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */
#define rFPGA0_AnalogParameter2 0x884 #define rFPGA0_AnalogParameter2 0x884
#define rFPGA0_AnalogParameter3 0x888 // Useless now #define rFPGA0_AnalogParameter3 0x888 /* Useless now */
#define rFPGA0_AnalogParameter4 0x88c #define rFPGA0_AnalogParameter4 0x88c
#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */
#define rFPGA0_XB_LSSIReadBack 0x8a4 #define rFPGA0_XB_LSSIReadBack 0x8a4
#define rFPGA0_XC_LSSIReadBack 0x8a8 #define rFPGA0_XC_LSSIReadBack 0x8a8
#define rFPGA0_XD_LSSIReadBack 0x8ac #define rFPGA0_XD_LSSIReadBack 0x8ac
#define rFPGA0_PSDReport 0x8b4 // Useless now #define rFPGA0_PSDReport 0x8b4 /* Useless now */
#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now RF Interface Readback Value */
#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */
// /* */
// 4. Page9(0x900) /* 4. Page9(0x900) */
// /* */
#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC RF BW Setting?? */
#define rFPGA1_TxBlock 0x904 // Useless now #define rFPGA1_TxBlock 0x904 /* Useless now */
#define rFPGA1_DebugSelect 0x908 // Useless now #define rFPGA1_DebugSelect 0x908 /* Useless now */
#define rFPGA1_TxInfo 0x90c // Useless now // Status report?? #define rFPGA1_TxInfo 0x90c /* Useless now Status report?? */
// /* */
// 5. PageA(0xA00) /* 5. PageA(0xA00) */
// /* */
// Set Control channel to upper or lower. These settings are required only for 40MHz /* Set Control channel to upper or lower. These settings are required only for 40MHz */
#define rCCK0_System 0xa00 #define rCCK0_System 0xa00
#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI #define rCCK0_AFESetting 0xa04 /* Disable init gain now Select RX path by RSSI */
#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain #define rCCK0_CCA 0xa08 /* Disable init gain now Init gain */
#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series #define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
#define rCCK0_RxAGC2 0xa10 //AGC & DAGC #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */
#define rCCK0_RxHP 0xa14 #define rCCK0_RxHP 0xa14
#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold #define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */
#define rCCK0_DSPParameter2 0xa1c //SQ threshold #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
#define rCCK0_TxFilter1 0xa20 #define rCCK0_TxFilter1 0xa20
#define rCCK0_TxFilter2 0xa24 #define rCCK0_TxFilter2 0xa24
#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */
#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */
#define rCCK0_TRSSIReport 0xa50 #define rCCK0_TRSSIReport 0xa50
#define rCCK0_RxReport 0xa54 //0xa57 #define rCCK0_RxReport 0xa54 /* 0xa57 */
#define rCCK0_FACounterLower 0xa5c //0xa5b #define rCCK0_FACounterLower 0xa5c /* 0xa5b */
#define rCCK0_FACounterUpper 0xa58 //0xa5c #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */
// /* */
// 6. PageC(0xC00) /* 6. PageC(0xC00) */
// /* */
#define rOFDM0_LSTF 0xc00 #define rOFDM0_LSTF 0xc00
#define rOFDM0_TRxPathEnable 0xc04 #define rOFDM0_TRxPathEnable 0xc04
#define rOFDM0_TRMuxPar 0xc08 #define rOFDM0_TRMuxPar 0xc08
#define rOFDM0_TRSWIsolation 0xc0c #define rOFDM0_TRSWIsolation 0xc0c
#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */
#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */
#define rOFDM0_XBRxAFE 0xc18 #define rOFDM0_XBRxAFE 0xc18
#define rOFDM0_XBRxIQImbalance 0xc1c #define rOFDM0_XBRxIQImbalance 0xc1c
#define rOFDM0_XCRxAFE 0xc20 #define rOFDM0_XCRxAFE 0xc20
@ -211,17 +204,17 @@
#define rOFDM0_XDRxAFE 0xc28 #define rOFDM0_XDRxAFE 0xc28
#define rOFDM0_XDRxIQImbalance 0xc2c #define rOFDM0_XDRxIQImbalance 0xc2c
#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain #define rOFDM0_RxDetector1 0xc30 /* PD,BW & SBD DM tune init gain */
#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */
#define rOFDM0_RxDetector3 0xc38 //Frame Sync. #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */
#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */
#define rOFDM0_RxDSP 0xc40 //Rx Sync Path #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */
#define rOFDM0_ECCAThreshold 0xc4c // energy CCA #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
#define rOFDM0_XAAGCCore1 0xc50 // DIG #define rOFDM0_XAAGCCore1 0xc50 /* DIG */
#define rOFDM0_XAAGCCore2 0xc54 #define rOFDM0_XAAGCCore2 0xc54
#define rOFDM0_XBAGCCore1 0xc58 #define rOFDM0_XBAGCCore1 0xc58
#define rOFDM0_XBAGCCore2 0xc5c #define rOFDM0_XBAGCCore2 0xc5c
@ -235,7 +228,7 @@
#define rOFDM0_AGCRSSITable 0xc78 #define rOFDM0_AGCRSSITable 0xc78
#define rOFDM0_HTSTFAGC 0xc7c #define rOFDM0_HTSTFAGC 0xc7c
#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */
#define rOFDM0_XATxAFE 0xc84 #define rOFDM0_XATxAFE 0xc84
#define rOFDM0_XBTxIQImbalance 0xc88 #define rOFDM0_XBTxIQImbalance 0xc88
#define rOFDM0_XBTxAFE 0xc8c #define rOFDM0_XBTxAFE 0xc8c
@ -257,13 +250,13 @@
#define rOFDM0_TxCoeff6 0xcb8 #define rOFDM0_TxCoeff6 0xcb8
// /* */
// 7. PageD(0xD00) /* 7. PageD(0xD00) */
// /* */
#define rOFDM1_LSTF 0xd00 #define rOFDM1_LSTF 0xd00
#define rOFDM1_TRxPathEnable 0xd04 #define rOFDM1_TRxPathEnable 0xd04
#define rOFDM1_CFO 0xd08 // No setting now #define rOFDM1_CFO 0xd08 /* No setting now */
#define rOFDM1_CSI1 0xd10 #define rOFDM1_CSI1 0xd10
#define rOFDM1_SBD 0xd14 #define rOFDM1_SBD 0xd14
#define rOFDM1_CSI2 0xd18 #define rOFDM1_CSI2 0xd18
@ -275,11 +268,11 @@
#define rOFDM1_PseudoNoiseStateCD 0xd54 #define rOFDM1_PseudoNoiseStateCD 0xd54
#define rOFDM1_RxPseudoNoiseWgt 0xd58 #define rOFDM1_RxPseudoNoiseWgt 0xd58
#define rOFDM_PHYCounter1 0xda0 //cca, parity fail #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */
#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */
#define rOFDM_PHYCounter3 0xda8 //MCS not support #define rOFDM_PHYCounter3 0xda8 /* MCS not support */
#define rOFDM_ShortCFOAB 0xdac // No setting now #define rOFDM_ShortCFOAB 0xdac /* No setting now */
#define rOFDM_ShortCFOCD 0xdb0 #define rOFDM_ShortCFOCD 0xdb0
#define rOFDM_LongCFOAB 0xdb4 #define rOFDM_LongCFOAB 0xdb4
#define rOFDM_LongCFOCD 0xdb8 #define rOFDM_LongCFOCD 0xdb8
@ -294,9 +287,9 @@
#define rOFDM_SIGReport 0xddc #define rOFDM_SIGReport 0xddc
// /* */
// 8. PageE(0xE00) /* 8. PageE(0xE00) */
// /* */
#define rTxAGC_Rate18_06 0xe00 #define rTxAGC_Rate18_06 0xe00
#define rTxAGC_Rate54_24 0xe04 #define rTxAGC_Rate54_24 0xe04
#define rTxAGC_CCK_Mcs32 0xe08 #define rTxAGC_CCK_Mcs32 0xe08
@ -305,107 +298,107 @@
#define rTxAGC_Mcs11_Mcs08 0xe18 #define rTxAGC_Mcs11_Mcs08 0xe18
#define rTxAGC_Mcs15_Mcs12 0xe1c #define rTxAGC_Mcs15_Mcs12 0xe1c
// Analog- control in RX_WAIT_CCA : REG: EE0 [Analog- Power & Control Register] /* Analog- control in RX_WAIT_CCA : REG: EE0 [Analog- Power & Control Register] */
#define rRx_Wait_CCCA 0xe70 #define rRx_Wait_CCCA 0xe70
#define rAnapar_Ctrl_BB 0xee0 #define rAnapar_Ctrl_BB 0xee0
// /* */
// 7. RF Register 0x00-0x2E (RF 8256) /* 7. RF Register 0x00-0x2E (RF 8256) */
// RF-0222D 0x00-3F /* RF-0222D 0x00-3F */
// /* */
//Zebra1 /* Zebra1 */
#define RTL92SE_FPGA_VERIFY 0 #define RTL92SE_FPGA_VERIFY 0
#define rZebra1_HSSIEnable 0x0 // Useless now #define rZebra1_HSSIEnable 0x0 /* Useless now */
#define rZebra1_TRxEnable1 0x1 #define rZebra1_TRxEnable1 0x1
#define rZebra1_TRxEnable2 0x2 #define rZebra1_TRxEnable2 0x2
#define rZebra1_AGC 0x4 #define rZebra1_AGC 0x4
#define rZebra1_ChargePump 0x5 #define rZebra1_ChargePump 0x5
//#if (RTL92SE_FPGA_VERIFY == 1) /* if (RTL92SE_FPGA_VERIFY == 1) */
#define rZebra1_Channel 0x7 // RF channel switch #define rZebra1_Channel 0x7 /* RF channel switch */
//#else /* else */
//#endif /* endif */
#define rZebra1_TxGain 0x8 // Useless now #define rZebra1_TxGain 0x8 /* Useless now */
#define rZebra1_TxLPF 0x9 #define rZebra1_TxLPF 0x9
#define rZebra1_RxLPF 0xb #define rZebra1_RxLPF 0xb
#define rZebra1_RxHPFCorner 0xc #define rZebra1_RxHPFCorner 0xc
//Zebra4 /* Zebra4 */
#define rGlobalCtrl 0 // Useless now #define rGlobalCtrl 0 /* Useless now */
#define rRTL8256_TxLPF 19 #define rRTL8256_TxLPF 19
#define rRTL8256_RxLPF 11 #define rRTL8256_RxLPF 11
//RTL8258 /* RTL8258 */
#define rRTL8258_TxLPF 0x11 // Useless now #define rRTL8258_TxLPF 0x11 /* Useless now */
#define rRTL8258_RxLPF 0x13 #define rRTL8258_RxLPF 0x13
#define rRTL8258_RSSILPF 0xa #define rRTL8258_RSSILPF 0xa
// /* */
// RL6052 Register definition /* RL6052 Register definition */
// /* */
#define RF_AC 0x00 // #define RF_AC 0x00 /* */
#define RF_IQADJ_G1 0x01 // #define RF_IQADJ_G1 0x01 /* */
#define RF_IQADJ_G2 0x02 // #define RF_IQADJ_G2 0x02 /* */
#define RF_POW_TRSW 0x05 // #define RF_POW_TRSW 0x05 /* */
#define RF_GAIN_RX 0x06 // #define RF_GAIN_RX 0x06 /* */
#define RF_GAIN_TX 0x07 // #define RF_GAIN_TX 0x07 /* */
#define RF_TXM_IDAC 0x08 // #define RF_TXM_IDAC 0x08 /* */
#define RF_BS_IQGEN 0x0F // #define RF_BS_IQGEN 0x0F /* */
#define RF_MODE1 0x10 // #define RF_MODE1 0x10 /* */
#define RF_MODE2 0x11 // #define RF_MODE2 0x11 /* */
#define RF_RX_AGC_HP 0x12 // #define RF_RX_AGC_HP 0x12 /* */
#define RF_TX_AGC 0x13 // #define RF_TX_AGC 0x13 /* */
#define RF_BIAS 0x14 // #define RF_BIAS 0x14 /* */
#define RF_IPA 0x15 // #define RF_IPA 0x15 /* */
#define RF_TXBIAS 0x16 // #define RF_TXBIAS 0x16 /* */
#define RF_POW_ABILITY 0x17 // #define RF_POW_ABILITY 0x17 /* */
#define RF_MODE_AG 0x18 // #define RF_MODE_AG 0x18 /* */
#define rRfChannel 0x18 // RF channel and BW switch #define rRfChannel 0x18 /* RF channel and BW switch */
#define RF_CHNLBW 0x18 // RF channel and BW switch #define RF_CHNLBW 0x18 /* RF channel and BW switch */
#define RF_TOP 0x19 // #define RF_TOP 0x19 /* */
#define RF_RX_G1 0x1A // #define RF_RX_G1 0x1A /* */
#define RF_RX_G2 0x1B // #define RF_RX_G2 0x1B /* */
#define RF_RX_BB2 0x1C // #define RF_RX_BB2 0x1C /* */
#define RF_RX_BB1 0x1D // #define RF_RX_BB1 0x1D /* */
#define RF_RCK1 0x1E // #define RF_RCK1 0x1E /* */
#define RF_RCK2 0x1F // #define RF_RCK2 0x1F /* */
#define RF_TX_G1 0x20 // #define RF_TX_G1 0x20 /* */
#define RF_TX_G2 0x21 // #define RF_TX_G2 0x21 /* */
#define RF_TX_G3 0x22 // #define RF_TX_G3 0x22 /* */
#define RF_TX_BB1 0x23 // #define RF_TX_BB1 0x23 /* */
#define RF_T_METER 0x24 // #define RF_T_METER 0x24 /* */
#define RF_SYN_G1 0x25 // RF TX Power control #define RF_SYN_G1 0x25 /* RF TX Power control */
#define RF_SYN_G2 0x26 // RF TX Power control #define RF_SYN_G2 0x26 /* RF TX Power control */
#define RF_SYN_G3 0x27 // RF TX Power control #define RF_SYN_G3 0x27 /* RF TX Power control */
#define RF_SYN_G4 0x28 // RF TX Power control #define RF_SYN_G4 0x28 /* RF TX Power control */
#define RF_SYN_G5 0x29 // RF TX Power control #define RF_SYN_G5 0x29 /* RF TX Power control */
#define RF_SYN_G6 0x2A // RF TX Power control #define RF_SYN_G6 0x2A /* RF TX Power control */
#define RF_SYN_G7 0x2B // RF TX Power control #define RF_SYN_G7 0x2B /* RF TX Power control */
#define RF_SYN_G8 0x2C // RF TX Power control #define RF_SYN_G8 0x2C /* RF TX Power control */
#define RF_RCK_OS 0x30 // RF TX PA control #define RF_RCK_OS 0x30 /* RF TX PA control */
#define RF_TXPA_G1 0x31 // RF TX PA control #define RF_TXPA_G1 0x31 /* RF TX PA control */
#define RF_TXPA_G2 0x32 // RF TX PA control #define RF_TXPA_G2 0x32 /* RF TX PA control */
#define RF_TXPA_G3 0x33 // RF TX PA control #define RF_TXPA_G3 0x33 /* RF TX PA control */
// /* */
//Bit Mask /* Bit Mask */
// /* */
// 1. Page1(0x100) /* 1. Page1(0x100) */
#define bBBResetB 0x100 // Useless now? #define bBBResetB 0x100 /* Useless now? */
#define bGlobalResetB 0x200 #define bGlobalResetB 0x200
#define bOFDMTxStart 0x4 #define bOFDMTxStart 0x4
#define bCCKTxStart 0x8 #define bCCKTxStart 0x8
@ -452,34 +445,34 @@
#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
// 2. Page8(0x800) /* 2. Page8(0x800) */
#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */
#define bJapanMode 0x2 #define bJapanMode 0x2
#define bCCKTxSC 0x30 #define bCCKTxSC 0x30
#define bCCKEn 0x1000000 #define bCCKEn 0x1000000
#define bOFDMEn 0x2000000 #define bOFDMEn 0x2000000
#define bOFDMRxADCPhase 0x10000 // Useless now #define bOFDMRxADCPhase 0x10000 /* Useless now */
#define bOFDMTxDACPhase 0x40000 #define bOFDMTxDACPhase 0x40000
#define bXATxAGC 0x3f #define bXATxAGC 0x3f
#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */
#define bXCTxAGC 0xf000 #define bXCTxAGC 0xf000
#define bXDTxAGC 0xf0000 #define bXDTxAGC 0xf0000
#define bPAStart 0xf0000000 // Useless now #define bPAStart 0xf0000000 /* Useless now */
#define bTRStart 0x00f00000 #define bTRStart 0x00f00000
#define bRFStart 0x0000f000 #define bRFStart 0x0000f000
#define bBBStart 0x000000f0 #define bBBStart 0x000000f0
#define bBBCCKStart 0x0000000f #define bBBCCKStart 0x0000000f
#define bPAEnd 0xf //Reg0x814 #define bPAEnd 0xf /* Reg0x814 */
#define bTREnd 0x0f000000 #define bTREnd 0x0f000000
#define bRFEnd 0x000f0000 #define bRFEnd 0x000f0000
#define bCCAMask 0x000000f0 //T2R #define bCCAMask 0x000000f0 /* T2R */
#define bR2RCCAMask 0x00000f00 #define bR2RCCAMask 0x00000f00
#define bHSSI_R2TDelay 0xf8000000 #define bHSSI_R2TDelay 0xf8000000
#define bHSSI_T2RDelay 0xf80000 #define bHSSI_T2RDelay 0xf80000
#define bContTxHSSI 0x400 //chane gain at continue Tx #define bContTxHSSI 0x400 /* chane gain at continue Tx */
#define bIGFromCCK 0x200 #define bIGFromCCK 0x200
#define bAGCAddress 0x3f #define bAGCAddress 0x3f
#define bRxHPTx 0x7000 #define bRxHPTx 0x7000
@ -488,11 +481,11 @@
#define bAGCTxCode 0xc00000 #define bAGCTxCode 0xc00000
#define bAGCRxCode 0x300000 #define bAGCRxCode 0x300000
#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
#define b3WireAddressLength 0x400 #define b3WireAddressLength 0x400
#define b3WireRFPowerDown 0x1 // Useless now #define b3WireRFPowerDown 0x1 /* Useless now */
//#define bHWSISelect 0x8 /* define bHWSISelect 0x8 */
#define b5GPAPEPolarity 0x40000000 #define b5GPAPEPolarity 0x40000000
#define b2GPAPEPolarity 0x80000000 #define b2GPAPEPolarity 0x80000000
#define bRFSW_TxDefaultAnt 0x3 #define bRFSW_TxDefaultAnt 0x3
@ -505,9 +498,9 @@
#define bRFSI_3WireRW 0x8 #define bRFSI_3WireRW 0x8
#define bRFSI_3Wire 0xf #define bRFSI_3Wire 0xf
#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
#define bRFSI_TRSW 0x20 // Useless now #define bRFSI_TRSW 0x20 /* Useless now */
#define bRFSI_TRSWB 0x40 #define bRFSI_TRSWB 0x40
#define bRFSI_ANTSW 0x100 #define bRFSI_ANTSW 0x100
#define bRFSI_ANTSWB 0x200 #define bRFSI_ANTSWB 0x200
@ -531,18 +524,18 @@
#define bLSIG_Parity 0x20 #define bLSIG_Parity 0x20
#define bCCKRxPhase 0x4 #define bCCKRxPhase 0x4
#if (RTL92SE_FPGA_VERIFY == 1) #if (RTL92SE_FPGA_VERIFY == 1)
#define bLSSIReadAddress 0x3f000000 //LSSI "Read" Address // Reg 0x824 rFPGA0_XA_HSSIParameter2 #define bLSSIReadAddress 0x3f000000 /* LSSI "Read" Address Reg 0x824 rFPGA0_XA_HSSIParameter2 */
#else #else
#define bLSSIReadAddress 0x7f800000 // T65 RF #define bLSSIReadAddress 0x7f800000 /* T65 RF */
#endif #endif
#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */
#if (RTL92SE_FPGA_VERIFY == 1) #if (RTL92SE_FPGA_VERIFY == 1)
#define bLSSIReadBackData 0xfff // Reg 0x8a0 rFPGA0_XA_LSSIReadBack #define bLSSIReadBackData 0xfff /* Reg 0x8a0 rFPGA0_XA_LSSIReadBack */
#else #else
#define bLSSIReadBackData 0xfffff // T65 RF #define bLSSIReadBackData 0xfffff /* T65 RF */
#endif #endif
#define bLSSIReadOKFlag 0x1000 // Useless now #define bLSSIReadOKFlag 0x1000 /* Useless now */
#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */
#define bRegulator0Standby 0x1 #define bRegulator0Standby 0x1
#define bRegulatorPLLStandby 0x2 #define bRegulatorPLLStandby 0x2
#define bRegulator1Standby 0x4 #define bRegulator1Standby 0x4
@ -556,17 +549,17 @@
#define bDA6DebugMode 0x20000 #define bDA6DebugMode 0x20000
#define bDA6Swing 0x380000 #define bDA6Swing 0x380000
#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ #define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
#define b80MClkDelay 0x18000000 // Useless #define b80MClkDelay 0x18000000 /* Useless */
#define bAFEWatchDogEnable 0x20000000 #define bAFEWatchDogEnable 0x20000000
#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap #define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
#define bXtalCap23 0x3 #define bXtalCap23 0x3
#define bXtalCap92x 0x0f000000 #define bXtalCap92x 0x0f000000
#define bXtalCap 0x0f000000 #define bXtalCap 0x0f000000
#define bIntDifClkEnable 0x400 // Useless #define bIntDifClkEnable 0x400 /* Useless */
#define bExtSigClkEnable 0x800 #define bExtSigClkEnable 0x800
#define bBandgapMbiasPowerUp 0x10000 #define bBandgapMbiasPowerUp 0x10000
#define bAD11SHGain 0xc0000 #define bAD11SHGain 0xc0000
@ -600,12 +593,12 @@
#define bPSDSineToneScale 0x7f000000 #define bPSDSineToneScale 0x7f000000
#define bPSDReport 0xffff #define bPSDReport 0xffff
// 3. Page9(0x900) /* 3. Page9(0x900) */
#define bOFDMTxSC 0x30000000 // Useless #define bOFDMTxSC 0x30000000 /* Useless */
#define bCCKTxOn 0x1 #define bCCKTxOn 0x1
#define bOFDMTxOn 0x2 #define bOFDMTxOn 0x2
#define bDebugPage 0xfff //reset debug page and also HWord, LWord #define bDebugPage 0xfff /* reset debug page and also HWord, LWord */
#define bDebugItem 0xff //reset debug page and LWord #define bDebugItem 0xff /* reset debug page and LWord */
#define bAntL 0x10 #define bAntL 0x10
#define bAntNonHT 0x100 #define bAntNonHT 0x100
#define bAntHT1 0x1000 #define bAntHT1 0x1000
@ -613,14 +606,14 @@
#define bAntHT1S1 0x100000 #define bAntHT1S1 0x100000
#define bAntNonHTS1 0x1000000 #define bAntNonHTS1 0x1000000
// 4. PageA(0xA00) /* 4. PageA(0xA00) */
#define bCCKBBMode 0x3 // Useless #define bCCKBBMode 0x3 /* Useless */
#define bCCKTxPowerSaving 0x80 #define bCCKTxPowerSaving 0x80
#define bCCKRxPowerSaving 0x40 #define bCCKRxPowerSaving 0x40
#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */
#define bCCKScramble 0x8 // Useless #define bCCKScramble 0x8 /* Useless */
#define bCCKAntDiversity 0x8000 #define bCCKAntDiversity 0x8000
#define bCCKCarrierRecovery 0x4000 #define bCCKCarrierRecovery 0x4000
#define bCCKTxRate 0x3000 #define bCCKTxRate 0x3000
@ -636,7 +629,7 @@
#define bCCKBistMode 0x80000000 #define bCCKBistMode 0x80000000
#define bCCKCCAMask 0x40000000 #define bCCKCCAMask 0x40000000
#define bCCKTxDACPhase 0x4 #define bCCKTxDACPhase 0x4
#define bCCKRxADCPhase 0x20000000 //r_rx_clk #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
#define bCCKr_cp_mode0 0x0100 #define bCCKr_cp_mode0 0x0100
#define bCCKTxDCOffset 0xf0 #define bCCKTxDCOffset 0xf0
#define bCCKRxDCOffset 0xf #define bCCKRxDCOffset 0xf
@ -650,12 +643,11 @@
#define bCCKRxIG 0x7f00 #define bCCKRxIG 0x7f00
#define bCCKLNAPolarity 0x800000 #define bCCKLNAPolarity 0x800000
#define bCCKRx1stGain 0x7f0000 #define bCCKRx1stGain 0x7f0000
#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */
#define bCCKRxAGCSatLevel 0x1f000000 #define bCCKRxAGCSatLevel 0x1f000000
#define bCCKRxAGCSatCount 0xe0 #define bCCKRxAGCSatCount 0xe0
#define bCCKRxRFSettle 0x1f //AGCsamp_dly #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */
#define bCCKFixedRxAGC 0x8000 #define bCCKFixedRxAGC 0x8000
//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
#define bCCKAntennaPolarity 0x2000 #define bCCKAntennaPolarity 0x2000
#define bCCKTxFilterType 0x0c00 #define bCCKTxFilterType 0x0c00
#define bCCKRxAGCReportType 0x0300 #define bCCKRxAGCReportType 0x0300
@ -694,8 +686,8 @@
#define bCCKDefaultRxPath 0xc000000 #define bCCKDefaultRxPath 0xc000000
#define bCCKOptionRxPath 0x3000000 #define bCCKOptionRxPath 0x3000000
// 5. PageC(0xC00) /* 5. PageC(0xC00) */
#define bNumOfSTF 0x3 // Useless #define bNumOfSTF 0x3 /* Useless */
#define bShift_L 0xc0 #define bShift_L 0xc0
#define bGI_TH 0xc #define bGI_TH 0xc
#define bRxPathA 0x1 #define bRxPathA 0x1
@ -796,8 +788,8 @@
#define bRxHP_BBP1 0x7000 #define bRxHP_BBP1 0x7000
#define bRxHP_BBP2 0x70000 #define bRxHP_BBP2 0x70000
#define bRxHP_BBP3 0x700000 #define bRxHP_BBP3 0x700000
#define bRSSI_H 0x7f0000 //the threshold for high power #define bRSSI_H 0x7f0000 /* the threshold for high power */
#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity #define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */
#define bRxSettle_TRSW 0x7 #define bRxSettle_TRSW 0x7
#define bRxSettle_LNA 0x38 #define bRxSettle_LNA 0x38
#define bRxSettle_RSSI 0x1c0 #define bRxSettle_RSSI 0x1c0
@ -831,7 +823,7 @@
#define bRxPD_Delay_TH1 0x38 #define bRxPD_Delay_TH1 0x38
#define bRxPD_Delay_TH2 0x1c0 #define bRxPD_Delay_TH2 0x1c0
#define bRxPD_DC_COUNT_MAX 0x600 #define bRxPD_DC_COUNT_MAX 0x600
//#define bRxMF_Hold 0x3800 /* define bRxMF_Hold 0x3800 */
#define bRxPD_Delay_TH 0x8000 #define bRxPD_Delay_TH 0x8000
#define bRxProcess_Delay 0xf0000 #define bRxProcess_Delay 0xf0000
#define bRxSearchrange_GI2_Early 0x700000 #define bRxSearchrange_GI2_Early 0x700000
@ -852,8 +844,8 @@
#define bTRSWIsolation_D 0x7f000000 #define bTRSWIsolation_D 0x7f000000
#define bExtLNAGain 0x7c00 #define bExtLNAGain 0x7c00
// 6. PageE(0xE00) /* 6. PageE(0xE00) */
#define bSTBCEn 0x4 // Useless #define bSTBCEn 0x4 /* Useless */
#define bAntennaMapping 0x10 #define bAntennaMapping 0x10
#define bNss 0x20 #define bNss 0x20
#define bCFOAntSumD 0x200 #define bCFOAntSumD 0x200
@ -862,12 +854,12 @@
#define bOFDMContinueTx 0x10000000 #define bOFDMContinueTx 0x10000000
#define bOFDMSingleCarrier 0x20000000 #define bOFDMSingleCarrier 0x20000000
#define bOFDMSingleTone 0x40000000 #define bOFDMSingleTone 0x40000000
//#define bRxPath1 0x01 /* define bRxPath1 0x01 */
//#define bRxPath2 0x02 /* define bRxPath2 0x02 */
//#define bRxPath3 0x04 /* define bRxPath3 0x04 */
//#define bRxPath4 0x08 /* define bRxPath4 0x08 */
//#define bTxPath1 0x10 /* define bTxPath1 0x10 */
//#define bTxPath2 0x20 /* define bTxPath2 0x20 */
#define bHTDetect 0x100 #define bHTDetect 0x100
#define bCFOEn 0x10000 #define bCFOEn 0x10000
#define bCFOValue 0xfff00000 #define bCFOValue 0xfff00000
@ -880,8 +872,8 @@
#define bCounter_MCSNoSupport 0xffff #define bCounter_MCSNoSupport 0xffff
#define bCounter_FastSync 0xffff #define bCounter_FastSync 0xffff
#define bShortCFO 0xfff #define bShortCFO 0xfff
#define bShortCFOTLength 12 //total #define bShortCFOTLength 12 /* total */
#define bShortCFOFLength 11 //fraction #define bShortCFOFLength 11 /* fraction */
#define bLongCFO 0x7ff #define bLongCFO 0x7ff
#define bLongCFOTLength 11 #define bLongCFOTLength 11
#define bLongCFOFLength 11 #define bLongCFOFLength 11
@ -916,7 +908,7 @@
#define bPWDB 0xff00 #define bPWDB 0xff00
#define bSGIEN 0x10000 #define bSGIEN 0x10000
#define bSFactorQAM1 0xf // Useless #define bSFactorQAM1 0xf /* Useless */
#define bSFactorQAM2 0xf0 #define bSFactorQAM2 0xf0
#define bSFactorQAM3 0xf00 #define bSFactorQAM3 0xf00
#define bSFactorQAM4 0xf000 #define bSFactorQAM4 0xf000
@ -927,7 +919,7 @@
#define bSFactorQAM9 0xf0000000 #define bSFactorQAM9 0xf0000000
#define bCSIScheme 0x100000 #define bCSIScheme 0x100000
#define bNoiseLvlTopSet 0x3 // Useless #define bNoiseLvlTopSet 0x3 /* Useless */
#define bChSmooth 0x4 #define bChSmooth 0x4
#define bChSmoothCfg1 0x38 #define bChSmoothCfg1 0x38
#define bChSmoothCfg2 0x1c0 #define bChSmoothCfg2 0x1c0
@ -936,7 +928,7 @@
#define bMRCMode 0x800000 #define bMRCMode 0x800000
#define bTHEVMCfg 0x7000000 #define bTHEVMCfg 0x7000000
#define bLoopFitType 0x1 // Useless #define bLoopFitType 0x1 /* Useless */
#define bUpdCFO 0x40 #define bUpdCFO 0x40
#define bUpdCFOOffData 0x80 #define bUpdCFOOffData 0x80
#define bAdvUpdCFO 0x100 #define bAdvUpdCFO 0x100
@ -952,7 +944,7 @@
#define bUChCfg 0x7000000 #define bUChCfg 0x7000000
#define bUpdEqz 0x8000000 #define bUpdEqz 0x8000000
#define bTxAGCRate18_06 0x7f7f7f7f // Useless #define bTxAGCRate18_06 0x7f7f7f7f /* Useless */
#define bTxAGCRate54_24 0x7f7f7f7f #define bTxAGCRate54_24 0x7f7f7f7f
#define bTxAGCRateMCS32 0x7f #define bTxAGCRateMCS32 0x7f
#define bTxAGCRateCCK 0x7f00 #define bTxAGCRateCCK 0x7f00
@ -961,8 +953,8 @@
#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f #define bTxAGCRateMCS11_MCS8 0x7f7f7f7f
#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f #define bTxAGCRateMCS15_MCS12 0x7f7f7f7f
//Rx Pseduo noise /* Rx Pseduo noise */
#define bRxPesudoNoiseOn 0x20000000 // Useless #define bRxPesudoNoiseOn 0x20000000 /* Useless */
#define bRxPesudoNoise_A 0xff #define bRxPesudoNoise_A 0xff
#define bRxPesudoNoise_B 0xff00 #define bRxPesudoNoise_B 0xff00
#define bRxPesudoNoise_C 0xff0000 #define bRxPesudoNoise_C 0xff0000
@ -972,9 +964,9 @@
#define bPesudoNoiseState_C 0xffff #define bPesudoNoiseState_C 0xffff
#define bPesudoNoiseState_D 0xffff0000 #define bPesudoNoiseState_D 0xffff0000
//7. RF Register /* 7. RF Register */
//Zebra1 /* Zebra1 */
#define bZebra1_HSSIEnable 0x8 // Useless #define bZebra1_HSSIEnable 0x8 /* Useless */
#define bZebra1_TRxControl 0xc00 #define bZebra1_TRxControl 0xc00
#define bZebra1_TRxGainSetting 0x07f #define bZebra1_TRxGainSetting 0x07f
#define bZebra1_RxCorner 0xc00 #define bZebra1_RxCorner 0xc00
@ -984,24 +976,24 @@
#define bZebra1_TxLPFBW 0x400 #define bZebra1_TxLPFBW 0x400
#define bZebra1_RxLPFBW 0x600 #define bZebra1_RxLPFBW 0x600
//Zebra4 /* Zebra4 */
#define bRTL8256RegModeCtrl1 0x100 // Useless #define bRTL8256RegModeCtrl1 0x100 /* Useless */
#define bRTL8256RegModeCtrl0 0x40 #define bRTL8256RegModeCtrl0 0x40
#define bRTL8256_TxLPFBW 0x18 #define bRTL8256_TxLPFBW 0x18
#define bRTL8256_RxLPFBW 0x600 #define bRTL8256_RxLPFBW 0x600
//RTL8258 /* RTL8258 */
#define bRTL8258_TxLPFBW 0xc // Useless #define bRTL8258_TxLPFBW 0xc /* Useless */
#define bRTL8258_RxLPFBW 0xc00 #define bRTL8258_RxLPFBW 0xc00
#define bRTL8258_RSSILPFBW 0xc0 #define bRTL8258_RSSILPFBW 0xc0
// /* */
// Other Definition /* Other Definition */
// /* */
//byte endable for sb_write /* byte endable for sb_write */
#define bByte0 0x1 // Useless #define bByte0 0x1 /* Useless */
#define bByte1 0x2 #define bByte1 0x2
#define bByte2 0x4 #define bByte2 0x4
#define bByte3 0x8 #define bByte3 0x8
@ -1009,8 +1001,8 @@
#define bWord1 0xc #define bWord1 0xc
#define bDWord 0xf #define bDWord 0xf
//for PutRegsetting & GetRegSetting BitMask /* for PutRegsetting & GetRegSetting BitMask */
#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
#define bMaskByte1 0xff00 #define bMaskByte1 0xff00
#define bMaskByte2 0xff0000 #define bMaskByte2 0xff0000
#define bMaskByte3 0xff000000 #define bMaskByte3 0xff000000
@ -1022,68 +1014,64 @@
#define bMaskCCK 0x3f3f3f3f #define bMaskCCK 0x3f3f3f3f
#define bMask12Bits 0xfff #define bMask12Bits 0xfff
//for PutRFRegsetting & GetRFRegSetting BitMask /* for PutRFRegsetting & GetRFRegSetting BitMask */
#if (RTL92SE_FPGA_VERIFY == 1) #if (RTL92SE_FPGA_VERIFY == 1)
//#define bMask12Bits 0xfff // RF Reg mask bits
//#define bMask20Bits 0xfff // RF Reg mask bits T65 RF
#define bRFRegOffsetMask 0xfff #define bRFRegOffsetMask 0xfff
#else #else
//#define bMask12Bits 0xfffff // RF Reg mask bits
//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF
#define bRFRegOffsetMask 0xfffff #define bRFRegOffsetMask 0xfffff
#endif #endif
#define bEnable 0x1 // Useless #define bEnable 0x1 /* Useless */
#define bDisable 0x0 #define bDisable 0x0
#define LeftAntenna 0x0 // Useless #define LeftAntenna 0x0 /* Useless */
#define RightAntenna 0x1 #define RightAntenna 0x1
#define tCheckTxStatus 500 //500ms // Useless #define tCheckTxStatus 500 /* 500ms Useless */
#define tUpdateRxCounter 100 //100ms #define tUpdateRxCounter 100 /* 100ms */
#define rateCCK 0 // Useless #define rateCCK 0 /* Useless */
#define rateOFDM 1 #define rateOFDM 1
#define rateHT 2 #define rateHT 2
//define Register-End /* define Register-End */
#define bPMAC_End 0x1ff // Useless #define bPMAC_End 0x1ff /* Useless */
#define bFPGAPHY0_End 0x8ff #define bFPGAPHY0_End 0x8ff
#define bFPGAPHY1_End 0x9ff #define bFPGAPHY1_End 0x9ff
#define bCCKPHY0_End 0xaff #define bCCKPHY0_End 0xaff
#define bOFDMPHY0_End 0xcff #define bOFDMPHY0_End 0xcff
#define bOFDMPHY1_End 0xdff #define bOFDMPHY1_End 0xdff
//define max debug item in each debug page /* define max debug item in each debug page */
//#define bMaxItem_FPGA_PHY0 0x9 /* define bMaxItem_FPGA_PHY0 0x9 */
//#define bMaxItem_FPGA_PHY1 0x3 /* define bMaxItem_FPGA_PHY1 0x3 */
//#define bMaxItem_PHY_11B 0x16 /* define bMaxItem_PHY_11B 0x16 */
//#define bMaxItem_OFDM_PHY0 0x29 /* define bMaxItem_OFDM_PHY0 0x29 */
//#define bMaxItem_OFDM_PHY1 0x0 /* define bMaxItem_OFDM_PHY1 0x0 */
#define bPMACControl 0x0 // Useless #define bPMACControl 0x0 /* Useless */
#define bWMACControl 0x1 #define bWMACControl 0x1
#define bWNICControl 0x2 #define bWNICControl 0x2
#define RCR_AAP BIT(0) // accept all physical address #define RCR_AAP BIT(0) /* accept all physical address */
#define RCR_APM BIT(1) // accept physical match #define RCR_APM BIT(1) /* accept physical match */
#define RCR_AM BIT(2) // accept multicast #define RCR_AM BIT(2) /* accept multicast */
#define RCR_AB BIT(3) // accept broadcast #define RCR_AB BIT(3) /* accept broadcast */
#define RCR_ACRC32 BIT(5) // accept error packet #define RCR_ACRC32 BIT(5) /* accept error packet */
#define RCR_9356SEL BIT(6) #define RCR_9356SEL BIT(6)
#define RCR_AICV BIT(12) // Accept ICV error packet #define RCR_AICV BIT(12) /* Accept ICV error packet */
#define RCR_RXFTH0 (BIT(13)|BIT(14)|BIT(15)) // Rx FIFO threshold #define RCR_RXFTH0 (BIT(13)|BIT(14)|BIT(15)) /* Rx FIFO threshold */
#define RCR_ADF BIT(18) // Accept Data(frame type) frame #define RCR_ADF BIT(18) /* Accept Data(frame type) frame */
#define RCR_ACF BIT(19) // Accept control frame #define RCR_ACF BIT(19) /* Accept control frame */
#define RCR_AMF BIT(20) // Accept management frame #define RCR_AMF BIT(20) /* Accept management frame */
#define RCR_ADD3 BIT(21) #define RCR_ADD3 BIT(21)
#define RCR_APWRMGT BIT(22) // Accept power management packet #define RCR_APWRMGT BIT(22) /* Accept power management packet */
#define RCR_CBSSID BIT(23) // Accept BSSID match packet #define RCR_CBSSID BIT(23) /* Accept BSSID match packet */
#define RCR_ENMARP BIT(28) // enable mac auto reset phy #define RCR_ENMARP BIT(28) /* enable mac auto reset phy */
#define RCR_EnCS1 BIT(29) // enable carrier sense method 1 #define RCR_EnCS1 BIT(29) /* enable carrier sense method 1 */
#define RCR_EnCS2 BIT(30) // enable carrier sense method 2 #define RCR_EnCS2 BIT(30) /* enable carrier sense method 2 */
#define RCR_OnlyErlPkt BIT(31) // Rx Early mode is performed for packet size greater than 1536 #define RCR_OnlyErlPkt BIT(31) /* Rx Early mode is performed for packet size greater than 1536 */
/*--------------------------Define Parameters-------------------------------*/ /*--------------------------Define Parameters-------------------------------*/
#endif //__INC_HAL8192SPHYREG_H #endif /* __INC_HAL8192SPHYREG_H */

2
include/rtw_odm.h
View file

@ -38,4 +38,4 @@ void rtw_odm_adaptivity_parm_msg(struct adapter *adapter);
void rtw_odm_adaptivity_parm_set(struct adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff, void rtw_odm_adaptivity_parm_set(struct adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff,
s8 IGI_Base, bool ForceEDCCA, u8 AdapEn_RSSI, u8 IGI_LowerBound); s8 IGI_Base, bool ForceEDCCA, u8 AdapEn_RSSI, u8 IGI_LowerBound);
#endif // __RTW_ODM_H__ #endif /* __RTW_ODM_H__ */

20
include/rtw_p2p.h
View file

@ -40,7 +40,7 @@ u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
u32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); u32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
u32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); u32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
#endif //CONFIG_P2P #endif /* CONFIG_P2P */
u32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); u32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len, struct sta_info *psta); u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len, struct sta_info *psta);
@ -59,7 +59,7 @@ void p2p_protocol_wk_hdl(struct adapter *padapter, int intCmdType);
void process_p2p_ps_ie(struct adapter *padapter, u8 *IEs, u32 IELength); void process_p2p_ps_ie(struct adapter *padapter, u8 *IEs, u32 IELength);
void p2p_ps_wk_hdl(struct adapter *padapter, u8 p2p_ps_state); void p2p_ps_wk_hdl(struct adapter *padapter, u8 p2p_ps_state);
u8 p2p_ps_wk_cmd(struct adapter*padapter, u8 p2p_ps_state, u8 enqueue); u8 p2p_ps_wk_cmd(struct adapter*padapter, u8 p2p_ps_state, u8 enqueue);
#endif // CONFIG_P2P #endif /* CONFIG_P2P */
void rtw_init_cfg80211_wifidirect_info( struct adapter* padapter); void rtw_init_cfg80211_wifidirect_info( struct adapter* padapter);
int rtw_p2p_check_frames(struct adapter *padapter, const u8 *buf, u32 len, u8 tx); int rtw_p2p_check_frames(struct adapter *padapter, const u8 *buf, u32 len, u8 tx);
@ -75,7 +75,7 @@ int rtw_p2p_enable(struct adapter *padapter, enum P2P_ROLE role);
static inline void _rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state) static inline void _rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state)
{ {
if(wdinfo->p2p_state != state) { if(wdinfo->p2p_state != state) {
//wdinfo->pre_p2p_state = wdinfo->p2p_state; /* wdinfo->pre_p2p_state = wdinfo->p2p_state; */
wdinfo->p2p_state = state; wdinfo->p2p_state = state;
} }
} }
@ -116,18 +116,18 @@ static inline bool _rtw_p2p_chk_role(struct wifidirect_info *wdinfo, enum P2P_RO
#ifdef CONFIG_DBG_P2P #ifdef CONFIG_DBG_P2P
void dbg_rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line); void dbg_rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line);
void dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line); void dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line);
//void dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line); /* void dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line); */
void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, const char *caller, int line); void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, const char *caller, int line);
#define rtw_p2p_set_state(wdinfo, state) dbg_rtw_p2p_set_state(wdinfo, state, __FUNCTION__, __LINE__) #define rtw_p2p_set_state(wdinfo, state) dbg_rtw_p2p_set_state(wdinfo, state, __FUNCTION__, __LINE__)
#define rtw_p2p_set_pre_state(wdinfo, state) dbg_rtw_p2p_set_pre_state(wdinfo, state, __FUNCTION__, __LINE__) #define rtw_p2p_set_pre_state(wdinfo, state) dbg_rtw_p2p_set_pre_state(wdinfo, state, __FUNCTION__, __LINE__)
#define rtw_p2p_set_role(wdinfo, role) dbg_rtw_p2p_set_role(wdinfo, role, __FUNCTION__, __LINE__) #define rtw_p2p_set_role(wdinfo, role) dbg_rtw_p2p_set_role(wdinfo, role, __FUNCTION__, __LINE__)
//#define rtw_p2p_restore_state(wdinfo) dbg_rtw_p2p_restore_state(wdinfo, __FUNCTION__, __LINE__) /* define rtw_p2p_restore_state(wdinfo) dbg_rtw_p2p_restore_state(wdinfo, __FUNCTION__, __LINE__) */
#else //CONFIG_DBG_P2P #else /* CONFIG_DBG_P2P */
#define rtw_p2p_set_state(wdinfo, state) _rtw_p2p_set_state(wdinfo, state) #define rtw_p2p_set_state(wdinfo, state) _rtw_p2p_set_state(wdinfo, state)
#define rtw_p2p_set_pre_state(wdinfo, state) _rtw_p2p_set_pre_state(wdinfo, state) #define rtw_p2p_set_pre_state(wdinfo, state) _rtw_p2p_set_pre_state(wdinfo, state)
#define rtw_p2p_set_role(wdinfo, role) _rtw_p2p_set_role(wdinfo, role) #define rtw_p2p_set_role(wdinfo, role) _rtw_p2p_set_role(wdinfo, role)
//#define rtw_p2p_restore_state(wdinfo) _rtw_p2p_restore_state(wdinfo) /* define rtw_p2p_restore_state(wdinfo) _rtw_p2p_restore_state(wdinfo) */
#endif //CONFIG_DBG_P2P #endif /* CONFIG_DBG_P2P */
#define rtw_p2p_state(wdinfo) _rtw_p2p_state(wdinfo) #define rtw_p2p_state(wdinfo) _rtw_p2p_state(wdinfo)
#define rtw_p2p_pre_state(wdinfo) _rtw_p2p_pre_state(wdinfo) #define rtw_p2p_pre_state(wdinfo) _rtw_p2p_pre_state(wdinfo)
@ -138,11 +138,11 @@ void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, co
#define rtw_p2p_findphase_ex_set(wdinfo, value) \ #define rtw_p2p_findphase_ex_set(wdinfo, value) \
(wdinfo)->find_phase_state_exchange_cnt = (value) (wdinfo)->find_phase_state_exchange_cnt = (value)
//is this find phase exchange for social channel scan? /* is this find phase exchange for social channel scan? */
#define rtw_p2p_findphase_ex_is_social(wdinfo) \ #define rtw_p2p_findphase_ex_is_social(wdinfo) \
(wdinfo)->find_phase_state_exchange_cnt >= P2P_FINDPHASE_EX_SOCIAL_FIRST (wdinfo)->find_phase_state_exchange_cnt >= P2P_FINDPHASE_EX_SOCIAL_FIRST
//should we need find phase exchange anymore? /* should we need find phase exchange anymore? */
#define rtw_p2p_findphase_ex_is_needed(wdinfo) \ #define rtw_p2p_findphase_ex_is_needed(wdinfo) \
((wdinfo)->find_phase_state_exchange_cnt < P2P_FINDPHASE_EX_MAX && \ ((wdinfo)->find_phase_state_exchange_cnt < P2P_FINDPHASE_EX_MAX && \
(wdinfo)->find_phase_state_exchange_cnt != P2P_FINDPHASE_EX_NONE) (wdinfo)->find_phase_state_exchange_cnt != P2P_FINDPHASE_EX_NONE)

62
include/rtw_pwrctrl.h
View file

@ -26,7 +26,7 @@
#ifdef CONFIG_HAS_EARLYSUSPEND #ifdef CONFIG_HAS_EARLYSUSPEND
#include <linux/earlysuspend.h> #include <linux/earlysuspend.h>
#endif //CONFIG_HAS_EARLYSUSPEND #endif /* CONFIG_HAS_EARLYSUSPEND */
#define FW_PWR0 0 #define FW_PWR0 0
@ -106,7 +106,7 @@ enum Power_Mgnt
struct reportpwrstate_parm { struct reportpwrstate_parm {
unsigned char mode; unsigned char mode;
unsigned char state; //the CPWM value unsigned char state; /* the CPWM value */
unsigned short rsvd; unsigned short rsvd;
}; };
@ -132,32 +132,32 @@ __inline static void _exit_pwrlock(struct semaphore *plock)
_rtw_up_sema(plock); _rtw_up_sema(plock);
} }
#define LPS_DELAY_TIME 1*HZ // 1 sec #define LPS_DELAY_TIME 1*HZ /* 1 sec */
#define EXE_PWR_NONE 0x01 #define EXE_PWR_NONE 0x01
#define EXE_PWR_IPS 0x02 #define EXE_PWR_IPS 0x02
#define EXE_PWR_LPS 0x04 #define EXE_PWR_LPS 0x04
// RF state. /* RF state. */
typedef enum _rt_rf_power_state typedef enum _rt_rf_power_state
{ {
rf_on, // RF is on after RFSleep or RFOff rf_on, /* RF is on after RFSleep or RFOff */
rf_sleep, // 802.11 Power Save mode rf_sleep, /* 802.11 Power Save mode */
rf_off, // HW/SW Radio OFF or Inactive Power Save rf_off, /* HW/SW Radio OFF or Inactive Power Save */
//=====Add the new RF state above this line=====// /* Add the new RF state above this line===== */
rf_max rf_max
}rt_rf_power_state; }rt_rf_power_state;
// RF Off Level for IPS or HW/SW radio off /* RF Off Level for IPS or HW/SW radio off */
#define RT_RF_OFF_LEVL_ASPM BIT(0) // PCI ASPM #define RT_RF_OFF_LEVL_ASPM BIT(0) /* PCI ASPM */
#define RT_RF_OFF_LEVL_CLK_REQ BIT(1) // PCI clock request #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /* PCI clock request */
#define RT_RF_OFF_LEVL_PCI_D3 BIT(2) // PCI D3 mode #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /* PCI D3 mode */
#define RT_RF_OFF_LEVL_HALT_NIC BIT(3) // NIC halt, re-initialize hw parameters #define RT_RF_OFF_LEVL_HALT_NIC BIT(3) /* NIC halt, re-initialize hw parameters */
#define RT_RF_OFF_LEVL_FREE_FW BIT(4) // FW free, re-download the FW #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /* FW free, re-download the FW */
#define RT_RF_OFF_LEVL_FW_32K BIT(5) // FW in 32k #define RT_RF_OFF_LEVL_FW_32K BIT(5) /* FW in 32k */
#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) // Always enable ASPM and Clock Req in initialization. #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) /* Always enable ASPM and Clock Req in initialization. */
#define RT_RF_LPS_DISALBE_2R BIT(30) // When LPS is on, disable 2R if no packet is received or transmittd. #define RT_RF_LPS_DISALBE_2R BIT(30) /* When LPS is on, disable 2R if no packet is received or transmittd. */
#define RT_RF_LPS_LEVEL_ASPM BIT(31) // LPS with ASPM #define RT_RF_LPS_LEVEL_ASPM BIT(31) /* LPS with ASPM */
#define RT_IN_PS_LEVEL(ppsc, _PS_FLAG) ((ppsc->cur_ps_level & _PS_FLAG) ? true : false) #define RT_IN_PS_LEVEL(ppsc, _PS_FLAG) ((ppsc->cur_ps_level & _PS_FLAG) ? true : false)
#define RT_CLEAR_PS_LEVEL(ppsc, _PS_FLAG) (ppsc->cur_ps_level &= (~(_PS_FLAG))) #define RT_CLEAR_PS_LEVEL(ppsc, _PS_FLAG) (ppsc->cur_ps_level &= (~(_PS_FLAG)))
@ -172,7 +172,7 @@ enum _PS_BBRegBackup_ {
PSBBREG_TOTALCNT PSBBREG_TOTALCNT
}; };
enum { // for ips_mode enum { /* for ips_mode */
IPS_NONE=0, IPS_NONE=0,
IPS_NORMAL, IPS_NORMAL,
IPS_LEVEL_2, IPS_LEVEL_2,
@ -181,10 +181,10 @@ enum { // for ips_mode
struct pwrctrl_priv struct pwrctrl_priv
{ {
struct semaphore lock; struct semaphore lock;
volatile u8 rpwm; // requested power state for fw volatile u8 rpwm; /* requested power state for fw */
volatile u8 cpwm; // fw current power state. updated when 1. read from HCPWM 2. driver lowers power level volatile u8 cpwm; /* fw current power state. updated when 1. read from HCPWM 2. driver lowers power level */
volatile u8 tog; // toggling volatile u8 tog; /* toggling */
volatile u8 cpwm_tog; // toggling volatile u8 cpwm_tog; /* toggling */
u8 pwr_mode; u8 pwr_mode;
u8 smart_ps; u8 smart_ps;
@ -196,10 +196,10 @@ struct pwrctrl_priv
u8 b_hw_radio_off; u8 b_hw_radio_off;
u8 reg_rfoff; u8 reg_rfoff;
u8 reg_pdnmode; //powerdown mode u8 reg_pdnmode; /* powerdown mode */
u32 rfoff_reason; u32 rfoff_reason;
//RF OFF Level /* RF OFF Level */
u32 cur_ps_level; u32 cur_ps_level;
u32 reg_rfps_level; u32 reg_rfps_level;
@ -207,7 +207,7 @@ struct pwrctrl_priv
uint ips_leave_cnts; uint ips_leave_cnts;
u8 ips_mode; u8 ips_mode;
u8 ips_mode_req; // used to accept the mode setting request, will update to ipsmode later u8 ips_mode_req; /* used to accept the mode setting request, will update to ipsmode later */
uint bips_processing; uint bips_processing;
u32 ips_deny_time; /* will deny IPS when system time is smaller than this */ u32 ips_deny_time; /* will deny IPS when system time is smaller than this */
u8 ps_processing; /* temporarily used to mark whether in rtw_ps_processor */ u8 ps_processing; /* temporarily used to mark whether in rtw_ps_processor */
@ -235,11 +235,11 @@ struct pwrctrl_priv
int ps_flag; int ps_flag;
rt_rf_power_state rf_pwrstate;//cur power state rt_rf_power_state rf_pwrstate;/* cur power state */
//rt_rf_power_state current_rfpwrstate; /* rt_rf_power_state current_rfpwrstate; */
rt_rf_power_state change_rfpwrstate; rt_rf_power_state change_rfpwrstate;
u8 bHWPowerdown;//if support hw power down u8 bHWPowerdown;/* if support hw power down */
u8 bHWPwrPindetect; u8 bHWPwrPindetect;
u8 bkeepfwalive; u8 bkeepfwalive;
u8 brfoffbyhw; u8 brfoffbyhw;
@ -248,7 +248,7 @@ struct pwrctrl_priv
#ifdef CONFIG_HAS_EARLYSUSPEND #ifdef CONFIG_HAS_EARLYSUSPEND
struct early_suspend early_suspend; struct early_suspend early_suspend;
u8 do_late_resume; u8 do_late_resume;
#endif //CONFIG_HAS_EARLYSUSPEND #endif /* CONFIG_HAS_EARLYSUSPEND */
#ifdef CONFIG_ANDROID_POWER #ifdef CONFIG_ANDROID_POWER
android_early_suspend_t early_suspend; android_early_suspend_t early_suspend;
@ -320,4 +320,4 @@ int _rtw_pwr_wakeup(struct adapter *padapter, u32 ips_deffer_ms, const char *cal
int rtw_pm_set_ips(struct adapter *padapter, u8 mode); int rtw_pm_set_ips(struct adapter *padapter, u8 mode);
int rtw_pm_set_lps(struct adapter *padapter, u8 mode); int rtw_pm_set_lps(struct adapter *padapter, u8 mode);
#endif //__RTL871X_PWRCTRL_H_ #endif /* __RTL871X_PWRCTRL_H_ */

4
include/rtw_qos.h
View file

@ -31,9 +31,9 @@
struct qos_priv { struct qos_priv {
unsigned int qos_option; //bit mask option: u-apsd, s-apsd, ts, block ack... unsigned int qos_option; /* bit mask option: u-apsd, s-apsd, ts, block ack... */
}; };
#endif //_RTL871X_QOS_H_ #endif /* _RTL871X_QOS_H_ */

120
include/rtw_recv.h
View file

@ -41,7 +41,7 @@ static u8 SNAP_ETH_TYPE_IPX[2] = {0x81, 0x37};
static u8 SNAP_ETH_TYPE_APPLETALK_AARP[2] = {0x80, 0xf3}; static u8 SNAP_ETH_TYPE_APPLETALK_AARP[2] = {0x80, 0xf3};
static u8 SNAP_ETH_TYPE_APPLETALK_DDP[2] = {0x80, 0x9b}; static u8 SNAP_ETH_TYPE_APPLETALK_DDP[2] = {0x80, 0x9b};
static u8 SNAP_ETH_TYPE_TDLS[2] = {0x89, 0x0d}; static u8 SNAP_ETH_TYPE_TDLS[2] = {0x89, 0x0d};
static u8 SNAP_HDR_APPLETALK_DDP[3] = {0x08, 0x00, 0x07}; // Datagram Delivery Protocol static u8 SNAP_HDR_APPLETALK_DDP[3] = {0x08, 0x00, 0x07}; /* Datagram Delivery Protocol */
static u8 oui_8021h[] = {0x00, 0x00, 0xf8}; static u8 oui_8021h[] = {0x00, 0x00, 0xf8};
static u8 oui_rfc1042[]= {0x00,0x00,0x00}; static u8 oui_rfc1042[]= {0x00,0x00,0x00};
@ -53,12 +53,12 @@ static u8 rtw_rfc1042_header[] =
static u8 rtw_bridge_tunnel_header[] = static u8 rtw_bridge_tunnel_header[] =
{ 0xaa, 0xaa, 0x03, 0x00, 0x00, 0xf8 }; { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0xf8 };
//for Rx reordering buffer control /* for Rx reordering buffer control */
struct recv_reorder_ctrl struct recv_reorder_ctrl
{ {
struct adapter *padapter; struct adapter *padapter;
u8 enable; u8 enable;
u16 indicate_seq;//=wstart_b, init_value=0xffff u16 indicate_seq;/* wstart_b, init_value=0xffff */
u16 wend_b; u16 wend_b;
u8 wsize_b; u8 wsize_b;
struct __queue pending_recvframe_queue; struct __queue pending_recvframe_queue;
@ -71,32 +71,32 @@ struct stainfo_rxcache {
struct smooth_rssi_data { struct smooth_rssi_data {
u32 elements[100]; //array to store values u32 elements[100]; /* array to store values */
u32 index; //index to current array to store u32 index; /* index to current array to store */
u32 total_num; //num of valid elements u32 total_num; /* num of valid elements */
u32 total_val; //sum of valid elements u32 total_val; /* sum of valid elements */
}; };
struct signal_stat { struct signal_stat {
u8 update_req; //used to indicate u8 update_req; /* used to indicate */
u8 avg_val; //avg of valid elements u8 avg_val; /* avg of valid elements */
u32 total_num; //num of valid elements u32 total_num; /* num of valid elements */
u32 total_val; //sum of valid elements u32 total_val; /* sum of valid elements */
}; };
#define MAX_PATH_NUM_92CS 2 #define MAX_PATH_NUM_92CS 2
struct phy_info //ODM_PHY_INFO_T struct phy_info /* ODM_PHY_INFO_T */
{ {
u8 RxPWDBAll; u8 RxPWDBAll;
u8 SignalQuality; // in 0-100 index. u8 SignalQuality; /* in 0-100 index. */
u8 RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; //EVM u8 RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; /* EVM */
u8 RxMIMOSignalStrength[MAX_PATH_NUM_92CS];// in 0~100 index u8 RxMIMOSignalStrength[MAX_PATH_NUM_92CS];/* in 0~100 index */
s8 RxPower; // in dBm Translate from PWdB s8 RxPower; /* in dBm Translate from PWdB */
s8 RecvSignalPower;// Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. s8 RecvSignalPower;/* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */
u8 BTRxRSSIPercentage; u8 BTRxRSSIPercentage;
u8 SignalStrength; // in 0-100 index. u8 SignalStrength; /* in 0-100 index. */
u8 RxPwr[MAX_PATH_NUM_92CS];//per-path's pwdb u8 RxPwr[MAX_PATH_NUM_92CS];/* per-path's pwdb */
u8 RxSNR[MAX_PATH_NUM_92CS];//per-path's SNR u8 RxSNR[MAX_PATH_NUM_92CS];/* per-path's SNR */
}; };
@ -105,7 +105,7 @@ struct rx_pkt_attrib {
u8 physt; u8 physt;
u8 drvinfo_sz; u8 drvinfo_sz;
u8 shift_sz; u8 shift_sz;
u8 hdrlen; //the WLAN Header Len u8 hdrlen; /* the WLAN Header Len */
u8 to_fr_ds; u8 to_fr_ds;
u8 amsdu; u8 amsdu;
u8 qos; u8 qos;
@ -116,9 +116,9 @@ struct rx_pkt_attrib {
u8 frag_num; u8 frag_num;
u8 mfrag; u8 mfrag;
u8 order; u8 order;
u8 privacy; //in frame_ctrl field u8 privacy; /* in frame_ctrl field */
u8 bdecrypted; u8 bdecrypted;
u8 encrypt; //when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith u8 encrypt; /* when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith */
u8 iv_len; u8 iv_len;
u8 icv_len; u8 icv_len;
u8 crc_err; u8 crc_err;
@ -134,27 +134,27 @@ struct rx_pkt_attrib {
u8 ack_policy; u8 ack_policy;
u8 tcpchk_valid; // 0: invalid, 1: valid u8 tcpchk_valid; /* 0: invalid, 1: valid */
u8 ip_chkrpt; //0: incorrect, 1: correct u8 ip_chkrpt; /* 0: incorrect, 1: correct */
u8 tcp_chkrpt; //0: incorrect, 1: correct u8 tcp_chkrpt; /* 0: incorrect, 1: correct */
u8 key_index; u8 key_index;
u8 mcs_rate; u8 mcs_rate;
u8 rxht; u8 rxht;
u8 sgi; u8 sgi;
u8 pkt_rpt_type; u8 pkt_rpt_type;
u32 MacIDValidEntry[2]; // 64 bits present 64 entry. u32 MacIDValidEntry[2]; /* 64 bits present 64 entry. */
struct phy_info phy_info; struct phy_info phy_info;
}; };
//These definition is used for Rx packet reordering. /* These definition is used for Rx packet reordering. */
#define SN_LESS(a, b) (((a-b)&0x800)!=0) #define SN_LESS(a, b) (((a-b)&0x800)!=0)
#define SN_EQUAL(a, b) (a == b) #define SN_EQUAL(a, b) (a == b)
//#define REORDER_WIN_SIZE 128 /* define REORDER_WIN_SIZE 128 */
//#define REORDER_ENTRY_NUM 128 /* define REORDER_ENTRY_NUM 128 */
#define REORDER_WAIT_TIME (50) // (ms) #define REORDER_WAIT_TIME (50) /* (ms) */
#define RECVBUFF_ALIGN_SZ 8 #define RECVBUFF_ALIGN_SZ 8
@ -203,7 +203,7 @@ struct recv_priv {
uint rx_smallpacket_crcerr; uint rx_smallpacket_crcerr;
uint rx_middlepacket_crcerr; uint rx_middlepacket_crcerr;
//u8 *pallocated_urb_buf; /* u8 *pallocated_urb_buf; */
struct semaphore allrxreturnevt; struct semaphore allrxreturnevt;
uint ff_hwaddr; uint ff_hwaddr;
u8 rx_pending_cnt; u8 rx_pending_cnt;
@ -212,7 +212,7 @@ struct recv_priv {
struct urb * int_in_urb; struct urb * int_in_urb;
u8 *int_in_buf; u8 *int_in_buf;
#endif //CONFIG_USB_INTERRUPT_IN_PIPE #endif /* CONFIG_USB_INTERRUPT_IN_PIPE */
struct tasklet_struct irq_prepare_beacon_tasklet; struct tasklet_struct irq_prepare_beacon_tasklet;
struct tasklet_struct recv_tasklet; struct tasklet_struct recv_tasklet;
@ -221,15 +221,15 @@ struct recv_priv {
#ifdef CONFIG_RX_INDICATE_QUEUE #ifdef CONFIG_RX_INDICATE_QUEUE
struct task rx_indicate_tasklet; struct task rx_indicate_tasklet;
struct ifqueue rx_indicate_queue; struct ifqueue rx_indicate_queue;
#endif // CONFIG_RX_INDICATE_QUEUE #endif /* CONFIG_RX_INDICATE_QUEUE */
u8 *pallocated_recv_buf; u8 *pallocated_recv_buf;
u8 *precv_buf; // 4 alignment u8 *precv_buf; /* 4 alignment */
struct __queue free_recv_buf_queue; struct __queue free_recv_buf_queue;
u32 free_recv_buf_queue_cnt; u32 free_recv_buf_queue_cnt;
u8 is_signal_dbg; // for debug u8 is_signal_dbg; /* for debug */
u8 signal_strength_dbg; // for debug u8 signal_strength_dbg; /* for debug */
s8 rssi; s8 rssi;
s8 rxpwdb; s8 rxpwdb;
u8 signal_strength; u8 signal_strength;
@ -251,7 +251,7 @@ struct sta_recv_priv {
spinlock_t lock; spinlock_t lock;
sint option; sint option;
struct __queue defrag_q; //keeping the fragment frame until defrag struct __queue defrag_q; /* keeping the fragment frame until defrag */
struct stainfo_rxcache rxcache; struct stainfo_rxcache rxcache;
}; };
@ -316,10 +316,10 @@ struct recv_frame_hdr {
void *precvbuf; void *precvbuf;
// /* */
struct sta_info *psta; struct sta_info *psta;
//for A-MPDU Rx reordering buffer control /* for A-MPDU Rx reordering buffer control */
struct recv_reorder_ctrl *preorder_ctrl; struct recv_reorder_ctrl *preorder_ctrl;
}; };
@ -331,8 +331,8 @@ union recv_frame{
}u; }u;
}; };
extern union recv_frame *_rtw_alloc_recvframe (struct __queue *pfree_recv_queue); //get a free recv_frame from pfree_recv_queue extern union recv_frame *_rtw_alloc_recvframe (struct __queue *pfree_recv_queue); /* get a free recv_frame from pfree_recv_queue */
extern union recv_frame *rtw_alloc_recvframe (struct __queue *pfree_recv_queue); //get a free recv_frame from pfree_recv_queue extern union recv_frame *rtw_alloc_recvframe (struct __queue *pfree_recv_queue); /* get a free recv_frame from pfree_recv_queue */
extern void rtw_init_recvframe(union recv_frame *precvframe ,struct recv_priv *precvpriv); extern void rtw_init_recvframe(union recv_frame *precvframe ,struct recv_priv *precvpriv);
extern int rtw_free_recvframe(union recv_frame *precvframe, struct __queue *pfree_recv_queue); extern int rtw_free_recvframe(union recv_frame *precvframe, struct __queue *pfree_recv_queue);
@ -351,7 +351,7 @@ void rtw_reordering_ctrl_timeout_handler(void *pcontext);
__inline static u8 *get_rxmem(union recv_frame *precvframe) __inline static u8 *get_rxmem(union recv_frame *precvframe)
{ {
//always return rx_head... /* always return rx_head... */
if(precvframe==NULL) if(precvframe==NULL)
return NULL; return NULL;
@ -368,7 +368,7 @@ __inline static u8 *get_rx_status(union recv_frame *precvframe)
__inline static u8 *get_recvframe_data(union recv_frame *precvframe) __inline static u8 *get_recvframe_data(union recv_frame *precvframe)
{ {
//alwasy return rx_data /* alwasy return rx_data */
if(precvframe==NULL) if(precvframe==NULL)
return NULL; return NULL;
@ -378,7 +378,7 @@ __inline static u8 *get_recvframe_data(union recv_frame *precvframe)
__inline static u8 *recvframe_push(union recv_frame *precvframe, sint sz) __inline static u8 *recvframe_push(union recv_frame *precvframe, sint sz)
{ {
// append data before rx_data /* append data before rx_data */
/* add data to the start of recv_frame /* add data to the start of recv_frame
* *
@ -406,9 +406,9 @@ __inline static u8 *recvframe_push(union recv_frame *precvframe, sint sz)
__inline static u8 *recvframe_pull(union recv_frame *precvframe, sint sz) __inline static u8 *recvframe_pull(union recv_frame *precvframe, sint sz)
{ {
// rx_data += sz; move rx_data sz bytes hereafter /* rx_data += sz; move rx_data sz bytes hereafter */
//used for extract sz bytes from rx_data, update rx_data and return the updated rx_data to the caller /* used for extract sz bytes from rx_data, update rx_data and return the updated rx_data to the caller */
if(precvframe==NULL) if(precvframe==NULL)
@ -431,10 +431,10 @@ __inline static u8 *recvframe_pull(union recv_frame *precvframe, sint sz)
__inline static u8 *recvframe_put(union recv_frame *precvframe, sint sz) __inline static u8 *recvframe_put(union recv_frame *precvframe, sint sz)
{ {
// rx_tai += sz; move rx_tail sz bytes hereafter /* rx_tai += sz; move rx_tail sz bytes hereafter */
//used for append sz bytes from ptr to rx_tail, update rx_tail and return the updated rx_tail to the caller /* used for append sz bytes from ptr to rx_tail, update rx_tail and return the updated rx_tail to the caller */
//after putting, rx_tail must be still larger than rx_end. /* after putting, rx_tail must be still larger than rx_end. */
unsigned char * prev_rx_tail; unsigned char * prev_rx_tail;
if(precvframe==NULL) if(precvframe==NULL)
@ -460,10 +460,10 @@ __inline static u8 *recvframe_put(union recv_frame *precvframe, sint sz)
__inline static u8 *recvframe_pull_tail(union recv_frame *precvframe, sint sz) __inline static u8 *recvframe_pull_tail(union recv_frame *precvframe, sint sz)
{ {
// rmv data from rx_tail (by yitsen) /* rmv data from rx_tail (by yitsen) */
//used for extract sz bytes from rx_end, update rx_end and return the updated rx_end to the caller /* used for extract sz bytes from rx_end, update rx_end and return the updated rx_end to the caller */
//after pulling, rx_end must be still larger than rx_data. /* after pulling, rx_end must be still larger than rx_data. */
if(precvframe==NULL) if(precvframe==NULL)
return NULL; return NULL;
@ -496,9 +496,9 @@ __inline static unsigned char *get_rxbuf_desc(union recv_frame *precvframe)
__inline static union recv_frame *rxmem_to_recvframe(u8 *rxmem) __inline static union recv_frame *rxmem_to_recvframe(u8 *rxmem)
{ {
//due to the design of 2048 bytes alignment of recv_frame, we can reference the union recv_frame /* due to the design of 2048 bytes alignment of recv_frame, we can reference the union recv_frame */
//from any given member of recv_frame. /* from any given member of recv_frame. */
// rxmem indicates the any member/address in recv_frame /* rxmem indicates the any member/address in recv_frame */
return (union recv_frame*)(((SIZE_PTR)rxmem >> RXFRAME_ALIGN) << RXFRAME_ALIGN); return (union recv_frame*)(((SIZE_PTR)rxmem >> RXFRAME_ALIGN) << RXFRAME_ALIGN);
@ -516,7 +516,7 @@ __inline static union recv_frame *pkt_to_recvframe(struct sk_buff *pkt)
__inline static u8 *pkt_to_recvmem(struct sk_buff *pkt) __inline static u8 *pkt_to_recvmem(struct sk_buff *pkt)
{ {
// return the rx_head /* return the rx_head */
union recv_frame * precv_frame = pkt_to_recvframe(pkt); union recv_frame * precv_frame = pkt_to_recvframe(pkt);
@ -526,7 +526,7 @@ __inline static u8 *pkt_to_recvmem(struct sk_buff *pkt)
__inline static u8 *pkt_to_recvdata(struct sk_buff *pkt) __inline static u8 *pkt_to_recvdata(struct sk_buff *pkt)
{ {
// return the rx_data /* return the rx_data */
union recv_frame * precv_frame =pkt_to_recvframe(pkt); union recv_frame * precv_frame =pkt_to_recvframe(pkt);
@ -543,9 +543,9 @@ __inline static sint get_recvframe_len(union recv_frame *precvframe)
__inline static s32 translate_percentage_to_dbm(u32 SignalStrengthIndex) __inline static s32 translate_percentage_to_dbm(u32 SignalStrengthIndex)
{ {
s32 SignalPower; // in dBm. s32 SignalPower; /* in dBm. */
// Translate to dBm (x=0.5y-95). /* Translate to dBm (x=0.5y-95). */
SignalPower = (s32)((SignalStrengthIndex + 1) >> 1); SignalPower = (s32)((SignalStrengthIndex + 1) >> 1);
SignalPower -= 95; SignalPower -= 95;

31
include/rtw_rf.h
View file

@ -1,22 +1,17 @@
/****************************************************************************** /******************************************************************************
* *
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as * under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation. * published by the Free Software Foundation.
* *
* This program is distributed in the hope that it will be useful, but WITHOUT * This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details. * more details.
* *
* You should have received a copy of the GNU General Public License along with ******************************************************************************/
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTW_RF_H_ #ifndef __RTW_RF_H_
#define __RTW_RF_H_ #define __RTW_RF_H_

100
include/rtw_security.h
View file

@ -32,11 +32,11 @@
#define _TKIP_WTMIC_ 0x3 #define _TKIP_WTMIC_ 0x3
#define _AES_ 0x4 #define _AES_ 0x4
#define _WEP104_ 0x5 #define _WEP104_ 0x5
#define _WEP_WPA_MIXED_ 0x07 // WEP + WPA #define _WEP_WPA_MIXED_ 0x07 /* WEP + WPA */
#define _SMS4_ 0x06 #define _SMS4_ 0x06
#ifdef CONFIG_IEEE80211W #ifdef CONFIG_IEEE80211W
#define _BIP_ 0x8 #define _BIP_ 0x8
#endif //CONFIG_IEEE80211W #endif /* CONFIG_IEEE80211W */
#define is_wep_enc(alg) (((alg) == _WEP40_) || ((alg) == _WEP104_)) #define is_wep_enc(alg) (((alg) == _WEP40_) || ((alg) == _WEP104_))
#define _WPA_IE_ID_ 0xdd #define _WPA_IE_ID_ 0xdd
@ -47,11 +47,11 @@
#define AES_PRIV_SIZE (4 * 44) #define AES_PRIV_SIZE (4 * 44)
typedef enum { typedef enum {
ENCRYP_PROTOCOL_OPENSYS, //open system ENCRYP_PROTOCOL_OPENSYS, /* open system */
ENCRYP_PROTOCOL_WEP, //WEP ENCRYP_PROTOCOL_WEP, /* WEP */
ENCRYP_PROTOCOL_WPA, //WPA ENCRYP_PROTOCOL_WPA, /* WPA */
ENCRYP_PROTOCOL_WPA2, //WPA2 ENCRYP_PROTOCOL_WPA2, /* WPA2 */
ENCRYP_PROTOCOL_WAPI, //WAPI: Not support in this version ENCRYP_PROTOCOL_WAPI, /* WAPI: Not support in this version */
ENCRYP_PROTOCOL_MAX ENCRYP_PROTOCOL_MAX
}ENCRYP_PROTOCOL_E; }ENCRYP_PROTOCOL_E;
@ -117,84 +117,78 @@ typedef struct _RT_PMKID_LIST
struct security_priv struct security_priv
{ {
u32 dot11AuthAlgrthm; // 802.11 auth, could be open, shared, 8021x and authswitch u32 dot11AuthAlgrthm; /* 802.11 auth, could be open, shared, 8021x and authswitch */
u32 dot11PrivacyAlgrthm; // This specify the privacy for shared auth. algorithm. u32 dot11PrivacyAlgrthm; /* This specify the privacy for shared auth. algorithm. */
/* WEP */ /* WEP */
u32 dot11PrivacyKeyIndex; // this is only valid for legendary wep, 0~3 for key id. (tx key index) u32 dot11PrivacyKeyIndex; /* this is only valid for legendary wep, 0~3 for key id. (tx key index) */
union Keytype dot11DefKey[4]; // this is only valid for def. key union Keytype dot11DefKey[4]; /* this is only valid for def. key */
u32 dot11DefKeylen[4]; u32 dot11DefKeylen[4];
u8 key_mask; /* use to restore wep key after hal_init */ u8 key_mask; /* use to restore wep key after hal_init */
u32 dot118021XGrpPrivacy; // This specify the privacy algthm. used for Grp key u32 dot118021XGrpPrivacy; /* This specify the privacy algthm. used for Grp key */
u32 dot118021XGrpKeyid; // key id used for Grp Key ( tx key index) u32 dot118021XGrpKeyid; /* key id used for Grp Key ( tx key index) */
union Keytype dot118021XGrpKey[4]; // 802.1x Group Key, for inx0 and inx1 union Keytype dot118021XGrpKey[4]; /* 802.1x Group Key, for inx0 and inx1 */
union Keytype dot118021XGrptxmickey[4]; union Keytype dot118021XGrptxmickey[4];
union Keytype dot118021XGrprxmickey[4]; union Keytype dot118021XGrprxmickey[4];
union pn48 dot11Grptxpn; // PN48 used for Grp Key xmit. union pn48 dot11Grptxpn; /* PN48 used for Grp Key xmit. */
union pn48 dot11Grprxpn; // PN48 used for Grp Key recv. union pn48 dot11Grprxpn; /* PN48 used for Grp Key recv. */
#ifdef CONFIG_IEEE80211W #ifdef CONFIG_IEEE80211W
u32 dot11wBIPKeyid; // key id used for BIP Key ( tx key index) u32 dot11wBIPKeyid; /* key id used for BIP Key ( tx key index) */
union Keytype dot11wBIPKey[6]; // BIP Key, for index4 and index5 union Keytype dot11wBIPKey[6]; /* BIP Key, for index4 and index5 */
union pn48 dot11wBIPtxpn; // PN48 used for Grp Key xmit. union pn48 dot11wBIPtxpn; /* PN48 used for Grp Key xmit. */
union pn48 dot11wBIPrxpn; // PN48 used for Grp Key recv. union pn48 dot11wBIPrxpn; /* PN48 used for Grp Key recv. */
#endif //CONFIG_IEEE80211W #endif /* CONFIG_IEEE80211W */
#ifdef CONFIG_AP_MODE #ifdef CONFIG_AP_MODE
//extend security capabilities for AP_MODE /* extend security capabilities for AP_MODE */
unsigned int dot8021xalg;//0:disable, 1:psk, 2:802.1x unsigned int dot8021xalg;/* 0:disable, 1:psk, 2:802.1x */
unsigned int wpa_psk;//0:disable, bit(0): WPA, bit(1):WPA2 unsigned int wpa_psk;/* 0:disable, bit(0): WPA, bit(1):WPA2 */
unsigned int wpa_group_cipher; unsigned int wpa_group_cipher;
unsigned int wpa2_group_cipher; unsigned int wpa2_group_cipher;
unsigned int wpa_pairwise_cipher; unsigned int wpa_pairwise_cipher;
unsigned int wpa2_pairwise_cipher; unsigned int wpa2_pairwise_cipher;
#endif #endif
u8 wps_ie[MAX_WPS_IE_LEN];//added in assoc req u8 wps_ie[MAX_WPS_IE_LEN];/* added in assoc req */
int wps_ie_len; int wps_ie_len;
u8 binstallGrpkey; u8 binstallGrpkey;
#ifdef CONFIG_IEEE80211W #ifdef CONFIG_IEEE80211W
u8 binstallBIPkey; u8 binstallBIPkey;
#endif //CONFIG_IEEE80211W #endif /* CONFIG_IEEE80211W */
u8 busetkipkey; u8 busetkipkey;
u8 bcheck_grpkey; u8 bcheck_grpkey;
u8 bgrpkey_handshake; u8 bgrpkey_handshake;
s32 sw_encrypt;//from registry_priv s32 sw_encrypt;/* from registry_priv */
s32 sw_decrypt;//from registry_priv s32 sw_decrypt;/* from registry_priv */
s32 hw_decrypted;//if the rx packets is hw_decrypted==false, it means the hw has not been ready. s32 hw_decrypted;/* if the rx packets is hw_decrypted==false, it means the hw has not been ready. */
//keeps the auth_type & enc_status from upper layer ioctl(wpa_supplicant or wzc) /* keeps the auth_type & enc_status from upper layer ioctl(wpa_supplicant or wzc) */
u32 ndisauthtype; // enum NDIS_802_11_AUTHENTICATION_MODE u32 ndisauthtype; /* enum NDIS_802_11_AUTHENTICATION_MODE */
u32 ndisencryptstatus; // NDIS_802_11_ENCRYPTION_STATUS u32 ndisencryptstatus; /* NDIS_802_11_ENCRYPTION_STATUS */
struct wlan_bssid_ex sec_bss; //for joinbss (h2c buffer) usage struct wlan_bssid_ex sec_bss; /* for joinbss (h2c buffer) usage */
struct ndis_802_11_wep ndiswep; struct ndis_802_11_wep ndiswep;
u8 assoc_info[600]; u8 assoc_info[600];
u8 szofcapability[256]; //for wpa2 usage u8 szofcapability[256]; /* for wpa2 usage */
u8 oidassociation[512]; //for wpa/wpa2 usage u8 oidassociation[512]; /* for wpa/wpa2 usage */
u8 authenticator_ie[256]; //store ap security information element u8 authenticator_ie[256]; /* store ap security information element */
u8 supplicant_ie[256]; //store sta security information element u8 supplicant_ie[256]; /* store sta security information element */
//for tkip countermeasure /* for tkip countermeasure */
u32 last_mic_err_time; u32 last_mic_err_time;
u8 btkip_countermeasure; u8 btkip_countermeasure;
u8 btkip_wait_report; u8 btkip_wait_report;
u32 btkip_countermeasure_time; u32 btkip_countermeasure_time;
//--------------------------------------------------------------------------- /* For WPA2 Pre-Authentication. */
// For WPA2 Pre-Authentication. RT_PMKID_LIST PMKIDList[NUM_PMKID_CACHE]; /* Renamed from PreAuthKey[NUM_PRE_AUTH_KEY]. Annie, 2006-10-13. */
//---------------------------------------------------------------------------
//u8 RegEnablePreAuth; // Default value: Pre-Authentication enabled or not, from registry "EnablePreAuth". Added by Annie, 2005-11-01.
//u8 EnablePreAuthentication; // Current Value: Pre-Authentication enabled or not.
RT_PMKID_LIST PMKIDList[NUM_PMKID_CACHE]; // Renamed from PreAuthKey[NUM_PRE_AUTH_KEY]. Annie, 2006-10-13.
u8 PMKIDIndex; u8 PMKIDIndex;
//u32 PMKIDCount; // Added by Annie, 2006-10-13.
//u8 szCapability[256]; // For WPA2-PSK using zero-config, by Annie, 2005-09-20.
u8 bWepDefaultKeyIdxSet; u8 bWepDefaultKeyIdxSet;
}; };
@ -272,10 +266,10 @@ do{\
struct mic_data struct mic_data
{ {
u32 K0, K1; // Key u32 K0, K1; /* Key */
u32 L, R; // Current state u32 L, R; /* Current state */
u32 M; // Message accumulator (single word) u32 M; /* Message accumulator (single word) */
u32 nBytesInM; // # bytes in M u32 nBytesInM; /* # bytes in M */
}; };
extern const u32 Te0[256]; extern const u32 Te0[256];
@ -402,7 +396,7 @@ static const unsigned long K[64] = {
#endif #endif
#ifdef CONFIG_IEEE80211W #ifdef CONFIG_IEEE80211W
int omac1_aes_128(u8 *key, u8 *data, size_t data_len, u8 *mac); int omac1_aes_128(u8 *key, u8 *data, size_t data_len, u8 *mac);
#endif //CONFIG_IEEE80211W #endif /* CONFIG_IEEE80211W */
void rtw_secmicsetkey(struct mic_data *pmicdata, u8 * key ); void rtw_secmicsetkey(struct mic_data *pmicdata, u8 * key );
void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b ); void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b );
void rtw_secmicappend(struct mic_data *pmicdata, u8 * src, u32 nBytes ); void rtw_secmicappend(struct mic_data *pmicdata, u8 * src, u32 nBytes );
@ -425,10 +419,10 @@ u32 rtw_tkip_decrypt(struct adapter *padapter, u8 *precvframe);
void rtw_wep_decrypt(struct adapter *padapter, u8 *precvframe); void rtw_wep_decrypt(struct adapter *padapter, u8 *precvframe);
#ifdef CONFIG_IEEE80211W #ifdef CONFIG_IEEE80211W
u32 rtw_BIP_verify(struct adapter *padapter, u8 *precvframe); u32 rtw_BIP_verify(struct adapter *padapter, u8 *precvframe);
#endif //CONFIG_IEEE80211W #endif /* CONFIG_IEEE80211W */
void rtw_use_tkipkey_handler(void* FunctionContext); void rtw_use_tkipkey_handler(void* FunctionContext);
void rtw_sec_restore_wep_key(struct adapter *adapter); void rtw_sec_restore_wep_key(struct adapter *adapter);
u8 rtw_handle_tkip_countermeasure(struct adapter* adapter, const char *caller); u8 rtw_handle_tkip_countermeasure(struct adapter* adapter, const char *caller);
#endif //__RTL871X_SECURITY_H_ #endif /* __RTL871X_SECURITY_H_ */

62
include/rtw_xmit.h
View file

@ -24,17 +24,17 @@
#include <osdep_service.h> #include <osdep_service.h>
#include <drv_types.h> #include <drv_types.h>
#define MAX_XMITBUF_SZ (20480) // 20k #define MAX_XMITBUF_SZ (20480) /* 20k */
#ifdef CONFIG_SINGLE_XMIT_BUF #ifdef CONFIG_SINGLE_XMIT_BUF
#define NR_XMITBUFF (1) #define NR_XMITBUFF (1)
#else #else
#define NR_XMITBUFF (4) #define NR_XMITBUFF (4)
#endif //CONFIG_SINGLE_XMIT_BUF #endif /* CONFIG_SINGLE_XMIT_BUF */
#define XMITBUF_ALIGN_SZ 512 #define XMITBUF_ALIGN_SZ 512
// xmit extension buff defination /* xmit extension buff defination */
#define MAX_XMIT_EXTBUF_SZ (1536) #define MAX_XMIT_EXTBUF_SZ (1536)
#define NR_XMIT_EXTBUFF (32) #define NR_XMIT_EXTBUFF (32)
@ -123,7 +123,7 @@ struct hw_xmit {
int accnt; int accnt;
}; };
//reduce size /* reduce size */
struct pkt_attrib struct pkt_attrib
{ {
u8 type; u8 type;
@ -132,12 +132,12 @@ struct pkt_attrib
u8 dhcp_pkt; u8 dhcp_pkt;
u16 ether_type; u16 ether_type;
u16 seqnum; u16 seqnum;
u16 pkt_hdrlen; //the original 802.3 pkt header len u16 pkt_hdrlen; /* the original 802.3 pkt header len */
u16 hdrlen; //the WLAN Header Len u16 hdrlen; /* the WLAN Header Len */
u32 pktlen; //the original 802.3 pkt raw_data len (not include ether_hdr data) u32 pktlen; /* the original 802.3 pkt raw_data len (not include ether_hdr data) */
u32 last_txcmdsz; u32 last_txcmdsz;
u8 nr_frags; u8 nr_frags;
u8 encrypt; //when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith u8 encrypt; /* when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith */
u8 iv_len; u8 iv_len;
u8 icv_len; u8 icv_len;
u8 iv[18]; u8 iv[18];
@ -145,7 +145,7 @@ struct pkt_attrib
u8 priority; u8 priority;
u8 ack_policy; u8 ack_policy;
u8 mac_id; u8 mac_id;
u8 vcs_mode; //virtual carrier sense method u8 vcs_mode; /* virtual carrier sense method */
u8 dst[ETH_ALEN]; u8 dst[ETH_ALEN];
u8 src[ETH_ALEN]; u8 src[ETH_ALEN];
u8 ta[ETH_ALEN]; u8 ta[ETH_ALEN];
@ -153,14 +153,14 @@ struct pkt_attrib
u8 key_idx; u8 key_idx;
u8 qos_en; u8 qos_en;
u8 ht_en; u8 ht_en;
u8 raid;//rate adpative id u8 raid;/* rate adpative id */
u8 bwmode; u8 bwmode;
u8 ch_offset;//PRIME_CHNL_OFFSET u8 ch_offset;/* PRIME_CHNL_OFFSET */
u8 sgi;//short GI u8 sgi;/* short GI */
u8 ampdu_en;//tx ampdu enable u8 ampdu_en;/* tx ampdu enable */
u8 mdata;//more data bit u8 mdata;/* more data bit */
u8 pctrl;//per packet txdesc control enable u8 pctrl;/* per packet txdesc control enable */
u8 triggered;//for ap mode handling Power Saving sta u8 triggered;/* for ap mode handling Power Saving sta */
u8 qsel; u8 qsel;
u8 eosp; u8 eosp;
u8 rate; u8 rate;
@ -224,7 +224,7 @@ struct xmit_buf
void *priv_data; void *priv_data;
u16 ext_tag; // 0: Normal xmitbuf, 1: extension xmitbuf. u16 ext_tag; /* 0: Normal xmitbuf, 1: extension xmitbuf. */
u16 flags; u16 flags;
u32 alloc_sz; u32 alloc_sz;
@ -283,12 +283,12 @@ struct sta_xmit_priv
{ {
spinlock_t lock; spinlock_t lock;
sint option; sint option;
sint apsd_setting; //When bit mask is on, the associated edca queue supports APSD. sint apsd_setting; /* When bit mask is on, the associated edca queue supports APSD. */
struct tx_servq be_q; //priority == 0,3 struct tx_servq be_q; /* priority == 0,3 */
struct tx_servq bk_q; //priority == 1,2 struct tx_servq bk_q; /* priority == 1,2 */
struct tx_servq vi_q; //priority == 4,5 struct tx_servq vi_q; /* priority == 4,5 */
struct tx_servq vo_q; //priority == 6,7 struct tx_servq vo_q; /* priority == 6,7 */
struct list_head legacy_dz; struct list_head legacy_dz;
struct list_head apsd; struct list_head apsd;
@ -299,7 +299,7 @@ struct sta_xmit_priv
struct hw_txqueue { struct hw_txqueue {
volatile sint head; volatile sint head;
volatile sint tail; volatile sint tail;
volatile sint free_sz; //in units of 64 bytes volatile sint free_sz; /* in units of 64 bytes */
volatile sint free_cmdsz; volatile sint free_cmdsz;
volatile sint txsz[8]; volatile sint txsz[8];
uint ff_hwaddr; uint ff_hwaddr;
@ -341,7 +341,7 @@ struct xmit_priv {
u8 vcs_setting; u8 vcs_setting;
u8 vcs; u8 vcs;
u8 vcs_type; u8 vcs_type;
//u16 rts_thresh; /* u16 rts_thresh; */
u64 tx_bytes; u64 tx_bytes;
u64 tx_pkts; u64 tx_pkts;
@ -352,13 +352,13 @@ struct xmit_priv {
struct hw_xmit *hwxmits; struct hw_xmit *hwxmits;
u8 hwxmit_entry; u8 hwxmit_entry;
u8 wmm_para_seq[4];//sequence for wmm ac parameter strength from large to small. it's value is 0->vo, 1->vi, 2->be, 3->bk. u8 wmm_para_seq[4];/* sequence for wmm ac parameter strength from large to small. it's value is 0->vo, 1->vi, 2->be, 3->bk. */
struct semaphore tx_retevt;//all tx return event; struct semaphore tx_retevt;/* all tx return event; */
u8 txirp_cnt;// u8 txirp_cnt;/* */
struct tasklet_struct xmit_tasklet; struct tasklet_struct xmit_tasklet;
//per AC pending irp /* per AC pending irp */
int beq_cnt; int beq_cnt;
int bkq_cnt; int bkq_cnt;
int viq_cnt; int viq_cnt;
@ -408,7 +408,7 @@ extern u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib);
extern s32 rtw_xmitframe_coalesce(struct adapter *padapter, struct sk_buff *pkt, struct xmit_frame *pxmitframe); extern s32 rtw_xmitframe_coalesce(struct adapter *padapter, struct sk_buff *pkt, struct xmit_frame *pxmitframe);
#ifdef CONFIG_IEEE80211W #ifdef CONFIG_IEEE80211W
extern s32 rtw_mgmt_xmitframe_coalesce(struct adapter *padapter, struct sk_buff *pkt, struct xmit_frame *pxmitframe); extern s32 rtw_mgmt_xmitframe_coalesce(struct adapter *padapter, struct sk_buff *pkt, struct xmit_frame *pxmitframe);
#endif //CONFIG_IEEE80211W #endif /* CONFIG_IEEE80211W */
s32 _rtw_init_hw_txqueue(struct hw_txqueue* phw_txqueue, u8 ac_tag); s32 _rtw_init_hw_txqueue(struct hw_txqueue* phw_txqueue, u8 ac_tag);
void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv); void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv);
@ -440,7 +440,7 @@ u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe);
int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms); int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms);
void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status); void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status);
//include after declaring struct xmit_buf, in order to avoid warning /* include after declaring struct xmit_buf, in order to avoid warning */
#include <xmit_osdep.h> #include <xmit_osdep.h>
#endif //_RTL871X_XMIT_H_ #endif /* _RTL871X_XMIT_H_ */

126
include/sta_info.h
View file

@ -30,17 +30,17 @@
#define NUM_ACL 16 #define NUM_ACL 16
//if mode ==0, then the sta is allowed once the addr is hit. /* if mode ==0, then the sta is allowed once the addr is hit. */
//if mode ==1, then the sta is rejected once the addr is non-hit. /* if mode ==1, then the sta is rejected once the addr is non-hit. */
struct rtw_wlan_acl_node { struct rtw_wlan_acl_node {
struct list_head list; struct list_head list;
u8 addr[ETH_ALEN]; u8 addr[ETH_ALEN];
u8 valid; u8 valid;
}; };
//mode=0, disable /* mode=0, disable */
//mode=1, accept unless in deny list /* mode=1, accept unless in deny list */
//mode=2, deny unless in accept list /* mode=2, deny unless in accept list */
struct wlan_acl_pool { struct wlan_acl_pool {
int mode; int mode;
int num; int num;
@ -88,8 +88,8 @@ struct stainfo_stats {
struct sta_info { struct sta_info {
spinlock_t lock; spinlock_t lock;
struct list_head list; //free_sta_queue struct list_head list; /* free_sta_queue */
struct list_head hash_list; //sta_hash struct list_head hash_list; /* sta_hash */
struct adapter *padapter; struct adapter *padapter;
struct sta_xmit_priv sta_xmitpriv; struct sta_xmit_priv sta_xmitpriv;
@ -104,16 +104,16 @@ struct sta_info {
uint qos_option; uint qos_option;
u8 hwaddr[ETH_ALEN]; u8 hwaddr[ETH_ALEN];
uint ieee8021x_blocked; //0: allowed, 1:blocked uint ieee8021x_blocked; /* 0: allowed, 1:blocked */
uint dot118021XPrivacy; //aes, tkip... uint dot118021XPrivacy; /* aes, tkip... */
union Keytype dot11tkiptxmickey; union Keytype dot11tkiptxmickey;
union Keytype dot11tkiprxmickey; union Keytype dot11tkiprxmickey;
union Keytype dot118021x_UncstKey; union Keytype dot118021x_UncstKey;
union pn48 dot11txpn; // PN48 used for Unicast xmit. union pn48 dot11txpn; /* PN48 used for Unicast xmit. */
#ifdef CONFIG_IEEE80211W #ifdef CONFIG_IEEE80211W
union pn48 dot11wtxpn; // PN48 used for Unicast mgmt xmit. union pn48 dot11wtxpn; /* PN48 used for Unicast mgmt xmit. */
#endif //CONFIG_IEEE80211W #endif /* CONFIG_IEEE80211W */
union pn48 dot11rxpn; // PN48 used for Unicast recv. union pn48 dot11rxpn; /* PN48 used for Unicast recv. */
u8 bssrateset[16]; u8 bssrateset[16];
@ -127,29 +127,29 @@ struct sta_info {
u8 raid; u8 raid;
u8 init_rate; u8 init_rate;
u32 ra_mask; u32 ra_mask;
u8 wireless_mode; // NETWORK_TYPE u8 wireless_mode; /* NETWORK_TYPE */
struct stainfo_stats sta_stats; struct stainfo_stats sta_stats;
//for A-MPDU TX, ADDBA timeout check /* for A-MPDU TX, ADDBA timeout check */
struct timer_list addba_retry_timer; struct timer_list addba_retry_timer;
//for A-MPDU Rx reordering buffer control /* for A-MPDU Rx reordering buffer control */
struct recv_reorder_ctrl recvreorder_ctrl[16]; struct recv_reorder_ctrl recvreorder_ctrl[16];
//for A-MPDU Tx /* for A-MPDU Tx */
//unsigned char ampdu_txen_bitmap; /* unsigned char ampdu_txen_bitmap; */
u16 BA_starting_seqctrl[16]; u16 BA_starting_seqctrl[16];
struct ht_priv htpriv; struct ht_priv htpriv;
//Notes: /* Notes: */
//STA_Mode: /* STA_Mode: */
//curr_network(mlme_priv/security_priv/qos/ht) + sta_info: (STA & AP) CAP/INFO /* curr_network(mlme_priv/security_priv/qos/ht) + sta_info: (STA & AP) CAP/INFO */
//scan_q: AP CAP/INFO /* scan_q: AP CAP/INFO */
//AP_Mode: /* AP_Mode: */
//curr_network(mlme_priv/security_priv/qos/ht) : AP CAP/INFO /* curr_network(mlme_priv/security_priv/qos/ht) : AP CAP/INFO */
//sta_info: (AP & STA) CAP/INFO /* sta_info: (AP & STA) CAP/INFO */
#ifdef CONFIG_AP_MODE #ifdef CONFIG_AP_MODE
@ -164,8 +164,8 @@ struct sta_info {
u16 capability; u16 capability;
int flags; int flags;
int dot8021xalg;//0:disable, 1:psk, 2:802.1x int dot8021xalg;/* 0:disable, 1:psk, 2:802.1x */
int wpa_psk;//0:disable, bit(0): WPA, bit(1):WPA2 int wpa_psk;/* 0:disable, bit(0): WPA, bit(1):WPA2 */
int wpa_group_cipher; int wpa_group_cipher;
int wpa2_group_cipher; int wpa2_group_cipher;
int wpa_pairwise_cipher; int wpa_pairwise_cipher;
@ -186,7 +186,7 @@ struct sta_info {
u8 qos_info; u8 qos_info;
u8 max_sp_len; u8 max_sp_len;
u8 uapsd_bk;//BIT(0): Delivery enabled, BIT(1): Trigger enabled u8 uapsd_bk;/* BIT(0): Delivery enabled, BIT(1): Trigger enabled */
u8 uapsd_be; u8 uapsd_be;
u8 uapsd_vi; u8 uapsd_vi;
u8 uapsd_vo; u8 uapsd_vo;
@ -195,71 +195,69 @@ struct sta_info {
unsigned int sleepq_ac_len; unsigned int sleepq_ac_len;
#ifdef CONFIG_P2P #ifdef CONFIG_P2P
//p2p priv data /* p2p priv data */
u8 is_p2p_device; u8 is_p2p_device;
u8 p2p_status_code; u8 p2p_status_code;
//p2p client info /* p2p client info */
u8 dev_addr[ETH_ALEN]; u8 dev_addr[ETH_ALEN];
//u8 iface_addr[ETH_ALEN];//= hwaddr[ETH_ALEN]
u8 dev_cap; u8 dev_cap;
u16 config_methods; u16 config_methods;
u8 primary_dev_type[8]; u8 primary_dev_type[8];
u8 num_of_secdev_type; u8 num_of_secdev_type;
u8 secdev_types_list[32];// 32/8 == 4; u8 secdev_types_list[32];/* 32/8 == 4; */
u16 dev_name_len; u16 dev_name_len;
u8 dev_name[32]; u8 dev_name[32];
#endif //CONFIG_P2P #endif /* CONFIG_P2P */
u8 under_exist_checking; u8 under_exist_checking;
u8 keep_alive_trycnt; u8 keep_alive_trycnt;
#endif // CONFIG_AP_MODE #endif /* CONFIG_AP_MODE */
u8 *passoc_req; u8 *passoc_req;
u32 assoc_req_len; u32 assoc_req_len;
#ifdef DBG_TRX_STA_PKTS #ifdef DBG_TRX_STA_PKTS
//per AC dbg irp cnts /* per AC dbg irp cnts */
int rx_be_cnt; int rx_be_cnt;
int rx_bk_cnt; int rx_bk_cnt;
int rx_vi_cnt; int rx_vi_cnt;
int rx_vo_cnt; int rx_vo_cnt;
//per AC dbg irp cnts /* per AC dbg irp cnts */
int tx_be_cnt; int tx_be_cnt;
int tx_bk_cnt; int tx_bk_cnt;
int tx_vi_cnt; int tx_vi_cnt;
int tx_vo_cnt; int tx_vo_cnt;
#endif #endif
//for DM /* for DM */
RSSI_STA rssi_stat; RSSI_STA rssi_stat;
//ODM_STA_INFO_T /* ODM_STA_INFO_T */
// ================ODM Relative Info======================= /* ================ODM Relative Info======================= */
// Please be care, dont declare too much structure here. It will cost memory * STA support num. /* Please be care, dont declare too much structure here. It will cost memory * STA support num. */
// /* */
// /* */
// 2011/10/20 MH Add for ODM STA info. /* 2011/10/20 MH Add for ODM STA info. */
// /* */
// Driver Write /* Driver Write */
u8 bValid; // record the sta status link or not? u8 bValid; /* record the sta status link or not? */
//u8 WirelessMode; // u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */
u8 IOTPeer; // Enum value. HT_IOT_PEER_E /* ODM Write */
// ODM Write /* 1 PHY_STATUS_INFO */
//1 PHY_STATUS_INFO u8 RSSI_Path[4]; /* */
u8 RSSI_Path[4]; //
u8 RSSI_Ave; u8 RSSI_Ave;
u8 RXEVM[4]; u8 RXEVM[4];
u8 RXSNR[4]; u8 RXSNR[4];
u8 rssi_level; //for Refresh RA mask u8 rssi_level; /* for Refresh RA mask */
// ODM Write /* ODM Write */
//1 TX_INFO (may changed by IC) /* 1 TX_INFO (may changed by IC) */
//TX_INFO_T pTxInfo; // Define in IC folder. Move lower layer. /* TX_INFO_T pTxInfo; Define in IC folder. Move lower layer. */
// /* */
// ================ODM Relative Info======================= /* ================ODM Relative Info======================= */
// /* */
/* To store the sequence number of received management frame */ /* To store the sequence number of received management frame */
u16 RxMgmtFrameSeqNum; u16 RxMgmtFrameSeqNum;
@ -368,9 +366,9 @@ struct sta_priv {
u8 asoc_list_cnt; u8 asoc_list_cnt;
u8 auth_list_cnt; u8 auth_list_cnt;
unsigned int auth_to; //sec, time to expire in authenticating. unsigned int auth_to; /* sec, time to expire in authenticating. */
unsigned int assoc_to; //sec, time to expire before associating. unsigned int assoc_to; /* sec, time to expire before associating. */
unsigned int expire_to; //sec , time to expire after associated. unsigned int expire_to; /* sec , time to expire after associated. */
/* pointers to STA info; based on allocated AID or NULL if AID free /* pointers to STA info; based on allocated AID or NULL if AID free
* AID is in the range 1-2007, so sta_aid[0] corresponders to AID 1 * AID is in the range 1-2007, so sta_aid[0] corresponders to AID 1
@ -378,8 +376,8 @@ struct sta_priv {
*/ */
struct sta_info *sta_aid[NUM_STA]; struct sta_info *sta_aid[NUM_STA];
u16 sta_dz_bitmap;//only support 15 stations, staion aid bitmap for sleeping sta. u16 sta_dz_bitmap;/* only support 15 stations, staion aid bitmap for sleeping sta. */
u16 tim_bitmap;//only support 15 stations, aid=0~15 mapping bit0~bit15 u16 tim_bitmap;/* only support 15 stations, aid=0~15 mapping bit0~bit15 */
u16 max_num_sta; u16 max_num_sta;
@ -420,4 +418,4 @@ extern u32 rtw_init_bcmc_stainfo(struct adapter* padapter);
extern struct sta_info* rtw_get_bcmc_stainfo(struct adapter* padapter); extern struct sta_info* rtw_get_bcmc_stainfo(struct adapter* padapter);
extern u8 rtw_access_ctrl(struct adapter *padapter, u8 *mac_addr); extern u8 rtw_access_ctrl(struct adapter *padapter, u8 *mac_addr);
#endif //_STA_INFO_H_ #endif /* _STA_INFO_H_ */

4
include/usb_hal.h
View file

@ -25,5 +25,5 @@ void rtl8188eu_set_hal_ops(struct adapter * padapter);
#ifdef CONFIG_INTEL_PROXIM #ifdef CONFIG_INTEL_PROXIM
extern struct adapter *rtw_usb_get_sw_pointer(void); extern struct adapter *rtw_usb_get_sw_pointer(void);
#endif //CONFIG_INTEL_PROXIM #endif /* CONFIG_INTEL_PROXIM */
#endif //__USB_HAL_H__ #endif /* __USB_HAL_H__ */

4
include/usb_ops.h
View file

@ -35,7 +35,7 @@ enum{
VENDOR_READ = 0x01, VENDOR_READ = 0x01,
}; };
#define ALIGNMENT_UNIT 16 #define ALIGNMENT_UNIT 16
#define MAX_VENDOR_REQ_CMD_SIZE 254 //8188cu SIE Support #define MAX_VENDOR_REQ_CMD_SIZE 254 /* 8188cu SIE Support */
#define MAX_USB_IO_CTL_SIZE (MAX_VENDOR_REQ_CMD_SIZE +ALIGNMENT_UNIT) #define MAX_USB_IO_CTL_SIZE (MAX_VENDOR_REQ_CMD_SIZE +ALIGNMENT_UNIT)
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12)) #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12))
@ -73,4 +73,4 @@ static inline u8 rtw_usb_bulk_size_boundary(struct adapter * padapter,int buf_le
return rst; return rst;
} }
#endif //__USB_OPS_H_ #endif /* __USB_OPS_H_ */

6
include/usb_ops_linux.h
View file

@ -22,13 +22,13 @@
#define VENDOR_CMD_MAX_DATA_LEN 254 #define VENDOR_CMD_MAX_DATA_LEN 254
#define RTW_USB_CONTROL_MSG_TIMEOUT_TEST 10//ms #define RTW_USB_CONTROL_MSG_TIMEOUT_TEST 10/* ms */
#define RTW_USB_CONTROL_MSG_TIMEOUT 500//ms #define RTW_USB_CONTROL_MSG_TIMEOUT 500/* ms */
/* vendor req retry should be in the situation when each vendor req is atomically submitted from others */ /* vendor req retry should be in the situation when each vendor req is atomically submitted from others */
#define MAX_USBCTRL_VENDORREQ_TIMES 10 #define MAX_USBCTRL_VENDORREQ_TIMES 10
#define RTW_USB_BULKOUT_TIMEOUT 5000//ms #define RTW_USB_BULKOUT_TIMEOUT 5000/* ms */
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)) #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18))
#define _usbctrl_vendorreq_async_callback(urb, regs) _usbctrl_vendorreq_async_callback(urb) #define _usbctrl_vendorreq_async_callback(urb, regs) _usbctrl_vendorreq_async_callback(urb)

4
include/usb_osintf.h
View file

@ -28,8 +28,8 @@
#define USBD_HALTED(Status) ((ULONG)(Status) >> 30 == 3) #define USBD_HALTED(Status) ((ULONG)(Status) >> 30 == 3)
//uint usb_dvobj_init(struct adapter * adapter); /* uint usb_dvobj_init(struct adapter * adapter); */
//void usb_dvobj_deinit(struct adapter * adapter); /* void usb_dvobj_deinit(struct adapter * adapter); */
u8 usbvendorrequest(struct dvobj_priv *pdvobjpriv, RT_USB_BREQUEST brequest, RT_USB_WVALUE wvalue, u8 windex, void* data, u8 datalen, u8 isdirectionin); u8 usbvendorrequest(struct dvobj_priv *pdvobjpriv, RT_USB_BREQUEST brequest, RT_USB_WVALUE wvalue, u8 windex, void* data, u8 datalen, u8 isdirectionin);
void dhcp_flag_bcast(struct adapter *priv, struct sk_buff *skb); void dhcp_flag_bcast(struct adapter *priv, struct sk_buff *skb);

12
include/usb_vendor_req.h
View file

@ -20,7 +20,7 @@
#ifndef _USB_VENDOR_REQUEST_H_ #ifndef _USB_VENDOR_REQUEST_H_
#define _USB_VENDOR_REQUEST_H_ #define _USB_VENDOR_REQUEST_H_
//4 Set/Get Register related wIndex/Data /* 4 Set/Get Register related wIndex/Data */
#define RT_USB_RESET_MASK_OFF 0 #define RT_USB_RESET_MASK_OFF 0
#define RT_USB_RESET_MASK_ON 1 #define RT_USB_RESET_MASK_ON 1
#define RT_USB_SLEEP_MASK_OFF 0 #define RT_USB_SLEEP_MASK_OFF 0
@ -28,7 +28,7 @@
#define RT_USB_LDO_ON 1 #define RT_USB_LDO_ON 1
#define RT_USB_LDO_OFF 0 #define RT_USB_LDO_OFF 0
//4 Set/Get SYSCLK related wValue or Data /* 4 Set/Get SYSCLK related wValue or Data */
#define RT_USB_SYSCLK_32KHZ 0 #define RT_USB_SYSCLK_32KHZ 0
#define RT_USB_SYSCLK_40MHZ 1 #define RT_USB_SYSCLK_40MHZ 1
#define RT_USB_SYSCLK_60MHZ 2 #define RT_USB_SYSCLK_60MHZ 2
@ -51,9 +51,9 @@ typedef enum _RT_USB_WVALUE {
} RT_USB_WVALUE; } RT_USB_WVALUE;
//bool usbvendorrequest(PCE_USB_DEVICE CEdevice, RT_USB_BREQUEST bRequest, RT_USB_WVALUE wValue, u8 wIndex, void * Data, u8 DataLength, bool isDirectionIn); /* bool usbvendorrequest(PCE_USB_DEVICE CEdevice, RT_USB_BREQUEST bRequest, RT_USB_WVALUE wValue, u8 wIndex, void * Data, u8 DataLength, bool isDirectionIn); */
//bool CEusbGetStatusRequest(PCE_USB_DEVICE CEdevice, IN u16 Op, IN u16 Index, void * Data); /* bool CEusbGetStatusRequest(PCE_USB_DEVICE CEdevice, IN u16 Op, IN u16 Index, void * Data); */
//bool CEusbFeatureRequest(PCE_USB_DEVICE CEdevice, IN u16 Op, IN u16 FeatureSelector, IN u16 Index); /* bool CEusbFeatureRequest(PCE_USB_DEVICE CEdevice, IN u16 Op, IN u16 FeatureSelector, IN u16 Index); */
//bool CEusbGetDescriptorRequest(PCE_USB_DEVICE CEdevice, IN short urbLength, IN u8 DescriptorType, IN u8 Index, IN u16 LanguageId, IN void * TransferBuffer, IN ULONG TransferBufferLength); /* bool CEusbGetDescriptorRequest(PCE_USB_DEVICE CEdevice, IN short urbLength, IN u8 DescriptorType, IN u8 Index, IN u16 LanguageId, IN void * TransferBuffer, IN ULONG TransferBufferLength); */
#endif #endif

78
include/wlan_bssdef.h
View file

@ -36,14 +36,14 @@ enum NDIS_802_11_NETWORK_TYPE {
Ndis802_11DS, Ndis802_11DS,
Ndis802_11OFDM5, Ndis802_11OFDM5,
Ndis802_11OFDM24, Ndis802_11OFDM24,
Ndis802_11NetworkTypeMax // not a real type, defined as an upper bound Ndis802_11NetworkTypeMax /* not a real type, defined as an upper bound */
}; };
struct ndis_802_11_configuration_fh { struct ndis_802_11_configuration_fh {
ULONG Length; // Length of structure ULONG Length; /* Length of structure */
ULONG HopPattern; // As defined by 802.11, MSB set ULONG HopPattern; /* As defined by 802.11, MSB set */
ULONG HopSet; // to one if non-802.11 ULONG HopSet; /* to one if non-802.11 */
ULONG DwellTime; // units are Kusec ULONG DwellTime; /* units are Kusec */
}; };
/* /*
@ -51,13 +51,13 @@ struct ndis_802_11_configuration_fh {
ODI Handler will convert the channel number to freq. number. ODI Handler will convert the channel number to freq. number.
*/ */
struct ndis_802_11_configuration { struct ndis_802_11_configuration {
ULONG Length; // Length of structure ULONG Length; /* Length of structure */
ULONG BeaconPeriod; // units are Kusec ULONG BeaconPeriod; /* units are Kusec */
ULONG ATIMWindow; // units are Kusec ULONG ATIMWindow; /* units are Kusec */
ULONG DSConfig; // Frequency, units are kHz ULONG DSConfig; /* Frequency, units are kHz */
struct ndis_802_11_configuration_fh FHConfig; struct ndis_802_11_configuration_fh FHConfig;
}; };
// struct ndis_802_11_configuration, *Pstruct ndis_802_11_configuration; /* struct ndis_802_11_configuration, *Pstruct ndis_802_11_configuration; */
@ -65,7 +65,7 @@ enum NDIS_802_11_NETWORK_INFRASTRUCTURE {
Ndis802_11IBSS, Ndis802_11IBSS,
Ndis802_11Infrastructure, Ndis802_11Infrastructure,
Ndis802_11AutoUnknown, Ndis802_11AutoUnknown,
Ndis802_11InfrastructureMax, // Not a real value, defined as upper bound Ndis802_11InfrastructureMax, /* Not a real value, defined as upper bound */
Ndis802_11APMode Ndis802_11APMode
}; };
@ -100,7 +100,7 @@ enum NDIS_802_11_AUTHENTICATION_MODE {
Ndis802_11AuthModeWPAPSK, Ndis802_11AuthModeWPAPSK,
Ndis802_11AuthModeWPANone, Ndis802_11AuthModeWPANone,
Ndis802_11AuthModeWAPI, Ndis802_11AuthModeWAPI,
Ndis802_11AuthModeMax // Not a real mode, defined as upper bound Ndis802_11AuthModeMax /* Not a real mode, defined as upper bound */
}; };
enum NDIS_802_11_WEP_STATUS { enum NDIS_802_11_WEP_STATUS {
@ -130,29 +130,29 @@ enum NDIS_802_11_WEP_STATUS {
/* Key mapping keys require a BSSID */ /* Key mapping keys require a BSSID */
struct ndis_802_11_key { struct ndis_802_11_key {
ULONG Length; // Length of this structure ULONG Length; /* Length of this structure */
ULONG KeyIndex; ULONG KeyIndex;
ULONG KeyLength; // length of key in bytes ULONG KeyLength; /* length of key in bytes */
u8 BSSID[ETH_ALEN]; u8 BSSID[ETH_ALEN];
unsigned long long KeyRSC; unsigned long long KeyRSC;
u8 KeyMaterial[32]; // variable length depending on above field u8 KeyMaterial[32]; /* variable length depending on above field */
}; };
struct ndis_802_11_remove_key { struct ndis_802_11_remove_key {
ULONG Length; // Length of this structure ULONG Length; /* Length of this structure */
ULONG KeyIndex; ULONG KeyIndex;
u8 BSSID[ETH_ALEN]; u8 BSSID[ETH_ALEN];
}; };
struct ndis_802_11_wep { struct ndis_802_11_wep {
ULONG Length; // Length of this structure ULONG Length; /* Length of this structure */
ULONG KeyIndex; // 0 is the per-client key, 1-N are the global keys ULONG KeyIndex; /* 0 is the per-client key, 1-N are the global keys */
ULONG KeyLength; // length of key in bytes ULONG KeyLength; /* length of key in bytes */
u8 KeyMaterial[16];// variable length depending on above field u8 KeyMaterial[16];/* variable length depending on above field */
}; };
struct ndis_802_11_authentication_request { struct ndis_802_11_authentication_request {
ULONG Length; // Length of structure ULONG Length; /* Length of structure */
u8 Bssid[ETH_ALEN]; u8 Bssid[ETH_ALEN];
ULONG Flags; ULONG Flags;
}; };
@ -161,21 +161,21 @@ enum NDIS_802_11_STATUS_TYPE {
Ndis802_11StatusType_Authentication, Ndis802_11StatusType_Authentication,
Ndis802_11StatusType_MediaStreamMode, Ndis802_11StatusType_MediaStreamMode,
Ndis802_11StatusType_PMKID_CandidateList, Ndis802_11StatusType_PMKID_CandidateList,
Ndis802_11StatusTypeMax // not a real type, defined as an upper bound Ndis802_11StatusTypeMax /* not a real type, defined as an upper bound */
}; };
struct ndis_802_11_status_indication { struct ndis_802_11_status_indication {
enum NDIS_802_11_STATUS_TYPE StatusType; enum NDIS_802_11_STATUS_TYPE StatusType;
}; };
// mask for authentication/integrity fields /* mask for authentication/integrity fields */
#define NDIS_802_11_AUTH_REQUEST_AUTH_FIELDS 0x0f #define NDIS_802_11_AUTH_REQUEST_AUTH_FIELDS 0x0f
#define NDIS_802_11_AUTH_REQUEST_REAUTH 0x01 #define NDIS_802_11_AUTH_REQUEST_REAUTH 0x01
#define NDIS_802_11_AUTH_REQUEST_KEYUPDATE 0x02 #define NDIS_802_11_AUTH_REQUEST_KEYUPDATE 0x02
#define NDIS_802_11_AUTH_REQUEST_PAIRWISE_ERROR 0x06 #define NDIS_802_11_AUTH_REQUEST_PAIRWISE_ERROR 0x06
#define NDIS_802_11_AUTH_REQUEST_GROUP_ERROR 0x0E #define NDIS_802_11_AUTH_REQUEST_GROUP_ERROR 0x0E
// MIC check time, 60 seconds. /* MIC check time, 60 seconds. */
#define MIC_CHECK_TIME 60000000 #define MIC_CHECK_TIME 60000000
struct ndis_802_11_authentication_event { struct ndis_802_11_authentication_event {
@ -188,18 +188,18 @@ struct ndis_802_11_authentication_event {
#endif #endif
struct wlan_phy_info { struct wlan_phy_info {
u8 SignalStrength;//(in percentage) u8 SignalStrength;/* in percentage) */
u8 SignalQuality;//(in percentage) u8 SignalQuality;/* in percentage) */
u8 Optimum_antenna; //for Antenna diversity u8 Optimum_antenna; /* for Antenna diversity */
u8 Reserved_0; u8 Reserved_0;
}; };
struct wlan_bcn_info { struct wlan_bcn_info {
/* these infor get from rtw_get_encrypt_info when /* these infor get from rtw_get_encrypt_info when
* * translate scan to UI */ * * translate scan to UI */
u8 encryp_protocol;//ENCRYP_PROTOCOL_E: OPEN/WEP/WPA/WPA2/WAPI u8 encryp_protocol;/* ENCRYP_PROTOCOL_E: OPEN/WEP/WPA/WPA2/WAPI */
int group_cipher; //WPA/WPA2 group cipher int group_cipher; /* WPA/WPA2 group cipher */
int pairwise_cipher;////WPA/WPA2/WEP pairwise cipher int pairwise_cipher;/* WPA/WPA2/WEP pairwise cipher */
int is_8021x; int is_8021x;
/* bwmode 20/40 and ch_offset UP/LOW */ /* bwmode 20/40 and ch_offset UP/LOW */
@ -213,17 +213,17 @@ struct wlan_bcn_info {
struct wlan_bssid_ex { struct wlan_bssid_ex {
ULONG Length; ULONG Length;
u8 MacAddress[ETH_ALEN]; u8 MacAddress[ETH_ALEN];
u8 Reserved[2];//[0]: IS beacon frame u8 Reserved[2];/* 0]: IS beacon frame */
struct ndis_802_11_ssid Ssid; struct ndis_802_11_ssid Ssid;
ULONG Privacy; ULONG Privacy;
long Rssi;//(in dBM,raw data ,get from PHY) long Rssi;/* in dBM,raw data ,get from PHY) */
enum NDIS_802_11_NETWORK_TYPE NetworkTypeInUse; enum NDIS_802_11_NETWORK_TYPE NetworkTypeInUse;
struct ndis_802_11_configuration Configuration; struct ndis_802_11_configuration Configuration;
enum NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode; enum NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode;
u8 SupportedRates[NDIS_802_11_LENGTH_RATES_EX]; u8 SupportedRates[NDIS_802_11_LENGTH_RATES_EX];
struct wlan_phy_info PhyInfo; struct wlan_phy_info PhyInfo;
ULONG IELength; ULONG IELength;
u8 IEs[MAX_IE_SZ]; //(timestamp, beacon interval, and capability information) u8 IEs[MAX_IE_SZ]; /* timestamp, beacon interval, and capability information) */
} __packed; } __packed;
__inline static uint get_wlan_bssid_ex_sz(struct wlan_bssid_ex *bss) __inline static uint get_wlan_bssid_ex_sz(struct wlan_bssid_ex *bss)
@ -233,12 +233,12 @@ __inline static uint get_wlan_bssid_ex_sz(struct wlan_bssid_ex *bss)
struct wlan_network { struct wlan_network {
struct list_head list; struct list_head list;
int network_type; //refer to ieee80211.h for WIRELESS_11A/B/G int network_type; /* refer to ieee80211.h for WIRELESS_11A/B/G */
int fixed; // set to fixed when not to be removed as site-surveying int fixed; /* set to fixed when not to be removed as site-surveying */
unsigned long last_scanned; //timestamp for the network unsigned long last_scanned; /* timestamp for the network */
int aid; //will only be valid when a BSS is joinned. int aid; /* will only be valid when a BSS is joinned. */
int join_res; int join_res;
struct wlan_bssid_ex network; //must be the last item struct wlan_bssid_ex network; /* must be the last item */
struct wlan_bcn_info BcnInfo; struct wlan_bcn_info BcnInfo;
}; };
@ -276,4 +276,4 @@ enum UAPSD_MAX_SP {
u8 convert_ip_addr(u8 hch, u8 mch, u8 lch); u8 convert_ip_addr(u8 hch, u8 mch, u8 lch);
#endif //#ifndef WLAN_BSSDEF_H_ #endif /* ifndef WLAN_BSSDEF_H_ */

4
include/xmit_osdep.h
View file

@ -26,7 +26,7 @@
struct pkt_file { struct pkt_file {
struct sk_buff *pkt; struct sk_buff *pkt;
SIZE_T pkt_len; //the remainder length of the open_file SIZE_T pkt_len; /* the remainder length of the open_file */
unsigned char *cur_buffer; unsigned char *cur_buffer;
u8 *buf_start; u8 *buf_start;
u8 *cur_addr; u8 *cur_addr;
@ -57,4 +57,4 @@ sint rtw_endofpktfile (struct pkt_file *pfile);
void rtw_os_pkt_complete(struct adapter *padapter, struct sk_buff *pkt); void rtw_os_pkt_complete(struct adapter *padapter, struct sk_buff *pkt);
void rtw_os_xmit_complete(struct adapter *padapter, struct xmit_frame *pxframe); void rtw_os_xmit_complete(struct adapter *padapter, struct xmit_frame *pxframe);
#endif //__XMIT_OSDEP_H_ #endif /* __XMIT_OSDEP_H_ */