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rtl8188eu: Remove all trailing spaces from code

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
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Larry Finger 2014-12-19 00:59:46 -06:00
parent 8db176767f
commit bb33327257
190 changed files with 53569 additions and 53764 deletions
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857
include/Hal8188EPhyCfg.h
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@ -1,429 +1,428 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8188EPHYCFG_H__
#define __INC_HAL8188EPHYCFG_H__
/*--------------------------Define Parameters-------------------------------*/
#define LOOP_LIMIT 5
#define MAX_STALL_TIME 50 //us
#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
#define MAX_TXPWR_IDX_NMODE_92S 63
#define Reset_Cnt_Limit 3
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM 9
#define HP_THERMAL_NUM 8
#ifdef CONFIG_PCI_HCI
#define MAX_AGGR_NUM 0x0B
#else
#define MAX_AGGR_NUM 0x07
#endif // CONFIG_PCI_HCI
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
typedef enum _SwChnlCmdID{
CmdID_End,
CmdID_SetTxPowerLevel,
CmdID_BBRegWrite10,
CmdID_WritePortUlong,
CmdID_WritePortUshort,
CmdID_WritePortUchar,
CmdID_RF_WriteReg,
}SwChnlCmdID;
/* 1. Switch channel related */
typedef struct _SwChnlCmd{
SwChnlCmdID CmdID;
u32 Para1;
u32 Para2;
u32 msDelay;
}SwChnlCmd;
typedef enum _HW90_BLOCK{
HW90_BLOCK_MAC = 0,
HW90_BLOCK_PHY0 = 1,
HW90_BLOCK_PHY1 = 2,
HW90_BLOCK_RF = 3,
HW90_BLOCK_MAXIMUM = 4, // Never use this
}HW90_BLOCK_E, *PHW90_BLOCK_E;
typedef enum _RF_RADIO_PATH{
RF_PATH_A = 0, //Radio Path A
RF_PATH_B = 1, //Radio Path B
RF_PATH_C = 2, //Radio Path C
RF_PATH_D = 3, //Radio Path D
//RF_PATH_MAX //Max RF number 90 support
}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E;
#define MAX_PG_GROUP 13
#define RF_PATH_MAX 2
#define MAX_RF_PATH RF_PATH_MAX
#define MAX_TX_COUNT_88E 1
#define MAX_TX_COUNT MAX_TX_COUNT_88E // 4 //path numbers
#define CHANNEL_MAX_NUMBER 14 // 14 is the max channel number
#define MAX_CHNL_GROUP_24G 6 // ch1~2, ch3~5, ch6~8,ch9~11,ch12~13,CH 14 total six groups
#define CHANNEL_GROUP_MAX_88E 6
typedef enum _WIRELESS_MODE {
WIRELESS_MODE_UNKNOWN = 0x00,
WIRELESS_MODE_A = BIT2,
WIRELESS_MODE_B = BIT0,
WIRELESS_MODE_G = BIT1,
WIRELESS_MODE_AUTO = BIT5,
WIRELESS_MODE_N_24G = BIT3,
WIRELESS_MODE_N_5G = BIT4,
WIRELESS_MODE_AC = BIT6
} WIRELESS_MODE;
typedef enum _PHY_Rate_Tx_Power_Offset_Area{
RA_OFFSET_LEGACY_OFDM1,
RA_OFFSET_LEGACY_OFDM2,
RA_OFFSET_HT_OFDM1,
RA_OFFSET_HT_OFDM2,
RA_OFFSET_HT_OFDM3,
RA_OFFSET_HT_OFDM4,
RA_OFFSET_HT_CCK,
}RA_OFFSET_AREA,*PRA_OFFSET_AREA;
/* BB/RF related */
typedef enum _RF_TYPE_8190P{
RF_TYPE_MIN, // 0
RF_8225=1, // 1 11b/g RF for verification only
RF_8256=2, // 2 11b/g/n
RF_8258=3, // 3 11a/b/g/n RF
RF_6052=4, // 4 11b/g/n RF
//RF_6052=5, // 4 11b/g/n RF
// TODO: We sholud remove this psudo PHY RF after we get new RF.
RF_PSEUDO_11N=5, // 5, It is a temporality RF.
}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
typedef struct _BB_REGISTER_DEFINITION{
u32 rfintfs; // set software control:
// 0x870~0x877[8 bytes]
u32 rfintfi; // readback data:
// 0x8e0~0x8e7[8 bytes]
u32 rfintfo; // output data:
// 0x860~0x86f [16 bytes]
u32 rfintfe; // output enable:
// 0x860~0x86f [16 bytes]
u32 rf3wireOffset; // LSSI data:
// 0x840~0x84f [16 bytes]
u32 rfLSSI_Select; // BB Band Select:
// 0x878~0x87f [8 bytes]
u32 rfTxGainStage; // Tx gain stage:
// 0x80c~0x80f [4 bytes]
u32 rfHSSIPara1; // wire parameter control1 :
// 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
u32 rfHSSIPara2; // wire parameter control2 :
// 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
u32 rfSwitchControl; //Tx Rx antenna control :
// 0x858~0x85f [16 bytes]
u32 rfAGCControl1; //AGC parameter control1 :
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
u32 rfAGCControl2; //AGC parameter control2 :
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
// 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
// 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
// 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
// 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
u32 rfLSSIReadBack; //LSSI RF readback data SI mode
// 0x8a0~0x8af [16 bytes]
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
typedef struct _R_ANTENNA_SELECT_OFDM{
u32 r_tx_antenna:4;
u32 r_ant_l:4;
u32 r_ant_non_ht:4;
u32 r_ant_ht1:4;
u32 r_ant_ht2:4;
u32 r_ant_ht_s1:4;
u32 r_ant_non_ht_s1:4;
u32 OFDM_TXSC:2;
u32 Reserved:2;
}R_ANTENNA_SELECT_OFDM;
typedef struct _R_ANTENNA_SELECT_CCK{
u8 r_cckrx_enable_2:2;
u8 r_cckrx_enable:2;
u8 r_ccktx_enable:4;
}R_ANTENNA_SELECT_CCK;
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*--------------------------Exported Function prototype---------------------*/
//
// BB and RF register read/write
//
u32 rtl8188e_PHY_QueryBBReg( IN struct adapter *Adapter,
IN u32 RegAddr,
IN u32 BitMask );
void rtl8188e_PHY_SetBBReg( IN struct adapter *Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
u32 rtl8188e_PHY_QueryRFReg( IN struct adapter * Adapter,
IN RF_RADIO_PATH_E eRFPath,
IN u32 RegAddr,
IN u32 BitMask );
void rtl8188e_PHY_SetRFReg( IN struct adapter * Adapter,
IN RF_RADIO_PATH_E eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
//
// Initialization related function
//
/* MAC/BB/RF HAL config */
int PHY_MACConfig8188E(IN struct adapter *Adapter );
int PHY_BBConfig8188E(IN struct adapter *Adapter );
int PHY_RFConfig8188E(IN struct adapter *Adapter );
/* RF config */
int rtl8188e_PHY_ConfigRFWithParaFile(IN struct adapter *Adapter, IN u8 * pFileName, RF_RADIO_PATH_E eRFPath);
int rtl8188e_PHY_ConfigRFWithHeaderFile( IN struct adapter * Adapter,
IN RF_RADIO_PATH_E eRFPath);
/* Read initi reg value for tx power setting. */
void rtl8192c_PHY_GetHWRegOriginalValue( IN struct adapter * Adapter );
//
// RF Power setting
//
//extern BOOLEAN PHY_SetRFPowerState(IN struct adapter * Adapter,
// IN RT_RF_POWER_STATE eRFPowerState);
//
// BB TX Power R/W
//
void PHY_GetTxPowerLevel8188E( IN struct adapter * Adapter,
OUT u32* powerlevel );
void PHY_SetTxPowerLevel8188E( IN struct adapter * Adapter,
IN u8 channel );
BOOLEAN PHY_UpdateTxPowerDbm8188E( IN struct adapter *Adapter,
IN int powerInDbm );
//
VOID
PHY_ScanOperationBackup8188E(IN struct adapter *Adapter,
IN u8 Operation );
//
// Switch bandwidth for 8192S
//
//extern void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer );
void PHY_SetBWMode8188E( IN struct adapter * pAdapter,
IN HT_CHANNEL_WIDTH ChnlWidth,
IN unsigned char Offset );
//
// Set FW CMD IO for 8192S.
//
//extern BOOLEAN HalSetIO8192C( IN struct adapter * Adapter,
// IN IO_TYPE IOType);
//
// Set A2 entry to fw for 8192S
//
extern void FillA2Entry8192C( IN struct adapter * Adapter,
IN u8 index,
IN u8* val);
//
// channel switch related funciton
//
//extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer );
void PHY_SwChnl8188E( IN struct adapter * pAdapter,
IN u8 channel );
// Call after initialization
void PHY_SwChnlPhy8192C( IN struct adapter * pAdapter,
IN u8 channel );
void ChkFwCmdIoDone( IN struct adapter *Adapter);
//
// BB/MAC/RF other monitor API
//
void PHY_SetMonitorMode8192C(IN struct adapter *pAdapter,
IN BOOLEAN bEnableMonitorMode );
BOOLEAN PHY_CheckIsLegalRfPath8192C(IN struct adapter *pAdapter,
IN u32 eRFPath );
VOID PHY_SetRFPathSwitch_8188E(IN struct adapter *pAdapter, IN BOOLEAN bMain);
extern VOID
PHY_SwitchEphyParameter(
IN struct adapter * Adapter
);
extern VOID
PHY_EnableHostClkReq(
IN struct adapter * Adapter
);
BOOLEAN
SetAntennaConfig92C(
IN struct adapter *Adapter,
IN u8 DefaultAnt
);
#ifdef CONFIG_PHY_SETTING_WITH_ODM
VOID
storePwrIndexDiffRateOffset(
IN struct adapter *Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
);
#endif //CONFIG_PHY_SETTING_WITH_ODM
/*--------------------------Exported Function prototype---------------------*/
#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtl8188e_PHY_QueryBBReg((Adapter), (RegAddr), (BitMask))
#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtl8188e_PHY_SetBBReg((Adapter), (RegAddr), (BitMask), (Data))
#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtl8188e_PHY_QueryRFReg((Adapter), (eRFPath), (RegAddr), (BitMask))
#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtl8188e_PHY_SetRFReg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
#define PHY_SetMacReg PHY_SetBBReg
#define PHY_QueryMacReg PHY_QueryBBReg
//
// Initialization related function
//
/* MAC/BB/RF HAL config */
//extern s32 PHY_MACConfig8723(struct adapter *padapter);
//s32 PHY_BBConfig8723(struct adapter *padapter);
//s32 PHY_RFConfig8723(struct adapter *padapter);
//==================================================================
// Note: If SIC_ENABLE under PCIE, because of the slow operation
// you should
// 2) "#define RTL8723_FPGA_VERIFICATION 1" in Precomp.h.WlanE.Windows
// 3) "#define RTL8190_Download_Firmware_From_Header 0" in Precomp.h.WlanE.Windows if needed.
//
#if (RTL8188E_SUPPORT == 1) && (RTL8188E_FPGA_TRUE_PHY_VERIFICATION == 1)
#define SIC_ENABLE 1
#define SIC_HW_SUPPORT 1
#else
#define SIC_ENABLE 0
#define SIC_HW_SUPPORT 0
#endif
//==================================================================
#define SIC_MAX_POLL_CNT 5
#if(SIC_HW_SUPPORT == 1)
#define SIC_CMD_READY 0
#define SIC_CMD_PREWRITE 0x1
#if(RTL8188E_SUPPORT == 1)
#define SIC_CMD_WRITE 0x40
#define SIC_CMD_PREREAD 0x2
#define SIC_CMD_READ 0x80
#define SIC_CMD_INIT 0xf0
#define SIC_INIT_VAL 0xff
#define SIC_INIT_REG 0x1b7
#define SIC_CMD_REG 0x1EB // 1byte
#define SIC_ADDR_REG 0x1E8 // 1b4~1b5, 2 bytes
#define SIC_DATA_REG 0x1EC // 1b0~1b3
#else
#define SIC_CMD_WRITE 0x11
#define SIC_CMD_PREREAD 0x2
#define SIC_CMD_READ 0x12
#define SIC_CMD_INIT 0x1f
#define SIC_INIT_VAL 0xff
#define SIC_INIT_REG 0x1b7
#define SIC_CMD_REG 0x1b6 // 1byte
#define SIC_ADDR_REG 0x1b4 // 1b4~1b5, 2 bytes
#define SIC_DATA_REG 0x1b0 // 1b0~1b3
#endif
#else
#define SIC_CMD_READY 0
#define SIC_CMD_WRITE 1
#define SIC_CMD_READ 2
#if(RTL8188E_SUPPORT == 1)
#define SIC_CMD_REG 0x1EB // 1byte
#define SIC_ADDR_REG 0x1E8 // 1b9~1ba, 2 bytes
#define SIC_DATA_REG 0x1EC // 1bc~1bf
#else
#define SIC_CMD_REG 0x1b8 // 1byte
#define SIC_ADDR_REG 0x1b9 // 1b9~1ba, 2 bytes
#define SIC_DATA_REG 0x1bc // 1bc~1bf
#endif
#endif
#if(SIC_ENABLE == 1)
VOID SIC_Init(IN struct adapter *Adapter);
#endif
#endif // __INC_HAL8192CPHYCFG_H
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8188EPHYCFG_H__
#define __INC_HAL8188EPHYCFG_H__
/*--------------------------Define Parameters-------------------------------*/
#define LOOP_LIMIT 5
#define MAX_STALL_TIME 50 //us
#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
#define MAX_TXPWR_IDX_NMODE_92S 63
#define Reset_Cnt_Limit 3
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM 9
#define HP_THERMAL_NUM 8
#ifdef CONFIG_PCI_HCI
#define MAX_AGGR_NUM 0x0B
#else
#define MAX_AGGR_NUM 0x07
#endif // CONFIG_PCI_HCI
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
typedef enum _SwChnlCmdID{
CmdID_End,
CmdID_SetTxPowerLevel,
CmdID_BBRegWrite10,
CmdID_WritePortUlong,
CmdID_WritePortUshort,
CmdID_WritePortUchar,
CmdID_RF_WriteReg,
}SwChnlCmdID;
/* 1. Switch channel related */
typedef struct _SwChnlCmd{
SwChnlCmdID CmdID;
u32 Para1;
u32 Para2;
u32 msDelay;
}SwChnlCmd;
typedef enum _HW90_BLOCK{
HW90_BLOCK_MAC = 0,
HW90_BLOCK_PHY0 = 1,
HW90_BLOCK_PHY1 = 2,
HW90_BLOCK_RF = 3,
HW90_BLOCK_MAXIMUM = 4, // Never use this
}HW90_BLOCK_E, *PHW90_BLOCK_E;
typedef enum _RF_RADIO_PATH{
RF_PATH_A = 0, //Radio Path A
RF_PATH_B = 1, //Radio Path B
RF_PATH_C = 2, //Radio Path C
RF_PATH_D = 3, //Radio Path D
//RF_PATH_MAX //Max RF number 90 support
}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E;
#define MAX_PG_GROUP 13
#define RF_PATH_MAX 2
#define MAX_RF_PATH RF_PATH_MAX
#define MAX_TX_COUNT_88E 1
#define MAX_TX_COUNT MAX_TX_COUNT_88E // 4 //path numbers
#define CHANNEL_MAX_NUMBER 14 // 14 is the max channel number
#define MAX_CHNL_GROUP_24G 6 // ch1~2, ch3~5, ch6~8,ch9~11,ch12~13,CH 14 total six groups
#define CHANNEL_GROUP_MAX_88E 6
typedef enum _WIRELESS_MODE {
WIRELESS_MODE_UNKNOWN = 0x00,
WIRELESS_MODE_A = BIT2,
WIRELESS_MODE_B = BIT0,
WIRELESS_MODE_G = BIT1,
WIRELESS_MODE_AUTO = BIT5,
WIRELESS_MODE_N_24G = BIT3,
WIRELESS_MODE_N_5G = BIT4,
WIRELESS_MODE_AC = BIT6
} WIRELESS_MODE;
typedef enum _PHY_Rate_Tx_Power_Offset_Area{
RA_OFFSET_LEGACY_OFDM1,
RA_OFFSET_LEGACY_OFDM2,
RA_OFFSET_HT_OFDM1,
RA_OFFSET_HT_OFDM2,
RA_OFFSET_HT_OFDM3,
RA_OFFSET_HT_OFDM4,
RA_OFFSET_HT_CCK,
}RA_OFFSET_AREA,*PRA_OFFSET_AREA;
/* BB/RF related */
typedef enum _RF_TYPE_8190P{
RF_TYPE_MIN, // 0
RF_8225=1, // 1 11b/g RF for verification only
RF_8256=2, // 2 11b/g/n
RF_8258=3, // 3 11a/b/g/n RF
RF_6052=4, // 4 11b/g/n RF
//RF_6052=5, // 4 11b/g/n RF
// TODO: We sholud remove this psudo PHY RF after we get new RF.
RF_PSEUDO_11N=5, // 5, It is a temporality RF.
}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
typedef struct _BB_REGISTER_DEFINITION{
u32 rfintfs; // set software control:
// 0x870~0x877[8 bytes]
u32 rfintfi; // readback data:
// 0x8e0~0x8e7[8 bytes]
u32 rfintfo; // output data:
// 0x860~0x86f [16 bytes]
u32 rfintfe; // output enable:
// 0x860~0x86f [16 bytes]
u32 rf3wireOffset; // LSSI data:
// 0x840~0x84f [16 bytes]
u32 rfLSSI_Select; // BB Band Select:
// 0x878~0x87f [8 bytes]
u32 rfTxGainStage; // Tx gain stage:
// 0x80c~0x80f [4 bytes]
u32 rfHSSIPara1; // wire parameter control1 :
// 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
u32 rfHSSIPara2; // wire parameter control2 :
// 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
u32 rfSwitchControl; //Tx Rx antenna control :
// 0x858~0x85f [16 bytes]
u32 rfAGCControl1; //AGC parameter control1 :
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
u32 rfAGCControl2; //AGC parameter control2 :
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
// 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
// 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
// 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
// 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
u32 rfLSSIReadBack; //LSSI RF readback data SI mode
// 0x8a0~0x8af [16 bytes]
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
typedef struct _R_ANTENNA_SELECT_OFDM{
u32 r_tx_antenna:4;
u32 r_ant_l:4;
u32 r_ant_non_ht:4;
u32 r_ant_ht1:4;
u32 r_ant_ht2:4;
u32 r_ant_ht_s1:4;
u32 r_ant_non_ht_s1:4;
u32 OFDM_TXSC:2;
u32 Reserved:2;
}R_ANTENNA_SELECT_OFDM;
typedef struct _R_ANTENNA_SELECT_CCK{
u8 r_cckrx_enable_2:2;
u8 r_cckrx_enable:2;
u8 r_ccktx_enable:4;
}R_ANTENNA_SELECT_CCK;
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*--------------------------Exported Function prototype---------------------*/
//
// BB and RF register read/write
//
u32 rtl8188e_PHY_QueryBBReg( IN struct adapter *Adapter,
IN u32 RegAddr,
IN u32 BitMask );
void rtl8188e_PHY_SetBBReg( IN struct adapter *Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
u32 rtl8188e_PHY_QueryRFReg( IN struct adapter * Adapter,
IN RF_RADIO_PATH_E eRFPath,
IN u32 RegAddr,
IN u32 BitMask );
void rtl8188e_PHY_SetRFReg( IN struct adapter * Adapter,
IN RF_RADIO_PATH_E eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data );
//
// Initialization related function
//
/* MAC/BB/RF HAL config */
int PHY_MACConfig8188E(IN struct adapter *Adapter );
int PHY_BBConfig8188E(IN struct adapter *Adapter );
int PHY_RFConfig8188E(IN struct adapter *Adapter );
/* RF config */
int rtl8188e_PHY_ConfigRFWithParaFile(IN struct adapter *Adapter, IN u8 * pFileName, RF_RADIO_PATH_E eRFPath);
int rtl8188e_PHY_ConfigRFWithHeaderFile( IN struct adapter * Adapter,
IN RF_RADIO_PATH_E eRFPath);
/* Read initi reg value for tx power setting. */
void rtl8192c_PHY_GetHWRegOriginalValue( IN struct adapter * Adapter );
//
// RF Power setting
//
//extern BOOLEAN PHY_SetRFPowerState(IN struct adapter * Adapter,
// IN RT_RF_POWER_STATE eRFPowerState);
//
// BB TX Power R/W
//
void PHY_GetTxPowerLevel8188E( IN struct adapter * Adapter,
OUT u32* powerlevel );
void PHY_SetTxPowerLevel8188E( IN struct adapter * Adapter,
IN u8 channel );
BOOLEAN PHY_UpdateTxPowerDbm8188E( IN struct adapter *Adapter,
IN int powerInDbm );
//
VOID
PHY_ScanOperationBackup8188E(IN struct adapter *Adapter,
IN u8 Operation );
//
// Switch bandwidth for 8192S
//
//extern void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer );
void PHY_SetBWMode8188E( IN struct adapter * pAdapter,
IN HT_CHANNEL_WIDTH ChnlWidth,
IN unsigned char Offset );
//
// Set FW CMD IO for 8192S.
//
//extern BOOLEAN HalSetIO8192C( IN struct adapter * Adapter,
// IN IO_TYPE IOType);
//
// Set A2 entry to fw for 8192S
//
extern void FillA2Entry8192C( IN struct adapter * Adapter,
IN u8 index,
IN u8* val);
//
// channel switch related funciton
//
//extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer );
void PHY_SwChnl8188E( IN struct adapter * pAdapter,
IN u8 channel );
// Call after initialization
void PHY_SwChnlPhy8192C( IN struct adapter * pAdapter,
IN u8 channel );
void ChkFwCmdIoDone( IN struct adapter *Adapter);
//
// BB/MAC/RF other monitor API
//
void PHY_SetMonitorMode8192C(IN struct adapter *pAdapter,
IN BOOLEAN bEnableMonitorMode );
BOOLEAN PHY_CheckIsLegalRfPath8192C(IN struct adapter *pAdapter,
IN u32 eRFPath );
VOID PHY_SetRFPathSwitch_8188E(IN struct adapter *pAdapter, IN BOOLEAN bMain);
extern VOID
PHY_SwitchEphyParameter(
IN struct adapter * Adapter
);
extern VOID
PHY_EnableHostClkReq(
IN struct adapter * Adapter
);
BOOLEAN
SetAntennaConfig92C(
IN struct adapter *Adapter,
IN u8 DefaultAnt
);
#ifdef CONFIG_PHY_SETTING_WITH_ODM
VOID
storePwrIndexDiffRateOffset(
IN struct adapter *Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
);
#endif //CONFIG_PHY_SETTING_WITH_ODM
/*--------------------------Exported Function prototype---------------------*/
#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtl8188e_PHY_QueryBBReg((Adapter), (RegAddr), (BitMask))
#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtl8188e_PHY_SetBBReg((Adapter), (RegAddr), (BitMask), (Data))
#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtl8188e_PHY_QueryRFReg((Adapter), (eRFPath), (RegAddr), (BitMask))
#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtl8188e_PHY_SetRFReg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
#define PHY_SetMacReg PHY_SetBBReg
#define PHY_QueryMacReg PHY_QueryBBReg
//
// Initialization related function
//
/* MAC/BB/RF HAL config */
//extern s32 PHY_MACConfig8723(struct adapter *padapter);
//s32 PHY_BBConfig8723(struct adapter *padapter);
//s32 PHY_RFConfig8723(struct adapter *padapter);
//==================================================================
// Note: If SIC_ENABLE under PCIE, because of the slow operation
// you should
// 2) "#define RTL8723_FPGA_VERIFICATION 1" in Precomp.h.WlanE.Windows
// 3) "#define RTL8190_Download_Firmware_From_Header 0" in Precomp.h.WlanE.Windows if needed.
//
#if (RTL8188E_SUPPORT == 1) && (RTL8188E_FPGA_TRUE_PHY_VERIFICATION == 1)
#define SIC_ENABLE 1
#define SIC_HW_SUPPORT 1
#else
#define SIC_ENABLE 0
#define SIC_HW_SUPPORT 0
#endif
//==================================================================
#define SIC_MAX_POLL_CNT 5
#if(SIC_HW_SUPPORT == 1)
#define SIC_CMD_READY 0
#define SIC_CMD_PREWRITE 0x1
#if(RTL8188E_SUPPORT == 1)
#define SIC_CMD_WRITE 0x40
#define SIC_CMD_PREREAD 0x2
#define SIC_CMD_READ 0x80
#define SIC_CMD_INIT 0xf0
#define SIC_INIT_VAL 0xff
#define SIC_INIT_REG 0x1b7
#define SIC_CMD_REG 0x1EB // 1byte
#define SIC_ADDR_REG 0x1E8 // 1b4~1b5, 2 bytes
#define SIC_DATA_REG 0x1EC // 1b0~1b3
#else
#define SIC_CMD_WRITE 0x11
#define SIC_CMD_PREREAD 0x2
#define SIC_CMD_READ 0x12
#define SIC_CMD_INIT 0x1f
#define SIC_INIT_VAL 0xff
#define SIC_INIT_REG 0x1b7
#define SIC_CMD_REG 0x1b6 // 1byte
#define SIC_ADDR_REG 0x1b4 // 1b4~1b5, 2 bytes
#define SIC_DATA_REG 0x1b0 // 1b0~1b3
#endif
#else
#define SIC_CMD_READY 0
#define SIC_CMD_WRITE 1
#define SIC_CMD_READ 2
#if(RTL8188E_SUPPORT == 1)
#define SIC_CMD_REG 0x1EB // 1byte
#define SIC_ADDR_REG 0x1E8 // 1b9~1ba, 2 bytes
#define SIC_DATA_REG 0x1EC // 1bc~1bf
#else
#define SIC_CMD_REG 0x1b8 // 1byte
#define SIC_ADDR_REG 0x1b9 // 1b9~1ba, 2 bytes
#define SIC_DATA_REG 0x1bc // 1bc~1bf
#endif
#endif
#if(SIC_ENABLE == 1)
VOID SIC_Init(IN struct adapter *Adapter);
#endif
#endif // __INC_HAL8192CPHYCFG_H

2223
include/Hal8188EPhyReg.h
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353
include/Hal8188EPwrSeq.h
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@ -1,177 +1,176 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL8188EPWRSEQ_H__
#define __HAL8188EPWRSEQ_H__
#include "HalPwrSeqCmd.h"
/*
Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
There are 6 HW Power States:
0: POFF--Power Off
1: PDN--Power Down
2: CARDEMU--Card Emulation
3: ACT--Active Mode
4: LPS--Low Power State
5: SUS--Suspend
The transision from different states are defined below
TRANS_CARDEMU_TO_ACT
TRANS_ACT_TO_CARDEMU
TRANS_CARDEMU_TO_SUS
TRANS_SUS_TO_CARDEMU
TRANS_CARDEMU_TO_PDN
TRANS_ACT_TO_LPS
TRANS_LPS_TO_ACT
TRANS_END
PWR SEQ Version: rtl8188E_PwrSeq_V09.h
*/
#define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10
#define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10
#define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10
#define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10
#define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10
#define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10
#define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15
#define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15
#define RTL8188E_TRANS_END_STEPS 1
#define RTL8188E_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0|BIT1, 0}, /* 0x02[1:0] = 0 reset BB*/ \
{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0}, /* 0x04[15] = 0 disable HWPDN (control by DRV)*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, 0}, /*0x04[12:11] = 2b'00 disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[8] = 1 polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0}, /*wait till 0x04[8] = 0*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*LDO normal mode*/ \
{0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*SDIO Driving*/ \
#define RTL8188E_TRANS_ACT_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*LDO Sleep mode*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
#define RTL8188E_TRANS_CARDEMU_TO_SUS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, BIT7}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \
{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \
{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8188E_TRANS_SUS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \
{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \
{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8188E_TRANS_CARDEMU_TO_PDN \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
#define RTL8188E_TRANS_PDN_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
//This is used by driver for LPSRadioOff Procedure, not for FW LPS Step
#define RTL8188E_TRANS_ACT_TO_LPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
#define RTL8188E_TRANS_LPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8188E_TRANS_END \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
extern WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS];
#endif //__HAL8188EPWRSEQ_H__
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL8188EPWRSEQ_H__
#define __HAL8188EPWRSEQ_H__
#include "HalPwrSeqCmd.h"
/*
Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
There are 6 HW Power States:
0: POFF--Power Off
1: PDN--Power Down
2: CARDEMU--Card Emulation
3: ACT--Active Mode
4: LPS--Low Power State
5: SUS--Suspend
The transision from different states are defined below
TRANS_CARDEMU_TO_ACT
TRANS_ACT_TO_CARDEMU
TRANS_CARDEMU_TO_SUS
TRANS_SUS_TO_CARDEMU
TRANS_CARDEMU_TO_PDN
TRANS_ACT_TO_LPS
TRANS_LPS_TO_ACT
TRANS_END
PWR SEQ Version: rtl8188E_PwrSeq_V09.h
*/
#define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10
#define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10
#define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10
#define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10
#define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10
#define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10
#define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15
#define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15
#define RTL8188E_TRANS_END_STEPS 1
#define RTL8188E_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0|BIT1, 0}, /* 0x02[1:0] = 0 reset BB*/ \
{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0}, /* 0x04[15] = 0 disable HWPDN (control by DRV)*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, 0}, /*0x04[12:11] = 2b'00 disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[8] = 1 polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0}, /*wait till 0x04[8] = 0*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*LDO normal mode*/ \
{0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*SDIO Driving*/ \
#define RTL8188E_TRANS_ACT_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*LDO Sleep mode*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
#define RTL8188E_TRANS_CARDEMU_TO_SUS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, BIT7}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \
{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \
{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8188E_TRANS_SUS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \
{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \
{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8188E_TRANS_CARDEMU_TO_PDN \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
#define RTL8188E_TRANS_PDN_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
//This is used by driver for LPSRadioOff Procedure, not for FW LPS Step
#define RTL8188E_TRANS_ACT_TO_LPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
#define RTL8188E_TRANS_LPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8188E_TRANS_END \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
extern WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS];
#endif //__HAL8188EPWRSEQ_H__

127
include/Hal8192CPhyCfg.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -21,18 +21,18 @@
* Module: __INC_HAL8192CPHYCFG_H
*
*
* Note:
*
* Note:
*
*
* Export: Constants, macro, functions(API), global variables(None).
*
* Abbrev:
* Abbrev:
*
* History:
* Data Who Remark
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* Data Who Remark
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* 2. Reorganize code architecture.
*
*
*****************************************************************************/
/* Check to see if the file has been included already. */
#ifndef __INC_HAL8192CPHYCFG_H
@ -79,7 +79,7 @@
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure----------------------------*/
typedef enum _SwChnlCmdID{
CmdID_End,
CmdID_SetTxPowerLevel,
@ -112,7 +112,7 @@ typedef enum _RF_RADIO_PATH{
RF_PATH_B = 1, //Radio Path B
RF_PATH_C = 2, //Radio Path C
RF_PATH_D = 3, //Radio Path D
//RF_PATH_MAX //Max RF number 90 support
//RF_PATH_MAX //Max RF number 90 support
}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E;
#define RF_PATH_MAX 2
@ -122,12 +122,12 @@ typedef enum _RF_RADIO_PATH{
typedef enum _WIRELESS_MODE {
WIRELESS_MODE_UNKNOWN = 0x00,
WIRELESS_MODE_A = BIT2,
WIRELESS_MODE_B = BIT0,
WIRELESS_MODE_G = BIT1,
WIRELESS_MODE_AUTO = BIT5,
WIRELESS_MODE_N_24G = BIT3,
WIRELESS_MODE_N_5G = BIT4,
WIRELESS_MODE_A = BIT2,
WIRELESS_MODE_B = BIT0,
WIRELESS_MODE_G = BIT1,
WIRELESS_MODE_AUTO = BIT5,
WIRELESS_MODE_N_24G = BIT3,
WIRELESS_MODE_N_5G = BIT4,
WIRELESS_MODE_AC = BIT6
} WIRELESS_MODE;
@ -152,75 +152,75 @@ typedef enum _PHY_Rate_Tx_Power_Offset_Area{
typedef enum _RF_TYPE_8190P{
RF_TYPE_MIN, // 0
RF_8225=1, // 1 11b/g RF for verification only
RF_8256=2, // 2 11b/g/n
RF_8256=2, // 2 11b/g/n
RF_8258=3, // 3 11a/b/g/n RF
RF_6052=4, // 4 11b/g/n RF
//RF_6052=5, // 4 11b/g/n RF
// TODO: We sholud remove this psudo PHY RF after we get new RF.
RF_PSEUDO_11N=5, // 5, It is a temporality RF.
RF_PSEUDO_11N=5, // 5, It is a temporality RF.
}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
typedef struct _BB_REGISTER_DEFINITION{
u32 rfintfs; // set software control:
u32 rfintfs; // set software control:
// 0x870~0x877[8 bytes]
u32 rfintfi; // readback data:
u32 rfintfi; // readback data:
// 0x8e0~0x8e7[8 bytes]
u32 rfintfo; // output data:
u32 rfintfo; // output data:
// 0x860~0x86f [16 bytes]
u32 rfintfe; // output enable:
u32 rfintfe; // output enable:
// 0x860~0x86f [16 bytes]
u32 rf3wireOffset; // LSSI data:
// 0x840~0x84f [16 bytes]
u32 rfLSSI_Select; // BB Band Select:
u32 rfLSSI_Select; // BB Band Select:
// 0x878~0x87f [8 bytes]
u32 rfTxGainStage; // Tx gain stage:
u32 rfTxGainStage; // Tx gain stage:
// 0x80c~0x80f [4 bytes]
u32 rfHSSIPara1; // wire parameter control1 :
u32 rfHSSIPara1; // wire parameter control1 :
// 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
u32 rfHSSIPara2; // wire parameter control2 :
u32 rfHSSIPara2; // wire parameter control2 :
// 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
u32 rfSwitchControl; //Tx Rx antenna control :
u32 rfSwitchControl; //Tx Rx antenna control :
// 0x858~0x85f [16 bytes]
u32 rfAGCControl1; //AGC parameter control1 :
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
u32 rfAGCControl2; //AGC parameter control2 :
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
u32 rfAGCControl1; //AGC parameter control1 :
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
u32 rfAGCControl2; //AGC parameter control2 :
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
// 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
// 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
// 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
// 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
u32 rfLSSIReadBack; //LSSI RF readback data SI mode
u32 rfLSSIReadBack; //LSSI RF readback data SI mode
// 0x8a0~0x8af [16 bytes]
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
typedef struct _R_ANTENNA_SELECT_OFDM{
u32 r_tx_antenna:4;
typedef struct _R_ANTENNA_SELECT_OFDM{
u32 r_tx_antenna:4;
u32 r_ant_l:4;
u32 r_ant_non_ht:4;
u32 r_ant_non_ht:4;
u32 r_ant_ht1:4;
u32 r_ant_ht2:4;
u32 r_ant_ht_s1:4;
@ -230,12 +230,12 @@ typedef struct _R_ANTENNA_SELECT_OFDM{
}R_ANTENNA_SELECT_OFDM;
typedef struct _R_ANTENNA_SELECT_CCK{
u8 r_cckrx_enable_2:2;
u8 r_cckrx_enable_2:2;
u8 r_cckrx_enable:2;
u8 r_ccktx_enable:4;
}R_ANTENNA_SELECT_CCK;
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
@ -276,7 +276,7 @@ int PHY_BBConfig8192C( IN struct adapter *Adapter );
int PHY_RFConfig8192C( IN struct adapter *Adapter );
/* RF config */
int rtl8192c_PHY_ConfigRFWithParaFile( IN struct adapter *Adapter,
IN u8* pFileName,
IN u8* pFileName,
IN RF_RADIO_PATH_E eRFPath);
int rtl8192c_PHY_ConfigRFWithHeaderFile( IN struct adapter * Adapter,
IN RF_RADIO_PATH_E eRFPath);
@ -291,21 +291,21 @@ void rtl8192c_PHY_GetHWRegOriginalValue( IN struct adapter * Adapter );
//
// RF Power setting
//
//extern BOOLEAN PHY_SetRFPowerState(IN struct adapter * Adapter,
//extern BOOLEAN PHY_SetRFPowerState(IN struct adapter * Adapter,
// IN RT_RF_POWER_STATE eRFPowerState);
//
// BB TX Power R/W
//
void PHY_GetTxPowerLevel8192C( IN struct adapter * Adapter,
OUT u32* powerlevel );
OUT u32* powerlevel );
void PHY_SetTxPowerLevel8192C( IN struct adapter * Adapter,
IN u8 channel );
BOOLEAN PHY_UpdateTxPowerDbm8192C( IN struct adapter *Adapter,
IN int powerInDbm );
//
VOID
VOID
PHY_ScanOperationBackup8192C(IN struct adapter *Adapter,
IN u8 Operation );
@ -342,7 +342,7 @@ void PHY_SwChnlPhy8192C( IN struct adapter * pAdapter,
IN u8 channel );
void ChkFwCmdIoDone( IN struct adapter *Adapter);
//
// BB/MAC/RF other monitor API
//
@ -358,7 +358,7 @@ VOID rtl8192c_PHY_SetRFPathSwitch(IN struct adapter *pAdapter, IN BOOLEAN bMain
//
// Modify the value of the hw register when beacon interval be changed.
//
void
void
rtl8192c_PHY_SetBeaconHwReg( IN struct adapter * Adapter,
IN u16 BeaconInterval );
@ -376,7 +376,7 @@ PHY_EnableHostClkReq(
BOOLEAN
SetAntennaConfig92C(
IN struct adapter *Adapter,
IN u8 DefaultAnt
IN u8 DefaultAnt
);
#ifdef RTL8192C_RECONFIG_TO_1T1R
@ -393,4 +393,3 @@ extern void PHY_Reconfig_To_1T1R(struct adapter *padapter);
#define PHY_QueryMacReg PHY_QueryBBReg
#endif // __INC_HAL8192CPHYCFG_H

451
include/Hal8192CPhyReg.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -27,18 +27,18 @@
* 3. PMAC/BB register bit mask.
* 4. RF reg bit mask.
* 5. Other BB/RF relative definition.
*
*
*
* Export: Constants, macro, functions(API), global variables(None).
*
* Abbrev:
* Abbrev:
*
* History:
* Data Who Remark
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* Data Who Remark
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* 2. Reorganize code architecture.
* 09/25/2008 MH 1. Add RL6052 register definition
*
*
*****************************************************************************/
#ifndef __INC_HAL8192CPHYREG_H
#define __INC_HAL8192CPHYREG_H
@ -179,8 +179,8 @@
#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI
#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain
#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series
#define rCCK0_RxAGC2 0xa10 //AGC & DAGC
#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series
#define rCCK0_RxAGC2 0xa10 //AGC & DAGC
#define rCCK0_RxHP 0xa14
@ -191,20 +191,20 @@
#define rCCK0_TxFilter2 0xa24
#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3
#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report
#define rCCK0_TRSSIReport 0xa50
#define rCCK0_RxReport 0xa54 //0xa57
#define rCCK0_FACounterLower 0xa5c //0xa5b
#define rCCK0_FACounterUpper 0xa58 //0xa5c
#define rCCK0_TRSSIReport 0xa50
#define rCCK0_RxReport 0xa54 //0xa57
#define rCCK0_FACounterLower 0xa5c //0xa5b
#define rCCK0_FACounterUpper 0xa58 //0xa5c
//
// PageB(0xB00)
//
#define rPdp_AntA 0xb00
#define rPdp_AntA_4 0xb04
#define rConfig_Pmpd_AntA 0xb28
#define rConfig_AntA 0xb68
#define rConfig_AntB 0xb6c
#define rPdp_AntB 0xb70
#define rPdp_AntB_4 0xb74
#define rPdp_AntA 0xb00
#define rPdp_AntA_4 0xb04
#define rConfig_Pmpd_AntA 0xb28
#define rConfig_AntA 0xb68
#define rConfig_AntB 0xb6c
#define rPdp_AntB 0xb70
#define rPdp_AntB_4 0xb74
#define rConfig_Pmpd_AntB 0xb98
#define rAPK 0xbd8
@ -218,16 +218,16 @@
#define rOFDM0_TRSWIsolation 0xc0c
#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter
#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
#define rOFDM0_XBRxAFE 0xc18
#define rOFDM0_XBRxIQImbalance 0xc1c
#define rOFDM0_XCRxAFE 0xc20
#define rOFDM0_XCRxIQImbalance 0xc24
#define rOFDM0_XDRxAFE 0xc28
#define rOFDM0_XDRxIQImbalance 0xc2c
#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
#define rOFDM0_XBRxAFE 0xc18
#define rOFDM0_XBRxIQImbalance 0xc1c
#define rOFDM0_XCRxAFE 0xc20
#define rOFDM0_XCRxIQImbalance 0xc24
#define rOFDM0_XDRxAFE 0xc28
#define rOFDM0_XDRxIQImbalance 0xc2c
#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain
#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
#define rOFDM0_RxDetector3 0xc38 //Frame Sync.
#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI
@ -255,7 +255,7 @@
#define rOFDM0_XBTxIQImbalance 0xc88
#define rOFDM0_XBTxAFE 0xc8c
#define rOFDM0_XCTxIQImbalance 0xc90
#define rOFDM0_XCTxAFE 0xc94
#define rOFDM0_XCTxAFE 0xc94
#define rOFDM0_XDTxIQImbalance 0xc98
#define rOFDM0_XDTxAFE 0xc9c
@ -298,8 +298,8 @@
#define rOFDM_LongCFOCD 0xdb8
#define rOFDM_TailCFOAB 0xdbc
#define rOFDM_TailCFOCD 0xdc0
#define rOFDM_PWMeasure1 0xdc4
#define rOFDM_PWMeasure2 0xdc8
#define rOFDM_PWMeasure1 0xdc4
#define rOFDM_PWMeasure2 0xdc8
#define rOFDM_BWReport 0xdcc
#define rOFDM_AGCReport 0xdd0
#define rOFDM_RxSNR 0xdd4
@ -324,7 +324,7 @@
#define rTx_IQK_PI_A 0xe38
#define rRx_IQK_PI_A 0xe3c
#define rTx_IQK 0xe40
#define rTx_IQK 0xe40
#define rRx_IQK 0xe44
#define rIQK_AGC_Pts 0xe48
#define rIQK_AGC_Rsp 0xe4c
@ -361,10 +361,10 @@
#define rRx_Power_After_IQK_B_2 0xecc
#define rRx_OFDM 0xed0
#define rRx_Wait_RIFS 0xed4
#define rRx_TO_Rx 0xed8
#define rStandby 0xedc
#define rSleep 0xee0
#define rRx_Wait_RIFS 0xed4
#define rRx_TO_Rx 0xed8
#define rStandby 0xedc
#define rSleep 0xee0
#define rPMPD_ANAEN 0xeec
//
@ -398,56 +398,56 @@
//
// RL6052 Register definition
//
#define RF_AC 0x00 //
#define RF_AC 0x00 //
#define RF_IQADJ_G1 0x01 //
#define RF_IQADJ_G2 0x02 //
#define RF_IQADJ_G1 0x01 //
#define RF_IQADJ_G2 0x02 //
#define RF_BS_PA_APSET_G1_G4 0x03
#define RF_BS_PA_APSET_G5_G8 0x04
#define RF_POW_TRSW 0x05 //
#define RF_POW_TRSW 0x05 //
#define RF_GAIN_RX 0x06 //
#define RF_GAIN_TX 0x07 //
#define RF_GAIN_RX 0x06 //
#define RF_GAIN_TX 0x07 //
#define RF_TXM_IDAC 0x08 //
#define RF_IPA_G 0x09 //
#define RF_TXM_IDAC 0x08 //
#define RF_IPA_G 0x09 //
#define RF_TXBIAS_G 0x0A
#define RF_TXPA_AG 0x0B
#define RF_IPA_A 0x0C //
#define RF_IPA_A 0x0C //
#define RF_TXBIAS_A 0x0D
#define RF_BS_PA_APSET_G9_G11 0x0E
#define RF_BS_IQGEN 0x0F //
#define RF_BS_IQGEN 0x0F //
#define RF_MODE1 0x10 //
#define RF_MODE2 0x11 //
#define RF_MODE1 0x10 //
#define RF_MODE2 0x11 //
#define RF_RX_AGC_HP 0x12 //
#define RF_TX_AGC 0x13 //
#define RF_BIAS 0x14 //
#define RF_IPA 0x15 //
#define RF_RX_AGC_HP 0x12 //
#define RF_TX_AGC 0x13 //
#define RF_BIAS 0x14 //
#define RF_IPA 0x15 //
#define RF_TXBIAS 0x16 //
#define RF_POW_ABILITY 0x17 //
#define RF_MODE_AG 0x18 //
#define RF_POW_ABILITY 0x17 //
#define RF_MODE_AG 0x18 //
#define rRfChannel 0x18 // RF channel and BW switch
#define RF_CHNLBW 0x18 // RF channel and BW switch
#define RF_TOP 0x19 //
#define RF_TOP 0x19 //
#define RF_RX_G1 0x1A //
#define RF_RX_G2 0x1B //
#define RF_RX_G1 0x1A //
#define RF_RX_G2 0x1B //
#define RF_RX_BB2 0x1C //
#define RF_RX_BB1 0x1D //
#define RF_RX_BB2 0x1C //
#define RF_RX_BB1 0x1D //
#define RF_RCK1 0x1E //
#define RF_RCK2 0x1F //
#define RF_RCK1 0x1E //
#define RF_RCK2 0x1F //
#define RF_TX_G1 0x20 //
#define RF_TX_G2 0x21 //
#define RF_TX_G3 0x22 //
#define RF_TX_G1 0x20 //
#define RF_TX_G2 0x21 //
#define RF_TX_G3 0x22 //
#define RF_TX_BB1 0x23 //
#define RF_TX_BB1 0x23 //
#define RF_T_METER 0x24 //
#define RF_T_METER 0x24 //
#define RF_SYN_G1 0x25 // RF TX Power control
#define RF_SYN_G2 0x26 // RF TX Power control
@ -513,7 +513,7 @@
#define bCCKTxStatus 0x1
#define bOFDMTxStatus 0x2
#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
// 2. Page8(0x800)
#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD
@ -522,157 +522,157 @@
#define bCCKEn 0x1000000
#define bOFDMEn 0x2000000
#define bOFDMRxADCPhase 0x10000 // Useless now
#define bOFDMTxDACPhase 0x40000
#define bXATxAGC 0x3f
#define bOFDMRxADCPhase 0x10000 // Useless now
#define bOFDMTxDACPhase 0x40000
#define bXATxAGC 0x3f
#define bAntennaSelect 0x0300
#define bAntennaSelect 0x0300
#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage
#define bXCTxAGC 0xf000
#define bXDTxAGC 0xf0000
#define bPAStart 0xf0000000 // Useless now
#define bTRStart 0x00f00000
#define bRFStart 0x0000f000
#define bBBStart 0x000000f0
#define bBBCCKStart 0x0000000f
#define bPAEnd 0xf //Reg0x814
#define bTREnd 0x0f000000
#define bRFEnd 0x000f0000
#define bCCAMask 0x000000f0 //T2R
#define bR2RCCAMask 0x00000f00
#define bHSSI_R2TDelay 0xf8000000
#define bHSSI_T2RDelay 0xf80000
#define bContTxHSSI 0x400 //chane gain at continue Tx
#define bIGFromCCK 0x200
#define bAGCAddress 0x3f
#define bRxHPTx 0x7000
#define bRxHPT2R 0x38000
#define bRxHPCCKIni 0xc0000
#define bAGCTxCode 0xc00000
#define bAGCRxCode 0x300000
#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage
#define bXCTxAGC 0xf000
#define bXDTxAGC 0xf0000
#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1
#define b3WireAddressLength 0x400
#define bPAStart 0xf0000000 // Useless now
#define bTRStart 0x00f00000
#define bRFStart 0x0000f000
#define bBBStart 0x000000f0
#define bBBCCKStart 0x0000000f
#define bPAEnd 0xf //Reg0x814
#define bTREnd 0x0f000000
#define bRFEnd 0x000f0000
#define bCCAMask 0x000000f0 //T2R
#define bR2RCCAMask 0x00000f00
#define bHSSI_R2TDelay 0xf8000000
#define bHSSI_T2RDelay 0xf80000
#define bContTxHSSI 0x400 //chane gain at continue Tx
#define bIGFromCCK 0x200
#define bAGCAddress 0x3f
#define bRxHPTx 0x7000
#define bRxHPT2R 0x38000
#define bRxHPCCKIni 0xc0000
#define bAGCTxCode 0xc00000
#define bAGCRxCode 0x300000
#define b3WireRFPowerDown 0x1 // Useless now
//#define bHWSISelect 0x8
#define b5GPAPEPolarity 0x40000000
#define b2GPAPEPolarity 0x80000000
#define bRFSW_TxDefaultAnt 0x3
#define bRFSW_TxOptionAnt 0x30
#define bRFSW_RxDefaultAnt 0x300
#define bRFSW_RxOptionAnt 0x3000
#define bRFSI_3WireData 0x1
#define bRFSI_3WireClock 0x2
#define bRFSI_3WireLoad 0x4
#define bRFSI_3WireRW 0x8
#define bRFSI_3Wire 0xf
#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1
#define b3WireAddressLength 0x400
#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW
#define b3WireRFPowerDown 0x1 // Useless now
//#define bHWSISelect 0x8
#define b5GPAPEPolarity 0x40000000
#define b2GPAPEPolarity 0x80000000
#define bRFSW_TxDefaultAnt 0x3
#define bRFSW_TxOptionAnt 0x30
#define bRFSW_RxDefaultAnt 0x300
#define bRFSW_RxOptionAnt 0x3000
#define bRFSI_3WireData 0x1
#define bRFSI_3WireClock 0x2
#define bRFSI_3WireLoad 0x4
#define bRFSI_3WireRW 0x8
#define bRFSI_3Wire 0xf
#define bRFSI_TRSW 0x20 // Useless now
#define bRFSI_TRSWB 0x40
#define bRFSI_ANTSW 0x100
#define bRFSI_ANTSWB 0x200
#define bRFSI_PAPE 0x400
#define bRFSI_PAPE5G 0x800
#define bBandSelect 0x1
#define bHTSIG2_GI 0x80
#define bHTSIG2_Smoothing 0x01
#define bHTSIG2_Sounding 0x02
#define bHTSIG2_Aggreaton 0x08
#define bHTSIG2_STBC 0x30
#define bHTSIG2_AdvCoding 0x40
#define bHTSIG2_NumOfHTLTF 0x300
#define bHTSIG2_CRC8 0x3fc
#define bHTSIG1_MCS 0x7f
#define bHTSIG1_BandWidth 0x80
#define bHTSIG1_HTLength 0xffff
#define bLSIG_Rate 0xf
#define bLSIG_Reserved 0x10
#define bLSIG_Length 0x1fffe
#define bLSIG_Parity 0x20
#define bCCKRxPhase 0x4
#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW
#define bLSSIReadAddress 0x7f800000 // T65 RF
#define bRFSI_TRSW 0x20 // Useless now
#define bRFSI_TRSWB 0x40
#define bRFSI_ANTSW 0x100
#define bRFSI_ANTSWB 0x200
#define bRFSI_PAPE 0x400
#define bRFSI_PAPE5G 0x800
#define bBandSelect 0x1
#define bHTSIG2_GI 0x80
#define bHTSIG2_Smoothing 0x01
#define bHTSIG2_Sounding 0x02
#define bHTSIG2_Aggreaton 0x08
#define bHTSIG2_STBC 0x30
#define bHTSIG2_AdvCoding 0x40
#define bHTSIG2_NumOfHTLTF 0x300
#define bHTSIG2_CRC8 0x3fc
#define bHTSIG1_MCS 0x7f
#define bHTSIG1_BandWidth 0x80
#define bHTSIG1_HTLength 0xffff
#define bLSIG_Rate 0xf
#define bLSIG_Reserved 0x10
#define bLSIG_Length 0x1fffe
#define bLSIG_Parity 0x20
#define bCCKRxPhase 0x4
#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
#define bLSSIReadAddress 0x7f800000 // T65 RF
#define bLSSIReadBackData 0xfffff // T65 RF
#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
#define bLSSIReadOKFlag 0x1000 // Useless now
#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
#define bRegulator0Standby 0x1
#define bRegulatorPLLStandby 0x2
#define bRegulator1Standby 0x4
#define bPLLPowerUp 0x8
#define bDPLLPowerUp 0x10
#define bDA10PowerUp 0x20
#define bAD7PowerUp 0x200
#define bDA6PowerUp 0x2000
#define bXtalPowerUp 0x4000
#define b40MDClkPowerUP 0x8000
#define bDA6DebugMode 0x20000
#define bDA6Swing 0x380000
#define bLSSIReadBackData 0xfffff // T65 RF
#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ
#define bLSSIReadOKFlag 0x1000 // Useless now
#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
#define bRegulator0Standby 0x1
#define bRegulatorPLLStandby 0x2
#define bRegulator1Standby 0x4
#define bPLLPowerUp 0x8
#define bDPLLPowerUp 0x10
#define bDA10PowerUp 0x20
#define bAD7PowerUp 0x200
#define bDA6PowerUp 0x2000
#define bXtalPowerUp 0x4000
#define b40MDClkPowerUP 0x8000
#define bDA6DebugMode 0x20000
#define bDA6Swing 0x380000
#define b80MClkDelay 0x18000000 // Useless
#define bAFEWatchDogEnable 0x20000000
#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ
#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap
#define bXtalCap23 0x3
#define b80MClkDelay 0x18000000 // Useless
#define bAFEWatchDogEnable 0x20000000
#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap
#define bXtalCap23 0x3
#define bXtalCap92x 0x0f000000
#define bXtalCap 0x0f000000
#define bXtalCap 0x0f000000
#define bIntDifClkEnable 0x400 // Useless
#define bExtSigClkEnable 0x800
#define bBandgapMbiasPowerUp 0x10000
#define bAD11SHGain 0xc0000
#define bAD11InputRange 0x700000
#define bAD11OPCurrent 0x3800000
#define bIPathLoopback 0x4000000
#define bQPathLoopback 0x8000000
#define bAFELoopback 0x10000000
#define bDA10Swing 0x7e0
#define bDA10Reverse 0x800
#define bDAClkSource 0x1000
#define bAD7InputRange 0x6000
#define bAD7Gain 0x38000
#define bAD7OutputCMMode 0x40000
#define bAD7InputCMMode 0x380000
#define bAD7Current 0xc00000
#define bRegulatorAdjust 0x7000000
#define bAD11PowerUpAtTx 0x1
#define bDA10PSAtTx 0x10
#define bAD11PowerUpAtRx 0x100
#define bDA10PSAtRx 0x1000
#define bCCKRxAGCFormat 0x200
#define bPSDFFTSamplepPoint 0xc000
#define bPSDAverageNum 0x3000
#define bIQPathControl 0xc00
#define bPSDFreq 0x3ff
#define bPSDAntennaPath 0x30
#define bPSDIQSwitch 0x40
#define bPSDRxTrigger 0x400000
#define bPSDTxTrigger 0x80000000
#define bPSDSineToneScale 0x7f000000
#define bPSDReport 0xffff
#define bIntDifClkEnable 0x400 // Useless
#define bExtSigClkEnable 0x800
#define bBandgapMbiasPowerUp 0x10000
#define bAD11SHGain 0xc0000
#define bAD11InputRange 0x700000
#define bAD11OPCurrent 0x3800000
#define bIPathLoopback 0x4000000
#define bQPathLoopback 0x8000000
#define bAFELoopback 0x10000000
#define bDA10Swing 0x7e0
#define bDA10Reverse 0x800
#define bDAClkSource 0x1000
#define bAD7InputRange 0x6000
#define bAD7Gain 0x38000
#define bAD7OutputCMMode 0x40000
#define bAD7InputCMMode 0x380000
#define bAD7Current 0xc00000
#define bRegulatorAdjust 0x7000000
#define bAD11PowerUpAtTx 0x1
#define bDA10PSAtTx 0x10
#define bAD11PowerUpAtRx 0x100
#define bDA10PSAtRx 0x1000
#define bCCKRxAGCFormat 0x200
#define bPSDFFTSamplepPoint 0xc000
#define bPSDAverageNum 0x3000
#define bIQPathControl 0xc00
#define bPSDFreq 0x3ff
#define bPSDAntennaPath 0x30
#define bPSDIQSwitch 0x40
#define bPSDRxTrigger 0x400000
#define bPSDTxTrigger 0x80000000
#define bPSDSineToneScale 0x7f000000
#define bPSDReport 0xffff
// 3. Page9(0x900)
#define bOFDMTxSC 0x30000000 // Useless
#define bCCKTxOn 0x1
#define bOFDMTxOn 0x2
#define bDebugPage 0xfff //reset debug page and also HWord, LWord
#define bDebugItem 0xff //reset debug page and LWord
#define bAntL 0x10
#define bAntNonHT 0x100
#define bAntHT1 0x1000
#define bAntHT2 0x10000
#define bAntHT1S1 0x100000
#define bAntNonHTS1 0x1000000
#define bOFDMTxSC 0x30000000 // Useless
#define bCCKTxOn 0x1
#define bOFDMTxOn 0x2
#define bDebugPage 0xfff //reset debug page and also HWord, LWord
#define bDebugItem 0xff //reset debug page and LWord
#define bAntL 0x10
#define bAntNonHT 0x100
#define bAntHT1 0x1000
#define bAntHT2 0x10000
#define bAntHT1S1 0x100000
#define bAntNonHTS1 0x1000000
// 4. PageA(0xA00)
#define bCCKBBMode 0x3 // Useless
@ -716,7 +716,7 @@
#define bCCKRxAGCSatCount 0xe0
#define bCCKRxRFSettle 0x1f //AGCsamp_dly
#define bCCKFixedRxAGC 0x8000
//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
#define bCCKAntennaPolarity 0x2000
#define bCCKTxFilterType 0x0c00
#define bCCKRxAGCReportType 0x0300
@ -748,9 +748,9 @@
#define bCCKRxFACounterLower 0xff
#define bCCKRxFACounterUpper 0xff000000
#define bCCKRxHPAGCStart 0xe000
#define bCCKRxHPAGCFinal 0x1c00
#define bCCKRxHPAGCFinal 0x1c00
#define bCCKRxFalseAlarmEnable 0x8000
#define bCCKFACounterFreeze 0x4000
#define bCCKFACounterFreeze 0x4000
#define bCCKTxPathSel 0x10000000
#define bCCKDefaultRxPath 0xc000000
#define bCCKOptionRxPath 0x3000000
@ -902,16 +902,16 @@
#define bRxSGI_TH 0xc0000000
#define bDFSCnt0 0xff
#define bDFSCnt1 0xff00
#define bDFSFlag 0xf0000
#define bDFSFlag 0xf0000
#define bMFWeightSum 0x300000
#define bMinIdxTH 0x7f000000
#define bDAFormat 0x40000
#define bTxChEmuEnable 0x01000000
#define bMinIdxTH 0x7f000000
#define bDAFormat 0x40000
#define bTxChEmuEnable 0x01000000
#define bTRSWIsolation_A 0x7f
#define bTRSWIsolation_B 0x7f00
#define bTRSWIsolation_C 0x7f0000
#define bTRSWIsolation_D 0x7f000000
#define bExtLNAGain 0x7c00
#define bTRSWIsolation_D 0x7f000000
#define bExtLNAGain 0x7c00
// 6. PageE(0xE00)
#define bSTBCEn 0x4 // Useless
@ -948,7 +948,7 @@
#define bLongCFOFLength 11
#define bTailCFO 0x1fff
#define bTailCFOTLength 13
#define bTailCFOFLength 12
#define bTailCFOFLength 12
#define bmax_en_pwdB 0xffff
#define bCC_power_dB 0xffff0000
#define bnoise_pwdB 0xffff
@ -956,27 +956,27 @@
#define bPowerMeasFLength 3
#define bRx_HT_BW 0x1
#define bRxSC 0x6
#define bRx_HT 0x8
#define bRx_HT 0x8
#define bNB_intf_det_on 0x1
#define bIntf_win_len_cfg 0x30
#define bNB_Intf_TH_cfg 0x1c0
#define bNB_Intf_TH_cfg 0x1c0
#define bRFGain 0x3f
#define bTableSel 0x40
#define bTRSW 0x80
#define bTRSW 0x80
#define bRxSNR_A 0xff
#define bRxSNR_B 0xff00
#define bRxSNR_C 0xff0000
#define bRxSNR_D 0xff000000
#define bSNREVMTLength 8
#define bSNREVMFLength 1
#define bSNREVMFLength 1
#define bCSI1st 0xff
#define bCSI2nd 0xff00
#define bRxEVM1st 0xff0000
#define bRxEVM2nd 0xff000000
#define bRxEVM2nd 0xff000000
#define bSIGEVM 0xff
#define bPWDB 0xff00
#define bSGIEN 0x10000
#define bSFactorQAM1 0xf // Useless
#define bSFactorQAM2 0xf0
#define bSFactorQAM3 0xf00
@ -987,7 +987,7 @@
#define bSFactorQAM8 0xf000000
#define bSFactorQAM9 0xf0000000
#define bCSIScheme 0x100000
#define bNoiseLvlTopSet 0x3 // Useless
#define bChSmooth 0x4
#define bChSmoothCfg1 0x38
@ -996,7 +996,7 @@
#define bChSmoothCfg4 0x7000
#define bMRCMode 0x800000
#define bTHEVMCfg 0x7000000
#define bLoopFitType 0x1 // Useless
#define bUpdCFO 0x40
#define bUpdCFOOffData 0x80
@ -1070,24 +1070,24 @@
#define bMaskLWord 0x0000ffff
#define bMaskDWord 0xffffffff
#define bMask12Bits 0xfff
#define bMaskH4Bits 0xf0000000
#define bMaskH4Bits 0xf0000000
#define bMaskOFDM_D 0xffc00000
#define bMaskCCK 0x3f3f3f3f
//for PutRFRegsetting & GetRFRegSetting BitMask
//#define bMask12Bits 0xfffff // RF Reg mask bits
//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF
#define bRFRegOffsetMask 0xfffff
#define bRFRegOffsetMask 0xfffff
#define bEnable 0x1 // Useless
#define bDisable 0x0
#define LeftAntenna 0x0 // Useless
#define RightAntenna 0x1
#define tCheckTxStatus 500 //500ms // Useless
#define tUpdateRxCounter 100 //100ms
#define rateCCK 0 // Useless
#define rateOFDM 1
#define rateHT 2
@ -1110,7 +1110,7 @@
#define bPMACControl 0x0 // Useless
#define bWMACControl 0x1
#define bWNICControl 0x2
#define PathA 0x0 // Useless
#define PathB 0x1
#define PathC 0x2
@ -1120,4 +1120,3 @@
#endif //__INC_HAL8192SPHYREG_H

129
include/Hal8192DPhyCfg.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -22,18 +22,18 @@
* Module: __INC_HAL8192DPHYCFG_H
*
*
* Note:
*
* Note:
*
*
* Export: Constants, macro, functions(API), global variables(None).
*
* Abbrev:
* Abbrev:
*
* History:
* Data Who Remark
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* Data Who Remark
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* 2. Reorganize code architecture.
*
*
*****************************************************************************/
/* Check to see if the file has been included already. */
#ifndef __INC_HAL8192DPHYCFG_H
@ -74,7 +74,7 @@
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure----------------------------*/
typedef enum _SwChnlCmdID{
CmdID_End,
CmdID_SetTxPowerLevel,
@ -115,7 +115,7 @@ typedef enum _RF_RADIO_PATH{
RF_PATH_B = 1, //Radio Path B
RF_PATH_C = 2, //Radio Path C
RF_PATH_D = 3, //Radio Path D
//RF_PATH_MAX //Max RF number 90 support
//RF_PATH_MAX //Max RF number 90 support
}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E;
#define RF_PATH_MAX 2
@ -150,8 +150,8 @@ typedef enum _WIRELESS_MODE {
#if (RTL8192D_DUAL_MAC_MODE_SWITCH == 1)
typedef enum _BaseBand_Config_Type{
BaseBand_Config_PHY_REG = 0,
BaseBand_Config_AGC_TAB = 1,
BaseBand_Config_PHY_REG = 0,
BaseBand_Config_AGC_TAB = 1,
BaseBand_Config_AGC_TAB_2G = 2,
BaseBand_Config_AGC_TAB_5G = 3,
}BaseBand_Config_Type, *PBaseBand_Config_Type;
@ -166,7 +166,7 @@ typedef enum _BaseBand_Config_Type{
typedef enum _MACPHY_MODE_8192D{
SINGLEMAC_SINGLEPHY, //SMSP
DUALMAC_DUALPHY, //DMDP
DUALMAC_SINGLEPHY, //DMSP
DUALMAC_SINGLEPHY, //DMSP
}MACPHY_MODE_8192D,*PMACPHY_MODE_8192D;
typedef enum _MACPHY_MODE_CHANGE_ACTION{
@ -180,7 +180,7 @@ typedef enum _MACPHY_MODE_CHANGE_ACTION{
}MACPHY_MODE_CHANGE_ACTION,*PMACPHY_MODE_CHANGE_ACTION;
typedef enum _BAND_TYPE{
BAND_ON_2_4G = 1,
BAND_ON_2_4G = 1,
BAND_ON_5G = 2,
BAND_ON_BOTH,
BANDMAX
@ -201,77 +201,77 @@ typedef enum _PHY_Rate_Tx_Power_Offset_Area{
typedef enum _RF_TYPE_8190P{
RF_TYPE_MIN, // 0
RF_8225=1, // 1 11b/g RF for verification only
RF_8256=2, // 2 11b/g/n
RF_8256=2, // 2 11b/g/n
RF_8258=3, // 3 11a/b/g/n RF
RF_6052=4, // 4 11b/g/n RF
//RF_6052=5, // 4 11b/g/n RF
// TODO: We sholud remove this psudo PHY RF after we get new RF.
RF_PSEUDO_11N=5, // 5, It is a temporality RF.
RF_PSEUDO_11N=5, // 5, It is a temporality RF.
}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
typedef struct _BB_REGISTER_DEFINITION{
u32 rfintfs; // set software control:
u32 rfintfs; // set software control:
// 0x870~0x877[8 bytes]
u32 rfintfi; // readback data:
u32 rfintfi; // readback data:
// 0x8e0~0x8e7[8 bytes]
u32 rfintfo; // output data:
u32 rfintfo; // output data:
// 0x860~0x86f [16 bytes]
u32 rfintfe; // output enable:
u32 rfintfe; // output enable:
// 0x860~0x86f [16 bytes]
u32 rf3wireOffset; // LSSI data:
// 0x840~0x84f [16 bytes]
u32 rfLSSI_Select; // BB Band Select:
u32 rfLSSI_Select; // BB Band Select:
// 0x878~0x87f [8 bytes]
u32 rfTxGainStage; // Tx gain stage:
u32 rfTxGainStage; // Tx gain stage:
// 0x80c~0x80f [4 bytes]
u32 rfHSSIPara1; // wire parameter control1 :
u32 rfHSSIPara1; // wire parameter control1 :
// 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
u32 rfHSSIPara2; // wire parameter control2 :
u32 rfHSSIPara2; // wire parameter control2 :
// 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
u32 rfSwitchControl; //Tx Rx antenna control :
u32 rfSwitchControl; //Tx Rx antenna control :
// 0x858~0x85f [16 bytes]
u32 rfAGCControl1; //AGC parameter control1 :
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
u32 rfAGCControl2; //AGC parameter control2 :
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
u32 rfAGCControl1; //AGC parameter control1 :
// 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
u32 rfAGCControl2; //AGC parameter control2 :
// 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
// 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
// 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
// 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type
// 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
u32 rfLSSIReadBack; //LSSI RF readback data SI mode
u32 rfLSSIReadBack; //LSSI RF readback data SI mode
// 0x8a0~0x8af [16 bytes]
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
typedef struct _R_ANTENNA_SELECT_OFDM{
u32 r_tx_antenna:4;
typedef struct _R_ANTENNA_SELECT_OFDM{
u32 r_tx_antenna:4;
u32 r_ant_l:4;
u32 r_ant_non_ht:4;
u32 r_ant_non_ht:4;
u32 r_ant_ht1:4;
u32 r_ant_ht2:4;
u32 r_ant_ht_s1:4;
@ -281,12 +281,12 @@ typedef struct _R_ANTENNA_SELECT_OFDM{
}R_ANTENNA_SELECT_OFDM;
typedef struct _R_ANTENNA_SELECT_CCK{
u8 r_cckrx_enable_2:2;
u8 r_cckrx_enable_2:2;
u8 r_cckrx_enable:2;
u8 r_ccktx_enable:4;
}R_ANTENNA_SELECT_CCK;
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
@ -329,7 +329,7 @@ extern int PHY_BBConfig8192D( IN struct adapter *Adapter );
extern int PHY_RFConfig8192D( IN struct adapter *Adapter );
/* RF config */
int rtl8192d_PHY_ConfigRFWithParaFile( IN struct adapter *Adapter,
IN u8* pFileName,
IN u8* pFileName,
IN RF_RADIO_PATH_E eRFPath);
int rtl8192d_PHY_ConfigRFWithHeaderFile( IN struct adapter * Adapter,
IN RF_CONTENT Content,
@ -344,21 +344,21 @@ void rtl8192d_PHY_GetHWRegOriginalValue( IN struct adapter * Adapter );
//
// RF Power setting
//
//extern BOOLEAN PHY_SetRFPowerState(IN struct adapter * Adapter,
//extern BOOLEAN PHY_SetRFPowerState(IN struct adapter * Adapter,
// IN RT_RF_POWER_STATE eRFPowerState);
//
// BB TX Power R/W
//
void PHY_GetTxPowerLevel8192D( IN struct adapter * Adapter,
OUT u32* powerlevel );
OUT u32* powerlevel );
void PHY_SetTxPowerLevel8192D( IN struct adapter * Adapter,
IN u8 channel );
BOOLEAN PHY_UpdateTxPowerDbm8192D( IN struct adapter *Adapter,
IN int powerInDbm );
//
VOID
VOID
PHY_ScanOperationBackup8192D(IN struct adapter *Adapter,
IN u8 Operation );
@ -396,7 +396,7 @@ void PHY_SwChnlPhy8192D( IN struct adapter * pAdapter,
extern void ChkFwCmdIoDone( IN struct adapter *Adapter);
//
// BB/MAC/RF other monitor API
//
@ -410,7 +410,7 @@ BOOLEAN PHY_CheckIsLegalRfPath8192D(IN struct adapter *pAdapter,
//
// Modify the value of the hw register when beacon interval be changed.
//
void
void
rtl8192d_PHY_SetBeaconHwReg( IN struct adapter * Adapter,
IN u16 BeaconInterval );
@ -428,7 +428,7 @@ PHY_EnableHostClkReq(
BOOLEAN
SetAntennaConfig92C(
IN struct adapter *Adapter,
IN u8 DefaultAnt
IN u8 DefaultAnt
);
VOID
@ -439,7 +439,7 @@ PHY_UpdateBBRFConfiguration8192D(
VOID PHY_ReadMacPhyMode92D(
IN struct adapter *Adapter,
IN BOOLEAN AutoloadFail
IN BOOLEAN AutoloadFail
);
VOID PHY_ConfigMacPhyMode92D(
@ -460,7 +460,7 @@ rtl8192d_PHY_InitRxSetting(
);
VOID
VOID
rtl8192d_PHY_SetRFPathSwitch(IN struct adapter *pAdapter, IN BOOLEAN bMain);
VOID
@ -469,7 +469,7 @@ HalChangeCCKStatus8192D(
IN BOOLEAN bCCKDisable
);
VOID
VOID
PHY_InitPABias92D(IN struct adapter *Adapter);
/*--------------------------Exported Function prototype---------------------*/
@ -484,4 +484,3 @@ PHY_InitPABias92D(IN struct adapter *Adapter);
#define PHY_QueryMacReg PHY_QueryBBReg
#endif // __INC_HAL8192SPHYCFG_H

2309
include/Hal8192DPhyReg.h
View file

File diff suppressed because it is too large Load diff

59
include/Hal8723APhyCfg.h
View file

@ -1,30 +1,29 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8723PHYCFG_H__
#define __INC_HAL8723PHYCFG_H__
#include <Hal8192CPhyCfg.h>
/* MAC/BB/RF HAL config */
int PHY_BBConfig8723A( IN struct adapter *Adapter );
int PHY_RFConfig8723A( IN struct adapter *Adapter );
s32 PHY_MACConfig8723A(struct adapter *padapter);
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8723PHYCFG_H__
#define __INC_HAL8723PHYCFG_H__
#include <Hal8192CPhyCfg.h>
/* MAC/BB/RF HAL config */
int PHY_BBConfig8723A( IN struct adapter *Adapter );
int PHY_RFConfig8723A( IN struct adapter *Adapter );
s32 PHY_MACConfig8723A(struct adapter *padapter);
#endif

147
include/Hal8723APhyReg.h
View file

@ -1,74 +1,73 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8723APHYREG_H__
#define __INC_HAL8723APHYREG_H__
#include <Hal8192CPhyReg.h>
//
// PageB(0xB00)
//
#define rPdp_AntA 0xb00
#define rPdp_AntA_4 0xb04
#define rPdp_AntA_8 0xb08
#define rPdp_AntA_C 0xb0c
#define rPdp_AntA_10 0xb10
#define rPdp_AntA_14 0xb14
#define rPdp_AntA_18 0xb18
#define rPdp_AntA_1C 0xb1c
#define rPdp_AntA_20 0xb20
#define rPdp_AntA_24 0xb24
#define rConfig_Pmpd_AntA 0xb28
#define rConfig_ram64x16 0xb2c
#define rBndA 0xb30
#define rHssiPar 0xb34
#define rConfig_AntA 0xb68
#define rConfig_AntB 0xb6c
#define rPdp_AntB 0xb70
#define rPdp_AntB_4 0xb74
#define rPdp_AntB_8 0xb78
#define rPdp_AntB_C 0xb7c
#define rPdp_AntB_10 0xb80
#define rPdp_AntB_14 0xb84
#define rPdp_AntB_18 0xb88
#define rPdp_AntB_1C 0xb8c
#define rPdp_AntB_20 0xb90
#define rPdp_AntB_24 0xb94
#define rConfig_Pmpd_AntB 0xb98
#define rBndB 0xba0
#define rAPK 0xbd8
#define rPm_Rx0_AntA 0xbdc
#define rPm_Rx1_AntA 0xbe0
#define rPm_Rx2_AntA 0xbe4
#define rPm_Rx3_AntA 0xbe8
#define rPm_Rx0_AntB 0xbec
#define rPm_Rx1_AntB 0xbf0
#define rPm_Rx2_AntB 0xbf4
#define rPm_Rx3_AntB 0xbf8
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8723APHYREG_H__
#define __INC_HAL8723APHYREG_H__
#include <Hal8192CPhyReg.h>
//
// PageB(0xB00)
//
#define rPdp_AntA 0xb00
#define rPdp_AntA_4 0xb04
#define rPdp_AntA_8 0xb08
#define rPdp_AntA_C 0xb0c
#define rPdp_AntA_10 0xb10
#define rPdp_AntA_14 0xb14
#define rPdp_AntA_18 0xb18
#define rPdp_AntA_1C 0xb1c
#define rPdp_AntA_20 0xb20
#define rPdp_AntA_24 0xb24
#define rConfig_Pmpd_AntA 0xb28
#define rConfig_ram64x16 0xb2c
#define rBndA 0xb30
#define rHssiPar 0xb34
#define rConfig_AntA 0xb68
#define rConfig_AntB 0xb6c
#define rPdp_AntB 0xb70
#define rPdp_AntB_4 0xb74
#define rPdp_AntB_8 0xb78
#define rPdp_AntB_C 0xb7c
#define rPdp_AntB_10 0xb80
#define rPdp_AntB_14 0xb84
#define rPdp_AntB_18 0xb88
#define rPdp_AntB_1C 0xb8c
#define rPdp_AntB_20 0xb90
#define rPdp_AntB_24 0xb94
#define rConfig_Pmpd_AntB 0xb98
#define rBndB 0xba0
#define rAPK 0xbd8
#define rPm_Rx0_AntA 0xbdc
#define rPm_Rx1_AntA 0xbe0
#define rPm_Rx2_AntA 0xbe4
#define rPm_Rx3_AntA 0xbe8
#define rPm_Rx0_AntB 0xbec
#define rPm_Rx1_AntB 0xbf0
#define rPm_Rx2_AntB 0xbf4
#define rPm_Rx3_AntB 0xbf8
#endif

341
include/Hal8723PwrSeq.h
View file

@ -1,171 +1,170 @@
#ifndef __HAL8723PWRSEQ_H__
#define __HAL8723PWRSEQ_H__
/*
Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
There are 6 HW Power States:
0: POFF--Power Off
1: PDN--Power Down
2: CARDEMU--Card Emulation
3: ACT--Active Mode
4: LPS--Low Power State
5: SUS--Suspend
The transision from different states are defined below
TRANS_CARDEMU_TO_ACT
TRANS_ACT_TO_CARDEMU
TRANS_CARDEMU_TO_SUS
TRANS_SUS_TO_CARDEMU
TRANS_CARDEMU_TO_PDN
TRANS_ACT_TO_LPS
TRANS_LPS_TO_ACT
TRANS_END
*/
#include "HalPwrSeqCmd.h"
#include "rtl8723a_spec.h"
#define RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS 15
#define RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS 15
#define RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS 15
#define RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS 15
#define RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS 15
#define RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS 15
#define RTL8723A_TRANS_ACT_TO_LPS_STEPS 15
#define RTL8723A_TRANS_LPS_TO_ACT_STEPS 15
#define RTL8723A_TRANS_END_STEPS 1
#define RTL8723A_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 1},/*0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */\
#define RTL8723A_TRANS_ACT_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \
#define RTL8723A_TRANS_CARDEMU_TO_SUS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8723A_TRANS_SUS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
#define RTL8723A_TRANS_CARDEMU_TO_PDN \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
#define RTL8723A_TRANS_PDN_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
#define RTL8723A_TRANS_ACT_TO_LPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
#define RTL8723A_TRANS_LPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8723A_TRANS_END \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
extern WLAN_PWR_CFG rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS];
#endif
#ifndef __HAL8723PWRSEQ_H__
#define __HAL8723PWRSEQ_H__
/*
Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
There are 6 HW Power States:
0: POFF--Power Off
1: PDN--Power Down
2: CARDEMU--Card Emulation
3: ACT--Active Mode
4: LPS--Low Power State
5: SUS--Suspend
The transision from different states are defined below
TRANS_CARDEMU_TO_ACT
TRANS_ACT_TO_CARDEMU
TRANS_CARDEMU_TO_SUS
TRANS_SUS_TO_CARDEMU
TRANS_CARDEMU_TO_PDN
TRANS_ACT_TO_LPS
TRANS_LPS_TO_ACT
TRANS_END
*/
#include "HalPwrSeqCmd.h"
#include "rtl8723a_spec.h"
#define RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS 15
#define RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS 15
#define RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS 15
#define RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS 15
#define RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS 15
#define RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS 15
#define RTL8723A_TRANS_ACT_TO_LPS_STEPS 15
#define RTL8723A_TRANS_LPS_TO_ACT_STEPS 15
#define RTL8723A_TRANS_END_STEPS 1
#define RTL8723A_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 1},/*0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */\
#define RTL8723A_TRANS_ACT_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \
#define RTL8723A_TRANS_CARDEMU_TO_SUS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8723A_TRANS_SUS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
#define RTL8723A_TRANS_CARDEMU_TO_PDN \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
#define RTL8723A_TRANS_PDN_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
#define RTL8723A_TRANS_ACT_TO_LPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
#define RTL8723A_TRANS_LPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8723A_TRANS_END \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
extern WLAN_PWR_CFG rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STEPS+RTL8723A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS];
#endif

275
include/HalPwrSeqCmd.h
View file

@ -1,138 +1,137 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HALPWRSEQCMD_H__
#define __HALPWRSEQCMD_H__
#include <drv_types.h>
/*---------------------------------------------*/
//3 The value of cmd: 4 bits
/*---------------------------------------------*/
#define PWR_CMD_READ 0x00
// offset: the read register offset
// msk: the mask of the read value
// value: N/A, left by 0
// note: dirver shall implement this function by read & msk
#define PWR_CMD_WRITE 0x01
// offset: the read register offset
// msk: the mask of the write bits
// value: write value
// note: driver shall implement this cmd by read & msk after write
#define PWR_CMD_POLLING 0x02
// offset: the read register offset
// msk: the mask of the polled value
// value: the value to be polled, masked by the msd field.
// note: driver shall implement this cmd by
// do{
// if( (Read(offset) & msk) == (value & msk) )
// break;
// } while(not timeout);
#define PWR_CMD_DELAY 0x03
// offset: the value to delay
// msk: N/A
// value: the unit of delay, 0: us, 1: ms
#define PWR_CMD_END 0x04
// offset: N/A
// msk: N/A
// value: N/A
/*---------------------------------------------*/
//3 The value of base: 4 bits
/*---------------------------------------------*/
// define the base address of each block
#define PWR_BASEADDR_MAC 0x00
#define PWR_BASEADDR_USB 0x01
#define PWR_BASEADDR_PCIE 0x02
#define PWR_BASEADDR_SDIO 0x03
/*---------------------------------------------*/
//3 The value of interface_msk: 4 bits
/*---------------------------------------------*/
#define PWR_INTF_SDIO_MSK BIT(0)
#define PWR_INTF_USB_MSK BIT(1)
#define PWR_INTF_PCI_MSK BIT(2)
#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
/*---------------------------------------------*/
//3 The value of fab_msk: 4 bits
/*---------------------------------------------*/
#define PWR_FAB_TSMC_MSK BIT(0)
#define PWR_FAB_UMC_MSK BIT(1)
#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
/*---------------------------------------------*/
//3 The value of cut_msk: 8 bits
/*---------------------------------------------*/
#define PWR_CUT_TESTCHIP_MSK BIT(0)
#define PWR_CUT_A_MSK BIT(1)
#define PWR_CUT_B_MSK BIT(2)
#define PWR_CUT_C_MSK BIT(3)
#define PWR_CUT_D_MSK BIT(4)
#define PWR_CUT_E_MSK BIT(5)
#define PWR_CUT_F_MSK BIT(6)
#define PWR_CUT_G_MSK BIT(7)
#define PWR_CUT_ALL_MSK 0xFF
typedef enum _PWRSEQ_CMD_DELAY_UNIT_
{
PWRSEQ_DELAY_US,
PWRSEQ_DELAY_MS,
} PWRSEQ_DELAY_UNIT;
typedef struct _WL_PWR_CFG_
{
u16 offset;
u8 cut_msk;
u8 fab_msk:4;
u8 interface_msk:4;
u8 base:4;
u8 cmd:4;
u8 msk;
u8 value;
} WLAN_PWR_CFG, *PWLAN_PWR_CFG;
#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk
#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk
#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk
#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base
#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
//================================================================================
// Prototype of protected function.
//================================================================================
u8 HalPwrSeqCmdParsing(
struct adapter * padapter,
u8 CutVersion,
u8 FabVersion,
u8 InterfaceType,
WLAN_PWR_CFG PwrCfgCmd[]);
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HALPWRSEQCMD_H__
#define __HALPWRSEQCMD_H__
#include <drv_types.h>
/*---------------------------------------------*/
//3 The value of cmd: 4 bits
/*---------------------------------------------*/
#define PWR_CMD_READ 0x00
// offset: the read register offset
// msk: the mask of the read value
// value: N/A, left by 0
// note: dirver shall implement this function by read & msk
#define PWR_CMD_WRITE 0x01
// offset: the read register offset
// msk: the mask of the write bits
// value: write value
// note: driver shall implement this cmd by read & msk after write
#define PWR_CMD_POLLING 0x02
// offset: the read register offset
// msk: the mask of the polled value
// value: the value to be polled, masked by the msd field.
// note: driver shall implement this cmd by
// do{
// if( (Read(offset) & msk) == (value & msk) )
// break;
// } while(not timeout);
#define PWR_CMD_DELAY 0x03
// offset: the value to delay
// msk: N/A
// value: the unit of delay, 0: us, 1: ms
#define PWR_CMD_END 0x04
// offset: N/A
// msk: N/A
// value: N/A
/*---------------------------------------------*/
//3 The value of base: 4 bits
/*---------------------------------------------*/
// define the base address of each block
#define PWR_BASEADDR_MAC 0x00
#define PWR_BASEADDR_USB 0x01
#define PWR_BASEADDR_PCIE 0x02
#define PWR_BASEADDR_SDIO 0x03
/*---------------------------------------------*/
//3 The value of interface_msk: 4 bits
/*---------------------------------------------*/
#define PWR_INTF_SDIO_MSK BIT(0)
#define PWR_INTF_USB_MSK BIT(1)
#define PWR_INTF_PCI_MSK BIT(2)
#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
/*---------------------------------------------*/
//3 The value of fab_msk: 4 bits
/*---------------------------------------------*/
#define PWR_FAB_TSMC_MSK BIT(0)
#define PWR_FAB_UMC_MSK BIT(1)
#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
/*---------------------------------------------*/
//3 The value of cut_msk: 8 bits
/*---------------------------------------------*/
#define PWR_CUT_TESTCHIP_MSK BIT(0)
#define PWR_CUT_A_MSK BIT(1)
#define PWR_CUT_B_MSK BIT(2)
#define PWR_CUT_C_MSK BIT(3)
#define PWR_CUT_D_MSK BIT(4)
#define PWR_CUT_E_MSK BIT(5)
#define PWR_CUT_F_MSK BIT(6)
#define PWR_CUT_G_MSK BIT(7)
#define PWR_CUT_ALL_MSK 0xFF
typedef enum _PWRSEQ_CMD_DELAY_UNIT_
{
PWRSEQ_DELAY_US,
PWRSEQ_DELAY_MS,
} PWRSEQ_DELAY_UNIT;
typedef struct _WL_PWR_CFG_
{
u16 offset;
u8 cut_msk;
u8 fab_msk:4;
u8 interface_msk:4;
u8 base:4;
u8 cmd:4;
u8 msk;
u8 value;
} WLAN_PWR_CFG, *PWLAN_PWR_CFG;
#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk
#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk
#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk
#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base
#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
//================================================================================
// Prototype of protected function.
//================================================================================
u8 HalPwrSeqCmdParsing(
struct adapter * padapter,
u8 CutVersion,
u8 FabVersion,
u8 InterfaceType,
WLAN_PWR_CFG PwrCfgCmd[]);
#endif

65
include/HalVerDef.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -20,60 +20,60 @@
#ifndef __HAL_VERSION_DEF_H__
#define __HAL_VERSION_DEF_H__
#define TRUE _TRUE
#define TRUE _TRUE
#define FALSE _FALSE
// HAL_IC_TYPE_E
typedef enum tag_HAL_IC_Type_Definition
{
CHIP_8192S = 0,
CHIP_8188C = 1,
CHIP_8192C = 2,
CHIP_8192D = 3,
CHIP_8723A = 4,
CHIP_8188E = 5,
CHIP_8881A = 6,
CHIP_8812A = 7,
CHIP_8821A = 8,
CHIP_8723B = 9,
CHIP_8192E = 10,
CHIP_8192S = 0,
CHIP_8188C = 1,
CHIP_8192C = 2,
CHIP_8192D = 3,
CHIP_8723A = 4,
CHIP_8188E = 5,
CHIP_8881A = 6,
CHIP_8812A = 7,
CHIP_8821A = 8,
CHIP_8723B = 9,
CHIP_8192E = 10,
}HAL_IC_TYPE_E;
//HAL_CHIP_TYPE_E
typedef enum tag_HAL_CHIP_Type_Definition
{
TEST_CHIP = 0,
NORMAL_CHIP = 1,
TEST_CHIP = 0,
NORMAL_CHIP = 1,
FPGA = 2,
}HAL_CHIP_TYPE_E;
//HAL_CUT_VERSION_E
typedef enum tag_HAL_Cut_Version_Definition
{
A_CUT_VERSION = 0,
B_CUT_VERSION = 1,
C_CUT_VERSION = 2,
D_CUT_VERSION = 3,
E_CUT_VERSION = 4,
F_CUT_VERSION = 5,
G_CUT_VERSION = 6,
H_CUT_VERSION = 7,
I_CUT_VERSION = 8,
J_CUT_VERSION = 9,
K_CUT_VERSION = 10,
A_CUT_VERSION = 0,
B_CUT_VERSION = 1,
C_CUT_VERSION = 2,
D_CUT_VERSION = 3,
E_CUT_VERSION = 4,
F_CUT_VERSION = 5,
G_CUT_VERSION = 6,
H_CUT_VERSION = 7,
I_CUT_VERSION = 8,
J_CUT_VERSION = 9,
K_CUT_VERSION = 10,
}HAL_CUT_VERSION_E;
// HAL_Manufacturer
typedef enum tag_HAL_Manufacturer_Version_Definition
{
CHIP_VENDOR_TSMC = 0,
CHIP_VENDOR_UMC = 1,
CHIP_VENDOR_TSMC = 0,
CHIP_VENDOR_UMC = 1,
}HAL_VENDOR_E;
typedef enum tag_HAL_RF_Type_Definition
{
RF_TYPE_1T1R = 0,
RF_TYPE_1T2R = 1,
RF_TYPE_1T1R = 0,
RF_TYPE_1T2R = 1,
RF_TYPE_2T2R = 2,
RF_TYPE_2T3R = 3,
RF_TYPE_2T4R = 4,
@ -88,7 +88,7 @@ typedef struct tag_HAL_VERSION
HAL_CHIP_TYPE_E ChipType;
HAL_CUT_VERSION_E CUTVersion;
HAL_VENDOR_E VendorType;
HAL_RF_TYPE_E RFType;
HAL_RF_TYPE_E RFType;
u8 ROMVer;
}HAL_VERSION,*PHAL_VERSION;
@ -145,7 +145,7 @@ typedef struct tag_HAL_VERSION
//----------------------------------------------------------------------------
#define IS_81XXC_TEST_CHIP(version) ((IS_81XXC(version) && (!IS_NORMAL_CHIP(version)))? TRUE: FALSE)
#define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? TRUE : FALSE)
#define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? TRUE : FALSE)
#define IS_81xxC_VENDOR_UMC_A_CUT(version) (IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE): FALSE)
#define IS_81xxC_VENDOR_UMC_B_CUT(version) (IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE): FALSE)
#define IS_81xxC_VENDOR_UMC_C_CUT(version) (IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE): FALSE)
@ -161,4 +161,3 @@ typedef struct tag_HAL_VERSION
#define IS_8723A_B_CUT(version) ((IS_8723_SERIES(version)) ? ( IS_B_CUT(version)?TRUE : FALSE) : FALSE)
#endif

135
include/autoconf.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -35,20 +35,20 @@
#define RTL871X_MODULE_NAME "88EU"
#define DRV_NAME "rtl8188eu"
#define CONFIG_USB_HCI
#define CONFIG_USB_HCI
#define CONFIG_RTL8188E
#define CONFIG_RTL8188E
#if defined(CONFIG_PLATFORM_ACTIONS_ATM702X)
#ifndef CONFIG_IOCTL_CFG80211
#define CONFIG_IOCTL_CFG80211
#ifndef CONFIG_IOCTL_CFG80211
#define CONFIG_IOCTL_CFG80211
#endif
#endif
#ifdef CONFIG_IOCTL_CFG80211
//#define RTW_USE_CFG80211_STA_EVENT /* Indecate new sta asoc through cfg80211_new_sta */
#define CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER
//#define CONFIG_DEBUG_CFG80211
//#define CONFIG_DEBUG_CFG80211
//#define CONFIG_DRV_ISSUE_PROV_REQ // IOT FOR S2
#define CONFIG_SET_SCAN_DENY_TIMER
@ -60,37 +60,37 @@
//#define CONFIG_H2CLBK
#define CONFIG_EMBEDDED_FWIMG
#define CONFIG_EMBEDDED_FWIMG
//#define CONFIG_FILE_FWIMG
#define CONFIG_XMIT_ACK
#ifdef CONFIG_XMIT_ACK
#define CONFIG_ACTIVE_KEEP_ALIVE_CHECK
#endif
#define CONFIG_80211N_HT
#define CONFIG_80211N_HT
#define CONFIG_RECV_REORDERING_CTRL
#define CONFIG_RECV_REORDERING_CTRL
//#define CONFIG_TCP_CSUM_OFFLOAD_RX
//#define CONFIG_TCP_CSUM_OFFLOAD_RX
//#define CONFIG_DRVEXT_MODULE
//#define CONFIG_DRVEXT_MODULE
#define CONFIG_SUPPORT_USB_INT
#ifdef CONFIG_SUPPORT_USB_INT
//#define CONFIG_USB_INTERRUPT_IN_PIPE
//#define CONFIG_USB_INTERRUPT_IN_PIPE
#endif
#define CONFIG_IPS
#define CONFIG_IPS
#ifdef CONFIG_IPS
//#define CONFIG_IPS_LEVEL_2 //enable this to set default IPS mode to IPS_LEVEL_2
#endif
#define SUPPORT_HW_RFOFF_DETECTED
#define SUPPORT_HW_RFOFF_DETECTED
#define CONFIG_LPS
#define CONFIG_LPS
#if defined(CONFIG_LPS) && defined(CONFIG_SUPPORT_USB_INT)
//#define CONFIG_LPS_LCLK
//#define CONFIG_LPS_LCLK
#endif
#ifdef CONFIG_LPS_LCLK
@ -101,21 +101,21 @@
#define CONFIG_ANTENNA_DIVERSITY
//after link
#ifdef CONFIG_ANTENNA_DIVERSITY
#define CONFIG_HW_ANTENNA_DIVERSITY
#ifdef CONFIG_ANTENNA_DIVERSITY
#define CONFIG_HW_ANTENNA_DIVERSITY
#endif
//#define CONFIG_CONCURRENT_MODE
//#define CONFIG_CONCURRENT_MODE
#ifdef CONFIG_CONCURRENT_MODE
//#define CONFIG_HWPORT_SWAP //Port0->Sec , Port1 -> Pri
//#define CONFIG_STA_MODE_SCAN_UNDER_AP_MODE
#define CONFIG_TSF_RESET_OFFLOAD // For 2 PORT TSF SYNC.
#define CONFIG_TSF_RESET_OFFLOAD // For 2 PORT TSF SYNC.
#endif
#define CONFIG_IOL
#define CONFIG_AP_MODE
#define CONFIG_AP_MODE
#ifdef CONFIG_AP_MODE
//#define CONFIG_INTERRUPT_BASED_TXBCN // Tx Beacon when driver BCN_OK ,BCN_ERR interrupt occurs
#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_INTERRUPT_BASED_TXBCN)
@ -123,22 +123,22 @@
#endif
#ifdef CONFIG_INTERRUPT_BASED_TXBCN
//#define CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
#define CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
#define CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
#endif
#define CONFIG_NATIVEAP_MLME
#ifndef CONFIG_NATIVEAP_MLME
#define CONFIG_HOSTAPD_MLME
#endif
#define CONFIG_FIND_BEST_CHANNEL
//#define CONFIG_NO_WIRELESS_HANDLERS
#define CONFIG_HOSTAPD_MLME
#endif
#define CONFIG_FIND_BEST_CHANNEL
//#define CONFIG_NO_WIRELESS_HANDLERS
#endif
#define CONFIG_P2P
#define CONFIG_P2P
#ifdef CONFIG_P2P
//The CONFIG_WFD is for supporting the Wi-Fi display
#define CONFIG_WFD
#ifndef CONFIG_WIFI_TEST
#define CONFIG_P2P_REMOVE_GROUP_INFO
#endif
@ -150,13 +150,13 @@
#endif
// Added by Kurt 20110511
//#define CONFIG_TDLS
//#define CONFIG_TDLS
#ifdef CONFIG_TDLS
// #ifndef CONFIG_WFD
// #define CONFIG_WFD
// #define CONFIG_WFD
// #endif
// #define CONFIG_TDLS_AUTOSETUP
// #define CONFIG_TDLS_AUTOCHECKALIVE
// #define CONFIG_TDLS_AUTOSETUP
// #define CONFIG_TDLS_AUTOCHECKALIVE
#endif
@ -175,9 +175,9 @@
#define CONFIG_IOL_READ_EFUSE_MAP
//#define DBG_IOL_READ_EFUSE_MAP
//#define CONFIG_IOL_LLT
#define CONFIG_IOL_EFUSE_PATCH
#define CONFIG_IOL_EFUSE_PATCH
//#define CONFIG_IOL_IOREG_CFG
//#define CONFIG_IOL_IOREG_CFG_DBG
//#define CONFIG_IOL_IOREG_CFG_DBG
#endif
@ -201,31 +201,31 @@
#endif // CONFIG_BR_EXT
#define CONFIG_TX_MCAST2UNI // Support IP multicast->unicast
//#define CONFIG_CHECK_AC_LIFETIME // Check packet lifetime of 4 ACs.
//#define CONFIG_CHECK_AC_LIFETIME // Check packet lifetime of 4 ACs.
/*
* Interface Related Config
/*
* Interface Related Config
*/
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
#define CONFIG_USB_TX_AGGREGATION
#define CONFIG_USB_RX_AGGREGATION
#define CONFIG_USB_TX_AGGREGATION
#define CONFIG_USB_RX_AGGREGATION
#endif
#define CONFIG_PREALLOC_RECV_SKB
#define CONFIG_PREALLOC_RECV_SKB
//#define CONFIG_REDUCE_USB_TX_INT // Trade-off: Improve performance, but may cause TX URBs blocked by USB Host/Bus driver on few platforms.
//#define CONFIG_EASY_REPLACEMENT
//#define CONFIG_EASY_REPLACEMENT
/*
/*
* CONFIG_USE_USB_BUFFER_ALLOC_XX uses Linux USB Buffer alloc API and is for Linux platform only now!
*/
//#define CONFIG_USE_USB_BUFFER_ALLOC_TX // Trade-off: For TX path, improve stability on some platforms, but may cause performance degrade on other platforms.
//#define CONFIG_USE_USB_BUFFER_ALLOC_RX // For RX path
//#define CONFIG_USE_USB_BUFFER_ALLOC_TX // Trade-off: For TX path, improve stability on some platforms, but may cause performance degrade on other platforms.
//#define CONFIG_USE_USB_BUFFER_ALLOC_RX // For RX path
#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
#undef CONFIG_PREALLOC_RECV_SKB
#endif
/*
/*
* USB VENDOR REQ BUFFER ALLOCATION METHOD
* if not set we'll use function local variable (stack memory)
*/
@ -235,7 +235,7 @@
#define CONFIG_USB_VENDOR_REQ_MUTEX
#define CONFIG_VENDOR_REQ_RETRY
//#define CONFIG_USB_SUPPORT_ASYNC_VDN_REQ
//#define CONFIG_USB_SUPPORT_ASYNC_VDN_REQ
/*
@ -254,7 +254,7 @@
#define ENABLE_USB_DROP_INCORRECT_OUT
//#define RTL8192CU_ADHOC_WORKAROUND_SETTING
//#define RTL8192CU_ADHOC_WORKAROUND_SETTING
#define DISABLE_BB_RF 0
@ -268,8 +268,8 @@
*/
#ifdef CONFIG_PLATFORM_MN10300
#define CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
#define CONFIG_USE_USB_BUFFER_ALLOC_RX
#define CONFIG_USE_USB_BUFFER_ALLOC_RX
#if defined (CONFIG_SW_ANTENNA_DIVERSITY)
#undef CONFIG_SW_ANTENNA_DIVERSITY
#define CONFIG_HW_ANTENNA_DIVERSITY
@ -278,18 +278,18 @@
#if defined (CONFIG_POWER_SAVING)
#undef CONFIG_POWER_SAVING
#endif
#endif//CONFIG_PLATFORM_MN10300
#ifdef CONFIG_PLATFORM_TI_DM365
#define CONFIG_USE_USB_BUFFER_ALLOC_RX
#define CONFIG_USE_USB_BUFFER_ALLOC_RX
#endif
#if defined(CONFIG_PLATFORM_ACTIONS_ATM702X)
#ifdef CONFIG_USB_TX_AGGREGATION
#ifdef CONFIG_USB_TX_AGGREGATION
#undef CONFIG_USB_TX_AGGREGATION
#endif
#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX
@ -305,20 +305,20 @@
* Outsource Related Config
*/
#define RTL8192CE_SUPPORT 0
#define RTL8192CU_SUPPORT 0
#define RTL8192C_SUPPORT (RTL8192CE_SUPPORT|RTL8192CU_SUPPORT)
#define RTL8192CE_SUPPORT 0
#define RTL8192CU_SUPPORT 0
#define RTL8192C_SUPPORT (RTL8192CE_SUPPORT|RTL8192CU_SUPPORT)
#define RTL8192DE_SUPPORT 0
#define RTL8192DU_SUPPORT 0
#define RTL8192D_SUPPORT (RTL8192DE_SUPPORT|RTL8192DU_SUPPORT)
#define RTL8192DE_SUPPORT 0
#define RTL8192DU_SUPPORT 0
#define RTL8192D_SUPPORT (RTL8192DE_SUPPORT|RTL8192DU_SUPPORT)
#define RTL8723AU_SUPPORT 0
#define RTL8723AS_SUPPORT 0
#define RTL8723AE_SUPPORT 0
#define RTL8723A_SUPPORT (RTL8723AU_SUPPORT|RTL8723AS_SUPPORT|RTL8723AE_SUPPORT)
#define RTL8723AU_SUPPORT 0
#define RTL8723AS_SUPPORT 0
#define RTL8723AE_SUPPORT 0
#define RTL8723A_SUPPORT (RTL8723AU_SUPPORT|RTL8723AS_SUPPORT|RTL8723AE_SUPPORT)
#define RTL8723_FPGA_VERIFICATION 0
#define RTL8723_FPGA_VERIFICATION 0
#define RTL8188EE_SUPPORT 0
#define RTL8188EU_SUPPORT 1
@ -326,13 +326,13 @@
#define RTL8188E_SUPPORT (RTL8188EE_SUPPORT|RTL8188EU_SUPPORT|RTL8188ES_SUPPORT)
#define RTL8188E_FOR_TEST_CHIP 0
//#if (RTL8188E_SUPPORT==1)
#define RATE_ADAPTIVE_SUPPORT 1
#define RATE_ADAPTIVE_SUPPORT 1
#define POWER_TRAINING_ACTIVE 1
//#endif
#ifdef CONFIG_USB_TX_AGGREGATION
//#define CONFIG_TX_EARLY_MODE
//#define CONFIG_TX_EARLY_MODE
#endif
#ifdef CONFIG_TX_EARLY_MODE
@ -381,10 +381,9 @@
//#define DBG_HAL_INIT_PROFILING
//#define DBG_MEMORY_LEAK
//#define DBG_MEMORY_LEAK
//TX use 1 urb
//#define CONFIG_SINGLE_XMIT_BUF
//RX use 1 urb
//#define CONFIG_SINGLE_RECV_BUF

41
include/basic_types.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -29,13 +29,13 @@
#ifndef TRUE
#define _TRUE 1
#else
#define _TRUE TRUE
#define _TRUE TRUE
#endif
#ifndef FALSE
#ifndef FALSE
#define _FALSE 0
#else
#define _FALSE FALSE
#define _FALSE FALSE
#endif
#include <linux/types.h>
@ -55,14 +55,14 @@
#define UCHAR u8
#define USHORT u16
#define UINT u32
#define ULONG u32
#define ULONG u32
typedef void (*proc_t)(void*);
typedef __kernel_size_t SIZE_T;
typedef __kernel_size_t SIZE_T;
typedef __kernel_ssize_t SSIZE_T;
#define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field)
#define MEM_ALIGNMENT_OFFSET (sizeof (SIZE_T))
#define MEM_ALIGNMENT_PADDING (sizeof(SIZE_T) - 1)
@ -83,8 +83,8 @@
//
// Byte Swapping routine.
//
#define EF1Byte
#define EF2Byte le16_to_cpu
#define EF1Byte
#define EF2Byte le16_to_cpu
#define EF4Byte le32_to_cpu
//
@ -99,7 +99,7 @@
//
#define WriteEF1Byte(_ptr, _val) (*((u8 *)(_ptr)))=EF1Byte(_val)
#define WriteEF2Byte(_ptr, _val) (*((u16 *)(_ptr)))=EF2Byte(_val)
#define WriteEF4Byte(_ptr, _val) (*((u32 *)(_ptr)))=EF4Byte(_val)
#define WriteEF4Byte(_ptr, _val) (*((u32 *)(_ptr)))=EF4Byte(_val)
//
// Example:
@ -116,7 +116,7 @@
// BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
//
#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \
(BIT_LEN_MASK_32(__BitLen) << (__BitOffset))
(BIT_LEN_MASK_32(__BitLen) << (__BitOffset))
//
// Description:
@ -140,7 +140,7 @@
//
// Description:
// Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering
// Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering
// and return the result in 4-byte value in host byte ordering.
//
#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
@ -152,7 +152,7 @@
//
// Description:
// Set subfield of little-endian 4-byte value to specified value.
// Set subfield of little-endian 4-byte value to specified value.
//
#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
*((u32 *)(__pStart)) = \
@ -162,23 +162,23 @@
( (((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset) ) \
);
#define BIT_LEN_MASK_16(__BitLen) \
(0xFFFF >> (16 - (__BitLen)))
#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) \
(BIT_LEN_MASK_16(__BitLen) << (__BitOffset))
#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) \
(EF2Byte(*((u16 *)(__pStart))))
#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
( \
( LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset) ) \
& \
BIT_LEN_MASK_16(__BitLen) \
)
#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
( \
LE_P2BYTE_TO_HOST_2BYTE(__pStart) \
@ -193,7 +193,7 @@
| \
( (((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset) ) \
);
#define BIT_LEN_MASK_8(__BitLen) \
(0xFF >> (8 - (__BitLen)))
@ -248,4 +248,3 @@
typedef unsigned char BOOLEAN,*PBOOLEAN;
#endif //__BASIC_TYPES_H__

3
include/circ_buf.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -25,4 +25,3 @@
#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size))
#endif //_CIRC_BUF_H_

3
include/cmd_osdep.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -33,4 +33,3 @@ extern sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj);
extern struct cmd_obj *_rtw_dequeue_cmd(_queue *queue);
#endif

5
include/drv_conf.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -56,7 +56,7 @@
#endif
//About USB VENDOR REQ
#if defined(CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
#if defined(CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
#warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC automatically"
#define CONFIG_USB_VENDOR_REQ_MUTEX
#endif
@ -69,4 +69,3 @@
//#include <rtl871x_byteorder.h>
#endif // __DRV_CONF_H__

27
include/drv_types.h
View file

@ -112,7 +112,7 @@ struct registry_priv
u8 network_mode; //infra, ad-hoc, auto
u8 channel;//ad-hoc support requirement
u8 wireless_mode;//A, B, G, auto
u8 scan_mode;//active, passive
u8 scan_mode;//active, passive
u8 radio_enable;
u8 preamble;//long, short, auto
u8 vrtl_carrier_sense;//Enable, Disable, Auto
@ -150,7 +150,7 @@ struct registry_priv
u8 ht_enable;
u8 cbw40_enable;
u8 ampdu_enable;//for tx
u8 rx_stbc;
u8 rx_stbc;
u8 ampdu_amsdu;//A-MPDU Supports A-MSDU is permitted
#endif
u8 lowrate_two_xmit;
@ -241,8 +241,8 @@ struct registry_priv
enum _IFACE_ID {
IFACE_ID0, //maping to PRIMARY_ADAPTER
IFACE_ID1, //maping to SECONDARY_ADAPTER
IFACE_ID2,
IFACE_ID3,
IFACE_ID2,
IFACE_ID3,
IFACE_ID_MAX,
};
@ -250,7 +250,7 @@ struct dvobj_priv
{
struct adapter *if1; //PRIMARY_ADAPTER
struct adapter *if2; //SECONDARY_ADAPTER
s32 processing_dev_remove;
//for local/global synchronization
@ -343,10 +343,10 @@ struct dvobj_priv
u8 const_hwsw_rfoff_d3;
u8 const_support_pciaspm;
// pci-e bridge */
u8 const_hostpci_aspm_setting;
u8 const_hostpci_aspm_setting;
// pci-e device */
u8 const_devicepci_aspm_setting;
u8 b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00.
u8 const_devicepci_aspm_setting;
u8 b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00.
u8 b_support_backdoor;
u8 bdma64;
@ -425,7 +425,7 @@ struct adapter {
int DriverState;// for disable driver using module, use dongle to replace module.
int pid[3];//process id from UI, 0:wps, 1:hostapd, 2:dhcpcd
int bDongle;//build-in module or external dongle
u16 chip_type;
u16 chip_type;
u16 HardwareType;
u16 interface_type;//USB,SDIO,SPI,PCI
@ -435,20 +435,20 @@ struct adapter {
struct cmd_priv cmdpriv;
struct evt_priv evtpriv;
//struct io_queue *pio_queue;
struct io_priv iopriv;
struct io_priv iopriv;
struct xmit_priv xmitpriv;
struct recv_priv recvpriv;
struct sta_priv stapriv;
struct security_priv securitypriv;
_lock security_key_mutex; // add for CONFIG_IEEE80211W, none 11w also can use
struct registry_priv registrypriv;
struct eeprom_priv eeprompriv;
struct eeprom_priv eeprompriv;
struct led_priv ledpriv;
#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
//Check BT status for BT Hung.
struct workqueue_struct *priv_checkbt_wq;
struct delayed_work checkbt_work;
#endif
#endif
#ifdef CONFIG_DRVEXT_MODULE
struct drvext_priv drvextpriv;
@ -611,4 +611,3 @@ __inline static u8 *myid(struct eeprom_priv *peepriv)
#endif //__DRV_TYPES_H__

7
include/drv_types_ce.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -49,7 +49,7 @@ typedef struct _MP_REG_ENTRY
u8 Type; // NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString
uint FieldOffset; // offset to MP_ADAPTER field
uint FieldSize; // size (in bytes) of the field
#ifdef UNDER_AMD64
u64 Default;
#else
@ -64,7 +64,7 @@ typedef struct _MP_REG_ENTRY
typedef struct _USB_EXTENSION {
LPCUSB_FUNCS _lpUsbFuncs;
USB_HANDLE _hDevice;
PVOID pAdapter;
PVOID pAdapter;
#if 0
USB_ENDPOINT_DESCRIPTOR _endpACLIn;
@ -90,4 +90,3 @@ typedef struct _OCTET_STRING{
#endif

89
include/drv_types_gspi.h
View file

@ -1,45 +1,44 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __DRV_TYPES_GSPI_H__
#define __DRV_TYPES_GSPI_H__
#include <drv_conf.h>
#include <basic_types.h>
// SPI Header Files
#include <linux/spi/spi.h>
typedef struct gspi_data
{
u8 func_number;
u8 tx_block_mode;
u8 rx_block_mode;
u32 block_transfer_len;
struct spi_device *func;
struct workqueue_struct *priv_wq;
struct delayed_work irq_work;
} GSPI_DATA, *PGSPI_DATA;
#endif // #ifndef __DRV_TYPES_GSPI_H__
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __DRV_TYPES_GSPI_H__
#define __DRV_TYPES_GSPI_H__
#include <drv_conf.h>
#include <basic_types.h>
// SPI Header Files
#include <linux/spi/spi.h>
typedef struct gspi_data
{
u8 func_number;
u8 tx_block_mode;
u8 rx_block_mode;
u32 block_transfer_len;
struct spi_device *func;
struct workqueue_struct *priv_wq;
struct delayed_work irq_work;
} GSPI_DATA, *PGSPI_DATA;
#endif // #ifndef __DRV_TYPES_GSPI_H__

3
include/drv_types_linux.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -22,4 +22,3 @@
#endif

83
include/drv_types_sdio.h
View file

@ -1,42 +1,41 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __DRV_TYPES_SDIO_H__
#define __DRV_TYPES_SDIO_H__
#include <drv_conf.h>
#include <basic_types.h>
// SDIO Header Files
#include <linux/mmc/sdio_func.h>
typedef struct sdio_data
{
u8 func_number;
u8 tx_block_mode;
u8 rx_block_mode;
u32 block_transfer_len;
struct sdio_func *func;
_thread_hdl_ sys_sdio_irq_thd;
} SDIO_DATA, *PSDIO_DATA;
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __DRV_TYPES_SDIO_H__
#define __DRV_TYPES_SDIO_H__
#include <drv_conf.h>
#include <basic_types.h>
// SDIO Header Files
#include <linux/mmc/sdio_func.h>
typedef struct sdio_data
{
u8 func_number;
u8 tx_block_mode;
u8 rx_block_mode;
u32 block_transfer_len;
struct sdio_func *func;
_thread_hdl_ sys_sdio_irq_thd;
} SDIO_DATA, *PSDIO_DATA;
#endif

5
include/drv_types_xp.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -70,7 +70,7 @@ typedef struct _MP_REG_ENTRY
u8 Type; // NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString
uint FieldOffset; // offset to MP_ADAPTER field
uint FieldSize; // size (in bytes) of the field
#ifdef UNDER_AMD64
u64 Default;
#else
@ -92,4 +92,3 @@ typedef struct _OCTET_STRING{
#endif

7
include/ethernet.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -17,7 +17,7 @@
*
*
******************************************************************************/
/*! \file */
/*! \file */
#ifndef __INC_ETHERNET_H
#define __INC_ETHERNET_H
@ -30,7 +30,7 @@
#define RT_ETH_IS_MULTICAST(_pAddr) ((((UCHAR *)(_pAddr))[0]&0x01)!=0) //!< Is Multicast Address?
#define RT_ETH_IS_BROADCAST(_pAddr) ( \
((UCHAR *)(_pAddr))[0]==0xff && \
((UCHAR *)(_pAddr))[0]==0xff && \
((UCHAR *)(_pAddr))[1]==0xff && \
((UCHAR *)(_pAddr))[2]==0xff && \
((UCHAR *)(_pAddr))[3]==0xff && \
@ -39,4 +39,3 @@
#endif // #ifndef __INC_ETHERNET_H

1
include/gspi_hal.h
View file

@ -26,4 +26,3 @@ void rtl8188es_set_hal_ops(struct adapter *padapter);
#define hal_set_hal_ops rtl8188es_set_hal_ops
#endif //__GSPI_HAL_H__

66
include/gspi_ops.h
View file

@ -25,28 +25,28 @@
* suppose that it will be the same
* for diff chips of GSPI, if not
* we should move it to HAL folder */
#define SPI_LOCAL_DOMAIN 0x0
#define WLAN_IOREG_DOMAIN 0x8
#define FW_FIFO_DOMAIN 0x4
#define TX_HIQ_DOMAIN 0xc
#define TX_MIQ_DOMAIN 0xd
#define TX_LOQ_DOMAIN 0xe
#define RX_RXFIFO_DOMAIN 0x1f
#define SPI_LOCAL_DOMAIN 0x0
#define WLAN_IOREG_DOMAIN 0x8
#define FW_FIFO_DOMAIN 0x4
#define TX_HIQ_DOMAIN 0xc
#define TX_MIQ_DOMAIN 0xd
#define TX_LOQ_DOMAIN 0xe
#define RX_RXFIFO_DOMAIN 0x1f
//IO Bus domain address mapping
#define DEFUALT_OFFSET 0x0
#define SPI_LOCAL_OFFSET 0x10250000
#define WLAN_IOREG_OFFSET 0x10260000
#define FW_FIFO_OFFSET 0x10270000
#define TX_HIQ_OFFSET 0x10310000
#define SPI_LOCAL_OFFSET 0x10250000
#define WLAN_IOREG_OFFSET 0x10260000
#define FW_FIFO_OFFSET 0x10270000
#define TX_HIQ_OFFSET 0x10310000
#define TX_MIQ_OFFSET 0x1032000
#define TX_LOQ_OFFSET 0x10330000
#define RX_RXOFF_OFFSET 0x10340000
#define RX_RXOFF_OFFSET 0x10340000
//SPI Local registers
#define SPI_REG_TX_CTRL 0x0000 // SPI Tx Control
#define SPI_REG_STATUS_RECOVERY 0x0004
#define SPI_REG_INT_TIMEOUT 0x0006
#define SPI_REG_INT_TIMEOUT 0x0006
#define SPI_REG_HIMR 0x0014 // SPI Host Interrupt Mask
#define SPI_REG_HISR 0x0018 // SPI Host Interrupt Service Routine
#define SPI_REG_RX0_REQ_LEN 0x001C // RXDMA Request Length
@ -62,18 +62,18 @@
#define SPI_REG_HISR_ON 0x0091 //SPI Host Extension Interrupt Status Always
#define SPI_REG_CFG 0x00F0 //SPI Configuration Register
#define SPI_TX_CTRL (SPI_REG_TX_CTRL |SPI_LOCAL_OFFSET)
#define SPI_STATUS_RECOVERY (SPI_REG_STATUS_RECOVERY |SPI_LOCAL_OFFSET)
#define SPI_INT_TIMEOUT (SPI_REG_INT_TIMEOUT |SPI_LOCAL_OFFSET)
#define SPI_HIMR (SPI_REG_HIMR |SPI_LOCAL_OFFSET)
#define SPI_HISR (SPI_REG_HISR |SPI_LOCAL_OFFSET)
#define SPI_RX0_REQ_LEN_1_BYTE (SPI_REG_RX0_REQ_LEN |SPI_LOCAL_OFFSET)
#define SPI_FREE_TXPG (SPI_REG_FREE_TXPG |SPI_LOCAL_OFFSET)
#define SPI_TX_CTRL (SPI_REG_TX_CTRL |SPI_LOCAL_OFFSET)
#define SPI_STATUS_RECOVERY (SPI_REG_STATUS_RECOVERY |SPI_LOCAL_OFFSET)
#define SPI_INT_TIMEOUT (SPI_REG_INT_TIMEOUT |SPI_LOCAL_OFFSET)
#define SPI_HIMR (SPI_REG_HIMR |SPI_LOCAL_OFFSET)
#define SPI_HISR (SPI_REG_HISR |SPI_LOCAL_OFFSET)
#define SPI_RX0_REQ_LEN_1_BYTE (SPI_REG_RX0_REQ_LEN |SPI_LOCAL_OFFSET)
#define SPI_FREE_TXPG (SPI_REG_FREE_TXPG |SPI_LOCAL_OFFSET)
#define SPI_HIMR_DISABLED 0
//SPI HIMR MASK diff with SDIO
#define SPI_HISR_RX_REQUEST BIT(0)
#define SPI_HISR_RX_REQUEST BIT(0)
#define SPI_HISR_AVAL BIT(1)
#define SPI_HISR_TXERR BIT(2)
#define SPI_HISR_RXERR BIT(3)
@ -110,17 +110,17 @@
SPI_HISR_PSTIMEOUT |\
SPI_HISR_OCPINT)
#define REG_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 8, x)//(x<<(unsigned int)24)
#define REG_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)//(x<<(unsigned int)16)
#define REG_DOMAIN_ID_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)//(x<<(unsigned int)0)
#define REG_FUN_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)//(x<<(unsigned int)5)
#define REG_RW_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)//(x<<(unsigned int)7)
#define REG_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 8, x)//(x<<(unsigned int)24)
#define REG_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)//(x<<(unsigned int)16)
#define REG_DOMAIN_ID_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)//(x<<(unsigned int)0)
#define REG_FUN_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)//(x<<(unsigned int)5)
#define REG_RW_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)//(x<<(unsigned int)7)
#define FIFO_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 16, x)//(x<<(unsigned int)24)
//#define FIFO_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)//(x<<(unsigned int)16)
#define FIFO_DOMAIN_ID_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)//(x<<(unsigned int)0)
#define FIFO_FUN_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)//(x<<(unsigned int)5)
#define FIFO_RW_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)//(x<<(unsigned int)7)
#define FIFO_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 16, x)//(x<<(unsigned int)24)
//#define FIFO_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)//(x<<(unsigned int)16)
#define FIFO_DOMAIN_ID_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)//(x<<(unsigned int)0)
#define FIFO_FUN_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)//(x<<(unsigned int)5)
#define FIFO_RW_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)//(x<<(unsigned int)7)
//get status dword0
@ -133,8 +133,8 @@
//get status dword1
#define GET_STATUS_HISR_MID8BIT(status) LE_BITS_TO_4BYTE(status + 4, 24, 8)
#define GET_STATUS_HISR_LOW8BIT(status) LE_BITS_TO_4BYTE(status + 4, 16, 8)
#define GET_STATUS_ERROR(status) LE_BITS_TO_4BYTE(status + 4, 17, 1)
#define GET_STATUS_INT(status) LE_BITS_TO_4BYTE(status + 4, 16, 1)
#define GET_STATUS_ERROR(status) LE_BITS_TO_4BYTE(status + 4, 17, 1)
#define GET_STATUS_INT(status) LE_BITS_TO_4BYTE(status + 4, 16, 1)
#define GET_STATUS_RX_LENGTH(status) LE_BITS_TO_4BYTE(status + 4, 0, 16)

1
include/gspi_ops_linux.h
View file

@ -21,4 +21,3 @@
#define __SDIO_OPS_LINUX_H__
#endif

1
include/gspi_osintf.h
View file

@ -32,4 +32,3 @@ extern void sd_setup_irs(struct adapter *padapter);
#endif
#endif

3
include/h2clbk.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -33,4 +33,3 @@ void _lbk_rsp(struct adapter *Adapter);
void _lbk_evt(IN struct adapter *Adapter);
void h2c_event_callback(unsigned char *dev, unsigned char *pbuf);

17
include/hal_com.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -28,7 +28,7 @@
#define RATR_2M 0x00000002
#define RATR_55M 0x00000004
#define RATR_11M 0x00000008
//OFDM
//OFDM
#define RATR_6M 0x00000010
#define RATR_9M 0x00000020
#define RATR_12M 0x00000040
@ -37,7 +37,7 @@
#define RATR_36M 0x00000200
#define RATR_48M 0x00000400
#define RATR_54M 0x00000800
//MCS 1 Spatial Stream
//MCS 1 Spatial Stream
#define RATR_MCS0 0x00001000
#define RATR_MCS1 0x00002000
#define RATR_MCS2 0x00004000
@ -61,7 +61,7 @@
#define RATE_2M BIT(1)
#define RATE_5_5M BIT(2)
#define RATE_11M BIT(3)
//OFDM
//OFDM
#define RATE_6M BIT(4)
#define RATE_9M BIT(5)
#define RATE_12M BIT(6)
@ -90,15 +90,15 @@
#define RATE_MCS15 BIT(27)
// ALL CCK Rate
#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M
#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M
#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\
RATR_36M|RATR_48M|RATR_54M
RATR_36M|RATR_48M|RATR_54M
#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\
RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7
RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7
#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11|\
RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
/*------------------------------ Tx Desc definition Macro ------------------------*/
/*------------------------------ Tx Desc definition Macro ------------------------*/
//#pragma mark -- Tx Desc related definition. --
//----------------------------------------------------------------------------
//-----------------------------------------------------------
@ -182,4 +182,3 @@ u8 SetHalDefVar(struct adapter *adapter, HAL_DEF_VARIABLE variable, void *value)
u8 GetHalDefVar(struct adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
#endif //__HAL_COMMON_H__

37
include/hal_intf.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -31,8 +31,8 @@
enum RTL871X_HCI_TYPE {
RTW_PCIE = BIT0,
RTW_USB = BIT1,
RTW_SDIO = BIT2,
RTW_USB = BIT1,
RTW_SDIO = BIT2,
RTW_GSPI = BIT3,
};
@ -43,7 +43,7 @@ enum _CHIP_TYPE {
RTL8188C_8192C,
RTL8192D,
RTL8723A,
RTL8188E,
RTL8188E,
MAX_CHIP_TYPE
};
@ -101,7 +101,7 @@ typedef enum _HW_VARIABLES{
HW_VAR_INITIAL_GAIN,
HW_VAR_TRIGGER_GPIO_0,
HW_VAR_BT_SET_COEXIST,
HW_VAR_BT_ISSUE_DELBA,
HW_VAR_BT_ISSUE_DELBA,
HW_VAR_CURRENT_ANTENNA,
HW_VAR_ANTENNA_DIVERSITY_LINK,
HW_VAR_ANTENNA_DIVERSITY_SELECT,
@ -121,7 +121,7 @@ typedef enum _HW_VARIABLES{
HW_VAR_SYS_CLKR,
HW_VAR_NAV_UPPER,
HW_VAR_RPT_TIMER_SETTING,
HW_VAR_TX_RPT_MAX_MACID,
HW_VAR_TX_RPT_MAX_MACID,
HW_VAR_H2C_MEDIA_STATUS_RPT,
HW_VAR_CHK_HI_QUEUE_EMPTY,
HW_VAR_READ_LLT_TAB,
@ -150,7 +150,7 @@ typedef enum _HAL_DEF_VARIABLE{
}HAL_DEF_VARIABLE;
typedef enum _HAL_ODM_VARIABLE{
HAL_ODM_STA_INFO,
HAL_ODM_STA_INFO,
HAL_ODM_P2P_STATE,
HAL_ODM_WIFI_DISPLAY_STATE,
}HAL_ODM_VARIABLE;
@ -243,14 +243,14 @@ struct hal_ops {
void (*ReadEFuse)(struct adapter *padapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, BOOLEAN bPseudoTest);
void (*EFUSEGetEfuseDefinition)(struct adapter *padapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest);
u16 (*EfuseGetCurrentSize)(struct adapter *padapter, u8 efuseType, BOOLEAN bPseudoTest);
int (*Efuse_PgPacketRead)(struct adapter *padapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);
int (*Efuse_PgPacketWrite)(struct adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
int (*Efuse_PgPacketRead)(struct adapter *padapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);
int (*Efuse_PgPacketWrite)(struct adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
u8 (*Efuse_WordEnableDataWrite)(struct adapter *padapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
BOOLEAN (*Efuse_PgPacketWrite_BT)(struct adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
#ifdef DBG_CONFIG_ERROR_DETECT
void (*sreset_init_value)(struct adapter *padapter);
void (*sreset_reset_value)(struct adapter *padapter);
void (*sreset_reset_value)(struct adapter *padapter);
void (*silentreset)(struct adapter *padapter);
void (*sreset_xmit_status_check)(struct adapter *padapter);
void (*sreset_linked_status_check) (struct adapter *padapter);
@ -273,8 +273,8 @@ struct hal_ops {
void (*hal_init_checkbthang_workqueue)(struct adapter * padapter);
void (*hal_free_checkbthang_workqueue)(struct adapter * padapter);
void (*hal_cancel_checkbthang_workqueue)(struct adapter * padapter);
void (*hal_checke_bt_hang)(struct adapter * padapter);
#endif
void (*hal_checke_bt_hang)(struct adapter * padapter);
#endif
};
typedef enum _RT_EEPROM_TYPE{
@ -286,10 +286,10 @@ typedef enum _RT_EEPROM_TYPE{
#define RF_CHANGE_BY_INIT 0
#define RF_CHANGE_BY_IPS BIT28
#define RF_CHANGE_BY_PS BIT29
#define RF_CHANGE_BY_HW BIT30
#define RF_CHANGE_BY_SW BIT31
#define RF_CHANGE_BY_IPS BIT28
#define RF_CHANGE_BY_PS BIT29
#define RF_CHANGE_BY_HW BIT30
#define RF_CHANGE_BY_SW BIT31
typedef enum _HARDWARE_TYPE{
HARDWARE_TYPE_RTL8180,
@ -412,7 +412,7 @@ u8 rtw_hal_get_def_var(struct adapter *padapter, HAL_DEF_VARIABLE eVariable, PVO
void rtw_hal_set_odm_var(struct adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,BOOLEAN bSet);
void rtw_hal_get_odm_var(struct adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,BOOLEAN bSet);
void rtw_hal_enable_interrupt(struct adapter *padapter);
void rtw_hal_disable_interrupt(struct adapter *padapter);
@ -484,4 +484,3 @@ s32 rtw_hal_c2h_handler(struct adapter *adapter, struct c2h_evt_hdr *c2h_evt);
c2h_id_filter rtw_hal_c2h_id_filter_ccx(struct adapter *adapter);
#endif //__HAL_INTF_H__

57
include/ieee80211.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -115,11 +115,11 @@ enum {
#define IEEE_CRYPT_ALG_NAME_LEN 16
#define WPA_CIPHER_NONE BIT(0)
#define WPA_CIPHER_WEP40 BIT(1)
#define WPA_CIPHER_NONE BIT(0)
#define WPA_CIPHER_WEP40 BIT(1)
#define WPA_CIPHER_WEP104 BIT(2)
#define WPA_CIPHER_TKIP BIT(3)
#define WPA_CIPHER_CCMP BIT(4)
#define WPA_CIPHER_TKIP BIT(3)
#define WPA_CIPHER_CCMP BIT(4)
@ -171,8 +171,8 @@ enum NETWORK_TYPE
WIRELESS_11A = BIT(2), // tx: ofdm only, rx: ofdm only, hw: ofdm only
WIRELESS_11_24N = BIT(3), // tx: MCS only, rx: MCS & cck, hw: MCS & cck
WIRELESS_11_5N = BIT(4), // tx: MCS only, rx: MCS & ofdm, hw: ofdm only
//WIRELESS_AUTO = BIT(5),
WIRELESS_AC = BIT(6),
//WIRELESS_AUTO = BIT(5),
WIRELESS_AC = BIT(6),
//Combination
WIRELESS_11BG = (WIRELESS_11B|WIRELESS_11G), // tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm
@ -198,7 +198,7 @@ enum NETWORK_TYPE
#define IsSupportedTxCCK(NetType) ((NetType) & (WIRELESS_11B) ? _TRUE : _FALSE)
#define IsSupportedTxOFDM(NetType) ((NetType) & (WIRELESS_11G|WIRELESS_11A) ? _TRUE : _FALSE)
#define IsSupportedTxMCS(NetType) ((NetType) & (WIRELESS_11_24N|WIRELESS_11_5N) ? _TRUE : _FALSE)
#define IsSupportedTxMCS(NetType) ((NetType) & (WIRELESS_11_24N|WIRELESS_11_5N) ? _TRUE : _FALSE)
typedef struct ieee_param {
@ -216,7 +216,7 @@ typedef struct ieee_param {
} wpa_ie;
struct{
int command;
int reason_code;
int reason_code;
} mlme;
struct {
u8 alg[IEEE_CRYPT_ALG_NAME_LEN];
@ -232,7 +232,7 @@ typedef struct ieee_param {
u16 aid;
u16 capability;
int flags;
u8 tx_supp_rates[16];
u8 tx_supp_rates[16];
struct rtw_ieee80211_ht_cap ht_cap;
} add_sta;
struct {
@ -241,7 +241,7 @@ typedef struct ieee_param {
} bcn_ie;
#endif
} u;
} u;
}ieee_param;
#ifdef CONFIG_AP_MODE
@ -256,7 +256,7 @@ struct sta_data{
u16 capability;
int flags;
u32 sta_set;
u8 tx_supp_rates[16];
u8 tx_supp_rates[16];
u32 tx_supp_rates_len;
struct rtw_ieee80211_ht_cap ht_cap;
u64 rx_pkts;
@ -388,7 +388,7 @@ enum eap_type {
/* management */
#define RTW_IEEE80211_STYPE_ASSOC_REQ 0x0000
#define RTW_IEEE80211_STYPE_ASSOC_RESP 0x0010
#define RTW_IEEE80211_STYPE_ASSOC_RESP 0x0010
#define RTW_IEEE80211_STYPE_REASSOC_REQ 0x0020
#define RTW_IEEE80211_STYPE_REASSOC_RESP 0x0030
#define RTW_IEEE80211_STYPE_PROBE_REQ 0x0040
@ -581,7 +581,7 @@ struct ieee80211_snap_hdr {
#define IEEE80211_24GHZ_BAND (1<<0)
#define IEEE80211_52GHZ_BAND (1<<1)
#define IEEE80211_CCK_RATE_LEN 4
#define IEEE80211_CCK_RATE_LEN 4
#define IEEE80211_NUM_OFDM_RATESLEN 8
@ -589,7 +589,7 @@ struct ieee80211_snap_hdr {
#define IEEE80211_CCK_RATE_2MB 0x04
#define IEEE80211_CCK_RATE_5MB 0x0B
#define IEEE80211_CCK_RATE_11MB 0x16
#define IEEE80211_OFDM_RATE_LEN 8
#define IEEE80211_OFDM_RATE_LEN 8
#define IEEE80211_OFDM_RATE_6MB 0x0C
#define IEEE80211_OFDM_RATE_9MB 0x12
#define IEEE80211_OFDM_RATE_12MB 0x18
@ -925,9 +925,9 @@ struct ieee80211_network {
u8 rates_len;
u8 rates_ex[MAX_RATES_EX_LENGTH];
u8 rates_ex_len;
u8 edca_parmsets[18];
u8 mode;
u8 flags;
u8 time_stamp[8];
@ -946,7 +946,7 @@ struct ieee80211_network {
u8 qbssload[5];
u8 network_type;
int join_res;
unsigned long last_scanned;
unsigned long last_scanned;
};
#endif
/*
@ -960,7 +960,7 @@ enum ieee80211_state {
/* the card is not linked at all */
IEEE80211_NOLINK = 0,
/* IEEE80211_ASSOCIATING* are for BSS client mode
* the driver shall not perform RX filtering unless
* the state is LINKED.
@ -968,31 +968,31 @@ enum ieee80211_state {
* defaults to NOLINK for ALL the other states (including
* LINKED_SCANNING)
*/
/* the association procedure will start (wq scheduling)*/
IEEE80211_ASSOCIATING,
IEEE80211_ASSOCIATING_RETRY,
/* the association procedure is sending AUTH request*/
IEEE80211_ASSOCIATING_AUTHENTICATING,
/* the association procedure has successfully authentcated
* and is sending association request
*/
IEEE80211_ASSOCIATING_AUTHENTICATED,
/* the link is ok. the card associated to a BSS or linked
* to a ibss cell or acting as an AP and creating the bss
*/
IEEE80211_LINKED,
/* same as LINKED, but the driver shall apply RX filter
* rules as we are in NO_LINK mode. As the card is still
* logically linked, but it is doing a syncro site survey
* then it will be back to LINKED state.
*/
IEEE80211_LINKED_SCANNING,
};
#define DEFAULT_MAX_SCAN_AGE (15 * HZ)
@ -1197,7 +1197,7 @@ enum rtw_ieee80211_back_parties {
RTW_IEEE80211_CHAN_NO_HT40PLUS = 1<<4,
RTW_IEEE80211_CHAN_NO_HT40MINUS = 1<<5,
};
#define RTW_IEEE80211_CHAN_NO_HT40 \
(RTW_IEEE80211_CHAN_NO_HT40PLUS | RTW_IEEE80211_CHAN_NO_HT40MINUS)
@ -1214,7 +1214,7 @@ struct rtw_ieee80211_channel {
//u32 orig_flags;
//int orig_mag;
//int orig_mpwr;
};
};
#define CHAN_FMT \
/*"band:%d, "*/ \
@ -1227,7 +1227,7 @@ struct rtw_ieee80211_channel {
/*"beacon_found:%u\n"*/ \
/*"orig_flags:0x%08x\n"*/ \
/*"orig_mag:%d\n"*/ \
/*"orig_mpwr:%d\n"*/
/*"orig_mpwr:%d\n"*/
#define CHAN_ARG(channel) \
/*(channel)->band*/ \
@ -1389,4 +1389,3 @@ int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8* category, u8 *act
const char *action_public_str(u8 action);
#endif /* IEEE80211_H */

587
include/ieee80211_ext.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -16,296 +16,295 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __IEEE80211_EXT_H
#define __IEEE80211_EXT_H
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#define WMM_OUI_TYPE 2
#define WMM_OUI_SUBTYPE_INFORMATION_ELEMENT 0
#define WMM_OUI_SUBTYPE_PARAMETER_ELEMENT 1
#define WMM_OUI_SUBTYPE_TSPEC_ELEMENT 2
#define WMM_VERSION 1
#define WPA_PROTO_WPA BIT(0)
#define WPA_PROTO_RSN BIT(1)
#define WPA_KEY_MGMT_IEEE8021X BIT(0)
#define WPA_KEY_MGMT_PSK BIT(1)
#define WPA_KEY_MGMT_NONE BIT(2)
#define WPA_KEY_MGMT_IEEE8021X_NO_WPA BIT(3)
#define WPA_KEY_MGMT_WPA_NONE BIT(4)
#define WPA_CAPABILITY_PREAUTH BIT(0)
#define WPA_CAPABILITY_MGMT_FRAME_PROTECTION BIT(6)
#define WPA_CAPABILITY_PEERKEY_ENABLED BIT(9)
#define PMKID_LEN 16
struct wpa_ie_hdr {
u8 elem_id;
u8 len;
u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */
u8 version[2]; /* little endian */
}__attribute__ ((packed));
struct rsn_ie_hdr {
u8 elem_id; /* WLAN_EID_RSN */
u8 len;
u8 version[2]; /* little endian */
}__attribute__ ((packed));
struct wme_ac_parameter {
#if defined(CONFIG_LITTLE_ENDIAN)
/* byte 1 */
u8 aifsn:4,
acm:1,
aci:2,
reserved:1;
/* byte 2 */
u8 eCWmin:4,
eCWmax:4;
#elif defined(CONFIG_BIG_ENDIAN)
/* byte 1 */
u8 reserved:1,
aci:2,
acm:1,
aifsn:4;
/* byte 2 */
u8 eCWmax:4,
eCWmin:4;
#else
#error "Please fix <endian.h>"
#endif
/* bytes 3 & 4 */
u16 txopLimit;
} __attribute__ ((packed));
struct wme_parameter_element {
/* required fields for WME version 1 */
u8 oui[3];
u8 oui_type;
u8 oui_subtype;
u8 version;
u8 acInfo;
u8 reserved;
struct wme_ac_parameter ac[4];
} __attribute__ ((packed));
#define WPA_PUT_LE16(a, val) \
do { \
(a)[1] = ((u16) (val)) >> 8; \
(a)[0] = ((u16) (val)) & 0xff; \
} while (0)
#define WPA_PUT_BE32(a, val) \
do { \
(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \
(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \
(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \
(a)[3] = (u8) (((u32) (val)) & 0xff); \
} while (0)
#define WPA_PUT_LE32(a, val) \
do { \
(a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \
(a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \
(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \
(a)[0] = (u8) (((u32) (val)) & 0xff); \
} while (0)
#define RSN_SELECTOR_PUT(a, val) WPA_PUT_BE32((u8 *) (a), (val))
//#define RSN_SELECTOR_PUT(a, val) WPA_PUT_LE32((u8 *) (a), (val))
/* Action category code */
enum ieee80211_category {
WLAN_CATEGORY_SPECTRUM_MGMT = 0,
WLAN_CATEGORY_QOS = 1,
WLAN_CATEGORY_DLS = 2,
WLAN_CATEGORY_BACK = 3,
WLAN_CATEGORY_HT = 7,
WLAN_CATEGORY_WMM = 17,
};
/* SPECTRUM_MGMT action code */
enum ieee80211_spectrum_mgmt_actioncode {
WLAN_ACTION_SPCT_MSR_REQ = 0,
WLAN_ACTION_SPCT_MSR_RPRT = 1,
WLAN_ACTION_SPCT_TPC_REQ = 2,
WLAN_ACTION_SPCT_TPC_RPRT = 3,
WLAN_ACTION_SPCT_CHL_SWITCH = 4,
WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5,
};
/* BACK action code */
enum ieee80211_back_actioncode {
WLAN_ACTION_ADDBA_REQ = 0,
WLAN_ACTION_ADDBA_RESP = 1,
WLAN_ACTION_DELBA = 2,
};
/* HT features action code */
enum ieee80211_ht_actioncode {
WLAN_ACTION_NOTIFY_CH_WIDTH = 0,
WLAN_ACTION_SM_PS = 1,
WLAN_ACTION_PSPM = 2,
WLAN_ACTION_PCO_PHASE = 3,
WLAN_ACTION_MIMO_CSI_MX = 4,
WLAN_ACTION_MIMO_NONCP_BF = 5,
WLAN_ACTION_MIMP_CP_BF = 6,
WLAN_ACTION_ASEL_INDICATES_FB = 7,
WLAN_ACTION_HI_INFO_EXCHG = 8,
};
/* BACK (block-ack) parties */
enum ieee80211_back_parties {
WLAN_BACK_RECIPIENT = 0,
WLAN_BACK_INITIATOR = 1,
WLAN_BACK_TIMER = 2,
};
struct ieee80211_mgmt {
u16 frame_control;
u16 duration;
u8 da[6];
u8 sa[6];
u8 bssid[6];
u16 seq_ctrl;
union {
struct {
u16 auth_alg;
u16 auth_transaction;
u16 status_code;
/* possibly followed by Challenge text */
u8 variable[0];
} __attribute__ ((packed)) auth;
struct {
u16 reason_code;
} __attribute__ ((packed)) deauth;
struct {
u16 capab_info;
u16 listen_interval;
/* followed by SSID and Supported rates */
u8 variable[0];
} __attribute__ ((packed)) assoc_req;
struct {
u16 capab_info;
u16 status_code;
u16 aid;
/* followed by Supported rates */
u8 variable[0];
} __attribute__ ((packed)) assoc_resp, reassoc_resp;
struct {
u16 capab_info;
u16 listen_interval;
u8 current_ap[6];
/* followed by SSID and Supported rates */
u8 variable[0];
} __attribute__ ((packed)) reassoc_req;
struct {
u16 reason_code;
} __attribute__ ((packed)) disassoc;
struct {
__le64 timestamp;
u16 beacon_int;
u16 capab_info;
/* followed by some of SSID, Supported rates,
* FH Params, DS Params, CF Params, IBSS Params, TIM */
u8 variable[0];
} __attribute__ ((packed)) beacon;
struct {
/* only variable items: SSID, Supported rates */
u8 variable[0];
} __attribute__ ((packed)) probe_req;
struct {
__le64 timestamp;
u16 beacon_int;
u16 capab_info;
/* followed by some of SSID, Supported rates,
* FH Params, DS Params, CF Params, IBSS Params */
u8 variable[0];
} __attribute__ ((packed)) probe_resp;
struct {
u8 category;
union {
struct {
u8 action_code;
u8 dialog_token;
u8 status_code;
u8 variable[0];
} __attribute__ ((packed)) wme_action;
#if 0
struct{
u8 action_code;
u8 element_id;
u8 length;
struct ieee80211_channel_sw_ie sw_elem;
} __attribute__ ((packed)) chan_switch;
struct{
u8 action_code;
u8 dialog_token;
u8 element_id;
u8 length;
struct ieee80211_msrment_ie msr_elem;
} __attribute__ ((packed)) measurement;
#endif
struct{
u8 action_code;
u8 dialog_token;
u16 capab;
u16 timeout;
u16 start_seq_num;
} __attribute__ ((packed)) addba_req;
struct{
u8 action_code;
u8 dialog_token;
u16 status;
u16 capab;
u16 timeout;
} __attribute__ ((packed)) addba_resp;
struct{
u8 action_code;
u16 params;
u16 reason_code;
} __attribute__ ((packed)) delba;
struct{
u8 action_code;
/* capab_info for open and confirm,
* reason for close
*/
u16 aux;
/* Followed in plink_confirm by status
* code, AID and supported rates,
* and directly by supported rates in
* plink_open and plink_close
*/
u8 variable[0];
} __attribute__ ((packed)) plink_action;
struct{
u8 action_code;
u8 variable[0];
} __attribute__ ((packed)) mesh_action;
} __attribute__ ((packed)) u;
} __attribute__ ((packed)) action;
} __attribute__ ((packed)) u;
}__attribute__ ((packed));
/* mgmt header + 1 byte category code */
#define IEEE80211_MIN_ACTION_SIZE FIELD_OFFSET(struct ieee80211_mgmt, u.action.u)
#endif
******************************************************************************/
#ifndef __IEEE80211_EXT_H
#define __IEEE80211_EXT_H
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#define WMM_OUI_TYPE 2
#define WMM_OUI_SUBTYPE_INFORMATION_ELEMENT 0
#define WMM_OUI_SUBTYPE_PARAMETER_ELEMENT 1
#define WMM_OUI_SUBTYPE_TSPEC_ELEMENT 2
#define WMM_VERSION 1
#define WPA_PROTO_WPA BIT(0)
#define WPA_PROTO_RSN BIT(1)
#define WPA_KEY_MGMT_IEEE8021X BIT(0)
#define WPA_KEY_MGMT_PSK BIT(1)
#define WPA_KEY_MGMT_NONE BIT(2)
#define WPA_KEY_MGMT_IEEE8021X_NO_WPA BIT(3)
#define WPA_KEY_MGMT_WPA_NONE BIT(4)
#define WPA_CAPABILITY_PREAUTH BIT(0)
#define WPA_CAPABILITY_MGMT_FRAME_PROTECTION BIT(6)
#define WPA_CAPABILITY_PEERKEY_ENABLED BIT(9)
#define PMKID_LEN 16
struct wpa_ie_hdr {
u8 elem_id;
u8 len;
u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */
u8 version[2]; /* little endian */
}__attribute__ ((packed));
struct rsn_ie_hdr {
u8 elem_id; /* WLAN_EID_RSN */
u8 len;
u8 version[2]; /* little endian */
}__attribute__ ((packed));
struct wme_ac_parameter {
#if defined(CONFIG_LITTLE_ENDIAN)
/* byte 1 */
u8 aifsn:4,
acm:1,
aci:2,
reserved:1;
/* byte 2 */
u8 eCWmin:4,
eCWmax:4;
#elif defined(CONFIG_BIG_ENDIAN)
/* byte 1 */
u8 reserved:1,
aci:2,
acm:1,
aifsn:4;
/* byte 2 */
u8 eCWmax:4,
eCWmin:4;
#else
#error "Please fix <endian.h>"
#endif
/* bytes 3 & 4 */
u16 txopLimit;
} __attribute__ ((packed));
struct wme_parameter_element {
/* required fields for WME version 1 */
u8 oui[3];
u8 oui_type;
u8 oui_subtype;
u8 version;
u8 acInfo;
u8 reserved;
struct wme_ac_parameter ac[4];
} __attribute__ ((packed));
#define WPA_PUT_LE16(a, val) \
do { \
(a)[1] = ((u16) (val)) >> 8; \
(a)[0] = ((u16) (val)) & 0xff; \
} while (0)
#define WPA_PUT_BE32(a, val) \
do { \
(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \
(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \
(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \
(a)[3] = (u8) (((u32) (val)) & 0xff); \
} while (0)
#define WPA_PUT_LE32(a, val) \
do { \
(a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \
(a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \
(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \
(a)[0] = (u8) (((u32) (val)) & 0xff); \
} while (0)
#define RSN_SELECTOR_PUT(a, val) WPA_PUT_BE32((u8 *) (a), (val))
//#define RSN_SELECTOR_PUT(a, val) WPA_PUT_LE32((u8 *) (a), (val))
/* Action category code */
enum ieee80211_category {
WLAN_CATEGORY_SPECTRUM_MGMT = 0,
WLAN_CATEGORY_QOS = 1,
WLAN_CATEGORY_DLS = 2,
WLAN_CATEGORY_BACK = 3,
WLAN_CATEGORY_HT = 7,
WLAN_CATEGORY_WMM = 17,
};
/* SPECTRUM_MGMT action code */
enum ieee80211_spectrum_mgmt_actioncode {
WLAN_ACTION_SPCT_MSR_REQ = 0,
WLAN_ACTION_SPCT_MSR_RPRT = 1,
WLAN_ACTION_SPCT_TPC_REQ = 2,
WLAN_ACTION_SPCT_TPC_RPRT = 3,
WLAN_ACTION_SPCT_CHL_SWITCH = 4,
WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5,
};
/* BACK action code */
enum ieee80211_back_actioncode {
WLAN_ACTION_ADDBA_REQ = 0,
WLAN_ACTION_ADDBA_RESP = 1,
WLAN_ACTION_DELBA = 2,
};
/* HT features action code */
enum ieee80211_ht_actioncode {
WLAN_ACTION_NOTIFY_CH_WIDTH = 0,
WLAN_ACTION_SM_PS = 1,
WLAN_ACTION_PSPM = 2,
WLAN_ACTION_PCO_PHASE = 3,
WLAN_ACTION_MIMO_CSI_MX = 4,
WLAN_ACTION_MIMO_NONCP_BF = 5,
WLAN_ACTION_MIMP_CP_BF = 6,
WLAN_ACTION_ASEL_INDICATES_FB = 7,
WLAN_ACTION_HI_INFO_EXCHG = 8,
};
/* BACK (block-ack) parties */
enum ieee80211_back_parties {
WLAN_BACK_RECIPIENT = 0,
WLAN_BACK_INITIATOR = 1,
WLAN_BACK_TIMER = 2,
};
struct ieee80211_mgmt {
u16 frame_control;
u16 duration;
u8 da[6];
u8 sa[6];
u8 bssid[6];
u16 seq_ctrl;
union {
struct {
u16 auth_alg;
u16 auth_transaction;
u16 status_code;
/* possibly followed by Challenge text */
u8 variable[0];
} __attribute__ ((packed)) auth;
struct {
u16 reason_code;
} __attribute__ ((packed)) deauth;
struct {
u16 capab_info;
u16 listen_interval;
/* followed by SSID and Supported rates */
u8 variable[0];
} __attribute__ ((packed)) assoc_req;
struct {
u16 capab_info;
u16 status_code;
u16 aid;
/* followed by Supported rates */
u8 variable[0];
} __attribute__ ((packed)) assoc_resp, reassoc_resp;
struct {
u16 capab_info;
u16 listen_interval;
u8 current_ap[6];
/* followed by SSID and Supported rates */
u8 variable[0];
} __attribute__ ((packed)) reassoc_req;
struct {
u16 reason_code;
} __attribute__ ((packed)) disassoc;
struct {
__le64 timestamp;
u16 beacon_int;
u16 capab_info;
/* followed by some of SSID, Supported rates,
* FH Params, DS Params, CF Params, IBSS Params, TIM */
u8 variable[0];
} __attribute__ ((packed)) beacon;
struct {
/* only variable items: SSID, Supported rates */
u8 variable[0];
} __attribute__ ((packed)) probe_req;
struct {
__le64 timestamp;
u16 beacon_int;
u16 capab_info;
/* followed by some of SSID, Supported rates,
* FH Params, DS Params, CF Params, IBSS Params */
u8 variable[0];
} __attribute__ ((packed)) probe_resp;
struct {
u8 category;
union {
struct {
u8 action_code;
u8 dialog_token;
u8 status_code;
u8 variable[0];
} __attribute__ ((packed)) wme_action;
#if 0
struct{
u8 action_code;
u8 element_id;
u8 length;
struct ieee80211_channel_sw_ie sw_elem;
} __attribute__ ((packed)) chan_switch;
struct{
u8 action_code;
u8 dialog_token;
u8 element_id;
u8 length;
struct ieee80211_msrment_ie msr_elem;
} __attribute__ ((packed)) measurement;
#endif
struct{
u8 action_code;
u8 dialog_token;
u16 capab;
u16 timeout;
u16 start_seq_num;
} __attribute__ ((packed)) addba_req;
struct{
u8 action_code;
u8 dialog_token;
u16 status;
u16 capab;
u16 timeout;
} __attribute__ ((packed)) addba_resp;
struct{
u8 action_code;
u16 params;
u16 reason_code;
} __attribute__ ((packed)) delba;
struct{
u8 action_code;
/* capab_info for open and confirm,
* reason for close
*/
u16 aux;
/* Followed in plink_confirm by status
* code, AID and supported rates,
* and directly by supported rates in
* plink_open and plink_close
*/
u8 variable[0];
} __attribute__ ((packed)) plink_action;
struct{
u8 action_code;
u8 variable[0];
} __attribute__ ((packed)) mesh_action;
} __attribute__ ((packed)) u;
} __attribute__ ((packed)) action;
} __attribute__ ((packed)) u;
}__attribute__ ((packed));
/* mgmt header + 1 byte category code */
#define IEEE80211_MIN_ACTION_SIZE FIELD_OFFSET(struct ieee80211_mgmt, u.action.u)
#endif

19
include/if_ether.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -17,13 +17,13 @@
*
*
******************************************************************************/
#ifndef _LINUX_IF_ETHER_H
#define _LINUX_IF_ETHER_H
/*
* IEEE 802.3 Ethernet magic constants. The frame sizes omit the preamble
* and FCS/CRC (frame check sequence).
* and FCS/CRC (frame check sequence).
*/
#define ETH_ALEN 6 /* Octets in one ethernet addr */
@ -69,18 +69,18 @@
/*
* Non DIX types. Won't clash for 1500 types.
*/
#define ETH_P_802_3 0x0001 /* Dummy type for 802.3 frames */
#define ETH_P_AX25 0x0002 /* Dummy protocol id for AX.25 */
#define ETH_P_ALL 0x0003 /* Every packet (be careful!!!) */
#define ETH_P_802_2 0x0004 /* 802.2 frames */
#define ETH_P_802_2 0x0004 /* 802.2 frames */
#define ETH_P_SNAP 0x0005 /* Internal only */
#define ETH_P_DDCMP 0x0006 /* DEC DDCMP: Internal only */
#define ETH_P_WAN_PPP 0x0007 /* Dummy type for WAN PPP frames*/
#define ETH_P_PPP_MP 0x0008 /* Dummy type for PPP MP frames */
#define ETH_P_LOCALTALK 0x0009 /* Localtalk pseudo type */
#define ETH_P_LOCALTALK 0x0009 /* Localtalk pseudo type */
#define ETH_P_PPPTALK 0x0010 /* Dummy type for Atalk over PPP*/
#define ETH_P_TR_802_2 0x0011 /* 802.2 frames */
#define ETH_P_TR_802_2 0x0011 /* 802.2 frames */
#define ETH_P_MOBITEX 0x0015 /* Mobitex (kaz@cafe.net) */
#define ETH_P_CONTROL 0x0016 /* Card specific control frames */
#define ETH_P_IRDA 0x0017 /* Linux-IrDA */
@ -89,8 +89,8 @@
/*
* This is an Ethernet frame header.
*/
struct ethhdr
struct ethhdr
{
unsigned char h_dest[ETH_ALEN]; /* destination eth addr */
unsigned char h_source[ETH_ALEN]; /* source ether addr */
@ -110,4 +110,3 @@ struct _vlan {
#endif /* _LINUX_IF_ETHER_H */

351
include/ioctl_cfg80211.h
View file

@ -1,176 +1,175 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __IOCTL_CFG80211_H__
#define __IOCTL_CFG80211_H__
#if defined(RTW_USE_CFG80211_STA_EVENT)
#undef CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER
#endif
struct rtw_wdev_invit_info {
u8 state; /* 0: req, 1:rep */
u8 peer_mac[ETH_ALEN];
u8 active;
u8 token;
u8 flags;
u8 status;
u8 req_op_ch;
u8 rsp_op_ch;
};
#define rtw_wdev_invit_info_init(invit_info) \
do { \
(invit_info)->state = 0xff; \
_rtw_memset((invit_info)->peer_mac, 0, ETH_ALEN); \
(invit_info)->active = 0xff; \
(invit_info)->token = 0; \
(invit_info)->flags = 0x00; \
(invit_info)->status = 0xff; \
(invit_info)->req_op_ch = 0; \
(invit_info)->rsp_op_ch = 0; \
} while (0)
struct rtw_wdev_nego_info {
u8 state; /* 0: req, 1:rep, 3:conf */
u8 peer_mac[ETH_ALEN];
u8 active;
u8 token;
u8 status;
u8 req_intent;
u8 req_op_ch;
u8 req_listen_ch;
u8 rsp_intent;
u8 rsp_op_ch;
u8 conf_op_ch;
};
#define rtw_wdev_nego_info_init(nego_info) \
do { \
(nego_info)->state = 0xff; \
_rtw_memset((nego_info)->peer_mac, 0, ETH_ALEN); \
(nego_info)->active = 0xff; \
(nego_info)->token = 0; \
(nego_info)->status = 0xff; \
(nego_info)->req_intent = 0xff; \
(nego_info)->req_op_ch = 0; \
(nego_info)->req_listen_ch = 0; \
(nego_info)->rsp_intent = 0xff; \
(nego_info)->rsp_op_ch = 0; \
(nego_info)->conf_op_ch = 0; \
} while (0)
struct rtw_wdev_priv
{
struct wireless_dev *rtw_wdev;
struct adapter *padapter;
struct cfg80211_scan_request *scan_request;
_lock scan_req_lock;
struct net_device *pmon_ndev;//for monitor interface
char ifname_mon[IFNAMSIZ + 1]; //interface name for monitor interface
u8 p2p_enabled;
u8 provdisc_req_issued;
struct rtw_wdev_invit_info invit_info;
struct rtw_wdev_nego_info nego_info;
u8 bandroid_scan;
bool block;
bool power_mgmt;
#ifdef CONFIG_CONCURRENT_MODE
ATOMIC_T ro_ch_to;
ATOMIC_T switch_ch_to;
#endif
};
#define wdev_to_priv(w) ((struct rtw_wdev_priv *)(wdev_priv(w)))
#define wiphy_to_adapter(x) (struct adapter *)(((struct rtw_wdev_priv*)wiphy_priv(x))->padapter)
#define wiphy_to_wdev(x) (struct wireless_dev *)(((struct rtw_wdev_priv*)wiphy_priv(x))->rtw_wdev)
int rtw_wdev_alloc(struct adapter *padapter, struct device *dev);
void rtw_wdev_free(struct wireless_dev *wdev);
void rtw_wdev_unregister(struct wireless_dev *wdev);
void rtw_cfg80211_init_wiphy(struct adapter *padapter);
void rtw_cfg80211_surveydone_event_callback(struct adapter *padapter);
struct cfg80211_bss *rtw_cfg80211_inform_bss(struct adapter *padapter, struct wlan_network *pnetwork);
int rtw_cfg80211_check_bss(struct adapter *padapter);
void rtw_cfg80211_ibss_indicate_connect(struct adapter *padapter);
void rtw_cfg80211_indicate_connect(struct adapter *padapter);
void rtw_cfg80211_indicate_disconnect(struct adapter *padapter);
void rtw_cfg80211_indicate_scan_done(struct rtw_wdev_priv *pwdev_priv, bool aborted);
#ifdef CONFIG_AP_MODE
void rtw_cfg80211_indicate_sta_assoc(struct adapter *padapter, u8 *pmgmt_frame, uint frame_len);
void rtw_cfg80211_indicate_sta_disassoc(struct adapter *padapter, unsigned char *da, unsigned short reason);
#endif //CONFIG_AP_MODE
void rtw_cfg80211_issue_p2p_provision_request(struct adapter *padapter, const u8 *buf, size_t len);
void rtw_cfg80211_rx_p2p_action_public(struct adapter *padapter, u8 *pmgmt_frame, uint frame_len);
void rtw_cfg80211_rx_action_p2p(struct adapter *padapter, u8 *pmgmt_frame, uint frame_len);
void rtw_cfg80211_rx_action(struct adapter *adapter, u8 *frame, uint frame_len, const char*msg);
int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, int type);
bool rtw_cfg80211_pwr_mgmt(struct adapter *adapter);
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) && !defined(COMPAT_KERNEL_RELEASE)
#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->pnetdev, freq, buf, len, gfp)
#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0))
#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->pnetdev, freq, sig_dbm, buf, len, gfp)
#else
#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->rtw_wdev, freq, sig_dbm, buf, len, gfp)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) && !defined(COMPAT_KERNEL_RELEASE)
#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) cfg80211_send_rx_assoc((adapter)->pnetdev, buf, len)
#else
#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) cfg80211_send_rx_assoc((adapter)->pnetdev, bss, buf, len)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0))
#define rtw_cfg80211_mgmt_tx_status(adapter, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status((adapter)->pnetdev, cookie, buf, len, ack, gfp)
#else
#define rtw_cfg80211_mgmt_tx_status(adapter, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status((adapter)->rtw_wdev, cookie, buf, len, ack, gfp)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0))
#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->pnetdev, cookie, chan, channel_type, duration, gfp)
#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->pnetdev, cookie, chan, chan_type, gfp)
#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0))
#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->rtw_wdev, cookie, chan, channel_type, duration, gfp)
#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->rtw_wdev, cookie, chan, chan_type, gfp)
#else
#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->rtw_wdev, cookie, chan, duration, gfp)
#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->rtw_wdev, cookie, chan, gfp)
#endif
#endif //__IOCTL_CFG80211_H__
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __IOCTL_CFG80211_H__
#define __IOCTL_CFG80211_H__
#if defined(RTW_USE_CFG80211_STA_EVENT)
#undef CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER
#endif
struct rtw_wdev_invit_info {
u8 state; /* 0: req, 1:rep */
u8 peer_mac[ETH_ALEN];
u8 active;
u8 token;
u8 flags;
u8 status;
u8 req_op_ch;
u8 rsp_op_ch;
};
#define rtw_wdev_invit_info_init(invit_info) \
do { \
(invit_info)->state = 0xff; \
_rtw_memset((invit_info)->peer_mac, 0, ETH_ALEN); \
(invit_info)->active = 0xff; \
(invit_info)->token = 0; \
(invit_info)->flags = 0x00; \
(invit_info)->status = 0xff; \
(invit_info)->req_op_ch = 0; \
(invit_info)->rsp_op_ch = 0; \
} while (0)
struct rtw_wdev_nego_info {
u8 state; /* 0: req, 1:rep, 3:conf */
u8 peer_mac[ETH_ALEN];
u8 active;
u8 token;
u8 status;
u8 req_intent;
u8 req_op_ch;
u8 req_listen_ch;
u8 rsp_intent;
u8 rsp_op_ch;
u8 conf_op_ch;
};
#define rtw_wdev_nego_info_init(nego_info) \
do { \
(nego_info)->state = 0xff; \
_rtw_memset((nego_info)->peer_mac, 0, ETH_ALEN); \
(nego_info)->active = 0xff; \
(nego_info)->token = 0; \
(nego_info)->status = 0xff; \
(nego_info)->req_intent = 0xff; \
(nego_info)->req_op_ch = 0; \
(nego_info)->req_listen_ch = 0; \
(nego_info)->rsp_intent = 0xff; \
(nego_info)->rsp_op_ch = 0; \
(nego_info)->conf_op_ch = 0; \
} while (0)
struct rtw_wdev_priv
{
struct wireless_dev *rtw_wdev;
struct adapter *padapter;
struct cfg80211_scan_request *scan_request;
_lock scan_req_lock;
struct net_device *pmon_ndev;//for monitor interface
char ifname_mon[IFNAMSIZ + 1]; //interface name for monitor interface
u8 p2p_enabled;
u8 provdisc_req_issued;
struct rtw_wdev_invit_info invit_info;
struct rtw_wdev_nego_info nego_info;
u8 bandroid_scan;
bool block;
bool power_mgmt;
#ifdef CONFIG_CONCURRENT_MODE
ATOMIC_T ro_ch_to;
ATOMIC_T switch_ch_to;
#endif
};
#define wdev_to_priv(w) ((struct rtw_wdev_priv *)(wdev_priv(w)))
#define wiphy_to_adapter(x) (struct adapter *)(((struct rtw_wdev_priv*)wiphy_priv(x))->padapter)
#define wiphy_to_wdev(x) (struct wireless_dev *)(((struct rtw_wdev_priv*)wiphy_priv(x))->rtw_wdev)
int rtw_wdev_alloc(struct adapter *padapter, struct device *dev);
void rtw_wdev_free(struct wireless_dev *wdev);
void rtw_wdev_unregister(struct wireless_dev *wdev);
void rtw_cfg80211_init_wiphy(struct adapter *padapter);
void rtw_cfg80211_surveydone_event_callback(struct adapter *padapter);
struct cfg80211_bss *rtw_cfg80211_inform_bss(struct adapter *padapter, struct wlan_network *pnetwork);
int rtw_cfg80211_check_bss(struct adapter *padapter);
void rtw_cfg80211_ibss_indicate_connect(struct adapter *padapter);
void rtw_cfg80211_indicate_connect(struct adapter *padapter);
void rtw_cfg80211_indicate_disconnect(struct adapter *padapter);
void rtw_cfg80211_indicate_scan_done(struct rtw_wdev_priv *pwdev_priv, bool aborted);
#ifdef CONFIG_AP_MODE
void rtw_cfg80211_indicate_sta_assoc(struct adapter *padapter, u8 *pmgmt_frame, uint frame_len);
void rtw_cfg80211_indicate_sta_disassoc(struct adapter *padapter, unsigned char *da, unsigned short reason);
#endif //CONFIG_AP_MODE
void rtw_cfg80211_issue_p2p_provision_request(struct adapter *padapter, const u8 *buf, size_t len);
void rtw_cfg80211_rx_p2p_action_public(struct adapter *padapter, u8 *pmgmt_frame, uint frame_len);
void rtw_cfg80211_rx_action_p2p(struct adapter *padapter, u8 *pmgmt_frame, uint frame_len);
void rtw_cfg80211_rx_action(struct adapter *adapter, u8 *frame, uint frame_len, const char*msg);
int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, int type);
bool rtw_cfg80211_pwr_mgmt(struct adapter *adapter);
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) && !defined(COMPAT_KERNEL_RELEASE)
#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->pnetdev, freq, buf, len, gfp)
#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0))
#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->pnetdev, freq, sig_dbm, buf, len, gfp)
#else
#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->rtw_wdev, freq, sig_dbm, buf, len, gfp)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) && !defined(COMPAT_KERNEL_RELEASE)
#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) cfg80211_send_rx_assoc((adapter)->pnetdev, buf, len)
#else
#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) cfg80211_send_rx_assoc((adapter)->pnetdev, bss, buf, len)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0))
#define rtw_cfg80211_mgmt_tx_status(adapter, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status((adapter)->pnetdev, cookie, buf, len, ack, gfp)
#else
#define rtw_cfg80211_mgmt_tx_status(adapter, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status((adapter)->rtw_wdev, cookie, buf, len, ack, gfp)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0))
#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->pnetdev, cookie, chan, channel_type, duration, gfp)
#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->pnetdev, cookie, chan, chan_type, gfp)
#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0))
#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->rtw_wdev, cookie, chan, channel_type, duration, gfp)
#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->rtw_wdev, cookie, chan, chan_type, gfp)
#else
#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->rtw_wdev, cookie, chan, duration, gfp)
#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->rtw_wdev, cookie, chan, gfp)
#endif
#endif //__IOCTL_CFG80211_H__

7
include/ip.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -101,7 +101,7 @@ struct ip_options {
is_data:1, /* Options in __data, rather than skb */
is_strictroute:1, /* Strict source route */
srr_is_hit:1, /* Packet destination addr was our one */
is_changed:1, /* IP checksum more not valid */
is_changed:1, /* IP checksum more not valid */
rr_needaddr:1, /* Need to record addr of outgoing dev */
ts_needtime:1, /* Need to record timestamp */
ts_needaddr:1; /* Need to record addr of outgoing dev */
@ -119,7 +119,7 @@ struct iphdr {
version:4;
#elif defined (__BIG_ENDIAN_BITFIELD)
__u8 version:4,
ihl:4;
ihl:4;
#else
#error "Please fix <asm/byteorder.h>"
#endif
@ -136,4 +136,3 @@ struct iphdr {
};
#endif /* _LINUX_IP_H */

3
include/mlme_osdep.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -37,4 +37,3 @@ extern void rtw_report_sec_ie(struct adapter *adapter,u8 authmode,u8 *sec_ie);
void rtw_reset_securitypriv( struct adapter *adapter );
#endif //_MLME_OSDEP_H_

35
include/mp_custom_oid.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -38,7 +38,7 @@
#define OID_RT_PRO_RESET_DUT 0xFF818000
#define OID_RT_PRO_SET_DATA_RATE 0xFF818001
#define OID_RT_PRO_START_TEST 0xFF818002
#define OID_RT_PRO_STOP_TEST 0xFF818003
#define OID_RT_PRO_STOP_TEST 0xFF818003
#define OID_RT_PRO_SET_PREAMBLE 0xFF818004
#define OID_RT_PRO_SET_SCRAMBLER 0xFF818005
#define OID_RT_PRO_SET_FILTER_BB 0xFF818006
@ -71,7 +71,7 @@
#define OID_RT_PRO_READ_EEPROM 0xFF818022
#define OID_RT_PRO_RESET_TX_PACKET_SENT 0xFF818023
#define OID_RT_PRO_QUERY_TX_PACKET_SENT 0xFF818024
#define OID_RT_PRO_RESET_RX_PACKET_RECEIVED 0xFF818025
#define OID_RT_PRO_RESET_RX_PACKET_RECEIVED 0xFF818025
#define OID_RT_PRO_QUERY_RX_PACKET_RECEIVED 0xFF818026
#define OID_RT_PRO_QUERY_RX_PACKET_CRC32_ERROR 0xFF818027
#define OID_RT_PRO_QUERY_CURRENT_ADDRESS 0xFF818028
@ -84,7 +84,7 @@
#define OID_RT_PRO_SET_MODULATION 0xFF81802F
//
//Sean
//Sean
#define OID_RT_DRIVER_OPTION 0xFF818080
#define OID_RT_RF_OFF 0xFF818081
#define OID_RT_AUTH_STATUS 0xFF818082
@ -114,15 +114,15 @@
#define OID_RT_WIRELESS_MODE_STARTING_ADHOC 0xFF818503
//
#define OID_RT_GET_CONNECT_STATE 0xFF030001
#define OID_RT_RESCAN 0xFF030002
#define OID_RT_GET_CONNECT_STATE 0xFF030001
#define OID_RT_RESCAN 0xFF030002
#define OID_RT_SET_KEY_LENGTH 0xFF030003
#define OID_RT_SET_DEFAULT_KEY_ID 0xFF030004
#define OID_RT_SET_CHANNEL 0xFF010182
#define OID_RT_SET_SNIFFER_MODE 0xFF010183
#define OID_RT_GET_SIGNAL_QUALITY 0xFF010184
#define OID_RT_GET_SMALL_PACKET_CRC 0xFF010185
#define OID_RT_SET_SNIFFER_MODE 0xFF010183
#define OID_RT_GET_SIGNAL_QUALITY 0xFF010184
#define OID_RT_GET_SMALL_PACKET_CRC 0xFF010185
#define OID_RT_GET_MIDDLE_PACKET_CRC 0xFF010186
#define OID_RT_GET_LARGE_PACKET_CRC 0xFF010187
#define OID_RT_GET_TX_RETRY 0xFF010188
@ -239,8 +239,8 @@
#define OID_RT_PRO_READ_REGISTER 0xFF871101 //Q
#define OID_RT_PRO_WRITE_REGISTER 0xFF871102 //S
#define OID_RT_PRO_BURST_READ_REGISTER 0xFF871103 //Q
#define OID_RT_PRO_BURST_WRITE_REGISTER 0xFF871104 //S
#define OID_RT_PRO_BURST_READ_REGISTER 0xFF871103 //Q
#define OID_RT_PRO_BURST_WRITE_REGISTER 0xFF871104 //S
#define OID_RT_PRO_WRITE_TXCMD 0xFF871105 //S
@ -283,9 +283,9 @@
#define OID_RT_PRO_READ_TSSI 0xFF871123//S
#define OID_RT_PRO_SET_POWER_TRACKING 0xFF871124//S
#define OID_RT_PRO_QRY_PWRSTATE 0xFF871150 //Q
#define OID_RT_PRO_SET_PWRSTATE 0xFF871151 //S
#define OID_RT_PRO_SET_PWRSTATE 0xFF871151 //S
//Method 2 , using workitem
#define OID_RT_SET_READ_REG 0xFF871181 //S
@ -299,7 +299,7 @@
//For SDIO INTERFACE only
#define OID_RT_PRO_SYNCPAGERW_SRAM 0xFF8711A0 //Q, S
#define OID_RT_PRO_871X_DRV_EXT 0xFF8711A1
#define OID_RT_PRO_871X_DRV_EXT 0xFF8711A1
//For USB INTERFACE only
#define OID_RT_PRO_USB_VENDOR_REQ 0xFF8711B0 //Q, S
@ -314,8 +314,8 @@
#define OID_RT_PRO_ENCRYPTION_CTRL 0xFF871200 //Q, S
#define OID_RT_PRO_ADD_STA_INFO 0xFF871201 //S
#define OID_RT_PRO_DELE_STA_INFO 0xFF871202 //S
#define OID_RT_PRO_QUERY_DR_VARIABLE 0xFF871203 //Q
#define OID_RT_PRO_DELE_STA_INFO 0xFF871202 //S
#define OID_RT_PRO_QUERY_DR_VARIABLE 0xFF871203 //Q
#define OID_RT_PRO_RX_PACKET_TYPE 0xFF871204 //Q, S
@ -327,7 +327,7 @@
#define OID_RT_SET_BANDWIDTH 0xFF871209 //S
#define OID_RT_SET_CRYSTAL_CAP 0xFF87120A //S
#define OID_RT_SET_RX_PACKET_TYPE 0xFF87120B //S
#define OID_RT_SET_RX_PACKET_TYPE 0xFF87120B //S
#define OID_RT_GET_EFUSE_MAX_SIZE 0xFF87120C //Q
@ -351,4 +351,3 @@
#define OID_RT_PRO_EFUSE_MAP 0xFF871217 //Q, S
#endif //#ifndef __CUSTOM_OID_H

5
include/nic_spec.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -16,7 +16,7 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
******************************************************************************/
#ifndef __NIC_SPEC_H__
@ -44,4 +44,3 @@
#endif // __RTL8711_SPEC_H__

6
include/odm.h
View file

@ -452,7 +452,7 @@ enum odm_ability_def {
ODM_RF_CALIBRATION = BIT26,
};
/* ODM_CMNINFO_INTERFACE */
/* ODM_CMNINFO_INTERFACE */
enum odm_interface_def {
ODM_ITRF_PCIE = 0x1,
ODM_ITRF_USB = 0x2,
@ -578,7 +578,7 @@ enum odm_security {
ODM_SEC_RESERVE = 3,
ODM_SEC_AESCCMP = 4,
ODM_SEC_WEP104 = 5,
ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */
ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */
ODM_SEC_SMS4 = 7,
};
@ -758,7 +758,7 @@ enum ant_div_type {
/* Copy from SD4 defined structure. We use to support PHY DM integration. */
struct odm_dm_struct {
/* Add for different team use temporarily */
/* Add for different team use temporarily */
struct adapter *Adapter; /* For CE/NIC team */
struct rtl8192cd_priv *priv; /* For AP/ADSL team */
/* WHen you use above pointers, they must be initialized. */

307
include/osdep_ce_service.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -16,156 +16,155 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __OSDEP_CE_SERVICE_H_
#define __OSDEP_CE_SERVICE_H_
#include <ndis.h>
#include <ntddndis.h>
#ifdef CONFIG_SDIO_HCI
#include "SDCardDDK.h"
#endif
#ifdef CONFIG_USB_HCI
#include <usbdi.h>
#endif
typedef HANDLE _sema;
typedef LIST_ENTRY _list;
typedef NDIS_STATUS _OS_STATUS;
typedef NDIS_SPIN_LOCK _lock;
typedef HANDLE _rwlock; //Mutex
typedef u32 _irqL;
typedef NDIS_HANDLE _nic_hdl;
typedef NDIS_MINIPORT_TIMER _timer;
struct __queue {
LIST_ENTRY queue;
_lock lock;
};
typedef NDIS_PACKET _pkt;
typedef NDIS_BUFFER _buffer;
typedef struct __queue _queue;
typedef HANDLE _thread_hdl_;
typedef DWORD thread_return;
typedef void* thread_context;
typedef NDIS_WORK_ITEM _workitem;
#define thread_exit() ExitThread(STATUS_SUCCESS); return 0;
#define SEMA_UPBND (0x7FFFFFFF) //8192
__inline static _list *get_prev(_list *list)
{
return list->Blink;
}
__inline static _list *get_next(_list *list)
{
return list->Flink;
}
__inline static _list *get_list_head(_queue *queue)
{
return (&(queue->queue));
}
#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
{
NdisAcquireSpinLock(plock);
}
__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
{
NdisReleaseSpinLock(plock);
}
__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprAcquireSpinLock(plock);
}
__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprReleaseSpinLock(plock);
}
__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
{
WaitForSingleObject(*prwlock, INFINITE );
}
__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
{
ReleaseMutex(*prwlock);
}
__inline static void rtw_list_delete(_list *plist)
{
RemoveEntryList(plist);
InitializeListHead(plist);
}
__inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,PVOID cntx)
{
NdisMInitializeTimer(ptimer, nic_hdl, pfunc, cntx);
}
__inline static void _set_timer(_timer *ptimer,u32 delay_time)
{
NdisMSetTimer(ptimer,delay_time);
}
__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled)
{
NdisMCancelTimer(ptimer,bcancelled);
}
__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
{
NdisInitializeWorkItem(pwork, pfunc, cntx);
}
__inline static void _set_workitem(_workitem *pwork)
{
NdisScheduleWorkItem(pwork);
}
#define ATOMIC_INIT(i) { (i) }
//
// Global Mutex: can only be used at PASSIVE level.
//
#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
{ \
while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
NdisMSleep(10000); \
} \
}
#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
}
#endif
******************************************************************************/
#ifndef __OSDEP_CE_SERVICE_H_
#define __OSDEP_CE_SERVICE_H_
#include <ndis.h>
#include <ntddndis.h>
#ifdef CONFIG_SDIO_HCI
#include "SDCardDDK.h"
#endif
#ifdef CONFIG_USB_HCI
#include <usbdi.h>
#endif
typedef HANDLE _sema;
typedef LIST_ENTRY _list;
typedef NDIS_STATUS _OS_STATUS;
typedef NDIS_SPIN_LOCK _lock;
typedef HANDLE _rwlock; //Mutex
typedef u32 _irqL;
typedef NDIS_HANDLE _nic_hdl;
typedef NDIS_MINIPORT_TIMER _timer;
struct __queue {
LIST_ENTRY queue;
_lock lock;
};
typedef NDIS_PACKET _pkt;
typedef NDIS_BUFFER _buffer;
typedef struct __queue _queue;
typedef HANDLE _thread_hdl_;
typedef DWORD thread_return;
typedef void* thread_context;
typedef NDIS_WORK_ITEM _workitem;
#define thread_exit() ExitThread(STATUS_SUCCESS); return 0;
#define SEMA_UPBND (0x7FFFFFFF) //8192
__inline static _list *get_prev(_list *list)
{
return list->Blink;
}
__inline static _list *get_next(_list *list)
{
return list->Flink;
}
__inline static _list *get_list_head(_queue *queue)
{
return (&(queue->queue));
}
#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
{
NdisAcquireSpinLock(plock);
}
__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
{
NdisReleaseSpinLock(plock);
}
__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprAcquireSpinLock(plock);
}
__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
{
NdisDprReleaseSpinLock(plock);
}
__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
{
WaitForSingleObject(*prwlock, INFINITE );
}
__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
{
ReleaseMutex(*prwlock);
}
__inline static void rtw_list_delete(_list *plist)
{
RemoveEntryList(plist);
InitializeListHead(plist);
}
__inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,PVOID cntx)
{
NdisMInitializeTimer(ptimer, nic_hdl, pfunc, cntx);
}
__inline static void _set_timer(_timer *ptimer,u32 delay_time)
{
NdisMSetTimer(ptimer,delay_time);
}
__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled)
{
NdisMCancelTimer(ptimer,bcancelled);
}
__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
{
NdisInitializeWorkItem(pwork, pfunc, cntx);
}
__inline static void _set_workitem(_workitem *pwork)
{
NdisScheduleWorkItem(pwork);
}
#define ATOMIC_INIT(i) { (i) }
//
// Global Mutex: can only be used at PASSIVE level.
//
#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
{ \
while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
NdisMSleep(10000); \
} \
}
#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
{ \
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
}
#endif

21
include/osdep_intf.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -26,9 +26,9 @@
#include <drv_types.h>
struct intf_priv {
u8 *intf_dev;
u32 max_iosz; //USB2.0: 128, USB1.1: 64, SDIO:64
u32 max_iosz; //USB2.0: 128, USB1.1: 64, SDIO:64
u32 max_xmitsz; //USB2.0: unlimited, SDIO:512
u32 max_recvsz; //USB2.0: unlimited, SDIO:512
@ -36,9 +36,9 @@ struct intf_priv {
volatile u8 *allocated_io_rwmem;
u32 io_wsz; //unit: 4bytes
u32 io_rsz;//unit: 4bytes
u8 intf_status;
void (*_bus_io)(u8 *priv);
u8 intf_status;
void (*_bus_io)(u8 *priv);
/*
Under Sync. IRP (SDIO/USB)
@ -50,10 +50,10 @@ The protection mechanism is through the pending queue.
_mutex ioctl_mutex;
#ifdef CONFIG_USB_HCI
#ifdef CONFIG_USB_HCI
// when in USB, IO is through interrupt in/out endpoints
struct usb_device *udev;
struct usb_device *udev;
PURB piorw_urb;
u8 io_irp_cnt;
u8 bio_irp_pending;
@ -62,7 +62,7 @@ The protection mechanism is through the pending queue.
u8 bio_irp_timeout;
u8 bio_timer_cancel;
#endif
};
};
#ifdef CONFIG_R871X_TEST
int rtw_start_pseudo_adhoc(struct adapter *padapter);
@ -126,4 +126,3 @@ int rtw_gw_addr_query(struct adapter *padapter);
#endif
#endif //_OSDEP_INTF_H_

66
include/osdep_service.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -34,7 +34,7 @@
#undef _FALSE
#define _FALSE 0
#include <linux/version.h>
#include <linux/spinlock.h>
@ -77,10 +77,10 @@
#include <net/flow.h>
#include <net/arp.h>
#ifdef CONFIG_IOCTL_CFG80211
// #include <linux/ieee80211.h>
#ifdef CONFIG_IOCTL_CFG80211
// #include <linux/ieee80211.h>
#include <net/ieee80211_radiotap.h>
#include <net/cfg80211.h>
#include <net/cfg80211.h>
#endif //CONFIG_IOCTL_CFG80211
#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
@ -103,7 +103,7 @@
#ifdef CONFIG_TX_MCAST2UNI
extern int rtw_mc2u_disable;
#endif // CONFIG_TX_MCAST2UNI
#endif // CONFIG_TX_MCAST2UNI
extern char* rtw_initmac;
@ -139,30 +139,30 @@ extern int pm_netdev_open(struct net_device *pnetdev,u8 bnormal);
#endif
#endif
typedef struct semaphore _sema;
typedef struct semaphore _sema;
typedef spinlock_t _lock;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
typedef struct mutex _mutex;
typedef struct mutex _mutex;
#else
typedef struct semaphore _mutex;
#endif
typedef struct timer_list _timer;
struct __queue {
struct list_head queue;
struct list_head queue;
_lock lock;
};
typedef struct sk_buff _pkt;
typedef unsigned char _buffer;
typedef struct __queue _queue;
typedef struct list_head _list;
typedef int _OS_STATUS;
//typedef u32 _irqL;
typedef unsigned long _irqL;
typedef struct net_device * _nic_hdl;
typedef void* _thread_hdl_;
typedef int thread_return;
typedef void* thread_context;
@ -203,18 +203,18 @@ static inline unsigned char *skb_end_pointer(const struct sk_buff *skb)
__inline static _list *get_next(_list *list)
{
return list->next;
}
}
__inline static _list *get_list_head(_queue *queue)
{
return (&(queue->queue));
}
#define LIST_CONTAINOR(ptr, type, member) \
((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
#define LIST_CONTAINOR(ptr, type, member) \
((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
{
spin_lock_irqsave(plock, *pirqL);
@ -274,20 +274,20 @@ __inline static void rtw_list_delete(_list *plist)
__inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,void* cntx)
{
//setup_timer(ptimer, pfunc,(u32)cntx);
//setup_timer(ptimer, pfunc,(u32)cntx);
ptimer->function = pfunc;
ptimer->data = (unsigned long)cntx;
init_timer(ptimer);
}
__inline static void _set_timer(_timer *ptimer,u32 delay_time)
{
mod_timer(ptimer , (jiffies+(delay_time*HZ/1000)));
{
mod_timer(ptimer , (jiffies+(delay_time*HZ/1000)));
}
__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled)
{
del_timer_sync(ptimer);
del_timer_sync(ptimer);
*bcancelled= _TRUE;//TRUE ==1; FALSE==0
}
@ -617,7 +617,7 @@ extern void rtw_sleep_schedulable(int ms);
extern void rtw_msleep_os(int ms);
extern void rtw_usleep_os(int us);
extern u32 rtw_atoi(u8* s);
extern u32 rtw_atoi(u8* s);
#ifdef DBG_DELAY_OS
#define rtw_mdelay_os(ms) _rtw_mdelay_os((ms), __FUNCTION__, __LINE__)
@ -645,9 +645,9 @@ static __inline void thread_enter(char *name)
allow_signal(SIGTERM);
}
__inline static void flush_signals_thread(void)
__inline static void flush_signals_thread(void)
{
if (signal_pending (current))
if (signal_pending (current))
{
flush_signals(current);
}
@ -674,7 +674,7 @@ __inline static u32 _RND4(u32 sz)
u32 val;
val = ((sz >> 2) + ((sz & 3) ? 1: 0)) << 2;
return val;
}
@ -685,7 +685,7 @@ __inline static u32 _RND8(u32 sz)
u32 val;
val = ((sz >> 3) + ((sz & 7) ? 1: 0)) << 3;
return val;
}
@ -696,7 +696,7 @@ __inline static u32 _RND128(u32 sz)
u32 val;
val = ((sz >> 7) + ((sz & 127) ? 1: 0)) << 7;
return val;
}
@ -707,7 +707,7 @@ __inline static u32 _RND256(u32 sz)
u32 val;
val = ((sz >> 8) + ((sz & 255) ? 1: 0)) << 8;
return val;
}
@ -718,7 +718,7 @@ __inline static u32 _RND512(u32 sz)
u32 val;
val = ((sz >> 9) + ((sz & 511) ? 1: 0)) << 9;
return val;
}
@ -829,7 +829,7 @@ extern u64 rtw_division64(u64 x, u64 y);
} while (0)
#define RTW_GET_BE24(a) ((((u32) (a)[0]) << 16) | (((u32) (a)[1]) << 8) | \
((u32) (a)[2]))
((u32) (a)[2]))
#define RTW_PUT_BE24(a, val) \
do { \
(a)[0] = (u8) ((((u32) (val)) >> 16) & 0xff); \
@ -838,7 +838,7 @@ extern u64 rtw_division64(u64 x, u64 y);
} while (0)
#define RTW_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \
(((u32) (a)[2]) << 8) | ((u32) (a)[3]))
(((u32) (a)[2]) << 8) | ((u32) (a)[3]))
#define RTW_PUT_BE32(a, val) \
do { \
(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \
@ -848,7 +848,7 @@ extern u64 rtw_division64(u64 x, u64 y);
} while (0)
#define RTW_GET_LE32(a) ((((u32) (a)[3]) << 24) | (((u32) (a)[2]) << 16) | \
(((u32) (a)[1]) << 8) | ((u32) (a)[0]))
(((u32) (a)[1]) << 8) | ((u32) (a)[0]))
#define RTW_PUT_LE32(a, val) \
do { \
(a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \
@ -860,7 +860,7 @@ extern u64 rtw_division64(u64 x, u64 y);
#define RTW_GET_BE64(a) ((((u64) (a)[0]) << 56) | (((u64) (a)[1]) << 48) | \
(((u64) (a)[2]) << 40) | (((u64) (a)[3]) << 32) | \
(((u64) (a)[4]) << 24) | (((u64) (a)[5]) << 16) | \
(((u64) (a)[6]) << 8) | ((u64) (a)[7]))
(((u64) (a)[6]) << 8) | ((u64) (a)[7]))
#define RTW_PUT_BE64(a, val) \
do { \
(a)[0] = (u8) (((u64) (val)) >> 56); \
@ -896,5 +896,3 @@ struct rtw_cbuf *rtw_cbuf_alloc(u32 size);
void rtw_cbuf_free(struct rtw_cbuf *cbuf);
#endif

51
include/pci_hal.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -31,32 +31,32 @@
#define PCI_MAX_DEVICES 32
#define PCI_MAX_FUNCTION 8
#define PCI_CONF_ADDRESS 0x0CF8 // PCI Configuration Space Address
#define PCI_CONF_DATA 0x0CFC // PCI Configuration Space Data
#define PCI_CONF_ADDRESS 0x0CF8 // PCI Configuration Space Address
#define PCI_CONF_DATA 0x0CFC // PCI Configuration Space Data
#define PCI_CLASS_BRIDGE_DEV 0x06
#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04
#define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10
#define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10
#define U1DONTCARE 0xFF
#define U2DONTCARE 0xFFFF
#define U4DONTCARE 0xFFFFFFFF
#define U1DONTCARE 0xFF
#define U2DONTCARE 0xFFFF
#define U4DONTCARE 0xFFFFFFFF
#define PCI_VENDER_ID_REALTEK 0x10ec
#define HAL_HW_PCI_8180_DEVICE_ID 0x8180
#define HAL_HW_PCI_8185_DEVICE_ID 0x8185 //8185 or 8185b
#define HAL_HW_PCI_8188_DEVICE_ID 0x8188 //8185b
#define HAL_HW_PCI_8198_DEVICE_ID 0x8198 //8185b
#define HAL_HW_PCI_8190_DEVICE_ID 0x8190 //8190
#define HAL_HW_PCI_8180_DEVICE_ID 0x8180
#define HAL_HW_PCI_8185_DEVICE_ID 0x8185 //8185 or 8185b
#define HAL_HW_PCI_8188_DEVICE_ID 0x8188 //8185b
#define HAL_HW_PCI_8198_DEVICE_ID 0x8198 //8185b
#define HAL_HW_PCI_8190_DEVICE_ID 0x8190 //8190
#define HAL_HW_PCI_8723E_DEVICE_ID 0x8723 //8723E
#define HAL_HW_PCI_8192_DEVICE_ID 0x8192 //8192 PCI-E
#define HAL_HW_PCI_8192_DEVICE_ID 0x8192 //8192 PCI-E
#define HAL_HW_PCI_8192SE_DEVICE_ID 0x8192 //8192 SE
#define HAL_HW_PCI_8174_DEVICE_ID 0x8174 //8192 SE
#define HAL_HW_PCI_8173_DEVICE_ID 0x8173 //8191 SE Crab
#define HAL_HW_PCI_8172_DEVICE_ID 0x8172 //8191 SE RE
#define HAL_HW_PCI_8171_DEVICE_ID 0x8171 //8191 SE Unicron
#define HAL_HW_PCI_8174_DEVICE_ID 0x8174 //8192 SE
#define HAL_HW_PCI_8173_DEVICE_ID 0x8173 //8191 SE Crab
#define HAL_HW_PCI_8172_DEVICE_ID 0x8172 //8191 SE RE
#define HAL_HW_PCI_8171_DEVICE_ID 0x8171 //8191 SE Unicron
#define HAL_HW_PCI_0045_DEVICE_ID 0x0045 //8190 PCI for Ceraga
#define HAL_HW_PCI_0046_DEVICE_ID 0x0046 //8190 Cardbus for Ceraga
#define HAL_HW_PCI_0044_DEVICE_ID 0x0044 //8192e PCIE for Ceraga
@ -68,12 +68,12 @@
#define HAL_HW_PCI_8192CE_DEVICE_ID 0x8178 //8192ce
#define HAL_HW_PCI_8191CE_DEVICE_ID 0x8177 //8192ce
#define HAL_HW_PCI_8188CE_DEVICE_ID 0x8176 //8192ce
#define HAL_HW_PCI_8192CU_DEVICE_ID 0x8191 //8192ce
#define HAL_HW_PCI_8192CU_DEVICE_ID 0x8191 //8192ce
#define HAL_HW_PCI_8192DE_DEVICE_ID 0x8193 //8192de
#define HAL_HW_PCI_002B_DEVICE_ID 0x002B //8192de, provided by HW SD
#define HAL_HW_PCI_8188EE_DEVICE_ID 0x8179
#define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI 0x1000 //8190 support 16 pages of IO registers
#define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI 0x1000 //8190 support 16 pages of IO registers
#define HAL_HW_PCI_REVISION_ID_8190PCI 0x00
#define HAL_MEMORY_MAPPED_IO_RANGE_8192PCIE 0x4000 //8192 support 16 pages of IO registers
#define HAL_HW_PCI_REVISION_ID_8192PCIE 0x01
@ -100,10 +100,10 @@ struct rt_pci_capabilities_header {
struct pci_priv{
u8 linkctrl_reg;
u8 busnumber;
u8 devnumber;
u8 funcnumber;
u8 devnumber;
u8 funcnumber;
u8 pcibridge_busnum;
u8 pcibridge_devnum;
@ -112,7 +112,7 @@ struct pci_priv{
u16 pcibridge_vendorid;
u16 pcibridge_deviceid;
u8 pcibridge_pciehdr_offset;
u8 pcibridge_linkctrlreg;
u8 pcibridge_linkctrlreg;
u8 amd_l1_patch;
};
@ -128,10 +128,10 @@ typedef struct _RT_ISR_CONTENT
//#define RegAddr(addr) (addr + 0xB2000000UL)
//some platform macros will def here
static inline void NdisRawWritePortUlong(u32 port, u32 val)
static inline void NdisRawWritePortUlong(u32 port, u32 val)
{
outl(val, port);
//writel(val, (u8 *)RegAddr(port));
//writel(val, (u8 *)RegAddr(port));
}
static inline void NdisRawWritePortUchar(u32 port, u8 val)
@ -162,4 +162,3 @@ void rtl8188ee_set_hal_ops(struct adapter * padapter);
#define hal_set_hal_ops rtl8188ee_set_hal_ops
#endif //__PCIE_HAL_H__

3
include/pci_ops.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -40,4 +40,3 @@ void rtl8188ee_set_intf_ops(struct _io_ops *pops);
#define pci_set_intf_ops rtl8188ee_set_intf_ops
#endif

3
include/pci_osintf.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -30,4 +30,3 @@ void rtw_pci_enable_aspm(struct adapter *padapter);
#endif

7
include/recv_osdep.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -35,13 +35,13 @@ extern sint _rtw_init_recv_priv(struct recv_priv *precvpriv, struct adapter *pad
extern void _rtw_free_recv_priv (struct recv_priv *precvpriv);
extern s32 rtw_recv_entry(union recv_frame *precv_frame);
extern s32 rtw_recv_entry(union recv_frame *precv_frame);
extern int rtw_recv_indicatepkt(struct adapter *adapter, union recv_frame *precv_frame);
extern void rtw_recv_returnpacket(IN _nic_hdl cnxt, IN _pkt *preturnedpkt);
extern void rtw_hostapd_mlme_rx(struct adapter *padapter, union recv_frame *precv_frame);
extern void rtw_handle_tkip_mic_err(struct adapter *padapter,u8 bgroup);
int rtw_init_recv_priv(struct recv_priv *precvpriv, struct adapter *padapter);
void rtw_free_recv_priv (struct recv_priv *precvpriv);
@ -61,4 +61,3 @@ void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl);
#endif //

24
include/rtl8188e_cmd.h
View file

@ -35,7 +35,7 @@ enum cmd_msg_element_id
P2P_PS_OFFLOAD_EID = 8,
SELECTIVE_SUSPEND_ROF_CMD = 9,
P2P_PS_CTW_CMD_EID = 32,
MAX_CMDMSG_EID
MAX_CMDMSG_EID
};
#else
typedef enum _RTL8188E_H2C_CMD_ID
@ -43,8 +43,8 @@ typedef enum _RTL8188E_H2C_CMD_ID
//Class Common
H2C_COM_RSVD_PAGE =0x00,
H2C_COM_MEDIA_STATUS_RPT =0x01,
H2C_COM_SCAN =0x02,
H2C_COM_KEEP_ALIVE =0x03,
H2C_COM_SCAN =0x02,
H2C_COM_KEEP_ALIVE =0x03,
H2C_COM_DISCNT_DECISION =0x04,
#ifndef CONFIG_WOWLAN
H2C_COM_WWLAN =0x05,
@ -71,7 +71,7 @@ typedef enum _RTL8188E_H2C_CMD_ID
H2C_BT_COEX_GPIO_MODE =0x61,
H2C_BT_DAC_SWING_VAL =0x62,
H2C_BT_PSD_RST =0x63,
//Class Remote WakeUp
#ifdef CONFIG_WOWLAN
H2C_COM_WWLAN =0x80,
@ -80,10 +80,10 @@ typedef enum _RTL8188E_H2C_CMD_ID
H2C_COM_AOAC_RSVD_PAGE =0x83,
#endif
//Class
//Class
H2C_RESET_TSF =0xc0,
}RTL8188E_H2C_CMD_ID;
#endif
@ -209,11 +209,11 @@ typedef struct _SETAOAC_GLOBAL_INFO{
#define SET_ARP_PKT_PROTOCOL(__pHeader, __Value) WriteEF2Byte( ((u8*)(__pHeader)) + 2, __Value)
#define SET_ARP_PKT_HW_ADDR_LEN(__pHeader, __Value) WriteEF1Byte( ((u8*)(__pHeader)) + 4, __Value)
#define SET_ARP_PKT_PROTOCOL_ADDR_LEN(__pHeader, __Value) WriteEF1Byte( ((u8*)(__pHeader)) + 5, __Value)
#define SET_ARP_PKT_OPERATION(__pHeader, __Value) WriteEF2Byte( ((u8*)(__pHeader)) + 6, __Value)
#define SET_ARP_PKT_SENDER_MAC_ADDR(__pHeader, _val) cpMacAddr(((u8*)(__pHeader))+8, (u8*)(_val))
#define SET_ARP_PKT_SENDER_IP_ADDR(__pHeader, _val) cpIpAddr(((u8*)(__pHeader))+14, (u8*)(_val))
#define SET_ARP_PKT_TARGET_MAC_ADDR(__pHeader, _val) cpMacAddr(((u8*)(__pHeader))+18, (u8*)(_val))
#define SET_ARP_PKT_TARGET_IP_ADDR(__pHeader, _val) cpIpAddr(((u8*)(__pHeader))+24, (u8*)(_val))
#define SET_ARP_PKT_OPERATION(__pHeader, __Value) WriteEF2Byte( ((u8*)(__pHeader)) + 6, __Value)
#define SET_ARP_PKT_SENDER_MAC_ADDR(__pHeader, _val) cpMacAddr(((u8*)(__pHeader))+8, (u8*)(_val))
#define SET_ARP_PKT_SENDER_IP_ADDR(__pHeader, _val) cpIpAddr(((u8*)(__pHeader))+14, (u8*)(_val))
#define SET_ARP_PKT_TARGET_MAC_ADDR(__pHeader, _val) cpMacAddr(((u8*)(__pHeader))+18, (u8*)(_val))
#define SET_ARP_PKT_TARGET_IP_ADDR(__pHeader, _val) cpIpAddr(((u8*)(__pHeader))+24, (u8*)(_val))
#define FW_WOWLAN_FUN_EN BIT(0)
#define FW_WOWLAN_PATTERN_MATCH BIT(1)
@ -254,5 +254,3 @@ void SetFwRelatedForWoWLAN8188ES(struct adapter* padapter, u8 bHostIsGoingtoSlee
#define SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#endif//__RTL8188E_CMD_H__

21
include/rtl8188e_dm.h
View file

@ -21,7 +21,7 @@
#define __RTL8188E_DM_H__
enum{
UP_LINK,
DOWN_LINK,
DOWN_LINK,
};
//###### duplicate code,will move to ODM #########
#define IQK_MAC_REG_NUM 4
@ -29,7 +29,7 @@ enum{
#define IQK_BB_REG_NUM 9
#define HP_THERMAL_NUM 8
//###### duplicate code,will move to ODM #########
struct dm_priv
struct dm_priv
{
u8 DM_Type;
u8 DMFlag;
@ -54,7 +54,7 @@ struct dm_priv
PS_T DM_PSTable;
FALSE_ALARM_STATISTICS FalseAlmCnt;
//for rate adaptive, in fact, 88c/92c fw will handle this
u8 bUseRAMask;
RATE_ADAPTIVE RateAdaptive;
@ -65,11 +65,11 @@ struct dm_priv
u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06
u8 PowerIndex_backup[6];
u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
#if 0
#if 0
//for tx power tracking
u8 bTXPowerTracking;
u8 TXPowercount;
u8 bTXPowerTrackingInit;
u8 bTXPowerTrackingInit;
u8 TM_Trigger;
@ -89,7 +89,7 @@ struct dm_priv
u8 bDPdone;
u8 bDPPathAOK;
u8 bDPPathBOK;
//for IQK
u32 RegC04;
u32 Reg874;
@ -103,7 +103,7 @@ struct dm_priv
u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
u32 IQK_BB_backup_recover[9];
u32 IQK_BB_backup[IQK_BB_REG_NUM];
u8 bCCKinCH14;
@ -137,10 +137,10 @@ struct dm_priv
//for Antenna diversity
#ifdef CONFIG_ANTENNA_DIVERSITY
// SWAT_T DM_SWAT_Table;
#endif
#endif
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
// _timer SwAntennaSwitchTimer;
/*
/*
u64 lastTxOkCnt;
u64 lastRxOkCnt;
u64 TXByteCnt_A;
@ -154,7 +154,7 @@ struct dm_priv
s32 OFDM_Pkt_Cnt;
u8 RSSI_Select;
// u8 DIG_Dynamic_MIN ;
// u8 DIG_Dynamic_MIN ;
//###### duplicate code,will move to ODM #########
#endif
// Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas
@ -176,4 +176,3 @@ void AntDivCompare8188E(struct adapter *Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_
u8 AntDivBeforeLink8188E(struct adapter *Adapter );
#endif
#endif

1427
include/rtl8188e_hal.h
View file

File diff suppressed because it is too large Load diff

91
include/rtl8188e_led.h
View file

@ -1,46 +1,45 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8188E_LED_H__
#define __RTL8188E_LED_H__
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
#ifdef CONFIG_USB_HCI
void rtl8188eu_InitSwLeds(struct adapter *padapter);
void rtl8188eu_DeInitSwLeds(struct adapter *padapter);
#endif
#ifdef CONFIG_PCI_HCI
void rtl8188ee_gen_RefreshLedState(struct adapter *Adapter);
void rtl8188ee_InitSwLeds(struct adapter *padapter);
void rtl8188ee_DeInitSwLeds(struct adapter *padapter);
#endif
#ifdef CONFIG_SDIO_HCI
void rtl8188es_InitSwLeds(struct adapter *padapter);
void rtl8188es_DeInitSwLeds(struct adapter *padapter);
#endif
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8188E_LED_H__
#define __RTL8188E_LED_H__
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
#ifdef CONFIG_USB_HCI
void rtl8188eu_InitSwLeds(struct adapter *padapter);
void rtl8188eu_DeInitSwLeds(struct adapter *padapter);
#endif
#ifdef CONFIG_PCI_HCI
void rtl8188ee_gen_RefreshLedState(struct adapter *Adapter);
void rtl8188ee_InitSwLeds(struct adapter *padapter);
void rtl8188ee_DeInitSwLeds(struct adapter *padapter);
#endif
#ifdef CONFIG_SDIO_HCI
void rtl8188es_InitSwLeds(struct adapter *padapter);
void rtl8188es_DeInitSwLeds(struct adapter *padapter);
#endif
#endif

291
include/rtl8188e_recv.h
View file

@ -1,146 +1,145 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8188E_RECV_H__
#define __RTL8188E_RECV_H__
#include <rtl8192c_recv.h>
#define TX_RPT1_PKT_LEN 8
typedef enum _RX_PACKET_TYPE{
NORMAL_RX,//Normal rx packet
TX_REPORT1,//CCX
TX_REPORT2,//TX RPT
HIS_REPORT,// USB HISR RPT
}RX_PACKET_TYPE, *PRX_PACKET_TYPE;
typedef struct rxreport_8188e
{
//Offset 0
u32 pktlen:14;
u32 crc32:1;
u32 icverr:1;
u32 drvinfosize:4;
u32 security:3;
u32 qos:1;
u32 shift:2;
u32 physt:1;
u32 swdec:1;
u32 ls:1;
u32 fs:1;
u32 eor:1;
u32 own:1;
//Offset 4
u32 macid:5;
u32 tid:4;
u32 hwrsvd:4;
u32 amsdu:1;
u32 paggr:1;
u32 faggr:1;
u32 a1fit:4;
u32 a2fit:4;
u32 pam:1;
u32 pwr:1;
u32 md:1;
u32 mf:1;
u32 type:2;
u32 mc:1;
u32 bc:1;
//Offset 8
u32 seq:12;
u32 frag:4;
u32 nextpktlen:14;
u32 nextind:1;
u32 rsvd0831:1;
//Offset 12
u32 rxmcs:6;
u32 rxht:1;
u32 gf:1;
u32 splcp:1;
u32 bw:1;
u32 htc:1;
u32 eosp:1;
u32 bssidfit:2;
u32 rpt_sel:2;
u32 rsvd1216:13;
u32 pattern_match:1;
u32 unicastwake:1;
u32 magicwake:1;
//Offset 16
/*
u32 pattern0match:1;
u32 pattern1match:1;
u32 pattern2match:1;
u32 pattern3match:1;
u32 pattern4match:1;
u32 pattern5match:1;
u32 pattern6match:1;
u32 pattern7match:1;
u32 pattern8match:1;
u32 pattern9match:1;
u32 patternamatch:1;
u32 patternbmatch:1;
u32 patterncmatch:1;
u32 rsvd1613:19;
*/
u32 rsvd16;
//Offset 20
u32 tsfl;
//Offset 24
u32 bassn:12;
u32 bavld:1;
u32 rsvd2413:19;
} RXREPORT, *PRXREPORT;
#ifdef CONFIG_SDIO_HCI
s32 rtl8188es_init_recv_priv(struct adapter *padapter);
void rtl8188es_free_recv_priv(struct adapter *padapter);
void rtl8188es_recv_hdl(struct adapter *padapter, struct recv_buf *precvbuf);
#endif
#ifdef CONFIG_USB_HCI
#define INTERRUPT_MSG_FORMAT_LEN 60
void rtl8188eu_init_recvbuf(struct adapter *padapter, struct recv_buf *precvbuf);
s32 rtl8188eu_init_recv_priv(struct adapter *padapter);
void rtl8188eu_free_recv_priv(struct adapter *padapter);
void rtl8188eu_recv_hdl(struct adapter *padapter, struct recv_buf *precvbuf);
void rtl8188eu_recv_tasklet(void *priv);
#endif
#ifdef CONFIG_PCI_HCI
s32 rtl8188ee_init_recv_priv(struct adapter *padapter);
void rtl8188ee_free_recv_priv(struct adapter *padapter);
#endif
void rtl8188e_query_rx_phy_status(union recv_frame *prframe, struct phy_stat *pphy_stat);
void rtl8188e_process_phy_info(struct adapter *padapter, void *prframe);
void update_recvframe_phyinfo_88e(union recv_frame *precvframe,struct phy_stat *pphy_status);
void update_recvframe_attrib_88e( union recv_frame *precvframe, struct recv_stat *prxstat);
#endif
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8188E_RECV_H__
#define __RTL8188E_RECV_H__
#include <rtl8192c_recv.h>
#define TX_RPT1_PKT_LEN 8
typedef enum _RX_PACKET_TYPE{
NORMAL_RX,//Normal rx packet
TX_REPORT1,//CCX
TX_REPORT2,//TX RPT
HIS_REPORT,// USB HISR RPT
}RX_PACKET_TYPE, *PRX_PACKET_TYPE;
typedef struct rxreport_8188e
{
//Offset 0
u32 pktlen:14;
u32 crc32:1;
u32 icverr:1;
u32 drvinfosize:4;
u32 security:3;
u32 qos:1;
u32 shift:2;
u32 physt:1;
u32 swdec:1;
u32 ls:1;
u32 fs:1;
u32 eor:1;
u32 own:1;
//Offset 4
u32 macid:5;
u32 tid:4;
u32 hwrsvd:4;
u32 amsdu:1;
u32 paggr:1;
u32 faggr:1;
u32 a1fit:4;
u32 a2fit:4;
u32 pam:1;
u32 pwr:1;
u32 md:1;
u32 mf:1;
u32 type:2;
u32 mc:1;
u32 bc:1;
//Offset 8
u32 seq:12;
u32 frag:4;
u32 nextpktlen:14;
u32 nextind:1;
u32 rsvd0831:1;
//Offset 12
u32 rxmcs:6;
u32 rxht:1;
u32 gf:1;
u32 splcp:1;
u32 bw:1;
u32 htc:1;
u32 eosp:1;
u32 bssidfit:2;
u32 rpt_sel:2;
u32 rsvd1216:13;
u32 pattern_match:1;
u32 unicastwake:1;
u32 magicwake:1;
//Offset 16
/*
u32 pattern0match:1;
u32 pattern1match:1;
u32 pattern2match:1;
u32 pattern3match:1;
u32 pattern4match:1;
u32 pattern5match:1;
u32 pattern6match:1;
u32 pattern7match:1;
u32 pattern8match:1;
u32 pattern9match:1;
u32 patternamatch:1;
u32 patternbmatch:1;
u32 patterncmatch:1;
u32 rsvd1613:19;
*/
u32 rsvd16;
//Offset 20
u32 tsfl;
//Offset 24
u32 bassn:12;
u32 bavld:1;
u32 rsvd2413:19;
} RXREPORT, *PRXREPORT;
#ifdef CONFIG_SDIO_HCI
s32 rtl8188es_init_recv_priv(struct adapter *padapter);
void rtl8188es_free_recv_priv(struct adapter *padapter);
void rtl8188es_recv_hdl(struct adapter *padapter, struct recv_buf *precvbuf);
#endif
#ifdef CONFIG_USB_HCI
#define INTERRUPT_MSG_FORMAT_LEN 60
void rtl8188eu_init_recvbuf(struct adapter *padapter, struct recv_buf *precvbuf);
s32 rtl8188eu_init_recv_priv(struct adapter *padapter);
void rtl8188eu_free_recv_priv(struct adapter *padapter);
void rtl8188eu_recv_hdl(struct adapter *padapter, struct recv_buf *precvbuf);
void rtl8188eu_recv_tasklet(void *priv);
#endif
#ifdef CONFIG_PCI_HCI
s32 rtl8188ee_init_recv_priv(struct adapter *padapter);
void rtl8188ee_free_recv_priv(struct adapter *padapter);
#endif
void rtl8188e_query_rx_phy_status(union recv_frame *prframe, struct phy_stat *pphy_stat);
void rtl8188e_process_phy_info(struct adapter *padapter, void *prframe);
void update_recvframe_phyinfo_88e(union recv_frame *precvframe,struct phy_stat *pphy_status);
void update_recvframe_attrib_88e( union recv_frame *precvframe, struct recv_stat *prxstat);
#endif

9
include/rtl8188e_rf.h
View file

@ -26,11 +26,11 @@
int PHY_RF6052_Config8188E( IN struct adapter * Adapter );
void rtl8188e_RF_ChangeTxPath( IN struct adapter *Adapter,
void rtl8188e_RF_ChangeTxPath( IN struct adapter *Adapter,
IN u16 DataRate);
void rtl8188e_PHY_RF6052SetBandwidth(
void rtl8188e_PHY_RF6052SetBandwidth(
IN struct adapter * Adapter,
IN HT_CHANNEL_WIDTH Bandwidth);
IN HT_CHANNEL_WIDTH Bandwidth);
VOID rtl8188e_PHY_RF6052SetCckTxPower(
IN struct adapter *Adapter,
IN u8* pPowerlevel);
@ -38,8 +38,7 @@ VOID rtl8188e_PHY_RF6052SetOFDMTxPower(
IN struct adapter *Adapter,
IN u8* pPowerLevelOFDM,
IN u8* pPowerLevelBW20,
IN u8* pPowerLevelBW40,
IN u8* pPowerLevelBW40,
IN u8 Channel);
#endif//__RTL8188E_RF_H__

3481
include/rtl8188e_spec.h
View file

File diff suppressed because it is too large Load diff

3
include/rtl8188e_sreset.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -30,4 +30,3 @@ extern void rtl8188e_sreset_xmit_status_check(struct adapter *padapter);
extern void rtl8188e_sreset_linked_status_check(struct adapter *padapter);
#endif
#endif

621
include/rtl8188e_xmit.h
View file

@ -1,311 +1,310 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8188E_XMIT_H__
#define __RTL8188E_XMIT_H__
#define MAX_TX_AGG_PACKET_NUMBER 0xFF
//
// Queue Select Value in TxDesc
//
#define QSLT_BK 0x2//0x01
#define QSLT_BE 0x0
#define QSLT_VI 0x5//0x4
#define QSLT_VO 0x7//0x6
#define QSLT_BEACON 0x10
#define QSLT_HIGH 0x11
#define QSLT_MGNT 0x12
#define QSLT_CMD 0x13
//For 88e early mode
#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)
#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)
#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
//
//defined for TX DESC Operation
//
#define MAX_TID (15)
//OFFSET 0
#define OFFSET_SZ 0
#define OFFSET_SHT 16
#define BMC BIT(24)
#define LSG BIT(26)
#define FSG BIT(27)
#define OWN BIT(31)
//OFFSET 4
#define PKT_OFFSET_SZ 0
#define QSEL_SHT 8
#define RATE_ID_SHT 16
#define NAVUSEHDR BIT(20)
#define SEC_TYPE_SHT 22
#define PKT_OFFSET_SHT 26
//OFFSET 8
#define AGG_EN BIT(12)
#define AGG_BK BIT(16)
#define AMPDU_DENSITY_SHT 20
#define ANTSEL_A BIT(24)
#define ANTSEL_B BIT(25)
#define TX_ANT_CCK_SHT 26
#define TX_ANTL_SHT 28
#define TX_ANT_HT_SHT 30
//OFFSET 12
#define SEQ_SHT 16
#define EN_HWSEQ BIT(31)
//OFFSET 16
#define QOS BIT(6)
#define HW_SSN BIT(7)
#define USERATE BIT(8)
#define DISDATAFB BIT(10)
#define CTS_2_SELF BIT(11)
#define RTS_EN BIT(12)
#define HW_RTS_EN BIT(13)
#define DATA_SHORT BIT(24)
#define PWR_STATUS_SHT 15
#define DATA_SC_SHT 20
#define DATA_BW BIT(25)
//OFFSET 20
#define RTY_LMT_EN BIT(17)
enum TXDESC_SC{
SC_DONT_CARE = 0x00,
SC_UPPER= 0x01,
SC_LOWER=0x02,
SC_DUPLICATE=0x03
};
//OFFSET 20
#define SGI BIT(6)
#define USB_TXAGG_NUM_SHT 24
typedef struct txdesc_88e
{
//Offset 0
u32 pktlen:16;
u32 offset:8;
u32 bmc:1;
u32 htc:1;
u32 ls:1;
u32 fs:1;
u32 linip:1;
u32 noacm:1;
u32 gf:1;
u32 own:1;
//Offset 4
u32 macid:6;
u32 rsvd0406:2;
u32 qsel:5;
u32 rd_nav_ext:1;
u32 lsig_txop_en:1;
u32 pifs:1;
u32 rate_id:4;
u32 navusehdr:1;
u32 en_desc_id:1;
u32 sectype:2;
u32 rsvd0424:2;
u32 pkt_offset:5; // unit: 8 bytes
u32 rsvd0431:1;
//Offset 8
u32 rts_rc:6;
u32 data_rc:6;
u32 agg_en:1;
u32 rd_en:1;
u32 bar_rty_th:2;
u32 bk:1;
u32 morefrag:1;
u32 raw:1;
u32 ccx:1;
u32 ampdu_density:3;
u32 bt_null:1;
u32 ant_sel_a:1;
u32 ant_sel_b:1;
u32 tx_ant_cck:2;
u32 tx_antl:2;
u32 tx_ant_ht:2;
//Offset 12
u32 nextheadpage:8;
u32 tailpage:8;
u32 seq:12;
u32 cpu_handle:1;
u32 tag1:1;
u32 trigger_int:1;
u32 hwseq_en:1;
//Offset 16
u32 rtsrate:5;
u32 ap_dcfe:1;
u32 hwseq_sel:2;
u32 userate:1;
u32 disrtsfb:1;
u32 disdatafb:1;
u32 cts2self:1;
u32 rtsen:1;
u32 hw_rts_en:1;
u32 port_id:1;
u32 pwr_status:3;
u32 wait_dcts:1;
u32 cts2ap_en:1;
u32 data_sc:2;
u32 data_stbc:2;
u32 data_short:1;
u32 data_bw:1;
u32 rts_short:1;
u32 rts_bw:1;
u32 rts_sc:2;
u32 vcs_stbc:2;
//Offset 20
u32 datarate:6;
u32 sgi:1;
u32 try_rate:1;
u32 data_ratefb_lmt:5;
u32 rts_ratefb_lmt:4;
u32 rty_lmt_en:1;
u32 data_rt_lmt:6;
u32 usb_txagg_num:8;
//Offset 24
u32 txagg_a:5;
u32 txagg_b:5;
u32 use_max_len:1;
u32 max_agg_num:5;
u32 mcsg1_max_len:4;
u32 mcsg2_max_len:4;
u32 mcsg3_max_len:4;
u32 mcs7_sgi_max_len:4;
//Offset 28
u32 checksum:16; // TxBuffSize(PCIe)/CheckSum(USB)
u32 sw0:8; /* offset 30 */
u32 sw1:4;
u32 mcs15_sgi_max_len:4;
}TXDESC, *PTXDESC;
#define txdesc_set_ccx_sw_88e(txdesc, value) \
do { \
((struct txdesc_88e *)(txdesc))->sw1 = (((value)>>8) & 0x0f); \
((struct txdesc_88e *)(txdesc))->sw0 = ((value) & 0xff); \
} while (0)
struct txrpt_ccx_88e {
/* offset 0 */
u8 tag1:1;
u8 pkt_num:3;
u8 txdma_underflow:1;
u8 int_bt:1;
u8 int_tri:1;
u8 int_ccx:1;
/* offset 1 */
u8 mac_id:6;
u8 pkt_ok:1;
u8 bmc:1;
/* offset 2 */
u8 retry_cnt:6;
u8 lifetime_over:1;
u8 retry_over:1;
/* offset 3 */
u8 ccx_qtime0;
u8 ccx_qtime1;
/* offset 5 */
u8 final_data_rate;
/* offset 6 */
u8 sw1:4;
u8 qsel:4;
/* offset 7 */
u8 sw0;
};
#define txrpt_ccx_sw_88e(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8))
#define txrpt_ccx_qtime_88e(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
void rtl8188e_fill_fake_txdesc(struct adapter *padapter,u8*pDesc,u32 BufferLen,u8 IsPsPoll,u8 IsBTQosNull);
#ifdef CONFIG_SDIO_HCI
s32 rtl8188es_init_xmit_priv(struct adapter *padapter);
void rtl8188es_free_xmit_priv(struct adapter *padapter);
s32 rtl8188es_hal_xmit(struct adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8188es_mgnt_xmit(struct adapter *padapter, struct xmit_frame *pmgntframe);
s32 rtl8188es_hal_xmitframe_enqueue(struct adapter *padapter, struct xmit_frame *pxmitframe);
thread_return rtl8188es_xmit_thread(thread_context context);
s32 rtl8188es_xmit_buf_handler(struct adapter *padapter);
#define hal_xmit_handler rtl8188es_xmit_buf_handler
#ifdef CONFIG_SDIO_TX_TASKLET
void rtl8188es_xmit_tasklet(void *priv);
#endif
#endif
#ifdef CONFIG_USB_HCI
s32 rtl8188eu_init_xmit_priv(struct adapter *padapter);
void rtl8188eu_free_xmit_priv(struct adapter *padapter);
s32 rtl8188eu_hal_xmit(struct adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8188eu_mgnt_xmit(struct adapter *padapter, struct xmit_frame *pmgntframe);
s32 rtl8188eu_hal_xmitframe_enqueue(struct adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8188eu_xmit_buf_handler(struct adapter *padapter);
#define hal_xmit_handler rtl8188eu_xmit_buf_handler
void rtl8188eu_xmit_tasklet(void *priv);
s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
#endif
#ifdef CONFIG_PCI_HCI
s32 rtl8188ee_init_xmit_priv(struct adapter *padapter);
void rtl8188ee_free_xmit_priv(struct adapter *padapter);
struct xmit_buf *rtl8188ee_dequeue_xmitbuf(struct rtw_tx_ring *ring);
void rtl8188ee_xmitframe_resume(struct adapter *padapter);
s32 rtl8188ee_hal_xmit(struct adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8188ee_mgnt_xmit(struct adapter *padapter, struct xmit_frame *pmgntframe);
void rtl8188ee_xmit_tasklet(void *priv);
#endif
#ifdef CONFIG_TX_EARLY_MODE
void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmitbuf );
#endif
#ifdef CONFIG_XMIT_ACK
void dump_txrpt_ccx_88e(void *buf);
void handle_txrpt_ccx_88e(struct adapter *adapter, u8 *buf);
#else
#define dump_txrpt_ccx_88e(buf) do {} while(0)
#define handle_txrpt_ccx_88e(adapter, buf) do {} while(0)
#endif //CONFIG_XMIT_ACK
void _dbg_dump_tx_info(struct adapter *padapter,int frame_tag,struct tx_desc *ptxdesc);
#endif //__RTL8188E_XMIT_H__
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8188E_XMIT_H__
#define __RTL8188E_XMIT_H__
#define MAX_TX_AGG_PACKET_NUMBER 0xFF
//
// Queue Select Value in TxDesc
//
#define QSLT_BK 0x2//0x01
#define QSLT_BE 0x0
#define QSLT_VI 0x5//0x4
#define QSLT_VO 0x7//0x6
#define QSLT_BEACON 0x10
#define QSLT_HIGH 0x11
#define QSLT_MGNT 0x12
#define QSLT_CMD 0x13
//For 88e early mode
#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)
#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)
#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
//
//defined for TX DESC Operation
//
#define MAX_TID (15)
//OFFSET 0
#define OFFSET_SZ 0
#define OFFSET_SHT 16
#define BMC BIT(24)
#define LSG BIT(26)
#define FSG BIT(27)
#define OWN BIT(31)
//OFFSET 4
#define PKT_OFFSET_SZ 0
#define QSEL_SHT 8
#define RATE_ID_SHT 16
#define NAVUSEHDR BIT(20)
#define SEC_TYPE_SHT 22
#define PKT_OFFSET_SHT 26
//OFFSET 8
#define AGG_EN BIT(12)
#define AGG_BK BIT(16)
#define AMPDU_DENSITY_SHT 20
#define ANTSEL_A BIT(24)
#define ANTSEL_B BIT(25)
#define TX_ANT_CCK_SHT 26
#define TX_ANTL_SHT 28
#define TX_ANT_HT_SHT 30
//OFFSET 12
#define SEQ_SHT 16
#define EN_HWSEQ BIT(31)
//OFFSET 16
#define QOS BIT(6)
#define HW_SSN BIT(7)
#define USERATE BIT(8)
#define DISDATAFB BIT(10)
#define CTS_2_SELF BIT(11)
#define RTS_EN BIT(12)
#define HW_RTS_EN BIT(13)
#define DATA_SHORT BIT(24)
#define PWR_STATUS_SHT 15
#define DATA_SC_SHT 20
#define DATA_BW BIT(25)
//OFFSET 20
#define RTY_LMT_EN BIT(17)
enum TXDESC_SC{
SC_DONT_CARE = 0x00,
SC_UPPER= 0x01,
SC_LOWER=0x02,
SC_DUPLICATE=0x03
};
//OFFSET 20
#define SGI BIT(6)
#define USB_TXAGG_NUM_SHT 24
typedef struct txdesc_88e
{
//Offset 0
u32 pktlen:16;
u32 offset:8;
u32 bmc:1;
u32 htc:1;
u32 ls:1;
u32 fs:1;
u32 linip:1;
u32 noacm:1;
u32 gf:1;
u32 own:1;
//Offset 4
u32 macid:6;
u32 rsvd0406:2;
u32 qsel:5;
u32 rd_nav_ext:1;
u32 lsig_txop_en:1;
u32 pifs:1;
u32 rate_id:4;
u32 navusehdr:1;
u32 en_desc_id:1;
u32 sectype:2;
u32 rsvd0424:2;
u32 pkt_offset:5; // unit: 8 bytes
u32 rsvd0431:1;
//Offset 8
u32 rts_rc:6;
u32 data_rc:6;
u32 agg_en:1;
u32 rd_en:1;
u32 bar_rty_th:2;
u32 bk:1;
u32 morefrag:1;
u32 raw:1;
u32 ccx:1;
u32 ampdu_density:3;
u32 bt_null:1;
u32 ant_sel_a:1;
u32 ant_sel_b:1;
u32 tx_ant_cck:2;
u32 tx_antl:2;
u32 tx_ant_ht:2;
//Offset 12
u32 nextheadpage:8;
u32 tailpage:8;
u32 seq:12;
u32 cpu_handle:1;
u32 tag1:1;
u32 trigger_int:1;
u32 hwseq_en:1;
//Offset 16
u32 rtsrate:5;
u32 ap_dcfe:1;
u32 hwseq_sel:2;
u32 userate:1;
u32 disrtsfb:1;
u32 disdatafb:1;
u32 cts2self:1;
u32 rtsen:1;
u32 hw_rts_en:1;
u32 port_id:1;
u32 pwr_status:3;
u32 wait_dcts:1;
u32 cts2ap_en:1;
u32 data_sc:2;
u32 data_stbc:2;
u32 data_short:1;
u32 data_bw:1;
u32 rts_short:1;
u32 rts_bw:1;
u32 rts_sc:2;
u32 vcs_stbc:2;
//Offset 20
u32 datarate:6;
u32 sgi:1;
u32 try_rate:1;
u32 data_ratefb_lmt:5;
u32 rts_ratefb_lmt:4;
u32 rty_lmt_en:1;
u32 data_rt_lmt:6;
u32 usb_txagg_num:8;
//Offset 24
u32 txagg_a:5;
u32 txagg_b:5;
u32 use_max_len:1;
u32 max_agg_num:5;
u32 mcsg1_max_len:4;
u32 mcsg2_max_len:4;
u32 mcsg3_max_len:4;
u32 mcs7_sgi_max_len:4;
//Offset 28
u32 checksum:16; // TxBuffSize(PCIe)/CheckSum(USB)
u32 sw0:8; /* offset 30 */
u32 sw1:4;
u32 mcs15_sgi_max_len:4;
}TXDESC, *PTXDESC;
#define txdesc_set_ccx_sw_88e(txdesc, value) \
do { \
((struct txdesc_88e *)(txdesc))->sw1 = (((value)>>8) & 0x0f); \
((struct txdesc_88e *)(txdesc))->sw0 = ((value) & 0xff); \
} while (0)
struct txrpt_ccx_88e {
/* offset 0 */
u8 tag1:1;
u8 pkt_num:3;
u8 txdma_underflow:1;
u8 int_bt:1;
u8 int_tri:1;
u8 int_ccx:1;
/* offset 1 */
u8 mac_id:6;
u8 pkt_ok:1;
u8 bmc:1;
/* offset 2 */
u8 retry_cnt:6;
u8 lifetime_over:1;
u8 retry_over:1;
/* offset 3 */
u8 ccx_qtime0;
u8 ccx_qtime1;
/* offset 5 */
u8 final_data_rate;
/* offset 6 */
u8 sw1:4;
u8 qsel:4;
/* offset 7 */
u8 sw0;
};
#define txrpt_ccx_sw_88e(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8))
#define txrpt_ccx_qtime_88e(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
void rtl8188e_fill_fake_txdesc(struct adapter *padapter,u8*pDesc,u32 BufferLen,u8 IsPsPoll,u8 IsBTQosNull);
#ifdef CONFIG_SDIO_HCI
s32 rtl8188es_init_xmit_priv(struct adapter *padapter);
void rtl8188es_free_xmit_priv(struct adapter *padapter);
s32 rtl8188es_hal_xmit(struct adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8188es_mgnt_xmit(struct adapter *padapter, struct xmit_frame *pmgntframe);
s32 rtl8188es_hal_xmitframe_enqueue(struct adapter *padapter, struct xmit_frame *pxmitframe);
thread_return rtl8188es_xmit_thread(thread_context context);
s32 rtl8188es_xmit_buf_handler(struct adapter *padapter);
#define hal_xmit_handler rtl8188es_xmit_buf_handler
#ifdef CONFIG_SDIO_TX_TASKLET
void rtl8188es_xmit_tasklet(void *priv);
#endif
#endif
#ifdef CONFIG_USB_HCI
s32 rtl8188eu_init_xmit_priv(struct adapter *padapter);
void rtl8188eu_free_xmit_priv(struct adapter *padapter);
s32 rtl8188eu_hal_xmit(struct adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8188eu_mgnt_xmit(struct adapter *padapter, struct xmit_frame *pmgntframe);
s32 rtl8188eu_hal_xmitframe_enqueue(struct adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8188eu_xmit_buf_handler(struct adapter *padapter);
#define hal_xmit_handler rtl8188eu_xmit_buf_handler
void rtl8188eu_xmit_tasklet(void *priv);
s32 rtl8188eu_xmitframe_complete(struct adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
#endif
#ifdef CONFIG_PCI_HCI
s32 rtl8188ee_init_xmit_priv(struct adapter *padapter);
void rtl8188ee_free_xmit_priv(struct adapter *padapter);
struct xmit_buf *rtl8188ee_dequeue_xmitbuf(struct rtw_tx_ring *ring);
void rtl8188ee_xmitframe_resume(struct adapter *padapter);
s32 rtl8188ee_hal_xmit(struct adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8188ee_mgnt_xmit(struct adapter *padapter, struct xmit_frame *pmgntframe);
void rtl8188ee_xmit_tasklet(void *priv);
#endif
#ifdef CONFIG_TX_EARLY_MODE
void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmitbuf );
#endif
#ifdef CONFIG_XMIT_ACK
void dump_txrpt_ccx_88e(void *buf);
void handle_txrpt_ccx_88e(struct adapter *adapter, u8 *buf);
#else
#define dump_txrpt_ccx_88e(buf) do {} while(0)
#define handle_txrpt_ccx_88e(adapter, buf) do {} while(0)
#endif //CONFIG_XMIT_ACK
void _dbg_dump_tx_info(struct adapter *padapter,int frame_tag,struct tx_desc *ptxdesc);
#endif //__RTL8188E_XMIT_H__

17
include/rtl8192c_cmd.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -22,7 +22,7 @@
enum cmd_msg_element_id
{
{
NONE_CMDMSG_EID,
AP_OFFLOAD_EID=0,
SET_PWRMODE_EID=1,
@ -49,13 +49,13 @@ struct cmd_msg_parm {
};
typedef struct _SETPWRMODE_PARM{
u8 Mode;
u8 SmartPS;
u8 Mode;
u8 SmartPS;
u8 BcnPassTime; // unit: 100ms
}SETPWRMODE_PARM, *PSETPWRMODE_PARM;
struct H2C_SS_RFOFF_PARAM{
u8 ROFOn; // 1: on, 0:off
u8 ROFOn; // 1: on, 0:off
u16 gpio_period; // unit: 1024 us
}__attribute__ ((packed));
@ -65,8 +65,8 @@ typedef struct JOINBSSRPT_PARM{
}JOINBSSRPT_PARM, *PJOINBSSRPT_PARM;
typedef struct _RSVDPAGE_LOC{
u8 LocProbeRsp;
u8 LocPsPoll;
u8 LocProbeRsp;
u8 LocPsPoll;
u8 LocNullData;
}RSVDPAGE_LOC, *PRSVDPAGE_LOC;
@ -98,7 +98,7 @@ void rtl8192c_set_p2p_ps_offload_cmd(struct adapter* padapter, u8 p2p_ps_state);
#ifdef CONFIG_IOL
typedef struct _IO_OFFLOAD_LOC{
u8 LocCmd;
u8 LocCmd;
}IO_OFFLOAD_LOC, *PIO_OFFLOAD_LOC;
int rtl8192c_IOL_exec_cmds_sync(struct adapter *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);
#endif //CONFIG_IOL
@ -113,4 +113,3 @@ u8 rtl8192c_reset_tsf(struct adapter *padapter, u8 reset_port);
#endif // CONFIG_TSF_RESET_OFFLOAD
#endif // __RTL8192C_CMD_H_

31
include/rtl8192c_dm.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -34,15 +34,15 @@
enum{
UP_LINK,
DOWN_LINK,
DOWN_LINK,
};
typedef enum _BT_Ant_NUM{
Ant_x2 = 0,
Ant_x2 = 0,
Ant_x1 = 1
} BT_Ant_NUM, *PBT_Ant_NUM;
typedef enum _BT_CoType{
BT_2Wire = 0,
BT_2Wire = 0,
BT_ISSC_3Wire = 1,
BT_Accel = 2,
BT_CSR_BC4 = 3,
@ -51,12 +51,12 @@ typedef enum _BT_CoType{
} BT_CoType, *PBT_CoType;
typedef enum _BT_CurState{
BT_OFF = 0,
BT_OFF = 0,
BT_ON = 1,
} BT_CurState, *PBT_CurState;
typedef enum _BT_ServiceType{
BT_SCO = 0,
BT_SCO = 0,
BT_A2DP = 1,
BT_HID = 2,
BT_HID_Idle = 3,
@ -69,7 +69,7 @@ typedef enum _BT_ServiceType{
} BT_ServiceType, *PBT_ServiceType;
typedef enum _BT_RadioShared{
BT_Radio_Shared = 0,
BT_Radio_Shared = 0,
BT_Radio_Individual = 1,
} BT_RadioShared, *PBT_RadioShared;
@ -116,7 +116,7 @@ struct btcoexist_priv {
#define IQK_BB_REG_NUM 9
#define HP_THERMAL_NUM 8
//###### duplicate code,will move to ODM #########
struct dm_priv
struct dm_priv
{
u8 DM_Type;
u8 DMFlag;
@ -141,7 +141,7 @@ struct dm_priv
PS_T DM_PSTable;
FALSE_ALARM_STATISTICS FalseAlmCnt;
//for rate adaptive, in fact, 88c/92c fw will handle this
u8 bUseRAMask;
RATE_ADAPTIVE RateAdaptive;
@ -150,11 +150,11 @@ struct dm_priv
u8 bDynamicTxPowerEnable;
u8 LastDTPLvl;
u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06
//for tx power tracking
u8 bTXPowerTracking;
u8 TXPowercount;
u8 bTXPowerTrackingInit;
u8 bTXPowerTrackingInit;
u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
u8 TM_Trigger;
@ -173,7 +173,7 @@ struct dm_priv
u8 bDPdone;
u8 bDPPathAOK;
u8 bDPPathBOK;
//for IQK
u32 RegC04;
u32 Reg874;
@ -221,10 +221,10 @@ struct dm_priv
//for Antenna diversity
#ifdef CONFIG_ANTENNA_DIVERSITY
// SWAT_T DM_SWAT_Table;
#endif
#endif
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
// _timer SwAntennaSwitchTimer;
/*
/*
u64 lastTxOkCnt;
u64 lastRxOkCnt;
u64 TXByteCnt_A;
@ -238,7 +238,7 @@ struct dm_priv
s32 OFDM_Pkt_Cnt;
u8 RSSI_Select;
// u8 DIG_Dynamic_MIN ;
// u8 DIG_Dynamic_MIN ;
//###### duplicate code,will move to ODM #########
// Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas
u8 INIDATA_RATE[32];
@ -260,4 +260,3 @@ void rtl8192c_InitHalDm( IN struct adapter *Adapter);
void rtl8192c_HalDmWatchDog(IN struct adapter *Adapter);
#endif //__HAL8190PCIDM_H__

20
include/rtl8192c_event.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -16,13 +16,11 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef _RTL8192C_EVENT_H_
#define _RTL8192C_EVENT_H_
#endif
******************************************************************************/
#ifndef _RTL8192C_EVENT_H_
#define _RTL8192C_EVENT_H_
#endif

185
include/rtl8192c_hal.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -38,7 +38,7 @@
#ifdef CONFIG_PCI_HCI
#define RTL819X_DEFAULT_RF_TYPE RF_2T2R
//#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
#define RTL819X_TOTAL_RF_PATH 2
@ -88,7 +88,7 @@
#define Rtl819XFwTSMCImageArray Rtl8192CEFwTSMCImgArray
#define Rtl819XFwUMCACutImageArray Rtl8192CEFwUMCACutImgArray
#define Rtl819XFwUMCBCutImageArray Rtl8192CEFwUMCBCutImgArray
// #define Rtl8723FwUMCImageArray Rtl8192CEFwUMC8723ImgArray
#define Rtl819XMAC_Array Rtl8192CEMAC_2T_Array
#define Rtl819XAGCTAB_2TArray Rtl8192CEAGCTAB_2TArray
@ -99,34 +99,34 @@
#define Rtl819XRadioA_1TArray Rtl8192CERadioA_1TArray
#define Rtl819XRadioB_2TArray Rtl8192CERadioB_2TArray
#define Rtl819XRadioB_1TArray Rtl8192CERadioB_1TArray
#define Rtl819XPHY_REG_Array_PG Rtl8192CEPHY_REG_Array_PG
#define Rtl819XPHY_REG_Array_MP Rtl8192CEPHY_REG_Array_MP
#define Rtl819XPHY_REG_Array_PG Rtl8192CEPHY_REG_Array_PG
#define Rtl819XPHY_REG_Array_MP Rtl8192CEPHY_REG_Array_MP
#define PHY_REG_2TArrayLength Rtl8192CEPHY_REG_2TArrayLength
#define PHY_REG_1TArrayLength Rtl8192CEPHY_REG_1TArrayLength
#define PHY_ChangeTo_1T1RArrayLength Rtl8192CEPHY_ChangeTo_1T1RArrayLength
#define PHY_ChangeTo_1T2RArrayLength Rtl8192CEPHY_ChangeTo_1T2RArrayLength
#define PHY_ChangeTo_2T2RArrayLength Rtl8192CEPHY_ChangeTo_2T2RArrayLength
#define PHY_REG_Array_PGLength Rtl8192CEPHY_REG_Array_PGLength
//#define PHY_REG_Array_PG_mCardLength Rtl8192CEPHY_REG_Array_PG_mCardLength
#define PHY_REG_Array_MPLength Rtl8192CEPHY_REG_Array_MPLength
#define PHY_REG_Array_MPLength Rtl8192CEPHY_REG_Array_MPLength
//#define PHY_REG_1T_mCardArrayLength Rtl8192CEPHY_REG_1T_mCardArrayLength
//#define PHY_REG_2T_mCardArrayLength Rtl8192CEPHY_REG_2T_mCardArrayLength
//#define PHY_REG_Array_PG_HPLength Rtl8192CEPHY_REG_Array_PG_HPLength
#define RadioA_2TArrayLength Rtl8192CERadioA_2TArrayLength
#define RadioB_2TArrayLength Rtl8192CERadioB_2TArrayLength
#define RadioA_1TArrayLength Rtl8192CERadioA_1TArrayLength
#define RadioB_1TArrayLength Rtl8192CERadioB_1TArrayLength
//#define RadioA_1T_mCardArrayLength Rtl8192CERadioA_1T_mCardArrayLength
//#define RadioB_1T_mCardArrayLength Rtl8192CERadioB_1T_mCardArrayLength
//#define RadioA_1T_HPArrayLength Rtl8192CERadioA_1T_HPArrayLength
#define RadioB_GM_ArrayLength Rtl8192CERadioB_GM_ArrayLength
#define MAC_2T_ArrayLength Rtl8192CEMAC_2T_ArrayLength
#define MACPHY_Array_PGLength Rtl8192CEMACPHY_Array_PGLength
#define AGCTAB_2TArrayLength Rtl8192CEAGCTAB_2TArrayLength
#define AGCTAB_1TArrayLength Rtl8192CEAGCTAB_1TArrayLength
//#define AGCTAB_1T_HPArrayLength Rtl8192CEAGCTAB_1T_HPArrayLength
#define PHY_REG_2TArrayLength Rtl8192CEPHY_REG_2TArrayLength
#define PHY_REG_1TArrayLength Rtl8192CEPHY_REG_1TArrayLength
#define PHY_ChangeTo_1T1RArrayLength Rtl8192CEPHY_ChangeTo_1T1RArrayLength
#define PHY_ChangeTo_1T2RArrayLength Rtl8192CEPHY_ChangeTo_1T2RArrayLength
#define PHY_ChangeTo_2T2RArrayLength Rtl8192CEPHY_ChangeTo_2T2RArrayLength
#define PHY_REG_Array_PGLength Rtl8192CEPHY_REG_Array_PGLength
//#define PHY_REG_Array_PG_mCardLength Rtl8192CEPHY_REG_Array_PG_mCardLength
#define PHY_REG_Array_MPLength Rtl8192CEPHY_REG_Array_MPLength
#define PHY_REG_Array_MPLength Rtl8192CEPHY_REG_Array_MPLength
//#define PHY_REG_1T_mCardArrayLength Rtl8192CEPHY_REG_1T_mCardArrayLength
//#define PHY_REG_2T_mCardArrayLength Rtl8192CEPHY_REG_2T_mCardArrayLength
//#define PHY_REG_Array_PG_HPLength Rtl8192CEPHY_REG_Array_PG_HPLength
#define RadioA_2TArrayLength Rtl8192CERadioA_2TArrayLength
#define RadioB_2TArrayLength Rtl8192CERadioB_2TArrayLength
#define RadioA_1TArrayLength Rtl8192CERadioA_1TArrayLength
#define RadioB_1TArrayLength Rtl8192CERadioB_1TArrayLength
//#define RadioA_1T_mCardArrayLength Rtl8192CERadioA_1T_mCardArrayLength
//#define RadioB_1T_mCardArrayLength Rtl8192CERadioB_1T_mCardArrayLength
//#define RadioA_1T_HPArrayLength Rtl8192CERadioA_1T_HPArrayLength
#define RadioB_GM_ArrayLength Rtl8192CERadioB_GM_ArrayLength
#define MAC_2T_ArrayLength Rtl8192CEMAC_2T_ArrayLength
#define MACPHY_Array_PGLength Rtl8192CEMACPHY_Array_PGLength
#define AGCTAB_2TArrayLength Rtl8192CEAGCTAB_2TArrayLength
#define AGCTAB_1TArrayLength Rtl8192CEAGCTAB_1TArrayLength
//#define AGCTAB_1T_HPArrayLength Rtl8192CEAGCTAB_1T_HPArrayLength
#elif defined(CONFIG_USB_HCI)
@ -140,7 +140,7 @@
#define RTL8192C_FW_UMC_IMG "rtl8192CU\\rtl8192cfwU.bin"
#define RTL8192C_FW_UMC_B_IMG "rtl8192CU\\rtl8192cfwU_B.bin"
//#define RTL819X_FW_BOOT_IMG "rtl8192CU\\boot.img"
//#define RTL819X_FW_BOOT_IMG "rtl8192CU\\boot.img"
//#define RTL819X_FW_MAIN_IMG "rtl8192CU\\main.img"
//#define RTL819X_FW_DATA_IMG "rtl8192CU\\data.img"
@ -148,7 +148,7 @@
#define RTL8188C_PHY_RADIO_A "rtl8188CU\\radio_a.txt"
#define RTL8188C_PHY_RADIO_B "rtl8188CU\\radio_b.txt"
#define RTL8188C_PHY_RADIO_A_mCard "rtl8192CU\\radio_a_1T_mCard.txt"
#define RTL8188C_PHY_RADIO_B_mCard "rtl8192CU\\radio_b_1T_mCard.txt"
#define RTL8188C_PHY_RADIO_B_mCard "rtl8192CU\\radio_b_1T_mCard.txt"
#define RTL8188C_PHY_RADIO_A_HP "rtl8192CU\\radio_a_1T_HP.txt"
#define RTL8188C_AGC_TAB "rtl8188CU\\AGC_TAB.txt"
#define RTL8188C_PHY_MACREG "rtl8188CU\\MACREG.txt"
@ -177,46 +177,46 @@
#define Rtl819XAGCTAB_1T_HPArray Rtl8192CUAGCTAB_1T_HPArray
#define Rtl819XPHY_REG_2TArray Rtl8192CUPHY_REG_2TArray
#define Rtl819XPHY_REG_1TArray Rtl8192CUPHY_REG_1TArray
#define Rtl819XPHY_REG_1T_mCardArray Rtl8192CUPHY_REG_1T_mCardArray
#define Rtl819XPHY_REG_2T_mCardArray Rtl8192CUPHY_REG_2T_mCardArray
#define Rtl819XPHY_REG_1T_mCardArray Rtl8192CUPHY_REG_1T_mCardArray
#define Rtl819XPHY_REG_2T_mCardArray Rtl8192CUPHY_REG_2T_mCardArray
#define Rtl819XPHY_REG_1T_HPArray Rtl8192CUPHY_REG_1T_HPArray
#define Rtl819XRadioA_2TArray Rtl8192CURadioA_2TArray
#define Rtl819XRadioA_1TArray Rtl8192CURadioA_1TArray
#define Rtl819XRadioA_1T_mCardArray Rtl8192CURadioA_1T_mCardArray
#define Rtl819XRadioA_1T_mCardArray Rtl8192CURadioA_1T_mCardArray
#define Rtl819XRadioB_2TArray Rtl8192CURadioB_2TArray
#define Rtl819XRadioB_1TArray Rtl8192CURadioB_1TArray
#define Rtl819XRadioB_1TArray Rtl8192CURadioB_1TArray
#define Rtl819XRadioB_1T_mCardArray Rtl8192CURadioB_1T_mCardArray
#define Rtl819XRadioA_1T_HPArray Rtl8192CURadioA_1T_HPArray
#define Rtl819XPHY_REG_Array_PG Rtl8192CUPHY_REG_Array_PG
#define Rtl819XPHY_REG_Array_PG_mCard Rtl8192CUPHY_REG_Array_PG_mCard
#define Rtl819XRadioA_1T_HPArray Rtl8192CURadioA_1T_HPArray
#define Rtl819XPHY_REG_Array_PG Rtl8192CUPHY_REG_Array_PG
#define Rtl819XPHY_REG_Array_PG_mCard Rtl8192CUPHY_REG_Array_PG_mCard
#define Rtl819XPHY_REG_Array_PG_HP Rtl8192CUPHY_REG_Array_PG_HP
#define Rtl819XPHY_REG_Array_MP Rtl8192CUPHY_REG_Array_MP
#define Rtl819XPHY_REG_Array_MP Rtl8192CUPHY_REG_Array_MP
#define PHY_REG_2TArrayLength Rtl8192CUPHY_REG_2TArrayLength
#define PHY_REG_1TArrayLength Rtl8192CUPHY_REG_1TArrayLength
#define PHY_ChangeTo_1T1RArrayLength Rtl8192CUPHY_ChangeTo_1T1RArrayLength
#define PHY_ChangeTo_1T2RArrayLength Rtl8192CUPHY_ChangeTo_1T2RArrayLength
#define PHY_ChangeTo_2T2RArrayLength Rtl8192CUPHY_ChangeTo_2T2RArrayLength
#define PHY_REG_Array_PGLength Rtl8192CUPHY_REG_Array_PGLength
#define PHY_REG_Array_PG_mCardLength Rtl8192CUPHY_REG_Array_PG_mCardLength
#define PHY_REG_Array_MPLength Rtl8192CUPHY_REG_Array_MPLength
#define PHY_REG_Array_MPLength Rtl8192CUPHY_REG_Array_MPLength
#define PHY_REG_1T_mCardArrayLength Rtl8192CUPHY_REG_1T_mCardArrayLength
#define PHY_REG_2T_mCardArrayLength Rtl8192CUPHY_REG_2T_mCardArrayLength
#define PHY_REG_Array_PG_HPLength Rtl8192CUPHY_REG_Array_PG_HPLength
#define RadioA_2TArrayLength Rtl8192CURadioA_2TArrayLength
#define RadioB_2TArrayLength Rtl8192CURadioB_2TArrayLength
#define RadioA_1TArrayLength Rtl8192CURadioA_1TArrayLength
#define RadioB_1TArrayLength Rtl8192CURadioB_1TArrayLength
#define RadioA_1T_mCardArrayLength Rtl8192CURadioA_1T_mCardArrayLength
#define RadioB_1T_mCardArrayLength Rtl8192CURadioB_1T_mCardArrayLength
#define RadioA_1T_HPArrayLength Rtl8192CURadioA_1T_HPArrayLength
#define RadioB_GM_ArrayLength Rtl8192CURadioB_GM_ArrayLength
#define MAC_2T_ArrayLength Rtl8192CUMAC_2T_ArrayLength
#define MACPHY_Array_PGLength Rtl8192CUMACPHY_Array_PGLength
#define AGCTAB_2TArrayLength Rtl8192CUAGCTAB_2TArrayLength
#define AGCTAB_1TArrayLength Rtl8192CUAGCTAB_1TArrayLength
#define AGCTAB_1T_HPArrayLength Rtl8192CUAGCTAB_1T_HPArrayLength
#define PHY_REG_2TArrayLength Rtl8192CUPHY_REG_2TArrayLength
#define PHY_REG_1TArrayLength Rtl8192CUPHY_REG_1TArrayLength
#define PHY_ChangeTo_1T1RArrayLength Rtl8192CUPHY_ChangeTo_1T1RArrayLength
#define PHY_ChangeTo_1T2RArrayLength Rtl8192CUPHY_ChangeTo_1T2RArrayLength
#define PHY_ChangeTo_2T2RArrayLength Rtl8192CUPHY_ChangeTo_2T2RArrayLength
#define PHY_REG_Array_PGLength Rtl8192CUPHY_REG_Array_PGLength
#define PHY_REG_Array_PG_mCardLength Rtl8192CUPHY_REG_Array_PG_mCardLength
#define PHY_REG_Array_MPLength Rtl8192CUPHY_REG_Array_MPLength
#define PHY_REG_Array_MPLength Rtl8192CUPHY_REG_Array_MPLength
#define PHY_REG_1T_mCardArrayLength Rtl8192CUPHY_REG_1T_mCardArrayLength
#define PHY_REG_2T_mCardArrayLength Rtl8192CUPHY_REG_2T_mCardArrayLength
#define PHY_REG_Array_PG_HPLength Rtl8192CUPHY_REG_Array_PG_HPLength
#define RadioA_2TArrayLength Rtl8192CURadioA_2TArrayLength
#define RadioB_2TArrayLength Rtl8192CURadioB_2TArrayLength
#define RadioA_1TArrayLength Rtl8192CURadioA_1TArrayLength
#define RadioB_1TArrayLength Rtl8192CURadioB_1TArrayLength
#define RadioA_1T_mCardArrayLength Rtl8192CURadioA_1T_mCardArrayLength
#define RadioB_1T_mCardArrayLength Rtl8192CURadioB_1T_mCardArrayLength
#define RadioA_1T_HPArrayLength Rtl8192CURadioA_1T_HPArrayLength
#define RadioB_GM_ArrayLength Rtl8192CURadioB_GM_ArrayLength
#define MAC_2T_ArrayLength Rtl8192CUMAC_2T_ArrayLength
#define MACPHY_Array_PGLength Rtl8192CUMACPHY_Array_PGLength
#define AGCTAB_2TArrayLength Rtl8192CUAGCTAB_2TArrayLength
#define AGCTAB_1TArrayLength Rtl8192CUAGCTAB_1TArrayLength
#define AGCTAB_1T_HPArrayLength Rtl8192CUAGCTAB_1T_HPArrayLength
#define PHY_REG_1T_HPArrayLength Rtl8192CUPHY_REG_1T_HPArrayLength
#endif
@ -381,15 +381,15 @@ typedef struct _TxPowerInfo{
#define EFUSE_MAP_LEN 128
#define EFUSE_MAX_SECTION 16
#define EFUSE_IC_ID_OFFSET 506 //For some inferiority IC purpose. added by Roger, 2009.09.02.
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN)
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN)
//
// <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
// 9bytes + 1byt + 5bytes and pre 1byte.
// For worst case:
// | 1byte|----8bytes----|1byte|--5bytes--|
// | 1byte|----8bytes----|1byte|--5bytes--|
// | | Reserved(14bytes) |
//
#define EFUSE_OOB_PROTECT_BYTES 15 // PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte.
#define EFUSE_OOB_PROTECT_BYTES 15 // PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte.
#define EFUSE_MAP_LEN_8723 256
@ -419,13 +419,13 @@ typedef enum _RT_MULTI_FUNC{
//
typedef enum _RT_POLARITY_CTL{
RT_POLARITY_LOW_ACT = 0,
RT_POLARITY_HIGH_ACT = 1,
RT_POLARITY_HIGH_ACT = 1,
}RT_POLARITY_CTL,*PRT_POLARITY_CTL;
// For RTL8723 regulator mode. by tynli. 2011.01.14.
typedef enum _RT_REGULATOR_MODE{
RT_SWITCHING_REGULATOR = 0,
RT_LDO_REGULATOR = 1,
RT_LDO_REGULATOR = 1,
}RT_REGULATOR_MODE,*PRT_REGULATOR_MODE;
enum c2h_id_8192c {
@ -460,7 +460,7 @@ struct hal_data_8192ce
u32 IntrMaskToSet[2];
u32 DisabledFunctions;
//current WIFI_PHY values
u32 ReceiveConfig;
u32 TransmitConfig;
@ -489,8 +489,8 @@ struct hal_data_8192ce
u16 EEPROMChannelPlan;
u16 EEPROMVersion;
u8 EEPROMChnlAreaTxPwrCCK[2][3];
u8 EEPROMChnlAreaTxPwrHT40_1S[2][3];
u8 EEPROMChnlAreaTxPwrCCK[2][3];
u8 EEPROMChnlAreaTxPwrHT40_1S[2][3];
u8 EEPROMChnlAreaTxPwrHT40_2SDiff[2][3];
u8 EEPROMPwrLimitHT20[3];
u8 EEPROMPwrLimitHT40[3];
@ -508,7 +508,7 @@ struct hal_data_8192ce
u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
// For power group
@ -517,11 +517,11 @@ struct hal_data_8192ce
u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff
BOOLEAN EepromOrEfuse;
BOOLEAN EepromOrEfuse;
u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes)
u8 EfuseUsedPercentage;
EFUSE_HAL EfuseHal;
#ifdef CONFIG_BT_COEXIST
struct btcoexist_priv bt_coexist;
#endif
@ -545,7 +545,7 @@ struct hal_data_8192ce
u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
//u32 TxPowerTrackControl;
u8 b1x1RecvCombine; // for 1T1R receive combining
u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo.
//vivi, for tx power tracking, 20080407
@ -556,9 +556,9 @@ struct hal_data_8192ce
u8 CurrentOfdm24GTxPwrIdx;
BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
u32 RfRegChnlVal[2];
//RDG enable
BOOLEAN bRDGEnable;
@ -571,8 +571,8 @@ struct hal_data_8192ce
u32 RegBcnCtrlVal;
u8 RegFwHwTxQCtrl;
u8 RegReg542;
u8 CurAntenna;
u8 CurAntenna;
//### ODM-DUPLICATE CODE ###
u8 AntDivCfg;
/*
@ -592,9 +592,9 @@ struct hal_data_8192ce
u32 OFDM_Ant2_Cnt;
#endif
*/
//### ODM-DUPLICATE CODE ###
//### ODM-DUPLICATE CODE ###
struct dm_priv dmpriv;
DM_ODM_T odmpriv;
DM_ODM_T odmpriv;
//_lock odm_stainfo_lock;
u8 bDumpRxPkt;//for debug
#ifdef DBG_CONFIG_ERROR_DETECT
@ -607,7 +607,7 @@ struct hal_data_8192ce
u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
u16 EfuseUsedBytes;
#ifdef CONFIG_P2P
struct P2P_PS_Offload_t p2p_ps_offload;
#endif //CONFIG_P2P
@ -682,7 +682,7 @@ struct hal_data_8192cu
u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
// For power group
@ -737,19 +737,19 @@ struct hal_data_8192cu
u32 RegBcnCtrlVal;
u8 RegFwHwTxQCtrl;
u8 RegReg542;
struct dm_priv dmpriv;
DM_ODM_T odmpriv;
DM_ODM_T odmpriv;
//_lock odm_stainfo_lock;
#ifdef DBG_CONFIG_ERROR_DETECT
struct sreset_priv srestpriv;
#endif
#endif
#ifdef CONFIG_BT_COEXIST
struct btcoexist_priv bt_coexist;
#endif
u8 CurAntenna;
u8 CurAntenna;
/*****ODM duplicate data********/
u8 AntDivCfg;
/*
@ -812,11 +812,11 @@ struct hal_data_8192cu
u16 EfuseUsedBytes;
BOOLEAN EepromOrEfuse;
BOOLEAN EepromOrEfuse;
u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes)
u8 EfuseUsedPercentage;
EFUSE_HAL EfuseHal;
#ifdef CONFIG_P2P
struct P2P_PS_Offload_t p2p_ps_offload;
@ -846,4 +846,3 @@ void rtl8192c_set_hal_ops(struct hal_ops *pHalFunc);
s32 c2h_id_filter_ccx_8192c(u8 id);
#endif

49
include/rtl8192c_led.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -16,27 +16,26 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8192C_LED_H_
#define __RTL8192C_LED_H_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
#ifdef CONFIG_USB_HCI
void rtl8192cu_InitSwLeds(struct adapter *padapter);
void rtl8192cu_DeInitSwLeds(struct adapter *padapter);
#endif
#ifdef CONFIG_PCI_HCI
void rtl8192ce_gen_RefreshLedState(struct adapter *Adapter);
void rtl8192ce_InitSwLeds(struct adapter *padapter);
void rtl8192ce_DeInitSwLeds(struct adapter *padapter);
#endif
#endif
******************************************************************************/
#ifndef __RTL8192C_LED_H_
#define __RTL8192C_LED_H_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
#ifdef CONFIG_USB_HCI
void rtl8192cu_InitSwLeds(struct adapter *padapter);
void rtl8192cu_DeInitSwLeds(struct adapter *padapter);
#endif
#ifdef CONFIG_PCI_HCI
void rtl8192ce_gen_RefreshLedState(struct adapter *Adapter);
void rtl8192ce_InitSwLeds(struct adapter *padapter);
void rtl8192ce_DeInitSwLeds(struct adapter *padapter);
#endif
#endif

5
include/rtl8192c_recv.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -34,7 +34,7 @@
#if defined(CONFIG_GSPI_HCI)
#define NR_RECVBUFF (32)
#elif defined(CONFIG_SDIO_HCI)
#define NR_RECVBUFF (8)
#define NR_RECVBUFF (8)
#else
#ifdef CONFIG_SINGLE_RECV_BUF
#define NR_RECVBUFF (1)
@ -144,4 +144,3 @@ void rtl8192c_translate_rx_signal_stuff(union recv_frame *precvframe, struct phy
void rtl8192c_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *pdesc);
#endif

149
include/rtl8192c_rf.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -16,77 +16,76 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/******************************************************************************
*
*
* Module: rtl8192c_rf.h ( Header File)
*
* Note: Collect every HAL RF type exter API or constant.
*
* Function:
*
* Export:
*
* Abbrev:
*
* History:
* Data Who Remark
*
* 09/25/2008 MHC Create initial version.
*
*
******************************************************************************/
#ifndef _RTL8192C_RF_H_
#define _RTL8192C_RF_H_
/* Check to see if the file has been included already. */
/*--------------------------Define Parameters-------------------------------*/
//
// For RF 6052 Series
//
#define RF6052_MAX_TX_PWR 0x3F
#define RF6052_MAX_REG 0x3F
#define RF6052_MAX_PATH 2
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*--------------------------Exported Function prototype---------------------*/
//
// RF RL6052 Series API
//
void rtl8192c_RF_ChangeTxPath( IN struct adapter *Adapter,
IN u16 DataRate);
void rtl8192c_PHY_RF6052SetBandwidth(
IN struct adapter * Adapter,
IN HT_CHANNEL_WIDTH Bandwidth);
VOID rtl8192c_PHY_RF6052SetCckTxPower(
IN struct adapter *Adapter,
IN u8* pPowerlevel);
VOID rtl8192c_PHY_RF6052SetOFDMTxPower(
IN struct adapter *Adapter,
IN u8* pPowerLevel,
IN u8 Channel);
int PHY_RF6052_Config8192C( IN struct adapter * Adapter );
/*--------------------------Exported Function prototype---------------------*/
#endif/* End of HalRf.h */
******************************************************************************/
/******************************************************************************
*
*
* Module: rtl8192c_rf.h ( Header File)
*
* Note: Collect every HAL RF type exter API or constant.
*
* Function:
*
* Export:
*
* Abbrev:
*
* History:
* Data Who Remark
*
* 09/25/2008 MHC Create initial version.
*
*
******************************************************************************/
#ifndef _RTL8192C_RF_H_
#define _RTL8192C_RF_H_
/* Check to see if the file has been included already. */
/*--------------------------Define Parameters-------------------------------*/
//
// For RF 6052 Series
//
#define RF6052_MAX_TX_PWR 0x3F
#define RF6052_MAX_REG 0x3F
#define RF6052_MAX_PATH 2
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*--------------------------Exported Function prototype---------------------*/
//
// RF RL6052 Series API
//
void rtl8192c_RF_ChangeTxPath( IN struct adapter *Adapter,
IN u16 DataRate);
void rtl8192c_PHY_RF6052SetBandwidth(
IN struct adapter * Adapter,
IN HT_CHANNEL_WIDTH Bandwidth);
VOID rtl8192c_PHY_RF6052SetCckTxPower(
IN struct adapter *Adapter,
IN u8* pPowerlevel);
VOID rtl8192c_PHY_RF6052SetOFDMTxPower(
IN struct adapter *Adapter,
IN u8* pPowerLevel,
IN u8 Channel);
int PHY_RF6052_Config8192C( IN struct adapter * Adapter );
/*--------------------------Exported Function prototype---------------------*/
#endif/* End of HalRf.h */

119
include/rtl8192c_spec.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -168,7 +168,7 @@
//
//-----------------------------------------------------
#define REG_PCIE_CTRL_REG 0x0300
#define REG_INT_MIG 0x0304 // Interrupt Migration
#define REG_INT_MIG 0x0304 // Interrupt Migration
#define REG_BCNQ_DESA 0x0308 // TX Beacon Descriptor Address
#define REG_HQ_DESA 0x0310 // TX High Queue Descriptor Address
#define REG_MGQ_DESA 0x0318 // TX Manage Queue Descriptor Address
@ -284,7 +284,7 @@
#define REG_ATIMWND 0x055A
#define REG_BCN_MAX_ERR 0x055D
#define REG_RXTSF_OFFSET_CCK 0x055E
#define REG_RXTSF_OFFSET_OFDM 0x055F
#define REG_RXTSF_OFFSET_OFDM 0x055F
#define REG_TSFTR 0x0560
#define REG_TSFTR1 0x0568
#define REG_INIT_TSFTR 0x0564
@ -453,14 +453,14 @@
#define InvalidBBRFValue 0x12345678
// Min Spacing related settings.
#define MAX_MSS_DENSITY_2T 0x13
#define MAX_MSS_DENSITY_1T 0x0A
#define MAX_MSS_DENSITY_2T 0x13
#define MAX_MSS_DENSITY_1T 0x0A
//----------------------------------------------------------------------------
// 8192C Cmd9346CR bits (Offset 0xA, 16bit)
//----------------------------------------------------------------------------
#define CmdEEPROM_En BIT5 // EEPROM enable when set 1
#define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346
#define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346
#define Cmd9346CR_9356SEL BIT4
#define AutoLoadEEPROM (CmdEEPROM_En|CmdEERPOMSEL)
#define AutoLoadEFUSE CmdEEPROM_En
@ -480,7 +480,7 @@
#define GPIO_MOD (REG_GPIO_PIN_CTRL+3)
//----------------------------------------------------------------------------
// 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits)
// 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits)
//----------------------------------------------------------------------------
/*
Network Type
@ -508,16 +508,16 @@ Default: 00b.
#define RRSR_RSC_LOWSUBCHNL 0x200000
#define RRSR_SHORT 0x800000
#define RRSR_1M BIT0
#define RRSR_2M BIT1
#define RRSR_5_5M BIT2
#define RRSR_11M BIT3
#define RRSR_6M BIT4
#define RRSR_9M BIT5
#define RRSR_12M BIT6
#define RRSR_18M BIT7
#define RRSR_24M BIT8
#define RRSR_36M BIT9
#define RRSR_48M BIT10
#define RRSR_2M BIT1
#define RRSR_5_5M BIT2
#define RRSR_11M BIT3
#define RRSR_6M BIT4
#define RRSR_9M BIT5
#define RRSR_12M BIT6
#define RRSR_18M BIT7
#define RRSR_24M BIT8
#define RRSR_36M BIT9
#define RRSR_48M BIT10
#define RRSR_54M BIT11
#define RRSR_MCS0 BIT12
#define RRSR_MCS1 BIT13
@ -527,7 +527,7 @@ Default: 00b.
#define RRSR_MCS5 BIT17
#define RRSR_MCS6 BIT18
#define RRSR_MCS7 BIT19
#define BRSR_AckShortPmb BIT23
#define BRSR_AckShortPmb BIT23
// CCK ACK: use Short Preamble or not
//----------------------------------------------------------------------------
@ -545,20 +545,20 @@ Default: 00b.
#define CAM_NOTVALID 0x0000
#define CAM_USEDK BIT5
#define CAM_CONTENT_COUNT 8
#define CAM_CONTENT_COUNT 8
#define CAM_NONE 0x0
#define CAM_WEP40 0x01
#define CAM_TKIP 0x02
#define CAM_AES 0x04
#define CAM_WEP104 0x05
#define TOTAL_CAM_ENTRY 32
#define HALF_CAM_ENTRY 16
#define HALF_CAM_ENTRY 16
#define CAM_CONFIG_USEDK _TRUE
#define CAM_CONFIG_NO_USEDK _FALSE
#define CAM_WRITE BIT16
#define CAM_READ 0x00000000
#define CAM_POLLINIG BIT31
@ -593,7 +593,7 @@ Default: 00b.
#define IMR_TIMEOUT2 BIT17 // Timeout interrupt 2
#define IMR_TIMEOUT1 BIT16 // Timeout interrupt 1
#define IMR_TXFOVW BIT15 // Transmit FIFO Overflow
#define IMR_PSTIMEOUT BIT14 // Power save time out interrupt
#define IMR_PSTIMEOUT BIT14 // Power save time out interrupt
#define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0
#define IMR_RXFOVW BIT12 // Receive FIFO Overflow
#define IMR_RDU BIT11 // Receive Descriptor Unavailable
@ -683,7 +683,7 @@ Default: 00b.
#define EEPROM_CID_TOSHIBA 0x4
#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25.
#define EEPROM_CID_QMI 0x0D
#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
#define RTL_EEPROM_ID 0x8129
@ -725,7 +725,7 @@ typedef enum _INTERFACE_SELECT_8192CPCIe{
#define EEPROM_HT40_MAX_PWR_OFFSET 0x6F
#define EEPROM_HT20_MAX_PWR_OFFSET 0x72
#define EEPROM_CHANNEL_PLAN 0x75
#define EEPROM_CHANNEL_PLAN 0x75
#define EEPROM_TSSI_A 0x76
#define EEPROM_TSSI_B 0x77
#define EEPROM_THERMAL_METER 0x78
@ -738,16 +738,16 @@ typedef enum _INTERFACE_SELECT_8192CPCIe{
#define EEPROM_NORMAL_BoardType EEPROM_RF_OPT1 //[7:5]
#endif
#endif
#ifdef CONFIG_USB_HCI
//should be renamed and moved to another file
typedef enum _BOARD_TYPE_8192CUSB{
BOARD_USB_DONGLE = 0, // USB dongle
BOARD_USB_High_PA = 1, // USB dongle with high power PA
BOARD_MINICARD = 2, // Minicard
BOARD_USB_SOLO = 3, // USB solo-Slim module
BOARD_USB_DONGLE = 0, // USB dongle
BOARD_USB_High_PA = 1, // USB dongle with high power PA
BOARD_MINICARD = 2, // Minicard
BOARD_USB_SOLO = 3, // USB solo-Slim module
BOARD_USB_COMBO = 4, // USB Combo-Slim module
} BOARD_TYPE_8192CUSB, *PBOARD_TYPE_8192CUSB;
@ -817,7 +817,7 @@ typedef enum _BOARD_TYPE_8192CUSB{
#define EEPROM_TxPowerCCK 0x5A // CCK Tx Power
// 2009/02/09 Cosa Add for SD3 requirement
// 2009/02/09 Cosa Add for SD3 requirement
#define EEPROM_TX_PWR_HT20_DIFF 0x6e// HT20 Tx Power Index Difference
#define DEFAULT_HT20_TXPWR_DIFF 2 // HT20<->40 default Tx Power Index Difference
#define EEPROM_TX_PWR_OFDM_DIFF 0x71// OFDM Tx Power Index Difference
@ -908,7 +908,7 @@ typedef enum _BOARD_TYPE_8192CUSB{
#define EEPROM_CID_DEFAULT 0x0
#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25.
@ -919,7 +919,7 @@ typedef enum _BOARD_TYPE_8192CUSB{
/*===================================================================
=====================================================================
Here the register defines are for 92C. When the define is as same with 92C,
Here the register defines are for 92C. When the define is as same with 92C,
we will use the 92C's define for the consistency
So the following defines for 92C is not entire!!!!!!
=====================================================================
@ -956,23 +956,23 @@ Current IOREG MAP
#define RCR_ACF BIT12 //Accept control type frame
#define RCR_ADF BIT11 //Accept data type frame
#define RCR_AICV BIT9 //Accept ICV error packet
#define RCR_ACRC32 BIT8 //Accept CRC32 error packet
#define RCR_ACRC32 BIT8 //Accept CRC32 error packet
#define RCR_CBSSID_BCN BIT7 //Accept BSSID match packet (Rx beacon, probe rsp)
#define RCR_CBSSID_DATA BIT6 //Accept BSSID match packet (Data)
#define RCR_CBSSID RCR_CBSSID_DATA //Accept BSSID match packet
#define RCR_APWRMGT BIT5 //Accept power management packet
#define RCR_ADD3 BIT4 //Accept address 3 match packet
#define RCR_AB BIT3 //Accept broadcast packet
#define RCR_AM BIT2 //Accept multicast packet
#define RCR_AB BIT3 //Accept broadcast packet
#define RCR_AM BIT2 //Accept multicast packet
#define RCR_APM BIT1 //Accept physical match packet
#define RCR_AAP BIT0 //Accept all unicast packet
#define RCR_AAP BIT0 //Accept all unicast packet
#define RCR_MXDMA_OFFSET 8
#define RCR_FIFO_OFFSET 13
//============================================================================
// 8192c USB specific Regsiter Offset and Content definition,
// 8192c USB specific Regsiter Offset and Content definition,
// 2009.08.18, added by vivi. for merge 92c and 92C into one driver
//============================================================================
//#define APS_FSMCO 0x0004 same with 92Ce
@ -1003,7 +1003,7 @@ Current IOREG MAP
#define InvalidBBRFValue 0x12345678
//============================================================================
// 8192C Regsiter Bit and Content definition
// 8192C Regsiter Bit and Content definition
//============================================================================
//-----------------------------------------------------
//
@ -1094,16 +1094,16 @@ Current IOREG MAP
//2 9346CR
#define EEDO BIT(0)
#define EEDI BIT(1)
#define EESK BIT(2)
#define EECS BIT(3)
//#define EERPROMSEL BIT(4)
//#define EEPROM_EN BIT(5)
#define EEDO BIT(0)
#define EEDI BIT(1)
#define EESK BIT(2)
#define EECS BIT(3)
//#define EERPROMSEL BIT(4)
//#define EEPROM_EN BIT(5)
#define BOOT_FROM_EEPROM BIT(4)
#define EEPROM_EN BIT(5)
#define EEM0 BIT(6)
#define EEM1 BIT(7)
#define EEM0 BIT(6)
#define EEM1 BIT(7)
//2 AFE_MISC
@ -1216,7 +1216,7 @@ Current IOREG MAP
#define EFUSE_ACCESS_ON 0x69 // For RTL8723 only.
#define EFUSE_ACCESS_OFF 0x00 // For RTL8723 only.
//2 PWR_DATA
//2 PWR_DATA
//2 CAL_TIMER
@ -1247,10 +1247,10 @@ Current IOREG MAP
//2 GPIO_INTM
//2 LEDCFG
#define LED0PL BIT(4)
#define LED0PL BIT(4)
#define LED0DIS BIT(7)
#define LED1DIS BIT(15)
#define LED1PL BIT(12)
#define LED1PL BIT(12)
#define SECCAM_CLR BIT(30)
@ -1303,7 +1303,7 @@ Current IOREG MAP
//2REG_GPIO_OUTSTS (For RTL8723 only)
#define EFS_HCI_SEL (BIT(0)|BIT(1))
#define PAD_HCI_SEL (BIT(2)|BIT(3))
#define HCI_SEL (BIT(4)|BIT(5))
#define HCI_SEL (BIT(4)|BIT(5))
#define PKG_SEL_HCI BIT(6)
#define FEN_GPS BIT(7)
#define FEN_BT BIT(8)
@ -1397,12 +1397,12 @@ Current IOREG MAP
#define HQSEL_HIQ BIT(5)
// For normal driver, 0x10C
#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 )
#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 )
#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 )
#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 )
#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 )
#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 )
#define QUEUE_LOW 1
#define QUEUE_NORMAL 2
@ -1787,4 +1787,3 @@ Current IOREG MAP
#include "basic_types.h"
#endif

31
include/rtl8192c_sreset.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -16,18 +16,17 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef _RTL8192C_SRESET_C_
#define _RTL8192C_SRESET_C_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#include <rtw_sreset.h>
#ifdef DBG_CONFIG_ERROR_DETECT
extern void rtl8192c_sreset_xmit_status_check(struct adapter *padapter);
extern void rtl8192c_sreset_linked_status_check(struct adapter *padapter);
#endif
#endif
******************************************************************************/
#ifndef _RTL8192C_SRESET_C_
#define _RTL8192C_SRESET_C_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#include <rtw_sreset.h>
#ifdef DBG_CONFIG_ERROR_DETECT
extern void rtl8192c_sreset_xmit_status_check(struct adapter *padapter);
extern void rtl8192c_sreset_linked_status_check(struct adapter *padapter);
#endif
#endif

5
include/rtl8192c_xmit.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -32,7 +32,7 @@
#define BMC BIT(24)
#define LSG BIT(26)
#define FSG BIT(27)
#define OWN BIT(31)
#define OWN BIT(31)
//OFFSET 4
@ -162,4 +162,3 @@ s32 rtl8192ce_hostap_mgnt_xmit_entry(struct adapter *padapter, _pkt *pkt);
#endif
#endif

8
include/rtl8192d_cmd.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -22,7 +22,7 @@
//--------------------------------------------
//3 Host Message Box
//3 Host Message Box
//--------------------------------------------
// User Define Message [31:8]
@ -63,7 +63,7 @@ struct P2P_PS_Offload_t {
// Description: Determine the types of H2C commands that are the same in driver and Fw.
// Fisrt constructed by tynli. 2009.10.09.
typedef enum _RTL8192D_H2C_CMD
typedef enum _RTL8192D_H2C_CMD
{
H2C_AP_OFFLOAD = 0, /*0*/
H2C_SETPWRMODE = 1, /*1*/
@ -99,5 +99,3 @@ void rtl8192d_set_p2p_ps_offload_cmd(struct adapter* padapter, u8 p2p_ps_state);
#endif //CONFIG_P2P
#endif

31
include/rtl8192d_dm.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -28,7 +28,7 @@
//============================================================
enum{
UP_LINK,
DOWN_LINK,
DOWN_LINK,
};
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
@ -51,13 +51,13 @@ enum{
#define IQK_Matrix_REG_NUM 8
#define IQK_Matrix_Settings_NUM 1+24+21
//###### duplicate code,will move to ODM #########
struct dm_priv
struct dm_priv
{
u8 DM_Type;
u8 DMFlag;
u8 InitDMFlag;
u32 InitODMFlag;
//* Upper and Lower Signal threshold for Rate Adaptive*/
int UndecoratedSmoothedPWDB;
int EntryMinUndecoratedSmoothedPWDB;
@ -73,22 +73,22 @@ struct dm_priv
PS_T DM_PSTable;
FALSE_ALARM_STATISTICS FalseAlmCnt;
FALSE_ALARM_STATISTICS FalseAlmCnt;
//for rate adaptive, in fact, 88c/92c fw will handle this
u8 bUseRAMask;
RATE_ADAPTIVE RateAdaptive;
*/
//for High Power
u8 bDynamicTxPowerEnable;
u8 LastDTPLvl;
u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06
//for tx power tracking
u8 bTXPowerTracking;
u8 TXPowercount;
u8 bTXPowerTrackingInit;
u8 bTXPowerTrackingInit;
u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
u8 TM_Trigger;
@ -111,7 +111,7 @@ struct dm_priv
u8 bAPKdone;
u8 bAPKThermalMeterIgnore;
u32 RegA24;
//for IQK
u32 Reg874;
u32 RegC08;
@ -125,22 +125,22 @@ struct dm_priv
u32 IQK_BB_backup[IQK_BB_REG_NUM];
u8 bCCKinCH14;
char CCK_index;
//u8 Record_CCK_20Mindex;
//u8 Record_CCK_40Mindex;
char OFDM_index[2];
BOOLEAN bDPKdone[2];
u8 PowerIndex_backup[6];
//for Antenna diversity
//#ifdef CONFIG_ANTENNA_DIVERSITY
//SWAT_T DM_SWAT_Table;
//#endif
//Neil Chen----2011--06--23-----
//3 Path Diversity
//3 Path Diversity
BOOLEAN bPathDiv_Enable; //For 92D Non-interrupt Antenna Diversity by Neil ,add by wl.2011.07.19
BOOLEAN RSSI_test;
s32 RSSI_sum_A;
@ -152,7 +152,7 @@ struct dm_priv
//for TxPwrTracking
int RegE94;
int RegE9C;
int RegE9C;
int RegEB4;
int RegEBC;
#if MP_DRIVER == 1
@ -180,4 +180,3 @@ void rtl8192d_InitHalDm(IN struct adapter *Adapter);
void rtl8192d_HalDmWatchDog(IN struct adapter *Adapter);
#endif //__HAL8190PCIDM_H__

111
include/rtl8192d_hal.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -33,14 +33,14 @@
#include "../hal/OUTSRC/odm_precomp.h"
#ifdef CONFIG_PCI_HCI
#include <pci_ops.h>
#include <pci_ops.h>
#define RTL819X_DEFAULT_RF_TYPE RF_2T2R
//---------------------------------------------------------------------
// RTL8192DE From file
//---------------------------------------------------------------------
#define RTL8192D_FW_IMG "rtl8192DE\\rtl8192dfw.bin"
#define RTL8192D_FW_IMG "rtl8192DE\\rtl8192dfw.bin"
#define RTL8192D_PHY_REG "rtl8192DE\\PHY_REG.txt"
#define RTL8192D_PHY_REG_PG "rtl8192DE\\PHY_REG_PG.txt"
@ -50,7 +50,7 @@
#define RTL8192D_AGC_TAB_2G "rtl8192DE\\AGC_TAB_2G.txt"
#define RTL8192D_AGC_TAB_5G "rtl8192DE\\AGC_TAB_5G.txt"
#define RTL8192D_PHY_RADIO_A "rtl8192DE\\radio_a.txt"
#define RTL8192D_PHY_RADIO_B "rtl8192DE\\radio_b.txt"
#define RTL8192D_PHY_RADIO_B "rtl8192DE\\radio_b.txt"
#define RTL8192D_PHY_RADIO_A_intPA "rtl8192DE\\radio_a_intPA.txt"
#define RTL8192D_PHY_RADIO_B_intPA "rtl8192DE\\radio_b_intPA.txt"
#define RTL8192D_PHY_MACREG "rtl8192DE\\MAC_REG.txt"
@ -59,16 +59,16 @@
// RTL8192DE From header
//---------------------------------------------------------------------
// Fw Array
#define Rtl8192D_FwImageArray Rtl8192DEFwImgArray
#define Rtl8192D_FwImageArray Rtl8192DEFwImgArray
// MAC/BB/PHY Array
#define Rtl8192D_MAC_Array Rtl8192DEMAC_2T_Array
#define Rtl8192D_AGCTAB_Array Rtl8192DEAGCTAB_Array
#define Rtl8192D_AGCTAB_5GArray Rtl8192DEAGCTAB_5GArray
#define Rtl8192D_AGCTAB_2GArray Rtl8192DEAGCTAB_2GArray
#define Rtl8192D_AGCTAB_2TArray Rtl8192DEAGCTAB_2TArray
#define Rtl8192D_AGCTAB_1TArray Rtl8192DEAGCTAB_1TArray
#define Rtl8192D_PHY_REG_2TArray Rtl8192DEPHY_REG_2TArray
#define Rtl8192D_AGCTAB_2TArray Rtl8192DEAGCTAB_2TArray
#define Rtl8192D_AGCTAB_1TArray Rtl8192DEAGCTAB_1TArray
#define Rtl8192D_PHY_REG_2TArray Rtl8192DEPHY_REG_2TArray
#define Rtl8192D_PHY_REG_1TArray Rtl8192DEPHY_REG_1TArray
#define Rtl8192D_PHY_REG_Array_PG Rtl8192DEPHY_REG_Array_PG
#define Rtl8192D_PHY_REG_Array_MP Rtl8192DEPHY_REG_Array_MP
@ -77,7 +77,7 @@
#define Rtl8192D_RadioB_2TArray Rtl8192DERadioB_2TArray
#define Rtl8192D_RadioB_1TArray Rtl8192DERadioB_1TArray
#define Rtl8192D_RadioA_2T_intPAArray Rtl8192DERadioA_2T_intPAArray
#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DERadioB_2T_intPAArray
#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DERadioB_2T_intPAArray
// Array length
#define Rtl8192D_FwImageArrayLength Rtl8192DEImgArrayLength
@ -86,7 +86,7 @@
#define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DEAGCTAB_2GArrayLength
#define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DEAGCTAB_2TArrayLength
#define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DEAGCTAB_1TArrayLength
#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DEAGCTAB_ArrayLength
#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DEAGCTAB_ArrayLength
#define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DEPHY_REG_2TArrayLength
#define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DEPHY_REG_1TArrayLength
#define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DEPHY_REG_Array_PGLength
@ -98,7 +98,7 @@
#elif defined(CONFIG_USB_HCI)
#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
//---------------------------------------------------------------------
@ -108,8 +108,8 @@
#define RTL8192D_PHY_REG "rtl8192DU\\PHY_REG.txt"
#define RTL8192D_PHY_REG_PG "rtl8192DU\\PHY_REG_PG.txt"
#define RTL8192D_PHY_REG_MP "rtl8192DU\\PHY_REG_MP.txt"
#define RTL8192D_PHY_REG_MP "rtl8192DU\\PHY_REG_MP.txt"
#define RTL8192D_AGC_TAB "rtl8192DU\\AGC_TAB.txt"
#define RTL8192D_AGC_TAB_2G "rtl8192DU\\AGC_TAB_2G.txt"
#define RTL8192D_AGC_TAB_5G "rtl8192DU\\AGC_TAB_5G.txt"
@ -124,16 +124,16 @@
//---------------------------------------------------------------------
// Fw Array
#define Rtl8192D_FwImageArray Rtl8192DUFwImgArray
#define Rtl8192D_FwImageArray Rtl8192DUFwImgArray
// MAC/BB/PHY Array
#define Rtl8192D_MAC_Array Rtl8192DUMAC_2T_Array
#define Rtl8192D_AGCTAB_Array Rtl8192DUAGCTAB_Array
#define Rtl8192D_AGCTAB_5GArray Rtl8192DUAGCTAB_5GArray
#define Rtl8192D_AGCTAB_2GArray Rtl8192DUAGCTAB_2GArray
#define Rtl8192D_AGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
#define Rtl8192D_AGCTAB_1TArray Rtl8192DUAGCTAB_1TArray
#define Rtl8192D_PHY_REG_2TArray Rtl8192DUPHY_REG_2TArray
#define Rtl8192D_AGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
#define Rtl8192D_AGCTAB_1TArray Rtl8192DUAGCTAB_1TArray
#define Rtl8192D_PHY_REG_2TArray Rtl8192DUPHY_REG_2TArray
#define Rtl8192D_PHY_REG_1TArray Rtl8192DUPHY_REG_1TArray
#define Rtl8192D_PHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
#define Rtl8192D_PHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
@ -142,8 +142,8 @@
#define Rtl8192D_RadioB_2TArray Rtl8192DURadioB_2TArray
#define Rtl8192D_RadioB_1TArray Rtl8192DURadioB_1TArray
#define Rtl8192D_RadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
// Array length
#define Rtl8192D_FwImageArrayLength Rtl8192DUImgArrayLength
#define Rtl8192D_MAC_ArrayLength Rtl8192DUMAC_2T_ArrayLength
@ -151,14 +151,14 @@
#define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DUAGCTAB_2GArrayLength
#define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DUAGCTAB_2TArrayLength
#define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DUAGCTAB_1TArrayLength
#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DUAGCTAB_ArrayLength
#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DUAGCTAB_ArrayLength
#define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DUPHY_REG_2TArrayLength
#define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DUPHY_REG_1TArrayLength
#define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DUPHY_REG_Array_PGLength
#define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DUPHY_REG_Array_MPLength
#define Rtl8192D_RadioA_2TArrayLength Rtl8192DURadioA_2TArrayLength
#define Rtl8192D_RadioB_2TArrayLength Rtl8192DURadioB_2TArrayLength
#define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DURadioA_2T_intPAArrayLength
#define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DURadioA_2T_intPAArrayLength
#define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DURadioB_2T_intPAArrayLength
// The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24.
@ -171,12 +171,12 @@
#define Rtl819XPHY_REG_1TArray Rtl8192DUPHY_REG_1TArray
#define Rtl819XRadioA_2TArray Rtl8192DURadioA_2TArray
#define Rtl819XRadioA_1TArray Rtl8192DURadioA_1TArray
#define Rtl819XRadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
#define Rtl819XRadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
#define Rtl819XRadioB_2TArray Rtl8192DURadioB_2TArray
#define Rtl819XRadioB_1TArray Rtl8192DURadioB_1TArray
#define Rtl819XRadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
#define Rtl819XPHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
#define Rtl819XPHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
#define Rtl819XRadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
#define Rtl819XPHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
#define Rtl819XPHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
#define Rtl819XAGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
#define Rtl819XAGCTAB_1TArray Rtl8192DUAGCTAB_1TArray*/
@ -187,7 +187,7 @@
#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
//
// Check if FW header exists. We do not consider the lower 4 bits in this case.
// Check if FW header exists. We do not consider the lower 4 bits in this case.
// By tynli. 2009.12.04.
//
#define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
@ -251,7 +251,7 @@ typedef struct _RT_8192D_FIRMWARE_HDR {//8-byte alinment required
#define BCN_DMA_ATIME_INT_TIME 0x02
typedef enum _BT_CoType{
BT_2Wire = 0,
BT_2Wire = 0,
BT_ISSC_3Wire = 1,
BT_Accel = 2,
BT_CSR = 3,
@ -260,12 +260,12 @@ typedef enum _BT_CoType{
} BT_CoType, *PBT_CoType;
typedef enum _BT_CurState{
BT_OFF = 0,
BT_OFF = 0,
BT_ON = 1,
} BT_CurState, *PBT_CurState;
typedef enum _BT_ServiceType{
BT_SCO = 0,
BT_SCO = 0,
BT_A2DP = 1,
BT_HID = 2,
BT_HID_Idle = 3,
@ -277,7 +277,7 @@ typedef enum _BT_ServiceType{
} BT_ServiceType, *PBT_ServiceType;
typedef enum _BT_RadioShared{
BT_Radio_Shared = 0,
BT_Radio_Shared = 0,
BT_Radio_Individual = 1,
} BT_RadioShared, *PBT_RadioShared;
@ -289,7 +289,7 @@ typedef struct _BT_COEXIST_STR{
u8 BT_CUR_State; //0:on, 1:off
u8 BT_Ant_isolation; //0:good, 1:bad
u8 BT_PapeCtrl; //0:SW, 1:SW/HW dynamic
u8 BT_Service;
u8 BT_Service;
u8 BT_RadioSharedType;
u8 Ratio_Tx;
u8 Ratio_PRI;
@ -410,12 +410,12 @@ typedef struct _TxPowerInfo{
// 9bytes + 1byt + 5bytes and pre 1byte.
// For worst case:
// | 2byte|----8bytes----|1byte|--7bytes--| //92D
#define EFUSE_OOB_PROTECT_BYTES 18 // PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte.
#define EFUSE_OOB_PROTECT_BYTES 18 // PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte.
typedef enum _PA_MODE {
PA_MODE_EXTERNAL = 0x00,
PA_MODE_INTERNAL_SP3T = 0x01,
PA_MODE_INTERNAL_SPDT = 0x02
PA_MODE_INTERNAL_SPDT = 0x02
} PA_MODE;
/* Copy from rtl8192c */
@ -437,8 +437,8 @@ enum c2h_id_8192d {
#ifdef CONFIG_PCI_HCI
struct hal_data_8192de
{
HAL_VERSION VersionID;
// add for 92D Phy mode/mac/Band mode
HAL_VERSION VersionID;
// add for 92D Phy mode/mac/Band mode
MACPHY_MODE_8192D MacPhyMode92D;
BAND_TYPE CurrentBandType92D; //0:2.4G, 1:5G
BAND_TYPE BandSet92D;
@ -498,7 +498,7 @@ struct hal_data_8192de
u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER_2G];
u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
// For power group
@ -543,7 +543,7 @@ struct hal_data_8192de
u8 CurrentOfdm24GTxPwrIdx;
BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
u32 RfRegChnlVal[2];
@ -568,7 +568,7 @@ struct hal_data_8192de
#else
//regc80、regc94、regc4c、regc88、regc9c、regc14、regca0、regc1c、regc78
u4Byte IQKMatrixReg[IQK_Matrix_REG_NUM];
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; // 1->2G,24->5G 20M channel,21->5G 40M channel.
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; // 1->2G,24->5G 20M channel,21->5G 40M channel.
#endif
//for host message to fw
@ -581,9 +581,9 @@ struct hal_data_8192de
u8 RegFwHwTxQCtrl;
u8 RegReg542;
u8 RegCR_1;
struct dm_priv dmpriv;
DM_ODM_T odmpriv;
DM_ODM_T odmpriv;
//_lock odm_stainfo_lock;
u8 bInterruptMigration;
@ -595,8 +595,8 @@ struct hal_data_8192de
u16 RegRRSR;
u16 EfuseUsedBytes;
BOOLEAN EepromOrEfuse;
BOOLEAN EepromOrEfuse;
u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes)
u8 EfuseUsedPercentage;
EFUSE_HAL EfuseHal;
@ -630,7 +630,7 @@ VOID UpdateInterruptMask8192DE(struct adapter *Adapter, u32 AddMSR, u32 RemoveMS
//should be renamed and moved to another file
typedef enum _INTERFACE_SELECT_8192DUSB{
INTF_SEL0_USB = 0, // USB
INTF_SEL0_USB = 0, // USB
INTF_SEL1_MINICARD = 1, // Minicard
INTF_SEL2_EKB_PRO = 2, // Eee keyboard proprietary
INTF_SEL3_PRO = 3, // Customized proprietary
@ -640,9 +640,9 @@ typedef INTERFACE_SELECT_8192DUSB INTERFACE_SELECT_USB;
struct hal_data_8192du
{
HAL_VERSION VersionID;
HAL_VERSION VersionID;
// add for 92D Phy mode/mac/Band mode
// add for 92D Phy mode/mac/Band mode
MACPHY_MODE_8192D MacPhyMode92D;
BAND_TYPE CurrentBandType92D; //0:2.4G, 1:5G
BAND_TYPE BandSet92D;
@ -687,7 +687,7 @@ struct hal_data_8192du
u16 EEPROMSVID;
u16 EEPROMSDID;
u8 EEPROMCustomerID;
u8 EEPROMSubCustomerID;
u8 EEPROMSubCustomerID;
u8 EEPROMRegulatory;
u8 EEPROMThermalMeter;
@ -698,7 +698,7 @@ struct hal_data_8192du
u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER_2G];
u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
// For power group
@ -743,7 +743,7 @@ struct hal_data_8192du
u8 CurrentOfdm24GTxPwrIdx;
BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
u32 RfRegChnlVal[2];
@ -769,7 +769,7 @@ struct hal_data_8192du
#else
//regc80、regc94、regc4c、regc88、regc9c、regc14、regca0、regc1c、regc78
u4Byte IQKMatrixReg[IQK_Matrix_REG_NUM];
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; // 1->2G,24->5G 20M channel,21->5G 40M channel.
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; // 1->2G,24->5G 20M channel,21->5G 40M channel.
#endif
//for host message to fw
@ -780,11 +780,11 @@ struct hal_data_8192du
u32 RegBcnCtrlVal;
u8 RegTxPause;
u8 RegFwHwTxQCtrl;
u8 RegReg542;
u8 RegReg542;
u8 RegCR_1;
struct dm_priv dmpriv;
DM_ODM_T odmpriv;
DM_ODM_T odmpriv;
//_lock odm_stainfo_lock;
u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
@ -820,8 +820,8 @@ struct hal_data_8192du
u16 RegRRSR;
u16 EfuseUsedBytes;
BOOLEAN EepromOrEfuse;
BOOLEAN EepromOrEfuse;
u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes)
u8 EfuseUsedPercentage;
EFUSE_HAL EfuseHal;
@ -851,4 +851,3 @@ VOID PHY_SetPowerOnFor8192D(struct adapter *Adapter);
void rtl8192d_free_hal_data(struct adapter * padapter);
void rtl8192d_set_hal_ops(struct hal_ops *pHalFunc);
#endif

51
include/rtl8192d_led.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -16,28 +16,27 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8192D_LED_H_
#define __RTL8192D_LED_H_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
#ifdef CONFIG_USB_HCI
void rtl8192du_InitSwLeds(struct adapter *padapter);
void rtl8192du_DeInitSwLeds(struct adapter *padapter);
#endif
#ifdef CONFIG_PCI_HCI
void rtl8192de_gen_RefreshLedState(struct adapter *Adapter);
void rtl8192de_InitSwLeds(struct adapter *padapter);
void rtl8192de_DeInitSwLeds(struct adapter *padapter);
#endif
#endif
******************************************************************************/
#ifndef __RTL8192D_LED_H_
#define __RTL8192D_LED_H_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
#ifdef CONFIG_USB_HCI
void rtl8192du_InitSwLeds(struct adapter *padapter);
void rtl8192du_DeInitSwLeds(struct adapter *padapter);
#endif
#ifdef CONFIG_PCI_HCI
void rtl8192de_gen_RefreshLedState(struct adapter *Adapter);
void rtl8192de_InitSwLeds(struct adapter *padapter);
void rtl8192de_DeInitSwLeds(struct adapter *padapter);
#endif
#endif

3
include/rtl8192d_recv.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -136,4 +136,3 @@ void rtl8192d_translate_rx_signal_stuff(union recv_frame *precvframe, struct phy
void rtl8192d_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *pdesc);
#endif

159
include/rtl8192d_rf.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -16,82 +16,81 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/******************************************************************************
*
*
* Module: rtl8192d_rf.h ( Header File)
*
* Note: Collect every HAL RF type exter API or constant.
*
* Function:
*
* Export:
*
* Abbrev:
*
* History:
* Data Who Remark
*
* 09/25/2008 MHC Create initial version.
*
*
******************************************************************************/
#ifndef _RTL8192D_RF_H_
#define _RTL8192D_RF_H_
/* Check to see if the file has been included already. */
/*--------------------------Define Parameters-------------------------------*/
//
// For RF 6052 Series
//
#define RF6052_MAX_TX_PWR 0x3F
#define RF6052_MAX_REG 0x3F
#define RF6052_MAX_PATH 2
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*--------------------------Exported Function prototype---------------------*/
//
// RF RL6052 Series API
//
void rtl8192d_RF_ChangeTxPath( IN struct adapter *Adapter,
IN u16 DataRate);
void rtl8192d_PHY_RF6052SetBandwidth(
IN struct adapter * Adapter,
IN HT_CHANNEL_WIDTH Bandwidth);
VOID rtl8192d_PHY_RF6052SetCckTxPower(
IN struct adapter *Adapter,
IN u8* pPowerlevel);
VOID rtl8192d_PHY_RF6052SetOFDMTxPower(
IN struct adapter *Adapter,
IN u8* pPowerLevel,
IN u8 Channel);
int PHY_RF6052_Config8192D( IN struct adapter * Adapter );
BOOLEAN rtl8192d_PHY_EnableAnotherPHY(IN struct adapter *Adapter, IN BOOLEAN bMac0);
void rtl8192d_PHY_PowerDownAnotherPHY(IN struct adapter *Adapter, IN BOOLEAN bMac0);
/*--------------------------Exported Function prototype---------------------*/
#endif/* End of HalRf.h */
******************************************************************************/
/******************************************************************************
*
*
* Module: rtl8192d_rf.h ( Header File)
*
* Note: Collect every HAL RF type exter API or constant.
*
* Function:
*
* Export:
*
* Abbrev:
*
* History:
* Data Who Remark
*
* 09/25/2008 MHC Create initial version.
*
*
******************************************************************************/
#ifndef _RTL8192D_RF_H_
#define _RTL8192D_RF_H_
/* Check to see if the file has been included already. */
/*--------------------------Define Parameters-------------------------------*/
//
// For RF 6052 Series
//
#define RF6052_MAX_TX_PWR 0x3F
#define RF6052_MAX_REG 0x3F
#define RF6052_MAX_PATH 2
/*--------------------------Define Parameters-------------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export global variable----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export Marco Definition---------------------------*/
/*--------------------------Exported Function prototype---------------------*/
//
// RF RL6052 Series API
//
void rtl8192d_RF_ChangeTxPath( IN struct adapter *Adapter,
IN u16 DataRate);
void rtl8192d_PHY_RF6052SetBandwidth(
IN struct adapter * Adapter,
IN HT_CHANNEL_WIDTH Bandwidth);
VOID rtl8192d_PHY_RF6052SetCckTxPower(
IN struct adapter *Adapter,
IN u8* pPowerlevel);
VOID rtl8192d_PHY_RF6052SetOFDMTxPower(
IN struct adapter *Adapter,
IN u8* pPowerLevel,
IN u8 Channel);
int PHY_RF6052_Config8192D( IN struct adapter * Adapter );
BOOLEAN rtl8192d_PHY_EnableAnotherPHY(IN struct adapter *Adapter, IN BOOLEAN bMac0);
void rtl8192d_PHY_PowerDownAnotherPHY(IN struct adapter *Adapter, IN BOOLEAN bMac0);
/*--------------------------Exported Function prototype---------------------*/
#endif/* End of HalRf.h */

147
include/rtl8192d_spec.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -91,14 +91,14 @@
#define REG_SYS_CFG 0x00F0
#define REG_MAC_PHY_CTRL_NORMAL 0x00f8
#define REG_MAC0 0x0081
#define REG_MAC1 0x0053
#define FW_MAC0_ready 0x18
#define FW_MAC1_ready 0x1A
#define MAC0_ON BIT7
#define MAC1_ON BIT0
#define mac0_ready BIT0
#define mac1_ready BIT0
#define REG_MAC0 0x0081
#define REG_MAC1 0x0053
#define FW_MAC0_ready 0x18
#define FW_MAC1_ready 0x1A
#define MAC0_ON BIT7
#define MAC1_ON BIT0
#define mac0_ready BIT0
#define mac1_ready BIT0
//-----------------------------------------------------
@ -177,7 +177,7 @@
//
//-----------------------------------------------------
#define REG_PCIE_CTRL_REG 0x0300
#define REG_INT_MIG 0x0304 // Interrupt Migration
#define REG_INT_MIG 0x0304 // Interrupt Migration
#define REG_BCNQ_DESA 0x0308 // TX Beacon Descriptor Address
#define REG_HQ_DESA 0x0310 // TX High Queue Descriptor Address
#define REG_MGQ_DESA 0x0318 // TX Manage Queue Descriptor Address
@ -189,7 +189,7 @@
#define REG_DBI 0x0348 // Backdoor REG for Access Configuration
//sherry added for DBI Read/Write 20091126
#define REG_DBI_WDATA 0x0348 // Backdoor REG for Access Configuration
#define REG_DBI_RDATA 0x034C //Backdoor REG for Access Configuration
#define REG_DBI_RDATA 0x034C //Backdoor REG for Access Configuration
#define REG_DBI_CTRL 0x0350 //Backdoor REG for Access Configuration
#define REG_DBI_FLAG 0x0352 //Backdoor REG for Access Configuration#define REG_MDIO 0x0354 // MDIO for Access PCIE PHY
#define REG_MDIO 0x0354 // MDIO for Access PCIE PHY
@ -300,7 +300,7 @@
#define REG_USTIME_TSF 0x055C
#define REG_BCN_MAX_ERR 0x055D
#define REG_RXTSF_OFFSET_CCK 0x055E
#define REG_RXTSF_OFFSET_OFDM 0x055F
#define REG_RXTSF_OFFSET_OFDM 0x055F
#define REG_TSFTR 0x0560
#define REG_TSFTR1 0x0568
#define REG_INIT_TSFTR 0x0564
@ -394,7 +394,7 @@
#define REG_USB_AGG_TO 0xFE5C
#define REG_USB_AGG_TH 0xFE5D
// for 92DU high_Queue low_Queue Normal_Queue select
// for 92DU high_Queue low_Queue Normal_Queue select
#define REG_USB_High_NORMAL_Queue_Select_MAC0 0xFE44
//#define REG_USB_LOW_Queue_Select_MAC0 0xFE45
#define REG_USB_High_NORMAL_Queue_Select_MAC1 0xFE47
@ -443,7 +443,7 @@
#define MACIDR0 REG_MACID // MAC ID Register, Offset 0x0050-0x0053
#define MACIDR4 (REG_MACID + 4) // MAC ID Register, Offset 0x0054-0x0055
#define PBP REG_PBP
#define PBP REG_PBP
// Redifine MACID register, to compatible prior ICs.
#define IDR0 MACIDR0
@ -463,20 +463,20 @@
#define UnusedRegister 0x1BF
#define DCAM UnusedRegister
#define PSR UnusedRegister
#define BBAddr UnusedRegister
#define BBAddr UnusedRegister
#define PhyDataR UnusedRegister
#define InvalidBBRFValue 0x12345678
// Min Spacing related settings.
#define MAX_MSS_DENSITY_2T 0x13
#define MAX_MSS_DENSITY_1T 0x0A
#define MAX_MSS_DENSITY_2T 0x13
#define MAX_MSS_DENSITY_1T 0x0A
//----------------------------------------------------------------------------
// 8192C Cmd9346CR bits (Offset 0xA, 16bit)
//----------------------------------------------------------------------------
#define CmdEEPROM_En BIT5 // EEPROM enable when set 1
#define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346
#define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346
#define Cmd9346CR_9356SEL BIT4
#define AutoLoadEEPROM (CmdEEPROM_En|CmdEERPOMSEL)
#define AutoLoadEFUSE CmdEEPROM_En
@ -496,7 +496,7 @@
//----------------------------------------------------------------------------
// 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits)
// 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits)
//----------------------------------------------------------------------------
/*
Network Type
@ -524,16 +524,16 @@ Default: 00b.
#define RRSR_RSC_LOWSUBCHNL 0x200000
#define RRSR_SHORT 0x800000
#define RRSR_1M BIT0
#define RRSR_2M BIT1
#define RRSR_5_5M BIT2
#define RRSR_11M BIT3
#define RRSR_6M BIT4
#define RRSR_9M BIT5
#define RRSR_12M BIT6
#define RRSR_18M BIT7
#define RRSR_24M BIT8
#define RRSR_36M BIT9
#define RRSR_48M BIT10
#define RRSR_2M BIT1
#define RRSR_5_5M BIT2
#define RRSR_11M BIT3
#define RRSR_6M BIT4
#define RRSR_9M BIT5
#define RRSR_12M BIT6
#define RRSR_18M BIT7
#define RRSR_24M BIT8
#define RRSR_36M BIT9
#define RRSR_48M BIT10
#define RRSR_54M BIT11
#define RRSR_MCS0 BIT12
#define RRSR_MCS1 BIT13
@ -543,7 +543,7 @@ Default: 00b.
#define RRSR_MCS5 BIT17
#define RRSR_MCS6 BIT18
#define RRSR_MCS7 BIT19
#define BRSR_AckShortPmb BIT23
#define BRSR_AckShortPmb BIT23
// CCK ACK: use Short Preamble or not
//----------------------------------------------------------------------------
@ -561,7 +561,7 @@ Default: 00b.
#define CAM_NOTVALID 0x0000
#define CAM_USEDK BIT5
#define CAM_CONTENT_COUNT 8
#define CAM_CONTENT_COUNT 8
#define CAM_NONE 0x0
#define CAM_WEP40 0x01
@ -572,11 +572,11 @@ Default: 00b.
#define TOTAL_CAM_ENTRY 32
#define HALF_CAM_ENTRY 16
#define HALF_CAM_ENTRY 16
#define CAM_CONFIG_USEDK _TRUE
#define CAM_CONFIG_NO_USEDK _FALSE
#define CAM_WRITE BIT16
#define CAM_READ 0x00000000
#define CAM_POLLINIG BIT31
@ -611,7 +611,7 @@ Default: 00b.
#define IMR_TIMEOUT2 BIT17 // Timeout interrupt 2
#define IMR_TIMEOUT1 BIT16 // Timeout interrupt 1
#define IMR_TXFOVW BIT15 // Transmit FIFO Overflow
#define IMR_PSTIMEOUT BIT14 // Power save time out interrupt
#define IMR_PSTIMEOUT BIT14 // Power save time out interrupt
#define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0
#define IMR_RXFOVW BIT12 // Receive FIFO Overflow
#define IMR_RDU BIT11 // Receive Descriptor Unavailable
@ -651,10 +651,10 @@ Default: 00b.
// Default Value for EEPROM or EFUSE!!!
//
#define EEPROM_Default_TSSI 0x0
#define EEPROM_Default_TxPowerDiff 0x0
#define EEPROM_Default_CrystalCap 0x0 //92D default 0x0
#define EEPROM_Default_BoardType 0x02 // Default: 2X2, RTL8192CE(QFPN68)
#define EEPROM_Default_TxPower 0x1010
#define EEPROM_Default_TxPowerDiff 0x0
#define EEPROM_Default_CrystalCap 0x0 //92D default 0x0
#define EEPROM_Default_BoardType 0x02 // Default: 2X2, RTL8192CE(QFPN68)
#define EEPROM_Default_TxPower 0x1010
#define EEPROM_Default_HT2T_TxPwr 0x10
#define EEPROM_Default_LegacyHTTxPowerDiff 0x4
@ -666,17 +666,17 @@ Default: 00b.
#define EEPROM_Default_TxPowerLevel_5G 0x22
#define EEPROM_Default_HT40_2SDiff 0x0
#define EEPROM_Default_HT20_Diff 2 // HT20<->40 default Tx Power Index Difference
#define EEPROM_Default_HT20_Diff 2 // HT20<->40 default Tx Power Index Difference
#define EEPROM_Default_LegacyHTTxPowerDiff 0x4 //OFDM Tx Power index diff
#define EEPROM_Default_HT40_PwrMaxOffset 0
#define EEPROM_Default_HT20_PwrMaxOffset 0
#define EEPROM_Default_HT40_PwrMaxOffset 0
#define EEPROM_Default_HT20_PwrMaxOffset 0
// For debug
#define EEPROM_Default_PID 0x1234
#define EEPROM_Default_VID 0x5678
#define EEPROM_Default_CustomerID 0xAB
#define EEPROM_Default_SubCustomerID 0xCD
#define EEPROM_Default_Version 0
#define EEPROM_Default_PID 0x1234
#define EEPROM_Default_VID 0x5678
#define EEPROM_Default_CustomerID 0xAB
#define EEPROM_Default_SubCustomerID 0xCD
#define EEPROM_Default_Version 0
#define EEPROM_Default_externalPA_C9 0x00
#define EEPROM_Default_externalPA_CC 0xFF
@ -704,11 +704,11 @@ Default: 00b.
#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
#define EEPROM_CID_DEFAULT 0x0
#define EEPROM_CID_TOSHIBA 0x4
#define EEPROM_CID_DEFAULT 0x0
#define EEPROM_CID_TOSHIBA 0x4
#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25.
#define EEPROM_CID_QMI 0x0D
#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
#define RTL8192_EEPROM_ID 0x8129
@ -767,7 +767,7 @@ Default: 00b.
#define EEPROM_HT40_MAX_PWR_OFFSET_5GH 0xB5
#define EEPROM_HT20_MAX_PWR_OFFSET_5GH 0xB8
#define EEPROM_CHANNEL_PLAN 0xBB // Map of supported channels.
#define EEPROM_CHANNEL_PLAN 0xBB // Map of supported channels.
#define EEPROM_IQK_DELTA 0xBC
#define EEPROM_LCK_DELTA 0xBC
#define EEPROM_XTAL_K 0xBD //[7:5]
@ -792,7 +792,7 @@ Default: 00b.
#define EEPROM_DEF_PART_NO 0x3FD //Byte
#define EEPROME_CHIP_VERSION_L 0x3FF
#define EEPROME_CHIP_VERSION_H 0x3FE
#endif
#endif
#ifdef CONFIG_USB_HCI
#define RTL8190_EEPROM_ID 0x8129 // 0-1
@ -846,7 +846,7 @@ Default: 00b.
#define EEPROM_HT40_MAX_PWR_OFFSET_5GH 0xB5
#define EEPROM_HT20_MAX_PWR_OFFSET_5GH 0xB8
#define EEPROM_CHANNEL_PLAN 0xBB // Map of supported channels.
#define EEPROM_CHANNEL_PLAN 0xBB // Map of supported channels.
#define EEPROM_TEST_CHANNEL_PLAN 0xBB
#define EEPROM_IQK_DELTA 0xBC
#define EEPROM_LCK_DELTA 0xBC
@ -946,7 +946,7 @@ Default: 00b.
#define EEPROM_CID_DEFAULT 0x0
#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25.
@ -957,7 +957,7 @@ Default: 00b.
/*===================================================================
=====================================================================
Here the register defines are for 92C. When the define is as same with 92C,
Here the register defines are for 92C. When the define is as same with 92C,
we will use the 92C's define for the consistency
So the following defines for 92C is not entire!!!!!!
=====================================================================
@ -993,23 +993,23 @@ Current IOREG MAP
#define RCR_ACF BIT12 //Accept control type frame
#define RCR_ADF BIT11 //Accept data type frame
#define RCR_AICV BIT9 //Accept ICV error packet
#define RCR_ACRC32 BIT8 //Accept CRC32 error packet
#define RCR_ACRC32 BIT8 //Accept CRC32 error packet
#define RCR_CBSSID_BCN BIT7 //Accept BSSID match packet (Rx beacon, probe rsp)
#define RCR_CBSSID_DATA BIT6 //Accept BSSID match packet (Data)
#define RCR_CBSSID RCR_CBSSID_DATA //Accept BSSID match packet
#define RCR_APWRMGT BIT5 //Accept power management packet
#define RCR_ADD3 BIT4 //Accept address 3 match packet
#define RCR_AB BIT3 //Accept broadcast packet
#define RCR_AM BIT2 //Accept multicast packet
#define RCR_AB BIT3 //Accept broadcast packet
#define RCR_AM BIT2 //Accept multicast packet
#define RCR_APM BIT1 //Accept physical match packet
#define RCR_AAP BIT0 //Accept all unicast packet
#define RCR_AAP BIT0 //Accept all unicast packet
#define RCR_MXDMA_OFFSET 8
#define RCR_FIFO_OFFSET 13
//============================================================================
// 8192c USB specific Regsiter Offset and Content definition,
// 8192c USB specific Regsiter Offset and Content definition,
// 2009.08.18, added by vivi. for merge 92c and 92C into one driver
//============================================================================
//#define APS_FSMCO 0x0004 same with 92Ce
@ -1040,7 +1040,7 @@ Current IOREG MAP
#define InvalidBBRFValue 0x12345678
//============================================================================
// 8192C Regsiter Bit and Content definition
// 8192C Regsiter Bit and Content definition
//============================================================================
//-----------------------------------------------------
//
@ -1230,11 +1230,11 @@ Current IOREG MAP
#define EF_PD BIT(19)
#define EF_FLAG BIT(31)
//2 EFUSE_TEST
//2 EFUSE_TEST
#define EF_TRPT BIT(7)
#define LDOE25_EN BIT(31)
//2 PWR_DATA
//2 PWR_DATA
//2 CAL_TIMER
@ -1264,8 +1264,8 @@ Current IOREG MAP
//2 GPIO_INTM
//2 LEDCFG
#define LED0PL BIT(4)
#define LED1PL BIT(12)
#define LED0PL BIT(4)
#define LED1PL BIT(12)
#define LED0DIS BIT(7)
#define SECCAM_CLR BIT(30)
@ -1387,12 +1387,12 @@ Current IOREG MAP
#define HQSEL_HIQ BIT(5)
// For normal driver, 0x10C
#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 )
#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 )
#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 )
#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 )
#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 )
#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 )
#define QUEUE_LOW 1
#define QUEUE_NORMAL 2
@ -1695,8 +1695,8 @@ Current IOREG MAP
#define SCR_RxDecEnable BIT(3) //Enable Rx Decryption
#define SCR_SKByA2 BIT(4) //Search kEY BY A2
#define SCR_NoSKMC BIT(5) //No Key Search Multicast
#define SCR_TXBCUSEDK BIT(6) // Force Tx Broadcast packets Use Default Key
#define SCR_RXBCUSEDK BIT(7) // Force Rx Broadcast packets Use Default Key
#define SCR_TXBCUSEDK BIT(6) // Force Tx Broadcast packets Use Default Key
#define SCR_RXBCUSEDK BIT(7) // Force Rx Broadcast packets Use Default Key
//vivi added for new cam search flow, 20091028
#ifdef HW_EN_DE_CRYPTION_FOR_NEW_CAM_SEARCH_FLOW
@ -1758,4 +1758,3 @@ Current IOREG MAP
#include "basic_types.h"
#endif

5
include/rtl8192d_xmit.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -32,7 +32,7 @@
#define BMC BIT(24)
#define LSG BIT(26)
#define FSG BIT(27)
#define OWN BIT(31)
#define OWN BIT(31)
//OFFSET 4
@ -178,4 +178,3 @@ s32 rtl8192de_hostap_mgnt_xmit_entry(struct adapter *padapter, _pkt *pkt);
#endif

33
include/rtw_android.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -17,7 +17,7 @@
*
*
******************************************************************************/
#ifndef __RTW_ANDROID_H__
#define __RTW_ANDROID_H__
@ -25,28 +25,28 @@
#include <linux/netdevice.h>
enum ANDROID_WIFI_CMD {
ANDROID_WIFI_CMD_START,
ANDROID_WIFI_CMD_STOP,
ANDROID_WIFI_CMD_START,
ANDROID_WIFI_CMD_STOP,
ANDROID_WIFI_CMD_SCAN_ACTIVE,
ANDROID_WIFI_CMD_SCAN_PASSIVE,
ANDROID_WIFI_CMD_RSSI,
ANDROID_WIFI_CMD_SCAN_PASSIVE,
ANDROID_WIFI_CMD_RSSI,
ANDROID_WIFI_CMD_LINKSPEED,
ANDROID_WIFI_CMD_RXFILTER_START,
ANDROID_WIFI_CMD_RXFILTER_STOP,
ANDROID_WIFI_CMD_RXFILTER_ADD,
ANDROID_WIFI_CMD_RXFILTER_STOP,
ANDROID_WIFI_CMD_RXFILTER_ADD,
ANDROID_WIFI_CMD_RXFILTER_REMOVE,
ANDROID_WIFI_CMD_BTCOEXSCAN_START,
ANDROID_WIFI_CMD_BTCOEXSCAN_STOP,
ANDROID_WIFI_CMD_BTCOEXMODE,
ANDROID_WIFI_CMD_SETSUSPENDOPT,
ANDROID_WIFI_CMD_P2P_DEV_ADDR,
ANDROID_WIFI_CMD_SETFWPATH,
ANDROID_WIFI_CMD_SETBAND,
ANDROID_WIFI_CMD_GETBAND,
ANDROID_WIFI_CMD_COUNTRY,
ANDROID_WIFI_CMD_P2P_DEV_ADDR,
ANDROID_WIFI_CMD_SETFWPATH,
ANDROID_WIFI_CMD_SETBAND,
ANDROID_WIFI_CMD_GETBAND,
ANDROID_WIFI_CMD_COUNTRY,
ANDROID_WIFI_CMD_P2P_SET_NOA,
ANDROID_WIFI_CMD_P2P_GET_NOA,
ANDROID_WIFI_CMD_P2P_SET_PS,
ANDROID_WIFI_CMD_P2P_GET_NOA,
ANDROID_WIFI_CMD_P2P_SET_PS,
ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE,
#ifdef PNO_SUPPORT
ANDROID_WIFI_CMD_PNOSSIDCLR_SET,
@ -61,7 +61,7 @@ enum ANDROID_WIFI_CMD {
ANDROID_WIFI_CMD_WFD_ENABLE,
ANDROID_WIFI_CMD_WFD_DISABLE,
ANDROID_WIFI_CMD_WFD_SET_TCPPORT,
ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT,
ANDROID_WIFI_CMD_WFD_SET_DEVTYPE,
@ -87,4 +87,3 @@ static void rtw_android_wifictrl_func_del(void) {}
#endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */
#endif //__RTW_ANDROID_H__

130
include/rtw_ap.h
View file

@ -1,65 +1,65 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTW_AP_H_
#define __RTW_AP_H_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#ifdef CONFIG_AP_MODE
//external function
extern void rtw_indicate_sta_assoc_event(struct adapter *padapter, struct sta_info *psta);
extern void rtw_indicate_sta_disassoc_event(struct adapter *padapter, struct sta_info *psta);
void init_mlme_ap_info(struct adapter *padapter);
void free_mlme_ap_info(struct adapter *padapter);
//void update_BCNTIM(struct adapter *padapter);
void rtw_add_bcn_ie(struct adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len);
void rtw_remove_bcn_ie(struct adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index);
void update_beacon(struct adapter *padapter, u8 ie_id, u8 *oui, u8 tx);
void add_RATid(struct adapter *padapter, struct sta_info *psta, u8 rssi_level);
void expire_timeout_chk(struct adapter *padapter);
void update_sta_info_apmode(struct adapter *padapter, struct sta_info *psta);
int rtw_check_beacon_data(struct adapter *padapter, u8 *pbuf, int len);
void rtw_ap_restore_network(struct adapter *padapter);
void rtw_set_macaddr_acl(struct adapter *padapter, int mode);
int rtw_acl_add_sta(struct adapter *padapter, u8 *addr);
int rtw_acl_remove_sta(struct adapter *padapter, u8 *addr);
#ifdef CONFIG_NATIVEAP_MLME
void associated_clients_update(struct adapter *padapter, u8 updated);
void bss_cap_update_on_sta_join(struct adapter *padapter, struct sta_info *psta);
u8 bss_cap_update_on_sta_leave(struct adapter *padapter, struct sta_info *psta);
void sta_info_update(struct adapter *padapter, struct sta_info *psta);
void ap_sta_info_defer_update(struct adapter *padapter, struct sta_info *psta);
u8 ap_free_sta(struct adapter *padapter, struct sta_info *psta, bool active, u16 reason);
int rtw_sta_flush(struct adapter *padapter);
int rtw_ap_inform_ch_switch(struct adapter *padapter, u8 new_ch, u8 ch_offset);
void start_ap_mode(struct adapter *padapter);
void stop_ap_mode(struct adapter *padapter);
#endif
#endif //end of CONFIG_AP_MODE
#endif
void update_bmc_sta(struct adapter *padapter);
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTW_AP_H_
#define __RTW_AP_H_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#ifdef CONFIG_AP_MODE
//external function
extern void rtw_indicate_sta_assoc_event(struct adapter *padapter, struct sta_info *psta);
extern void rtw_indicate_sta_disassoc_event(struct adapter *padapter, struct sta_info *psta);
void init_mlme_ap_info(struct adapter *padapter);
void free_mlme_ap_info(struct adapter *padapter);
//void update_BCNTIM(struct adapter *padapter);
void rtw_add_bcn_ie(struct adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len);
void rtw_remove_bcn_ie(struct adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index);
void update_beacon(struct adapter *padapter, u8 ie_id, u8 *oui, u8 tx);
void add_RATid(struct adapter *padapter, struct sta_info *psta, u8 rssi_level);
void expire_timeout_chk(struct adapter *padapter);
void update_sta_info_apmode(struct adapter *padapter, struct sta_info *psta);
int rtw_check_beacon_data(struct adapter *padapter, u8 *pbuf, int len);
void rtw_ap_restore_network(struct adapter *padapter);
void rtw_set_macaddr_acl(struct adapter *padapter, int mode);
int rtw_acl_add_sta(struct adapter *padapter, u8 *addr);
int rtw_acl_remove_sta(struct adapter *padapter, u8 *addr);
#ifdef CONFIG_NATIVEAP_MLME
void associated_clients_update(struct adapter *padapter, u8 updated);
void bss_cap_update_on_sta_join(struct adapter *padapter, struct sta_info *psta);
u8 bss_cap_update_on_sta_leave(struct adapter *padapter, struct sta_info *psta);
void sta_info_update(struct adapter *padapter, struct sta_info *psta);
void ap_sta_info_defer_update(struct adapter *padapter, struct sta_info *psta);
u8 ap_free_sta(struct adapter *padapter, struct sta_info *psta, bool active, u16 reason);
int rtw_sta_flush(struct adapter *padapter);
int rtw_ap_inform_ch_switch(struct adapter *padapter, u8 new_ch, u8 ch_offset);
void start_ap_mode(struct adapter *padapter);
void stop_ap_mode(struct adapter *padapter);
#endif
#endif //end of CONFIG_AP_MODE
#endif
void update_bmc_sta(struct adapter *padapter);

7
include/rtw_br_ext.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -21,7 +21,7 @@
#define _RTW_BR_EXT_H_
#if 1 // rtw_wifi_driver
#define CL_IPV6_PASS 1
#define CL_IPV6_PASS 1
#define MACADDRLEN 6
#define _DEBUG_ERR DBG_8192C
#define _DEBUG_INFO //DBG_8192C
@ -49,7 +49,7 @@ struct nat25_network_db_entry
atomic_t use_count;
unsigned char macAddr[6];
unsigned long ageing_timer;
unsigned char networkAddr[MAX_NETWORK_ADDR_LEN];
unsigned char networkAddr[MAX_NETWORK_ADDR_LEN];
};
enum NAT25_METHOD {
@ -74,4 +74,3 @@ void nat25_db_cleanup(struct adapter *priv);
void netdev_br_init(struct net_device *netdev);
#endif // _RTW_BR_EXT_H_

635
include/rtw_bt_mp.h
View file

@ -1,318 +1,317 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTW_BT_MP_H
#define __RTW_BT_MP_H
#include <osdep_service.h>
#include <drv_types.h>
#include <rtw_mp.h>
#if(MP_DRIVER == 1)
#pragma pack(1)
// definition for BT_UP_OP_BT_READY
#define MP_BT_NOT_READY 0
#define MP_BT_READY 1
// definition for BT_UP_OP_BT_SET_MODE
typedef enum _MP_BT_MODE{
MP_BT_MODE_RF_TXRX_TEST_MODE = 0,
MP_BT_MODE_BT20_DUT_TEST_MODE = 1,
MP_BT_MODE_BT40_DIRECT_TEST_MODE = 2,
MP_BT_MODE_CONNECT_TEST_MODE = 3,
MP_BT_MODE_MAX
}MP_BT_MODE,*PMP_BT_MODE;
// definition for BT_UP_OP_BT_SET_TX_RX_PARAMETER
typedef struct _BT_TXRX_PARAMETERS{
u1Byte txrxChannel;
u4Byte txrxTxPktCnt;
u1Byte txrxTxPktInterval;
u1Byte txrxPayloadType;
u1Byte txrxPktType;
u2Byte txrxPayloadLen;
u4Byte txrxPktHeader;
u1Byte txrxWhitenCoeff;
u1Byte txrxBdaddr[6];
u1Byte txrxTxGainIndex;
} BT_TXRX_PARAMETERS, *PBT_TXRX_PARAMETERS;
// txrxPktType
typedef enum _MP_BT_PKT_TYPE{
MP_BT_PKT_DH1 = 0,
MP_BT_PKT_DH3 = 1,
MP_BT_PKT_DH5 = 2,
MP_BT_PKT_2DH1 = 3,
MP_BT_PKT_2DH3 = 4,
MP_BT_PKT_2DH5 = 5,
MP_BT_PKT_3DH1 = 6,
MP_BT_PKT_3DH3 = 7,
MP_BT_PKT_3DH5 = 8,
MP_BT_PKT_LE = 9,
MP_BT_PKT_MAX
}MP_BT_PKT_TYPE,*PMP_BT_PKT_TYPE;
// txrxPayloadType
typedef enum _MP_BT_PAYLOAD_TYPE{
MP_BT_PAYLOAD_01010101 = 0,
MP_BT_PAYLOAD_ALL_1 = 1,
MP_BT_PAYLOAD_ALL_0 = 2,
MP_BT_PAYLOAD_11110000 = 3,
MP_BT_PAYLOAD_PRBS9 = 4,
MP_BT_PAYLOAD_MAX
}MP_BT_PAYLOAD_TYPE,*PMP_BT_PAYLOAD_TYPE;
// definition for BT_UP_OP_BT_TEST_CTRL
typedef enum _MP_BT_TEST_CTRL{
MP_BT_TEST_STOP_ALL_TESTS = 0,
MP_BT_TEST_START_RX_TEST = 1,
MP_BT_TEST_START_PACKET_TX_TEST = 2,
MP_BT_TEST_START_CONTINUOUS_TX_TEST = 3,
MP_BT_TEST_START_INQUIRY_SCAN_TEST = 4,
MP_BT_TEST_START_PAGE_SCAN_TEST = 5,
MP_BT_TEST_START_INQUIRY_PAGE_SCAN_TEST = 6,
MP_BT_TEST_START_LEGACY_CONNECT_TEST = 7,
MP_BT_TEST_START_LE_CONNECT_TEST_INITIATOR = 8,
MP_BT_TEST_START_LE_CONNECT_TEST_ADVERTISER = 9,
MP_BT_TEST_MAX
}MP_BT_TEST_CTRL,*PMP_BT_TEST_CTRL;
typedef enum _RTL_EXT_C2H_EVT
{
EXT_C2H_WIFI_FW_ACTIVE_RSP = 0,
EXT_C2H_TRIG_BY_BT_FW = 1,
MAX_EXT_C2HEVENT
}RTL_EXT_C2H_EVT;
// return status definition to the user layer
typedef enum _BT_CTRL_STATUS{
BT_STATUS_SUCCESS = 0x00, // Success
BT_STATUS_BT_OP_SUCCESS = 0x01, // bt fw op execution success
BT_STATUS_H2C_SUCCESS = 0x02, // H2c success
BT_STATUS_H2C_TIMTOUT = 0x03, // H2c timeout
BT_STATUS_H2C_BT_NO_RSP = 0x04, // H2c sent, bt no rsp
BT_STATUS_C2H_SUCCESS = 0x05, // C2h success
BT_STATUS_C2H_REQNUM_MISMATCH = 0x06, // bt fw wrong rsp
BT_STATUS_OPCODE_U_VERSION_MISMATCH = 0x07, // Upper layer OP code version mismatch.
BT_STATUS_OPCODE_L_VERSION_MISMATCH = 0x08, // Lower layer OP code version mismatch.
BT_STATUS_UNKNOWN_OPCODE_U = 0x09, // Unknown Upper layer OP code
BT_STATUS_UNKNOWN_OPCODE_L = 0x0a, // Unknown Lower layer OP code
BT_STATUS_PARAMETER_FORMAT_ERROR_U = 0x0b, // Wrong parameters sent by upper layer.
BT_STATUS_PARAMETER_FORMAT_ERROR_L = 0x0c, // bt fw parameter format is not consistency
BT_STATUS_PARAMETER_OUT_OF_RANGE_U = 0x0d, // uppery layer parameter value is out of range
BT_STATUS_PARAMETER_OUT_OF_RANGE_L = 0x0e, // bt fw parameter value is out of range
BT_STATUS_UNKNOWN_STATUS_L = 0x0f, // bt returned an defined status code
BT_STATUS_UNKNOWN_STATUS_H = 0x10, // driver need to do error handle or not handle-well.
BT_STATUS_WRONG_LEVEL = 0x11, // should be under passive level
BT_STATUS_MAX
}BT_CTRL_STATUS,*PBT_CTRL_STATUS;
// OP codes definition between the user layer and driver
typedef enum _BT_CTRL_OPCODE_UPPER{
BT_UP_OP_BT_READY = 0x00,
BT_UP_OP_BT_SET_MODE = 0x01,
BT_UP_OP_BT_SET_TX_RX_PARAMETER = 0x02,
BT_UP_OP_BT_SET_GENERAL = 0x03,
BT_UP_OP_BT_GET_GENERAL = 0x04,
BT_UP_OP_BT_TEST_CTRL = 0x05,
BT_UP_OP_TEST_BT = 0x06,
BT_UP_OP_MAX
}BT_CTRL_OPCODE_UPPER,*PBT_CTRL_OPCODE_UPPER;
typedef enum _BT_SET_GENERAL{
BT_GSET_REG = 0x00,
BT_GSET_RESET = 0x01,
BT_GSET_TARGET_BD_ADDR = 0x02,
BT_GSET_TX_PWR_FINETUNE = 0x03,
BT_SET_TRACKING_INTERVAL = 0x04,
BT_SET_THERMAL_METER = 0x05,
BT_ENABLE_CFO_TRACKING = 0x06,
BT_GSET_UPDATE_BT_PATCH = 0x07,
BT_GSET_MAX
}BT_SET_GENERAL,*PBT_SET_GENERAL;
typedef enum _BT_GET_GENERAL{
BT_GGET_REG = 0x00,
BT_GGET_STATUS = 0x01,
BT_GGET_REPORT = 0x02,
BT_GGET_AFH_MAP = 0x03,
BT_GGET_AFH_STATUS = 0x04,
BT_GGET_MAX
}BT_GET_GENERAL,*PBT_GET_GENERAL;
// definition for BT_UP_OP_BT_SET_GENERAL
typedef enum _BT_REG_TYPE{
BT_REG_RF = 0,
BT_REG_MODEM = 1,
BT_REG_BLUEWIZE = 2,
BT_REG_VENDOR = 3,
BT_REG_LE = 4,
BT_REG_MAX
}BT_REG_TYPE,*PBT_REG_TYPE;
// definition for BT_LO_OP_GET_AFH_MAP
typedef enum _BT_AFH_MAP_TYPE{
BT_AFH_MAP_RESULT = 0,
BT_AFH_MAP_WIFI_PSD_ONLY = 1,
BT_AFH_MAP_WIFI_CH_BW_ONLY = 2,
BT_AFH_MAP_BT_PSD_ONLY = 3,
BT_AFH_MAP_HOST_CLASSIFICATION_ONLY = 4,
BT_AFH_MAP_MAX
}BT_AFH_MAP_TYPE,*PBT_AFH_MAP_TYPE;
// definition for BT_UP_OP_BT_GET_GENERAL
typedef enum _BT_REPORT_TYPE{
BT_REPORT_RX_PACKET_CNT = 0,
BT_REPORT_RX_ERROR_BITS = 1,
BT_REPORT_RSSI = 2,
BT_REPORT_CFO_HDR_QUALITY = 3,
BT_REPORT_CONNECT_TARGET_BD_ADDR = 4,
BT_REPORT_MAX
}BT_REPORT_TYPE,*PBT_REPORT_TYPE;
VOID
MPTBT_Test(
IN struct adapter *Adapter,
IN u1Byte opCode,
IN u1Byte byte1,
IN u1Byte byte2,
IN u1Byte byte3
);
NDIS_STATUS
MPTBT_SendOidBT(
IN struct adapter * pAdapter,
IN PVOID InformationBuffer,
IN ULONG InformationBufferLength,
OUT PULONG BytesRead,
OUT PULONG BytesNeeded
);
VOID
MPTBT_FwC2hBtMpCtrl(
struct adapter *Adapter,
pu1Byte tmpBuf,
u1Byte length
);
void MPh2c_timeout_handle(void *FunctionContext);
VOID mptbt_BtControlProcess(
struct adapter *Adapter,
PVOID pInBuf
);
#define BT_H2C_MAX_RETRY 1
#define BT_MAX_C2H_LEN 20
typedef struct _BT_REQ_CMD{
UCHAR opCodeVer;
UCHAR OpCode;
USHORT paraLength;
UCHAR pParamStart[100];
} BT_REQ_CMD, *PBT_REQ_CMD;
typedef struct _BT_RSP_CMD{
USHORT status;
USHORT paraLength;
UCHAR pParamStart[100];
} BT_RSP_CMD, *PBT_RSP_CMD;
typedef struct _BT_H2C{
u1Byte opCodeVer:4;
u1Byte reqNum:4;
u1Byte opCode;
u1Byte buf[100];
}BT_H2C, *PBT_H2C;
typedef struct _BT_EXT_C2H{
u1Byte extendId;
u1Byte statusCode:4;
u1Byte retLen:4;
u1Byte opCodeVer:4;
u1Byte reqNum:4;
u1Byte buf[100];
}BT_EXT_C2H, *PBT_EXT_C2H;
typedef enum _BT_OPCODE_STATUS{
BT_OP_STATUS_SUCCESS = 0x00, // Success
BT_OP_STATUS_VERSION_MISMATCH = 0x01,
BT_OP_STATUS_UNKNOWN_OPCODE = 0x02,
BT_OP_STATUS_ERROR_PARAMETER = 0x03,
BT_OP_STATUS_MAX
}BT_OPCODE_STATUS,*PBT_OPCODE_STATUS;
//OP codes definition between driver and bt fw
typedef enum _BT_CTRL_OPCODE_LOWER{
BT_LO_OP_GET_BT_VERSION = 0x00,
BT_LO_OP_RESET = 0x01,
BT_LO_OP_TEST_CTRL = 0x02,
BT_LO_OP_SET_BT_MODE = 0x03,
BT_LO_OP_SET_CHNL_TX_GAIN = 0x04,
BT_LO_OP_SET_PKT_TYPE_LEN = 0x05,
BT_LO_OP_SET_PKT_CNT_L_PL_TYPE = 0x06,
BT_LO_OP_SET_PKT_CNT_H_PKT_INTV = 0x07,
BT_LO_OP_SET_PKT_HEADER = 0x08,
BT_LO_OP_SET_WHITENCOEFF = 0x09,
BT_LO_OP_SET_BD_ADDR_L = 0x0a,
BT_LO_OP_SET_BD_ADDR_H = 0x0b,
BT_LO_OP_WRITE_REG_ADDR = 0x0c,
BT_LO_OP_WRITE_REG_VALUE = 0x0d,
BT_LO_OP_GET_BT_STATUS = 0x0e,
BT_LO_OP_GET_BD_ADDR_L = 0x0f,
BT_LO_OP_GET_BD_ADDR_H = 0x10,
BT_LO_OP_READ_REG = 0x11,
BT_LO_OP_SET_TARGET_BD_ADDR_L = 0x12,
BT_LO_OP_SET_TARGET_BD_ADDR_H = 0x13,
BT_LO_OP_SET_TX_POWER_CALIBRATION = 0x14,
BT_LO_OP_GET_RX_PKT_CNT_L = 0x15,
BT_LO_OP_GET_RX_PKT_CNT_H = 0x16,
BT_LO_OP_GET_RX_ERROR_BITS_L = 0x17,
BT_LO_OP_GET_RX_ERROR_BITS_H = 0x18,
BT_LO_OP_GET_RSSI = 0x19,
BT_LO_OP_GET_CFO_HDR_QUALITY_L = 0x1a,
BT_LO_OP_GET_CFO_HDR_QUALITY_H = 0x1b,
BT_LO_OP_GET_TARGET_BD_ADDR_L = 0x1c,
BT_LO_OP_GET_TARGET_BD_ADDR_H = 0x1d,
BT_LO_OP_GET_AFH_MAP_L = 0x1e,
BT_LO_OP_GET_AFH_MAP_M = 0x1f,
BT_LO_OP_GET_AFH_MAP_H = 0x20,
BT_LO_OP_GET_AFH_STATUS = 0x21,
BT_LO_OP_SET_TRACKING_INTERVAL = 0x22,
BT_LO_OP_SET_THERMAL_METER = 0x23,
BT_LO_OP_ENABLE_CFO_TRACKING = 0x24,
BT_LO_OP_MAX
}BT_CTRL_OPCODE_LOWER,*PBT_CTRL_OPCODE_LOWER;
#endif /* #if(MP_DRIVER == 1) */
#endif // #ifndef __INC_MPT_BT_H
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTW_BT_MP_H
#define __RTW_BT_MP_H
#include <osdep_service.h>
#include <drv_types.h>
#include <rtw_mp.h>
#if(MP_DRIVER == 1)
#pragma pack(1)
// definition for BT_UP_OP_BT_READY
#define MP_BT_NOT_READY 0
#define MP_BT_READY 1
// definition for BT_UP_OP_BT_SET_MODE
typedef enum _MP_BT_MODE{
MP_BT_MODE_RF_TXRX_TEST_MODE = 0,
MP_BT_MODE_BT20_DUT_TEST_MODE = 1,
MP_BT_MODE_BT40_DIRECT_TEST_MODE = 2,
MP_BT_MODE_CONNECT_TEST_MODE = 3,
MP_BT_MODE_MAX
}MP_BT_MODE,*PMP_BT_MODE;
// definition for BT_UP_OP_BT_SET_TX_RX_PARAMETER
typedef struct _BT_TXRX_PARAMETERS{
u1Byte txrxChannel;
u4Byte txrxTxPktCnt;
u1Byte txrxTxPktInterval;
u1Byte txrxPayloadType;
u1Byte txrxPktType;
u2Byte txrxPayloadLen;
u4Byte txrxPktHeader;
u1Byte txrxWhitenCoeff;
u1Byte txrxBdaddr[6];
u1Byte txrxTxGainIndex;
} BT_TXRX_PARAMETERS, *PBT_TXRX_PARAMETERS;
// txrxPktType
typedef enum _MP_BT_PKT_TYPE{
MP_BT_PKT_DH1 = 0,
MP_BT_PKT_DH3 = 1,
MP_BT_PKT_DH5 = 2,
MP_BT_PKT_2DH1 = 3,
MP_BT_PKT_2DH3 = 4,
MP_BT_PKT_2DH5 = 5,
MP_BT_PKT_3DH1 = 6,
MP_BT_PKT_3DH3 = 7,
MP_BT_PKT_3DH5 = 8,
MP_BT_PKT_LE = 9,
MP_BT_PKT_MAX
}MP_BT_PKT_TYPE,*PMP_BT_PKT_TYPE;
// txrxPayloadType
typedef enum _MP_BT_PAYLOAD_TYPE{
MP_BT_PAYLOAD_01010101 = 0,
MP_BT_PAYLOAD_ALL_1 = 1,
MP_BT_PAYLOAD_ALL_0 = 2,
MP_BT_PAYLOAD_11110000 = 3,
MP_BT_PAYLOAD_PRBS9 = 4,
MP_BT_PAYLOAD_MAX
}MP_BT_PAYLOAD_TYPE,*PMP_BT_PAYLOAD_TYPE;
// definition for BT_UP_OP_BT_TEST_CTRL
typedef enum _MP_BT_TEST_CTRL{
MP_BT_TEST_STOP_ALL_TESTS = 0,
MP_BT_TEST_START_RX_TEST = 1,
MP_BT_TEST_START_PACKET_TX_TEST = 2,
MP_BT_TEST_START_CONTINUOUS_TX_TEST = 3,
MP_BT_TEST_START_INQUIRY_SCAN_TEST = 4,
MP_BT_TEST_START_PAGE_SCAN_TEST = 5,
MP_BT_TEST_START_INQUIRY_PAGE_SCAN_TEST = 6,
MP_BT_TEST_START_LEGACY_CONNECT_TEST = 7,
MP_BT_TEST_START_LE_CONNECT_TEST_INITIATOR = 8,
MP_BT_TEST_START_LE_CONNECT_TEST_ADVERTISER = 9,
MP_BT_TEST_MAX
}MP_BT_TEST_CTRL,*PMP_BT_TEST_CTRL;
typedef enum _RTL_EXT_C2H_EVT
{
EXT_C2H_WIFI_FW_ACTIVE_RSP = 0,
EXT_C2H_TRIG_BY_BT_FW = 1,
MAX_EXT_C2HEVENT
}RTL_EXT_C2H_EVT;
// return status definition to the user layer
typedef enum _BT_CTRL_STATUS{
BT_STATUS_SUCCESS = 0x00, // Success
BT_STATUS_BT_OP_SUCCESS = 0x01, // bt fw op execution success
BT_STATUS_H2C_SUCCESS = 0x02, // H2c success
BT_STATUS_H2C_TIMTOUT = 0x03, // H2c timeout
BT_STATUS_H2C_BT_NO_RSP = 0x04, // H2c sent, bt no rsp
BT_STATUS_C2H_SUCCESS = 0x05, // C2h success
BT_STATUS_C2H_REQNUM_MISMATCH = 0x06, // bt fw wrong rsp
BT_STATUS_OPCODE_U_VERSION_MISMATCH = 0x07, // Upper layer OP code version mismatch.
BT_STATUS_OPCODE_L_VERSION_MISMATCH = 0x08, // Lower layer OP code version mismatch.
BT_STATUS_UNKNOWN_OPCODE_U = 0x09, // Unknown Upper layer OP code
BT_STATUS_UNKNOWN_OPCODE_L = 0x0a, // Unknown Lower layer OP code
BT_STATUS_PARAMETER_FORMAT_ERROR_U = 0x0b, // Wrong parameters sent by upper layer.
BT_STATUS_PARAMETER_FORMAT_ERROR_L = 0x0c, // bt fw parameter format is not consistency
BT_STATUS_PARAMETER_OUT_OF_RANGE_U = 0x0d, // uppery layer parameter value is out of range
BT_STATUS_PARAMETER_OUT_OF_RANGE_L = 0x0e, // bt fw parameter value is out of range
BT_STATUS_UNKNOWN_STATUS_L = 0x0f, // bt returned an defined status code
BT_STATUS_UNKNOWN_STATUS_H = 0x10, // driver need to do error handle or not handle-well.
BT_STATUS_WRONG_LEVEL = 0x11, // should be under passive level
BT_STATUS_MAX
}BT_CTRL_STATUS,*PBT_CTRL_STATUS;
// OP codes definition between the user layer and driver
typedef enum _BT_CTRL_OPCODE_UPPER{
BT_UP_OP_BT_READY = 0x00,
BT_UP_OP_BT_SET_MODE = 0x01,
BT_UP_OP_BT_SET_TX_RX_PARAMETER = 0x02,
BT_UP_OP_BT_SET_GENERAL = 0x03,
BT_UP_OP_BT_GET_GENERAL = 0x04,
BT_UP_OP_BT_TEST_CTRL = 0x05,
BT_UP_OP_TEST_BT = 0x06,
BT_UP_OP_MAX
}BT_CTRL_OPCODE_UPPER,*PBT_CTRL_OPCODE_UPPER;
typedef enum _BT_SET_GENERAL{
BT_GSET_REG = 0x00,
BT_GSET_RESET = 0x01,
BT_GSET_TARGET_BD_ADDR = 0x02,
BT_GSET_TX_PWR_FINETUNE = 0x03,
BT_SET_TRACKING_INTERVAL = 0x04,
BT_SET_THERMAL_METER = 0x05,
BT_ENABLE_CFO_TRACKING = 0x06,
BT_GSET_UPDATE_BT_PATCH = 0x07,
BT_GSET_MAX
}BT_SET_GENERAL,*PBT_SET_GENERAL;
typedef enum _BT_GET_GENERAL{
BT_GGET_REG = 0x00,
BT_GGET_STATUS = 0x01,
BT_GGET_REPORT = 0x02,
BT_GGET_AFH_MAP = 0x03,
BT_GGET_AFH_STATUS = 0x04,
BT_GGET_MAX
}BT_GET_GENERAL,*PBT_GET_GENERAL;
// definition for BT_UP_OP_BT_SET_GENERAL
typedef enum _BT_REG_TYPE{
BT_REG_RF = 0,
BT_REG_MODEM = 1,
BT_REG_BLUEWIZE = 2,
BT_REG_VENDOR = 3,
BT_REG_LE = 4,
BT_REG_MAX
}BT_REG_TYPE,*PBT_REG_TYPE;
// definition for BT_LO_OP_GET_AFH_MAP
typedef enum _BT_AFH_MAP_TYPE{
BT_AFH_MAP_RESULT = 0,
BT_AFH_MAP_WIFI_PSD_ONLY = 1,
BT_AFH_MAP_WIFI_CH_BW_ONLY = 2,
BT_AFH_MAP_BT_PSD_ONLY = 3,
BT_AFH_MAP_HOST_CLASSIFICATION_ONLY = 4,
BT_AFH_MAP_MAX
}BT_AFH_MAP_TYPE,*PBT_AFH_MAP_TYPE;
// definition for BT_UP_OP_BT_GET_GENERAL
typedef enum _BT_REPORT_TYPE{
BT_REPORT_RX_PACKET_CNT = 0,
BT_REPORT_RX_ERROR_BITS = 1,
BT_REPORT_RSSI = 2,
BT_REPORT_CFO_HDR_QUALITY = 3,
BT_REPORT_CONNECT_TARGET_BD_ADDR = 4,
BT_REPORT_MAX
}BT_REPORT_TYPE,*PBT_REPORT_TYPE;
VOID
MPTBT_Test(
IN struct adapter *Adapter,
IN u1Byte opCode,
IN u1Byte byte1,
IN u1Byte byte2,
IN u1Byte byte3
);
NDIS_STATUS
MPTBT_SendOidBT(
IN struct adapter * pAdapter,
IN PVOID InformationBuffer,
IN ULONG InformationBufferLength,
OUT PULONG BytesRead,
OUT PULONG BytesNeeded
);
VOID
MPTBT_FwC2hBtMpCtrl(
struct adapter *Adapter,
pu1Byte tmpBuf,
u1Byte length
);
void MPh2c_timeout_handle(void *FunctionContext);
VOID mptbt_BtControlProcess(
struct adapter *Adapter,
PVOID pInBuf
);
#define BT_H2C_MAX_RETRY 1
#define BT_MAX_C2H_LEN 20
typedef struct _BT_REQ_CMD{
UCHAR opCodeVer;
UCHAR OpCode;
USHORT paraLength;
UCHAR pParamStart[100];
} BT_REQ_CMD, *PBT_REQ_CMD;
typedef struct _BT_RSP_CMD{
USHORT status;
USHORT paraLength;
UCHAR pParamStart[100];
} BT_RSP_CMD, *PBT_RSP_CMD;
typedef struct _BT_H2C{
u1Byte opCodeVer:4;
u1Byte reqNum:4;
u1Byte opCode;
u1Byte buf[100];
}BT_H2C, *PBT_H2C;
typedef struct _BT_EXT_C2H{
u1Byte extendId;
u1Byte statusCode:4;
u1Byte retLen:4;
u1Byte opCodeVer:4;
u1Byte reqNum:4;
u1Byte buf[100];
}BT_EXT_C2H, *PBT_EXT_C2H;
typedef enum _BT_OPCODE_STATUS{
BT_OP_STATUS_SUCCESS = 0x00, // Success
BT_OP_STATUS_VERSION_MISMATCH = 0x01,
BT_OP_STATUS_UNKNOWN_OPCODE = 0x02,
BT_OP_STATUS_ERROR_PARAMETER = 0x03,
BT_OP_STATUS_MAX
}BT_OPCODE_STATUS,*PBT_OPCODE_STATUS;
//OP codes definition between driver and bt fw
typedef enum _BT_CTRL_OPCODE_LOWER{
BT_LO_OP_GET_BT_VERSION = 0x00,
BT_LO_OP_RESET = 0x01,
BT_LO_OP_TEST_CTRL = 0x02,
BT_LO_OP_SET_BT_MODE = 0x03,
BT_LO_OP_SET_CHNL_TX_GAIN = 0x04,
BT_LO_OP_SET_PKT_TYPE_LEN = 0x05,
BT_LO_OP_SET_PKT_CNT_L_PL_TYPE = 0x06,
BT_LO_OP_SET_PKT_CNT_H_PKT_INTV = 0x07,
BT_LO_OP_SET_PKT_HEADER = 0x08,
BT_LO_OP_SET_WHITENCOEFF = 0x09,
BT_LO_OP_SET_BD_ADDR_L = 0x0a,
BT_LO_OP_SET_BD_ADDR_H = 0x0b,
BT_LO_OP_WRITE_REG_ADDR = 0x0c,
BT_LO_OP_WRITE_REG_VALUE = 0x0d,
BT_LO_OP_GET_BT_STATUS = 0x0e,
BT_LO_OP_GET_BD_ADDR_L = 0x0f,
BT_LO_OP_GET_BD_ADDR_H = 0x10,
BT_LO_OP_READ_REG = 0x11,
BT_LO_OP_SET_TARGET_BD_ADDR_L = 0x12,
BT_LO_OP_SET_TARGET_BD_ADDR_H = 0x13,
BT_LO_OP_SET_TX_POWER_CALIBRATION = 0x14,
BT_LO_OP_GET_RX_PKT_CNT_L = 0x15,
BT_LO_OP_GET_RX_PKT_CNT_H = 0x16,
BT_LO_OP_GET_RX_ERROR_BITS_L = 0x17,
BT_LO_OP_GET_RX_ERROR_BITS_H = 0x18,
BT_LO_OP_GET_RSSI = 0x19,
BT_LO_OP_GET_CFO_HDR_QUALITY_L = 0x1a,
BT_LO_OP_GET_CFO_HDR_QUALITY_H = 0x1b,
BT_LO_OP_GET_TARGET_BD_ADDR_L = 0x1c,
BT_LO_OP_GET_TARGET_BD_ADDR_H = 0x1d,
BT_LO_OP_GET_AFH_MAP_L = 0x1e,
BT_LO_OP_GET_AFH_MAP_M = 0x1f,
BT_LO_OP_GET_AFH_MAP_H = 0x20,
BT_LO_OP_GET_AFH_STATUS = 0x21,
BT_LO_OP_SET_TRACKING_INTERVAL = 0x22,
BT_LO_OP_SET_THERMAL_METER = 0x23,
BT_LO_OP_ENABLE_CFO_TRACKING = 0x24,
BT_LO_OP_MAX
}BT_CTRL_OPCODE_LOWER,*PBT_CTRL_OPCODE_LOWER;
#endif /* #if(MP_DRIVER == 1) */
#endif // #ifndef __INC_MPT_BT_H

3
include/rtw_byteorder.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -37,4 +37,3 @@
#endif
#endif /* _RTL871X_BYTEORDER_H_ */

255
include/rtw_cmd.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -32,7 +32,7 @@
#define FREE_CMDOBJ_SZ 128
#define MAX_CMDSZ 1024
#define MAX_RSPSZ 512
#define MAX_EVTSZ 1024
@ -47,19 +47,19 @@
u32 cmdsz;
u8 *rsp;
u32 rspsz;
//_sema cmd_sem;
//_sema cmd_sem;
_list list;
};
struct cmd_priv {
_sema cmd_queue_sema;
//_sema cmd_done_sema;
_sema terminate_cmdthread_sema;
_sema terminate_cmdthread_sema;
_queue cmd_queue;
u8 cmd_seq;
u8 *cmd_buf; //shall be non-paged, and 4 bytes aligned
u8 *cmd_allocated_buf;
u8 *rsp_buf; //shall be non-paged, and 4 bytes aligned
u8 *rsp_buf; //shall be non-paged, and 4 bytes aligned
u8 *rsp_allocated_buf;
u32 cmd_issued_cnt;
u32 cmd_done_cnt;
@ -74,7 +74,7 @@
u16 evtcode;
u8 res;
u8 *parmbuf;
u32 evtsz;
u32 evtsz;
_list list;
};
#endif
@ -93,15 +93,15 @@
struct rtw_cbuf *c2h_queue;
#define C2H_QUEUE_MAX_LEN 10
#endif
#ifdef CONFIG_H2CLBK
_sema lbkevt_done;
u8 lbkevt_limit;
u8 lbkevt_num;
u8 *cmdevt_parm;
u8 *cmdevt_parm;
#endif
ATOMIC_T event_seq;
u8 *evt_buf; //shall be non-paged, and 4 bytes aligned
u8 *evt_buf; //shall be non-paged, and 4 bytes aligned
u8 *evt_allocated_buf;
u32 evt_done_cnt;
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
@ -155,7 +155,7 @@ u8 p2p_protocol_wk_cmd(struct adapter*padapter, int intCmdType );
#endif //CONFIG_P2P
enum rtw_drvextra_cmd_id
{
{
NONE_WK_CID,
DYNAMIC_CHK_WK_CID,
DM_CTRL_WK_CID,
@ -173,7 +173,7 @@ enum rtw_drvextra_cmd_id
FREE_ASSOC_RESOURCES, // add for CONFIG_IEEE80211W, none 11w also can use
#ifdef CONFIG_DETECT_C2H_BY_POLLING
EVENT_POLLING_CID,
#endif
#endif
MAX_WK_CID
};
@ -277,14 +277,14 @@ Caller Mode: AP, Ad-HoC, Infra
Notes: To ask RTL8711 performing site-survey
Command-Event Mode
Command-Event Mode
*/
#define RTW_SSID_SCAN_AMOUNT 9 // for WEXT_CSCAN_AMOUNT 9
#define RTW_CHANNEL_SCAN_AMOUNT (14+37)
struct sitesurvey_parm {
sint scan_mode; //active: 1, passive: 0
sint scan_mode; //active: 1, passive: 0
/* sint bsslimit; // 1 ~ 48 */
u8 ssid_num;
u8 ch_num;
@ -320,25 +320,25 @@ when 802.1x ==> keyid > 2 ==> unicast key
*/
struct setkey_parm {
u8 algorithm; // encryption algorithm, could be none, wep40, TKIP, CCMP, wep104
u8 keyid;
u8 grpkey; // 1: this is the grpkey for 802.1x. 0: this is the unicast key for 802.1x
u8 set_tx; // 1: main tx key for wep. 0: other key.
u8 keyid;
u8 grpkey; // 1: this is the grpkey for 802.1x. 0: this is the unicast key for 802.1x
u8 set_tx; // 1: main tx key for wep. 0: other key.
u8 key[16]; // this could be 40 or 104
};
/*
When in AP or Ad-Hoc mode, this is used to
When in AP or Ad-Hoc mode, this is used to
allocate an sw/hw entry for a newly associated sta.
Command
when shared key ==> algorithm/keyid
when shared key ==> algorithm/keyid
*/
struct set_stakey_parm {
u8 addr[ETH_ALEN];
u8 algorithm;
u8 id;// currently for erasing cam entry if algorithm == _NO_PRIVACY_
u8 id;// currently for erasing cam entry if algorithm == _NO_PRIVACY_
u8 key[16];
};
@ -369,16 +369,16 @@ struct set_assocsta_rsp {
/*
Caller Ad-Hoc/AP
Command mode
This is to force fw to del an sta_data entry per driver's request
FW will invalidate the cam entry associated with it.
*/
struct del_assocsta_parm {
u8 addr[ETH_ALEN];
u8 addr[ETH_ALEN];
};
/*
@ -450,7 +450,7 @@ Command-Rsp Mode
*/
struct getdatarate_parm {
u32 rsvd;
};
struct getdatarate_rsp {
u8 datarates[NumRates];
@ -560,18 +560,18 @@ struct Tx_Beacon_param
/*
Notes: This command is used for H2C/C2H loopback testing
mac[0] == 0
mac[0] == 0
==> CMD mode, return H2C_SUCCESS.
The following condition must be ture under CMD mode
mac[1] == mac[4], mac[2] == mac[3], mac[0]=mac[5]= 0;
s0 == 0x1234, s1 == 0xabcd, w0 == 0x78563412, w1 == 0x5aa5def7;
s2 == (b1 << 8 | b0);
mac[0] == 1
==> CMD_RSP mode, return H2C_SUCCESS_RSP
The rsp layout shall be:
rsp: parm:
rsp: parm:
mac[0] = mac[5];
mac[1] = mac[4];
mac[2] = mac[3];
@ -580,14 +580,14 @@ struct Tx_Beacon_param
mac[5] = mac[0];
s0 = s1;
s1 = swap16(s0);
w0 = swap32(w1);
b0 = b1
s2 = s0 + s1
b1 = b0
w0 = swap32(w1);
b0 = b1
s2 = s0 + s1
b1 = b0
w1 = w0
mac[0] == 2
==> CMD_EVENT mode, return H2C_SUCCESS
mac[0] == 2
==> CMD_EVENT mode, return H2C_SUCCESS
The event layout shall be:
event: parm:
mac[0] = mac[5];
@ -598,17 +598,17 @@ struct Tx_Beacon_param
mac[5] = mac[0];
s0 = swap16(s0) - event.mac[2];
s1 = s1 + event.mac[2];
w0 = swap32(w0);
b0 = b1
s2 = s0 + event.mac[2]
b1 = b0
w1 = swap32(w1) - event.mac[2];
w0 = swap32(w0);
b0 = b1
s2 = s0 + event.mac[2]
b1 = b0
w1 = swap32(w1) - event.mac[2];
parm->mac[3] is the total event counts that host requested.
event will be the same with the cmd's param.
*/
#ifdef CONFIG_H2CLBK
@ -625,7 +625,7 @@ struct seth2clbk_parm {
};
struct geth2clbk_parm {
u32 rsv;
u32 rsv;
};
struct geth2clbk_rsp {
@ -651,10 +651,10 @@ struct drvextra_cmd_parm {
/*------------------- Below are used for RF/BB tunning ---------------------*/
struct setantenna_parm {
u8 tx_antset;
u8 tx_antset;
u8 rx_antset;
u8 tx_antenna;
u8 rx_antenna;
u8 tx_antenna;
u8 rx_antenna;
};
struct enrateadaptive_parm {
@ -807,7 +807,7 @@ struct setassocrspextraie_parm {
struct addBaReq_parm
{
unsigned int tid;
unsigned int tid;
u8 addr[ETH_ALEN];
};
@ -876,25 +876,25 @@ struct SwitchBandwidth_parm
#endif /* MP_FIRMWARE_OFFLOAD */
/*H2C Handler index: 59 */
/*H2C Handler index: 59 */
struct SetChannelPlan_param
{
u8 channel_plan;
};
/*H2C Handler index: 60 */
/*H2C Handler index: 60 */
struct LedBlink_param
{
PLED_871x pLed;
};
/*H2C Handler index: 61 */
/*H2C Handler index: 61 */
struct SetChannelSwitch_param
{
u8 new_ch_no;
};
/*H2C Handler index: 62 */
/*H2C Handler index: 62 */
struct TDLSoption_param
{
u8 addr[ETH_ALEN];
@ -906,7 +906,7 @@ struct TDLSoption_param
/*
Result:
Result:
0x00: success
0x01: sucess, and check Response.
0x02: cmd ignored due to duplicated sequcne number
@ -988,7 +988,7 @@ u8 rtw_drvextra_cmd_hdl(struct adapter *padapter, unsigned char *pbuf);
extern void rtw_survey_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd);
extern void rtw_disassoc_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd);
extern void rtw_joinbss_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd);
extern void rtw_joinbss_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd);
extern void rtw_createbss_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd);
extern void rtw_getbbrfreg_cmdrsp_callback(struct adapter *padapter, struct cmd_obj *pcmd);
extern void rtw_readtssi_cmdrsp_callback(struct adapter* padapter, struct cmd_obj *pcmd);
@ -1006,90 +1006,90 @@ struct _cmd_callback {
enum rtw_h2c_cmd
{
GEN_CMD_CODE(_Read_MACREG) , /*0*/
GEN_CMD_CODE(_Write_MACREG) ,
GEN_CMD_CODE(_Read_BBREG) ,
GEN_CMD_CODE(_Write_BBREG) ,
GEN_CMD_CODE(_Read_RFREG) ,
GEN_CMD_CODE(_Write_RFREG) , /*5*/
GEN_CMD_CODE(_Read_EEPROM) ,
GEN_CMD_CODE(_Write_EEPROM) ,
GEN_CMD_CODE(_Read_EFUSE) ,
GEN_CMD_CODE(_Write_EFUSE) ,
GEN_CMD_CODE(_Read_CAM) , /*10*/
GEN_CMD_CODE(_Write_CAM) ,
GEN_CMD_CODE(_setBCNITV),
GEN_CMD_CODE(_setMBIDCFG),
GEN_CMD_CODE(_JoinBss), /*14*/
GEN_CMD_CODE(_DisConnect) , /*15*/
GEN_CMD_CODE(_CreateBss) ,
GEN_CMD_CODE(_SetOpMode) ,
GEN_CMD_CODE(_Write_MACREG) ,
GEN_CMD_CODE(_Read_BBREG) ,
GEN_CMD_CODE(_Write_BBREG) ,
GEN_CMD_CODE(_Read_RFREG) ,
GEN_CMD_CODE(_Write_RFREG) , /*5*/
GEN_CMD_CODE(_Read_EEPROM) ,
GEN_CMD_CODE(_Write_EEPROM) ,
GEN_CMD_CODE(_Read_EFUSE) ,
GEN_CMD_CODE(_Write_EFUSE) ,
GEN_CMD_CODE(_Read_CAM) , /*10*/
GEN_CMD_CODE(_Write_CAM) ,
GEN_CMD_CODE(_setBCNITV),
GEN_CMD_CODE(_setMBIDCFG),
GEN_CMD_CODE(_JoinBss), /*14*/
GEN_CMD_CODE(_DisConnect) , /*15*/
GEN_CMD_CODE(_CreateBss) ,
GEN_CMD_CODE(_SetOpMode) ,
GEN_CMD_CODE(_SiteSurvey), /*18*/
GEN_CMD_CODE(_SetAuth) ,
GEN_CMD_CODE(_SetKey) , /*20*/
GEN_CMD_CODE(_SetStaKey) ,
GEN_CMD_CODE(_SetAssocSta) ,
GEN_CMD_CODE(_DelAssocSta) ,
GEN_CMD_CODE(_SetStaPwrState) ,
GEN_CMD_CODE(_SetBasicRate) , /*25*/
GEN_CMD_CODE(_GetBasicRate) ,
GEN_CMD_CODE(_SetDataRate) ,
GEN_CMD_CODE(_GetDataRate) ,
GEN_CMD_CODE(_SetAuth) ,
GEN_CMD_CODE(_SetKey) , /*20*/
GEN_CMD_CODE(_SetStaKey) ,
GEN_CMD_CODE(_SetAssocSta) ,
GEN_CMD_CODE(_DelAssocSta) ,
GEN_CMD_CODE(_SetStaPwrState) ,
GEN_CMD_CODE(_SetBasicRate) , /*25*/
GEN_CMD_CODE(_GetBasicRate) ,
GEN_CMD_CODE(_SetDataRate) ,
GEN_CMD_CODE(_GetDataRate) ,
GEN_CMD_CODE(_SetPhyInfo) ,
GEN_CMD_CODE(_GetPhyInfo) , /*30*/
GEN_CMD_CODE(_GetPhyInfo) , /*30*/
GEN_CMD_CODE(_SetPhy) ,
GEN_CMD_CODE(_GetPhy) ,
GEN_CMD_CODE(_readRssi) ,
GEN_CMD_CODE(_readGain) ,
GEN_CMD_CODE(_SetAtim) , /*35*/
GEN_CMD_CODE(_SetPwrMode) ,
GEN_CMD_CODE(_JoinbssRpt),
GEN_CMD_CODE(_SetRaTable) ,
GEN_CMD_CODE(_GetRaTable) ,
GEN_CMD_CODE(_GetCCXReport), /*40*/
GEN_CMD_CODE(_GetDTMReport),
GEN_CMD_CODE(_GetTXRateStatistics),
GEN_CMD_CODE(_SetUsbSuspend),
GEN_CMD_CODE(_SetH2cLbk),
GEN_CMD_CODE(_AddBAReq) , /*45*/
GEN_CMD_CODE(_GetPhy) ,
GEN_CMD_CODE(_readRssi) ,
GEN_CMD_CODE(_readGain) ,
GEN_CMD_CODE(_SetAtim) , /*35*/
GEN_CMD_CODE(_SetPwrMode) ,
GEN_CMD_CODE(_JoinbssRpt),
GEN_CMD_CODE(_SetRaTable) ,
GEN_CMD_CODE(_GetRaTable) ,
GEN_CMD_CODE(_GetCCXReport), /*40*/
GEN_CMD_CODE(_GetDTMReport),
GEN_CMD_CODE(_GetTXRateStatistics),
GEN_CMD_CODE(_SetUsbSuspend),
GEN_CMD_CODE(_SetH2cLbk),
GEN_CMD_CODE(_AddBAReq) , /*45*/
GEN_CMD_CODE(_SetChannel), /*46*/
GEN_CMD_CODE(_SetTxPower),
GEN_CMD_CODE(_SetTxPower),
GEN_CMD_CODE(_SwitchAntenna),
GEN_CMD_CODE(_SetCrystalCap),
GEN_CMD_CODE(_SetSingleCarrierTx), /*50*/
GEN_CMD_CODE(_SetSingleToneTx),/*51*/
GEN_CMD_CODE(_SetCarrierSuppressionTx),
GEN_CMD_CODE(_SetContinuousTx),
GEN_CMD_CODE(_SwitchBandwidth), /*54*/
GEN_CMD_CODE(_TX_Beacon), /*55*/
GEN_CMD_CODE(_Set_MLME_EVT), /*56*/
GEN_CMD_CODE(_Set_Drv_Extra), /*57*/
GEN_CMD_CODE(_Set_H2C_MSG), /*58*/
GEN_CMD_CODE(_SetChannelPlan), /*59*/
GEN_CMD_CODE(_LedBlink), /*60*/
GEN_CMD_CODE(_SetChannelSwitch), /*61*/
GEN_CMD_CODE(_TDLS), /*62*/
MAX_H2CCMD
};
#define _GetBBReg_CMD_ _Read_BBREG_CMD_
#define _SetBBReg_CMD_ _Write_BBREG_CMD_
#define _GetRFReg_CMD_ _Read_RFREG_CMD_
#define _SetRFReg_CMD_ _Write_RFREG_CMD_
#define _SetBBReg_CMD_ _Write_BBREG_CMD_
#define _GetRFReg_CMD_ _Read_RFREG_CMD_
#define _SetRFReg_CMD_ _Write_RFREG_CMD_
#ifdef _RTW_CMD_C_
static struct _cmd_callback rtw_cmd_callback[] =
static struct _cmd_callback rtw_cmd_callback[] =
{
{GEN_CMD_CODE(_Read_MACREG), NULL}, /*0*/
{GEN_CMD_CODE(_Write_MACREG), NULL},
{GEN_CMD_CODE(_Write_MACREG), NULL},
{GEN_CMD_CODE(_Read_BBREG), &rtw_getbbrfreg_cmdrsp_callback},
{GEN_CMD_CODE(_Write_BBREG), NULL},
{GEN_CMD_CODE(_Read_RFREG), &rtw_getbbrfreg_cmdrsp_callback},
@ -1098,32 +1098,32 @@ static struct _cmd_callback rtw_cmd_callback[] =
{GEN_CMD_CODE(_Write_EEPROM), NULL},
{GEN_CMD_CODE(_Read_EFUSE), NULL},
{GEN_CMD_CODE(_Write_EFUSE), NULL},
{GEN_CMD_CODE(_Read_CAM), NULL}, /*10*/
{GEN_CMD_CODE(_Write_CAM), NULL},
{GEN_CMD_CODE(_Write_CAM), NULL},
{GEN_CMD_CODE(_setBCNITV), NULL},
{GEN_CMD_CODE(_setMBIDCFG), NULL},
{GEN_CMD_CODE(_setMBIDCFG), NULL},
{GEN_CMD_CODE(_JoinBss), &rtw_joinbss_cmd_callback}, /*14*/
{GEN_CMD_CODE(_DisConnect), &rtw_disassoc_cmd_callback}, /*15*/
{GEN_CMD_CODE(_CreateBss), &rtw_createbss_cmd_callback},
{GEN_CMD_CODE(_SetOpMode), NULL},
{GEN_CMD_CODE(_SiteSurvey), &rtw_survey_cmd_callback}, /*18*/
{GEN_CMD_CODE(_SetAuth), NULL},
{GEN_CMD_CODE(_SetKey), NULL}, /*20*/
{GEN_CMD_CODE(_SetStaKey), &rtw_setstaKey_cmdrsp_callback},
{GEN_CMD_CODE(_SetAssocSta), &rtw_setassocsta_cmdrsp_callback},
{GEN_CMD_CODE(_DelAssocSta), NULL},
{GEN_CMD_CODE(_SetStaPwrState), NULL},
{GEN_CMD_CODE(_DelAssocSta), NULL},
{GEN_CMD_CODE(_SetStaPwrState), NULL},
{GEN_CMD_CODE(_SetBasicRate), NULL}, /*25*/
{GEN_CMD_CODE(_GetBasicRate), NULL},
{GEN_CMD_CODE(_SetDataRate), NULL},
{GEN_CMD_CODE(_GetDataRate), NULL},
{GEN_CMD_CODE(_SetPhyInfo), NULL},
{GEN_CMD_CODE(_GetPhyInfo), NULL}, /*30*/
{GEN_CMD_CODE(_SetPhy), NULL},
{GEN_CMD_CODE(_GetPhy), NULL},
{GEN_CMD_CODE(_GetPhy), NULL},
{GEN_CMD_CODE(_readRssi), NULL},
{GEN_CMD_CODE(_readGain), NULL},
{GEN_CMD_CODE(_SetAtim), NULL}, /*35*/
@ -1131,19 +1131,19 @@ static struct _cmd_callback rtw_cmd_callback[] =
{GEN_CMD_CODE(_JoinbssRpt), NULL},
{GEN_CMD_CODE(_SetRaTable), NULL},
{GEN_CMD_CODE(_GetRaTable) , NULL},
{GEN_CMD_CODE(_GetCCXReport), NULL}, /*40*/
{GEN_CMD_CODE(_GetDTMReport), NULL},
{GEN_CMD_CODE(_GetTXRateStatistics), NULL},
{GEN_CMD_CODE(_SetUsbSuspend), NULL},
{GEN_CMD_CODE(_SetH2cLbk), NULL},
{GEN_CMD_CODE(_AddBAReq), NULL}, /*45*/
{GEN_CMD_CODE(_GetDTMReport), NULL},
{GEN_CMD_CODE(_GetTXRateStatistics), NULL},
{GEN_CMD_CODE(_SetUsbSuspend), NULL},
{GEN_CMD_CODE(_SetH2cLbk), NULL},
{GEN_CMD_CODE(_AddBAReq), NULL}, /*45*/
{GEN_CMD_CODE(_SetChannel), NULL}, /*46*/
{GEN_CMD_CODE(_SetTxPower), NULL},
{GEN_CMD_CODE(_SwitchAntenna), NULL},
{GEN_CMD_CODE(_SetCrystalCap), NULL},
{GEN_CMD_CODE(_SetSingleCarrierTx), NULL}, /*50*/
{GEN_CMD_CODE(_SetSingleToneTx), NULL}, /*51*/
{GEN_CMD_CODE(_SetCarrierSuppressionTx), NULL},
{GEN_CMD_CODE(_SetContinuousTx), NULL},
@ -1155,11 +1155,10 @@ static struct _cmd_callback rtw_cmd_callback[] =
{GEN_CMD_CODE(_Set_H2C_MSG), NULL},/*58*/
{GEN_CMD_CODE(_SetChannelPlan), NULL},/*59*/
{GEN_CMD_CODE(_LedBlink), NULL},/*60*/
{GEN_CMD_CODE(_SetChannelSwitch), NULL},/*61*/
{GEN_CMD_CODE(_TDLS), NULL},/*62*/
};
#endif
#endif // _CMD_H_

15
include/rtw_debug.h
View file

@ -172,7 +172,7 @@ extern u32 GlobalDebugLevel;
#define DRIVER_PREFIX "R8188EU: "
#define DEBUG_LEVEL (_drv_err_)
#if defined (_dbgdump)
#if defined (_dbgdump)
#undef DBG_871X_LEVEL
#define DBG_871X_LEVEL(level, fmt, arg...) \
do {\
@ -279,7 +279,7 @@ extern u32 GlobalDebugLevel;
off_t offset, int count,
int *eof, void *data);
int proc_set_write_reg(struct file *file, const char *buffer,
int proc_set_write_reg(struct file *file, const char *buffer,
unsigned long count, void *data);
int proc_get_read_reg(char *page, char **start,
@ -399,7 +399,7 @@ extern u32 GlobalDebugLevel;
int proc_get_ht_enable(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_set_ht_enable(struct file *file, const char *buffer,
unsigned long count, void *data);
@ -409,18 +409,18 @@ extern u32 GlobalDebugLevel;
int proc_set_cbw40_enable(struct file *file, const char *buffer,
unsigned long count, void *data);
int proc_get_ampdu_enable(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_set_ampdu_enable(struct file *file, const char *buffer,
unsigned long count, void *data);
int proc_get_rx_stbc(char *page, char **start,
off_t offset, int count,
int *eof, void *data);
int proc_set_rx_stbc(struct file *file, const char *buffer,
unsigned long count, void *data);
#endif //CONFIG_80211N_HT
@ -462,4 +462,3 @@ int proc_set_odm_adaptivity(struct file *file, const char *buffer, unsigned long
#endif //CONFIG_PROC_DEBUG
#endif //__RTW_DEBUG_H__

33
include/rtw_eeprom.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -30,7 +30,7 @@
#define HWSET_MAX_SIZE_512 512
#define EEPROM_MAX_SIZE HWSET_MAX_SIZE_512
#define CLOCK_RATE 50 //100us
#define CLOCK_RATE 50 //100us
//- EEPROM opcodes
#define EEPROM_READ_OPCODE 06
@ -41,7 +41,7 @@
//Country codes
#define USA 0x555320
#define EUROPE 0x1 //temp, should be provided later
#define EUROPE 0x1 //temp, should be provided later
#define JAPAN 0x2 //temp, should be provided later
#ifdef CONFIG_SDIO_HCI
@ -64,9 +64,9 @@
#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
//
// Customer ID, note that:
// This variable is initiailzed through EEPROM or registry,
// however, its definition may be different with that in EEPROM for
// Customer ID, note that:
// This variable is initiailzed through EEPROM or registry,
// however, its definition may be different with that in EEPROM for
// EEPROM size consideration. So, we have to perform proper translation between them.
// Besides, CustomerID of registry has precedence of that of EEPROM.
// defined below. 060703, by rcnjko.
@ -79,7 +79,7 @@ typedef enum _RT_CUSTOMER_ID
RT_CID_8187_HW_LED = 3,
RT_CID_8187_NETGEAR = 4,
RT_CID_WHQL = 5,
RT_CID_819x_CAMEO = 6,
RT_CID_819x_CAMEO = 6,
RT_CID_819x_RUNTOP = 7,
RT_CID_819x_Senao = 8,
RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31.
@ -92,10 +92,10 @@ typedef enum _RT_CUSTOMER_ID
RT_CID_819x_ALPHA = 16,
RT_CID_819x_Sitecom = 17,
RT_CID_CCX = 18, // It's set under CCX logo test and isn't demanded for CCX functions, but for test behavior like retry limit and tx report. By Bruce, 2009-02-17.
RT_CID_819x_Lenovo = 19,
RT_CID_819x_Lenovo = 19,
RT_CID_819x_QMI = 20,
RT_CID_819x_Edimax_Belkin = 21,
RT_CID_819x_Sercomm_Belkin = 22,
RT_CID_819x_Edimax_Belkin = 21,
RT_CID_819x_Sercomm_Belkin = 22,
RT_CID_819x_CAMEO1 = 23,
RT_CID_819x_MSI = 24,
RT_CID_819x_Acer = 25,
@ -117,8 +117,8 @@ typedef enum _RT_CUSTOMER_ID
RT_CID_819x_ALPHA_WD=41,
}RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
struct eeprom_priv
{
struct eeprom_priv
{
u8 bautoload_fail_flag;
u8 bloadfile_fail_flag;
u8 bloadmac_fail_flag;
@ -127,7 +127,7 @@ struct eeprom_priv
u8 mac_addr[6]; //PermanentAddress
//u8 config0;
u16 channel_plan;
//u8 country_string[3];
//u8 country_string[3];
//u8 tx_power_b[15];
//u8 tx_power_g[15];
//u8 tx_power_a[201];
@ -142,10 +142,10 @@ struct eeprom_priv
#endif //CONFIG_RF_GAIN_OFFSET
#ifdef CONFIG_SDIO_HCI
u8 sdio_setting;
u8 sdio_setting;
u32 ocr;
u8 cis0[eeprom_cis0_sz];
u8 cis1[eeprom_cis1_sz];
u8 cis1[eeprom_cis1_sz];
#endif
};
@ -153,7 +153,7 @@ struct eeprom_priv
extern void eeprom_write16(struct adapter *padapter, u16 reg, u16 data);
extern u16 eeprom_read16(struct adapter *padapter, u16 reg);
extern void read_eeprom_content(struct adapter *padapter);
extern void eeprom_read_sz(struct adapter * padapter, u16 reg,u8* data, u32 sz);
extern void eeprom_read_sz(struct adapter * padapter, u16 reg,u8* data, u32 sz);
extern void read_eeprom_content_by_attrib(struct adapter * padapter );
@ -164,4 +164,3 @@ extern int retriveAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv);
#endif //CONFIG_ADAPTOR_INFO_CACHING_FILE
#endif //__RTL871X_EEPROM_H__

17
include/rtw_efuse.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -25,7 +25,7 @@
#define EFUSE_ERROE_HANDLE 1
#define PG_STATE_HEADER 0x01
#define PG_STATE_HEADER 0x01
#define PG_STATE_WORD_0 0x02
#define PG_STATE_WORD_1 0x04
#define PG_STATE_WORD_2 0x08
@ -76,15 +76,15 @@ enum _EFUSE_DEF_TYPE {
/*--------------------------Define Parameters-------------------------------*/
#define EFUSE_MAX_WORD_UNIT 4
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure----------------------------*/
typedef struct PG_PKT_STRUCT_A{
u8 offset;
u8 word_en;
u8 data[8];
u8 data[8];
u8 word_cnts;
}PGPKT_STRUCT,*PPGPKT_STRUCT;
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure----------------------------*/
typedef struct _EFUSE_HAL{
u8 fakeEfuseBank;
u32 fakeEfuseUsedBytes;
@ -129,7 +129,7 @@ u8 rtw_efuse_access(struct adapter *padapter, u8 bRead, u16 start_addr, u16 cnts
u8 rtw_efuse_map_read(struct adapter *padapter, u16 addr, u16 cnts, u8 *data);
u8 rtw_efuse_map_write(struct adapter *padapter, u16 addr, u16 cnts, u8 *data);
u8 rtw_BT_efuse_map_read(struct adapter *padapter, u16 addr, u16 cnts, u8 *data);
u8 rtw_BT_efuse_map_write(struct adapter *padapter, u16 addr, u16 cnts, u8 *data);
u8 rtw_BT_efuse_map_write(struct adapter *padapter, u16 addr, u16 cnts, u8 *data);
u16 Efuse_GetCurrentSize(struct adapter *pAdapter, u8 efuseType, BOOLEAN bPseudoTest);
u8 Efuse_CalculateWordCnts(u8 word_en);
@ -139,8 +139,8 @@ u8 efuse_OneByteRead(struct adapter *pAdapter, u16 addr, u8 *data, BOOLEAN bPse
u8 efuse_OneByteWrite(struct adapter *pAdapter, u16 addr, u8 data, BOOLEAN bPseudoTest);
void Efuse_PowerSwitch(struct adapter *pAdapter,u8 bWrite,u8 PwrState);
int Efuse_PgPacketRead(struct adapter *pAdapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);
int Efuse_PgPacketWrite(struct adapter *pAdapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
int Efuse_PgPacketRead(struct adapter *pAdapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);
int Efuse_PgPacketWrite(struct adapter *pAdapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
void efuse_WordEnableDataRead(u8 word_en, u8 *sourdata, u8 *targetdata);
u8 Efuse_WordEnableDataWrite(struct adapter *pAdapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
@ -149,4 +149,3 @@ void EFUSE_ShadowMapUpdate(struct adapter *pAdapter, u8 efuseType, BOOLEAN bPseu
void EFUSE_ShadowRead(struct adapter *pAdapter, u8 Type, u16 Offset, u32 *Value);
#endif

17
include/rtw_event.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -50,8 +50,8 @@ bss_cnt indicates the number of bss that has been reported.
*/
struct surveydone_event {
unsigned int bss_cnt;
unsigned int bss_cnt;
};
/*
@ -78,7 +78,7 @@ struct stassoc_event {
unsigned char macaddr[6];
unsigned char rsvd[2];
int cam_id;
};
struct stadel_event {
@ -89,7 +89,7 @@ struct stadel_event {
struct addba_event
{
unsigned int tid;
unsigned int tid;
};
@ -102,7 +102,7 @@ struct c2hlbk_event{
unsigned char b0;
unsigned short s2;
unsigned char b1;
unsigned int w1;
unsigned int w1;
};
#endif//CONFIG_H2CLBK
@ -116,7 +116,7 @@ struct fwevent {
};
#define C2HEVENT_SZ 32
#define C2HEVENT_SZ 32
struct event_node{
unsigned char *node;
@ -138,9 +138,8 @@ struct c2hevent_queue {
struct network_queue {
volatile int head;
volatile int tail;
WLAN_BSSID_EX networks[NETWORK_QUEUE_SZ];
WLAN_BSSID_EX networks[NETWORK_QUEUE_SZ];
};
#endif // _WLANEVENT_H_

9
include/rtw_ht.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -26,13 +26,13 @@
struct ht_priv
{
u32 ht_option;
u32 ht_option;
u32 ampdu_enable;//for enable Tx A-MPDU
//u8 baddbareq_issued[16];
u32 tx_amsdu_enable;//for enable Tx A-MSDU
u32 tx_amdsu_maxlen; // 1: 8k, 0:4k ; default:8k, for tx
u32 rx_ampdu_maxlen; //for rx reordering ctrl win_sz, updated when join_callback.
u8 bwmode;//
u8 ch_offset;//PRIME_CHNL_OFFSET
u8 sgi;//short GI
@ -43,8 +43,7 @@ struct ht_priv
u8 candidate_tid_bitmap;
struct rtw_ieee80211_ht_cap ht_cap;
};
#endif //_RTL871X_HT_H_

93
include/rtw_io.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -66,7 +66,7 @@
#define _IO_CMDMASK_ (0x1F80)
/*
/*
For prompt mode accessing, caller shall free io_req
Otherwise, io_handler will free io_req
*/
@ -143,16 +143,16 @@ struct _io_ops
void (*_read_port_cancel)(struct intf_hdl *pintfhdl);
void (*_write_port_cancel)(struct intf_hdl *pintfhdl);
};
struct io_req {
struct io_req {
_list list;
u32 addr;
u32 addr;
volatile u32 val;
u32 command;
u32 status;
u8 *pbuf;
u8 *pbuf;
_sema sema;
#ifdef PLATFORM_OS_CE
@ -161,31 +161,31 @@ struct io_req {
USB_TRANSFER usb_transfer_write_mem;
#endif
#endif
void (*_async_io_callback)(struct adapter *padater, struct io_req *pio_req, u8 *cnxt);
u8 *cnxt;
#ifdef PLATFORM_OS_XP
void (*_async_io_callback)(struct adapter *padater, struct io_req *pio_req, u8 *cnxt);
u8 *cnxt;
#ifdef PLATFORM_OS_XP
PMDL pmdl;
PIRP pirp;
PIRP pirp;
#ifdef CONFIG_SDIO_HCI
PSDBUS_REQUEST_PACKET sdrp;
#endif
#endif
#endif
#endif
};
struct intf_hdl {
/*
/*
u32 intf_option;
u32 bus_status;
u32 do_flush;
u8 *adapter;
u8 *intf_dev;
u8 *intf_dev;
struct intf_priv *pintfpriv;
u8 cnt;
void (*intf_hdl_init)(u8 *priv);
@ -195,7 +195,7 @@ struct intf_hdl {
struct _io_ops io_ops;
//u8 intf_status;//moved to struct intf_priv
u16 len;
u16 done_len;
u16 done_len;
*/
struct adapter *padapter;
struct dvobj_priv *pintf_dev;// pointer to &(padapter->dvobjpriv);
@ -206,7 +206,7 @@ struct intf_hdl {
struct reg_protocol_rd {
#ifdef CONFIG_LITTLE_ENDIAN
#ifdef CONFIG_LITTLE_ENDIAN
//DW1
u32 NumOfTrans:4;
@ -231,22 +231,22 @@ struct reg_protocol_rd {
//DW1
u32 Reserved1 :4;
u32 NumOfTrans :4;
u32 NumOfTrans :4;
u32 Reserved2 :24;
u32 Reserved2 :24;
//DW2
u32 WriteEnable : 1;
u32 ByteCount :7;
u32 ByteCount :7;
u32 Reserved3 : 3;
u32 Byte4Access : 1;
u32 Byte4Access : 1;
u32 Byte2Access : 1;
u32 Byte1Access : 1;
u32 BurstMode :1 ;
u32 FixOrContinuous : 1;
u32 Byte1Access : 1;
u32 BurstMode :1 ;
u32 FixOrContinuous : 1;
u32 Reserved4 : 16;
@ -257,12 +257,12 @@ struct reg_protocol_rd {
//u32 Value;
#endif
};
struct reg_protocol_wt {
#ifdef CONFIG_LITTLE_ENDIAN
@ -288,21 +288,21 @@ struct reg_protocol_wt {
#else
//DW1
u32 Reserved1 :4;
u32 NumOfTrans :4;
u32 NumOfTrans :4;
u32 Reserved2 :24;
u32 Reserved2 :24;
//DW2
u32 WriteEnable : 1;
u32 ByteCount :7;
u32 ByteCount :7;
u32 Reserved3 : 3;
u32 Byte4Access : 1;
u32 Byte4Access : 1;
u32 Byte2Access : 1;
u32 Byte1Access : 1;
u32 BurstMode :1 ;
u32 FixOrContinuous : 1;
u32 Byte1Access : 1;
u32 BurstMode :1 ;
u32 FixOrContinuous : 1;
u32 Reserved4 : 16;
@ -337,10 +337,10 @@ Below is the data structure used by _io_handler
*/
struct io_queue {
_lock lock;
_list free_ioreqs;
_list pending; //The io_req list that will be served in the single protocol read/write.
struct io_queue {
_lock lock;
_list free_ioreqs;
_list pending; //The io_req list that will be served in the single protocol read/write.
_list processing;
u8 *free_ioreqs_buf; // 4-byte aligned
u8 *pallocated_free_ioreqs_buf;
@ -348,9 +348,9 @@ struct io_queue {
};
struct io_priv{
struct adapter *padapter;
struct adapter *padapter;
struct intf_hdl intf;
};
@ -449,9 +449,9 @@ extern int dbg_rtw_writeN(struct adapter *adapter, u32 addr ,u32 length , u8 *da
extern void rtw_write_scsi(struct adapter *adapter, u32 cnt, u8 *pmem);
//ioreq
//ioreq
extern void ioreq_read8(struct adapter *adapter, u32 addr, u8 *pval);
extern void ioreq_read16(struct adapter *adapter, u32 addr, u16 *pval);
extern void ioreq_read16(struct adapter *adapter, u32 addr, u16 *pval);
extern void ioreq_read32(struct adapter *adapter, u32 addr, u32 *pval);
extern void ioreq_write8(struct adapter *adapter, u32 addr, u8 val);
extern void ioreq_write16(struct adapter *adapter, u32 addr, u16 val);
@ -459,11 +459,11 @@ extern void ioreq_write32(struct adapter *adapter, u32 addr, u32 val);
extern uint async_read8(struct adapter *adapter, u32 addr, u8 *pbuff,
void (*_async_io_callback)(struct adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
void (*_async_io_callback)(struct adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
extern uint async_read16(struct adapter *adapter, u32 addr, u8 *pbuff,
void (*_async_io_callback)(struct adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
void (*_async_io_callback)(struct adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
extern uint async_read32(struct adapter *adapter, u32 addr, u8 *pbuff,
void (*_async_io_callback)(struct adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
void (*_async_io_callback)(struct adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
extern void async_read_mem(struct adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
extern void async_read_port(struct adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
@ -522,4 +522,3 @@ extern void dev_power_down(struct adapter * Adapter, u8 bpwrup);
rtw_read32(_a,_b)
#endif //_RTL8711_IO_H_

23
include/rtw_ioctl.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -64,11 +64,11 @@
#define OID_MP_SEG3 0xFF818700
#define OID_MP_SEG4 0xFF011100
#define DEBUG_OID(dbg, str) \
if((!dbg)) \
{ \
#define DEBUG_OID(dbg, str) \
if((!dbg)) \
{ \
RT_TRACE(_module_rtl871x_ioctl_c_,_drv_info_,("%s(%d): %s", __FUNCTION__, __LINE__, str)); \
}
}
enum oid_type
@ -80,10 +80,10 @@ enum oid_type
struct oid_funs_node {
unsigned int oid_start; //the starting number for OID
unsigned int oid_end; //the ending number for OID
struct oid_obj_priv *node_array;
struct oid_obj_priv *node_array;
unsigned int array_sz; //the size of node_array
int query_counter; //count the number of query hits for this segment
int set_counter; //count the number of set hits for this segment
int query_counter; //count the number of query hits for this segment
int set_counter; //count the number of set hits for this segment
};
struct oid_par_priv
@ -99,8 +99,8 @@ struct oid_par_priv
};
struct oid_obj_priv {
unsigned char dbg; // 0: without OID debug message 1: with OID debug message
NDIS_STATUS (*oidfuns)(struct oid_par_priv *poid_par_priv);
unsigned char dbg; // 0: without OID debug message 1: with OID debug message
NDIS_STATUS (*oidfuns)(struct oid_par_priv *poid_par_priv);
};
#if defined(CONFIG_WIRELESS_EXT)
@ -116,7 +116,7 @@ extern NDIS_STATUS drv_query_info(
OUT u32* BytesNeeded
);
extern NDIS_STATUS drv_set_info(
extern NDIS_STATUS drv_set_info(
IN _nic_hdl MiniportAdapterContext,
IN NDIS_OID Oid,
IN void * InformationBuffer,
@ -126,4 +126,3 @@ extern NDIS_STATUS drv_set_info(
);
#endif // #ifndef __INC_CEINFO_

3
include/rtw_ioctl_query.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -25,4 +25,3 @@
#endif

11
include/rtw_ioctl_rtl.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -24,7 +24,7 @@
#include <osdep_service.h>
#include <drv_types.h>
//************** oid_rtl_seg_01_01 **************
//************** oid_rtl_seg_01_01 **************
NDIS_STATUS oid_rt_get_signal_quality_hdl(struct oid_par_priv* poid_par_priv);//84
NDIS_STATUS oid_rt_get_small_packet_crc_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_get_middle_packet_crc_hdl(struct oid_par_priv* poid_par_priv);
@ -63,17 +63,17 @@ NDIS_STATUS oid_rt_wireless_mode_for_scan_list_hdl(struct oid_par_priv* poid_par
NDIS_STATUS oid_rt_get_bss_wireless_mode_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_scan_with_magic_packet_hdl(struct oid_par_priv* poid_par_priv);
//************** oid_rtl_seg_01_03 section start **************
//************** oid_rtl_seg_01_03 section start **************
NDIS_STATUS oid_rt_ap_get_associated_station_list_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_ap_switch_into_ap_mode_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_ap_supported_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_ap_set_passphrase_hdl(struct oid_par_priv* poid_par_priv);
// oid_rtl_seg_01_11
// oid_rtl_seg_01_11
NDIS_STATUS oid_rt_pro_rf_write_registry_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_pro_rf_read_registry_hdl(struct oid_par_priv* poid_par_priv);
//************** oid_rtl_seg_03_00 section start **************
//************** oid_rtl_seg_03_00 section start **************
NDIS_STATUS oid_rt_get_connect_state_hdl(struct oid_par_priv* poid_par_priv);
NDIS_STATUS oid_rt_set_default_key_id_hdl(struct oid_par_priv* poid_par_priv);
@ -81,4 +81,3 @@ NDIS_STATUS oid_rt_set_default_key_id_hdl(struct oid_par_priv* poid_par_priv);
#endif

3
include/rtw_ioctl_set.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -53,4 +53,3 @@ int rtw_set_channel_plan(struct adapter *adapter, u8 channel_plan);
int rtw_set_country(struct adapter *adapter, const char *country_code);
#endif

277
include/rtw_iol.h
View file

@ -1,139 +1,138 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTW_IOL_H_
#define __RTW_IOL_H_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
struct xmit_frame *rtw_IOL_accquire_xmit_frame(struct adapter *adapter);
int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len);
int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary);
int rtw_IOL_exec_cmds_sync(struct adapter *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);
bool rtw_IOL_applied(struct adapter *adapter);
int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us);
int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms);
int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame);
#ifdef CONFIG_IOL_NEW_GENERATION
#define IOREG_CMD_END_LEN 4
struct ioreg_cfg{
u8 length;
u8 cmd_id;
u16 address;
u32 data;
u32 mask;
};
enum ioreg_cmd{
IOREG_CMD_LLT = 0x01,
IOREG_CMD_REFUSE = 0x02,
IOREG_CMD_EFUSE_PATH = 0x03,
IOREG_CMD_WB_REG = 0x04,
IOREG_CMD_WW_REG = 0x05,
IOREG_CMD_WD_REG = 0x06,
IOREG_CMD_W_RF = 0x07,
IOREG_CMD_DELAY_US = 0x10,
IOREG_CMD_DELAY_MS = 0x11,
IOREG_CMD_END = 0xFF,
};
void read_efuse_from_txpktbuf(struct adapter *adapter, int bcnhead, u8 *content, u16 *size);
int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, u8 mask);
int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, u16 mask);
int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, u32 mask);
int _rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, u16 addr, u32 value, u32 mask);
#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value,mask) _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value) ,(mask))
#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value,mask) _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value),(mask))
#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value,mask) _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value),(mask))
#define rtw_IOL_append_WRF_cmd(xmit_frame, rf_path, addr, value,mask) _rtw_IOL_append_WRF_cmd((xmit_frame),(rf_path), (addr), (value),(mask))
u8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame);
void rtw_IOL_cmd_buf_dump(struct adapter *Adapter,int buf_len,u8 *pbuf);
#ifdef CONFIG_IOL_IOREG_CFG_DBG
struct cmd_cmp{
u16 addr;
u32 value;
};
#endif
#else //CONFIG_IOL_NEW_GENERATION
typedef struct _io_offload_cmd {
u8 rsvd0;
u8 cmd;
u16 address;
u32 value;
} IO_OFFLOAD_CMD, IOL_CMD;
#define IOL_CMD_LLT 0x00
//#define IOL_CMD_R_EFUSE 0x01
#define IOL_CMD_WB_REG 0x02
#define IOL_CMD_WW_REG 0x03
#define IOL_CMD_WD_REG 0x04
//#define IOL_CMD_W_RF 0x05
#define IOL_CMD_DELAY_US 0x80
#define IOL_CMD_DELAY_MS 0x81
//#define IOL_CMD_DELAY_S 0x82
#define IOL_CMD_END 0x83
/*****************************************************
CMD Address Value
(B1) (B2/B3:H/L addr) (B4:B7 : MSB:LSB)
******************************************************
IOL_CMD_LLT - B7: PGBNDY
//IOL_CMD_R_EFUSE - -
IOL_CMD_WB_REG 0x0~0xFFFF B7
IOL_CMD_WW_REG 0x0~0xFFFF B6~B7
IOL_CMD_WD_REG 0x0~0xFFFF B4~B7
//IOL_CMD_W_RF RF Reg B5~B7
IOL_CMD_DELAY_US - B6~B7
IOL_CMD_DELAY_MS - B6~B7
//IOL_CMD_DELAY_S - B6~B7
IOL_CMD_END - -
******************************************************/
int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value);
int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value);
int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value);
int rtw_IOL_exec_cmd_array_sync(struct adapter *adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms);
int rtw_IOL_exec_empty_cmds_sync(struct adapter *adapter, u32 max_wating_ms);
#ifdef DBG_IO
int dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line);
int dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line);
int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line);
#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__)
#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__)
#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__)
#else
#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value))
#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value))
#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value))
#endif // DBG_IO
#endif // CONFIG_IOL_NEW_GENERATION
#endif //__RTW_IOL_H_
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTW_IOL_H_
#define __RTW_IOL_H_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
struct xmit_frame *rtw_IOL_accquire_xmit_frame(struct adapter *adapter);
int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len);
int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary);
int rtw_IOL_exec_cmds_sync(struct adapter *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);
bool rtw_IOL_applied(struct adapter *adapter);
int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us);
int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms);
int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame);
#ifdef CONFIG_IOL_NEW_GENERATION
#define IOREG_CMD_END_LEN 4
struct ioreg_cfg{
u8 length;
u8 cmd_id;
u16 address;
u32 data;
u32 mask;
};
enum ioreg_cmd{
IOREG_CMD_LLT = 0x01,
IOREG_CMD_REFUSE = 0x02,
IOREG_CMD_EFUSE_PATH = 0x03,
IOREG_CMD_WB_REG = 0x04,
IOREG_CMD_WW_REG = 0x05,
IOREG_CMD_WD_REG = 0x06,
IOREG_CMD_W_RF = 0x07,
IOREG_CMD_DELAY_US = 0x10,
IOREG_CMD_DELAY_MS = 0x11,
IOREG_CMD_END = 0xFF,
};
void read_efuse_from_txpktbuf(struct adapter *adapter, int bcnhead, u8 *content, u16 *size);
int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, u8 mask);
int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, u16 mask);
int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, u32 mask);
int _rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, u16 addr, u32 value, u32 mask);
#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value,mask) _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value) ,(mask))
#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value,mask) _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value),(mask))
#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value,mask) _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value),(mask))
#define rtw_IOL_append_WRF_cmd(xmit_frame, rf_path, addr, value,mask) _rtw_IOL_append_WRF_cmd((xmit_frame),(rf_path), (addr), (value),(mask))
u8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame);
void rtw_IOL_cmd_buf_dump(struct adapter *Adapter,int buf_len,u8 *pbuf);
#ifdef CONFIG_IOL_IOREG_CFG_DBG
struct cmd_cmp{
u16 addr;
u32 value;
};
#endif
#else //CONFIG_IOL_NEW_GENERATION
typedef struct _io_offload_cmd {
u8 rsvd0;
u8 cmd;
u16 address;
u32 value;
} IO_OFFLOAD_CMD, IOL_CMD;
#define IOL_CMD_LLT 0x00
//#define IOL_CMD_R_EFUSE 0x01
#define IOL_CMD_WB_REG 0x02
#define IOL_CMD_WW_REG 0x03
#define IOL_CMD_WD_REG 0x04
//#define IOL_CMD_W_RF 0x05
#define IOL_CMD_DELAY_US 0x80
#define IOL_CMD_DELAY_MS 0x81
//#define IOL_CMD_DELAY_S 0x82
#define IOL_CMD_END 0x83
/*****************************************************
CMD Address Value
(B1) (B2/B3:H/L addr) (B4:B7 : MSB:LSB)
******************************************************
IOL_CMD_LLT - B7: PGBNDY
//IOL_CMD_R_EFUSE - -
IOL_CMD_WB_REG 0x0~0xFFFF B7
IOL_CMD_WW_REG 0x0~0xFFFF B6~B7
IOL_CMD_WD_REG 0x0~0xFFFF B4~B7
//IOL_CMD_W_RF RF Reg B5~B7
IOL_CMD_DELAY_US - B6~B7
IOL_CMD_DELAY_MS - B6~B7
//IOL_CMD_DELAY_S - B6~B7
IOL_CMD_END - -
******************************************************/
int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value);
int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value);
int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value);
int rtw_IOL_exec_cmd_array_sync(struct adapter *adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms);
int rtw_IOL_exec_empty_cmds_sync(struct adapter *adapter, u32 max_wating_ms);
#ifdef DBG_IO
int dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line);
int dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line);
int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line);
#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__)
#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__)
#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__)
#else
#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value))
#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value))
#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value))
#endif // DBG_IO
#endif // CONFIG_IOL_NEW_GENERATION
#endif //__RTW_IOL_H_

437
include/rtw_led.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -16,222 +16,221 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTW_LED_H_
#define __RTW_LED_H_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#define MSECS(t) (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000)
#define LED_BLINK_NORMAL_INTERVAL 100
#define LED_BLINK_SLOWLY_INTERVAL 200
#define LED_BLINK_LONG_INTERVAL 400
#define LED_BLINK_NO_LINK_INTERVAL_ALPHA 1000
#define LED_BLINK_LINK_INTERVAL_ALPHA 500 //500
#define LED_BLINK_SCAN_INTERVAL_ALPHA 180 //150
#define LED_BLINK_FASTER_INTERVAL_ALPHA 50
#define LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA 5000
#define LED_BLINK_NORMAL_INTERVAL_NETTRONIX 100
#define LED_BLINK_SLOWLY_INTERVAL_NETTRONIX 2000
#define LED_BLINK_SLOWLY_INTERVAL_PORNET 1000
#define LED_BLINK_NORMAL_INTERVAL_PORNET 100
#define LED_BLINK_FAST_INTERVAL_BITLAND 30
// 060403, rcnjko: Customized for AzWave.
#define LED_CM2_BLINK_ON_INTERVAL 250
#define LED_CM2_BLINK_OFF_INTERVAL 4750
#define LED_CM8_BLINK_INTERVAL 500 //for QMI
#define LED_CM8_BLINK_OFF_INTERVAL 3750 //for QMI
// 080124, lanhsin: Customized for RunTop
#define LED_RunTop_BLINK_INTERVAL 300
// 060421, rcnjko: Customized for Sercomm Printer Server case.
#define LED_CM3_BLINK_INTERVAL 1500
typedef enum _LED_CTL_MODE{
LED_CTL_POWER_ON = 1,
LED_CTL_LINK = 2,
LED_CTL_NO_LINK = 3,
LED_CTL_TX = 4,
LED_CTL_RX = 5,
LED_CTL_SITE_SURVEY = 6,
LED_CTL_POWER_OFF = 7,
LED_CTL_START_TO_LINK = 8,
LED_CTL_START_WPS = 9,
LED_CTL_STOP_WPS = 10,
LED_CTL_START_WPS_BOTTON = 11, //added for runtop
LED_CTL_STOP_WPS_FAIL = 12, //added for ALPHA
LED_CTL_STOP_WPS_FAIL_OVERLAP = 13, //added for BELKIN
LED_CTL_CONNECTION_NO_TRANSFER = 14,
}LED_CTL_MODE;
typedef enum _LED_STATE_871x{
LED_UNKNOWN = 0,
RTW_LED_ON = 1,
RTW_LED_OFF = 2,
LED_BLINK_NORMAL = 3,
LED_BLINK_SLOWLY = 4,
LED_BLINK_POWER_ON = 5,
LED_BLINK_SCAN = 6, // LED is blinking during scanning period, the # of times to blink is depend on time for scanning.
LED_BLINK_NO_LINK = 7, // LED is blinking during no link state.
LED_BLINK_StartToBlink = 8,// Customzied for Sercomm Printer Server case
LED_BLINK_TXRX = 9,
LED_BLINK_WPS = 10, // LED is blinkg during WPS communication
LED_BLINK_WPS_STOP = 11, //for ALPHA
LED_BLINK_WPS_STOP_OVERLAP = 12, //for BELKIN
LED_BLINK_RUNTOP = 13, // Customized for RunTop
LED_BLINK_CAMEO = 14,
LED_BLINK_XAVI = 15,
LED_BLINK_ALWAYS_ON = 16,
}LED_STATE_871x;
typedef enum _LED_PIN_871x{
LED_PIN_NULL = 0,
LED_PIN_LED0 = 1,
LED_PIN_LED1 = 2,
LED_PIN_LED2 = 3,
LED_PIN_GPIO0 = 4,
}LED_PIN_871x;
typedef struct _LED_871x{
struct adapter *padapter;
LED_PIN_871x LedPin; // Identify how to implement this SW led.
LED_STATE_871x CurrLedState; // Current LED state.
LED_STATE_871x BlinkingLedState; // Next state for blinking, either RTW_LED_ON or RTW_LED_OFF are.
u8 bLedOn; // true if LED is ON, false if LED is OFF.
u8 bLedBlinkInProgress; // true if it is blinking, false o.w..
u8 bLedWPSBlinkInProgress;
u32 BlinkTimes; // Number of times to toggle led state for blinking.
_timer BlinkTimer; // Timer object for led blinking.
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
u8 bSWLedCtrl;
// ALPHA, added by chiyoko, 20090106
u8 bLedNoLinkBlinkInProgress;
u8 bLedLinkBlinkInProgress;
u8 bLedStartToLinkBlinkInProgress;
u8 bLedScanBlinkInProgress;
******************************************************************************/
#ifndef __RTW_LED_H_
#define __RTW_LED_H_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#define MSECS(t) (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000)
#define LED_BLINK_NORMAL_INTERVAL 100
#define LED_BLINK_SLOWLY_INTERVAL 200
#define LED_BLINK_LONG_INTERVAL 400
#define LED_BLINK_NO_LINK_INTERVAL_ALPHA 1000
#define LED_BLINK_LINK_INTERVAL_ALPHA 500 //500
#define LED_BLINK_SCAN_INTERVAL_ALPHA 180 //150
#define LED_BLINK_FASTER_INTERVAL_ALPHA 50
#define LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA 5000
#define LED_BLINK_NORMAL_INTERVAL_NETTRONIX 100
#define LED_BLINK_SLOWLY_INTERVAL_NETTRONIX 2000
#define LED_BLINK_SLOWLY_INTERVAL_PORNET 1000
#define LED_BLINK_NORMAL_INTERVAL_PORNET 100
#define LED_BLINK_FAST_INTERVAL_BITLAND 30
// 060403, rcnjko: Customized for AzWave.
#define LED_CM2_BLINK_ON_INTERVAL 250
#define LED_CM2_BLINK_OFF_INTERVAL 4750
#define LED_CM8_BLINK_INTERVAL 500 //for QMI
#define LED_CM8_BLINK_OFF_INTERVAL 3750 //for QMI
// 080124, lanhsin: Customized for RunTop
#define LED_RunTop_BLINK_INTERVAL 300
// 060421, rcnjko: Customized for Sercomm Printer Server case.
#define LED_CM3_BLINK_INTERVAL 1500
typedef enum _LED_CTL_MODE{
LED_CTL_POWER_ON = 1,
LED_CTL_LINK = 2,
LED_CTL_NO_LINK = 3,
LED_CTL_TX = 4,
LED_CTL_RX = 5,
LED_CTL_SITE_SURVEY = 6,
LED_CTL_POWER_OFF = 7,
LED_CTL_START_TO_LINK = 8,
LED_CTL_START_WPS = 9,
LED_CTL_STOP_WPS = 10,
LED_CTL_START_WPS_BOTTON = 11, //added for runtop
LED_CTL_STOP_WPS_FAIL = 12, //added for ALPHA
LED_CTL_STOP_WPS_FAIL_OVERLAP = 13, //added for BELKIN
LED_CTL_CONNECTION_NO_TRANSFER = 14,
}LED_CTL_MODE;
typedef enum _LED_STATE_871x{
LED_UNKNOWN = 0,
RTW_LED_ON = 1,
RTW_LED_OFF = 2,
LED_BLINK_NORMAL = 3,
LED_BLINK_SLOWLY = 4,
LED_BLINK_POWER_ON = 5,
LED_BLINK_SCAN = 6, // LED is blinking during scanning period, the # of times to blink is depend on time for scanning.
LED_BLINK_NO_LINK = 7, // LED is blinking during no link state.
LED_BLINK_StartToBlink = 8,// Customzied for Sercomm Printer Server case
LED_BLINK_TXRX = 9,
LED_BLINK_WPS = 10, // LED is blinkg during WPS communication
LED_BLINK_WPS_STOP = 11, //for ALPHA
LED_BLINK_WPS_STOP_OVERLAP = 12, //for BELKIN
LED_BLINK_RUNTOP = 13, // Customized for RunTop
LED_BLINK_CAMEO = 14,
LED_BLINK_XAVI = 15,
LED_BLINK_ALWAYS_ON = 16,
}LED_STATE_871x;
typedef enum _LED_PIN_871x{
LED_PIN_NULL = 0,
LED_PIN_LED0 = 1,
LED_PIN_LED1 = 2,
LED_PIN_LED2 = 3,
LED_PIN_GPIO0 = 4,
}LED_PIN_871x;
typedef struct _LED_871x{
struct adapter *padapter;
LED_PIN_871x LedPin; // Identify how to implement this SW led.
LED_STATE_871x CurrLedState; // Current LED state.
LED_STATE_871x BlinkingLedState; // Next state for blinking, either RTW_LED_ON or RTW_LED_OFF are.
u8 bLedOn; // true if LED is ON, false if LED is OFF.
u8 bLedBlinkInProgress; // true if it is blinking, false o.w..
u8 bLedWPSBlinkInProgress;
u32 BlinkTimes; // Number of times to toggle led state for blinking.
_timer BlinkTimer; // Timer object for led blinking.
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
u8 bSWLedCtrl;
// ALPHA, added by chiyoko, 20090106
u8 bLedNoLinkBlinkInProgress;
u8 bLedLinkBlinkInProgress;
u8 bLedStartToLinkBlinkInProgress;
u8 bLedScanBlinkInProgress;
#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
_workitem BlinkWorkItem; // Workitem used by BlinkTimer to manipulate H/W to blink LED.
#endif
#endif //defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#if defined(CONFIG_PCI_HCI)
u8 bLedSlowBlinkInProgress;//added by vivi, for led new mode
#endif
} LED_871x, *PLED_871x;
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#define IS_LED_WPS_BLINKING(_LED_871x) (((PLED_871x)_LED_871x)->CurrLedState==LED_BLINK_WPS \
|| ((PLED_871x)_LED_871x)->CurrLedState==LED_BLINK_WPS_STOP \
|| ((PLED_871x)_LED_871x)->bLedWPSBlinkInProgress)
#define IS_LED_BLINKING(_LED_871x) (((PLED_871x)_LED_871x)->bLedWPSBlinkInProgress \
||((PLED_871x)_LED_871x)->bLedScanBlinkInProgress)
//================================================================================
// LED customization.
//================================================================================
typedef enum _LED_STRATEGY_871x{
SW_LED_MODE0 = 0, // SW control 1 LED via GPIO0. It is default option.
SW_LED_MODE1= 1, // 2 LEDs, through LED0 and LED1. For ALPHA.
SW_LED_MODE2 = 2, // SW control 1 LED via GPIO0, customized for AzWave 8187 minicard.
SW_LED_MODE3 = 3, // SW control 1 LED via GPIO0, customized for Sercomm Printer Server case.
SW_LED_MODE4 = 4, //for Edimax / Belkin
SW_LED_MODE5 = 5, //for Sercomm / Belkin
SW_LED_MODE6 = 6, //for 88CU minicard, porting from ce SW_LED_MODE7
HW_LED = 50, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes, see MAC.CONFIG1 for details.)
LED_ST_NONE = 99,
}LED_STRATEGY_871x, *PLED_STRATEGY_871x;
void
LedControl871x(
struct adapter *padapter,
LED_CTL_MODE LedAction
);
#endif //defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#if defined(CONFIG_PCI_HCI)
//================================================================================
// LED customization.
//================================================================================
typedef enum _LED_STRATEGY_871x{
SW_LED_MODE0 = 0, // SW control 1 LED via GPIO0. It is default option.
SW_LED_MODE1 = 1, // SW control for PCI Express
SW_LED_MODE2 = 2, // SW control for Cameo.
SW_LED_MODE3 = 3, // SW contorl for RunTop.
SW_LED_MODE4 = 4, // SW control for Netcore
SW_LED_MODE5 = 5, //added by vivi, for led new mode, DLINK
SW_LED_MODE6 = 6, //added by vivi, for led new mode, PRONET
SW_LED_MODE7 = 7, //added by chiyokolin, for Lenovo, PCI Express Minicard Spec Rev.1.2 spec
SW_LED_MODE8 = 8, //added by chiyokolin, for QMI
SW_LED_MODE9 = 9, //added by chiyokolin, for BITLAND, PCI Express Minicard Spec Rev.1.1
SW_LED_MODE10 = 10, //added by chiyokolin, for Edimax-ASUS
HW_LED = 50, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
LED_ST_NONE = 99,
}LED_STRATEGY_871x, *PLED_STRATEGY_871x;
#endif //defined(CONFIG_PCI_HCI)
struct led_priv{
/* add for led controll */
LED_871x SwLed0;
LED_871x SwLed1;
LED_STRATEGY_871x LedStrategy;
u8 bRegUseLed;
void (*LedControlHandler)(struct adapter *padapter, LED_CTL_MODE LedAction);
/* add for led controll */
};
#ifdef CONFIG_SW_LED
#define rtw_led_control(adapter, LedAction) \
do { \
if((adapter)->ledpriv.LedControlHandler) \
(adapter)->ledpriv.LedControlHandler((adapter), (LedAction)); \
} while(0)
#else //CONFIG_SW_LED
#define rtw_led_control(adapter, LedAction)
#endif //CONFIG_SW_LED
void BlinkTimerCallback(void *data);
void BlinkWorkItemCallback(struct work_struct *work);
void ResetLedStatus(PLED_871x pLed);
void
InitLed871x(
struct adapter *padapter,
PLED_871x pLed,
LED_PIN_871x LedPin
);
void
DeInitLed871x(
PLED_871x pLed
);
//hal...
extern void BlinkHandler(PLED_871x pLed);
#endif //__RTW_LED_H_
_workitem BlinkWorkItem; // Workitem used by BlinkTimer to manipulate H/W to blink LED.
#endif
#endif //defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#if defined(CONFIG_PCI_HCI)
u8 bLedSlowBlinkInProgress;//added by vivi, for led new mode
#endif
} LED_871x, *PLED_871x;
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#define IS_LED_WPS_BLINKING(_LED_871x) (((PLED_871x)_LED_871x)->CurrLedState==LED_BLINK_WPS \
|| ((PLED_871x)_LED_871x)->CurrLedState==LED_BLINK_WPS_STOP \
|| ((PLED_871x)_LED_871x)->bLedWPSBlinkInProgress)
#define IS_LED_BLINKING(_LED_871x) (((PLED_871x)_LED_871x)->bLedWPSBlinkInProgress \
||((PLED_871x)_LED_871x)->bLedScanBlinkInProgress)
//================================================================================
// LED customization.
//================================================================================
typedef enum _LED_STRATEGY_871x{
SW_LED_MODE0 = 0, // SW control 1 LED via GPIO0. It is default option.
SW_LED_MODE1= 1, // 2 LEDs, through LED0 and LED1. For ALPHA.
SW_LED_MODE2 = 2, // SW control 1 LED via GPIO0, customized for AzWave 8187 minicard.
SW_LED_MODE3 = 3, // SW control 1 LED via GPIO0, customized for Sercomm Printer Server case.
SW_LED_MODE4 = 4, //for Edimax / Belkin
SW_LED_MODE5 = 5, //for Sercomm / Belkin
SW_LED_MODE6 = 6, //for 88CU minicard, porting from ce SW_LED_MODE7
HW_LED = 50, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes, see MAC.CONFIG1 for details.)
LED_ST_NONE = 99,
}LED_STRATEGY_871x, *PLED_STRATEGY_871x;
void
LedControl871x(
struct adapter *padapter,
LED_CTL_MODE LedAction
);
#endif //defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#if defined(CONFIG_PCI_HCI)
//================================================================================
// LED customization.
//================================================================================
typedef enum _LED_STRATEGY_871x{
SW_LED_MODE0 = 0, // SW control 1 LED via GPIO0. It is default option.
SW_LED_MODE1 = 1, // SW control for PCI Express
SW_LED_MODE2 = 2, // SW control for Cameo.
SW_LED_MODE3 = 3, // SW contorl for RunTop.
SW_LED_MODE4 = 4, // SW control for Netcore
SW_LED_MODE5 = 5, //added by vivi, for led new mode, DLINK
SW_LED_MODE6 = 6, //added by vivi, for led new mode, PRONET
SW_LED_MODE7 = 7, //added by chiyokolin, for Lenovo, PCI Express Minicard Spec Rev.1.2 spec
SW_LED_MODE8 = 8, //added by chiyokolin, for QMI
SW_LED_MODE9 = 9, //added by chiyokolin, for BITLAND, PCI Express Minicard Spec Rev.1.1
SW_LED_MODE10 = 10, //added by chiyokolin, for Edimax-ASUS
HW_LED = 50, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
LED_ST_NONE = 99,
}LED_STRATEGY_871x, *PLED_STRATEGY_871x;
#endif //defined(CONFIG_PCI_HCI)
struct led_priv{
/* add for led controll */
LED_871x SwLed0;
LED_871x SwLed1;
LED_STRATEGY_871x LedStrategy;
u8 bRegUseLed;
void (*LedControlHandler)(struct adapter *padapter, LED_CTL_MODE LedAction);
/* add for led controll */
};
#ifdef CONFIG_SW_LED
#define rtw_led_control(adapter, LedAction) \
do { \
if((adapter)->ledpriv.LedControlHandler) \
(adapter)->ledpriv.LedControlHandler((adapter), (LedAction)); \
} while(0)
#else //CONFIG_SW_LED
#define rtw_led_control(adapter, LedAction)
#endif //CONFIG_SW_LED
void BlinkTimerCallback(void *data);
void BlinkWorkItemCallback(struct work_struct *work);
void ResetLedStatus(PLED_871x pLed);
void
InitLed871x(
struct adapter *padapter,
PLED_871x pLed,
LED_PIN_871x LedPin
);
void
DeInitLed871x(
PLED_871x pLed
);
//hal...
extern void BlinkHandler(PLED_871x pLed);
#endif //__RTW_LED_H_

61
include/rtw_mlme.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -38,7 +38,7 @@
// Commented by Albert 20101105
// Increase the scanning timeout because of increasing the SURVEY_TO value.
#define SCANNING_TIMEOUT 8000
#define SCANNING_TIMEOUT 8000
#define SCAN_INTERVAL (30) // unit:2sec, 30*2=60sec
@ -48,10 +48,10 @@
#define SCANQUEUE_LIFETIME 20 // unit:sec
#endif
#define WIFI_NULL_STATE 0x00000000
#define WIFI_NULL_STATE 0x00000000
#define WIFI_ASOC_STATE 0x00000001 // Under Linked state...
#define WIFI_REASOC_STATE 0x00000002
#define WIFI_REASOC_STATE 0x00000002
#define WIFI_SLEEP_STATE 0x00000004
#define WIFI_STATION_STATE 0x00000008
@ -211,7 +211,7 @@ struct wifi_display_info{
u8 wfd_pc; // WFD preferred connection
// 0 -> Prefer to use the P2P for WFD connection on peer side.
// 1 -> Prefer to use the TDLS for WFD connection on peer side.
u8 wfd_device_type; // WFD Device Type
// 0 -> WFD Source Device
// 1 -> WFD Primary Sink Device
@ -230,7 +230,7 @@ struct tx_provdisc_req_info{
struct rx_provdisc_req_info{ //When peer device issue prov_disc_req first, we should store the following informations
u8 peerDevAddr[ ETH_ALEN ]; // Peer device address
u8 strconfig_method_desc_of_prov_disc_req[4]; // description for the config method located in the provisioning discovery request frame.
u8 strconfig_method_desc_of_prov_disc_req[4]; // description for the config method located in the provisioning discovery request frame.
// The UI must know this information to know which config method the remote p2p device is requiring.
};
@ -269,7 +269,7 @@ struct wifidirect_info{
struct adapter* padapter;
_timer find_phase_timer;
_timer restore_p2p_state_timer;
// Used to do the scanning. After confirming the peer is availalble, the driver transmits the P2P frame to peer.
_timer pre_tx_scan_timer;
_timer reset_ch_sitesurvey;
@ -289,11 +289,11 @@ struct wifidirect_info{
struct scan_limit_info p2p_info; // Used for get the limit scan channel from the P2P negotiation handshake
#ifdef CONFIG_WFD
struct wifi_display_info *wfd_info;
#endif
#endif
enum P2P_ROLE role;
enum P2P_STATE pre_p2p_state;
enum P2P_STATE p2p_state;
u8 device_addr[ETH_ALEN]; // The device address should be the mac address of this device.
u8 device_addr[ETH_ALEN]; // The device address should be the mac address of this device.
u8 interface_addr[ETH_ALEN];
u8 social_chan[4];
u8 listen_channel;
@ -314,8 +314,8 @@ struct wifidirect_info{
u8 negotiation_dialog_token;
u8 nego_ssid[ WLAN_SSID_MAXLEN ]; // SSID information for group negotitation
u8 nego_ssidlen;
u8 p2p_group_ssid[WLAN_SSID_MAXLEN];
u8 p2p_group_ssid_len;
u8 p2p_group_ssid[WLAN_SSID_MAXLEN];
u8 p2p_group_ssid_len;
u8 persistent_supported; // Flag to know the persistent function should be supported or not.
// In the Sigma test, the Sigma will provide this enable from the sta_set_p2p CAPI.
// 0: disable
@ -337,7 +337,7 @@ struct wifidirect_info{
enum P2P_WPSINFO ui_got_wps_info; // This field will store the WPS value (PIN value or PBC) that UI had got from the user.
u16 supported_wps_cm; // This field describes the WPS config method which this driver supported.
// The value should be the combination of config method defined in page104 of WPS v2.0 spec.
// The value should be the combination of config method defined in page104 of WPS v2.0 spec.
u8 external_uuid; // UUID flag
u8 uuid[16]; // UUID
uint channel_list_attr_len; // This field will contain the length of body of P2P Channel List attribute of group negotitation response frame.
@ -388,7 +388,7 @@ struct tdls_info{
u8 enable;
#ifdef CONFIG_WFD
struct wifi_display_info *wfd_info;
#endif
#endif
};
struct mlme_priv {
@ -450,7 +450,7 @@ struct mlme_priv {
int num_sta_no_ht;
/* Number of HT AP/stations 20 MHz */
//int num_sta_ht_20mhz;
//int num_sta_ht_20mhz;
int num_FortyMHzIntolerant;
@ -464,9 +464,9 @@ struct mlme_priv {
u8 acm_mask; // for wmm acm mask
u8 ChannelPlan;
RT_SCAN_TYPE scan_mode; // active: 1, passive: 0
RT_SCAN_TYPE scan_mode; // active: 1, passive: 0
//u8 probereq_wpsie[MAX_WPS_IE_LEN];//added in probe req
//u8 probereq_wpsie[MAX_WPS_IE_LEN];//added in probe req
//int probereq_wpsie_len;
u8 *wps_probe_req_ie;
u32 wps_probe_req_ie_len;
@ -495,17 +495,17 @@ struct mlme_priv {
/* Overlapping BSS information */
int olbc_ht;
#ifdef CONFIG_80211N_HT
u16 ht_op_mode;
#endif /* CONFIG_80211N_HT */
#endif /* CONFIG_80211N_HT */
u8 *assoc_req;
u32 assoc_req_len;
u8 *assoc_rsp;
u32 assoc_rsp_len;
u8 *wps_beacon_ie;
u8 *wps_beacon_ie;
//u8 *wps_probe_req_ie;
u8 *wps_probe_resp_ie;
u8 *wps_assoc_resp_ie; // for CONFIG_IOCTL_CFG80211, this IE could include p2p ie / wfd ie
@ -514,11 +514,11 @@ struct mlme_priv {
//u32 wps_probe_req_ie_len;
u32 wps_probe_resp_ie_len;
u32 wps_assoc_resp_ie_len; // for CONFIG_IOCTL_CFG80211, this IE len could include p2p ie / wfd ie
u8 *p2p_beacon_ie;
u8 *p2p_probe_req_ie;
u8 *p2p_probe_resp_ie;
u8 *p2p_go_probe_resp_ie; //for GO
u8 *p2p_probe_resp_ie;
u8 *p2p_go_probe_resp_ie; //for GO
u8 *p2p_assoc_req_ie;
u32 p2p_beacon_ie_len;
@ -538,19 +538,19 @@ struct mlme_priv {
u32 wps_p2p_assoc_resp_ie_len;
#endif
*/
_lock bcn_update_lock;
u8 update_bcn;
#endif //#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211)
u8 *wfd_beacon_ie;
u8 *wfd_probe_req_ie;
u8 *wfd_probe_resp_ie;
u8 *wfd_go_probe_resp_ie; //for GO
u8 *wfd_probe_resp_ie;
u8 *wfd_go_probe_resp_ie; //for GO
u8 *wfd_assoc_req_ie;
u32 wfd_beacon_ie_len;
@ -612,8 +612,8 @@ struct hostapd_priv
#ifdef CONFIG_HOSTAPD_MLME
struct net_device *pmgnt_netdev;
struct usb_anchor anchored;
#endif
#endif
};
extern int hostapd_mode_init(struct adapter *padapter);
@ -846,4 +846,3 @@ void rtw_proxim_disable(struct adapter *padapter);
void rtw_proxim_send_packet(struct adapter *padapter,u8 *pbuf,u16 len,u8 hw_rate);
#endif //CONFIG_INTEL_PROXIM
#endif //__RTL871X_MLME_H_

199
include/rtw_mlme_ext.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -49,7 +49,7 @@
#else
#define ROAMING_LIMIT 8
#endif
//#define IOCMD_REG0 0x10250370
//#define IOCMD_REG0 0x10250370
//#define IOCMD_REG1 0x10250374
//#define IOCMD_REG2 0x10250378
@ -65,32 +65,32 @@
// BB ODM section BIT 0-15
#define DYNAMIC_BB_DIG BIT(0)
#define DYNAMIC_BB_RA_MASK BIT(1)
#define DYNAMIC_BB_DYNAMIC_TXPWR BIT(2)
#define DYNAMIC_BB_BB_FA_CNT BIT(3)
#define DYNAMIC_BB_DYNAMIC_TXPWR BIT(2)
#define DYNAMIC_BB_BB_FA_CNT BIT(3)
#define DYNAMIC_BB_RSSI_MONITOR BIT(4)
#define DYNAMIC_BB_CCK_PD BIT(5)
#define DYNAMIC_BB_ANT_DIV BIT(6)
#define DYNAMIC_BB_PWR_SAVE BIT(7)
#define DYNAMIC_BB_PWR_TRAIN BIT(8)
#define DYNAMIC_BB_RATE_ADAPTIVE BIT(9)
#define DYNAMIC_BB_PATH_DIV BIT(10)
#define DYNAMIC_BB_PSD BIT(11)
#define DYNAMIC_BB_RSSI_MONITOR BIT(4)
#define DYNAMIC_BB_CCK_PD BIT(5)
#define DYNAMIC_BB_ANT_DIV BIT(6)
#define DYNAMIC_BB_PWR_SAVE BIT(7)
#define DYNAMIC_BB_PWR_TRAIN BIT(8)
#define DYNAMIC_BB_RATE_ADAPTIVE BIT(9)
#define DYNAMIC_BB_PATH_DIV BIT(10)
#define DYNAMIC_BB_PSD BIT(11)
// MAC DM section BIT 16-23
#define DYNAMIC_MAC_EDCA_TURBO BIT(16)
#define DYNAMIC_MAC_EARLY_MODE BIT(17)
#define DYNAMIC_MAC_EDCA_TURBO BIT(16)
#define DYNAMIC_MAC_EARLY_MODE BIT(17)
// RF ODM section BIT 24-31
#define DYNAMIC_RF_TX_PWR_TRACK BIT(24)
#define DYNAMIC_RF_RX_GAIN_TRACK BIT(25)
#define DYNAMIC_RF_CALIBRATION BIT(26)
#define DYNAMIC_RF_TX_PWR_TRACK BIT(24)
#define DYNAMIC_RF_RX_GAIN_TRACK BIT(25)
#define DYNAMIC_RF_CALIBRATION BIT(26)
#define DYNAMIC_ALL_FUNC_ENABLE 0xFFFFFFF
#define DYNAMIC_ALL_FUNC_ENABLE 0xFFFFFFF
#define _HW_STATE_NOLINK_ 0x00
#define _HW_STATE_ADHOC_ 0x01
#define _HW_STATE_STATION_ 0x02
#define _HW_STATE_STATION_ 0x02
#define _HW_STATE_AP_ 0x03
@ -120,12 +120,12 @@ extern unsigned char REALTEK_96B_IE[];
//
// Channel Plan Type.
// Note:
// We just add new channel plan when the new channel plan is different from any of the following
// channel plan.
// Note:
// We just add new channel plan when the new channel plan is different from any of the following
// channel plan.
// If you just wnat to customize the acitions(scan period or join actions) about one of the channel plan,
// customize them in RT_CHANNEL_INFO in the RT_CHANNEL_LIST.
//
//
typedef enum _RT_CHANNEL_DOMAIN
{
//===== old channel plan mapping =====//
@ -252,31 +252,31 @@ enum Associated_AP
marvellAP = 3,
ralinkAP = 4,
realtekAP = 5,
airgocapAP = 6,
airgocapAP = 6,
unknownAP = 7,
maxAP,
};
typedef enum _HT_IOT_PEER
{
HT_IOT_PEER_UNKNOWN = 0,
HT_IOT_PEER_REALTEK = 1,
HT_IOT_PEER_REALTEK_92SE = 2,
HT_IOT_PEER_BROADCOM = 3,
HT_IOT_PEER_RALINK = 4,
HT_IOT_PEER_ATHEROS = 5,
HT_IOT_PEER_CISCO = 6,
HT_IOT_PEER_MERU = 7,
HT_IOT_PEER_MARVELL = 8,
HT_IOT_PEER_REALTEK_SOFTAP = 9,// peer is RealTek SOFT_AP, by Bohn, 2009.12.17
HT_IOT_PEER_SELF_SOFTAP = 10, // Self is SoftAP
HT_IOT_PEER_AIRGO = 11,
HT_IOT_PEER_INTEL = 12,
HT_IOT_PEER_RTK_APCLIENT = 13,
HT_IOT_PEER_REALTEK_81XX = 14,
HT_IOT_PEER_REALTEK_WOW = 15,
HT_IOT_PEER_TENDA = 16,
HT_IOT_PEER_MAX = 17
HT_IOT_PEER_UNKNOWN = 0,
HT_IOT_PEER_REALTEK = 1,
HT_IOT_PEER_REALTEK_92SE = 2,
HT_IOT_PEER_BROADCOM = 3,
HT_IOT_PEER_RALINK = 4,
HT_IOT_PEER_ATHEROS = 5,
HT_IOT_PEER_CISCO = 6,
HT_IOT_PEER_MERU = 7,
HT_IOT_PEER_MARVELL = 8,
HT_IOT_PEER_REALTEK_SOFTAP = 9,// peer is RealTek SOFT_AP, by Bohn, 2009.12.17
HT_IOT_PEER_SELF_SOFTAP = 10, // Self is SoftAP
HT_IOT_PEER_AIRGO = 11,
HT_IOT_PEER_INTEL = 12,
HT_IOT_PEER_RTK_APCLIENT = 13,
HT_IOT_PEER_REALTEK_81XX = 14,
HT_IOT_PEER_REALTEK_WOW = 15,
HT_IOT_PEER_TENDA = 16,
HT_IOT_PEER_MAX = 17
}HT_IOT_PEER_E, *PHTIOT_PEER_E;
@ -302,7 +302,7 @@ struct action_handler {
unsigned int (*func)(struct adapter *padapter, union recv_frame *precv_frame);
};
struct ss_res
struct ss_res
{
int state;
int bss_cnt;
@ -319,7 +319,7 @@ struct ss_res
//#define AD_HOC_MODE 0x04
//#define NO_LINK_MODE 0x00
#define WIFI_FW_NULL_STATE _HW_STATE_NOLINK_
#define WIFI_FW_NULL_STATE _HW_STATE_NOLINK_
#define WIFI_FW_STATION_STATE _HW_STATE_STATION_
#define WIFI_FW_AP_STATE _HW_STATE_AP_
#define WIFI_FW_ADHOC_STATE _HW_STATE_ADHOC_
@ -349,15 +349,15 @@ struct ss_res
// 13: Free TDLS sta
enum TDLS_option
{
TDLS_WRCR = 1,
TDLS_SD_PTI = 2,
TDLS_CS_OFF = 3,
TDLS_INIT_CH_SEN = 4,
TDLS_WRCR = 1,
TDLS_SD_PTI = 2,
TDLS_CS_OFF = 3,
TDLS_INIT_CH_SEN = 4,
TDLS_DONE_CH_SEN = 5,
TDLS_OFF_CH = 6,
TDLS_BASE_CH = 7,
TDLS_BASE_CH = 7,
TDLS_P_OFF_CH = 8,
TDLS_P_BASE_CH = 9,
TDLS_P_BASE_CH = 9,
TDLS_RS_RCR = 10,
TDLS_CKALV_PH1 = 11,
TDLS_CKALV_PH2 = 12,
@ -378,17 +378,17 @@ struct FW_Sta_Info
/*
* Usage:
* When one iface acted as AP mode and the other iface is STA mode and scanning,
* When one iface acted as AP mode and the other iface is STA mode and scanning,
* it should switch back to AP's operating channel periodically.
* Parameters info:
* When the driver scanned RTW_SCAN_NUM_OF_CH channels, it would switch back to AP's operating channel for
* RTW_STAY_AP_CH_MILLISECOND * SURVEY_TO milliseconds.
* Example:
* For chip supports 2.4G + 5GHz and AP mode is operating in channel 1,
* For chip supports 2.4G + 5GHz and AP mode is operating in channel 1,
* RTW_SCAN_NUM_OF_CH is 8, RTW_STAY_AP_CH_MILLISECOND is 3 and SURVEY_TO is 100.
* When it's STA mode gets set_scan command,
* it would
* 1. Doing the scan on channel 1.2.3.4.5.6.7.8
* When it's STA mode gets set_scan command,
* it would
* 1. Doing the scan on channel 1.2.3.4.5.6.7.8
* 2. Back to channel 1 for 300 milliseconds
* 3. Go through doing site survey on channel 9.10.11.36.40.44.48.52
* 4. Back to channel 1 for 300 milliseconds
@ -396,8 +396,8 @@ struct FW_Sta_Info
*/
#if defined CONFIG_STA_MODE_SCAN_UNDER_AP_MODE && defined CONFIG_CONCURRENT_MODE
#define RTW_SCAN_NUM_OF_CH 8
#define RTW_STAY_AP_CH_MILLISECOND 3 // this value is a multiplier,for example, when this value is 3, it would stay AP's op ch for
// 3 * SURVEY_TO millisecond.
#define RTW_STAY_AP_CH_MILLISECOND 3 // this value is a multiplier,for example, when this value is 3, it would stay AP's op ch for
// 3 * SURVEY_TO millisecond.
#endif //defined CONFIG_STA_MODE_SCAN_UNDER_AP_MODE && defined CONFIG_CONCURRENT_MODE
struct mlme_ext_info
@ -423,7 +423,7 @@ struct mlme_ext_info
u8 ERP_enable;
u8 ERP_IE;
u8 HT_enable;
u8 HT_caps_enable;
u8 HT_caps_enable;
u8 HT_info_enable;
u8 HT_protection;
u8 turboMode_cts2self;
@ -509,20 +509,20 @@ struct mlme_ext_priv
u64 mgnt_80211w_IPN;
u64 mgnt_80211w_IPN_rx;
#endif //CONFIG_IEEE80211W
//struct fw_priv fwpriv;
//struct fw_priv fwpriv;
unsigned char cur_channel;
unsigned char cur_bwmode;
unsigned char cur_ch_offset;//PRIME_CHNL_OFFSET
unsigned char cur_wireless_mode; // NETWORK_TYPE
unsigned char max_chan_nums;
RT_CHANNEL_INFO channel_set[MAX_CHANNEL_NUM];
struct p2p_channels channel_list;
unsigned char basicrate[NumRates];
unsigned char datarate[NumRates];
struct ss_res sitesurvey_res;
struct ss_res sitesurvey_res;
struct mlme_ext_info mlmext_info;//for sta/adhoc mode, including current scanning/connecting/connected related info.
//for ap mode, network includes ap's cap_info
_timer survey_timer;
@ -537,19 +537,19 @@ struct mlme_ext_priv
u8 tx_rate; // TXRATE when USERATE is set.
u32 retry; //retry for issue probereq
u64 TSFValue;
#ifdef CONFIG_AP_MODE
#ifdef CONFIG_AP_MODE
unsigned char bstart_bss;
#endif
#ifdef CONFIG_80211D
u8 update_channel_plan_by_ap_done;
#endif
//recv_decache check for Action_public frame
//recv_decache check for Action_public frame
u8 action_public_dialog_token;
u16 action_public_rxseq;
u16 action_public_rxseq;
#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
u8 active_keep_alive_check;
@ -810,7 +810,7 @@ int rtw_get_ch_setting_union(struct adapter *adapter, u8 *ch, u8 *bw, u8 *offset
struct cmd_hdl {
uint parmsize;
u8 (*h2cfuns)(struct adapter *padapter, u8 *pbuf);
u8 (*h2cfuns)(struct adapter *padapter, u8 *pbuf);
};
@ -827,7 +827,7 @@ u8 join_cmd_hdl(struct adapter *padapter, u8 *pbuf);
u8 disconnect_hdl(struct adapter *padapter, u8 *pbuf);
u8 createbss_hdl(struct adapter *padapter, u8 *pbuf);
u8 setopmode_hdl(struct adapter *padapter, u8 *pbuf);
u8 sitesurvey_cmd_hdl(struct adapter *padapter, u8 *pbuf);
u8 sitesurvey_cmd_hdl(struct adapter *padapter, u8 *pbuf);
u8 setauth_hdl(struct adapter *padapter, u8 *pbuf);
u8 setkey_hdl(struct adapter *padapter, u8 *pbuf);
u8 set_stakey_hdl(struct adapter *padapter, u8 *pbuf);
@ -864,7 +864,7 @@ static struct cmd_hdl wlancmds[] = {
GEN_MLME_EXT_HANDLER(0, NULL) /*10*/
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(sizeof (struct joinbss_parm), join_cmd_hdl) /*14*/
GEN_MLME_EXT_HANDLER(sizeof (struct disconnect_parm), disconnect_hdl)
GEN_MLME_EXT_HANDLER(sizeof (struct createbss_parm), createbss_hdl)
@ -896,7 +896,7 @@ static struct cmd_hdl wlancmds[] = {
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(sizeof(struct addBaReq_parm), add_ba_hdl)
GEN_MLME_EXT_HANDLER(sizeof(struct addBaReq_parm), add_ba_hdl)
GEN_MLME_EXT_HANDLER(sizeof(struct set_ch_parm), set_ch_hdl) /* 46 */
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
@ -905,7 +905,7 @@ static struct cmd_hdl wlancmds[] = {
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(0, NULL)
GEN_MLME_EXT_HANDLER(sizeof(struct Tx_Beacon_param), tx_beacon_hdl) /*55*/
GEN_MLME_EXT_HANDLER(0, mlme_evt_hdl) /*56*/
@ -929,13 +929,13 @@ struct C2HEvent_Header
unsigned int len:16;
unsigned int ID:8;
unsigned int seq:8;
#elif defined(CONFIG_BIG_ENDIAN)
unsigned int seq:8;
unsigned int ID:8;
unsigned int len:16;
#else
# error "Must be LITTLE or BIG Endian"
@ -953,39 +953,39 @@ enum rtw_c2h_event
{
GEN_EVT_CODE(_Read_MACREG)=0, /*0*/
GEN_EVT_CODE(_Read_BBREG),
GEN_EVT_CODE(_Read_RFREG),
GEN_EVT_CODE(_Read_EEPROM),
GEN_EVT_CODE(_Read_EFUSE),
GEN_EVT_CODE(_Read_RFREG),
GEN_EVT_CODE(_Read_EEPROM),
GEN_EVT_CODE(_Read_EFUSE),
GEN_EVT_CODE(_Read_CAM), /*5*/
GEN_EVT_CODE(_Get_BasicRate),
GEN_EVT_CODE(_Get_DataRate),
GEN_EVT_CODE(_Survey), /*8*/
GEN_EVT_CODE(_SurveyDone), /*9*/
GEN_EVT_CODE(_JoinBss) , /*10*/
GEN_EVT_CODE(_AddSTA),
GEN_EVT_CODE(_DelSTA),
GEN_EVT_CODE(_AtimDone) ,
GEN_EVT_CODE(_TX_Report),
GEN_EVT_CODE(_Get_BasicRate),
GEN_EVT_CODE(_Get_DataRate),
GEN_EVT_CODE(_Survey), /*8*/
GEN_EVT_CODE(_SurveyDone), /*9*/
GEN_EVT_CODE(_JoinBss) , /*10*/
GEN_EVT_CODE(_AddSTA),
GEN_EVT_CODE(_DelSTA),
GEN_EVT_CODE(_AtimDone) ,
GEN_EVT_CODE(_TX_Report),
GEN_EVT_CODE(_CCX_Report), /*15*/
GEN_EVT_CODE(_DTM_Report),
GEN_EVT_CODE(_TX_Rate_Statistics),
GEN_EVT_CODE(_C2HLBK),
GEN_EVT_CODE(_FWDBG),
GEN_EVT_CODE(_DTM_Report),
GEN_EVT_CODE(_TX_Rate_Statistics),
GEN_EVT_CODE(_C2HLBK),
GEN_EVT_CODE(_FWDBG),
GEN_EVT_CODE(_C2HFEEDBACK), /*20*/
GEN_EVT_CODE(_ADDBA),
GEN_EVT_CODE(_C2HBCN),
GEN_EVT_CODE(_ReportPwrState), //filen: only for PCIE, USB
GEN_EVT_CODE(_ReportPwrState), //filen: only for PCIE, USB
GEN_EVT_CODE(_CloseRF), //filen: only for PCIE, work around ASPM
MAX_C2HEVT
MAX_C2HEVT
};
#ifdef _RTW_MLME_EXT_C_
#ifdef _RTW_MLME_EXT_C_
static struct fwevent wlanevents[] =
static struct fwevent wlanevents[] =
{
{0, rtw_dummy_event_callback}, /*0*/
{0, rtw_dummy_event_callback}, /*0*/
{0, NULL},
{0, NULL},
{0, NULL},
@ -995,10 +995,10 @@ static struct fwevent wlanevents[] =
{0, NULL},
{0, &rtw_survey_event_callback}, /*8*/
{sizeof (struct surveydone_event), &rtw_surveydone_event_callback}, /*9*/
{0, &rtw_joinbss_event_callback}, /*10*/
{sizeof(struct stassoc_event), &rtw_stassoc_event_callback},
{sizeof(struct stadel_event), &rtw_stadel_event_callback},
{sizeof(struct stadel_event), &rtw_stadel_event_callback},
{0, &rtw_atimdone_event_callback},
{0, rtw_dummy_event_callback},
{0, NULL}, /*15*/
@ -1008,11 +1008,10 @@ static struct fwevent wlanevents[] =
{0, rtw_fwdbg_event_callback},
{0, NULL}, /*20*/
{0, NULL},
{0, NULL},
{0, NULL},
{0, &rtw_cpwm_event_callback},
};
#endif//_RTL8192C_CMD_C_
#endif

79
include/rtw_mp.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -88,19 +88,19 @@ typedef enum _ANTENNA_PATH{
ANTENNA_B ,
ANTENNA_BD ,
ANTENNA_BC ,
ANTENNA_BCD ,
ANTENNA_BCD ,
ANTENNA_A ,
ANTENNA_AD ,
ANTENNA_AC ,
ANTENNA_ACD ,
ANTENNA_ACD ,
ANTENNA_AB ,
ANTENNA_ABD ,
ANTENNA_ABC ,
ANTENNA_ABCD
ANTENNA_ABD ,
ANTENNA_ABC ,
ANTENNA_ABCD
} ANTENNA_PATH;
#define MAX_MP_XMITBUF_SZ 2048
#define MAX_MP_XMITBUF_SZ 2048
#define NR_MP_XMITFRAME 8
struct mp_xmit_frame
@ -167,28 +167,28 @@ struct mp_tx
#define u4Byte u32
#define s4Byte s32
#define u1Byte u8
#define pu1Byte u8*
#define pu1Byte u8*
#define u2Byte u16
#define pu2Byte u16*
#define pu2Byte u16*
#define u4Byte u32
#define pu4Byte u32*
#define pu4Byte u32*
#define u8Byte u64
#define pu8Byte u64*
#define pu8Byte u64*
#define s1Byte s8
#define ps1Byte s8*
#define ps1Byte s8*
#define s2Byte s16
#define ps2Byte s16*
#define ps2Byte s16*
#define s4Byte s32
#define ps4Byte s32*
#define ps4Byte s32*
#define s8Byte s64
#define ps8Byte s64*
#define ps8Byte s64*
#define UCHAR u8
#define USHORT u16
@ -214,7 +214,7 @@ typedef struct _MPT_CONTEXT
BOOLEAN MptH2cRspEvent;
BOOLEAN MptBtC2hEvent;
BOOLEAN bMPh2c_timeout;
/* 8190 PCI does not support NDIS_WORK_ITEM. */
// Work Item for Mass Production Test.
//NDIS_WORK_ITEM MptWorkItem;
@ -233,7 +233,7 @@ typedef struct _MPT_CONTEXT
// _TEST_MODE, defined in MPT_Req2.h
ULONG MptTestItem;
// Variable needed in each implementation of CurrMptAct.
ULONG MptActType; // Type of action performed in CurrMptAct.
ULONG MptActType; // Type of action performed in CurrMptAct.
// The Offset of IO operation is depend of MptActType.
ULONG MptIoOffset;
// The Value of IO operation is depend of MptActType.
@ -242,9 +242,9 @@ typedef struct _MPT_CONTEXT
ULONG MptRfPath;
WIRELESS_MODE MptWirelessModeToSw; // Wireless mode to switch.
u8 MptChannelToSw; // Channel to switch.
u8 MptInitGainToSet; // Initial gain to set.
//ULONG bMptAntennaA; // TRUE if we want to use antenna A.
u8 MptChannelToSw; // Channel to switch.
u8 MptInitGainToSet; // Initial gain to set.
//ULONG bMptAntennaA; // TRUE if we want to use antenna A.
ULONG MptBandWidth; // bandwidth to switch.
ULONG MptRateIndex; // rate index.
// Register value kept for Single Carrier Tx test.
@ -258,14 +258,14 @@ typedef struct _MPT_CONTEXT
ULONG MptRCR;
// TRUE if we only receive packets with specific pattern.
BOOLEAN bMptFilterPattern;
// Rx OK count, statistics used in Mass Production Test.
ULONG MptRxOkCnt;
// Rx CRC32 error count, statistics used in Mass Production Test.
ULONG MptRxCrcErrCnt;
// Rx OK count, statistics used in Mass Production Test.
ULONG MptRxOkCnt;
// Rx CRC32 error count, statistics used in Mass Production Test.
ULONG MptRxCrcErrCnt;
BOOLEAN bCckContTx; // TRUE if we are in CCK Continuous Tx test.
BOOLEAN bOfdmContTx; // TRUE if we are in OFDM Continuous Tx test.
BOOLEAN bStartContTx; // TRUE if we have start Continuous Tx test.
BOOLEAN bOfdmContTx; // TRUE if we are in OFDM Continuous Tx test.
BOOLEAN bStartContTx; // TRUE if we have start Continuous Tx test.
// TRUE if we are in Single Carrier Tx test.
BOOLEAN bSingleCarrier;
// TRUE if we are in Carrier Suppression Tx Test.
@ -288,19 +288,19 @@ typedef struct _MPT_CONTEXT
u8 backup0xc50;
u8 backup0xc58;
u8 backup0xc30;
u8 backup0x52_RF_A;
u8 backup0x52_RF_B;
u8 backup0x52_RF_A;
u8 backup0x52_RF_B;
u1Byte h2cReqNum;
u1Byte c2hBuf[20];
u1Byte btInBuf[100];
ULONG mptOutLen;
u1Byte mptOutBuf[100];
}MPT_CONTEXT, *PMPT_CONTEXT;
enum {
enum {
WRITE_REG = 1,
READ_REG,
WRITE_RF,
@ -377,7 +377,7 @@ struct mp_priv
u16 antenna_tx;
u16 antenna_rx;
// u8 curr_rfpath;
u8 check_mp_pkt;
u8 bSetTxPower;
@ -412,7 +412,7 @@ struct bb_reg_param {
};
//=======================================================================
#define LOWER _TRUE
#define LOWER _TRUE
#define RAISE _FALSE
/* Hardware Registers */
@ -521,7 +521,7 @@ typedef enum _POWER_MODE_ {
#define RPTMaxCount 0x000FFFFF;
// parameter 1 : BitMask
// bit 0 : OFDM PPDU
// bit 0 : OFDM PPDU
// bit 1 : OFDM False Alarm
// bit 2 : OFDM MPDU OK
// bit 3 : OFDM MPDU Fail
@ -560,15 +560,15 @@ typedef enum _ENCRY_CTRL_STATE_ {
SW_ENCRY_HW_DECRY //sw encryption & hw decryption
}ENCRY_CTRL_STATE;
#define Mac_OFDM_OK 0x00000000
#define Mac_OFDM_Fail 0x10000000
#define Mac_OFDM_FasleAlarm 0x20000000
#define Mac_OFDM_OK 0x00000000
#define Mac_OFDM_Fail 0x10000000
#define Mac_OFDM_FasleAlarm 0x20000000
#define Mac_CCK_OK 0x30000000
#define Mac_CCK_Fail 0x40000000
#define Mac_CCK_FasleAlarm 0x50000000
#define Mac_HT_OK 0x60000000
#define Mac_HT_OK 0x60000000
#define Mac_HT_Fail 0x70000000
#define Mac_HT_FasleAlarm 0x90000000
#define Mac_HT_FasleAlarm 0x90000000
#define Mac_DropPacket 0xA0000000
//=======================================================================
@ -673,4 +673,3 @@ void MP_PHY_SetRFPathSwitch(struct adapter *pAdapter ,BOOLEAN bMain);
void MPT_PwrCtlDM(struct adapter *padapter, u32 bstart);
#endif //_RTW_MP_H_

7
include/rtw_mp_ioctl.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -387,7 +387,7 @@ static struct oid_obj_priv oid_rtl_seg_87_12_00[]=
{1, &oid_rt_pro_read_efuse_hdl}, //0x05 Q OID_RT_PRO_READ_EFUSE
{1, &oid_rt_pro_write_efuse_hdl}, //0x06 S OID_RT_PRO_WRITE_EFUSE
{1, &oid_rt_pro_rw_efuse_pgpkt_hdl}, //0x07 Q,S
{1, &oid_rt_get_efuse_current_size_hdl}, //0x08 Q
{1, &oid_rt_get_efuse_current_size_hdl}, //0x08 Q
{1, &oid_rt_set_bandwidth_hdl}, //0x09
{1, &oid_rt_set_crystal_cap_hdl}, //0x0a
{1, &oid_rt_set_rx_packet_type_hdl}, //0x0b S
@ -528,7 +528,7 @@ enum RTL871X_MP_IOCTL_SUBCODE {
GEN_MP_IOCTL_SUBCODE(TRIGGER_GPIO),
GEN_MP_IOCTL_SUBCODE(SET_DM_BT), /*35*/
GEN_MP_IOCTL_SUBCODE(DEL_BA), /*36*/
GEN_MP_IOCTL_SUBCODE(GET_WIFI_STATUS), /*37*/
GEN_MP_IOCTL_SUBCODE(GET_WIFI_STATUS), /*37*/
MAX_MP_IOCTL_SUBCODE,
};
@ -592,4 +592,3 @@ extern struct mp_ioctl_handler mp_ioctl_hdl[];
#endif /* _RTW_MP_IOCTL_C_ */
#endif

731
include/rtw_mp_phy_regdef.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -27,18 +27,18 @@
* 3. PMAC/BB register bit mask.
* 4. RF reg bit mask.
* 5. Other BB/RF relative definition.
*
*
*
* Export: Constants, macro, functions(API), global variables(None).
*
* Abbrev:
* Abbrev:
*
* History:
* Data Who Remark
* Data Who Remark
* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
* 2. Reorganize code architecture.
* 09/25/2008 MH 1. Add RL6052 register definition
*
*
*****************************************************************************/
#ifndef __RTW_MP_PHY_REGDEF_H_
#define __RTW_MP_PHY_REGDEF_H_
@ -111,8 +111,8 @@
#define rFPGA0_RFTiming1 0x810 // Useless now
#define rFPGA0_RFTiming2 0x814
//#define rFPGA0_XC_RFTiming 0x818
//#define rFPGA0_XD_RFTiming 0x81c
//#define rFPGA0_XC_RFTiming 0x818
//#define rFPGA0_XD_RFTiming 0x81c
#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register
#define rFPGA0_XA_HSSIParameter2 0x824
@ -176,8 +176,8 @@
#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI
#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain
#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series
#define rCCK0_RxAGC2 0xa10 //AGC & DAGC
#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series
#define rCCK0_RxAGC2 0xa10 //AGC & DAGC
#define rCCK0_RxHP 0xa14
@ -188,10 +188,10 @@
#define rCCK0_TxFilter2 0xa24
#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3
#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report
#define rCCK0_TRSSIReport 0xa50
#define rCCK0_RxReport 0xa54 //0xa57
#define rCCK0_FACounterLower 0xa5c //0xa5b
#define rCCK0_FACounterUpper 0xa58 //0xa5c
#define rCCK0_TRSSIReport 0xa50
#define rCCK0_RxReport 0xa54 //0xa57
#define rCCK0_FACounterLower 0xa5c //0xa5b
#define rCCK0_FACounterUpper 0xa58 //0xa5c
//
// 6. PageC(0xC00)
@ -203,16 +203,16 @@
#define rOFDM0_TRSWIsolation 0xc0c
#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter
#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
#define rOFDM0_XBRxAFE 0xc18
#define rOFDM0_XBRxIQImbalance 0xc1c
#define rOFDM0_XCRxAFE 0xc20
#define rOFDM0_XCRxIQImbalance 0xc24
#define rOFDM0_XDRxAFE 0xc28
#define rOFDM0_XDRxIQImbalance 0xc2c
#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
#define rOFDM0_XBRxAFE 0xc18
#define rOFDM0_XBRxIQImbalance 0xc1c
#define rOFDM0_XCRxAFE 0xc20
#define rOFDM0_XCRxIQImbalance 0xc24
#define rOFDM0_XDRxAFE 0xc28
#define rOFDM0_XDRxIQImbalance 0xc2c
#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain
#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
#define rOFDM0_RxDetector3 0xc38 //Frame Sync.
#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI
@ -221,7 +221,7 @@
#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold
#define rOFDM0_ECCAThreshold 0xc4c // energy CCA
#define rOFDM0_XAAGCCore1 0xc50 // DIG
#define rOFDM0_XAAGCCore1 0xc50 // DIG
#define rOFDM0_XAAGCCore2 0xc54
#define rOFDM0_XBAGCCore1 0xc58
#define rOFDM0_XBAGCCore2 0xc5c
@ -240,7 +240,7 @@
#define rOFDM0_XBTxIQImbalance 0xc88
#define rOFDM0_XBTxAFE 0xc8c
#define rOFDM0_XCTxIQImbalance 0xc90
#define rOFDM0_XCTxAFE 0xc94
#define rOFDM0_XCTxAFE 0xc94
#define rOFDM0_XDTxIQImbalance 0xc98
#define rOFDM0_XDTxAFE 0xc9c
#define rOFDM0_RxIQExtAnta 0xca0
@ -285,8 +285,8 @@
#define rOFDM_LongCFOCD 0xdb8
#define rOFDM_TailCFOAB 0xdbc
#define rOFDM_TailCFOCD 0xdc0
#define rOFDM_PWMeasure1 0xdc4
#define rOFDM_PWMeasure2 0xdc8
#define rOFDM_PWMeasure1 0xdc4
#define rOFDM_PWMeasure2 0xdc8
#define rOFDM_BWReport 0xdcc
#define rOFDM_AGCReport 0xdd0
#define rOFDM_RxSNR 0xdd4
@ -306,7 +306,7 @@
#define rTxAGC_Mcs15_Mcs12 0xe1c
// Analog- control in RX_WAIT_CCA : REG: EE0 [Analog- Power & Control Register]
#define rRx_Wait_CCCA 0xe70
#define rRx_Wait_CCCA 0xe70
#define rAnapar_Ctrl_BB 0xee0
//
@ -343,48 +343,48 @@
//
// RL6052 Register definition
//
#define RF_AC 0x00 //
#define RF_AC 0x00 //
#define RF_IQADJ_G1 0x01 //
#define RF_IQADJ_G2 0x02 //
#define RF_POW_TRSW 0x05 //
#define RF_IQADJ_G1 0x01 //
#define RF_IQADJ_G2 0x02 //
#define RF_POW_TRSW 0x05 //
#define RF_GAIN_RX 0x06 //
#define RF_GAIN_TX 0x07 //
#define RF_GAIN_RX 0x06 //
#define RF_GAIN_TX 0x07 //
#define RF_TXM_IDAC 0x08 //
#define RF_BS_IQGEN 0x0F //
#define RF_TXM_IDAC 0x08 //
#define RF_BS_IQGEN 0x0F //
#define RF_MODE1 0x10 //
#define RF_MODE2 0x11 //
#define RF_MODE1 0x10 //
#define RF_MODE2 0x11 //
#define RF_RX_AGC_HP 0x12 //
#define RF_TX_AGC 0x13 //
#define RF_BIAS 0x14 //
#define RF_IPA 0x15 //
#define RF_RX_AGC_HP 0x12 //
#define RF_TX_AGC 0x13 //
#define RF_BIAS 0x14 //
#define RF_IPA 0x15 //
#define RF_TXBIAS 0x16 //
#define RF_POW_ABILITY 0x17 //
#define RF_MODE_AG 0x18 //
#define RF_POW_ABILITY 0x17 //
#define RF_MODE_AG 0x18 //
#define rRfChannel 0x18 // RF channel and BW switch
#define RF_CHNLBW 0x18 // RF channel and BW switch
#define RF_TOP 0x19 //
#define RF_TOP 0x19 //
#define RF_RX_G1 0x1A //
#define RF_RX_G2 0x1B //
#define RF_RX_G1 0x1A //
#define RF_RX_G2 0x1B //
#define RF_RX_BB2 0x1C //
#define RF_RX_BB1 0x1D //
#define RF_RX_BB2 0x1C //
#define RF_RX_BB1 0x1D //
#define RF_RCK1 0x1E //
#define RF_RCK2 0x1F //
#define RF_RCK1 0x1E //
#define RF_RCK2 0x1F //
#define RF_TX_G1 0x20 //
#define RF_TX_G2 0x21 //
#define RF_TX_G3 0x22 //
#define RF_TX_G1 0x20 //
#define RF_TX_G2 0x21 //
#define RF_TX_G3 0x22 //
#define RF_TX_BB1 0x23 //
#define RF_TX_BB1 0x23 //
#define RF_T_METER 0x24 //
#define RF_T_METER 0x24 //
#define RF_SYN_G1 0x25 // RF TX Power control
#define RF_SYN_G2 0x26 // RF TX Power control
@ -450,7 +450,7 @@
#define bCCKTxStatus 0x1
#define bOFDMTxStatus 0x2
#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
// 2. Page8(0x800)
#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD
@ -459,317 +459,317 @@
#define bCCKEn 0x1000000
#define bOFDMEn 0x2000000
#define bOFDMRxADCPhase 0x10000 // Useless now
#define bOFDMTxDACPhase 0x40000
#define bXATxAGC 0x3f
#define bOFDMRxADCPhase 0x10000 // Useless now
#define bOFDMTxDACPhase 0x40000
#define bXATxAGC 0x3f
#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage
#define bXCTxAGC 0xf000
#define bXDTxAGC 0xf0000
#define bPAStart 0xf0000000 // Useless now
#define bTRStart 0x00f00000
#define bRFStart 0x0000f000
#define bBBStart 0x000000f0
#define bBBCCKStart 0x0000000f
#define bPAEnd 0xf //Reg0x814
#define bTREnd 0x0f000000
#define bRFEnd 0x000f0000
#define bCCAMask 0x000000f0 //T2R
#define bR2RCCAMask 0x00000f00
#define bHSSI_R2TDelay 0xf8000000
#define bHSSI_T2RDelay 0xf80000
#define bContTxHSSI 0x400 //chane gain at continue Tx
#define bIGFromCCK 0x200
#define bAGCAddress 0x3f
#define bRxHPTx 0x7000
#define bRxHPT2R 0x38000
#define bRxHPCCKIni 0xc0000
#define bAGCTxCode 0xc00000
#define bAGCRxCode 0x300000
#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage
#define bXCTxAGC 0xf000
#define bXDTxAGC 0xf0000
#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1
#define b3WireAddressLength 0x400
#define bPAStart 0xf0000000 // Useless now
#define bTRStart 0x00f00000
#define bRFStart 0x0000f000
#define bBBStart 0x000000f0
#define bBBCCKStart 0x0000000f
#define bPAEnd 0xf //Reg0x814
#define bTREnd 0x0f000000
#define bRFEnd 0x000f0000
#define bCCAMask 0x000000f0 //T2R
#define bR2RCCAMask 0x00000f00
#define bHSSI_R2TDelay 0xf8000000
#define bHSSI_T2RDelay 0xf80000
#define bContTxHSSI 0x400 //chane gain at continue Tx
#define bIGFromCCK 0x200
#define bAGCAddress 0x3f
#define bRxHPTx 0x7000
#define bRxHPT2R 0x38000
#define bRxHPCCKIni 0xc0000
#define bAGCTxCode 0xc00000
#define bAGCRxCode 0x300000
#define b3WireRFPowerDown 0x1 // Useless now
//#define bHWSISelect 0x8
#define b5GPAPEPolarity 0x40000000
#define b2GPAPEPolarity 0x80000000
#define bRFSW_TxDefaultAnt 0x3
#define bRFSW_TxOptionAnt 0x30
#define bRFSW_RxDefaultAnt 0x300
#define bRFSW_RxOptionAnt 0x3000
#define bRFSI_3WireData 0x1
#define bRFSI_3WireClock 0x2
#define bRFSI_3WireLoad 0x4
#define bRFSI_3WireRW 0x8
#define bRFSI_3Wire 0xf
#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1
#define b3WireAddressLength 0x400
#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW
#define b3WireRFPowerDown 0x1 // Useless now
//#define bHWSISelect 0x8
#define b5GPAPEPolarity 0x40000000
#define b2GPAPEPolarity 0x80000000
#define bRFSW_TxDefaultAnt 0x3
#define bRFSW_TxOptionAnt 0x30
#define bRFSW_RxDefaultAnt 0x300
#define bRFSW_RxOptionAnt 0x3000
#define bRFSI_3WireData 0x1
#define bRFSI_3WireClock 0x2
#define bRFSI_3WireLoad 0x4
#define bRFSI_3WireRW 0x8
#define bRFSI_3Wire 0xf
#define bRFSI_TRSW 0x20 // Useless now
#define bRFSI_TRSWB 0x40
#define bRFSI_ANTSW 0x100
#define bRFSI_ANTSWB 0x200
#define bRFSI_PAPE 0x400
#define bRFSI_PAPE5G 0x800
#define bBandSelect 0x1
#define bHTSIG2_GI 0x80
#define bHTSIG2_Smoothing 0x01
#define bHTSIG2_Sounding 0x02
#define bHTSIG2_Aggreaton 0x08
#define bHTSIG2_STBC 0x30
#define bHTSIG2_AdvCoding 0x40
#define bHTSIG2_NumOfHTLTF 0x300
#define bHTSIG2_CRC8 0x3fc
#define bHTSIG1_MCS 0x7f
#define bHTSIG1_BandWidth 0x80
#define bHTSIG1_HTLength 0xffff
#define bLSIG_Rate 0xf
#define bLSIG_Reserved 0x10
#define bLSIG_Length 0x1fffe
#define bLSIG_Parity 0x20
#define bCCKRxPhase 0x4
#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW
#define bRFSI_TRSW 0x20 // Useless now
#define bRFSI_TRSWB 0x40
#define bRFSI_ANTSW 0x100
#define bRFSI_ANTSWB 0x200
#define bRFSI_PAPE 0x400
#define bRFSI_PAPE5G 0x800
#define bBandSelect 0x1
#define bHTSIG2_GI 0x80
#define bHTSIG2_Smoothing 0x01
#define bHTSIG2_Sounding 0x02
#define bHTSIG2_Aggreaton 0x08
#define bHTSIG2_STBC 0x30
#define bHTSIG2_AdvCoding 0x40
#define bHTSIG2_NumOfHTLTF 0x300
#define bHTSIG2_CRC8 0x3fc
#define bHTSIG1_MCS 0x7f
#define bHTSIG1_BandWidth 0x80
#define bHTSIG1_HTLength 0xffff
#define bLSIG_Rate 0xf
#define bLSIG_Reserved 0x10
#define bLSIG_Length 0x1fffe
#define bLSIG_Parity 0x20
#define bCCKRxPhase 0x4
#if (RTL92SE_FPGA_VERIFY == 1)
#define bLSSIReadAddress 0x3f000000 //LSSI "Read" Address // Reg 0x824 rFPGA0_XA_HSSIParameter2
#define bLSSIReadAddress 0x3f000000 //LSSI "Read" Address // Reg 0x824 rFPGA0_XA_HSSIParameter2
#else
#define bLSSIReadAddress 0x7f800000 // T65 RF
#define bLSSIReadAddress 0x7f800000 // T65 RF
#endif
#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
#if (RTL92SE_FPGA_VERIFY == 1)
#define bLSSIReadBackData 0xfff // Reg 0x8a0 rFPGA0_XA_LSSIReadBack
#define bLSSIReadBackData 0xfff // Reg 0x8a0 rFPGA0_XA_LSSIReadBack
#else
#define bLSSIReadBackData 0xfffff // T65 RF
#define bLSSIReadBackData 0xfffff // T65 RF
#endif
#define bLSSIReadOKFlag 0x1000 // Useless now
#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
#define bRegulator0Standby 0x1
#define bRegulatorPLLStandby 0x2
#define bRegulator1Standby 0x4
#define bPLLPowerUp 0x8
#define bDPLLPowerUp 0x10
#define bDA10PowerUp 0x20
#define bAD7PowerUp 0x200
#define bDA6PowerUp 0x2000
#define bXtalPowerUp 0x4000
#define b40MDClkPowerUP 0x8000
#define bDA6DebugMode 0x20000
#define bDA6Swing 0x380000
#define bLSSIReadOKFlag 0x1000 // Useless now
#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
#define bRegulator0Standby 0x1
#define bRegulatorPLLStandby 0x2
#define bRegulator1Standby 0x4
#define bPLLPowerUp 0x8
#define bDPLLPowerUp 0x10
#define bDA10PowerUp 0x20
#define bAD7PowerUp 0x200
#define bDA6PowerUp 0x2000
#define bXtalPowerUp 0x4000
#define b40MDClkPowerUP 0x8000
#define bDA6DebugMode 0x20000
#define bDA6Swing 0x380000
#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ
#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ
#define b80MClkDelay 0x18000000 // Useless
#define bAFEWatchDogEnable 0x20000000
#define b80MClkDelay 0x18000000 // Useless
#define bAFEWatchDogEnable 0x20000000
#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap
#define bXtalCap23 0x3
#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap
#define bXtalCap23 0x3
#define bXtalCap92x 0x0f000000
#define bXtalCap 0x0f000000
#define bXtalCap 0x0f000000
#define bIntDifClkEnable 0x400 // Useless
#define bExtSigClkEnable 0x800
#define bBandgapMbiasPowerUp 0x10000
#define bAD11SHGain 0xc0000
#define bAD11InputRange 0x700000
#define bAD11OPCurrent 0x3800000
#define bIPathLoopback 0x4000000
#define bQPathLoopback 0x8000000
#define bAFELoopback 0x10000000
#define bDA10Swing 0x7e0
#define bDA10Reverse 0x800
#define bDAClkSource 0x1000
#define bAD7InputRange 0x6000
#define bAD7Gain 0x38000
#define bAD7OutputCMMode 0x40000
#define bAD7InputCMMode 0x380000
#define bAD7Current 0xc00000
#define bRegulatorAdjust 0x7000000
#define bAD11PowerUpAtTx 0x1
#define bDA10PSAtTx 0x10
#define bAD11PowerUpAtRx 0x100
#define bDA10PSAtRx 0x1000
#define bCCKRxAGCFormat 0x200
#define bPSDFFTSamplepPoint 0xc000
#define bPSDAverageNum 0x3000
#define bIQPathControl 0xc00
#define bPSDFreq 0x3ff
#define bPSDAntennaPath 0x30
#define bPSDIQSwitch 0x40
#define bPSDRxTrigger 0x400000
#define bPSDTxTrigger 0x80000000
#define bPSDSineToneScale 0x7f000000
#define bPSDReport 0xffff
#define bIntDifClkEnable 0x400 // Useless
#define bExtSigClkEnable 0x800
#define bBandgapMbiasPowerUp 0x10000
#define bAD11SHGain 0xc0000
#define bAD11InputRange 0x700000
#define bAD11OPCurrent 0x3800000
#define bIPathLoopback 0x4000000
#define bQPathLoopback 0x8000000
#define bAFELoopback 0x10000000
#define bDA10Swing 0x7e0
#define bDA10Reverse 0x800
#define bDAClkSource 0x1000
#define bAD7InputRange 0x6000
#define bAD7Gain 0x38000
#define bAD7OutputCMMode 0x40000
#define bAD7InputCMMode 0x380000
#define bAD7Current 0xc00000
#define bRegulatorAdjust 0x7000000
#define bAD11PowerUpAtTx 0x1
#define bDA10PSAtTx 0x10
#define bAD11PowerUpAtRx 0x100
#define bDA10PSAtRx 0x1000
#define bCCKRxAGCFormat 0x200
#define bPSDFFTSamplepPoint 0xc000
#define bPSDAverageNum 0x3000
#define bIQPathControl 0xc00
#define bPSDFreq 0x3ff
#define bPSDAntennaPath 0x30
#define bPSDIQSwitch 0x40
#define bPSDRxTrigger 0x400000
#define bPSDTxTrigger 0x80000000
#define bPSDSineToneScale 0x7f000000
#define bPSDReport 0xffff
// 3. Page9(0x900)
#define bOFDMTxSC 0x30000000 // Useless
#define bCCKTxOn 0x1
#define bOFDMTxOn 0x2
#define bDebugPage 0xfff //reset debug page and also HWord, LWord
#define bDebugItem 0xff //reset debug page and LWord
#define bAntL 0x10
#define bAntNonHT 0x100
#define bAntHT1 0x1000
#define bAntHT2 0x10000
#define bAntHT1S1 0x100000
#define bAntNonHTS1 0x1000000
#define bOFDMTxSC 0x30000000 // Useless
#define bCCKTxOn 0x1
#define bOFDMTxOn 0x2
#define bDebugPage 0xfff //reset debug page and also HWord, LWord
#define bDebugItem 0xff //reset debug page and LWord
#define bAntL 0x10
#define bAntNonHT 0x100
#define bAntHT1 0x1000
#define bAntHT2 0x10000
#define bAntHT1S1 0x100000
#define bAntNonHTS1 0x1000000
// 4. PageA(0xA00)
#define bCCKBBMode 0x3 // Useless
#define bCCKTxPowerSaving 0x80
#define bCCKRxPowerSaving 0x40
#define bCCKBBMode 0x3 // Useless
#define bCCKTxPowerSaving 0x80
#define bCCKRxPowerSaving 0x40
#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch
#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch
#define bCCKScramble 0x8 // Useless
#define bCCKAntDiversity 0x8000
#define bCCKCarrierRecovery 0x4000
#define bCCKTxRate 0x3000
#define bCCKDCCancel 0x0800
#define bCCKISICancel 0x0400
#define bCCKMatchFilter 0x0200
#define bCCKEqualizer 0x0100
#define bCCKPreambleDetect 0x800000
#define bCCKFastFalseCCA 0x400000
#define bCCKChEstStart 0x300000
#define bCCKCCACount 0x080000
#define bCCKcs_lim 0x070000
#define bCCKBistMode 0x80000000
#define bCCKCCAMask 0x40000000
#define bCCKTxDACPhase 0x4
#define bCCKRxADCPhase 0x20000000 //r_rx_clk
#define bCCKr_cp_mode0 0x0100
#define bCCKTxDCOffset 0xf0
#define bCCKRxDCOffset 0xf
#define bCCKCCAMode 0xc000
#define bCCKFalseCS_lim 0x3f00
#define bCCKCS_ratio 0xc00000
#define bCCKCorgBit_sel 0x300000
#define bCCKPD_lim 0x0f0000
#define bCCKNewCCA 0x80000000
#define bCCKRxHPofIG 0x8000
#define bCCKRxIG 0x7f00
#define bCCKLNAPolarity 0x800000
#define bCCKRx1stGain 0x7f0000
#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity
#define bCCKRxAGCSatLevel 0x1f000000
#define bCCKRxAGCSatCount 0xe0
#define bCCKRxRFSettle 0x1f //AGCsamp_dly
#define bCCKFixedRxAGC 0x8000
//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
#define bCCKAntennaPolarity 0x2000
#define bCCKTxFilterType 0x0c00
#define bCCKRxAGCReportType 0x0300
#define bCCKRxDAGCEn 0x80000000
#define bCCKRxDAGCPeriod 0x20000000
#define bCCKRxDAGCSatLevel 0x1f000000
#define bCCKTimingRecovery 0x800000
#define bCCKTxC0 0x3f0000
#define bCCKTxC1 0x3f000000
#define bCCKTxC2 0x3f
#define bCCKTxC3 0x3f00
#define bCCKTxC4 0x3f0000
#define bCCKTxC5 0x3f000000
#define bCCKTxC6 0x3f
#define bCCKTxC7 0x3f00
#define bCCKDebugPort 0xff0000
#define bCCKDACDebug 0x0f000000
#define bCCKFalseAlarmEnable 0x8000
#define bCCKFalseAlarmRead 0x4000
#define bCCKTRSSI 0x7f
#define bCCKRxAGCReport 0xfe
#define bCCKRxReport_AntSel 0x80000000
#define bCCKRxReport_MFOff 0x40000000
#define bCCKRxRxReport_SQLoss 0x20000000
#define bCCKRxReport_Pktloss 0x10000000
#define bCCKRxReport_Lockedbit 0x08000000
#define bCCKRxReport_RateError 0x04000000
#define bCCKRxReport_RxRate 0x03000000
#define bCCKRxFACounterLower 0xff
#define bCCKRxFACounterUpper 0xff000000
#define bCCKRxHPAGCStart 0xe000
#define bCCKRxHPAGCFinal 0x1c00
#define bCCKRxFalseAlarmEnable 0x8000
#define bCCKFACounterFreeze 0x4000
#define bCCKTxPathSel 0x10000000
#define bCCKDefaultRxPath 0xc000000
#define bCCKOptionRxPath 0x3000000
#define bCCKScramble 0x8 // Useless
#define bCCKAntDiversity 0x8000
#define bCCKCarrierRecovery 0x4000
#define bCCKTxRate 0x3000
#define bCCKDCCancel 0x0800
#define bCCKISICancel 0x0400
#define bCCKMatchFilter 0x0200
#define bCCKEqualizer 0x0100
#define bCCKPreambleDetect 0x800000
#define bCCKFastFalseCCA 0x400000
#define bCCKChEstStart 0x300000
#define bCCKCCACount 0x080000
#define bCCKcs_lim 0x070000
#define bCCKBistMode 0x80000000
#define bCCKCCAMask 0x40000000
#define bCCKTxDACPhase 0x4
#define bCCKRxADCPhase 0x20000000 //r_rx_clk
#define bCCKr_cp_mode0 0x0100
#define bCCKTxDCOffset 0xf0
#define bCCKRxDCOffset 0xf
#define bCCKCCAMode 0xc000
#define bCCKFalseCS_lim 0x3f00
#define bCCKCS_ratio 0xc00000
#define bCCKCorgBit_sel 0x300000
#define bCCKPD_lim 0x0f0000
#define bCCKNewCCA 0x80000000
#define bCCKRxHPofIG 0x8000
#define bCCKRxIG 0x7f00
#define bCCKLNAPolarity 0x800000
#define bCCKRx1stGain 0x7f0000
#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity
#define bCCKRxAGCSatLevel 0x1f000000
#define bCCKRxAGCSatCount 0xe0
#define bCCKRxRFSettle 0x1f //AGCsamp_dly
#define bCCKFixedRxAGC 0x8000
//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
#define bCCKAntennaPolarity 0x2000
#define bCCKTxFilterType 0x0c00
#define bCCKRxAGCReportType 0x0300
#define bCCKRxDAGCEn 0x80000000
#define bCCKRxDAGCPeriod 0x20000000
#define bCCKRxDAGCSatLevel 0x1f000000
#define bCCKTimingRecovery 0x800000
#define bCCKTxC0 0x3f0000
#define bCCKTxC1 0x3f000000
#define bCCKTxC2 0x3f
#define bCCKTxC3 0x3f00
#define bCCKTxC4 0x3f0000
#define bCCKTxC5 0x3f000000
#define bCCKTxC6 0x3f
#define bCCKTxC7 0x3f00
#define bCCKDebugPort 0xff0000
#define bCCKDACDebug 0x0f000000
#define bCCKFalseAlarmEnable 0x8000
#define bCCKFalseAlarmRead 0x4000
#define bCCKTRSSI 0x7f
#define bCCKRxAGCReport 0xfe
#define bCCKRxReport_AntSel 0x80000000
#define bCCKRxReport_MFOff 0x40000000
#define bCCKRxRxReport_SQLoss 0x20000000
#define bCCKRxReport_Pktloss 0x10000000
#define bCCKRxReport_Lockedbit 0x08000000
#define bCCKRxReport_RateError 0x04000000
#define bCCKRxReport_RxRate 0x03000000
#define bCCKRxFACounterLower 0xff
#define bCCKRxFACounterUpper 0xff000000
#define bCCKRxHPAGCStart 0xe000
#define bCCKRxHPAGCFinal 0x1c00
#define bCCKRxFalseAlarmEnable 0x8000
#define bCCKFACounterFreeze 0x4000
#define bCCKTxPathSel 0x10000000
#define bCCKDefaultRxPath 0xc000000
#define bCCKOptionRxPath 0x3000000
// 5. PageC(0xC00)
#define bNumOfSTF 0x3 // Useless
#define bShift_L 0xc0
#define bGI_TH 0xc
#define bRxPathA 0x1
#define bRxPathB 0x2
#define bRxPathC 0x4
#define bRxPathD 0x8
#define bTxPathA 0x1
#define bTxPathB 0x2
#define bTxPathC 0x4
#define bTxPathD 0x8
#define bTRSSIFreq 0x200
#define bADCBackoff 0x3000
#define bDFIRBackoff 0xc000
#define bTRSSILatchPhase 0x10000
#define bRxIDCOffset 0xff
#define bRxQDCOffset 0xff00
#define bRxDFIRMode 0x1800000
#define bRxDCNFType 0xe000000
#define bRXIQImb_A 0x3ff
#define bRXIQImb_B 0xfc00
#define bRXIQImb_C 0x3f0000
#define bRXIQImb_D 0xffc00000
#define bDC_dc_Notch 0x60000
#define bRxNBINotch 0x1f000000
#define bPD_TH 0xf
#define bPD_TH_Opt2 0xc000
#define bPWED_TH 0x700
#define bIfMF_Win_L 0x800
#define bPD_Option 0x1000
#define bMF_Win_L 0xe000
#define bBW_Search_L 0x30000
#define bwin_enh_L 0xc0000
#define bBW_TH 0x700000
#define bED_TH2 0x3800000
#define bBW_option 0x4000000
#define bRatio_TH 0x18000000
#define bWindow_L 0xe0000000
#define bSBD_Option 0x1
#define bFrame_TH 0x1c
#define bFS_Option 0x60
#define bDC_Slope_check 0x80
#define bFGuard_Counter_DC_L 0xe00
#define bFrame_Weight_Short 0x7000
#define bSub_Tune 0xe00000
#define bFrame_DC_Length 0xe000000
#define bSBD_start_offset 0x30000000
#define bFrame_TH_2 0x7
#define bFrame_GI2_TH 0x38
#define bGI2_Sync_en 0x40
#define bSarch_Short_Early 0x300
#define bSarch_Short_Late 0xc00
#define bSarch_GI2_Late 0x70000
#define bCFOAntSum 0x1
#define bCFOAcc 0x2
#define bCFOStartOffset 0xc
#define bCFOLookBack 0x70
#define bCFOSumWeight 0x80
#define bDAGCEnable 0x10000
#define bTXIQImb_A 0x3ff
#define bTXIQImb_B 0xfc00
#define bTXIQImb_C 0x3f0000
#define bTXIQImb_D 0xffc00000
#define bTxIDCOffset 0xff
#define bTxQDCOffset 0xff00
#define bTxDFIRMode 0x10000
#define bTxPesudoNoiseOn 0x4000000
#define bTxPesudoNoise_A 0xff
#define bTxPesudoNoise_B 0xff00
#define bTxPesudoNoise_C 0xff0000
#define bTxPesudoNoise_D 0xff000000
#define bCCADropOption 0x20000
#define bCCADropThres 0xfff00000
#define bEDCCA_H 0xf
#define bEDCCA_L 0xf0
#define bNumOfSTF 0x3 // Useless
#define bShift_L 0xc0
#define bGI_TH 0xc
#define bRxPathA 0x1
#define bRxPathB 0x2
#define bRxPathC 0x4
#define bRxPathD 0x8
#define bTxPathA 0x1
#define bTxPathB 0x2
#define bTxPathC 0x4
#define bTxPathD 0x8
#define bTRSSIFreq 0x200
#define bADCBackoff 0x3000
#define bDFIRBackoff 0xc000
#define bTRSSILatchPhase 0x10000
#define bRxIDCOffset 0xff
#define bRxQDCOffset 0xff00
#define bRxDFIRMode 0x1800000
#define bRxDCNFType 0xe000000
#define bRXIQImb_A 0x3ff
#define bRXIQImb_B 0xfc00
#define bRXIQImb_C 0x3f0000
#define bRXIQImb_D 0xffc00000
#define bDC_dc_Notch 0x60000
#define bRxNBINotch 0x1f000000
#define bPD_TH 0xf
#define bPD_TH_Opt2 0xc000
#define bPWED_TH 0x700
#define bIfMF_Win_L 0x800
#define bPD_Option 0x1000
#define bMF_Win_L 0xe000
#define bBW_Search_L 0x30000
#define bwin_enh_L 0xc0000
#define bBW_TH 0x700000
#define bED_TH2 0x3800000
#define bBW_option 0x4000000
#define bRatio_TH 0x18000000
#define bWindow_L 0xe0000000
#define bSBD_Option 0x1
#define bFrame_TH 0x1c
#define bFS_Option 0x60
#define bDC_Slope_check 0x80
#define bFGuard_Counter_DC_L 0xe00
#define bFrame_Weight_Short 0x7000
#define bSub_Tune 0xe00000
#define bFrame_DC_Length 0xe000000
#define bSBD_start_offset 0x30000000
#define bFrame_TH_2 0x7
#define bFrame_GI2_TH 0x38
#define bGI2_Sync_en 0x40
#define bSarch_Short_Early 0x300
#define bSarch_Short_Late 0xc00
#define bSarch_GI2_Late 0x70000
#define bCFOAntSum 0x1
#define bCFOAcc 0x2
#define bCFOStartOffset 0xc
#define bCFOLookBack 0x70
#define bCFOSumWeight 0x80
#define bDAGCEnable 0x10000
#define bTXIQImb_A 0x3ff
#define bTXIQImb_B 0xfc00
#define bTXIQImb_C 0x3f0000
#define bTXIQImb_D 0xffc00000
#define bTxIDCOffset 0xff
#define bTxQDCOffset 0xff00
#define bTxDFIRMode 0x10000
#define bTxPesudoNoiseOn 0x4000000
#define bTxPesudoNoise_A 0xff
#define bTxPesudoNoise_B 0xff00
#define bTxPesudoNoise_C 0xff0000
#define bTxPesudoNoise_D 0xff000000
#define bCCADropOption 0x20000
#define bCCADropThres 0xfff00000
#define bEDCCA_H 0xf
#define bEDCCA_L 0xf0
#define bLambda_ED 0x300
#define bRxInitialGain 0x7f
#define bRxAntDivEn 0x80
@ -841,16 +841,16 @@
#define bRxSGI_TH 0xc0000000
#define bDFSCnt0 0xff
#define bDFSCnt1 0xff00
#define bDFSFlag 0xf0000
#define bDFSFlag 0xf0000
#define bMFWeightSum 0x300000
#define bMinIdxTH 0x7f000000
#define bDAFormat 0x40000
#define bTxChEmuEnable 0x01000000
#define bMinIdxTH 0x7f000000
#define bDAFormat 0x40000
#define bTxChEmuEnable 0x01000000
#define bTRSWIsolation_A 0x7f
#define bTRSWIsolation_B 0x7f00
#define bTRSWIsolation_C 0x7f0000
#define bTRSWIsolation_D 0x7f000000
#define bExtLNAGain 0x7c00
#define bTRSWIsolation_D 0x7f000000
#define bExtLNAGain 0x7c00
// 6. PageE(0xE00)
#define bSTBCEn 0x4 // Useless
@ -887,7 +887,7 @@
#define bLongCFOFLength 11
#define bTailCFO 0x1fff
#define bTailCFOTLength 13
#define bTailCFOFLength 12
#define bTailCFOFLength 12
#define bmax_en_pwdB 0xffff
#define bCC_power_dB 0xffff0000
#define bnoise_pwdB 0xffff
@ -895,27 +895,27 @@
#define bPowerMeasFLength 3
#define bRx_HT_BW 0x1
#define bRxSC 0x6
#define bRx_HT 0x8
#define bRx_HT 0x8
#define bNB_intf_det_on 0x1
#define bIntf_win_len_cfg 0x30
#define bNB_Intf_TH_cfg 0x1c0
#define bNB_Intf_TH_cfg 0x1c0
#define bRFGain 0x3f
#define bTableSel 0x40
#define bTRSW 0x80
#define bTRSW 0x80
#define bRxSNR_A 0xff
#define bRxSNR_B 0xff00
#define bRxSNR_C 0xff0000
#define bRxSNR_D 0xff000000
#define bSNREVMTLength 8
#define bSNREVMFLength 1
#define bSNREVMFLength 1
#define bCSI1st 0xff
#define bCSI2nd 0xff00
#define bRxEVM1st 0xff0000
#define bRxEVM2nd 0xff000000
#define bRxEVM2nd 0xff000000
#define bSIGEVM 0xff
#define bPWDB 0xff00
#define bSGIEN 0x10000
#define bSFactorQAM1 0xf // Useless
#define bSFactorQAM2 0xf0
#define bSFactorQAM3 0xf00
@ -926,7 +926,7 @@
#define bSFactorQAM8 0xf000000
#define bSFactorQAM9 0xf0000000
#define bCSIScheme 0x100000
#define bNoiseLvlTopSet 0x3 // Useless
#define bChSmooth 0x4
#define bChSmoothCfg1 0x38
@ -935,7 +935,7 @@
#define bChSmoothCfg4 0x7000
#define bMRCMode 0x800000
#define bTHEVMCfg 0x7000000
#define bLoopFitType 0x1 // Useless
#define bUpdCFO 0x40
#define bUpdCFOOffData 0x80
@ -1017,8 +1017,8 @@
#define bMaskHWord 0xffff0000
#define bMaskLWord 0x0000ffff
#define bMaskDWord 0xffffffff
#define bMaskH4Bits 0xf0000000
#define bMaskOFDM_D 0xffc00000
#define bMaskH4Bits 0xf0000000
#define bMaskOFDM_D 0xffc00000
#define bMaskCCK 0x3f3f3f3f
#define bMask12Bits 0xfff
@ -1026,21 +1026,21 @@
#if (RTL92SE_FPGA_VERIFY == 1)
//#define bMask12Bits 0xfff // RF Reg mask bits
//#define bMask20Bits 0xfff // RF Reg mask bits T65 RF
#define bRFRegOffsetMask 0xfff
#define bRFRegOffsetMask 0xfff
#else
//#define bMask12Bits 0xfffff // RF Reg mask bits
//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF
#define bRFRegOffsetMask 0xfffff
#endif
#define bRFRegOffsetMask 0xfffff
#endif
#define bEnable 0x1 // Useless
#define bDisable 0x0
#define LeftAntenna 0x0 // Useless
#define RightAntenna 0x1
#define tCheckTxStatus 500 //500ms // Useless
#define tUpdateRxCounter 100 //100ms
#define rateCCK 0 // Useless
#define rateOFDM 1
#define rateHT 2
@ -1096,4 +1096,3 @@
#endif //__INC_HAL8192SPHYREG_H

1
include/rtw_odm.h
View file

@ -39,4 +39,3 @@ void rtw_odm_adaptivity_parm_set(struct adapter *adapter, s8 TH_L2H_ini, s8 TH_E
s8 IGI_Base, bool ForceEDCCA, u8 AdapEn_RSSI, u8 IGI_LowerBound);
#endif // __RTW_ODM_H__

3
include/rtw_p2p.h
View file

@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@ -158,4 +158,3 @@ void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, co
(wdinfo)->find_phase_state_exchange_cnt != P2P_FINDPHASE_EX_NONE)
#endif

45
include/rtw_pwrctrl.h
View file

@ -29,15 +29,15 @@
#endif //CONFIG_HAS_EARLYSUSPEND
#define FW_PWR0 0
#define FW_PWR1 1
#define FW_PWR2 2
#define FW_PWR3 3
#define FW_PWR0 0
#define FW_PWR1 1
#define FW_PWR2 2
#define FW_PWR3 3
#define HW_PWR0 7
#define HW_PWR1 6
#define HW_PWR2 2
#define HW_PWR0 7
#define HW_PWR1 6
#define HW_PWR2 2
#define HW_PWR3 0
#define HW_PWR4 8
@ -108,7 +108,7 @@ struct reportpwrstate_parm {
unsigned char mode;
unsigned char state; //the CPWM value
unsigned short rsvd;
};
};
typedef _sema _pwrlock;
@ -179,7 +179,7 @@ enum _PS_BBRegBackup_ {
enum { // for ips_mode
IPS_NONE=0,
IPS_NORMAL,
IPS_LEVEL_2,
IPS_LEVEL_2,
};
struct pwrctrl_priv
@ -216,17 +216,17 @@ struct pwrctrl_priv
#ifdef CONFIG_PCI_HCI
//just for PCIE ASPM
u8 b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00.
u8 b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00.
u8 b_support_backdoor;
//just for PCIE ASPM
u8 const_amdpci_aspm;
#endif
uint ips_enter_cnts;
uint ips_leave_cnts;
uint ips_enter_cnts;
uint ips_leave_cnts;
u8 ips_mode;
u8 ips_mode;
u8 ips_mode_req; // used to accept the mode setting request, will update to ipsmode later
uint bips_processing;
u32 ips_deny_time; /* will deny IPS when system time is smaller than this */
@ -237,7 +237,7 @@ struct pwrctrl_priv
u8 power_mgnt;
u8 bFwCurrentInPSMode;
u32 DelayLPSLastTimeStamp;
u8 btcoex_rfon;
u8 btcoex_rfon;
s32 pnp_current_pwr_state;
u8 pnp_bstop_trx;
@ -248,7 +248,7 @@ struct pwrctrl_priv
u8 bAutoResume;
u8 autopm_cnt;
#endif
u8 bSupportRemoteWakeup;
u8 bSupportRemoteWakeup;
#ifdef CONFIG_WOWLAN
u8 wowlan_mode;
u8 wowlan_pattern;
@ -259,19 +259,19 @@ struct pwrctrl_priv
u32 wowlan_pattern_context[8][5];
u64 wowlan_fw_iv;
#endif // CONFIG_WOWLAN
_timer pwr_state_check_timer;
_timer pwr_state_check_timer;
int pwr_state_check_interval;
u8 pwr_state_check_cnts;
int ps_flag;
int ps_flag;
rt_rf_power_state rf_pwrstate;//cur power state
//rt_rf_power_state current_rfpwrstate;
//rt_rf_power_state current_rfpwrstate;
rt_rf_power_state change_rfpwrstate;
u8 bHWPowerdown;//if support hw power down
u8 bHWPwrPindetect;
u8 bkeepfwalive;
u8 bkeepfwalive;
u8 brfoffbyhw;
unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT];
@ -284,7 +284,7 @@ struct pwrctrl_priv
struct early_suspend early_suspend;
u8 do_late_resume;
#endif //CONFIG_HAS_EARLYSUSPEND
#ifdef CONFIG_ANDROID_POWER
android_early_suspend_t early_suspend;
u8 do_late_resume;
@ -308,7 +308,7 @@ struct pwrctrl_priv
/*DBG_871X("%s _rtw_set_pwr_state_check_timer(%p, %d)\n", __FUNCTION__, (pwrctl), (ms));*/ \
_set_timer(&(pwrctl)->pwr_state_check_timer, (ms)); \
} while(0)
#define rtw_set_pwr_state_check_timer(pwrctl) \
_rtw_set_pwr_state_check_timer((pwrctl), (pwrctl)->pwr_state_check_interval)
@ -381,4 +381,3 @@ int rtw_pm_set_ips(struct adapter *padapter, u8 mode);
int rtw_pm_set_lps(struct adapter *padapter, u8 mode);
#endif //__RTL871X_PWRCTRL_H_

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