rtl8188eu: Remove CONFIG_LPS_LCLK

This symbol is not defined.

Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2015-02-24 20:22:38 -06:00
parent 4bfca25407
commit e932bd9250
8 changed files with 5 additions and 563 deletions

View file

@ -531,15 +531,6 @@ s32 rtl8188eu_xmit_buf_handler(struct adapter *padapter)
if(check_pending_xmitbuf(pxmitpriv) == false)
return _SUCCESS;
#ifdef CONFIG_LPS_LCLK
ret = rtw_register_tx_alive(padapter);
if (ret != _SUCCESS) {
RT_TRACE(_module_hal_xmit_c_, _drv_notice_,
("%s: wait to leave LPS_LCLK\n", __FUNCTION__));
return _SUCCESS;
}
#endif
do {
pxmitbuf = dequeue_pending_xmitbuf(pxmitpriv);
if (pxmitbuf == NULL) break;
@ -547,11 +538,6 @@ s32 rtl8188eu_xmit_buf_handler(struct adapter *padapter)
rtw_write_port(padapter, pxmitbuf->ff_hwaddr, pxmitbuf->len, (unsigned char*)pxmitbuf);
} while (1);
#ifdef CONFIG_LPS_LCLK
rtw_unregister_tx_alive(padapter);
#endif
return _SUCCESS;
}
#endif

View file

@ -3010,19 +3010,6 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
#endif
break;
case HW_VAR_SET_RPWM:
#ifdef CONFIG_LPS_LCLK
{
u8 ps_state = *((u8 *)val);
/* rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit) for 88e. */
/* BIT0 value - 1: 32k, 0:40MHz. */
/* BIT6 value - 1: report cpwm value after success set, 0:do not report. */
/* BIT7 value - Toggle bit change. */
/* modify by Thomas. 2012/4/2. */
ps_state = ps_state & 0xC1;
/* DBG_871X("##### Change RPWM value to = %x for switch clk #####\n",ps_state); */
rtw_write8(Adapter, REG_USB_HRPWM, ps_state);
}
#endif
break;
case HW_VAR_H2C_FW_PWRMODE:
{
@ -3364,11 +3351,6 @@ static void GetHwReg8188EU(struct adapter *Adapter, u8 variable, u8* val)
}
break;
case HW_VAR_GET_CPWM:
#ifdef CONFIG_LPS_LCLK
{
*val = rtw_read8(Adapter, REG_USB_HCPWM);
}
#endif
break;
case HW_VAR_C2HEVT_CLEAR:
*val = rtw_read8(Adapter, REG_C2HEVT_CLEAR);

View file

@ -334,16 +334,6 @@ static void interrupt_handler_8188eu(struct adapter *padapter,u16 pkt_len,u8 *pb
memcpy(&(pHalData->IntArray[0]), &(pbuf[USB_INTR_CONTENT_HISR_OFFSET]), 4);
memcpy(&(pHalData->IntArray[1]), &(pbuf[USB_INTR_CONTENT_HISRE_OFFSET]), 4);
#ifdef CONFIG_LPS_LCLK
if ( pHalData->IntArray[0] & IMR_CPWM_88E ) {
memcpy(&pwr_rpt.state, &(pbuf[USB_INTR_CONTENT_CPWM1_OFFSET]), 1);
/* 88e's cpwm value only change BIT0, so driver need to add PS_STATE_S2 for LPS flow. */
pwr_rpt.state |= PS_STATE_S2;
_set_workitem(&(adapter_to_pwrctl(padapter)->cpwm_event));
}
#endif/* CONFIG_LPS_LCLK */
#ifdef DBG_CONFIG_ERROR_DETECT_INT
if ( pHalData->IntArray[1] & IMR_TXERR_88E )
DBG_871X("===> %s Tx Error Flag Interrupt Status \n",__FUNCTION__);