mirror of
https://github.com/lwfinger/rtl8188eu.git
synced 2025-05-09 06:43:06 +00:00
rtl8188eu: Revert part of 76e49ee
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
parent
76e49eeec2
commit
eac0a699d8
16 changed files with 1004 additions and 86 deletions
168
core/rtw_mp.c
168
core/rtw_mp.c
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@ -25,8 +25,23 @@
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#include <sys/unistd.h> /* for RFHIGHPID */
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#endif
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#ifdef CONFIG_RTL8712
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#include <rtw_mp_phy_regdef.h>
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#endif
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#ifdef CONFIG_RTL8192C
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#include <rtl8192c_hal.h>
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#endif
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#ifdef CONFIG_RTL8192D
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#include <rtl8192d_hal.h>
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#endif
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#ifdef CONFIG_RTL8723A
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#include <rtl8723a_hal.h>
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#include "rtw_bt_mp.h"
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#endif
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#ifdef CONFIG_RTL8188E
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#include "odm_precomp.h"
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#include "rtl8188e_hal.h"
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#endif
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#ifdef CONFIG_MP_INCLUDED
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@ -322,9 +337,25 @@ void free_mp_priv(struct mp_priv *pmp_priv)
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pmp_priv->pmp_xmtframe_buf = NULL;
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}
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#if defined (CONFIG_RTL8192C) || defined (CONFIG_RTL8723A)
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#define PHY_IQCalibrate(a,b) rtl8192c_PHY_IQCalibrate(a,b)
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#define PHY_LCCalibrate(a) rtl8192c_PHY_LCCalibrate(a)
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//#define dm_CheckTXPowerTracking(a) rtl8192c_odm_CheckTXPowerTracking(a)
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#define PHY_SetRFPathSwitch(a,b) rtl8192c_PHY_SetRFPathSwitch(a,b)
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#endif
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#ifdef CONFIG_RTL8192D
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#define PHY_IQCalibrate(a,b) rtl8192d_PHY_IQCalibrate(a)
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#define PHY_LCCalibrate(a) rtl8192d_PHY_LCCalibrate(a)
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//#define dm_CheckTXPowerTracking(a) rtl8192d_odm_CheckTXPowerTracking(a)
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#define PHY_SetRFPathSwitch(a,b) rtl8192d_PHY_SetRFPathSwitch(a,b)
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#endif
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#ifdef CONFIG_RTL8188E
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#define PHY_IQCalibrate(a,b) PHY_IQCalibrate_8188E(a,b)
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#define PHY_LCCalibrate(a) PHY_LCCalibrate_8188E(a)
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#define PHY_SetRFPathSwitch(a,b) PHY_SetRFPathSwitch_8188E(a,b)
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#endif
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s32
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MPT_InitializeAdapter(
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@ -349,28 +380,66 @@ MPT_InitializeAdapter(
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pMptCtx->bMptIndexEven = true; //default gain index is -6.0db
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pMptCtx->h2cReqNum = 0x0;
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/* Init mpt event. */
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//init for BT MP
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#ifdef CONFIG_RTL8723A
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pMptCtx->bMPh2c_timeout = false;
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pMptCtx->MptH2cRspEvent = false;
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pMptCtx->MptBtC2hEvent = false;
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_rtw_init_sema(&pMptCtx->MPh2c_Sema, 0);
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_init_timer( &pMptCtx->MPh2c_timeout_timer, pAdapter->pnetdev, MPh2c_timeout_handle, pAdapter );
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#endif
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pMptCtx->bMptWorkItemInProgress = false;
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pMptCtx->CurrMptAct = NULL;
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//-------------------------------------------------------------------------
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#if 1
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// Don't accept any packets
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rtw_write32(pAdapter, REG_RCR, 0);
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#else
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// Accept CRC error and destination address
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//pHalData->ReceiveConfig |= (RCR_ACRC32|RCR_AAP);
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//rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig);
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rtw_write32(pAdapter, REG_RCR, 0x70000101);
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#endif
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if (IS_HARDWARE_TYPE_8192DU(pAdapter))
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{
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rtw_write32(pAdapter, REG_LEDCFG0, 0x8888);
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}
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else
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{
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//rtw_write32(pAdapter, REG_LEDCFG0, 0x08080);
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ledsetting = rtw_read32(pAdapter, REG_LEDCFG0);
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#if defined (CONFIG_RTL8192C) || defined( CONFIG_RTL8192D )
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rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS);
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#endif
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}
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PHY_IQCalibrate(pAdapter, false);
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dm_CheckTXPowerTracking(&pHalData->odmpriv); //trigger thermal meter
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PHY_LCCalibrate(pAdapter);
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#ifdef CONFIG_PCI_HCI
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PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); //Wifi default use Main
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#else
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#ifdef CONFIG_RTL8192C
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if (pHalData->BoardType == BOARD_MINICARD)
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PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); //default use Main
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#endif
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#endif
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pMptCtx->backup0xc50 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0);
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pMptCtx->backup0xc58 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0);
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pMptCtx->backup0xc30 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_RxDetector1, bMaskByte0);
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#ifdef CONFIG_RTL8188E
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pMptCtx->backup0x52_RF_A = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
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pMptCtx->backup0x52_RF_B = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
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#endif
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//set ant to wifi side in mp mode
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rtw_write16(pAdapter, 0x870, 0x300);
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@ -407,6 +476,10 @@ MPT_DeInitAdapter(
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PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
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pMptCtx->bMptDrvUnload = true;
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#ifdef CONFIG_RTL8723A
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_rtw_free_sema(&(pMptCtx->MPh2c_Sema));
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_cancel_timer_ex( &pMptCtx->MPh2c_timeout_timer);
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#endif
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}
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static u8 mpt_ProStartTest(PADAPTER padapter)
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@ -441,15 +514,22 @@ void GetPowerTracking(PADAPTER padapter, u8 *enable)
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static void disable_dm(PADAPTER padapter)
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{
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#ifndef CONFIG_RTL8723A
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u8 v8;
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#endif
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
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struct dm_priv *pdmpriv = &pHalData->dmpriv;
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//3 1. disable firmware dynamic mechanism
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// disable Power Training, Rate Adaptive
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#ifdef CONFIG_RTL8723A
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SetBcnCtrlReg(padapter, 0, EN_BCN_FUNCTION);
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#else
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v8 = rtw_read8(padapter, REG_BCN_CTRL);
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v8 &= ~EN_BCN_FUNCTION;
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rtw_write8(padapter, REG_BCN_CTRL, v8);
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#endif
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//3 2. disable driver dynamic mechanism
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// disable Dynamic Initial Gain
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@ -458,6 +538,9 @@ static void disable_dm(PADAPTER padapter)
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Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, false);
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// enable APK, LCK and IQK but disable power tracking
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#ifndef CONFIG_RTL8188E
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pdmpriv->TxPowerTrackControl = false;
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#endif
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Switch_DM_Func(padapter, DYNAMIC_RF_CALIBRATION, true);
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}
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@ -569,10 +652,24 @@ end_of_mp_start_test:
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if (res == _SUCCESS)
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{
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// set MSR to WIFI_FW_ADHOC_STATE
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#if !defined (CONFIG_RTL8712)
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val8 = rtw_read8(padapter, MSR) & 0xFC; // 0x0102
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val8 |= WIFI_FW_ADHOC_STATE;
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rtw_write8(padapter, MSR, val8); // Link in ad hoc network
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#endif
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#if defined (CONFIG_RTL8712)
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rtw_write8(padapter, MSR, 1); // Link in ad hoc network
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rtw_write8(padapter, RCR, 0); // RCR : disable all pkt, 0x10250048
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rtw_write8(padapter, RCR+2, 0x57); // RCR disable Check BSSID, 0x1025004a
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// disable RX filter map , mgt frames will put in RX FIFO 0
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rtw_write16(padapter, RXFLTMAP0, 0x0); // 0x10250116
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val8 = rtw_read8(padapter, EE_9346CR); // 0x1025000A
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if (!(val8 & _9356SEL))//boot from EFUSE
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efuse_change_max_size(padapter);
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#endif
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}
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return res;
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@ -726,6 +823,27 @@ void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter ,bool bMain)
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}
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#if defined (CONFIG_RTL8712)
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/*------------------------------Define structure----------------------------*/
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typedef struct _R_ANTENNA_SELECT_OFDM {
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u32 r_tx_antenna:4;
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u32 r_ant_l:4;
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u32 r_ant_non_ht:4;
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u32 r_ant_ht1:4;
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u32 r_ant_ht2:4;
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u32 r_ant_ht_s1:4;
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u32 r_ant_non_ht_s1:4;
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u32 OFDM_TXSC:2;
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u32 Reserved:2;
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}R_ANTENNA_SELECT_OFDM;
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typedef struct _R_ANTENNA_SELECT_CCK {
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u8 r_cckrx_enable_2:2;
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u8 r_cckrx_enable:2;
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u8 r_ccktx_enable:4;
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}R_ANTENNA_SELECT_CCK;
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#endif
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s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
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{
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return Hal_SetThermalMeter( pAdapter, target_ther);
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@ -788,7 +906,15 @@ void PhySetTxPowerLevel(PADAPTER pAdapter)
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struct mp_priv *pmp_priv = &pAdapter->mppriv;
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if (pmp_priv->bSetTxPower==0) // for NO manually set power index
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{
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#ifdef CONFIG_RTL8188E
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PHY_SetTxPowerLevel8188E(pAdapter,pmp_priv->channel);
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#elif defined(CONFIG_RTL8192D)
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PHY_SetTxPowerLevel8192D(pAdapter,pmp_priv->channel);
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#else
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PHY_SetTxPowerLevel8192C(pAdapter,pmp_priv->channel);
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#endif
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}
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}
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//------------------------------------------------------------------------------
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@ -945,24 +1071,44 @@ void SetPacketTx(PADAPTER padapter)
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//3 3. init TX descriptor
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// offset 0
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#if defined(CONFIG_RTL8188E) && !defined(CONFIG_RTL8188E_SDIO)
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desc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
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desc->txdw0 |= cpu_to_le32(pkt_size & 0x0000FFFF); // packet size
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desc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00FF0000); //32 bytes for TX Desc
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if (bmcast) desc->txdw0 |= cpu_to_le32(BMC); // broadcast packet
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desc->txdw1 |= cpu_to_le32((0x01 << 26) & 0xff000000);
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#endif
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// offset 4
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#ifndef CONFIG_RTL8188E
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desc->txdw1 |= cpu_to_le32(BK); // don't aggregate(AMPDU)
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desc->txdw1 |= cpu_to_le32((pattrib->mac_id) & 0x1F); //CAM_ID(MAC_ID)
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#else
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desc->txdw1 |= cpu_to_le32((pattrib->mac_id) & 0x3F); //CAM_ID(MAC_ID)
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#endif
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desc->txdw1 |= cpu_to_le32((pattrib->qsel << QSEL_SHT) & 0x00001F00); // Queue Select, TID
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#ifdef CONFIG_RTL8188E
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desc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000F0000); // Rate Adaptive ID
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#else
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desc->txdw1 |= cpu_to_le32((pattrib->raid << Rate_ID_SHT) & 0x000F0000); // Rate Adaptive ID
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#endif
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// offset 8
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// desc->txdw2 |= cpu_to_le32(AGG_BK);//AGG BK
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// offset 12
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desc->txdw3 |= cpu_to_le32((pattrib->seqnum<<16)&0x0fff0000);
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// desc->txdw3 |= cpu_to_le32((pattrib->seqnum & 0xFFF) << SEQ_SHT);
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//desc->txdw3 |= cpu_to_le32((pattrib->seqnum << SEQ_SHT) & 0xffff0000);
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// offset 16
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desc->txdw4 |= cpu_to_le32(HW_SSN);
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//desc->txdw4 |= cpu_to_le32(QoS)
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#ifdef CONFIG_RTL8188E
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desc->txdw4 |= cpu_to_le32(HW_SSN);
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#else
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desc->txdw4 |= cpu_to_le32(HW_SEQ_EN);
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#endif
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desc->txdw4 |= cpu_to_le32(USERATE);
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desc->txdw4 |= cpu_to_le32(DISDATAFB);
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@ -980,8 +1126,12 @@ void SetPacketTx(PADAPTER padapter)
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if (pmp_priv->rateidx > MPT_RATE_54M)
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desc->txdw5 |= cpu_to_le32(SGI); // MCS Short Guard Interval
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}
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desc->txdw5 |= cpu_to_le32(RTY_LMT_EN); // retry limit enable
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desc->txdw5 |= cpu_to_le32(0x00180000); // DATA/RTS Rate Fallback Limit
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#ifdef CONFIG_RTL8188E
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desc->txdw5 |= cpu_to_le32(RTY_LMT_EN); // retry limit enable
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desc->txdw5 |= cpu_to_le32(0x00180000); // DATA/RTS Rate Fallback Limit
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#else
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desc->txdw5 |= cpu_to_le32(0x0001FF00); // DATA/RTS Rate Fallback Limit
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#endif
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//3 4. make wlan header, make_wlanhdr()
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hdr = (struct rtw_ieee80211_hdr *)pkt_start;
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@ -1036,8 +1186,11 @@ void SetPacketRx(PADAPTER pAdapter, u8 bStartRx)
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{
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
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if (bStartRx) {
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if (bStartRx)
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{
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// Accept CRC error and destination address
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#if 1
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//ndef CONFIG_RTL8723A
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pHalData->ReceiveConfig = AAP | APM | AM | AB | APP_ICV | ADF | AMF | HTC_LOC_CTRL | APP_MIC | APP_PHYSTS;
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pHalData->ReceiveConfig |= ACRC32;
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@ -1046,7 +1199,12 @@ void SetPacketRx(PADAPTER pAdapter, u8 bStartRx)
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// Accept all data frames
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rtw_write16(pAdapter, REG_RXFLTMAP2, 0xFFFF);
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} else {
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#else
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rtw_write32(pAdapter, REG_RCR, 0x70000101);
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#endif
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}
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else
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{
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rtw_write32(pAdapter, REG_RCR, 0);
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}
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}
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