From efaf0dce64a68a5223a02d891382ff7f153f6c69 Mon Sep 17 00:00:00 2001
From: Larry Finger <Larry.Finger@lwfinger.net>
Date: Fri, 27 Feb 2015 20:38:37 -0600
Subject: [PATCH] rtl8188eu: Remove remaining configuration code for other
 devices

Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
---
 hal/odm.h                |  8 --------
 include/Hal8188EPhyCfg.h |  5 -----
 include/autoconf.h       | 18 ------------------
 3 files changed, 31 deletions(-)

diff --git a/hal/odm.h b/hal/odm.h
index 7f58331..eb8aa3a 100755
--- a/hal/odm.h
+++ b/hal/odm.h
@@ -85,11 +85,7 @@
 #define	Smooth_TH_3	4
 #define   Smooth_Step_Size 5
 #define	Adaptive_SIR	1
-#if(RTL8723_FPGA_VERIFICATION == 1)
-#define	PSD_RESCAN		1
-#else
 #define	PSD_RESCAN		4
-#endif
 #define	PSD_SCAN_INTERVAL	700 /* ms */
 
 
@@ -309,11 +305,7 @@ typedef struct _ODM_RATE_ADAPTIVE
 #define IQK_MAC_REG_NUM		4
 #define IQK_ADDA_REG_NUM		16
 #define IQK_BB_REG_NUM_MAX	10
-#if (RTL8192D_SUPPORT==1) 
-#define IQK_BB_REG_NUM		10
-#else
 #define IQK_BB_REG_NUM		9
-#endif
 #define HP_THERMAL_NUM		8
 
 #define AVG_THERMAL_NUM		8
diff --git a/include/Hal8188EPhyCfg.h b/include/Hal8188EPhyCfg.h
index 1badfd5..523a05b 100755
--- a/include/Hal8188EPhyCfg.h
+++ b/include/Hal8188EPhyCfg.h
@@ -345,11 +345,6 @@ storePwrIndexDiffRateOffset(
 #define PHY_QueryMacReg PHY_QueryBBReg
 
 //==================================================================
-// Note: If SIC_ENABLE under PCIE, because of the slow operation
-//	you should
-//	2) "#define RTL8723_FPGA_VERIFICATION	1"				in Precomp.h.WlanE.Windows
-//	3) "#define RTL8190_Download_Firmware_From_Header	0"	in Precomp.h.WlanE.Windows if needed.
-//
 #define	SIC_ENABLE		0
 #define	SIC_HW_SUPPORT		0
 //==================================================================
diff --git a/include/autoconf.h b/include/autoconf.h
index 2cb862c..64ddeab 100755
--- a/include/autoconf.h
+++ b/include/autoconf.h
@@ -95,32 +95,14 @@
  * Outsource  Related Config
  */
 
-#define		RTL8192CE_SUPPORT				0
-#define		RTL8192CU_SUPPORT			0
-#define		RTL8192C_SUPPORT				(RTL8192CE_SUPPORT|RTL8192CU_SUPPORT)
-
-#define		RTL8192DE_SUPPORT				0
-#define		RTL8192DU_SUPPORT			0
-#define		RTL8192D_SUPPORT				(RTL8192DE_SUPPORT|RTL8192DU_SUPPORT)
-
-#define		RTL8723AU_SUPPORT				0
-#define		RTL8723AS_SUPPORT				0
-#define		RTL8723AE_SUPPORT				0
-#define		RTL8723A_SUPPORT				(RTL8723AU_SUPPORT|RTL8723AS_SUPPORT|RTL8723AE_SUPPORT)
-
-#define		RTL8723_FPGA_VERIFICATION		0
-
 #define RTL8188EE_SUPPORT				0
 #define RTL8188EU_SUPPORT				1
 #define RTL8188ES_SUPPORT				0
 #define RTL8188E_SUPPORT				(RTL8188EE_SUPPORT|RTL8188EU_SUPPORT|RTL8188ES_SUPPORT)
 #define RTL8188E_FOR_TEST_CHIP			0
-//#if (RTL8188E_SUPPORT==1)
 #define RATE_ADAPTIVE_SUPPORT			1
 #define POWER_TRAINING_ACTIVE			1
 
-//#endif
-
 #ifdef CONFIG_TX_EARLY_MODE
 #define	RTL8188E_EARLY_MODE_PKT_NUM_10	0
 #endif