rtl8188eu: Remove dead code inside #if 0 .... #endif

Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2018-11-12 19:26:10 -06:00
parent e3e242b712
commit f0050d3365
52 changed files with 38 additions and 3703 deletions

View file

@ -52,20 +52,6 @@ static u8 RETRY_PENALTY_UP[RETRYSIZE + 1] = {49, 44, 16, 16, 0, 48}; /* 12% for
static u8 PT_PENALTY[RETRYSIZE + 1] = {34, 31, 30, 24, 0, 32};
#if 0
static u8 RETRY_PENALTY_IDX[2][RATESIZE] = {{
4, 4, 4, 5, 4, 4, 5, 7, 7, 7, 8, 0x0a, /* SS>TH */
4, 4, 4, 4, 6, 0x0a, 0x0b, 0x0d,
5, 5, 7, 7, 8, 0x0b, 0x0d, 0x0f
}, /* 0329 R01 */
{
4, 4, 4, 5, 7, 7, 9, 9, 0x0c, 0x0e, 0x10, 0x12, /* SS<TH */
4, 4, 5, 5, 6, 0x0a, 0x11, 0x13,
9, 9, 9, 9, 0x0c, 0x0e, 0x11, 0x13
}
};
#endif
/* wilson modify */
static u8 RETRY_PENALTY_IDX[2][RATESIZE] = {{
@ -106,14 +92,6 @@ static u8 TRYING_NECESSARY[RATESIZE] = {2, 2, 2, 2,
4, 4, 7, 10, 10, 12, 12, 18,
5, 7, 7, 8, 11, 18, 36, 60
}; /* 0329 */ /* 1207 */
#if 0
static u8 POOL_RETRY_TH[RATESIZE] = {30, 30, 30, 30,
30, 30, 25, 25, 20, 15, 15, 10,
30, 25, 25, 20, 15, 10, 10, 10,
30, 25, 25, 20, 15, 10, 10, 10
};
#endif
static u8 DROPING_NECESSARY[RATESIZE] = {1, 1, 1, 1,
1, 2, 3, 4, 5, 6, 7, 8,
1, 2, 3, 4, 5, 6, 7, 8,
@ -630,34 +608,9 @@ odm_ra_info_init(
)
{
struct _odm_ra_info_ *p_ra_info = &p_dm_odm->ra_info[mac_id];
#if 0
u8 wireless_mode = 0xFF; /* invalid value */
u8 max_rate_idx = 0x13; /* MCS7 */
if (p_dm_odm->p_wireless_mode != NULL)
wireless_mode = *(p_dm_odm->p_wireless_mode);
if (wireless_mode != 0xFF) {
if (wireless_mode & ODM_WM_N24G)
max_rate_idx = 0x13;
else if (wireless_mode & ODM_WM_G)
max_rate_idx = 0x0b;
else if (wireless_mode & ODM_WM_B)
max_rate_idx = 0x03;
}
/* printk("%s ==>wireless_mode:0x%08x,max_raid_idx:0x%02x\n ",__func__,wireless_mode,max_rate_idx); */
ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD,
("odm_ra_info_init(): wireless_mode:0x%08x,max_raid_idx:0x%02x\n",
wireless_mode, max_rate_idx));
p_ra_info->decision_rate = max_rate_idx;
p_ra_info->pre_rate = max_rate_idx;
p_ra_info->highest_rate = max_rate_idx;
#else
p_ra_info->decision_rate = 0x13;
p_ra_info->pre_rate = 0x13;
p_ra_info->highest_rate = 0x13;
#endif
p_ra_info->lowest_rate = 0;
p_ra_info->rate_id = 0;
p_ra_info->rate_mask = 0xffffffff;

View file

@ -313,11 +313,6 @@ odm_update_rx_idle_ant(
value16 |= ((u16)optional_ant << 6);
value16 |= ((u16)default_ant << 9);
odm_write_2byte(p_dm_odm, ODM_REG_TRMUX_11AC + 2, value16);
#if 0
odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC, BIT(21) | BIT20 | BIT19, default_ant); /* Default RX */
odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC, BIT(24) | BIT23 | BIT22, optional_ant); /* Optional RX */
odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC, BIT(27) | BIT26 | BIT25, default_ant); /* Default TX */
#endif
}
if (p_dm_odm->support_ic_type == ODM_RTL8188E) {
@ -1614,39 +1609,12 @@ odm_fast_ant_training(
if (target_ant_path_a == 0)
odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF);
}
#if 0
#if (RTL8192E_SUPPORT == 1)
/* 3 [path-B]--------------------------- */
if (is_pkt_filter_macth_path_b == false) {
if (p_dm_odm->fat_print_rssi == 1)
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***[%d]{path-B}: None Packet is matched\n\n\n", __LINE__));
} else {
if (p_dm_odm->fat_print_rssi == 1) {
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
(" ***target_ant_path_b = (( %d )) *** max_rssi = (( %d ))***\n\n\n", target_ant_path_b, max_rssi_path_b));
}
odm_set_bb_reg(p_dm_odm, 0xB38, BIT(21) | BIT20 | BIT19, target_ant_path_b); /* Default RX is Omni, Optional RX is the best decision by FAT */
odm_set_bb_reg(p_dm_odm, 0x80c, BIT(21), 1); /* Reg80c[21]=1'b1 //from TX Info */
p_dm_fat_table->antsel_pathB[p_dm_fat_table->train_idx] = target_ant_path_b;
}
#endif
#endif
/* 2 Reset counter */
for (i = 0; i < (p_dm_odm->fat_comb_a); i++) {
p_dm_fat_table->ant_sum_rssi[i] = 0;
p_dm_fat_table->ant_rssi_cnt[i] = 0;
}
/*
#if (RTL8192E_SUPPORT == 1)
for(i=0; i<=(p_dm_odm->fat_comb_b); i++)
{
p_dm_fat_table->antSumRSSI_pathB[i] = 0;
p_dm_fat_table->antRSSIcnt_pathB[i] = 0;
}
#endif
*/
p_dm_fat_table->fat_state = FAT_PREPARE_STATE;
return;
@ -3225,11 +3193,6 @@ odm_antenna_diversity_init(
{
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
#if 0
if (p_dm_odm->mp_mode == true)
return;
#endif
#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
odm_ant_div_config(p_dm_odm);
odm_ant_div_init(p_dm_odm);

View file

@ -457,16 +457,8 @@ phydm_bb_debug_info(
u8 rf_gain_path_a, rf_gain_path_b, rf_gain_path_c, rf_gain_path_d;
u8 rx_snr_path_a, rx_snr_path_b, rx_snr_path_c, rx_snr_path_d;
s32 sig_power;
const char *L_rate[8] = {"6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M"};
#if 0
const double evm_comp_20M = 0.579919469776867; /* 10*log10(64.0/56.0) */
const double evm_comp_40M = 0.503051183113957; /* 10*log10(128.0/114.0) */
const double evm_comp_80M = 0.244245993314183; /* 10*log10(256.0/242.0) */
const double evm_comp_160M = 0.244245993314183; /* 10*log10(512.0/484.0) */
#endif
if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) {
phydm_bb_debug_info_n_series(p_dm_odm, &used, output, &out_len);
return;
@ -2300,21 +2292,6 @@ phydm_fw_trace_handler_code(
/**/
/*C2H_RA_Dbg_code(F_RA_H2C,1,0, SysMib.ODM.DEBUG.fw_trace_en, mode, macid, 0); //RA MASK*/
}
#if 0
else if (dbg_num == 2) {
if (content_0 == 1) {
ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x40] MACID=((%d)), rate ID=((%d)), SGI=((%d)), BW=((%d))\n", content_1, content_2, content_3, content_4));
/**/
} else if (content_0 == 2) {
ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x40] VHT_en=((%d)), Disable_PowerTraining=((%d)), Disable_RA=((%d)), No_Update=((%d))\n", content_1, content_2, content_3, content_4));
/**/
} else if (content_0 == 3) {
ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x40] RA_MSK=[%x | %x | %x | %x ]\n", content_1, content_2, content_3, content_4));
/**/
}
}
#endif
}
}
/*--------------------------------------------*/
@ -2359,11 +2336,6 @@ phydm_fw_trace_handler_8051(
{
#if CONFIG_PHYDM_DEBUG_FUNCTION
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
#if 0
if (cmd_len >= 3)
cmd_buf[cmd_len - 1] = '\0';
ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s\n", &(cmd_buf[3])));
#else
int i = 0;
u8 extend_c2h_sub_id = 0, extend_c2h_dbg_len = 0, extend_c2h_dbg_seq = 0;
@ -2397,6 +2369,5 @@ go_backfor_aggre_dbg_pkt:
}
#endif
#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/
}

View file

@ -39,20 +39,14 @@
#define _bit_all(_name) BIT_##_name
#define _bit_ic(_name, _ic) BIT_##_name##_ic
/* _cat: implemented by Token-Pasting Operator. */
#if 0
#define _cat(_name, _ic_type, _func) \
(\
_func##_all(_name) \
)
#endif
/* _cat: implemented by Token-Passing Operator. */
/*===================================
#define ODM_REG_DIG_11N 0xC50
#define ODM_REG_DIG_11AC 0xDDD
ODM_REG(DIG,_pdm_odm)
ODM_REG(DIG, _pdm_odm)
=====================================*/
#define _reg_11N(_name) ODM_REG_##_name##_11N

View file

@ -219,19 +219,7 @@ odm_ra_para_adjust_init(
u8 ra_para_pool_u8[3] = { RADBG_RTY_PENALTY, RADBG_RATE_UP_RTY_RATIO, RADBG_RATE_DOWN_RTY_RATIO};
u8 rate_size_ht_1ss = 20, rate_size_ht_2ss = 28, rate_size_ht_3ss = 36; /*4+8+8+8+8 =36*/
u8 rate_size_vht_1ss = 10, rate_size_vht_2ss = 20, rate_size_vht_3ss = 30; /*10 + 10 +10 =30*/
#if 0
/* RTY_PENALTY = 1, u8 */
/* N_HIGH = 2, */
/* N_LOW = 3, */
/* RATE_UP_TABLE = 4, */
/* RATE_DOWN_TABLE = 5, */
/* TRYING_NECESSARY = 6, */
/* DROPING_NECESSARY = 7, */
/* RATE_UP_RTY_RATIO = 8, u8 */
/* RATE_DOWN_RTY_RATIO= 9, u8 */
/* ALL_PARA = 0xff */
#endif
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("odm_ra_para_adjust_init\n"));
if (p_dm_odm->support_ic_type & (ODM_RTL8188F | ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8723D))

View file

@ -288,89 +288,6 @@ static struct _RT_CHANNEL_PLAN_MAXPWR chnl_plan_pwr_max_2g[] = {
/* ...... */
};
#if 0
/* ===========================================1:(2G_WORLD, 5G_NULL) */
struct _RT_CHANNEL_PLAN_MAXPWR RT_DOMAIN_01 = {{{01, 13, 20}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}}, 1}
/* ===========================================2:(2G_ETSI1, 5G_NULL) */
RT_DOMAIN_02 = {{{01, 13, 20}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}}, 1}
/* ===========================================3:(2G_FCC1, 5G_NULL) */
RT_DOMAIN_03 = {{{01, 11, 30}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}}, 1}
/* ===========================================4:(2G_MKK1, 5G_NULL) */
RT_DOMAIN_04 = {{{01, 14, 23}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}}, 1}
/* ===========================================5:(2G_ETSI2, 5G_NULL) */
RT_DOMAIN_05 = {{{10, 13, 20}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}}, 1}
/* ===========================================6:(2G_FCC1, 5G_FCC1) */
RT_DOMAIN_06 = {{{01, 13, 30}, {36, 48, 17}, {52, 64, 24}, {100, 140, 24}, {149, 165, 30}}, 5}
/* ===========================================7:(2G_WORLD, 5G_ETSI1) */
RT_DOMAIN_07 = {{{01, 13, 20}, {36, 48, 23}, {52, 64, 23}, {100, 140, 30}, {NR, NR, 0}}, 4}
/* ===========================================8:(2G_MKK1, 5G_MKK1) */
RT_DOMAIN_08 = {{{01, 14, 23}, {36, 48, 23}, {52, 64, 23}, {100, 140, 23}, {NR, NR, 0}}, 4}
/* ===========================================9:(2G_WORLD, 5G_KCC1) */
RT_DOMAIN_09 = {{{01, 13, 20}, {36, 48, 17}, {52, 64, 23}, {100, 124, 23}, {149, 165, 23}}, 5}
/* ===========================================10:(2G_WORLD, 5G_FCC2) */
RT_DOMAIN_10 = {{{01, 13, 20}, {36, 48, 17}, {NR, NR, 0}, {NR, NR, 0}, {149, 165, 30}}, 3}
/* ===========================================11:(2G_WORLD, 5G_FCC3) */
RT_DOMAIN_11 = {{{01, 13, 20}, {36, 48, 23}, {52, 64, 23}, {NR, NR, 0}, {149, 165, 23}}, 4}
/* ===========================================12:(2G_WORLD, 5G_FCC4) */
RT_DOMAIN_12 = {{{01, 13, 20}, {36, 48, 24}, {52, 64, 24}, {NR, NR, 0}, {149, 161, 27}}, 4}
/* ===========================================13:(2G_WORLD, 5G_FCC5) */
RT_DOMAIN_13 = {{{01, 13, 20}, {NR, NR, 0}, {NR, NR, 0}, {NR, NR, 0}, {149, 165, 27}}, 2}
/* ===========================================14:(2G_WORLD, 5G_FCC6) */
RT_DOMAIN_14 = {{{01, 13, 20}, {36, 48, 17}, {52, 64, 17}, {NR, NR, 0}, {NR, NR, 0}}, 3}
/* ===========================================15:(2G_FCC1, 5G_FCC7) */
RT_DOMAIN_15 = {{{01, 11, 30}, {36, 48, 23}, {52, 64, 24}, {100, 140, 24}, {149, 165, 30}}, 5}
/* ===========================================16:(2G_WORLD, 5G_ETSI2) */
RT_DOMAIN_16 = {{{01, 13, 20}, {36, 48, 23}, {52, 64, 23}, {100, 140, 30}, {149, 165, 30}}, 5}
/* ===========================================17:(2G_WORLD, 5G_ETSI3) */
RT_DOMAIN_17 = {{{01, 13, 20}, {36, 48, 23}, {52, 64, 23}, {100, 132, 30}, {149, 165, 20}}, 5}
/* ===========================================18:(2G_MKK1, 5G_MKK2) */
RT_DOMAIN_18 = {{{01, 14, 23}, {36, 48, 23}, {52, 64, 23}, {NR, NR, 0}, {NR, NR, 0}}, 3}
/* ===========================================19:(2G_MKK1, 5G_MKK3) */
RT_DOMAIN_19 = {{{01, 14, 23}, {NR, NR, 0}, {NR, NR, 0}, {100, 140, 23}, {NR, NR, 0}}, 2}
/* ===========================================20:(2G_FCC1, 5G_NCC1) */
RT_DOMAIN_20 = {{{01, 11, 30}, {NR, NR, 0}, {56, 64, 23}, {100, 140, 24}, {149, 165, 30}}, 4}
/* ===========================================21:(2G_FCC1, 5G_NCC2) */
RT_DOMAIN_21 = {{{01, 11, 30}, {NR, NR, 0}, {56, 64, 23}, {NR, NR, 0}, {149, 165, 30}}, 3}
/* ===========================================22:(2G_WORLD, 5G_FCC3) */
RT_DOMAIN_22 = {{{01, 13, 24}, {36, 48, 20}, {52, 64, 24}, {NR, NR, 0}, {149, 165, 30}}, 4}
/* ===========================================23:(2G_WORLD, 5G_ETSI2) */
RT_DOMAIN_23 = {{{01, 13, 20}, {36, 48, 23}, {52, 64, 23}, {100, 140, 30}, {149, 165, 30}}, 5}
#endif
/*
* counter & Realtek channel plan transfer table.
* */
@ -383,93 +300,4 @@ struct _RT_CHANNEL_PLAN_COUNTRY_TRANSFER_TABLE rt_ctry_chnl_tbl[] = {
RT_5G_WORLD,
RT_CHANNEL_DOMAIN_UNDEFINED /* 2G/5G world. */
},
#if 0
{
RT_CTRY_BB, /* "Barbados巴巴多斯" */
"BB",
RT_2G_WORLD,
RT_5G_NULL,
RT_CHANNEL_DOMAIN_EFUSE_0x20 /* 2G world. 5G_NULL */
},
{
RT_CTRY_DE, /* "Germany德國" */
"DE",
RT_2G_WORLD,
RT_5G_ETSI1,
RT_CHANNEL_DOMAIN_EFUSE_0x26
},
{
RT_CTRY_US, /* "Germany德國" */
"US",
RT_2G_FCC1,
RT_5G_FCC7,
RT_CHANNEL_DOMAIN_EFUSE_0x34
},
{
RT_CTRY_JP, /* "Germany德國" */
"JP",
RT_2G_MKK1,
RT_5G_MKK1,
RT_CHANNEL_DOMAIN_EFUSE_0x34
},
{
RT_CTRY_TW, /* "Germany德國" */
"TW",
RT_2G_FCC1,
RT_5G_NCC1,
RT_CHANNEL_DOMAIN_EFUSE_0x39
},
#endif
}; /* rt_ctry_chnl_tbl */
/*
* Realtek Defined channel plan.
* */
#if 0
static struct _RT_CHANNEL_PLAN_NEW rt_chnl_plan[] = {
/* channel Plan 0x20. */
{
&rt_ctry_chnl_tbl[1], /* struct _RT_CHANNEL_PLAN_COUNTRY_TRANSFER_TABLE Country & channel plan transfer table. */
RT_CHANNEL_DOMAIN_EFUSE_0x20, /* RT_CHANNEL_DOMAIN RT channel Plan Define */
RT_2G_WORLD, /* enum rt_regulation_2g */
RT_5G_NULL, /* enum rt_regulation_5g */
RT_WORLD, /* enum rt_regulation_cmn RT Regulatory domain definition. */
RT_SREQ_NA, /* RT channel plan special & customerize requirement. */
CHNL_RT_2G_WORLD,
CHNL_RT_2G_WORLD_SCAN_TYPE,
&chnl_plan_pwr_max_2g[0],
CHNL_RT_5G_NULL,
CHNL_RT_5G_NULL_SCAN_TYPE,
},
/* channel Plan 0x26. */
{
&rt_ctry_chnl_tbl[1], /* struct _RT_CHANNEL_PLAN_COUNTRY_TRANSFER_TABLE Country & channel plan transfer table. */
RT_CHANNEL_DOMAIN_EFUSE_0x26, /* RT_CHANNEL_DOMAIN RT channel Plan Define */
RT_2G_WORLD, /* enum rt_regulation_2g */
RT_5G_ETSI1, /* enum rt_regulation_5g */
RT_WORLD, /* enum rt_regulation_cmn RT Regulatory domain definition. */
RT_SREQ_NA, /* RT channel plan special & customerize requirement. */
CHNL_RT_2G_WORLD, /* 2G workd cannel */
CHNL_RT_2G_WORLD_SCAN_TYPE,
&chnl_plan_pwr_max_2g[1],
CHNL_RT_5G_ETSI1,
CHNL_RT_5G_ETSI1_SCAN_TYPE,
}
};
#endif

View file

@ -43,57 +43,6 @@ enum rt_channel_domain_new {
};
#if 0
#define DOMAIN_CODE_2G_WORLD \
{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13
#define DOMAIN_CODE_2G_ETSI1 \
{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13
#define DOMAIN_CODE_2G_ETSI2 \
{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}, 11
#define DOMAIN_CODE_2G_FCC1 \
{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}, 14
#define DOMAIN_CODE_2G_MKK1 \
{10, 11, 12, 13}, 4
#define DOMAIN_CODE_5G_ETSI1 \
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 19
#define DOMAIN_CODE_5G_ETSI2 \
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 24
#define DOMAIN_CODE_5G_ETSI3 \
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165}, 22
#define DOMAIN_CODE_5G_FCC1 \
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 24
#define DOMAIN_CODE_5G_FCC2 \
{36, 40, 44, 48, 149, 153, 157, 161, 165}, 9
#define DOMAIN_CODE_5G_FCC3 \
{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165}, 13
#define DOMAIN_CODE_5G_FCC4 \
{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161}, 12
#define DOMAIN_CODE_5G_FCC5 \
{149, 153, 157, 161, 165}, 5
#define DOMAIN_CODE_5G_FCC6 \
{36, 40, 44, 48, 52, 56, 60, 64}, 8
#define DOMAIN_CODE_5G_FCC7 \
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 20
#define DOMAIN_CODE_5G_IC1 \
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 20
#define DOMAIN_CODE_5G_KCC1 \
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165}, 20
#define DOMAIN_CODE_5G_MKK1 \
{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 19
#define DOMAIN_CODE_5G_MKK2 \
{36, 40, 44, 48, 52, 56, 60, 64}, 8
#define DOMAIN_CODE_5G_MKK3 \
{100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 11
#define DOMAIN_CODE_5G_NCC1 \
{56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 24
#define DOMAIN_CODE_5G_NCC2 \
{56, 60, 64, 149, 153, 157, 161, 165}, 8
#define UNDEFINED \
{0}, 0
#endif
/*
*
*