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rtl8188eu: Convert all typedef statements in include/odm.h
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
parent
d8af6fff83
commit
f311a752bb
32 changed files with 603 additions and 710 deletions
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@ -40,40 +40,40 @@ Major Change History:
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void
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ODM_RASupport_Init(
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PDM_ODM_T pDM_Odm
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struct odm_dm_struct *pDM_Odm
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);
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int
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ODM_RAInfo_Init_all(
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PDM_ODM_T pDM_Odm
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struct odm_dm_struct * pDM_Odm
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);
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int
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ODM_RAInfo_Init(
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PDM_ODM_T pDM_Odm,
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struct odm_dm_struct *pDM_Odm,
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u1Byte MacID
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);
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u1Byte
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ODM_RA_GetShortGI_8188E(
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PDM_ODM_T pDM_Odm,
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struct odm_dm_struct *pDM_Odm,
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u1Byte MacID
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);
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u1Byte
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ODM_RA_GetDecisionRate_8188E(
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PDM_ODM_T pDM_Odm,
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struct odm_dm_struct *pDM_Odm,
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u1Byte MacID
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);
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u1Byte
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ODM_RA_GetHwPwrStatus_8188E(
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PDM_ODM_T pDM_Odm,
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struct odm_dm_struct *pDM_Odm,
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u1Byte MacID
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);
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void
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ODM_RA_UpdateRateInfo_8188E(
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PDM_ODM_T pDM_Odm,
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struct odm_dm_struct *pDM_Odm,
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u1Byte MacID,
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u1Byte RateID,
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u4Byte RateMask,
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@ -82,14 +82,14 @@ ODM_RA_UpdateRateInfo_8188E(
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void
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ODM_RA_SetRSSI_8188E(
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PDM_ODM_T pDM_Odm,
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struct odm_dm_struct * pDM_Odm,
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u1Byte MacID,
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u1Byte Rssi
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);
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void
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ODM_RA_TxRPT2Handle_8188E(
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PDM_ODM_T pDM_Odm,
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struct odm_dm_struct * pDM_Odm,
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pu1Byte TxRPT_Buf,
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u2Byte TxRPT_Len,
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u4Byte MacIDValidEntry0,
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@ -99,7 +99,7 @@ ODM_RA_TxRPT2Handle_8188E(
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void
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ODM_RA_Set_TxRPT_Time(
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PDM_ODM_T pDM_Odm,
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struct odm_dm_struct * pDM_Odm,
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u2Byte minRptTime
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);
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#endif
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@ -30,7 +30,7 @@
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HAL_STATUS
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ODM_ReadAndConfig_AGC_TAB_1T_8188E(
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PDM_ODM_T pDM_Odm
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struct odm_dm_struct * pDM_Odm
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);
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/******************************************************************************
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@ -39,7 +39,7 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E(
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HAL_STATUS
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ODM_ReadAndConfig_PHY_REG_1T_8188E(
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PDM_ODM_T pDM_Odm
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struct odm_dm_struct * pDM_Odm
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);
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/******************************************************************************
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@ -48,7 +48,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
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void
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ODM_ReadAndConfig_PHY_REG_PG_8188E(
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PDM_ODM_T pDM_Odm
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struct odm_dm_struct * pDM_Odm
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);
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#endif
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@ -18,7 +18,6 @@
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*
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******************************************************************************/
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#if (RTL8188E_SUPPORT == 1)
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#ifndef __INC_MAC_8188E_HW_IMG_H
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#define __INC_MAC_8188E_HW_IMG_H
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@ -28,10 +27,6 @@
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* MAC_REG.TXT
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******************************************************************************/
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HAL_STATUS
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ODM_ReadAndConfig_MAC_REG_8188E(
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PDM_ODM_T pDM_Odm
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);
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HAL_STATUS ODM_ReadAndConfig_MAC_REG_8188E( struct odm_dm_struct *pDM_Odm);
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#endif
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#endif // end of HWIMG_SUPPORT
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@ -18,17 +18,13 @@
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*
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******************************************************************************/
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#if (RTL8188E_SUPPORT == 1)
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#ifndef __INC_RF_8188E_HW_IMG_H
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#define __INC_RF_8188E_HW_IMG_H
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//static bool CheckCondition(const u4Byte Condition, const u4Byte Hex);
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/******************************************************************************
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* RadioA_1T.TXT
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******************************************************************************/
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* RadioA_1T.TXT
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******************************************************************************/
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HAL_STATUS ODM_ReadAndConfig_RadioA_1T_8188E(PDM_ODM_T pDM_Odm);
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HAL_STATUS ODM_ReadAndConfig_RadioA_1T_8188E(struct odm_dm_struct * pDM_Odm);
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#endif
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#endif // end of HWIMG_SUPPORT
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@ -23,14 +23,8 @@
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#define ODM_TARGET_CHNL_NUM_2G_5G 59
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void
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ODM_ResetIQKResult(
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PDM_ODM_T pDM_Odm
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);
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void ODM_ResetIQKResult(struct odm_dm_struct *pDM_Odm);
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u1Byte
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ODM_GetRightChnlPlaceforIQK(
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u1Byte chnl
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);
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u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl);
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#endif // #ifndef __HAL_PHY_RF_H__
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@ -29,7 +29,7 @@
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void
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ODM_TxPwrTrackAdjust88E(
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PDM_ODM_T pDM_Odm,
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struct odm_dm_struct *pDM_Odm,
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u1Byte Type, // 0 = OFDM, 1 = CCK
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pu1Byte pDirection, // 1 = +(increase) 2 = -(decrease)
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pu4Byte pOutWriteVal // Tx tracking CCK/OFDM BB swing index adjust
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427
include/odm.h
427
include/odm.h
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@ -113,18 +113,16 @@
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// 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement.
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// We need to remove to other position???
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//
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typedef struct rtl8192cd_priv {
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struct rtl8192cd_priv {
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u1Byte temp;
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};
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}rtl8192cd_priv, *prtl8192cd_priv;
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typedef struct _Dynamic_Initial_Gain_Threshold_
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{
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struct rtw_dig {
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u1Byte Dig_Enable_Flag;
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u1Byte Dig_Ext_Port_Stage;
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int RssiLowThresh;
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int RssiHighThresh;
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int RssiLowThresh;
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int RssiHighThresh;
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u4Byte FALowThresh;
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u4Byte FAHighThresh;
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@ -160,10 +158,9 @@ typedef struct _Dynamic_Initial_Gain_Threshold_
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u4Byte AntDiv_RSSI_max;
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u4Byte RSSI_max;
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}DIG_T,*pDIG_T;
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};
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typedef struct _Dynamic_Power_Saving_
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{
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struct rtl_ps {
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u1Byte PreCCAState;
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u1Byte CurCCAState;
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@ -175,9 +172,9 @@ typedef struct _Dynamic_Power_Saving_
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u1Byte initialize;
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u4Byte Reg874,RegC70,Reg85C,RegA74;
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}PS_T,*pPS_T;
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};
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typedef struct _false_ALARM_STATISTICS{
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struct false_alarm_stats {
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u4Byte Cnt_Parity_Fail;
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u4Byte Cnt_Rate_Illegal;
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u4Byte Cnt_Crc8_fail;
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@ -192,18 +189,17 @@ typedef struct _false_ALARM_STATISTICS{
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u4Byte Cnt_CCA_all;
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u4Byte Cnt_BW_USC; //Gary
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u4Byte Cnt_BW_LSC; //Gary
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}false_ALARM_STATISTICS, *Pfalse_ALARM_STATISTICS;
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};
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typedef struct _Dynamic_Primary_CCA{
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struct dyn_primary_cca {
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u1Byte PriCCA_flag;
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u1Byte intf_flag;
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u1Byte intf_type;
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u1Byte DupRTS_flag;
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u1Byte Monitor_flag;
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}Pri_CCA_T, *pPri_CCA_T;
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};
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typedef struct _RX_High_Power_
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{
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struct rx_hpc {
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u1Byte RXHP_flag;
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u1Byte PSD_func_trigger;
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u1Byte PSD_bitmap_RXHP[80];
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@ -215,7 +211,7 @@ typedef struct _RX_High_Power_
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bool RXHP_enable;
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u1Byte TP_Mode;
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RT_TIMER PSDTimer;
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}RXHP_T, *pRXHP_T;
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};
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#define ASSOCIATE_ENTRY_NUM 32 // Max size of AsocEntry[].
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#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
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@ -232,8 +228,7 @@ typedef struct _RX_High_Power_
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#define TRAFFIC_LOW 0
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#define TRAFFIC_HIGH 1
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typedef struct _SW_Antenna_Switch_
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{
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struct sw_ant_switch {
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u1Byte try_flag;
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s4Byte PreRSSI;
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u1Byte CurAntenna;
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@ -274,24 +269,22 @@ typedef struct _SW_Antenna_Switch_
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u1Byte TargetSTA;
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u1Byte antsel;
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u1Byte RxIdleAnt;
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}SWAT_T, *pSWAT_T;
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};
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typedef struct _EDCA_TURBO_
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{
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struct edca_turbo {
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bool bCurrentTurboEDCA;
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bool bIsCurRDLState;
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u4Byte prv_traffic_idx; // edca turbo
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}EDCA_T,*pEDCA_T;
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};
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typedef struct _ODM_RATE_ADAPTIVE
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{
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struct odm_rate_adapt {
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u1Byte Type; // DM_Type_ByFW/DM_Type_ByDriver
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u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH
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u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW
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u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW
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u4Byte LastRATR; // RATR Register Content
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} ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE;
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};
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#define IQK_MAC_REG_NUM 4
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#define IQK_ADDA_REG_NUM 16
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@ -313,8 +306,7 @@ typedef struct _ODM_RATE_ADAPTIVE
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//
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#define MAX_PATH_NUM_92CS 2
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typedef struct _ODM_Phy_Status_Info_
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{
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struct odm_phy_status_info {
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u1Byte RxPWDBAll;
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u1Byte SignalQuality; // in 0-100 index.
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u1Byte RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; //EVM
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@ -325,11 +317,10 @@ typedef struct _ODM_Phy_Status_Info_
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u1Byte SignalStrength; // in 0-100 index.
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u1Byte RxPwr[MAX_PATH_NUM_92CS];//per-path's pwdb
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u1Byte RxSNR[MAX_PATH_NUM_92CS];//per-path's SNR
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}ODM_PHY_INFO_T,*PODM_PHY_INFO_T;
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};
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typedef struct _ODM_Phy_Dbg_Info_
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{
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struct odm_phy_dbg_info {
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//ODM Write,debug info
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s1Byte RxSNRdB[MAX_PATH_NUM_92CS];
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u8Byte NumQryPhyStatus;
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@ -338,26 +329,22 @@ typedef struct _ODM_Phy_Dbg_Info_
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//Others
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s4Byte RxEVM[MAX_PATH_NUM_92CS];
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}ODM_PHY_DBG_INFO_T;
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};
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typedef struct _ODM_Per_Pkt_Info_
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{
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struct odm_per_pkt_info {
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s8 Rate;
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u8 StationID;
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bool bPacketMatchBSSID;
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bool bPacketToSelf;
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bool bPacketBeacon;
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}ODM_PACKET_INFO_T,*PODM_PACKET_INFO_T;
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};
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typedef struct _ODM_Mac_Status_Info_
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{
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struct odm_mac_status_info {
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u1Byte test;
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}ODM_MAC_INFO;
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};
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typedef enum tag_Dynamic_ODM_Support_Ability_Type
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{
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enum odm_ability {
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// BB Team
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ODM_DIG = 0x00000001,
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ODM_HIGH_POWER = 0x00000002,
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@ -371,13 +358,13 @@ typedef enum tag_Dynamic_ODM_Support_Ability_Type
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ODM_2TPATHDIV = 0x00000200,
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ODM_1TPATHDIV = 0x00000400,
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ODM_PSD2AFH = 0x00000800
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}ODM_Ability_E;
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};
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//
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// 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T
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// Please declare below ODM relative info in your STA info structure.
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//
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typedef struct _ODM_STA_INFO{
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struct odm_sta_info {
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// Driver Write
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bool bUsed; // record the sta status link or not?
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//u1Byte WirelessMode; //
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@ -396,13 +383,12 @@ typedef struct _ODM_STA_INFO{
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//
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// ODM Write Wilson will handle this part(said by Luke.Lee)
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}ODM_STA_INFO_T, *PODM_STA_INFO_T;
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};
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//
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// 2011/10/20 MH Define Common info enum for all team.
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//
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typedef enum _ODM_Common_Info_Definition
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{
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enum odm_common_info_def {
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//-------------REMOVED CASE-----------//
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//ODM_CMNINFO_CCK_HP,
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//ODM_CMNINFO_RFPATH_ENABLE, // Define as ODM write???
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@ -487,15 +473,12 @@ typedef enum _ODM_Common_Info_Definition
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ODM_CMNINFO_MAC_STATUS,
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ODM_CMNINFO_MAX,
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}ODM_CMNINFO_E;
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};
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//
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// 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY
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//
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typedef enum _ODM_Support_Ability_Definition
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{
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enum odm_ability_def {
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//
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// BB ODM section BIT 0-15
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//
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@ -526,20 +509,18 @@ typedef enum _ODM_Support_Ability_Definition
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ODM_RF_RX_GAIN_TRACK = BIT25,
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ODM_RF_CALIBRATION = BIT26,
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}ODM_ABILITY_E;
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};
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// ODM_CMNINFO_INTERFACE
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typedef enum tag_ODM_Support_Interface_Definition
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{
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enum odm_interface_def {
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ODM_ITRF_PCIE = 0x1,
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ODM_ITRF_USB = 0x2,
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ODM_ITRF_SDIO = 0x4,
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ODM_ITRF_ALL = 0x7,
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}ODM_INTERFACE_E;
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};
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// ODM_CMNINFO_IC_TYPE
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typedef enum tag_ODM_Support_IC_Type_Definition
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{
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enum odm_ic_type {
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ODM_RTL8192S = BIT0,
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ODM_RTL8192C = BIT1,
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ODM_RTL8192D = BIT2,
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@ -547,14 +528,13 @@ typedef enum tag_ODM_Support_IC_Type_Definition
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ODM_RTL8188E = BIT4,
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ODM_RTL8812 = BIT5,
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ODM_RTL8821 = BIT6,
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}ODM_IC_TYPE_E;
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};
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#define ODM_IC_11N_SERIES (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E)
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#define ODM_IC_11AC_SERIES (ODM_RTL8812)
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//ODM_CMNINFO_CUT_VER
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typedef enum tag_ODM_Cut_Version_Definition
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{
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enum odm_cut_version {
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ODM_CUT_A = 1,
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ODM_CUT_B = 2,
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ODM_CUT_C = 3,
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@ -562,21 +542,19 @@ typedef enum tag_ODM_Cut_Version_Definition
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ODM_CUT_E = 5,
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ODM_CUT_F = 6,
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ODM_CUT_TEST = 7,
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}ODM_CUT_VERSION_E;
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};
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// ODM_CMNINFO_FAB_VER
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typedef enum tag_ODM_Fab_Version_Definition
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{
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enum odm_fab_Version {
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ODM_TSMC = 0,
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ODM_UMC = 1,
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||||
}ODM_FAB_E;
|
||||
};
|
||||
|
||||
// ODM_CMNINFO_RF_TYPE
|
||||
//
|
||||
// For example 1T2R (A+AB = BIT0|BIT4|BIT5)
|
||||
//
|
||||
typedef enum tag_ODM_RF_Path_Bit_Definition
|
||||
{
|
||||
enum odm_rf_path {
|
||||
ODM_RF_TX_A = BIT0,
|
||||
ODM_RF_TX_B = BIT1,
|
||||
ODM_RF_TX_C = BIT2,
|
||||
|
|
@ -585,11 +563,9 @@ typedef enum tag_ODM_RF_Path_Bit_Definition
|
|||
ODM_RF_RX_B = BIT5,
|
||||
ODM_RF_RX_C = BIT6,
|
||||
ODM_RF_RX_D = BIT7,
|
||||
}ODM_RF_PATH_E;
|
||||
};
|
||||
|
||||
|
||||
typedef enum tag_ODM_RF_Type_Definition
|
||||
{
|
||||
enum odm_rf_type {
|
||||
ODM_1T1R = 0,
|
||||
ODM_1T2R = 1,
|
||||
ODM_2T2R = 2,
|
||||
|
|
@ -598,32 +574,25 @@ typedef enum tag_ODM_RF_Type_Definition
|
|||
ODM_3T3R = 5,
|
||||
ODM_3T4R = 6,
|
||||
ODM_4T4R = 7,
|
||||
}ODM_RF_TYPE_E;
|
||||
};
|
||||
|
||||
|
||||
//
|
||||
// ODM Dynamic common info value definition
|
||||
//
|
||||
|
||||
typedef enum tag_ODM_MAC_PHY_Mode_Definition
|
||||
{
|
||||
enum odm_mac_phy_mode {
|
||||
ODM_SMSP = 0,
|
||||
ODM_DMSP = 1,
|
||||
ODM_DMDP = 2,
|
||||
}ODM_MAC_PHY_MODE_E;
|
||||
};
|
||||
|
||||
|
||||
typedef enum tag_BT_Coexist_Definition
|
||||
{
|
||||
enum odm_bt_coexist {
|
||||
ODM_BT_BUSY = 1,
|
||||
ODM_BT_ON = 2,
|
||||
ODM_BT_OFF = 3,
|
||||
ODM_BT_NONE = 4,
|
||||
}ODM_BT_COEXIST_E;
|
||||
};
|
||||
|
||||
// ODM_CMNINFO_OP_MODE
|
||||
typedef enum tag_Operation_Mode_Definition
|
||||
{
|
||||
enum odm_operation_mode {
|
||||
ODM_NO_LINK = BIT0,
|
||||
ODM_LINK = BIT1,
|
||||
ODM_SCAN = BIT2,
|
||||
|
|
@ -633,40 +602,35 @@ typedef enum tag_Operation_Mode_Definition
|
|||
ODM_AD_HOC = BIT6,
|
||||
ODM_WIFI_DIRECT = BIT7,
|
||||
ODM_WIFI_DISPLAY = BIT8,
|
||||
}ODM_OPERATION_MODE_E;
|
||||
};
|
||||
|
||||
// ODM_CMNINFO_WM_MODE
|
||||
typedef enum tag_Wireless_Mode_Definition
|
||||
{
|
||||
enum odm_wireless_mode {
|
||||
ODM_WM_UNKNOW = 0x0,
|
||||
ODM_WM_B = BIT0,
|
||||
ODM_WM_G = BIT1,
|
||||
ODM_WM_A = BIT2,
|
||||
ODM_WM_N24G = BIT3,
|
||||
ODM_WM_N5G = BIT4,
|
||||
ODM_WM_AUTO = BIT5,
|
||||
ODM_WM_AC = BIT6,
|
||||
}ODM_WIRELESS_MODE_E;
|
||||
ODM_WM_B = BIT0,
|
||||
ODM_WM_G = BIT1,
|
||||
ODM_WM_A = BIT2,
|
||||
ODM_WM_N24G = BIT3,
|
||||
ODM_WM_N5G = BIT4,
|
||||
ODM_WM_AUTO = BIT5,
|
||||
ODM_WM_AC = BIT6,
|
||||
};
|
||||
|
||||
// ODM_CMNINFO_BAND
|
||||
typedef enum tag_Band_Type_Definition
|
||||
{
|
||||
enum odm_band_type {
|
||||
ODM_BAND_2_4G = BIT0,
|
||||
ODM_BAND_5G = BIT1,
|
||||
|
||||
}ODM_BAND_TYPE_E;
|
||||
};
|
||||
|
||||
// ODM_CMNINFO_SEC_CHNL_OFFSET
|
||||
typedef enum tag_Secondary_Channel_Offset_Definition
|
||||
{
|
||||
enum odm_sec_chnl_offset {
|
||||
ODM_DONT_CARE = 0,
|
||||
ODM_BELOW = 1,
|
||||
ODM_ABOVE = 2
|
||||
}ODM_SEC_CHNL_OFFSET_E;
|
||||
};
|
||||
|
||||
// ODM_CMNINFO_SEC_MODE
|
||||
typedef enum tag_Security_Definition
|
||||
{
|
||||
enum odm_security {
|
||||
ODM_SEC_OPEN = 0,
|
||||
ODM_SEC_WEP40 = 1,
|
||||
ODM_SEC_TKIP = 2,
|
||||
|
|
@ -675,42 +639,34 @@ typedef enum tag_Security_Definition
|
|||
ODM_SEC_WEP104 = 5,
|
||||
ODM_WEP_WPA_MIXED = 6, // WEP + WPA
|
||||
ODM_SEC_SMS4 = 7,
|
||||
}ODM_SECURITY_E;
|
||||
};
|
||||
|
||||
// ODM_CMNINFO_BW
|
||||
typedef enum tag_Bandwidth_Definition
|
||||
{
|
||||
enum odm_bw {
|
||||
ODM_BW20M = 0,
|
||||
ODM_BW40M = 1,
|
||||
ODM_BW80M = 2,
|
||||
ODM_BW160M = 3,
|
||||
ODM_BW10M = 4,
|
||||
}ODM_BW_E;
|
||||
|
||||
// ODM_CMNINFO_CHNL
|
||||
};
|
||||
|
||||
// ODM_CMNINFO_BOARD_TYPE
|
||||
typedef enum tag_Board_Definition
|
||||
{
|
||||
enum odm_board_type {
|
||||
ODM_BOARD_NORMAL = 0,
|
||||
ODM_BOARD_HIGHPWR = 1,
|
||||
ODM_BOARD_MINICARD = 2,
|
||||
ODM_BOARD_SLIM = 3,
|
||||
ODM_BOARD_COMBO = 4,
|
||||
|
||||
}ODM_BOARD_TYPE_E;
|
||||
};
|
||||
|
||||
// ODM_CMNINFO_ONE_PATH_CCA
|
||||
typedef enum tag_CCA_Path
|
||||
{
|
||||
enum odm_cca_path {
|
||||
ODM_CCA_2R = 0,
|
||||
ODM_CCA_1R_A = 1,
|
||||
ODM_CCA_1R_B = 2,
|
||||
}ODM_CCA_PATH_E;
|
||||
};
|
||||
|
||||
|
||||
typedef struct _ODM_RA_Info_
|
||||
{
|
||||
struct odm_ra_info {
|
||||
u1Byte RateID;
|
||||
u4Byte RateMask;
|
||||
u4Byte RAUseRate;
|
||||
|
|
@ -740,15 +696,14 @@ typedef struct _ODM_RA_Info_
|
|||
u1Byte PTModeSS; // decide whitch rate should do PT
|
||||
u1Byte RAstage; // StageRA, decide how many times RA will be done between PT
|
||||
u1Byte PTSmoothFactor;
|
||||
} ODM_RA_INFO_T,*PODM_RA_INFO_T;
|
||||
};
|
||||
|
||||
typedef struct _IQK_MATRIX_REGS_SETTING{
|
||||
struct ijk_matrix_regs_set {
|
||||
bool bIQKDone;
|
||||
s4Byte Value[1][IQK_Matrix_REG_NUM];
|
||||
}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING;
|
||||
};
|
||||
|
||||
typedef struct ODM_RF_Calibration_Structure
|
||||
{
|
||||
struct odm_rf_cal {
|
||||
//for tx power tracking
|
||||
|
||||
u4Byte RegA24; // for TempCCK
|
||||
|
|
@ -790,7 +745,7 @@ typedef struct ODM_RF_Calibration_Structure
|
|||
|
||||
u1Byte ThermalValue_HP[HP_THERMAL_NUM];
|
||||
u1Byte ThermalValue_HP_index;
|
||||
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
|
||||
struct ijk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
|
||||
|
||||
u1Byte Delta_IQK;
|
||||
u1Byte Delta_LCK;
|
||||
|
|
@ -820,13 +775,11 @@ typedef struct ODM_RF_Calibration_Structure
|
|||
u1Byte bDPdone;
|
||||
u1Byte bDPPathAOK;
|
||||
u1Byte bDPPathBOK;
|
||||
}ODM_RF_CAL_T,*PODM_RF_CAL_T;
|
||||
//
|
||||
// ODM Dynamic common info value definition
|
||||
//
|
||||
};
|
||||
|
||||
typedef struct _FAST_ANTENNA_TRAINNING_
|
||||
{
|
||||
// ODM Dynamic common info value definition
|
||||
|
||||
struct fast_ant_train {
|
||||
u1Byte Bssid[6];
|
||||
u1Byte antsel_rx_keep_0;
|
||||
u1Byte antsel_rx_keep_1;
|
||||
|
|
@ -845,68 +798,43 @@ typedef struct _FAST_ANTENNA_TRAINNING_
|
|||
u4Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u1Byte RxIdleAnt;
|
||||
bool bBecomeLinked;
|
||||
};
|
||||
|
||||
}FAT_T,*pFAT_T;
|
||||
|
||||
typedef enum _FAT_STATE
|
||||
{
|
||||
FAT_NORMAL_STATE = 0,
|
||||
enum fat_state {
|
||||
FAT_NORMAL_STATE = 0,
|
||||
FAT_TRAINING_STATE = 1,
|
||||
}FAT_STATE_E, *PFAT_STATE_E;
|
||||
};
|
||||
|
||||
typedef enum _ANT_DIV_TYPE
|
||||
{
|
||||
NO_ANTDIV = 0xFF,
|
||||
CG_TRX_HW_ANTDIV = 0x01,
|
||||
enum ant_div_type {
|
||||
NO_ANTDIV = 0xFF,
|
||||
CG_TRX_HW_ANTDIV = 0x01,
|
||||
CGCS_RX_HW_ANTDIV = 0x02,
|
||||
FIXED_HW_ANTDIV = 0x03,
|
||||
FIXED_HW_ANTDIV = 0x03,
|
||||
CG_TRX_SMART_ANTDIV = 0x04,
|
||||
CGCS_RX_SW_ANTDIV = 0x05,
|
||||
};
|
||||
|
||||
}ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//
|
||||
// 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration.
|
||||
//
|
||||
typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
|
||||
{
|
||||
//RT_TIMER FastAntTrainingTimer;
|
||||
//
|
||||
struct odm_dm_struct {
|
||||
// Add for different team use temporarily
|
||||
//
|
||||
PADAPTER Adapter; // For CE/NIC team
|
||||
prtl8192cd_priv priv; // For AP/ADSL team
|
||||
struct rtl8192cd_priv *priv; // For AP/ADSL team
|
||||
// WHen you use Adapter or priv pointer, you must make sure the pointer is ready.
|
||||
bool odm_ready;
|
||||
|
||||
rtl8192cd_priv fake_priv;
|
||||
struct rtl8192cd_priv *fake_priv;
|
||||
u8Byte DebugComponents;
|
||||
u4Byte DebugLevel;
|
||||
|
||||
//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//
|
||||
//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------
|
||||
bool bCckHighPower;
|
||||
u1Byte RFPathRxEnable; // ODM_CMNINFO_RFPATH_ENABLE
|
||||
u1Byte ControlChannel;
|
||||
//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//
|
||||
//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------
|
||||
|
||||
//1 COMMON INFORMATION
|
||||
|
||||
//
|
||||
// Init Value
|
||||
//
|
||||
//-----------HOOK BEFORE REG INIT-----------//
|
||||
//-----------HOOK BEFORE REG INIT-----------
|
||||
// ODM Platform info AP/ADSL/CE/MP = 1/2/3/4
|
||||
u1Byte SupportPlatform;
|
||||
// ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K
|
||||
|
|
@ -936,12 +864,12 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
|
|||
bool bDualMacSmartConcurrent;
|
||||
u4Byte BK_SupportAbility;
|
||||
u1Byte AntDivType;
|
||||
//-----------HOOK BEFORE REG INIT-----------//
|
||||
//-----------HOOK BEFORE REG INIT-----------
|
||||
|
||||
//
|
||||
// Dynamic Value
|
||||
//
|
||||
//--------- POINTER REFERENCE-----------//
|
||||
//--------- POINTER REFERENCE-----------
|
||||
|
||||
u1Byte u1Byte_temp;
|
||||
bool bool_temp;
|
||||
|
|
@ -978,9 +906,9 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
|
|||
//pMgntInfo->AntennaTest
|
||||
u1Byte *pAntennaTest;
|
||||
bool *pbNet_closed;
|
||||
//--------- POINTER REFERENCE-----------//
|
||||
//--------- POINTER REFERENCE-----------
|
||||
//
|
||||
//------------CALL BY VALUE-------------//
|
||||
//------------CALL BY VALUE-------------
|
||||
bool bWIFI_Direct;
|
||||
bool bWIFI_Display;
|
||||
bool bLinked;
|
||||
|
|
@ -994,7 +922,7 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
|
|||
u1Byte btHsDigVal; // use BT rssi to decide the DIG value
|
||||
bool bBtDisableEdcaTurbo; // Under some condition, don't enable the EDCA Turbo
|
||||
bool bBtBusy; // BT is busy.
|
||||
//------------CALL BY VALUE-------------//
|
||||
//------------CALL BY VALUE-------------
|
||||
|
||||
//2 Define STA info.
|
||||
// _ODM_STA_INFO
|
||||
|
|
@ -1003,7 +931,7 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
|
|||
|
||||
#if (RATE_ADAPTIVE_SUPPORT == 1)
|
||||
u2Byte CurrminRptTime;
|
||||
ODM_RA_INFO_T RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119
|
||||
struct odm_ra_info RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119
|
||||
#endif
|
||||
//
|
||||
// 2012/02/14 MH Add to share 88E ra with other SW team.
|
||||
|
|
@ -1014,34 +942,25 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
|
|||
// Define ...........
|
||||
|
||||
// Latest packet phy info (ODM write)
|
||||
ODM_PHY_DBG_INFO_T PhyDbgInfo;
|
||||
//PHY_INFO_88E PhyInfo;
|
||||
struct odm_phy_dbg_info PhyDbgInfo;
|
||||
|
||||
// Latest packet phy info (ODM write)
|
||||
ODM_MAC_INFO *pMacInfo;
|
||||
//MAC_INFO_88E MacInfo;
|
||||
struct odm_mac_status_info *pMacInfo;
|
||||
|
||||
// Different Team independt structure??
|
||||
|
||||
//
|
||||
//TX_RTP_CMN TX_retrpo;
|
||||
//TX_RTP_88E TX_retrpo;
|
||||
//TX_RTP_8195 TX_retrpo;
|
||||
|
||||
//
|
||||
//ODM Structure
|
||||
//
|
||||
FAT_T DM_FatTable;
|
||||
DIG_T DM_DigTable;
|
||||
PS_T DM_PSTable;
|
||||
Pri_CCA_T DM_PriCCA;
|
||||
RXHP_T DM_RXHP_Table;
|
||||
false_ALARM_STATISTICS FalseAlmCnt;
|
||||
false_ALARM_STATISTICS FlaseAlmCntBuddyAdapter;
|
||||
SWAT_T DM_SWAT_Table;
|
||||
struct fast_ant_train DM_FatTable;
|
||||
struct rtw_dig DM_DigTable;
|
||||
struct rtl_ps DM_PSTable;
|
||||
struct dyn_primary_cca DM_PriCCA;
|
||||
struct rx_hpc DM_RXHP_Table;
|
||||
struct false_alarm_stats FalseAlmCnt;
|
||||
struct false_alarm_stats FlaseAlmCntBuddyAdapter;
|
||||
struct sw_ant_switch DM_SWAT_Table;
|
||||
bool RSSI_test;
|
||||
|
||||
EDCA_T DM_EDCA_Table;
|
||||
struct edca_turbo DM_EDCA_Table;
|
||||
u4Byte WMMEDCA_BE;
|
||||
// Copy from SD4 structure
|
||||
//
|
||||
|
|
@ -1062,10 +981,10 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
|
|||
//for rate adaptive, in fact, 88c/92c fw will handle this
|
||||
u1Byte bUseRAMask;
|
||||
|
||||
ODM_RATE_ADAPTIVE RateAdaptive;
|
||||
struct odm_rate_adapt RateAdaptive;
|
||||
|
||||
|
||||
ODM_RF_CAL_T RFCalibrateInfo;
|
||||
struct odm_rf_cal RFCalibrateInfo;
|
||||
|
||||
//
|
||||
// TX power tracking
|
||||
|
|
@ -1088,34 +1007,34 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
|
|||
//2011.09.27 add for Path Diversity
|
||||
RT_TIMER CCKPathDiversityTimer;
|
||||
RT_TIMER FastAntTrainingTimer;
|
||||
} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure
|
||||
}; // DM_Dynamic_Mechanism_Structure
|
||||
|
||||
#define ODM_RF_PATH_MAX 2
|
||||
|
||||
typedef enum _ODM_RF_RADIO_PATH {
|
||||
enum ODM_RF_RADIO_PATH {
|
||||
ODM_RF_PATH_A = 0, //Radio Path A
|
||||
ODM_RF_PATH_B = 1, //Radio Path B
|
||||
ODM_RF_PATH_C = 2, //Radio Path C
|
||||
ODM_RF_PATH_D = 3, //Radio Path D
|
||||
} ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E;
|
||||
};
|
||||
|
||||
typedef enum _ODM_RF_CONTENT{
|
||||
enum ODM_RF_CONTENT {
|
||||
odm_radioa_txt = 0x1000,
|
||||
odm_radiob_txt = 0x1001,
|
||||
odm_radioc_txt = 0x1002,
|
||||
odm_radiod_txt = 0x1003
|
||||
} ODM_RF_CONTENT;
|
||||
};
|
||||
|
||||
typedef enum _ODM_BB_Config_Type{
|
||||
enum odm_bb_config_type {
|
||||
CONFIG_BB_PHY_REG,
|
||||
CONFIG_BB_AGC_TAB,
|
||||
CONFIG_BB_AGC_TAB_2G,
|
||||
CONFIG_BB_AGC_TAB_5G,
|
||||
CONFIG_BB_PHY_REG_PG,
|
||||
} ODM_BB_Config_Type, *PODM_BB_Config_Type;
|
||||
};
|
||||
|
||||
// Status code
|
||||
typedef enum _RT_STATUS{
|
||||
enum rt_status {
|
||||
RT_STATUS_SUCCESS,
|
||||
RT_STATUS_FAILURE,
|
||||
RT_STATUS_PENDING,
|
||||
|
|
@ -1124,23 +1043,22 @@ typedef enum _RT_STATUS{
|
|||
RT_STATUS_INVALID_PARAMETER,
|
||||
RT_STATUS_NOT_SUPPORT,
|
||||
RT_STATUS_OS_API_FAILED,
|
||||
}RT_STATUS,*PRT_STATUS;
|
||||
};
|
||||
|
||||
//3===========================================================
|
||||
//3 DIG
|
||||
//3===========================================================
|
||||
|
||||
typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition
|
||||
{
|
||||
DIG_TYPE_THRESH_HIGH = 0,
|
||||
DIG_TYPE_THRESH_LOW = 1,
|
||||
DIG_TYPE_BACKOFF = 2,
|
||||
DIG_TYPE_RX_GAIN_MIN = 3,
|
||||
DIG_TYPE_RX_GAIN_MAX = 4,
|
||||
DIG_TYPE_ENABLE = 5,
|
||||
DIG_TYPE_DISABLE = 6,
|
||||
enum dm_dig_op {
|
||||
RT_TYPE_THRESH_HIGH = 0,
|
||||
RT_TYPE_THRESH_LOW = 1,
|
||||
RT_TYPE_BACKOFF = 2,
|
||||
RT_TYPE_RX_GAIN_MIN = 3,
|
||||
RT_TYPE_RX_GAIN_MAX = 4,
|
||||
RT_TYPE_ENABLE = 5,
|
||||
RT_TYPE_DISABLE = 6,
|
||||
DIG_OP_TYPE_MAX
|
||||
}DM_DIG_OP_E;
|
||||
};
|
||||
|
||||
#define DM_DIG_THRESH_HIGH 40
|
||||
#define DM_DIG_THRESH_LOW 35
|
||||
|
|
@ -1226,29 +1144,26 @@ typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition
|
|||
//3===========================================================
|
||||
|
||||
|
||||
typedef enum tag_1R_CCA_Type_Definition
|
||||
{
|
||||
enum dm_1r_cca {
|
||||
CCA_1R =0,
|
||||
CCA_2R = 1,
|
||||
CCA_MAX = 2,
|
||||
}DM_1R_CCA_E;
|
||||
};
|
||||
|
||||
typedef enum tag_RF_Type_Definition
|
||||
{
|
||||
enum dm_rf {
|
||||
RF_Save =0,
|
||||
RF_Normal = 1,
|
||||
RF_MAX = 2,
|
||||
}DM_RF_E;
|
||||
};
|
||||
|
||||
//3===========================================================
|
||||
//3 Antenna Diversity
|
||||
//3===========================================================
|
||||
typedef enum tag_SW_Antenna_Switch_Definition
|
||||
{
|
||||
enum dm_swas {
|
||||
Antenna_A = 1,
|
||||
Antenna_B = 2,
|
||||
Antenna_MAX = 3,
|
||||
}DM_SWAS_E;
|
||||
};
|
||||
|
||||
|
||||
// Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28.
|
||||
|
|
@ -1279,117 +1194,117 @@ extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
|
|||
#define SWAW_STEP_PEAK 0
|
||||
#define SWAW_STEP_DETERMINE 1
|
||||
|
||||
void ODM_Write_DIG( PDM_ODM_T pDM_Odm, u1Byte CurrentIGI);
|
||||
void ODM_Write_CCK_CCA_Thres( PDM_ODM_T pDM_Odm, u1Byte CurCCK_CCAThres);
|
||||
void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u1Byte CurrentIGI);
|
||||
void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u1Byte CurCCK_CCAThres);
|
||||
|
||||
void
|
||||
ODM_SetAntenna(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
struct odm_dm_struct *pDM_Odm,
|
||||
u1Byte Antenna);
|
||||
|
||||
|
||||
#define dm_RF_Saving ODM_RF_Saving
|
||||
void ODM_RF_Saving( PDM_ODM_T pDM_Odm,
|
||||
void ODM_RF_Saving( struct odm_dm_struct *pDM_Odm,
|
||||
u1Byte bForceInNormal );
|
||||
|
||||
#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink
|
||||
void ODM_SwAntDivRestAfterLink( PDM_ODM_T pDM_Odm);
|
||||
void ODM_SwAntDivRestAfterLink( struct odm_dm_struct *pDM_Odm);
|
||||
|
||||
#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
|
||||
void
|
||||
ODM_TXPowerTrackingCheck(
|
||||
PDM_ODM_T pDM_Odm
|
||||
struct odm_dm_struct *pDM_Odm
|
||||
);
|
||||
|
||||
bool
|
||||
ODM_RAStateCheck(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
struct odm_dm_struct *pDM_Odm,
|
||||
s4Byte RSSI,
|
||||
bool bForceUpdate,
|
||||
pu1Byte pRATRState
|
||||
);
|
||||
|
||||
#define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi
|
||||
void ODM_SwAntDivChkPerPktRssi(PDM_ODM_T pDM_Odm, u1Byte StationID, PODM_PHY_INFO_T pPhyInfo);
|
||||
void ODM_SwAntDivChkPerPktRssi(struct odm_dm_struct *pDM_Odm, u1Byte StationID, struct odm_phy_status_info *pPhyInfo);
|
||||
|
||||
u4Byte ConvertTo_dB(u4Byte Value);
|
||||
|
||||
u4Byte
|
||||
GetPSDData(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
struct odm_dm_struct *pDM_Odm,
|
||||
unsigned int point,
|
||||
u1Byte initial_gain_psd);
|
||||
|
||||
void
|
||||
odm_DIGbyRSSI_LPS(
|
||||
PDM_ODM_T pDM_Odm
|
||||
struct odm_dm_struct *pDM_Odm
|
||||
);
|
||||
|
||||
u4Byte ODM_Get_Rate_Bitmap(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
struct odm_dm_struct *pDM_Odm,
|
||||
u4Byte macid,
|
||||
u4Byte ra_mask,
|
||||
u1Byte rssi_level);
|
||||
|
||||
void ODM_DMInit( PDM_ODM_T pDM_Odm);
|
||||
void ODM_DMInit( struct odm_dm_struct *pDM_Odm);
|
||||
|
||||
void
|
||||
ODM_DMWatchdog(
|
||||
PDM_ODM_T pDM_Odm // For common use in the future
|
||||
struct odm_dm_struct *pDM_Odm // For common use in the future
|
||||
);
|
||||
|
||||
void
|
||||
ODM_CmnInfoInit(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
ODM_CMNINFO_E CmnInfo,
|
||||
struct odm_dm_struct *pDM_Odm,
|
||||
enum odm_common_info_def CmnInfo,
|
||||
u4Byte Value
|
||||
);
|
||||
|
||||
void
|
||||
ODM_CmnInfoHook(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
ODM_CMNINFO_E CmnInfo,
|
||||
struct odm_dm_struct *pDM_Odm,
|
||||
enum odm_common_info_def CmnInfo,
|
||||
void * pValue
|
||||
);
|
||||
|
||||
void
|
||||
ODM_CmnInfoPtrArrayHook(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
ODM_CMNINFO_E CmnInfo,
|
||||
struct odm_dm_struct *pDM_Odm,
|
||||
enum odm_common_info_def CmnInfo,
|
||||
u2Byte Index,
|
||||
void * pValue
|
||||
);
|
||||
|
||||
void
|
||||
ODM_CmnInfoUpdate(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
struct odm_dm_struct *pDM_Odm,
|
||||
u4Byte CmnInfo,
|
||||
u8Byte Value
|
||||
);
|
||||
|
||||
void
|
||||
ODM_InitAllTimers(
|
||||
PDM_ODM_T pDM_Odm
|
||||
struct odm_dm_struct *pDM_Odm
|
||||
);
|
||||
|
||||
void
|
||||
ODM_CancelAllTimers(
|
||||
PDM_ODM_T pDM_Odm
|
||||
struct odm_dm_struct *pDM_Odm
|
||||
);
|
||||
|
||||
void
|
||||
ODM_ReleaseAllTimers(
|
||||
PDM_ODM_T pDM_Odm
|
||||
struct odm_dm_struct *pDM_Odm
|
||||
);
|
||||
|
||||
void
|
||||
ODM_ResetIQKResult(
|
||||
PDM_ODM_T pDM_Odm
|
||||
struct odm_dm_struct *pDM_Odm
|
||||
);
|
||||
|
||||
void
|
||||
ODM_AntselStatistics_88C(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
struct odm_dm_struct *pDM_Odm,
|
||||
u1Byte MacId,
|
||||
u4Byte PWDBAll,
|
||||
bool isCCKrate
|
||||
|
|
@ -1397,15 +1312,15 @@ ODM_AntselStatistics_88C(
|
|||
|
||||
void
|
||||
ODM_SingleDualAntennaDefaultSetting(
|
||||
PDM_ODM_T pDM_Odm
|
||||
struct odm_dm_struct *pDM_Odm
|
||||
);
|
||||
|
||||
bool
|
||||
ODM_SingleDualAntennaDetection(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
struct odm_dm_struct *pDM_Odm,
|
||||
u1Byte mode
|
||||
);
|
||||
|
||||
void odm_dtc(PDM_ODM_T pDM_Odm);
|
||||
void odm_dtc(struct odm_dm_struct *pDM_Odm);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -150,20 +150,20 @@ typedef struct _Phy_Status_Rpt_8195
|
|||
|
||||
void
|
||||
odm_Init_RSSIForDM(
|
||||
PDM_ODM_T pDM_Odm
|
||||
struct odm_dm_struct *pDM_Odm
|
||||
);
|
||||
|
||||
void
|
||||
ODM_PhyStatusQuery(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
PODM_PHY_INFO_T pPhyInfo,
|
||||
struct odm_dm_struct * pDM_Odm,
|
||||
struct odm_phy_status_info *pPhyInfo,
|
||||
pu1Byte pPhyStatus,
|
||||
PODM_PACKET_INFO_T pPktinfo
|
||||
struct odm_per_pkt_info *pPktinfo
|
||||
);
|
||||
|
||||
void
|
||||
ODM_MacStatusQuery(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
struct odm_dm_struct * pDM_Odm,
|
||||
pu1Byte pMacStatus,
|
||||
u1Byte MacID,
|
||||
bool bPacketMatchBSSID,
|
||||
|
|
@ -173,20 +173,20 @@ ODM_MacStatusQuery(
|
|||
|
||||
HAL_STATUS
|
||||
ODM_ConfigRFWithHeaderFile(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
ODM_RF_RADIO_PATH_E Content,
|
||||
ODM_RF_RADIO_PATH_E eRFPath
|
||||
struct odm_dm_struct * pDM_Odm,
|
||||
enum ODM_RF_RADIO_PATH Content,
|
||||
enum ODM_RF_RADIO_PATH eRFPath
|
||||
);
|
||||
|
||||
HAL_STATUS
|
||||
ODM_ConfigBBWithHeaderFile(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
ODM_BB_Config_Type ConfigType
|
||||
struct odm_dm_struct * pDM_Odm,
|
||||
enum odm_bb_config_type ConfigType
|
||||
);
|
||||
|
||||
HAL_STATUS
|
||||
ODM_ConfigMACWithHeaderFile(
|
||||
PDM_ODM_T pDM_Odm
|
||||
struct odm_dm_struct *pDM_Odm
|
||||
);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -27,20 +27,20 @@
|
|||
#define MAIN_ANT_CGCS_RX 0
|
||||
#define AUX_ANT_CGCS_RX 1
|
||||
|
||||
void ODM_DIG_LowerBound_88E(PDM_ODM_T pDM_Odm);
|
||||
void ODM_DIG_LowerBound_88E(struct odm_dm_struct *pDM_Odm);
|
||||
|
||||
void ODM_AntennaDiversityInit_88E(PDM_ODM_T pDM_Odm);
|
||||
void ODM_AntennaDiversityInit_88E(struct odm_dm_struct *pDM_Odm);
|
||||
|
||||
void ODM_AntennaDiversity_88E(PDM_ODM_T pDM_Odm);
|
||||
void ODM_AntennaDiversity_88E(struct odm_dm_struct *pDM_Odm);
|
||||
|
||||
void ODM_SetTxAntByTxInfo_88E(PDM_ODM_T pDM_Odm,
|
||||
void ODM_SetTxAntByTxInfo_88E(struct odm_dm_struct *pDM_Odm,
|
||||
pu1Byte pDesc,
|
||||
u1Byte macId
|
||||
);
|
||||
|
||||
void ODM_UpdateRxIdleAnt_88E(PDM_ODM_T pDM_Odm, u1Byte Ant);
|
||||
void ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *pDM_Odm, u1Byte Ant);
|
||||
|
||||
void ODM_AntselStatistics_88E(PDM_ODM_T pDM_Odm,
|
||||
void ODM_AntselStatistics_88E(struct odm_dm_struct *pDM_Odm,
|
||||
u1Byte antsel_tr_mux,
|
||||
u4Byte MacId,
|
||||
u1Byte RxPWDBAll
|
||||
|
|
@ -48,29 +48,29 @@ void ODM_AntselStatistics_88E(PDM_ODM_T pDM_Odm,
|
|||
|
||||
void
|
||||
odm_FastAntTraining(
|
||||
PDM_ODM_T pDM_Odm
|
||||
struct odm_dm_struct *pDM_Odm
|
||||
);
|
||||
|
||||
void
|
||||
odm_FastAntTrainingCallback(
|
||||
PDM_ODM_T pDM_Odm
|
||||
struct odm_dm_struct *pDM_Odm
|
||||
);
|
||||
|
||||
void
|
||||
odm_FastAntTrainingWorkItemCallback(
|
||||
PDM_ODM_T pDM_Odm
|
||||
struct odm_dm_struct *pDM_Odm
|
||||
);
|
||||
|
||||
void
|
||||
odm_PrimaryCCA_Init(
|
||||
PDM_ODM_T pDM_Odm);
|
||||
struct odm_dm_struct *pDM_Odm);
|
||||
|
||||
bool
|
||||
ODM_DynamicPrimaryCCA_DupRTS(
|
||||
PDM_ODM_T pDM_Odm);
|
||||
struct odm_dm_struct *pDM_Odm);
|
||||
|
||||
void
|
||||
odm_DynamicPrimaryCCA(
|
||||
PDM_ODM_T pDM_Odm);
|
||||
struct odm_dm_struct *pDM_Odm);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -22,39 +22,33 @@
|
|||
|
||||
#if (RTL8188E_SUPPORT == 1)
|
||||
|
||||
void
|
||||
odm_ConfigRFReg_8188E(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
u4Byte Addr,
|
||||
u4Byte Data,
|
||||
ODM_RF_RADIO_PATH_E RF_PATH,
|
||||
u4Byte RegAddr
|
||||
);
|
||||
void odm_ConfigRFReg_8188E(struct odm_dm_struct *pDM_Odm, u4Byte Addr, u4Byte Data,
|
||||
enum ODM_RF_RADIO_PATH RF_PATH, u4Byte RegAddr);
|
||||
|
||||
void
|
||||
odm_ConfigRF_RadioA_8188E(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
struct odm_dm_struct *pDM_Odm,
|
||||
u4Byte Addr,
|
||||
u4Byte Data
|
||||
);
|
||||
|
||||
void
|
||||
odm_ConfigRF_RadioB_8188E(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
struct odm_dm_struct *pDM_Odm,
|
||||
u4Byte Addr,
|
||||
u4Byte Data
|
||||
);
|
||||
|
||||
void
|
||||
odm_ConfigMAC_8188E(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
struct odm_dm_struct *pDM_Odm,
|
||||
u4Byte Addr,
|
||||
u1Byte Data
|
||||
);
|
||||
|
||||
void
|
||||
odm_ConfigBB_AGC_8188E(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
struct odm_dm_struct *pDM_Odm,
|
||||
u4Byte Addr,
|
||||
u4Byte Bitmask,
|
||||
u4Byte Data
|
||||
|
|
@ -62,7 +56,7 @@ odm_ConfigBB_AGC_8188E(
|
|||
|
||||
void
|
||||
odm_ConfigBB_PHY_REG_PG_8188E(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
struct odm_dm_struct *pDM_Odm,
|
||||
u4Byte Addr,
|
||||
u4Byte Bitmask,
|
||||
u4Byte Data
|
||||
|
|
@ -70,7 +64,7 @@ odm_ConfigBB_PHY_REG_PG_8188E(
|
|||
|
||||
void
|
||||
odm_ConfigBB_PHY_8188E(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
struct odm_dm_struct *pDM_Odm,
|
||||
u4Byte Addr,
|
||||
u4Byte Bitmask,
|
||||
u4Byte Data
|
||||
|
|
|
|||
|
|
@ -161,6 +161,6 @@
|
|||
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr)
|
||||
#endif
|
||||
|
||||
void ODM_InitDebugSetting(PDM_ODM_T pDM_Odm);
|
||||
void ODM_InitDebugSetting(struct odm_dm_struct *pDM_Odm);
|
||||
|
||||
#endif // __ODM_DBG_H__
|
||||
|
|
|
|||
|
|
@ -83,49 +83,49 @@ typedef void (*RT_WORKITEM_CALL_BACK)(void * pContext);
|
|||
// =========== EXtern Function Prototype
|
||||
//
|
||||
|
||||
u1Byte ODM_Read1Byte(PDM_ODM_T pDM_Odm, u4Byte RegAddr);
|
||||
u1Byte ODM_Read1Byte(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr);
|
||||
|
||||
u2Byte ODM_Read2Byte(PDM_ODM_T pDM_Odm, u4Byte RegAddr);
|
||||
u2Byte ODM_Read2Byte(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr);
|
||||
|
||||
u4Byte ODM_Read4Byte(PDM_ODM_T pDM_Odm, u4Byte RegAddr);
|
||||
u4Byte ODM_Read4Byte(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr);
|
||||
|
||||
void ODM_Write1Byte(PDM_ODM_T pDM_Odm, u4Byte RegAddr, u1Byte Data);
|
||||
void ODM_Write1Byte(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr, u1Byte Data);
|
||||
|
||||
void ODM_Write2Byte(PDM_ODM_T pDM_Odm, u4Byte RegAddr, u2Byte Data);
|
||||
void ODM_Write2Byte(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr, u2Byte Data);
|
||||
|
||||
void ODM_Write4Byte(PDM_ODM_T pDM_Odm, u4Byte RegAddr, u4Byte Data);
|
||||
void ODM_Write4Byte(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr, u4Byte Data);
|
||||
|
||||
void ODM_SetMACReg(PDM_ODM_T pDM_Odm, u4Byte RegAddr, u4Byte BitMask, u4Byte Data);
|
||||
void ODM_SetMACReg(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr, u4Byte BitMask, u4Byte Data);
|
||||
|
||||
u4Byte ODM_GetMACReg(PDM_ODM_T pDM_Odm, u4Byte RegAddr, u4Byte BitMask);
|
||||
u4Byte ODM_GetMACReg(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr, u4Byte BitMask);
|
||||
|
||||
void ODM_SetBBReg(PDM_ODM_T pDM_Odm, u4Byte RegAddr, u4Byte BitMask, u4Byte Data);
|
||||
void ODM_SetBBReg(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr, u4Byte BitMask, u4Byte Data);
|
||||
|
||||
u4Byte ODM_GetBBReg(PDM_ODM_T pDM_Odm, u4Byte RegAddr, u4Byte BitMask);
|
||||
u4Byte ODM_GetBBReg(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr, u4Byte BitMask);
|
||||
|
||||
void ODM_SetRFReg(PDM_ODM_T pDM_Odm, ODM_RF_RADIO_PATH_E eRFPath, u4Byte RegAddr, u4Byte BitMask, u4Byte Data);
|
||||
void ODM_SetRFReg(struct odm_dm_struct *pDM_Odm, enum ODM_RF_RADIO_PATH eRFPath, u4Byte RegAddr, u4Byte BitMask, u4Byte Data);
|
||||
|
||||
u4Byte ODM_GetRFReg(PDM_ODM_T pDM_Odm, ODM_RF_RADIO_PATH_E eRFPath, u4Byte RegAddr, u4Byte BitMask);
|
||||
u4Byte ODM_GetRFReg(struct odm_dm_struct *pDM_Odm, enum ODM_RF_RADIO_PATH eRFPath, u4Byte RegAddr, u4Byte BitMask);
|
||||
|
||||
//
|
||||
// Memory Relative Function.
|
||||
//
|
||||
void ODM_AllocateMemory(PDM_ODM_T pDM_Odm, void **pPtr, u4Byte length);
|
||||
void ODM_FreeMemory(PDM_ODM_T pDM_Odm, void *pPtr, u4Byte length);
|
||||
void ODM_AllocateMemory(struct odm_dm_struct *pDM_Odm, void **pPtr, u4Byte length);
|
||||
void ODM_FreeMemory(struct odm_dm_struct *pDM_Odm, void *pPtr, u4Byte length);
|
||||
|
||||
s4Byte ODM_CompareMemory(PDM_ODM_T pDM_Odm, void *pBuf1, void *pBuf2, u4Byte length);
|
||||
s4Byte ODM_CompareMemory(struct odm_dm_struct *pDM_Odm, void *pBuf1, void *pBuf2, u4Byte length);
|
||||
|
||||
//
|
||||
// ODM MISC-spin lock relative API.
|
||||
//
|
||||
void ODM_AcquireSpinLock(PDM_ODM_T pDM_Odm, RT_SPINLOCK_TYPE type);
|
||||
void ODM_AcquireSpinLock(struct odm_dm_struct *pDM_Odm, RT_SPINLOCK_TYPE type);
|
||||
|
||||
void ODM_ReleaseSpinLock(PDM_ODM_T pDM_Odm, RT_SPINLOCK_TYPE type);
|
||||
void ODM_ReleaseSpinLock(struct odm_dm_struct *pDM_Odm, RT_SPINLOCK_TYPE type);
|
||||
|
||||
//
|
||||
// ODM MISC-workitem relative API.
|
||||
//
|
||||
void ODM_InitializeWorkItem(PDM_ODM_T pDM_Odm, void *pRtWorkItem,
|
||||
void ODM_InitializeWorkItem(struct odm_dm_struct *pDM_Odm, void *pRtWorkItem,
|
||||
RT_WORKITEM_CALL_BACK RtWorkItemCallback,
|
||||
void *pContext, const char *szID);
|
||||
|
||||
|
|
@ -152,13 +152,13 @@ void ODM_sleep_ms(u4Byte ms);
|
|||
|
||||
void ODM_sleep_us(u4Byte us);
|
||||
|
||||
void ODM_SetTimer(PDM_ODM_T pDM_Odm, PRT_TIMER pTimer, u4Byte msDelay);
|
||||
void ODM_SetTimer(struct odm_dm_struct *pDM_Odm, PRT_TIMER pTimer, u4Byte msDelay);
|
||||
|
||||
void ODM_InitializeTimer(PDM_ODM_T pDM_Odm, PRT_TIMER pTimer, RT_TIMER_CALL_BACK CallBackFunc, void *pContext, const char *szID);
|
||||
void ODM_InitializeTimer(struct odm_dm_struct *pDM_Odm, PRT_TIMER pTimer, RT_TIMER_CALL_BACK CallBackFunc, void *pContext, const char *szID);
|
||||
|
||||
void ODM_CancelTimer(PDM_ODM_T pDM_Odm, PRT_TIMER pTimer);
|
||||
void ODM_CancelTimer(struct odm_dm_struct *pDM_Odm, PRT_TIMER pTimer);
|
||||
|
||||
void ODM_ReleaseTimer(PDM_ODM_T pDM_Odm, PRT_TIMER pTimer);
|
||||
void ODM_ReleaseTimer(struct odm_dm_struct *pDM_Odm, PRT_TIMER pTimer);
|
||||
|
||||
//
|
||||
// ODM FW relative API.
|
||||
|
|
|
|||
|
|
@ -409,7 +409,7 @@ typedef struct hal_data_8188e
|
|||
u8 RegCR_1;
|
||||
|
||||
struct dm_priv dmpriv;
|
||||
DM_ODM_T odmpriv;
|
||||
struct odm_dm_struct odmpriv;
|
||||
struct sreset_priv srestpriv;
|
||||
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
|
|
|
|||
|
|
@ -101,8 +101,7 @@ struct signal_stat {
|
|||
u32 total_val; //sum of valid elements
|
||||
};
|
||||
#define MAX_PATH_NUM_92CS 2
|
||||
struct phy_info //ODM_PHY_INFO_T
|
||||
{
|
||||
struct phy_info {
|
||||
u8 RxPWDBAll;
|
||||
u8 SignalQuality; // in 0-100 index.
|
||||
u8 RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; //EVM
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue