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rtl8188eu: Convert all typedef statements in include/odm.h

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2013-07-26 11:20:42 -05:00
parent d8af6fff83
commit f311a752bb
32 changed files with 603 additions and 710 deletions
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78
hal/Hal8188ERateAdaptive.c
View file

@ -117,8 +117,8 @@ static u2Byte DynamicTxRPTTiming[6] = {
/* End Rate adaptive parameters */
static void odm_SetTxRPTTiming_8188E(
PDM_ODM_T pDM_Odm,
PODM_RA_INFO_T pRaInfo,
struct odm_dm_struct * pDM_Odm,
struct odm_ra_info *pRaInfo,
u1Byte extend
)
{
@ -145,8 +145,8 @@ static void odm_SetTxRPTTiming_8188E(
}
static int odm_RateDown_8188E(
PDM_ODM_T pDM_Odm,
PODM_RA_INFO_T pRaInfo
struct odm_dm_struct *pDM_Odm,
struct odm_ra_info *pRaInfo
)
{
u1Byte RateID, LowestRate, HighestRate;
@ -204,8 +204,8 @@ RateDownFinish:
}
static int odm_RateUp_8188E(
PDM_ODM_T pDM_Odm,
PODM_RA_INFO_T pRaInfo
struct odm_dm_struct * pDM_Odm,
struct odm_ra_info *pRaInfo
)
{
u1Byte RateID, HighestRate;
@ -259,15 +259,15 @@ RateUpfinish:
return 0;
}
static void odm_ResetRaCounter_8188E(PODM_RA_INFO_T pRaInfo){
static void odm_ResetRaCounter_8188E(struct odm_ra_info *pRaInfo){
u1Byte RateID;
RateID=pRaInfo->DecisionRate;
pRaInfo->NscUp=(N_THRESHOLD_HIGH[RateID]+N_THRESHOLD_LOW[RateID])>>1;
pRaInfo->NscDown=(N_THRESHOLD_HIGH[RateID]+N_THRESHOLD_LOW[RateID])>>1;
}
static void odm_RateDecision_8188E(PDM_ODM_T pDM_Odm,
PODM_RA_INFO_T pRaInfo
static void odm_RateDecision_8188E(struct odm_dm_struct * pDM_Odm,
struct odm_ra_info *pRaInfo
)
{
u1Byte RateID = 0, RtyPtID = 0, PenaltyID1 = 0, PenaltyID2 = 0;
@ -356,8 +356,8 @@ static void odm_RateDecision_8188E(PDM_ODM_T pDM_Odm,
static int
odm_ARFBRefresh_8188E(
PDM_ODM_T pDM_Odm,
PODM_RA_INFO_T pRaInfo
struct odm_dm_struct * pDM_Odm,
struct odm_ra_info *pRaInfo
)
{ /* Wilson 2011/10/26 */
u4Byte MaskFromReg;
@ -460,7 +460,7 @@ odm_ARFBRefresh_8188E(
#if POWER_TRAINING_ACTIVE == 1
static void
odm_PTTryState_8188E(
PODM_RA_INFO_T pRaInfo
struct odm_ra_info *pRaInfo
)
{
pRaInfo->PTTryState=0;
@ -520,7 +520,7 @@ odm_PTTryState_8188E(
static void
odm_PTDecision_8188E(
PODM_RA_INFO_T pRaInfo
struct odm_ra_info *pRaInfo
)
{
u1Byte j;
@ -561,7 +561,7 @@ odm_PTDecision_8188E(
static void
odm_RATxRPTTimerSetting(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct * pDM_Odm,
u2Byte minRptTime
)
{
@ -579,7 +579,7 @@ odm_RATxRPTTimerSetting(
void
ODM_RASupport_Init(
PDM_ODM_T pDM_Odm
struct odm_dm_struct *pDM_Odm
)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>ODM_RASupport_Init()\n"));
@ -594,11 +594,11 @@ ODM_RASupport_Init(
int
ODM_RAInfo_Init(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u1Byte MacID
)
{
PODM_RA_INFO_T pRaInfo = &pDM_Odm->RAInfo[MacID];
struct odm_ra_info *pRaInfo = &pDM_Odm->RAInfo[MacID];
#if 1
u1Byte WirelessMode=0xFF; /* invalid value */
u1Byte max_rate_idx = 0x13; /* MCS7 */
@ -664,7 +664,7 @@ ODM_RAInfo_Init(
int
ODM_RAInfo_Init_all(
PDM_ODM_T pDM_Odm
struct odm_dm_struct * pDM_Odm
)
{
u1Byte MacID = 0;
@ -681,7 +681,7 @@ ODM_RAInfo_Init_all(
u1Byte
ODM_RA_GetShortGI_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u1Byte MacID
)
{
@ -694,7 +694,7 @@ ODM_RA_GetShortGI_8188E(
u1Byte
ODM_RA_GetDecisionRate_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u1Byte MacID
)
{
@ -710,7 +710,7 @@ ODM_RA_GetDecisionRate_8188E(
u1Byte
ODM_RA_GetHwPwrStatus_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u1Byte MacID
)
{
@ -725,14 +725,14 @@ ODM_RA_GetHwPwrStatus_8188E(
void
ODM_RA_UpdateRateInfo_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u1Byte MacID,
u1Byte RateID,
u4Byte RateMask,
u1Byte SGIEnable
)
{
PODM_RA_INFO_T pRaInfo = NULL;
struct odm_ra_info *pRaInfo = NULL;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD,
("MacID=%d RateID=0x%x RateMask=0x%x SGIEnable=%d\n",
@ -749,12 +749,12 @@ ODM_RA_UpdateRateInfo_8188E(
void
ODM_RA_SetRSSI_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct * pDM_Odm,
u1Byte MacID,
u1Byte Rssi
)
{
PODM_RA_INFO_T pRaInfo = NULL;
struct odm_ra_info *pRaInfo = NULL;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,
(" MacID=%d Rssi=%d\n", MacID, Rssi));
@ -767,7 +767,7 @@ ODM_RA_SetRSSI_8188E(
void
ODM_RA_Set_TxRPT_Time(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct * pDM_Odm,
u2Byte minRptTime
)
{
@ -777,14 +777,14 @@ ODM_RA_Set_TxRPT_Time(
void
ODM_RA_TxRPT2Handle_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct * pDM_Odm,
pu1Byte TxRPT_Buf,
u2Byte TxRPT_Len,
u4Byte MacIDValidEntry0,
u4Byte MacIDValidEntry1
)
{
PODM_RA_INFO_T pRAInfo = NULL;
struct odm_ra_info *pRAInfo = NULL;
u1Byte MacId = 0;
pu1Byte pBuffer = NULL;
u4Byte valid = 0, ItemNum = 0;
@ -894,7 +894,7 @@ ODM_RA_TxRPT2Handle_8188E(
static void
odm_RATxRPTTimerSetting(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct * pDM_Odm,
u2Byte minRptTime
)
{
@ -904,7 +904,7 @@ odm_RATxRPTTimerSetting(
void
ODM_RASupport_Init(
PDM_ODM_T pDM_Odm
struct odm_dm_struct *pDM_Odm
)
{
return;
@ -912,7 +912,7 @@ ODM_RASupport_Init(
int
ODM_RAInfo_Init(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u1Byte MacID
)
{
@ -921,7 +921,7 @@ ODM_RAInfo_Init(
int
ODM_RAInfo_Init_all(
PDM_ODM_T pDM_Odm
struct odm_dm_struct * pDM_Odm
)
{
return 0;
@ -929,7 +929,7 @@ ODM_RAInfo_Init_all(
u1Byte
ODM_RA_GetShortGI_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u1Byte MacID
)
{
@ -938,7 +938,7 @@ ODM_RA_GetShortGI_8188E(
u1Byte
ODM_RA_GetDecisionRate_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u1Byte MacID
)
{
@ -946,7 +946,7 @@ ODM_RA_GetDecisionRate_8188E(
}
u1Byte
ODM_RA_GetHwPwrStatus_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u1Byte MacID
)
{
@ -955,7 +955,7 @@ ODM_RA_GetHwPwrStatus_8188E(
void
ODM_RA_UpdateRateInfo_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u1Byte MacID,
u1Byte RateID,
u4Byte RateMask,
@ -967,7 +967,7 @@ ODM_RA_UpdateRateInfo_8188E(
void
ODM_RA_SetRSSI_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct * pDM_Odm,
u1Byte MacID,
u1Byte Rssi
)
@ -977,7 +977,7 @@ ODM_RA_SetRSSI_8188E(
void
ODM_RA_Set_TxRPT_Time(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct * pDM_Odm,
u2Byte minRptTime
)
{
@ -986,7 +986,7 @@ ODM_RA_Set_TxRPT_Time(
void
ODM_RA_TxRPT2Handle_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct * pDM_Odm,
pu1Byte TxRPT_Buf,
u2Byte TxRPT_Len,
u4Byte MacIDValidEntry0,

6
hal/HalHWImg8188E_BB.c
View file

@ -191,7 +191,7 @@ static u4Byte Array_AGC_TAB_1T_8188E[] = {
HAL_STATUS
ODM_ReadAndConfig_AGC_TAB_1T_8188E(
PDM_ODM_T pDM_Odm
struct odm_dm_struct * pDM_Odm
)
{
#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while (0)
@ -493,7 +493,7 @@ static u4Byte Array_PHY_REG_1T_8188E[] = {
HAL_STATUS
ODM_ReadAndConfig_PHY_REG_1T_8188E(
PDM_ODM_T pDM_Odm
struct odm_dm_struct * pDM_Odm
)
{
#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while (0)
@ -742,7 +742,7 @@ static u4Byte Array_PHY_REG_PG_8188E[] = {
void
ODM_ReadAndConfig_PHY_REG_PG_8188E(
PDM_ODM_T pDM_Odm
struct odm_dm_struct * pDM_Odm
)
{
u4Byte hex = 0;

2
hal/HalHWImg8188E_MAC.c
View file

@ -151,7 +151,7 @@ static u4Byte Array_MAC_REG_8188E[] = {
HAL_STATUS
ODM_ReadAndConfig_MAC_REG_8188E(
PDM_ODM_T pDM_Odm
struct odm_dm_struct * pDM_Odm
)
{
#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while (0)

2
hal/HalHWImg8188E_RF.c
View file

@ -160,7 +160,7 @@ static u4Byte Array_RadioA_1T_8188E[] = {
0x000, 0x00033E60,
};
HAL_STATUS ODM_ReadAndConfig_RadioA_1T_8188E(PDM_ODM_T pDM_Odm)
HAL_STATUS ODM_ReadAndConfig_RadioA_1T_8188E(struct odm_dm_struct * pDM_Odm)
{
#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while (0)

4
hal/HalPhyRf.c
View file

@ -26,7 +26,7 @@
void
ODM_ResetIQKResult(
PDM_ODM_T pDM_Odm
struct odm_dm_struct *pDM_Odm
)
{
u1Byte i;
@ -34,7 +34,7 @@ ODM_ResetIQKResult(
if (!IS_HARDWARE_TYPE_8192D(Adapter))
return;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("PHY_ResetIQKResult:: settings regs %d default regs %d\n", (u32)(sizeof(pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting)/sizeof(IQK_MATRIX_REGS_SETTING)), IQK_Matrix_Settings_NUM));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("PHY_ResetIQKResult:: settings regs %d default regs %d\n", (u32)(sizeof(pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting)/sizeof(struct ijk_matrix_regs_set)), IQK_Matrix_Settings_NUM));
/* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */
for (i = 0; i < IQK_Matrix_Settings_NUM; i++)

50
hal/HalPhyRf_8188e.c
View file

@ -53,7 +53,7 @@
*---------------------------------------------------------------------------*/
void
ODM_TxPwrTrackAdjust88E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u1Byte Type, /* 0 = OFDM, 1 = CCK */
pu1Byte pDirection, /* 1 = +(increase) 2 = -(decrease) */
pu4Byte pOutWriteVal /* Tx tracking CCK/OFDM BB swing index adjust */
@ -132,7 +132,7 @@ ODM_TxPwrTrackAdjust88E(
*---------------------------------------------------------------------------*/
static void
odm_TxPwrTrackSetPwr88E(
PDM_ODM_T pDM_Odm
struct odm_dm_struct *pDM_Odm
)
{
if (pDM_Odm->BbSwingFlagOfdm == true || pDM_Odm->BbSwingFlagCck == true)
@ -181,7 +181,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
12, 14, 16, 18, 20, 22,
25, 25, 25},
};
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
odm_TxPwrTrackSetPwr88E(pDM_Odm);
@ -554,7 +554,7 @@ phy_PathA_IQK_8188E(
u4Byte regEAC, regE94, regE9C, regEA4;
u1Byte result = 0x00;
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n"));
/* 1 Tx IQK */
@ -607,7 +607,7 @@ phy_PathA_RxIQK(
u4Byte regEAC, regE94, regE9C, regEA4, u4tmp;
u1Byte result = 0x00;
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n"));
/* 1 Get TXIMR setting */
@ -740,7 +740,7 @@ phy_PathB_IQK_8188E(
u4Byte regEAC, regEB4, regEBC, regEC4, regECC;
u1Byte result = 0x00;
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n"));
/* One shot, path B LOK & IQK */
@ -796,7 +796,7 @@ _PHY_PathAFillIQKMatrix(
u4Byte Oldval_0, X, TX0_A, reg;
s4Byte Y, TX0_C;
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed"));
if (final_candidate == 0xFF)
@ -856,7 +856,7 @@ _PHY_PathBFillIQKMatrix(
u4Byte Oldval_1, X, TX1_A, reg;
s4Byte Y, TX1_C;
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed"));
if (final_candidate == 0xFF)
@ -921,7 +921,7 @@ _PHY_SaveADDARegisters(
{
u4Byte i;
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
if (ODM_CheckPowerStatus(pAdapter) == false)
return;
@ -941,7 +941,7 @@ static void _PHY_SaveMACRegisters(
{
u4Byte i;
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n"));
for ( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){
MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]);
@ -961,7 +961,7 @@ _PHY_ReloadADDARegisters(
{
u4Byte i;
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n"));
for (i = 0 ; i < RegiesterNum; i++)
@ -979,7 +979,7 @@ _PHY_ReloadMACRegisters(
{
u4Byte i;
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n"));
for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){
@ -1000,7 +1000,7 @@ _PHY_PathADDAOn(
u4Byte pathOn;
u4Byte i;
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n"));
pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4;
@ -1027,7 +1027,7 @@ _PHY_MACSettingCalibration(
{
u4Byte i = 0;
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n"));
@ -1046,7 +1046,7 @@ _PHY_PathAStandBy(
)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n"));
@ -1062,7 +1062,7 @@ static void _PHY_PIModeSwitch(
{
u4Byte mode;
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI")));
@ -1080,7 +1080,7 @@ static bool phy_SimularityCompare_8188E(
{
u4Byte i, j, diff, SimularityBitMap, bound = 0;
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
u1Byte final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */
bool bResult = true;
bool is2T;
@ -1199,7 +1199,7 @@ static void phy_IQCalibrate_8188E(
)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
u4Byte i;
u1Byte PathAOK, PathBOK;
u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = {
@ -1387,7 +1387,7 @@ static void phy_LCCalibrate_8188E(
u1Byte tmpReg;
u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal;
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
/* Check continuous TX and Packet TX */
tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03);
@ -1454,7 +1454,7 @@ static void phy_APCalibrate_8188E(
)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
u4Byte regD[PATH_NUM];
u4Byte tmpReg, index, offset, apkbound;
u1Byte path, i, pathbound = PATH_NUM;
@ -1887,7 +1887,7 @@ PHY_IQCalibrate_8188E(
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
#if (MP_DRIVER == 1)
PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
@ -2078,7 +2078,7 @@ PHY_LCCalibrate_8188E(
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
#if (MP_DRIVER == 1)
PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
@ -2136,7 +2136,7 @@ PHY_APCalibrate_8188E(
)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
#if DISABLE_BB_RF
return;
@ -2168,7 +2168,7 @@ static void phy_SetRFPathSwitch_8188E(
)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
if (pAdapter->hw_init_completed == false)
{
@ -2200,7 +2200,7 @@ void PHY_SetRFPathSwitch_8188E(
)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
struct odm_dm_struct * pDM_Odm = &pHalData->odmpriv;
#if DISABLE_BB_RF
return;

326
hal/odm.c
View file

File diff suppressed because it is too large Load diff

60
hal/odm_HWConfig.c
View file

@ -55,7 +55,7 @@ static u1Byte odm_QueryRxPwrPercentage(s1Byte AntPower)
/* IF other SW team do not support the feature, remove this section.?? */
/* */
static s4Byte odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
s4Byte CurrSig
)
{
@ -64,7 +64,7 @@ static s4Byte odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo(
}
static s4Byte odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
s4Byte CurrSig
)
{
@ -74,7 +74,7 @@ static s4Byte odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore(
static s4Byte
odm_SignalScaleMapping_92CSeries(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
s4Byte CurrSig
)
{
@ -167,7 +167,7 @@ odm_SignalScaleMapping_92CSeries(
}
static s4Byte
odm_SignalScaleMapping(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
s4Byte CurrSig
)
{
@ -191,7 +191,7 @@ odm_SignalScaleMapping(
/* pMgntInfo->CustomerID == RT_CID_819x_Lenovo */
static u1Byte odm_SQ_process_patch_RT_CID_819x_Lenovo(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u1Byte isCCKrate,
u1Byte PWDB_ALL,
u1Byte path,
@ -235,13 +235,13 @@ odm_EVMdbToPercentage(
static void
odm_RxPhyStatus92CSeries_Parsing(
PDM_ODM_T pDM_Odm,
PODM_PHY_INFO_T pPhyInfo,
struct odm_dm_struct * pDM_Odm,
struct odm_phy_status_info *pPhyInfo,
pu1Byte pPhyStatus,
PODM_PACKET_INFO_T pPktinfo
struct odm_per_pkt_info *pPktinfo
)
{
SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
u1Byte i, Max_spatial_stream;
s1Byte rx_pwr[4], rx_pwr_all=0;
u1Byte EVM, PWDB_ALL = 0, PWDB_ALL_BT;
@ -566,16 +566,16 @@ odm_RxPhyStatus92CSeries_Parsing(
void
odm_Init_RSSIForDM(
PDM_ODM_T pDM_Odm
struct odm_dm_struct *pDM_Odm
)
{
}
static void odm_Process_RSSIForDM(
PDM_ODM_T pDM_Odm,
PODM_PHY_INFO_T pPhyInfo,
PODM_PACKET_INFO_T pPktinfo
struct odm_dm_struct * pDM_Odm,
struct odm_phy_status_info *pPhyInfo,
struct odm_per_pkt_info *pPktinfo
)
{
@ -611,7 +611,7 @@ static void odm_Process_RSSIForDM(
if (pDM_Odm->SupportICType == ODM_RTL8188E)
{
u1Byte antsel_tr_mux;
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
struct fast_ant_train *pDM_FatTable = &pDM_Odm->DM_FatTable;
if (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)
{
@ -778,10 +778,10 @@ static void odm_Process_RSSIForDM(
/* */
static void
ODM_PhyStatusQuery_92CSeries(
PDM_ODM_T pDM_Odm,
PODM_PHY_INFO_T pPhyInfo,
struct odm_dm_struct * pDM_Odm,
struct odm_phy_status_info *pPhyInfo,
pu1Byte pPhyStatus,
PODM_PACKET_INFO_T pPktinfo
struct odm_per_pkt_info *pPktinfo
)
{
@ -808,10 +808,10 @@ ODM_PhyStatusQuery_92CSeries(
/* */
static void
ODM_PhyStatusQuery_JaguarSeries(
PDM_ODM_T pDM_Odm,
PODM_PHY_INFO_T pPhyInfo,
struct odm_dm_struct * pDM_Odm,
struct odm_phy_status_info *pPhyInfo,
pu1Byte pPhyStatus,
PODM_PACKET_INFO_T pPktinfo
struct odm_per_pkt_info *pPktinfo
)
{
@ -820,10 +820,10 @@ ODM_PhyStatusQuery_JaguarSeries(
void
ODM_PhyStatusQuery(
PDM_ODM_T pDM_Odm,
PODM_PHY_INFO_T pPhyInfo,
struct odm_dm_struct * pDM_Odm,
struct odm_phy_status_info *pPhyInfo,
pu1Byte pPhyStatus,
PODM_PACKET_INFO_T pPktinfo
struct odm_per_pkt_info *pPktinfo
)
{
ODM_PhyStatusQuery_92CSeries(pDM_Odm,pPhyInfo,pPhyStatus,pPktinfo);
@ -832,7 +832,7 @@ ODM_PhyStatusQuery(
/* For future use. */
void
ODM_MacStatusQuery(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct * pDM_Odm,
pu1Byte pMacStatus,
u1Byte MacID,
bool bPacketMatchBSSID,
@ -846,9 +846,9 @@ ODM_MacStatusQuery(
HAL_STATUS
ODM_ConfigRFWithHeaderFile(
PDM_ODM_T pDM_Odm,
ODM_RF_RADIO_PATH_E Content,
ODM_RF_RADIO_PATH_E eRFPath
struct odm_dm_struct * pDM_Odm,
enum ODM_RF_RADIO_PATH Content,
enum ODM_RF_RADIO_PATH eRFPath
)
{
/* RT_STATUS rtStatus = RT_STATUS_SUCCESS; */
@ -875,8 +875,8 @@ ODM_ConfigRFWithHeaderFile(
HAL_STATUS
ODM_ConfigBBWithHeaderFile(
PDM_ODM_T pDM_Odm,
ODM_BB_Config_Type ConfigType
struct odm_dm_struct * pDM_Odm,
enum odm_bb_config_type ConfigType
)
{
@ -905,7 +905,7 @@ ODM_ConfigBBWithHeaderFile(
HAL_STATUS
ODM_ConfigMACWithHeaderFile(
PDM_ODM_T pDM_Odm
struct odm_dm_struct *pDM_Odm
)
{
u1Byte result = HAL_STATUS_SUCCESS;

64
hal/odm_RTL8188E.c
View file

@ -28,10 +28,10 @@
void
ODM_DIG_LowerBound_88E(
PDM_ODM_T pDM_Odm
struct odm_dm_struct * pDM_Odm
)
{
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
struct rtw_dig * pDM_DigTable = &pDM_Odm->DM_DigTable;
if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
{
@ -46,7 +46,7 @@ ODM_DIG_LowerBound_88E(
static void
odm_RX_HWAntDivInit(
PDM_ODM_T pDM_Odm
struct odm_dm_struct * pDM_Odm
)
{
u4Byte value32;
@ -81,7 +81,7 @@ odm_RX_HWAntDivInit(
static void
odm_TRX_HWAntDivInit(
PDM_ODM_T pDM_Odm
struct odm_dm_struct * pDM_Odm
)
{
u4Byte value32;
@ -129,11 +129,11 @@ odm_TRX_HWAntDivInit(
static void
odm_FastAntTrainingInit(
PDM_ODM_T pDM_Odm
struct odm_dm_struct * pDM_Odm
)
{
u4Byte value32, i;
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
struct fast_ant_train *pDM_FatTable = &pDM_Odm->DM_FatTable;
u4Byte AntCombination = 2;
PADAPTER Adapter = pDM_Odm->Adapter;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_FastAntTrainingInit()\n"));
@ -226,7 +226,7 @@ odm_FastAntTrainingInit(
void
ODM_AntennaDiversityInit_88E(
PDM_ODM_T pDM_Odm
struct odm_dm_struct * pDM_Odm
)
{
if (pDM_Odm->SupportICType != ODM_RTL8188E)
@ -245,9 +245,9 @@ ODM_AntennaDiversityInit_88E(
void
ODM_UpdateRxIdleAnt_88E(PDM_ODM_T pDM_Odm, u1Byte Ant)
ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *pDM_Odm, u1Byte Ant)
{
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
struct fast_ant_train *pDM_FatTable = &pDM_Odm->DM_FatTable;
u4Byte DefaultAnt, OptionalAnt;
if (pDM_FatTable->RxIdleAnt != Ant)
@ -285,9 +285,9 @@ ODM_UpdateRxIdleAnt_88E(PDM_ODM_T pDM_Odm, u1Byte Ant)
static void
odm_UpdateTxAnt_88E(PDM_ODM_T pDM_Odm, u1Byte Ant, u4Byte MacId)
odm_UpdateTxAnt_88E(struct odm_dm_struct *pDM_Odm, u1Byte Ant, u4Byte MacId)
{
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
struct fast_ant_train *pDM_FatTable = &pDM_Odm->DM_FatTable;
u1Byte TargetAnt;
if (Ant == MAIN_ANT)
@ -307,12 +307,12 @@ odm_UpdateTxAnt_88E(PDM_ODM_T pDM_Odm, u1Byte Ant, u4Byte MacId)
void
ODM_SetTxAntByTxInfo_88E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct * pDM_Odm,
pu1Byte pDesc,
u1Byte macId
)
{
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
struct fast_ant_train *pDM_FatTable = &pDM_Odm->DM_FatTable;
if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
{
@ -324,13 +324,13 @@ ODM_SetTxAntByTxInfo_88E(
void
ODM_AntselStatistics_88E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct * pDM_Odm,
u1Byte antsel_tr_mux,
u4Byte MacId,
u1Byte RxPWDBAll
)
{
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
struct fast_ant_train *pDM_FatTable = &pDM_Odm->DM_FatTable;
if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
{
if (antsel_tr_mux == MAIN_ANT_CG_TRX)
@ -366,14 +366,14 @@ ODM_AntselStatistics_88E(
#define TX_BY_REG 0
static void
odm_HWAntDiv(
PDM_ODM_T pDM_Odm
struct odm_dm_struct * pDM_Odm
)
{
u4Byte i, MinRSSI=0xFF, AntDivMaxRSSI=0, MaxRSSI=0, LocalMinRSSI, LocalMaxRSSI;
u4Byte Main_RSSI, Aux_RSSI;
u1Byte RxIdleAnt=0, TargetAnt=7;
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
struct fast_ant_train *pDM_FatTable = &pDM_Odm->DM_FatTable;
struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
bool bMatchBSSID;
bool bPktFilterMacth = false;
PSTA_INFO_T pEntry;
@ -433,10 +433,10 @@ odm_HWAntDiv(
void
ODM_AntennaDiversity_88E(
PDM_ODM_T pDM_Odm
struct odm_dm_struct * pDM_Odm
)
{
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
struct fast_ant_train *pDM_FatTable = &pDM_Odm->DM_FatTable;
if ((pDM_Odm->SupportICType != ODM_RTL8188E) || (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)))
return;
if (!pDM_Odm->bLinked)
@ -484,9 +484,9 @@ ODM_AntennaDiversity_88E(
void
odm_PrimaryCCA_Init(
PDM_ODM_T pDM_Odm)
struct odm_dm_struct * pDM_Odm)
{
pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
struct dyn_primary_cca *PrimaryCCA = &(pDM_Odm->DM_PriCCA);
PrimaryCCA->DupRTS_flag = 0;
PrimaryCCA->intf_flag = 0;
PrimaryCCA->intf_type = 0;
@ -496,26 +496,26 @@ odm_PrimaryCCA_Init(
bool
ODM_DynamicPrimaryCCA_DupRTS(
PDM_ODM_T pDM_Odm
struct odm_dm_struct * pDM_Odm
)
{
pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
struct dyn_primary_cca *PrimaryCCA = &(pDM_Odm->DM_PriCCA);
return PrimaryCCA->DupRTS_flag;
}
void
odm_DynamicPrimaryCCA(
PDM_ODM_T pDM_Odm
struct odm_dm_struct * pDM_Odm
)
{
PADAPTER Adapter = pDM_Odm->Adapter; /* for NIC */
prtl8192cd_priv priv = pDM_Odm->priv; /* for AP */
struct rtl8192cd_priv *priv = pDM_Odm->priv; /* for AP */
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
Pfalse_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
struct dyn_primary_cca *PrimaryCCA = &(pDM_Odm->DM_PriCCA);
bool Is40MHz;
bool Client_40MHz = false, Client_tmp = false; /* connected client BW */
@ -802,23 +802,23 @@ odm_DynamicPrimaryCCA(
}
#else /* if (RTL8188E_SUPPORT == 1) */
void
ODM_UpdateRxIdleAnt_88E(PDM_ODM_T pDM_Odm, u1Byte Ant)
ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *pDM_Odm, u1Byte Ant)
{
}
void
odm_PrimaryCCA_Init(
PDM_ODM_T pDM_Odm)
struct odm_dm_struct * pDM_Odm)
{
}
void
odm_DynamicPrimaryCCA(
PDM_ODM_T pDM_Odm
struct odm_dm_struct * pDM_Odm
)
{
}
bool
ODM_DynamicPrimaryCCA_DupRTS(
PDM_ODM_T pDM_Odm
struct odm_dm_struct * pDM_Odm
)
{
return false;

16
hal/odm_RegConfig8188E.c
View file

@ -24,10 +24,10 @@
void
odm_ConfigRFReg_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct * pDM_Odm,
u4Byte Addr,
u4Byte Data,
ODM_RF_RADIO_PATH_E RF_PATH,
enum ODM_RF_RADIO_PATH RF_PATH,
u4Byte RegAddr
)
{
@ -66,7 +66,7 @@ odm_ConfigRFReg_8188E(
void
odm_ConfigRF_RadioA_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct * pDM_Odm,
u4Byte Addr,
u4Byte Data
)
@ -81,7 +81,7 @@ odm_ConfigRF_RadioA_8188E(
void
odm_ConfigRF_RadioB_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct * pDM_Odm,
u4Byte Addr,
u4Byte Data
)
@ -97,7 +97,7 @@ odm_ConfigRF_RadioB_8188E(
void
odm_ConfigMAC_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u4Byte Addr,
u1Byte Data
)
@ -108,7 +108,7 @@ odm_ConfigMAC_8188E(
void
odm_ConfigBB_AGC_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u4Byte Addr,
u4Byte Bitmask,
u4Byte Data
@ -123,7 +123,7 @@ odm_ConfigBB_AGC_8188E(
void
odm_ConfigBB_PHY_REG_PG_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u4Byte Addr,
u4Byte Bitmask,
u4Byte Data
@ -155,7 +155,7 @@ odm_ConfigBB_PHY_REG_PG_8188E(
void
odm_ConfigBB_PHY_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u4Byte Addr,
u4Byte Bitmask,
u4Byte Data

2
hal/odm_debug.c
View file

@ -26,7 +26,7 @@
void
ODM_InitDebugSetting(
PDM_ODM_T pDM_Odm
struct odm_dm_struct * pDM_Odm
)
{
pDM_Odm->DebugLevel = ODM_DBG_TRACE;

48
hal/odm_interface.c
View file

@ -27,43 +27,43 @@
/* ODM IO Relative API. */
/* */
u1Byte ODM_Read1Byte(PDM_ODM_T pDM_Odm, u4Byte RegAddr)
u1Byte ODM_Read1Byte(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr)
{
PADAPTER Adapter = pDM_Odm->Adapter;
return rtw_read8(Adapter,RegAddr);
}
u2Byte ODM_Read2Byte(PDM_ODM_T pDM_Odm, u4Byte RegAddr)
u2Byte ODM_Read2Byte(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr)
{
PADAPTER Adapter = pDM_Odm->Adapter;
return rtw_read16(Adapter,RegAddr);
}
u4Byte ODM_Read4Byte(PDM_ODM_T pDM_Odm, u4Byte RegAddr)
u4Byte ODM_Read4Byte(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr)
{
PADAPTER Adapter = pDM_Odm->Adapter;
return rtw_read32(Adapter,RegAddr);
}
void ODM_Write1Byte(PDM_ODM_T pDM_Odm, u4Byte RegAddr, u1Byte Data)
void ODM_Write1Byte(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr, u1Byte Data)
{
PADAPTER Adapter = pDM_Odm->Adapter;
rtw_write8(Adapter,RegAddr, Data);
}
void ODM_Write2Byte(PDM_ODM_T pDM_Odm, u4Byte RegAddr, u2Byte Data)
void ODM_Write2Byte(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr, u2Byte Data)
{
PADAPTER Adapter = pDM_Odm->Adapter;
rtw_write16(Adapter,RegAddr, Data);
}
void ODM_Write4Byte(PDM_ODM_T pDM_Odm, u4Byte RegAddr, u4Byte Data)
void ODM_Write4Byte(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr, u4Byte Data)
{
PADAPTER Adapter = pDM_Odm->Adapter;
rtw_write32(Adapter,RegAddr, Data);
}
void ODM_SetMACReg(PDM_ODM_T pDM_Odm, u4Byte RegAddr, u4Byte BitMask, u4Byte Data)
void ODM_SetMACReg(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr, u4Byte BitMask, u4Byte Data)
{
PADAPTER Adapter = pDM_Odm->Adapter;
PHY_SetBBReg(Adapter, RegAddr, BitMask, Data);
@ -71,7 +71,7 @@ void ODM_SetMACReg(PDM_ODM_T pDM_Odm, u4Byte RegAddr, u4Byte BitMask, u4Byte Dat
u4Byte
ODM_GetMACReg(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u4Byte RegAddr,
u4Byte BitMask
)
@ -82,7 +82,7 @@ ODM_GetMACReg(
void
ODM_SetBBReg(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u4Byte RegAddr,
u4Byte BitMask,
u4Byte Data
@ -94,7 +94,7 @@ ODM_SetBBReg(
u4Byte
ODM_GetBBReg(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u4Byte RegAddr,
u4Byte BitMask
)
@ -106,8 +106,8 @@ ODM_GetBBReg(
void
ODM_SetRFReg(
PDM_ODM_T pDM_Odm,
ODM_RF_RADIO_PATH_E eRFPath,
struct odm_dm_struct *pDM_Odm,
enum ODM_RF_RADIO_PATH eRFPath,
u4Byte RegAddr,
u4Byte BitMask,
u4Byte Data
@ -120,8 +120,8 @@ ODM_SetRFReg(
u4Byte
ODM_GetRFReg(
PDM_ODM_T pDM_Odm,
ODM_RF_RADIO_PATH_E eRFPath,
struct odm_dm_struct *pDM_Odm,
enum ODM_RF_RADIO_PATH eRFPath,
u4Byte RegAddr,
u4Byte BitMask
)
@ -138,7 +138,7 @@ ODM_GetRFReg(
/* */
void
ODM_AllocateMemory(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
void * *pPtr,
u4Byte length
)
@ -149,7 +149,7 @@ ODM_AllocateMemory(
/* length could be ignored, used to detect memory leakage. */
void
ODM_FreeMemory(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
void * pPtr,
u4Byte length
)
@ -158,7 +158,7 @@ ODM_FreeMemory(
}
s4Byte ODM_CompareMemory(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
void * pBuf1,
void * pBuf2,
u4Byte length
@ -172,7 +172,7 @@ s4Byte ODM_CompareMemory(
/* */
void
ODM_AcquireSpinLock(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
RT_SPINLOCK_TYPE type
)
{
@ -180,7 +180,7 @@ ODM_AcquireSpinLock(
void
ODM_ReleaseSpinLock(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
RT_SPINLOCK_TYPE type
)
{
@ -189,7 +189,7 @@ ODM_ReleaseSpinLock(
/* */
/* Work item relative API. FOr MP driver only~! */
/* */
void ODM_InitializeWorkItem(PDM_ODM_T pDM_Odm, void *pRtWorkItem,
void ODM_InitializeWorkItem(struct odm_dm_struct *pDM_Odm, void *pRtWorkItem,
RT_WORKITEM_CALL_BACK RtWorkItemCallback,
void *pContext, const char*szID)
{
@ -243,12 +243,12 @@ void ODM_sleep_us(u4Byte us)
rtw_usleep_os(us);
}
void ODM_SetTimer(PDM_ODM_T pDM_Odm, PRT_TIMER pTimer, u4Byte msDelay)
void ODM_SetTimer(struct odm_dm_struct *pDM_Odm, PRT_TIMER pTimer, u4Byte msDelay)
{
_set_timer(pTimer,msDelay ); /* ms */
}
void ODM_InitializeTimer(PDM_ODM_T pDM_Odm, PRT_TIMER pTimer,
void ODM_InitializeTimer(struct odm_dm_struct *pDM_Odm, PRT_TIMER pTimer,
RT_TIMER_CALL_BACK CallBackFunc, void *pContext,
const char *szID)
{
@ -256,12 +256,12 @@ void ODM_InitializeTimer(PDM_ODM_T pDM_Odm, PRT_TIMER pTimer,
_init_timer(pTimer,Adapter->pnetdev,CallBackFunc,pDM_Odm);
}
void ODM_CancelTimer(PDM_ODM_T pDM_Odm, PRT_TIMER pTimer)
void ODM_CancelTimer(struct odm_dm_struct *pDM_Odm, PRT_TIMER pTimer)
{
_cancel_timer_ex(pTimer);
}
void ODM_ReleaseTimer(PDM_ODM_T pDM_Odm, PRT_TIMER pTimer)
void ODM_ReleaseTimer(struct odm_dm_struct *pDM_Odm, PRT_TIMER pTimer)
{
}

16
hal/rtl8188e_dm.c
View file

@ -132,7 +132,7 @@ static void Init_ODM_ComInfo_88E(PADAPTER Adapter)
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
struct odm_dm_struct * pDM_Odm = &(pHalData->odmpriv);
u8 cut_ver,fab_ver;
/* */
@ -187,7 +187,7 @@ static void Update_ODM_ComInfo_88E(PADAPTER Adapter)
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv;
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
struct odm_dm_struct * pDM_Odm = &(pHalData->odmpriv);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
int i;
@ -238,7 +238,7 @@ rtl8188e_InitHalDm(
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
struct odm_dm_struct * pDM_Odm = &(pHalData->odmpriv);
u8 i;
dm_InitGPIOSetting(Adapter);
@ -264,7 +264,7 @@ rtl8188e_HalDmWatchDog(
u8 hw_init_completed = false;
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
struct odm_dm_struct * pDM_Odm = &(pHalData->odmpriv);
_func_enter_;
@ -326,7 +326,7 @@ void rtl8188e_init_dm_priv(PADAPTER Adapter)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
PDM_ODM_T podmpriv = &pHalData->odmpriv;
struct odm_dm_struct * podmpriv = &pHalData->odmpriv;
_rtw_memset(pdmpriv, 0, sizeof(struct dm_priv));
Init_ODM_ComInfo_88E(Adapter);
ODM_InitDebugSetting(podmpriv);
@ -336,7 +336,7 @@ void rtl8188e_deinit_dm_priv(PADAPTER Adapter)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
PDM_ODM_T podmpriv = &pHalData->odmpriv;
struct odm_dm_struct * podmpriv = &pHalData->odmpriv;
}
/* Add new function to reset the state of antenna diversity before link. */
@ -360,8 +360,8 @@ u8 AntDivBeforeLink8188E(PADAPTER Adapter )
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
PDM_ODM_T pDM_Odm =&pHalData->odmpriv;
SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
struct odm_dm_struct *pDM_Odm =&pHalData->odmpriv;
struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
/* Condition that does not need to use antenna diversity. */

4
hal/rtl8188e_hal_init.c
View file

@ -2433,7 +2433,7 @@ static void rtl8188e_GetHalODMVar(
bool bSet)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
PDM_ODM_T podmpriv = &pHalData->odmpriv;
struct odm_dm_struct *podmpriv = &pHalData->odmpriv;
switch (eVariable){
case HAL_ODM_STA_INFO:
break;
@ -2448,7 +2448,7 @@ static void rtl8188e_SetHalODMVar(
bool bSet)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
PDM_ODM_T podmpriv = &pHalData->odmpriv;
struct odm_dm_struct *podmpriv = &pHalData->odmpriv;
switch (eVariable){
case HAL_ODM_STA_INFO:
{

10
hal/rtl8188e_mp.c
View file

@ -31,7 +31,7 @@ s32 Hal_SetPowerTracking(PADAPTER padapter, u8 enable)
struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
struct odm_dm_struct * pDM_Odm = &(pHalData->odmpriv);
if (!netif_running(padapter->pnetdev)) {
@ -59,7 +59,7 @@ void Hal_GetPowerTracking(PADAPTER padapter, u8 *enable)
struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
struct odm_dm_struct * pDM_Odm = &(pHalData->odmpriv);
*enable = pDM_Odm->RFCalibrateInfo.TxPowerTrackControl;
@ -71,7 +71,7 @@ static void Hal_disable_dm(PADAPTER padapter)
struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
struct odm_dm_struct * pDM_Odm = &(pHalData->odmpriv);
/* 3 1. disable firmware dynamic mechanism */
@ -215,7 +215,7 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, bool beven)
PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
struct dm_priv *pdmpriv = &pHalData->dmpriv;
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
struct odm_dm_struct * pDM_Odm = &(pHalData->odmpriv);
if (!IS_92C_SERIAL(pHalData->VersionID))
@ -297,7 +297,7 @@ void Hal_SetChannel(PADAPTER pAdapter)
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
struct mp_priv *pmp = &pAdapter->mppriv;
struct dm_priv *pdmpriv = &pHalData->dmpriv;
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
struct odm_dm_struct * pDM_Odm = &(pHalData->odmpriv);
u8 channel = pmp->channel;
u8 bandwidth = pmp->bandwidth;

4
hal/rtl8188e_rf6052.c
View file

@ -615,11 +615,11 @@ phy_RF6052_Config_ParaFile(
/*----Initialize RF fom connfiguration file----*/
switch (eRFPath) {
case RF_PATH_A:
if (HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(ODM_RF_RADIO_PATH_E)eRFPath, (ODM_RF_RADIO_PATH_E)eRFPath))
if (HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(enum ODM_RF_RADIO_PATH)eRFPath, (enum ODM_RF_RADIO_PATH)eRFPath))
rtStatus= _FAIL;
break;
case RF_PATH_B:
if (HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(ODM_RF_RADIO_PATH_E)eRFPath, (ODM_RF_RADIO_PATH_E)eRFPath))
if (HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(enum ODM_RF_RADIO_PATH)eRFPath, (enum ODM_RF_RADIO_PATH)eRFPath))
rtStatus= _FAIL;
break;
case RF_PATH_C:

4
hal/rtl8188e_rxdesc.c
View file

@ -177,9 +177,9 @@ void update_recvframe_phyinfo_88e(
PADAPTER padapter = precvframe->u.hdr.adapter;
struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
PODM_PHY_INFO_T pPHYInfo = (PODM_PHY_INFO_T)(&pattrib->phy_info);
struct odm_phy_status_info *pPHYInfo = (struct odm_phy_status_info *)(&pattrib->phy_info);
u8 *wlanhdr;
ODM_PACKET_INFO_T pkt_info;
struct odm_per_pkt_info pkt_info;
u8 *sa;
struct sta_priv *pstapriv;
struct sta_info *psta;

16
hal/usb_halinit.c
View file

@ -2052,7 +2052,7 @@ static void SetHwReg8188EU(PADAPTER Adapter, u8 variable, u8* val)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
DM_ODM_T *podmpriv = &pHalData->odmpriv;
struct odm_dm_struct *podmpriv = &pHalData->odmpriv;
_func_enter_;
switch (variable)
@ -2551,7 +2551,7 @@ _func_enter_;
break;
case HW_VAR_INITIAL_GAIN:
{
DIG_T *pDigTable = &podmpriv->DM_DigTable;
struct rtw_dig *pDigTable = &podmpriv->DM_DigTable;
u32 rx_gain = ((u32 *)(val))[0];
if (rx_gain == 0xff){/* restore rx gain */
@ -2758,7 +2758,7 @@ _func_exit_;
static void GetHwReg8188EU(PADAPTER Adapter, u8 variable, u8* val)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
DM_ODM_T *podmpriv = &pHalData->odmpriv;
struct odm_dm_struct *podmpriv = &pHalData->odmpriv;
_func_enter_;
switch (variable)
@ -2925,7 +2925,7 @@ GetHalDefVar8188EUsb(
case HW_DEF_ODM_DBG_FLAG:
{
u8Byte DebugComponents = *((u32*)pValue);
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
struct odm_dm_struct *pDM_Odm = &(pHalData->odmpriv);
printk("pDM_Odm->DebugComponents = 0x%llx\n",pDM_Odm->DebugComponents );
}
break;
@ -2967,7 +2967,7 @@ static u8 SetHalDefVar8188EUsb(
{
u8 dm_func = *(( u8*)pValue);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
DM_ODM_T *podmpriv = &pHalData->odmpriv;
struct odm_dm_struct *podmpriv = &pHalData->odmpriv;
if (dm_func == 0){ /* disable all dynamic func */
podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE;
@ -2990,7 +2990,7 @@ static u8 SetHalDefVar8188EUsb(
else if (dm_func == 6){/* turn on all dynamic func */
if (!(podmpriv->SupportAbility & DYNAMIC_BB_DIG))
{
DIG_T *pDigTable = &podmpriv->DM_DigTable;
struct rtw_dig *pDigTable = &podmpriv->DM_DigTable;
pDigTable->CurIGValue= rtw_read8(Adapter,0xc50);
}
podmpriv->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE;
@ -3007,7 +3007,7 @@ static u8 SetHalDefVar8188EUsb(
case HW_DEF_FA_CNT_DUMP:
{
u8 bRSSIDump = *((u8*)pValue);
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
struct odm_dm_struct * pDM_Odm = &(pHalData->odmpriv);
if (bRSSIDump)
pDM_Odm->DebugComponents = ODM_COMP_DIG|ODM_COMP_FA_CNT ;
else
@ -3018,7 +3018,7 @@ static u8 SetHalDefVar8188EUsb(
case HW_DEF_ODM_DBG_FLAG:
{
u8Byte DebugComponents = *((u8Byte*)pValue);
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
struct odm_dm_struct *pDM_Odm = &(pHalData->odmpriv);
pDM_Odm->DebugComponents = DebugComponents;
}
break;

20
include/Hal8188ERateAdaptive.h
View file

@ -40,40 +40,40 @@ Major Change History:
void
ODM_RASupport_Init(
PDM_ODM_T pDM_Odm
struct odm_dm_struct *pDM_Odm
);
int
ODM_RAInfo_Init_all(
PDM_ODM_T pDM_Odm
struct odm_dm_struct * pDM_Odm
);
int
ODM_RAInfo_Init(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u1Byte MacID
);
u1Byte
ODM_RA_GetShortGI_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u1Byte MacID
);
u1Byte
ODM_RA_GetDecisionRate_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u1Byte MacID
);
u1Byte
ODM_RA_GetHwPwrStatus_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u1Byte MacID
);
void
ODM_RA_UpdateRateInfo_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u1Byte MacID,
u1Byte RateID,
u4Byte RateMask,
@ -82,14 +82,14 @@ ODM_RA_UpdateRateInfo_8188E(
void
ODM_RA_SetRSSI_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct * pDM_Odm,
u1Byte MacID,
u1Byte Rssi
);
void
ODM_RA_TxRPT2Handle_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct * pDM_Odm,
pu1Byte TxRPT_Buf,
u2Byte TxRPT_Len,
u4Byte MacIDValidEntry0,
@ -99,7 +99,7 @@ ODM_RA_TxRPT2Handle_8188E(
void
ODM_RA_Set_TxRPT_Time(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct * pDM_Odm,
u2Byte minRptTime
);
#endif

6
include/HalHWImg8188E_BB.h
View file

@ -30,7 +30,7 @@
HAL_STATUS
ODM_ReadAndConfig_AGC_TAB_1T_8188E(
PDM_ODM_T pDM_Odm
struct odm_dm_struct * pDM_Odm
);
/******************************************************************************
@ -39,7 +39,7 @@ ODM_ReadAndConfig_AGC_TAB_1T_8188E(
HAL_STATUS
ODM_ReadAndConfig_PHY_REG_1T_8188E(
PDM_ODM_T pDM_Odm
struct odm_dm_struct * pDM_Odm
);
/******************************************************************************
@ -48,7 +48,7 @@ ODM_ReadAndConfig_PHY_REG_1T_8188E(
void
ODM_ReadAndConfig_PHY_REG_PG_8188E(
PDM_ODM_T pDM_Odm
struct odm_dm_struct * pDM_Odm
);
#endif

7
include/HalHWImg8188E_MAC.h
View file

@ -18,7 +18,6 @@
*
******************************************************************************/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_MAC_8188E_HW_IMG_H
#define __INC_MAC_8188E_HW_IMG_H
@ -28,10 +27,6 @@
* MAC_REG.TXT
******************************************************************************/
HAL_STATUS
ODM_ReadAndConfig_MAC_REG_8188E(
PDM_ODM_T pDM_Odm
);
HAL_STATUS ODM_ReadAndConfig_MAC_REG_8188E( struct odm_dm_struct *pDM_Odm);
#endif
#endif // end of HWIMG_SUPPORT

10
include/HalHWImg8188E_RF.h
View file

@ -18,17 +18,13 @@
*
******************************************************************************/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_RF_8188E_HW_IMG_H
#define __INC_RF_8188E_HW_IMG_H
//static bool CheckCondition(const u4Byte Condition, const u4Byte Hex);
/******************************************************************************
* RadioA_1T.TXT
******************************************************************************/
* RadioA_1T.TXT
******************************************************************************/
HAL_STATUS ODM_ReadAndConfig_RadioA_1T_8188E(PDM_ODM_T pDM_Odm);
HAL_STATUS ODM_ReadAndConfig_RadioA_1T_8188E(struct odm_dm_struct * pDM_Odm);
#endif
#endif // end of HWIMG_SUPPORT

10
include/HalPhyRf.h
View file

@ -23,14 +23,8 @@
#define ODM_TARGET_CHNL_NUM_2G_5G 59
void
ODM_ResetIQKResult(
PDM_ODM_T pDM_Odm
);
void ODM_ResetIQKResult(struct odm_dm_struct *pDM_Odm);
u1Byte
ODM_GetRightChnlPlaceforIQK(
u1Byte chnl
);
u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl);
#endif // #ifndef __HAL_PHY_RF_H__

2
include/HalPhyRf_8188e.h
View file

@ -29,7 +29,7 @@
void
ODM_TxPwrTrackAdjust88E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u1Byte Type, // 0 = OFDM, 1 = CCK
pu1Byte pDirection, // 1 = +(increase) 2 = -(decrease)
pu4Byte pOutWriteVal // Tx tracking CCK/OFDM BB swing index adjust

401
include/odm.h
View file

@ -113,13 +113,11 @@
// 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement.
// We need to remove to other position???
//
typedef struct rtl8192cd_priv {
struct rtl8192cd_priv {
u1Byte temp;
};
}rtl8192cd_priv, *prtl8192cd_priv;
typedef struct _Dynamic_Initial_Gain_Threshold_
{
struct rtw_dig {
u1Byte Dig_Enable_Flag;
u1Byte Dig_Ext_Port_Stage;
@ -160,10 +158,9 @@ typedef struct _Dynamic_Initial_Gain_Threshold_
u4Byte AntDiv_RSSI_max;
u4Byte RSSI_max;
}DIG_T,*pDIG_T;
};
typedef struct _Dynamic_Power_Saving_
{
struct rtl_ps {
u1Byte PreCCAState;
u1Byte CurCCAState;
@ -175,9 +172,9 @@ typedef struct _Dynamic_Power_Saving_
u1Byte initialize;
u4Byte Reg874,RegC70,Reg85C,RegA74;
}PS_T,*pPS_T;
};
typedef struct _false_ALARM_STATISTICS{
struct false_alarm_stats {
u4Byte Cnt_Parity_Fail;
u4Byte Cnt_Rate_Illegal;
u4Byte Cnt_Crc8_fail;
@ -192,18 +189,17 @@ typedef struct _false_ALARM_STATISTICS{
u4Byte Cnt_CCA_all;
u4Byte Cnt_BW_USC; //Gary
u4Byte Cnt_BW_LSC; //Gary
}false_ALARM_STATISTICS, *Pfalse_ALARM_STATISTICS;
};
typedef struct _Dynamic_Primary_CCA{
struct dyn_primary_cca {
u1Byte PriCCA_flag;
u1Byte intf_flag;
u1Byte intf_type;
u1Byte DupRTS_flag;
u1Byte Monitor_flag;
}Pri_CCA_T, *pPri_CCA_T;
};
typedef struct _RX_High_Power_
{
struct rx_hpc {
u1Byte RXHP_flag;
u1Byte PSD_func_trigger;
u1Byte PSD_bitmap_RXHP[80];
@ -215,7 +211,7 @@ typedef struct _RX_High_Power_
bool RXHP_enable;
u1Byte TP_Mode;
RT_TIMER PSDTimer;
}RXHP_T, *pRXHP_T;
};
#define ASSOCIATE_ENTRY_NUM 32 // Max size of AsocEntry[].
#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
@ -232,8 +228,7 @@ typedef struct _RX_High_Power_
#define TRAFFIC_LOW 0
#define TRAFFIC_HIGH 1
typedef struct _SW_Antenna_Switch_
{
struct sw_ant_switch {
u1Byte try_flag;
s4Byte PreRSSI;
u1Byte CurAntenna;
@ -274,24 +269,22 @@ typedef struct _SW_Antenna_Switch_
u1Byte TargetSTA;
u1Byte antsel;
u1Byte RxIdleAnt;
}SWAT_T, *pSWAT_T;
};
typedef struct _EDCA_TURBO_
{
struct edca_turbo {
bool bCurrentTurboEDCA;
bool bIsCurRDLState;
u4Byte prv_traffic_idx; // edca turbo
}EDCA_T,*pEDCA_T;
};
typedef struct _ODM_RATE_ADAPTIVE
{
struct odm_rate_adapt {
u1Byte Type; // DM_Type_ByFW/DM_Type_ByDriver
u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH
u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW
u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW
u4Byte LastRATR; // RATR Register Content
} ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE;
};
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
@ -313,8 +306,7 @@ typedef struct _ODM_RATE_ADAPTIVE
//
#define MAX_PATH_NUM_92CS 2
typedef struct _ODM_Phy_Status_Info_
{
struct odm_phy_status_info {
u1Byte RxPWDBAll;
u1Byte SignalQuality; // in 0-100 index.
u1Byte RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; //EVM
@ -325,11 +317,10 @@ typedef struct _ODM_Phy_Status_Info_
u1Byte SignalStrength; // in 0-100 index.
u1Byte RxPwr[MAX_PATH_NUM_92CS];//per-path's pwdb
u1Byte RxSNR[MAX_PATH_NUM_92CS];//per-path's SNR
}ODM_PHY_INFO_T,*PODM_PHY_INFO_T;
};
typedef struct _ODM_Phy_Dbg_Info_
{
struct odm_phy_dbg_info {
//ODM Write,debug info
s1Byte RxSNRdB[MAX_PATH_NUM_92CS];
u8Byte NumQryPhyStatus;
@ -338,26 +329,22 @@ typedef struct _ODM_Phy_Dbg_Info_
//Others
s4Byte RxEVM[MAX_PATH_NUM_92CS];
}ODM_PHY_DBG_INFO_T;
};
typedef struct _ODM_Per_Pkt_Info_
{
struct odm_per_pkt_info {
s8 Rate;
u8 StationID;
bool bPacketMatchBSSID;
bool bPacketToSelf;
bool bPacketBeacon;
}ODM_PACKET_INFO_T,*PODM_PACKET_INFO_T;
};
typedef struct _ODM_Mac_Status_Info_
{
struct odm_mac_status_info {
u1Byte test;
}ODM_MAC_INFO;
};
typedef enum tag_Dynamic_ODM_Support_Ability_Type
{
enum odm_ability {
// BB Team
ODM_DIG = 0x00000001,
ODM_HIGH_POWER = 0x00000002,
@ -371,13 +358,13 @@ typedef enum tag_Dynamic_ODM_Support_Ability_Type
ODM_2TPATHDIV = 0x00000200,
ODM_1TPATHDIV = 0x00000400,
ODM_PSD2AFH = 0x00000800
}ODM_Ability_E;
};
//
// 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T
// Please declare below ODM relative info in your STA info structure.
//
typedef struct _ODM_STA_INFO{
struct odm_sta_info {
// Driver Write
bool bUsed; // record the sta status link or not?
//u1Byte WirelessMode; //
@ -396,13 +383,12 @@ typedef struct _ODM_STA_INFO{
//
// ODM Write Wilson will handle this part(said by Luke.Lee)
}ODM_STA_INFO_T, *PODM_STA_INFO_T;
};
//
// 2011/10/20 MH Define Common info enum for all team.
//
typedef enum _ODM_Common_Info_Definition
{
enum odm_common_info_def {
//-------------REMOVED CASE-----------//
//ODM_CMNINFO_CCK_HP,
//ODM_CMNINFO_RFPATH_ENABLE, // Define as ODM write???
@ -487,15 +473,12 @@ typedef enum _ODM_Common_Info_Definition
ODM_CMNINFO_MAC_STATUS,
ODM_CMNINFO_MAX,
}ODM_CMNINFO_E;
};
//
// 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY
//
typedef enum _ODM_Support_Ability_Definition
{
enum odm_ability_def {
//
// BB ODM section BIT 0-15
//
@ -526,20 +509,18 @@ typedef enum _ODM_Support_Ability_Definition
ODM_RF_RX_GAIN_TRACK = BIT25,
ODM_RF_CALIBRATION = BIT26,
}ODM_ABILITY_E;
};
// ODM_CMNINFO_INTERFACE
typedef enum tag_ODM_Support_Interface_Definition
{
enum odm_interface_def {
ODM_ITRF_PCIE = 0x1,
ODM_ITRF_USB = 0x2,
ODM_ITRF_SDIO = 0x4,
ODM_ITRF_ALL = 0x7,
}ODM_INTERFACE_E;
};
// ODM_CMNINFO_IC_TYPE
typedef enum tag_ODM_Support_IC_Type_Definition
{
enum odm_ic_type {
ODM_RTL8192S = BIT0,
ODM_RTL8192C = BIT1,
ODM_RTL8192D = BIT2,
@ -547,14 +528,13 @@ typedef enum tag_ODM_Support_IC_Type_Definition
ODM_RTL8188E = BIT4,
ODM_RTL8812 = BIT5,
ODM_RTL8821 = BIT6,
}ODM_IC_TYPE_E;
};
#define ODM_IC_11N_SERIES (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E)
#define ODM_IC_11AC_SERIES (ODM_RTL8812)
//ODM_CMNINFO_CUT_VER
typedef enum tag_ODM_Cut_Version_Definition
{
enum odm_cut_version {
ODM_CUT_A = 1,
ODM_CUT_B = 2,
ODM_CUT_C = 3,
@ -562,21 +542,19 @@ typedef enum tag_ODM_Cut_Version_Definition
ODM_CUT_E = 5,
ODM_CUT_F = 6,
ODM_CUT_TEST = 7,
}ODM_CUT_VERSION_E;
};
// ODM_CMNINFO_FAB_VER
typedef enum tag_ODM_Fab_Version_Definition
{
enum odm_fab_Version {
ODM_TSMC = 0,
ODM_UMC = 1,
}ODM_FAB_E;
};
// ODM_CMNINFO_RF_TYPE
//
// For example 1T2R (A+AB = BIT0|BIT4|BIT5)
//
typedef enum tag_ODM_RF_Path_Bit_Definition
{
enum odm_rf_path {
ODM_RF_TX_A = BIT0,
ODM_RF_TX_B = BIT1,
ODM_RF_TX_C = BIT2,
@ -585,11 +563,9 @@ typedef enum tag_ODM_RF_Path_Bit_Definition
ODM_RF_RX_B = BIT5,
ODM_RF_RX_C = BIT6,
ODM_RF_RX_D = BIT7,
}ODM_RF_PATH_E;
};
typedef enum tag_ODM_RF_Type_Definition
{
enum odm_rf_type {
ODM_1T1R = 0,
ODM_1T2R = 1,
ODM_2T2R = 2,
@ -598,32 +574,25 @@ typedef enum tag_ODM_RF_Type_Definition
ODM_3T3R = 5,
ODM_3T4R = 6,
ODM_4T4R = 7,
}ODM_RF_TYPE_E;
};
//
// ODM Dynamic common info value definition
//
typedef enum tag_ODM_MAC_PHY_Mode_Definition
{
enum odm_mac_phy_mode {
ODM_SMSP = 0,
ODM_DMSP = 1,
ODM_DMDP = 2,
}ODM_MAC_PHY_MODE_E;
};
typedef enum tag_BT_Coexist_Definition
{
enum odm_bt_coexist {
ODM_BT_BUSY = 1,
ODM_BT_ON = 2,
ODM_BT_OFF = 3,
ODM_BT_NONE = 4,
}ODM_BT_COEXIST_E;
};
// ODM_CMNINFO_OP_MODE
typedef enum tag_Operation_Mode_Definition
{
enum odm_operation_mode {
ODM_NO_LINK = BIT0,
ODM_LINK = BIT1,
ODM_SCAN = BIT2,
@ -633,11 +602,10 @@ typedef enum tag_Operation_Mode_Definition
ODM_AD_HOC = BIT6,
ODM_WIFI_DIRECT = BIT7,
ODM_WIFI_DISPLAY = BIT8,
}ODM_OPERATION_MODE_E;
};
// ODM_CMNINFO_WM_MODE
typedef enum tag_Wireless_Mode_Definition
{
enum odm_wireless_mode {
ODM_WM_UNKNOW = 0x0,
ODM_WM_B = BIT0,
ODM_WM_G = BIT1,
@ -646,27 +614,23 @@ typedef enum tag_Wireless_Mode_Definition
ODM_WM_N5G = BIT4,
ODM_WM_AUTO = BIT5,
ODM_WM_AC = BIT6,
}ODM_WIRELESS_MODE_E;
};
// ODM_CMNINFO_BAND
typedef enum tag_Band_Type_Definition
{
enum odm_band_type {
ODM_BAND_2_4G = BIT0,
ODM_BAND_5G = BIT1,
}ODM_BAND_TYPE_E;
};
// ODM_CMNINFO_SEC_CHNL_OFFSET
typedef enum tag_Secondary_Channel_Offset_Definition
{
enum odm_sec_chnl_offset {
ODM_DONT_CARE = 0,
ODM_BELOW = 1,
ODM_ABOVE = 2
}ODM_SEC_CHNL_OFFSET_E;
};
// ODM_CMNINFO_SEC_MODE
typedef enum tag_Security_Definition
{
enum odm_security {
ODM_SEC_OPEN = 0,
ODM_SEC_WEP40 = 1,
ODM_SEC_TKIP = 2,
@ -675,42 +639,34 @@ typedef enum tag_Security_Definition
ODM_SEC_WEP104 = 5,
ODM_WEP_WPA_MIXED = 6, // WEP + WPA
ODM_SEC_SMS4 = 7,
}ODM_SECURITY_E;
};
// ODM_CMNINFO_BW
typedef enum tag_Bandwidth_Definition
{
enum odm_bw {
ODM_BW20M = 0,
ODM_BW40M = 1,
ODM_BW80M = 2,
ODM_BW160M = 3,
ODM_BW10M = 4,
}ODM_BW_E;
// ODM_CMNINFO_CHNL
};
// ODM_CMNINFO_BOARD_TYPE
typedef enum tag_Board_Definition
{
enum odm_board_type {
ODM_BOARD_NORMAL = 0,
ODM_BOARD_HIGHPWR = 1,
ODM_BOARD_MINICARD = 2,
ODM_BOARD_SLIM = 3,
ODM_BOARD_COMBO = 4,
}ODM_BOARD_TYPE_E;
};
// ODM_CMNINFO_ONE_PATH_CCA
typedef enum tag_CCA_Path
{
enum odm_cca_path {
ODM_CCA_2R = 0,
ODM_CCA_1R_A = 1,
ODM_CCA_1R_B = 2,
}ODM_CCA_PATH_E;
};
typedef struct _ODM_RA_Info_
{
struct odm_ra_info {
u1Byte RateID;
u4Byte RateMask;
u4Byte RAUseRate;
@ -740,15 +696,14 @@ typedef struct _ODM_RA_Info_
u1Byte PTModeSS; // decide whitch rate should do PT
u1Byte RAstage; // StageRA, decide how many times RA will be done between PT
u1Byte PTSmoothFactor;
} ODM_RA_INFO_T,*PODM_RA_INFO_T;
};
typedef struct _IQK_MATRIX_REGS_SETTING{
struct ijk_matrix_regs_set {
bool bIQKDone;
s4Byte Value[1][IQK_Matrix_REG_NUM];
}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING;
};
typedef struct ODM_RF_Calibration_Structure
{
struct odm_rf_cal {
//for tx power tracking
u4Byte RegA24; // for TempCCK
@ -790,7 +745,7 @@ typedef struct ODM_RF_Calibration_Structure
u1Byte ThermalValue_HP[HP_THERMAL_NUM];
u1Byte ThermalValue_HP_index;
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
struct ijk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
u1Byte Delta_IQK;
u1Byte Delta_LCK;
@ -820,13 +775,11 @@ typedef struct ODM_RF_Calibration_Structure
u1Byte bDPdone;
u1Byte bDPPathAOK;
u1Byte bDPPathBOK;
}ODM_RF_CAL_T,*PODM_RF_CAL_T;
//
// ODM Dynamic common info value definition
//
};
typedef struct _FAST_ANTENNA_TRAINNING_
{
// ODM Dynamic common info value definition
struct fast_ant_train {
u1Byte Bssid[6];
u1Byte antsel_rx_keep_0;
u1Byte antsel_rx_keep_1;
@ -845,68 +798,43 @@ typedef struct _FAST_ANTENNA_TRAINNING_
u4Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte RxIdleAnt;
bool bBecomeLinked;
};
}FAT_T,*pFAT_T;
typedef enum _FAT_STATE
{
enum fat_state {
FAT_NORMAL_STATE = 0,
FAT_TRAINING_STATE = 1,
}FAT_STATE_E, *PFAT_STATE_E;
};
typedef enum _ANT_DIV_TYPE
{
enum ant_div_type {
NO_ANTDIV = 0xFF,
CG_TRX_HW_ANTDIV = 0x01,
CGCS_RX_HW_ANTDIV = 0x02,
FIXED_HW_ANTDIV = 0x03,
CG_TRX_SMART_ANTDIV = 0x04,
CGCS_RX_SW_ANTDIV = 0x05,
};
}ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E;
//
// 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration.
//
typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
{
//RT_TIMER FastAntTrainingTimer;
//
struct odm_dm_struct {
// Add for different team use temporarily
//
PADAPTER Adapter; // For CE/NIC team
prtl8192cd_priv priv; // For AP/ADSL team
struct rtl8192cd_priv *priv; // For AP/ADSL team
// WHen you use Adapter or priv pointer, you must make sure the pointer is ready.
bool odm_ready;
rtl8192cd_priv fake_priv;
struct rtl8192cd_priv *fake_priv;
u8Byte DebugComponents;
u4Byte DebugLevel;
//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//
//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------
bool bCckHighPower;
u1Byte RFPathRxEnable; // ODM_CMNINFO_RFPATH_ENABLE
u1Byte ControlChannel;
//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//
//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------
//1 COMMON INFORMATION
//
// Init Value
//
//-----------HOOK BEFORE REG INIT-----------//
//-----------HOOK BEFORE REG INIT-----------
// ODM Platform info AP/ADSL/CE/MP = 1/2/3/4
u1Byte SupportPlatform;
// ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K
@ -936,12 +864,12 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
bool bDualMacSmartConcurrent;
u4Byte BK_SupportAbility;
u1Byte AntDivType;
//-----------HOOK BEFORE REG INIT-----------//
//-----------HOOK BEFORE REG INIT-----------
//
// Dynamic Value
//
//--------- POINTER REFERENCE-----------//
//--------- POINTER REFERENCE-----------
u1Byte u1Byte_temp;
bool bool_temp;
@ -978,9 +906,9 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
//pMgntInfo->AntennaTest
u1Byte *pAntennaTest;
bool *pbNet_closed;
//--------- POINTER REFERENCE-----------//
//--------- POINTER REFERENCE-----------
//
//------------CALL BY VALUE-------------//
//------------CALL BY VALUE-------------
bool bWIFI_Direct;
bool bWIFI_Display;
bool bLinked;
@ -994,7 +922,7 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
u1Byte btHsDigVal; // use BT rssi to decide the DIG value
bool bBtDisableEdcaTurbo; // Under some condition, don't enable the EDCA Turbo
bool bBtBusy; // BT is busy.
//------------CALL BY VALUE-------------//
//------------CALL BY VALUE-------------
//2 Define STA info.
// _ODM_STA_INFO
@ -1003,7 +931,7 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
#if (RATE_ADAPTIVE_SUPPORT == 1)
u2Byte CurrminRptTime;
ODM_RA_INFO_T RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119
struct odm_ra_info RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119
#endif
//
// 2012/02/14 MH Add to share 88E ra with other SW team.
@ -1014,34 +942,25 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
// Define ...........
// Latest packet phy info (ODM write)
ODM_PHY_DBG_INFO_T PhyDbgInfo;
//PHY_INFO_88E PhyInfo;
struct odm_phy_dbg_info PhyDbgInfo;
// Latest packet phy info (ODM write)
ODM_MAC_INFO *pMacInfo;
//MAC_INFO_88E MacInfo;
struct odm_mac_status_info *pMacInfo;
// Different Team independt structure??
//
//TX_RTP_CMN TX_retrpo;
//TX_RTP_88E TX_retrpo;
//TX_RTP_8195 TX_retrpo;
//
//ODM Structure
//
FAT_T DM_FatTable;
DIG_T DM_DigTable;
PS_T DM_PSTable;
Pri_CCA_T DM_PriCCA;
RXHP_T DM_RXHP_Table;
false_ALARM_STATISTICS FalseAlmCnt;
false_ALARM_STATISTICS FlaseAlmCntBuddyAdapter;
SWAT_T DM_SWAT_Table;
struct fast_ant_train DM_FatTable;
struct rtw_dig DM_DigTable;
struct rtl_ps DM_PSTable;
struct dyn_primary_cca DM_PriCCA;
struct rx_hpc DM_RXHP_Table;
struct false_alarm_stats FalseAlmCnt;
struct false_alarm_stats FlaseAlmCntBuddyAdapter;
struct sw_ant_switch DM_SWAT_Table;
bool RSSI_test;
EDCA_T DM_EDCA_Table;
struct edca_turbo DM_EDCA_Table;
u4Byte WMMEDCA_BE;
// Copy from SD4 structure
//
@ -1062,10 +981,10 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
//for rate adaptive, in fact, 88c/92c fw will handle this
u1Byte bUseRAMask;
ODM_RATE_ADAPTIVE RateAdaptive;
struct odm_rate_adapt RateAdaptive;
ODM_RF_CAL_T RFCalibrateInfo;
struct odm_rf_cal RFCalibrateInfo;
//
// TX power tracking
@ -1088,34 +1007,34 @@ typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
//2011.09.27 add for Path Diversity
RT_TIMER CCKPathDiversityTimer;
RT_TIMER FastAntTrainingTimer;
} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure
}; // DM_Dynamic_Mechanism_Structure
#define ODM_RF_PATH_MAX 2
typedef enum _ODM_RF_RADIO_PATH {
enum ODM_RF_RADIO_PATH {
ODM_RF_PATH_A = 0, //Radio Path A
ODM_RF_PATH_B = 1, //Radio Path B
ODM_RF_PATH_C = 2, //Radio Path C
ODM_RF_PATH_D = 3, //Radio Path D
} ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E;
};
typedef enum _ODM_RF_CONTENT{
enum ODM_RF_CONTENT {
odm_radioa_txt = 0x1000,
odm_radiob_txt = 0x1001,
odm_radioc_txt = 0x1002,
odm_radiod_txt = 0x1003
} ODM_RF_CONTENT;
};
typedef enum _ODM_BB_Config_Type{
enum odm_bb_config_type {
CONFIG_BB_PHY_REG,
CONFIG_BB_AGC_TAB,
CONFIG_BB_AGC_TAB_2G,
CONFIG_BB_AGC_TAB_5G,
CONFIG_BB_PHY_REG_PG,
} ODM_BB_Config_Type, *PODM_BB_Config_Type;
};
// Status code
typedef enum _RT_STATUS{
enum rt_status {
RT_STATUS_SUCCESS,
RT_STATUS_FAILURE,
RT_STATUS_PENDING,
@ -1124,23 +1043,22 @@ typedef enum _RT_STATUS{
RT_STATUS_INVALID_PARAMETER,
RT_STATUS_NOT_SUPPORT,
RT_STATUS_OS_API_FAILED,
}RT_STATUS,*PRT_STATUS;
};
//3===========================================================
//3 DIG
//3===========================================================
typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition
{
DIG_TYPE_THRESH_HIGH = 0,
DIG_TYPE_THRESH_LOW = 1,
DIG_TYPE_BACKOFF = 2,
DIG_TYPE_RX_GAIN_MIN = 3,
DIG_TYPE_RX_GAIN_MAX = 4,
DIG_TYPE_ENABLE = 5,
DIG_TYPE_DISABLE = 6,
enum dm_dig_op {
RT_TYPE_THRESH_HIGH = 0,
RT_TYPE_THRESH_LOW = 1,
RT_TYPE_BACKOFF = 2,
RT_TYPE_RX_GAIN_MIN = 3,
RT_TYPE_RX_GAIN_MAX = 4,
RT_TYPE_ENABLE = 5,
RT_TYPE_DISABLE = 6,
DIG_OP_TYPE_MAX
}DM_DIG_OP_E;
};
#define DM_DIG_THRESH_HIGH 40
#define DM_DIG_THRESH_LOW 35
@ -1226,29 +1144,26 @@ typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition
//3===========================================================
typedef enum tag_1R_CCA_Type_Definition
{
enum dm_1r_cca {
CCA_1R =0,
CCA_2R = 1,
CCA_MAX = 2,
}DM_1R_CCA_E;
};
typedef enum tag_RF_Type_Definition
{
enum dm_rf {
RF_Save =0,
RF_Normal = 1,
RF_MAX = 2,
}DM_RF_E;
};
//3===========================================================
//3 Antenna Diversity
//3===========================================================
typedef enum tag_SW_Antenna_Switch_Definition
{
enum dm_swas {
Antenna_A = 1,
Antenna_B = 2,
Antenna_MAX = 3,
}DM_SWAS_E;
};
// Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28.
@ -1279,117 +1194,117 @@ extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
#define SWAW_STEP_PEAK 0
#define SWAW_STEP_DETERMINE 1
void ODM_Write_DIG( PDM_ODM_T pDM_Odm, u1Byte CurrentIGI);
void ODM_Write_CCK_CCA_Thres( PDM_ODM_T pDM_Odm, u1Byte CurCCK_CCAThres);
void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u1Byte CurrentIGI);
void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u1Byte CurCCK_CCAThres);
void
ODM_SetAntenna(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u1Byte Antenna);
#define dm_RF_Saving ODM_RF_Saving
void ODM_RF_Saving( PDM_ODM_T pDM_Odm,
void ODM_RF_Saving( struct odm_dm_struct *pDM_Odm,
u1Byte bForceInNormal );
#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink
void ODM_SwAntDivRestAfterLink( PDM_ODM_T pDM_Odm);
void ODM_SwAntDivRestAfterLink( struct odm_dm_struct *pDM_Odm);
#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
void
ODM_TXPowerTrackingCheck(
PDM_ODM_T pDM_Odm
struct odm_dm_struct *pDM_Odm
);
bool
ODM_RAStateCheck(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
s4Byte RSSI,
bool bForceUpdate,
pu1Byte pRATRState
);
#define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi
void ODM_SwAntDivChkPerPktRssi(PDM_ODM_T pDM_Odm, u1Byte StationID, PODM_PHY_INFO_T pPhyInfo);
void ODM_SwAntDivChkPerPktRssi(struct odm_dm_struct *pDM_Odm, u1Byte StationID, struct odm_phy_status_info *pPhyInfo);
u4Byte ConvertTo_dB(u4Byte Value);
u4Byte
GetPSDData(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
unsigned int point,
u1Byte initial_gain_psd);
void
odm_DIGbyRSSI_LPS(
PDM_ODM_T pDM_Odm
struct odm_dm_struct *pDM_Odm
);
u4Byte ODM_Get_Rate_Bitmap(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u4Byte macid,
u4Byte ra_mask,
u1Byte rssi_level);
void ODM_DMInit( PDM_ODM_T pDM_Odm);
void ODM_DMInit( struct odm_dm_struct *pDM_Odm);
void
ODM_DMWatchdog(
PDM_ODM_T pDM_Odm // For common use in the future
struct odm_dm_struct *pDM_Odm // For common use in the future
);
void
ODM_CmnInfoInit(
PDM_ODM_T pDM_Odm,
ODM_CMNINFO_E CmnInfo,
struct odm_dm_struct *pDM_Odm,
enum odm_common_info_def CmnInfo,
u4Byte Value
);
void
ODM_CmnInfoHook(
PDM_ODM_T pDM_Odm,
ODM_CMNINFO_E CmnInfo,
struct odm_dm_struct *pDM_Odm,
enum odm_common_info_def CmnInfo,
void * pValue
);
void
ODM_CmnInfoPtrArrayHook(
PDM_ODM_T pDM_Odm,
ODM_CMNINFO_E CmnInfo,
struct odm_dm_struct *pDM_Odm,
enum odm_common_info_def CmnInfo,
u2Byte Index,
void * pValue
);
void
ODM_CmnInfoUpdate(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u4Byte CmnInfo,
u8Byte Value
);
void
ODM_InitAllTimers(
PDM_ODM_T pDM_Odm
struct odm_dm_struct *pDM_Odm
);
void
ODM_CancelAllTimers(
PDM_ODM_T pDM_Odm
struct odm_dm_struct *pDM_Odm
);
void
ODM_ReleaseAllTimers(
PDM_ODM_T pDM_Odm
struct odm_dm_struct *pDM_Odm
);
void
ODM_ResetIQKResult(
PDM_ODM_T pDM_Odm
struct odm_dm_struct *pDM_Odm
);
void
ODM_AntselStatistics_88C(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u1Byte MacId,
u4Byte PWDBAll,
bool isCCKrate
@ -1397,15 +1312,15 @@ ODM_AntselStatistics_88C(
void
ODM_SingleDualAntennaDefaultSetting(
PDM_ODM_T pDM_Odm
struct odm_dm_struct *pDM_Odm
);
bool
ODM_SingleDualAntennaDetection(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u1Byte mode
);
void odm_dtc(PDM_ODM_T pDM_Odm);
void odm_dtc(struct odm_dm_struct *pDM_Odm);
#endif

22
include/odm_HWConfig.h
View file

@ -150,20 +150,20 @@ typedef struct _Phy_Status_Rpt_8195
void
odm_Init_RSSIForDM(
PDM_ODM_T pDM_Odm
struct odm_dm_struct *pDM_Odm
);
void
ODM_PhyStatusQuery(
PDM_ODM_T pDM_Odm,
PODM_PHY_INFO_T pPhyInfo,
struct odm_dm_struct * pDM_Odm,
struct odm_phy_status_info *pPhyInfo,
pu1Byte pPhyStatus,
PODM_PACKET_INFO_T pPktinfo
struct odm_per_pkt_info *pPktinfo
);
void
ODM_MacStatusQuery(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct * pDM_Odm,
pu1Byte pMacStatus,
u1Byte MacID,
bool bPacketMatchBSSID,
@ -173,20 +173,20 @@ ODM_MacStatusQuery(
HAL_STATUS
ODM_ConfigRFWithHeaderFile(
PDM_ODM_T pDM_Odm,
ODM_RF_RADIO_PATH_E Content,
ODM_RF_RADIO_PATH_E eRFPath
struct odm_dm_struct * pDM_Odm,
enum ODM_RF_RADIO_PATH Content,
enum ODM_RF_RADIO_PATH eRFPath
);
HAL_STATUS
ODM_ConfigBBWithHeaderFile(
PDM_ODM_T pDM_Odm,
ODM_BB_Config_Type ConfigType
struct odm_dm_struct * pDM_Odm,
enum odm_bb_config_type ConfigType
);
HAL_STATUS
ODM_ConfigMACWithHeaderFile(
PDM_ODM_T pDM_Odm
struct odm_dm_struct *pDM_Odm
);
#endif

24
include/odm_RTL8188E.h
View file

@ -27,20 +27,20 @@
#define MAIN_ANT_CGCS_RX 0
#define AUX_ANT_CGCS_RX 1
void ODM_DIG_LowerBound_88E(PDM_ODM_T pDM_Odm);
void ODM_DIG_LowerBound_88E(struct odm_dm_struct *pDM_Odm);
void ODM_AntennaDiversityInit_88E(PDM_ODM_T pDM_Odm);
void ODM_AntennaDiversityInit_88E(struct odm_dm_struct *pDM_Odm);
void ODM_AntennaDiversity_88E(PDM_ODM_T pDM_Odm);
void ODM_AntennaDiversity_88E(struct odm_dm_struct *pDM_Odm);
void ODM_SetTxAntByTxInfo_88E(PDM_ODM_T pDM_Odm,
void ODM_SetTxAntByTxInfo_88E(struct odm_dm_struct *pDM_Odm,
pu1Byte pDesc,
u1Byte macId
);
void ODM_UpdateRxIdleAnt_88E(PDM_ODM_T pDM_Odm, u1Byte Ant);
void ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *pDM_Odm, u1Byte Ant);
void ODM_AntselStatistics_88E(PDM_ODM_T pDM_Odm,
void ODM_AntselStatistics_88E(struct odm_dm_struct *pDM_Odm,
u1Byte antsel_tr_mux,
u4Byte MacId,
u1Byte RxPWDBAll
@ -48,29 +48,29 @@ void ODM_AntselStatistics_88E(PDM_ODM_T pDM_Odm,
void
odm_FastAntTraining(
PDM_ODM_T pDM_Odm
struct odm_dm_struct *pDM_Odm
);
void
odm_FastAntTrainingCallback(
PDM_ODM_T pDM_Odm
struct odm_dm_struct *pDM_Odm
);
void
odm_FastAntTrainingWorkItemCallback(
PDM_ODM_T pDM_Odm
struct odm_dm_struct *pDM_Odm
);
void
odm_PrimaryCCA_Init(
PDM_ODM_T pDM_Odm);
struct odm_dm_struct *pDM_Odm);
bool
ODM_DynamicPrimaryCCA_DupRTS(
PDM_ODM_T pDM_Odm);
struct odm_dm_struct *pDM_Odm);
void
odm_DynamicPrimaryCCA(
PDM_ODM_T pDM_Odm);
struct odm_dm_struct *pDM_Odm);
#endif

22
include/odm_RegConfig8188E.h
View file

@ -22,39 +22,33 @@
#if (RTL8188E_SUPPORT == 1)
void
odm_ConfigRFReg_8188E(
PDM_ODM_T pDM_Odm,
u4Byte Addr,
u4Byte Data,
ODM_RF_RADIO_PATH_E RF_PATH,
u4Byte RegAddr
);
void odm_ConfigRFReg_8188E(struct odm_dm_struct *pDM_Odm, u4Byte Addr, u4Byte Data,
enum ODM_RF_RADIO_PATH RF_PATH, u4Byte RegAddr);
void
odm_ConfigRF_RadioA_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u4Byte Addr,
u4Byte Data
);
void
odm_ConfigRF_RadioB_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u4Byte Addr,
u4Byte Data
);
void
odm_ConfigMAC_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u4Byte Addr,
u1Byte Data
);
void
odm_ConfigBB_AGC_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u4Byte Addr,
u4Byte Bitmask,
u4Byte Data
@ -62,7 +56,7 @@ odm_ConfigBB_AGC_8188E(
void
odm_ConfigBB_PHY_REG_PG_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u4Byte Addr,
u4Byte Bitmask,
u4Byte Data
@ -70,7 +64,7 @@ odm_ConfigBB_PHY_REG_PG_8188E(
void
odm_ConfigBB_PHY_8188E(
PDM_ODM_T pDM_Odm,
struct odm_dm_struct *pDM_Odm,
u4Byte Addr,
u4Byte Bitmask,
u4Byte Data

2
include/odm_debug.h
View file

@ -161,6 +161,6 @@
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr)
#endif
void ODM_InitDebugSetting(PDM_ODM_T pDM_Odm);
void ODM_InitDebugSetting(struct odm_dm_struct *pDM_Odm);
#endif // __ODM_DBG_H__

44
include/odm_interface.h
View file

@ -83,49 +83,49 @@ typedef void (*RT_WORKITEM_CALL_BACK)(void * pContext);
// =========== EXtern Function Prototype
//
u1Byte ODM_Read1Byte(PDM_ODM_T pDM_Odm, u4Byte RegAddr);
u1Byte ODM_Read1Byte(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr);
u2Byte ODM_Read2Byte(PDM_ODM_T pDM_Odm, u4Byte RegAddr);
u2Byte ODM_Read2Byte(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr);
u4Byte ODM_Read4Byte(PDM_ODM_T pDM_Odm, u4Byte RegAddr);
u4Byte ODM_Read4Byte(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr);
void ODM_Write1Byte(PDM_ODM_T pDM_Odm, u4Byte RegAddr, u1Byte Data);
void ODM_Write1Byte(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr, u1Byte Data);
void ODM_Write2Byte(PDM_ODM_T pDM_Odm, u4Byte RegAddr, u2Byte Data);
void ODM_Write2Byte(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr, u2Byte Data);
void ODM_Write4Byte(PDM_ODM_T pDM_Odm, u4Byte RegAddr, u4Byte Data);
void ODM_Write4Byte(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr, u4Byte Data);
void ODM_SetMACReg(PDM_ODM_T pDM_Odm, u4Byte RegAddr, u4Byte BitMask, u4Byte Data);
void ODM_SetMACReg(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr, u4Byte BitMask, u4Byte Data);
u4Byte ODM_GetMACReg(PDM_ODM_T pDM_Odm, u4Byte RegAddr, u4Byte BitMask);
u4Byte ODM_GetMACReg(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr, u4Byte BitMask);
void ODM_SetBBReg(PDM_ODM_T pDM_Odm, u4Byte RegAddr, u4Byte BitMask, u4Byte Data);
void ODM_SetBBReg(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr, u4Byte BitMask, u4Byte Data);
u4Byte ODM_GetBBReg(PDM_ODM_T pDM_Odm, u4Byte RegAddr, u4Byte BitMask);
u4Byte ODM_GetBBReg(struct odm_dm_struct *pDM_Odm, u4Byte RegAddr, u4Byte BitMask);
void ODM_SetRFReg(PDM_ODM_T pDM_Odm, ODM_RF_RADIO_PATH_E eRFPath, u4Byte RegAddr, u4Byte BitMask, u4Byte Data);
void ODM_SetRFReg(struct odm_dm_struct *pDM_Odm, enum ODM_RF_RADIO_PATH eRFPath, u4Byte RegAddr, u4Byte BitMask, u4Byte Data);
u4Byte ODM_GetRFReg(PDM_ODM_T pDM_Odm, ODM_RF_RADIO_PATH_E eRFPath, u4Byte RegAddr, u4Byte BitMask);
u4Byte ODM_GetRFReg(struct odm_dm_struct *pDM_Odm, enum ODM_RF_RADIO_PATH eRFPath, u4Byte RegAddr, u4Byte BitMask);
//
// Memory Relative Function.
//
void ODM_AllocateMemory(PDM_ODM_T pDM_Odm, void **pPtr, u4Byte length);
void ODM_FreeMemory(PDM_ODM_T pDM_Odm, void *pPtr, u4Byte length);
void ODM_AllocateMemory(struct odm_dm_struct *pDM_Odm, void **pPtr, u4Byte length);
void ODM_FreeMemory(struct odm_dm_struct *pDM_Odm, void *pPtr, u4Byte length);
s4Byte ODM_CompareMemory(PDM_ODM_T pDM_Odm, void *pBuf1, void *pBuf2, u4Byte length);
s4Byte ODM_CompareMemory(struct odm_dm_struct *pDM_Odm, void *pBuf1, void *pBuf2, u4Byte length);
//
// ODM MISC-spin lock relative API.
//
void ODM_AcquireSpinLock(PDM_ODM_T pDM_Odm, RT_SPINLOCK_TYPE type);
void ODM_AcquireSpinLock(struct odm_dm_struct *pDM_Odm, RT_SPINLOCK_TYPE type);
void ODM_ReleaseSpinLock(PDM_ODM_T pDM_Odm, RT_SPINLOCK_TYPE type);
void ODM_ReleaseSpinLock(struct odm_dm_struct *pDM_Odm, RT_SPINLOCK_TYPE type);
//
// ODM MISC-workitem relative API.
//
void ODM_InitializeWorkItem(PDM_ODM_T pDM_Odm, void *pRtWorkItem,
void ODM_InitializeWorkItem(struct odm_dm_struct *pDM_Odm, void *pRtWorkItem,
RT_WORKITEM_CALL_BACK RtWorkItemCallback,
void *pContext, const char *szID);
@ -152,13 +152,13 @@ void ODM_sleep_ms(u4Byte ms);
void ODM_sleep_us(u4Byte us);
void ODM_SetTimer(PDM_ODM_T pDM_Odm, PRT_TIMER pTimer, u4Byte msDelay);
void ODM_SetTimer(struct odm_dm_struct *pDM_Odm, PRT_TIMER pTimer, u4Byte msDelay);
void ODM_InitializeTimer(PDM_ODM_T pDM_Odm, PRT_TIMER pTimer, RT_TIMER_CALL_BACK CallBackFunc, void *pContext, const char *szID);
void ODM_InitializeTimer(struct odm_dm_struct *pDM_Odm, PRT_TIMER pTimer, RT_TIMER_CALL_BACK CallBackFunc, void *pContext, const char *szID);
void ODM_CancelTimer(PDM_ODM_T pDM_Odm, PRT_TIMER pTimer);
void ODM_CancelTimer(struct odm_dm_struct *pDM_Odm, PRT_TIMER pTimer);
void ODM_ReleaseTimer(PDM_ODM_T pDM_Odm, PRT_TIMER pTimer);
void ODM_ReleaseTimer(struct odm_dm_struct *pDM_Odm, PRT_TIMER pTimer);
//
// ODM FW relative API.

2
include/rtl8188e_hal.h
View file

@ -409,7 +409,7 @@ typedef struct hal_data_8188e
u8 RegCR_1;
struct dm_priv dmpriv;
DM_ODM_T odmpriv;
struct odm_dm_struct odmpriv;
struct sreset_priv srestpriv;
#ifdef CONFIG_BT_COEXIST

3
include/rtw_recv.h
View file

@ -101,8 +101,7 @@ struct signal_stat {
u32 total_val; //sum of valid elements
};
#define MAX_PATH_NUM_92CS 2
struct phy_info //ODM_PHY_INFO_T
{
struct phy_info {
u8 RxPWDBAll;
u8 SignalQuality; // in 0-100 index.
u8 RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; //EVM