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rtl8188eu: Remove more code dependent on DM_ODM_SUPPORT_TYPE
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
parent
3fc952a0d5
commit
f4cc4ed0a2
49 changed files with 123 additions and 17668 deletions
3
Makefile
3
Makefile
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@ -206,10 +206,7 @@ _OUTSRC_FILES := hal/phydm/phydm_debug.o \
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hal/phydm/phydm_cfotracking.o\
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hal/phydm/phydm_noisemonitor.o\
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hal/phydm/phydm_acs.o\
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hal/phydm/phydm_beamforming.o\
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hal/phydm/phydm_dfs.o\
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hal/phydm/txbf/halcomtxbf.o\
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hal/phydm/txbf/haltxbfinterface.o\
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hal/phydm/txbf/phydm_hal_txbf_api.o\
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hal/phydm/phydm_adc_sampling.o\
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hal/phydm/phydm_kfree.o\
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@ -66,50 +66,7 @@ static u8 RETRY_PENALTY_IDX[2][RATESIZE] = {{
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};
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#endif
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#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
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static u8 RETRY_PENALTY_IDX[2][RATESIZE] = {{
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4, 4, 4, 5, 4, 4, 5, 7, 7, 7, 8, 0x0a, /* SS>TH */
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#if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
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4, 4, 4, 4, 0x0d, 0x0d, 0x0f, 0x0f,
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#else
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4, 4, 4, 4, 6, 0x0a, 0x0b, 0x0d,
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#endif
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5, 5, 7, 7, 8, 0x0b, 0x0d, 0x0f
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}, /* 0329 R01 */
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{
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0x0a, 0x0a, 0x0a, 0x0a, 0x0c, 0x0c, 0x0e, 0x10, 0x11, 0x12, 0x12, 0x13, /* SS<TH */
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0x0e, 0x0f, 0x10, 0x10, 0x11, 0x14, 0x14, 0x15,
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9, 9, 9, 9, 0x0c, 0x0e, 0x11, 0x13
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}
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};
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static u8 RETRY_PENALTY_UP_IDX[RATESIZE] = {0x10, 0x10, 0x10, 0x10, 0x11, 0x11, 0x12, 0x12, 0x12, 0x13, 0x13, 0x14, /* SS>TH */
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0x13, 0x13, 0x14, 0x14, 0x15, 0x15, 0x15, 0x15,
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0x11, 0x11, 0x12, 0x13, 0x13, 0x13, 0x14, 0x15
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};
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static u8 RSSI_THRESHOLD[RATESIZE] = {0, 0, 0, 0,
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0, 0, 0, 0, 0, 0x24, 0x26, 0x2a,
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0x17, 0x1a, 0x1c, 0x1f, 0x23, 0x28, 0x2a, 0x2c,
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0, 0, 0, 0x1f, 0x23, 0x28, 0x2a, 0x2c
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};
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#else
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/* wilson modify */
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#if 0
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static u8 RETRY_PENALTY_IDX[2][RATESIZE] = {{
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4, 4, 4, 5, 4, 4, 5, 7, 7, 7, 8, 0x0a, /* SS>TH */
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4, 4, 4, 4, 6, 0x0a, 0x0b, 0x0d,
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5, 5, 7, 7, 8, 0x0b, 0x0d, 0x0f
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}, /* 0329 R01 */
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{
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0x0a, 0x0a, 0x0b, 0x0c, 0x0a, 0x0a, 0x0b, 0x0c, 0x0d, 0x10, 0x13, 0x14, /* SS<TH */
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0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x11, 0x13, 0x15,
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9, 9, 9, 9, 0x0c, 0x0e, 0x11, 0x13
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}
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};
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#endif
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static u8 RETRY_PENALTY_IDX[2][RATESIZE] = {{
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4, 4, 4, 5, 4, 4, 5, 7, 7, 7, 8, 0x0a, /* SS>TH */
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@ -134,20 +91,6 @@ static u8 RSSI_THRESHOLD[RATESIZE] = {0, 0, 0, 0,
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0, 0, 0, 0x1f, 0x23, 0x28, 0x2a, 0x2c
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};
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#endif
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/*static u8 RSSI_THRESHOLD[RATESIZE] = {0,0,0,0,
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0,0,0,0,0,0x24,0x26,0x2a,
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0x1a,0x1c,0x1e,0x21,0x24,0x2a,0x2b,0x2d,
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0,0,0,0x1f,0x23,0x28,0x2a,0x2c};*/
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/*static u16 N_THRESHOLD_HIGH[RATESIZE] = {4,4,8,16,
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24,36,48,72,96,144,192,216,
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60,80,100,160,240,400,560,640,
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300,320,480,720,1000,1200,1600,2000};
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static u16 N_THRESHOLD_LOW[RATESIZE] = {2,2,4,8,
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12,18,24,36,48,72,96,108,
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30,40,50,80,120,200,280,320,
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150,160,240,360,500,600,800,1000};*/
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static u16 N_THRESHOLD_HIGH[RATESIZE] = {4, 4, 8, 16,
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24, 36, 48, 72, 96, 144, 192, 216,
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60, 80, 100, 160, 240, 400, 600, 800,
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@ -201,73 +144,6 @@ static u16 dynamic_tx_rpt_timing[6] = {0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12, 0
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/* End rate adaptive parameters */
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \
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((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
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static int
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odm_ra_learn_bounding(
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struct PHY_DM_STRUCT *p_dm_odm,
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struct _odm_ra_info_ *p_ra_info
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)
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{
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ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, (" odm_ra_learn_bounding\n"));
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if (DM_RA_RATE_UP != p_ra_info->rate_direction) {
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/* Check if previous RA adjustment trend as +++--- or ++++----*/
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if (((3 == p_ra_info->rate_up_counter && p_ra_info->bounding_learning_time <= 10)
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|| (4 == p_ra_info->rate_up_counter && p_ra_info->bounding_learning_time <= 16))
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&& (p_ra_info->rate_up_counter == p_ra_info->rate_down_counter)) {
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if (1 != p_ra_info->bounding_type) {
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p_ra_info->bounding_type = 1;
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p_ra_info->bounding_counter = 0;
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}
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p_ra_info->bounding_counter++;
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/* Check if previous RA adjustment trend as ++--*/
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} else if ((2 == p_ra_info->rate_up_counter) && (p_ra_info->bounding_learning_time <= 7)
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&& (p_ra_info->rate_up_counter == p_ra_info->rate_down_counter)) {
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if (2 != p_ra_info->bounding_type) {
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p_ra_info->bounding_type = 2;
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p_ra_info->bounding_counter = 0;
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}
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p_ra_info->bounding_counter++;
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/* Check if previous RA adjustment trend as +++++-----*/
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} else if ((5 == p_ra_info->rate_up_counter) && (p_ra_info->bounding_learning_time <= 17)
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&& (p_ra_info->rate_up_counter == p_ra_info->rate_down_counter)) {
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if (3 != p_ra_info->bounding_type) {
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p_ra_info->bounding_type = 3;
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p_ra_info->bounding_counter = 0;
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}
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p_ra_info->bounding_counter++;
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} else
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p_ra_info->bounding_type = 0;
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p_ra_info->rate_down_counter = 0;
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p_ra_info->rate_up_counter = 0;
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p_ra_info->bounding_learning_time = 1;
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} else if (p_ra_info->bounding_type) {
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/* Check if RA adjustment trend as +++---++(+) or ++++----++(+)*/
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if ((1 == p_ra_info->bounding_type) && (1 == p_ra_info->bounding_counter)
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&& (2 == p_ra_info->rate_up_counter)) {
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p_ra_info->bounding_type = 0;
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if (p_ra_info->bounding_learning_time <= 5)
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return 1;
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/* Check if RA adjustment trend as ++--++--+(+)*/
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} else if ((2 == p_ra_info->bounding_type) && (2 == p_ra_info->bounding_counter)
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&& (1 == p_ra_info->rate_up_counter)) {
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p_ra_info->bounding_type = 0;
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if (p_ra_info->bounding_learning_time <= 2)
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return 1;
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/* Check if RA adjustment trend as +++++-----++(+)*/
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} else if ((3 == p_ra_info->bounding_type) && (1 == p_ra_info->bounding_counter)
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&& (2 == p_ra_info->rate_up_counter)) {
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p_ra_info->bounding_type = 0;
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if (p_ra_info->bounding_learning_time <= 4)
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return 1;
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}
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}
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return 0;
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}
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#endif
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static void
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odm_set_tx_rpt_timing_8188e(
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struct PHY_DM_STRUCT *p_dm_odm,
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@ -325,19 +201,6 @@ odm_rate_down_8188e(
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if (rate_id > 0) {
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for (i = rate_id - 1; i >= lowest_rate; i--) {
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if (p_ra_info->ra_use_rate & BIT(i)) {
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \
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((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
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p_ra_info->rate_down_counter++;
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p_ra_info->rate_direction = DM_RA_RATE_DOWN;
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/* Learning +(0)-(-)(-)+ and ++(0)--(-)(-)(0)+ after the persistence of learned TX rate expire*/
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if (0xFF == p_ra_info->rate_down_start_time) {
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if ((0 == p_ra_info->rate_up_counter) || (p_ra_info->rate_up_counter + 2 < p_ra_info->bounding_learning_time))
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p_ra_info->rate_down_start_time = 0;
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else
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p_ra_info->rate_down_start_time = p_ra_info->bounding_learning_time;
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}
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#endif
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rate_id = i;
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goto rate_down_finish;
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@ -347,36 +210,14 @@ odm_rate_down_8188e(
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} else if (rate_id <= lowest_rate)
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rate_id = lowest_rate;
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rate_down_finish:
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \
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((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
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/*if (p_ra_info->RTY[2] >= 100) {
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p_ra_info->ra_waiting_counter = 2;
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if (p_ra_info->ra_waiting_counter == 1) {
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p_ra_info->ra_waiting_counter += 1;
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p_ra_info->ra_pending_counter += 1;
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} else */if ((0 != p_ra_info->rate_down_start_time) && (0xFF != p_ra_info->rate_down_start_time)) {
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/* Learning +(0)-(-)(-)+ and ++(0)--(-)(-)(0)+ after the persistence of learned TX rate expire*/
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if (p_ra_info->rate_down_counter < p_ra_info->rate_up_counter) {
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} else if (p_ra_info->rate_down_counter == p_ra_info->rate_up_counter) {
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p_ra_info->ra_waiting_counter = 2;
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p_ra_info->ra_pending_counter += 1;
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} else if (p_ra_info->rate_down_counter <= p_ra_info->rate_up_counter + 2)
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rate_id = p_ra_info->pre_rate;
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else {
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p_ra_info->ra_waiting_counter = 0;
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p_ra_info->ra_pending_counter = 0;
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p_ra_info->rate_down_start_time = 0;
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}
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} else
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#endif
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if (p_ra_info->ra_waiting_counter == 1) {
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p_ra_info->ra_waiting_counter += 1;
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p_ra_info->ra_pending_counter += 1;
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} else if (p_ra_info->ra_waiting_counter == 0) {
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} else {
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p_ra_info->ra_waiting_counter = 0;
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p_ra_info->ra_pending_counter = 0;
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}
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} else if (p_ra_info->ra_waiting_counter == 0) {
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} else {
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p_ra_info->ra_waiting_counter = 0;
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p_ra_info->ra_pending_counter = 0;
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}
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if (p_ra_info->ra_pending_counter >= 4)
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p_ra_info->ra_pending_counter = 4;
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p_ra_info->ra_drop_after_down = 1;
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@ -413,10 +254,6 @@ odm_rate_up_8188e(
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p_ra_info->ra_pending_counter = 0;
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} else if (p_ra_info->ra_waiting_counter > 1) {
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p_ra_info->pre_rssi_sta_ra = p_ra_info->rssi_sta_ra;
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \
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((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
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p_ra_info->rate_down_start_time = 0;
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#endif
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goto rate_up_finish;
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}
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odm_set_tx_rpt_timing_8188e(p_dm_odm, p_ra_info, 0);
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@ -425,16 +262,6 @@ odm_rate_up_8188e(
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if (rate_id < highest_rate) {
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for (i = rate_id + 1; i <= highest_rate; i++) {
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if (p_ra_info->ra_use_rate & BIT(i)) {
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \
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((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
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if (odm_ra_learn_bounding(p_dm_odm, p_ra_info)) {
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p_ra_info->ra_waiting_counter = 2;
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p_ra_info->ra_pending_counter = 1;
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goto rate_up_finish;
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}
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p_ra_info->rate_up_counter++;
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p_ra_info->rate_direction = DM_RA_RATE_UP;
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#endif
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rate_id = i;
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goto rate_up_finish;
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}
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@ -451,15 +278,6 @@ rate_up_finish:
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/* if(p_ra_info->ra_waiting_counter==10) */
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if (p_ra_info->ra_waiting_counter == (4 + pending_for_rate_up_fail[p_ra_info->ra_pending_counter])) {
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p_ra_info->ra_waiting_counter = 0;
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \
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((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
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/* Mark persistence expiration state*/
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p_ra_info->rate_down_start_time = 0xFF;
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/* Clear state to avoid wrong bounding check*/
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p_ra_info->rate_down_counter = 0;
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p_ra_info->rate_up_counter = 0;
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p_ra_info->rate_direction = 0;
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#endif
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} else
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p_ra_info->ra_waiting_counter++;
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@ -491,35 +309,17 @@ odm_rate_decision_8188e(
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ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_rate_decision_8188e()\n"));
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if (p_ra_info->active && (p_ra_info->TOTAL > 0)) { /* STA used and data packet exits */
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \
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((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
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if (((p_ra_info->rssi_sta_ra <= 17) && (p_ra_info->rssi_sta_ra > p_ra_info->pre_rssi_sta_ra))
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|| ((p_ra_info->pre_rssi_sta_ra <= 17) && (p_ra_info->pre_rssi_sta_ra > p_ra_info->rssi_sta_ra))) {
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/* don't reset state in low signal due to the power different between CCK and MCS is large.*/
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} else
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#endif
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if (p_ra_info->ra_drop_after_down) {
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p_ra_info->ra_drop_after_down--;
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odm_reset_ra_counter_8188e(p_ra_info);
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return;
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}
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if (p_ra_info->ra_drop_after_down) {
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p_ra_info->ra_drop_after_down--;
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odm_reset_ra_counter_8188e(p_ra_info);
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return;
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}
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if ((p_ra_info->rssi_sta_ra < (p_ra_info->pre_rssi_sta_ra - 3)) || (p_ra_info->rssi_sta_ra > (p_ra_info->pre_rssi_sta_ra + 3))) {
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p_ra_info->pre_rssi_sta_ra = p_ra_info->rssi_sta_ra;
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p_ra_info->ra_waiting_counter = 0;
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p_ra_info->ra_pending_counter = 0;
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \
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((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
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p_ra_info->bounding_type = 0;
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#endif
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}
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#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
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if (0xff != p_dm_odm->priv->pshare->rf_ft_var.txforce) {
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p_ra_info->pre_rate = p_dm_odm->priv->pshare->rf_ft_var.txforce;
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odm_reset_ra_counter_8188e(p_ra_info);
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}
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#endif
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/* Start RA decision */
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if (p_ra_info->pre_rate > p_ra_info->highest_rate)
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rate_id = p_ra_info->highest_rate;
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@ -567,21 +367,11 @@ odm_rate_decision_8188e(
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ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE | ODM_COMP_INIT, ODM_DBG_LOUD,
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(" RssiStaRa= %d rty_pt_id=%d penalty_id1=0x%x penalty_id2=0x%x rate_id=%d nsc_down=%d nsc_up=%d SGI=%d\n",
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p_ra_info->rssi_sta_ra, rty_pt_id, penalty_id1, penalty_id2, rate_id, p_ra_info->nsc_down, p_ra_info->nsc_up, p_ra_info->rate_sgi));
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \
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((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
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if (0xFF != p_ra_info->bounding_learning_time)
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p_ra_info->bounding_learning_time++;
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#endif
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if ((p_ra_info->nsc_down < N_THRESHOLD_LOW[rate_id]) || (p_ra_info->DROP > DROPING_NECESSARY[rate_id]))
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odm_rate_down_8188e(p_dm_odm, p_ra_info);
|
||||
/* else if ((p_ra_info->nsc_up > N_THRESHOLD_HIGH[rate_id])&&(pool_retry<POOL_RETRY_TH[rate_id])) */
|
||||
else if (p_ra_info->nsc_up > N_THRESHOLD_HIGH[rate_id])
|
||||
odm_rate_up_8188e(p_dm_odm, p_ra_info);
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \
|
||||
((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
|
||||
else if ((p_ra_info->RTY[2] >= 100) && (ODM_BW20M == *p_dm_odm->p_band_width))
|
||||
odm_rate_down_8188e(p_dm_odm, p_ra_info);
|
||||
#endif
|
||||
|
||||
if ((p_ra_info->decision_rate) == (p_ra_info->pre_rate))
|
||||
dynamic_tx_rpt_timing_counter += 1;
|
||||
|
@ -748,7 +538,6 @@ odm_pt_try_state_8188e(
|
|||
}
|
||||
p_ra_info->pt_pre_rate = p_ra_info->decision_rate;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
/* Disable power training when noisy environment */
|
||||
if (p_dm_odm->is_disable_power_training) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_pt_try_state_8188e(): Disable power training when noisy environment\n"));
|
||||
|
@ -756,7 +545,6 @@ odm_pt_try_state_8188e(
|
|||
p_ra_info->ra_stage = 0;
|
||||
p_ra_info->pt_stop_count = 0;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static void
|
||||
|
@ -813,11 +601,7 @@ odm_ra_tx_rpt_timer_setting(
|
|||
if (p_dm_odm->currmin_rpt_time != min_rpt_time) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD,
|
||||
(" currmin_rpt_time =0x%04x min_rpt_time=0x%04x\n", p_dm_odm->currmin_rpt_time, min_rpt_time));
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP))
|
||||
odm_ra_set_tx_rpt_time(p_dm_odm, min_rpt_time);
|
||||
#else
|
||||
rtw_rpt_timer_cfg_cmd(p_dm_odm->adapter, min_rpt_time);
|
||||
#endif
|
||||
p_dm_odm->currmin_rpt_time = min_rpt_time;
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, (" <=====odm_ra_tx_rpt_timer_setting()\n"));
|
||||
|
@ -906,16 +690,6 @@ odm_ra_info_init(
|
|||
p_ra_info->pt_pre_rssi = 0;
|
||||
p_ra_info->pt_mode_ss = 0;
|
||||
p_ra_info->ra_stage = 0;
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \
|
||||
((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
|
||||
p_ra_info->rate_down_counter = 0;
|
||||
p_ra_info->rate_up_counter = 0;
|
||||
p_ra_info->rate_direction = 0;
|
||||
p_ra_info->bounding_type = 0;
|
||||
p_ra_info->bounding_counter = 0;
|
||||
p_ra_info->bounding_learning_time = 0;
|
||||
p_ra_info->rate_down_start_time = 0;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
@ -935,8 +709,6 @@ odm_ra_info_init_all(
|
|||
|
||||
/* Redifine arrays for I-cut NIC */
|
||||
if (p_dm_odm->cut_version == ODM_CUT_I) {
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
|
||||
u8 i;
|
||||
u8 RETRY_PENALTY_IDX_S[2][RATESIZE] = {{
|
||||
4, 4, 4, 5,
|
||||
|
@ -965,79 +737,10 @@ odm_ra_info_init_all(
|
|||
RETRY_PENALTY_UP_IDX[i] = RETRY_PENALTY_UP_IDX_S[i];
|
||||
}
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)/* This is for non-I-cut */
|
||||
{
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
|
||||
/* dbg_print("adapter->mgnt_info.reg_ra_lvl = %d\n", adapter->mgnt_info.reg_ra_lvl); */
|
||||
|
||||
/* */
|
||||
/* 2012/09/14 MH Add for different Ra pattern init. For TPLINK case, we */
|
||||
/* need to to adjust different RA pattern for middle range RA. 20-30dB degarde */
|
||||
/* 88E rate adptve will raise too slow. */
|
||||
/* */
|
||||
if (adapter->MgntInfo.RegRALvl == 0) {
|
||||
RETRY_PENALTY_UP_IDX[11] = 0x14;
|
||||
|
||||
RETRY_PENALTY_UP_IDX[17] = 0x13;
|
||||
RETRY_PENALTY_UP_IDX[18] = 0x14;
|
||||
RETRY_PENALTY_UP_IDX[19] = 0x15;
|
||||
|
||||
RETRY_PENALTY_UP_IDX[23] = 0x13;
|
||||
RETRY_PENALTY_UP_IDX[24] = 0x13;
|
||||
RETRY_PENALTY_UP_IDX[25] = 0x13;
|
||||
RETRY_PENALTY_UP_IDX[26] = 0x14;
|
||||
RETRY_PENALTY_UP_IDX[27] = 0x15;
|
||||
} else if (adapter->MgntInfo.RegRALvl == 1) {
|
||||
RETRY_PENALTY_UP_IDX[17] = 0x13;
|
||||
RETRY_PENALTY_UP_IDX[18] = 0x13;
|
||||
RETRY_PENALTY_UP_IDX[19] = 0x14;
|
||||
|
||||
RETRY_PENALTY_UP_IDX[23] = 0x12;
|
||||
RETRY_PENALTY_UP_IDX[24] = 0x13;
|
||||
RETRY_PENALTY_UP_IDX[25] = 0x13;
|
||||
RETRY_PENALTY_UP_IDX[26] = 0x13;
|
||||
RETRY_PENALTY_UP_IDX[27] = 0x14;
|
||||
} else if (adapter->MgntInfo.RegRALvl == 2) {
|
||||
/* Compile flag default is lvl2, we need not to update. */
|
||||
} else if (adapter->MgntInfo.RegRALvl >= 0x80) {
|
||||
u8 index = 0, offset = adapter->MgntInfo.RegRALvl - 0x80;
|
||||
|
||||
/* Reset to default rate adaptive value. */
|
||||
RETRY_PENALTY_UP_IDX[11] = 0x14;
|
||||
|
||||
RETRY_PENALTY_UP_IDX[17] = 0x13;
|
||||
RETRY_PENALTY_UP_IDX[18] = 0x14;
|
||||
RETRY_PENALTY_UP_IDX[19] = 0x15;
|
||||
|
||||
RETRY_PENALTY_UP_IDX[23] = 0x13;
|
||||
RETRY_PENALTY_UP_IDX[24] = 0x13;
|
||||
RETRY_PENALTY_UP_IDX[25] = 0x13;
|
||||
RETRY_PENALTY_UP_IDX[26] = 0x14;
|
||||
RETRY_PENALTY_UP_IDX[27] = 0x15;
|
||||
|
||||
if (adapter->MgntInfo.RegRALvl >= 0x90) {
|
||||
offset = adapter->MgntInfo.RegRALvl - 0x90;
|
||||
/* Lazy mode. */
|
||||
for (index = 0; index < 28; index++)
|
||||
RETRY_PENALTY_UP_IDX[index] += (offset);
|
||||
} else {
|
||||
/* Aggrasive side. */
|
||||
for (index = 0; index < 28; index++)
|
||||
RETRY_PENALTY_UP_IDX[index] -= (offset);
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
u8
|
||||
odm_ra_get_sgi_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
|
@ -1140,14 +843,7 @@ odm_ra_set_tx_rpt_time(
|
|||
u16 min_rpt_time
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
if (min_rpt_time != 0xffff) {
|
||||
notify_tx_report_interval_change(p_dm_odm->priv, min_rpt_time);
|
||||
}
|
||||
#else
|
||||
odm_write_2byte(p_dm_odm, REG_TX_RPT_TIME, min_rpt_time);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
void odm_ra_tx_rpt2_handle_8188e(struct PHY_DM_STRUCT *p_dm_odm,
|
||||
|
|
|
@ -16,95 +16,50 @@ Major Change History:
|
|||
--*/
|
||||
|
||||
/* rate adaptive define */
|
||||
#define PERENTRY 23
|
||||
#define RETRYSIZE 5
|
||||
#define RATESIZE 28
|
||||
#define PERENTRY 23
|
||||
#define RETRYSIZE 5
|
||||
#define RATESIZE 28
|
||||
#define TX_RPT2_ITEM_SIZE 8
|
||||
|
||||
#define DM_RA_RATE_UP 1
|
||||
#define DM_RA_RATE_DOWN 2
|
||||
#define DM_RA_RATE_UP 1
|
||||
#define DM_RA_RATE_DOWN 2
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
|
||||
/*
|
||||
* TX report 2 format in Rx desc
|
||||
* */
|
||||
#define GET_TX_RPT2_DESC_PKT_LEN_88E(__prx_status_desc) LE_BITS_TO_4BYTE(__prx_status_desc, 0, 9)
|
||||
#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__prx_status_desc) LE_BITS_TO_4BYTE(__prx_status_desc+16, 0, 32)
|
||||
#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__prx_status_desc) LE_BITS_TO_4BYTE(__prx_status_desc+20, 0, 32)
|
||||
/* TX report 2 format in Rx desc */
|
||||
#define GET_TX_RPT2_DESC_PKT_LEN_88E(__prx_status_desc) \
|
||||
LE_BITS_TO_4BYTE(__prx_status_desc, 0, 9)
|
||||
#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__prx_status_desc) \
|
||||
LE_BITS_TO_4BYTE(__prx_status_desc+16, 0, 32)
|
||||
#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__prx_status_desc) \
|
||||
LE_BITS_TO_4BYTE(__prx_status_desc+20, 0, 32)
|
||||
|
||||
#define GET_TX_REPORT_TYPE1_RERTY_0(__paddr) LE_BITS_TO_4BYTE(__paddr, 0, 16)
|
||||
#define GET_TX_REPORT_TYPE1_RERTY_1(__paddr) LE_BITS_TO_1BYTE(__paddr+2, 0, 8)
|
||||
#define GET_TX_REPORT_TYPE1_RERTY_2(__paddr) LE_BITS_TO_1BYTE(__paddr+3, 0, 8)
|
||||
#define GET_TX_REPORT_TYPE1_RERTY_3(__paddr) LE_BITS_TO_1BYTE(__paddr+4, 0, 8)
|
||||
#define GET_TX_REPORT_TYPE1_RERTY_4(__paddr) LE_BITS_TO_1BYTE(__paddr+4+1, 0, 8)
|
||||
#define GET_TX_REPORT_TYPE1_DROP_0(__paddr) LE_BITS_TO_1BYTE(__paddr+4+2, 0, 8)
|
||||
#define GET_TX_REPORT_TYPE1_DROP_1(__paddr) LE_BITS_TO_1BYTE(__paddr+4+3, 0, 8)
|
||||
#endif
|
||||
#define GET_TX_REPORT_TYPE1_RERTY_0(__paddr) \
|
||||
LE_BITS_TO_4BYTE(__paddr, 0, 16)
|
||||
#define GET_TX_REPORT_TYPE1_RERTY_1(__paddr) \
|
||||
LE_BITS_TO_1BYTE(__paddr+2, 0, 8)
|
||||
#define GET_TX_REPORT_TYPE1_RERTY_2(__paddr) \
|
||||
LE_BITS_TO_1BYTE(__paddr+3, 0, 8)
|
||||
#define GET_TX_REPORT_TYPE1_RERTY_3(__paddr) \
|
||||
LE_BITS_TO_1BYTE(__paddr+4, 0, 8)
|
||||
#define GET_TX_REPORT_TYPE1_RERTY_4(__paddr) \
|
||||
LE_BITS_TO_1BYTE(__paddr+4+1, 0, 8)
|
||||
#define GET_TX_REPORT_TYPE1_DROP_0(__paddr) \
|
||||
LE_BITS_TO_1BYTE(__paddr+4+2, 0, 8)
|
||||
#define GET_TX_REPORT_TYPE1_DROP_1(__paddr) \
|
||||
LE_BITS_TO_1BYTE(__paddr+4+3, 0, 8)
|
||||
|
||||
/* End rate adaptive define */
|
||||
|
||||
void
|
||||
odm_ra_support_init(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
void odm_ra_support_init(struct PHY_DM_STRUCT *p_dm_odm);
|
||||
int odm_ra_info_init_all(struct PHY_DM_STRUCT *p_dm_odm);
|
||||
int odm_ra_info_init(struct PHY_DM_STRUCT *p_dm_odm, u32 mac_id);
|
||||
u8 odm_ra_get_sgi_8188e(struct PHY_DM_STRUCT *p_dm_odm, u8 mac_id);
|
||||
u8 odm_ra_get_decision_rate_8188e(struct PHY_DM_STRUCT *p_dm_odm, u8 mac_id);
|
||||
u8 odm_ra_get_hw_pwr_status_8188e(struct PHY_DM_STRUCT *p_dm_odm, u8 mac_id);
|
||||
void odm_ra_update_rate_info_8188e(struct PHY_DM_STRUCT *p_dm_odm, u8 mac_id,
|
||||
u8 rate_id, u32 rate_mask, u8 sgi_enable);
|
||||
void odm_ra_set_rssi_8188e(struct PHY_DM_STRUCT *p_dm_odm, u8 mac_id, u8 rssi);
|
||||
void odm_ra_tx_rpt2_handle_8188e(struct PHY_DM_STRUCT *p_dm_odm, u8 *tx_rpt_buf,
|
||||
__le16 tx_rpt_len, u32 mac_id_valid_entry0, u32 mac_id_valid_entry1);
|
||||
void odm_ra_set_tx_rpt_time(struct PHY_DM_STRUCT *p_dm_odm, u16 min_rpt_time);
|
||||
|
||||
int
|
||||
odm_ra_info_init_all(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
int
|
||||
odm_ra_info_init(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 mac_id
|
||||
);
|
||||
|
||||
u8
|
||||
odm_ra_get_sgi_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 mac_id
|
||||
);
|
||||
|
||||
u8
|
||||
odm_ra_get_decision_rate_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 mac_id
|
||||
);
|
||||
|
||||
u8
|
||||
odm_ra_get_hw_pwr_status_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 mac_id
|
||||
);
|
||||
void
|
||||
odm_ra_update_rate_info_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 mac_id,
|
||||
u8 rate_id,
|
||||
u32 rate_mask,
|
||||
u8 sgi_enable
|
||||
);
|
||||
|
||||
void
|
||||
odm_ra_set_rssi_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 mac_id,
|
||||
u8 rssi
|
||||
);
|
||||
|
||||
void
|
||||
odm_ra_tx_rpt2_handle_8188e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 *tx_rpt_buf,
|
||||
__le16 tx_rpt_len,
|
||||
u32 mac_id_valid_entry0,
|
||||
u32 mac_id_valid_entry1
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
odm_ra_set_tx_rpt_time(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u16 min_rpt_time
|
||||
);
|
||||
#endif
|
||||
|
|
|
@ -1729,14 +1729,6 @@ odm_read_and_config_mp_8188e_phy_reg_pg(
|
|||
u32 array_len = sizeof(array_mp_8188e_phy_reg_pg) / sizeof(u32);
|
||||
u32 *array = array_mp_8188e_phy_reg_pg;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
|
||||
PlatformZeroMemory(p_hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT);
|
||||
p_hal_data->nLinesReadPwrByRate = array_len / 6;
|
||||
#endif
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8188e_phy_reg_pg\n"));
|
||||
|
||||
p_dm_odm->phy_reg_pg_version = 1;
|
||||
|
@ -1751,14 +1743,7 @@ odm_read_and_config_mp_8188e_phy_reg_pg(
|
|||
u32 v6 = array[i + 5];
|
||||
|
||||
odm_config_bb_phy_reg_pg_8188e(p_dm_odm, v1, v2, v3, v4, v5, v6);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
rsprintf((char *)p_hal_data->BufOfLinesPwrByRate[i / 6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,",
|
||||
(v1 == 0 ? "2.4G" : " 5G"), (v2 == 0 ? "A" : "B"), (v3 == 0 ? "1Tx" : "2Tx"), v4, v5, v6);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
#endif /* end of HWIMG_SUPPORT*/
|
||||
|
|
|
@ -113,43 +113,13 @@ void do_iqk_8188e(
|
|||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
#endif
|
||||
|
||||
odm_reset_iqk_result(p_dm_odm);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
|
||||
#if USE_WORKITEM
|
||||
platform_acquire_mutex(&p_hal_data->mx_chnl_bw_control);
|
||||
#else
|
||||
platform_acquire_spin_lock(adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK);
|
||||
#endif
|
||||
#elif ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
|
||||
platform_acquire_mutex(&p_hal_data->mx_chnl_bw_control);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
p_dm_odm->rf_calibrate_info.thermal_value_iqk = thermal_value;
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
phy_iq_calibrate_8188e(p_dm_odm, false);
|
||||
#else
|
||||
phy_iq_calibrate_8188e(adapter, false);
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
|
||||
#if USE_WORKITEM
|
||||
platform_release_mutex(&p_hal_data->mx_chnl_bw_control);
|
||||
#else
|
||||
platform_release_spin_lock(adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK);
|
||||
#endif
|
||||
#elif ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
|
||||
platform_release_mutex(&p_hal_data->mx_chnl_bw_control);
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
|
@ -189,30 +159,16 @@ odm_tx_pwr_track_set_pwr88_e(
|
|||
struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
|
||||
|
||||
if (p_dm_odm->mp_mode == true) {
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
#if (MP_DRIVER == 1)
|
||||
PMPT_CONTEXT p_mpt_ctx = &(adapter->mpt_ctx);
|
||||
|
||||
tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
|
||||
#endif
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
|
||||
|
||||
tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
|
||||
#endif
|
||||
#endif
|
||||
} else {
|
||||
u16 rate = *(p_dm_odm->p_forced_data_rate);
|
||||
|
||||
if (!rate) { /*auto rate*/
|
||||
if (rate != 0xFF) {
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(p_dm_odm->tx_rate);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
if (p_dm_odm->number_linked_client != 0)
|
||||
tx_rate = hw_rate_to_m_rate(p_dm_odm->tx_rate);
|
||||
#endif
|
||||
}
|
||||
} else /*force rate*/
|
||||
tx_rate = (u8)rate;
|
||||
|
@ -252,8 +208,6 @@ odm_tx_pwr_track_set_pwr88_e(
|
|||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr88E CH=%d\n", *(p_dm_odm->p_channel)));
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
|
||||
if (p_dm_odm->mp_mode == true) {
|
||||
pwr = phy_query_bb_reg(adapter, REG_TX_AGC_A_RATE18_06, 0xFF);
|
||||
pwr += p_dm_odm->rf_calibrate_info.power_index_offset[ODM_RF_PATH_A];
|
||||
|
@ -283,13 +237,6 @@ odm_tx_pwr_track_set_pwr88_e(
|
|||
phy_set_tx_power_index_by_rate_section(adapter, ODM_RF_PATH_A, *p_dm_odm->p_channel, HT_MCS0_MCS7);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
/* phy_rf6052_set_cck_tx_power(p_dm_odm->priv, *(p_dm_odm->p_channel)); */
|
||||
/* phy_rf6052_set_ofdm_tx_power(p_dm_odm->priv, *(p_dm_odm->p_channel)); */
|
||||
#endif
|
||||
|
||||
} else if (method == BBSWING) {
|
||||
final_ofdm_swing_index = p_rf_calibrate_info->default_ofdm_index + p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path];
|
||||
final_cck_swing_index = p_rf_calibrate_info->default_cck_index + p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path];
|
||||
|
@ -495,30 +442,16 @@ get_delta_swing_table_8188e(
|
|||
u8 channel = *p_dm_odm->p_channel;
|
||||
|
||||
if (p_dm_odm->mp_mode == true) {
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
#if (MP_DRIVER == 1)
|
||||
PMPT_CONTEXT p_mpt_ctx = &(adapter->mpt_ctx);
|
||||
|
||||
tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
|
||||
#endif
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
|
||||
|
||||
tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
|
||||
#endif
|
||||
#endif
|
||||
} else {
|
||||
u16 rate = *(p_dm_odm->p_forced_data_rate);
|
||||
|
||||
if (!rate) { /*auto rate*/
|
||||
if (rate != 0xFF) {
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(p_dm_odm->tx_rate);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
if (p_dm_odm->number_linked_client != 0)
|
||||
tx_rate = hw_rate_to_m_rate(p_dm_odm->tx_rate);
|
||||
#endif
|
||||
}
|
||||
} else /*force rate*/
|
||||
tx_rate = (u8)rate;
|
||||
|
|
|
@ -60,14 +60,9 @@ odm_tx_pwr_track_set_pwr88_e(
|
|||
|
||||
void
|
||||
phy_iq_calibrate_8188e(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#else
|
||||
struct _ADAPTER *adapter,
|
||||
#endif
|
||||
bool is_recovery);
|
||||
|
||||
|
||||
/*
|
||||
* LC calibrate
|
||||
* */
|
||||
|
@ -75,19 +70,6 @@ void
|
|||
phy_lc_calibrate_8188e(
|
||||
void *p_dm_void
|
||||
);
|
||||
#if 0
|
||||
/*
|
||||
* AP calibrate
|
||||
* */
|
||||
void
|
||||
phy_ap_calibrate_8188e(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#else
|
||||
struct _ADAPTER *p_adapter,
|
||||
#endif
|
||||
s8 delta);
|
||||
#endif
|
||||
|
||||
void
|
||||
phy_digital_predistortion_8188e(struct _ADAPTER *p_adapter);
|
||||
|
@ -95,11 +77,7 @@ phy_digital_predistortion_8188e(struct _ADAPTER *p_adapter);
|
|||
|
||||
void
|
||||
_phy_save_adda_registers(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#else
|
||||
struct _ADAPTER *p_adapter,
|
||||
#endif
|
||||
u32 *adda_reg,
|
||||
u32 *adda_backup,
|
||||
u32 register_num
|
||||
|
@ -107,11 +85,7 @@ _phy_save_adda_registers(
|
|||
|
||||
void
|
||||
_phy_path_adda_on(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#else
|
||||
struct _ADAPTER *p_adapter,
|
||||
#endif
|
||||
u32 *adda_reg,
|
||||
bool is_path_a_on,
|
||||
bool is2T
|
||||
|
@ -119,11 +93,7 @@ _phy_path_adda_on(
|
|||
|
||||
void
|
||||
_phy_mac_setting_calibration(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
#else
|
||||
struct _ADAPTER *p_adapter,
|
||||
#endif
|
||||
u32 *mac_reg,
|
||||
u32 *mac_backup
|
||||
);
|
||||
|
@ -131,11 +101,7 @@ _phy_mac_setting_calibration(
|
|||
|
||||
void
|
||||
_phy_path_a_stand_by(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
#else
|
||||
struct _ADAPTER *p_adapter
|
||||
#endif
|
||||
);
|
||||
|
||||
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -22,17 +22,6 @@
|
|||
#define __HAL_PHY_RF_H__
|
||||
|
||||
#include "phydm_powertracking_ap.h"
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
#include "rtl8814a/phydm_iqk_8814a.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
#include "rtl8822b/phydm_iqk_8822b.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8821C_SUPPORT == 1)
|
||||
#include "rtl8822b/phydm_iqk_8821c.h"
|
||||
#endif
|
||||
|
||||
enum pwrtrack_method {
|
||||
BBSWING,
|
||||
|
@ -75,52 +64,25 @@ configure_txpower_track(
|
|||
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
void *p_dm_void
|
||||
#else
|
||||
struct _ADAPTER *adapter
|
||||
#endif
|
||||
);
|
||||
|
||||
#if (RTL8192E_SUPPORT == 1)
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter_92e(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
void *p_dm_void
|
||||
#else
|
||||
struct _ADAPTER *adapter
|
||||
#endif
|
||||
);
|
||||
#endif
|
||||
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter_jaguar_series2(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
void *p_dm_void
|
||||
#else
|
||||
struct _ADAPTER *adapter
|
||||
#endif
|
||||
);
|
||||
|
||||
#elif ODM_IC_11AC_SERIES_SUPPORT
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter_jaguar_series(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
void *p_dm_void
|
||||
#else
|
||||
struct _ADAPTER *adapter
|
||||
#endif
|
||||
);
|
||||
|
||||
#elif (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter_jaguar_series3(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
void *p_dm_void
|
||||
#else
|
||||
struct _ADAPTER *adapter
|
||||
#endif
|
||||
);
|
||||
|
||||
#endif
|
||||
|
@ -128,41 +90,8 @@ odm_txpowertracking_callback_thermal_meter_jaguar_series3(
|
|||
#define IS_CCK_RATE(_rate) (ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M)
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
#define MAX_TOLERANCE 5
|
||||
#define IQK_DELAY_TIME 1 /* ms */
|
||||
|
||||
/*
|
||||
* BB/MAC/RF other monitor API
|
||||
* */
|
||||
|
||||
void phy_set_monitor_mode8192c(struct _ADAPTER *p_adapter,
|
||||
bool is_enable_monitor_mode);
|
||||
|
||||
/*
|
||||
* IQ calibrate
|
||||
* */
|
||||
void
|
||||
phy_iq_calibrate_8192c(struct _ADAPTER *p_adapter,
|
||||
bool is_recovery);
|
||||
|
||||
/*
|
||||
* LC calibrate
|
||||
* */
|
||||
void
|
||||
phy_lc_calibrate_8192c(struct _ADAPTER *p_adapter);
|
||||
|
||||
/*
|
||||
* AP calibrate
|
||||
* */
|
||||
void
|
||||
phy_ap_calibrate_8192c(struct _ADAPTER *p_adapter,
|
||||
s8 delta);
|
||||
#endif
|
||||
|
||||
#define ODM_TARGET_CHNL_NUM_2G_5G 59
|
||||
|
||||
|
||||
void
|
||||
odm_reset_iqk_result(
|
||||
void *p_dm_void
|
||||
|
|
|
@ -144,37 +144,22 @@ odm_clear_txpowertracking_state(
|
|||
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
#else
|
||||
struct _ADAPTER *adapter
|
||||
#endif
|
||||
)
|
||||
{
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
|
||||
|
||||
u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
|
||||
s8 diff_DPK[4] = {0};
|
||||
u8 thermal_value_avg_count = 0;
|
||||
u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
|
||||
|
||||
u8 OFDM_min_index = 0; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
|
||||
u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(p_hal_data->current_channel) */
|
||||
u8 power_tracking_type = p_hal_data->rf_power_tracking_type;
|
||||
u8 xtal_offset_eanble = 0;
|
||||
|
||||
struct _TXPWRTRACK_CFG c;
|
||||
|
||||
/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
|
||||
u8 *delta_swing_table_idx_tup_a = NULL;
|
||||
u8 *delta_swing_table_idx_tdown_a = NULL;
|
||||
|
@ -209,14 +194,8 @@ odm_txpowertracking_callback_thermal_meter(
|
|||
/*p_rf_calibrate_info->txpowertrack_control = p_hal_data->txpowertrack_control;
|
||||
<Kordan> We should keep updating the control variable according to HalData.
|
||||
<Kordan> rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
#if (MP_DRIVER == 1)
|
||||
p_rf_calibrate_info->rega24 = 0x090e1317;
|
||||
#endif
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
if (p_dm_odm->mp_mode == true)
|
||||
p_rf_calibrate_info->rega24 = 0x090e1317;
|
||||
#endif
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("===>odm_txpowertracking_callback_thermal_meter\n p_rf_calibrate_info->bb_swing_idx_cck_base: %d, p_rf_calibrate_info->bb_swing_idx_ofdm_base[A]: %d, p_rf_calibrate_info->default_ofdm_index: %d\n",
|
||||
|
@ -316,22 +295,13 @@ odm_txpowertracking_callback_thermal_meter(
|
|||
|
||||
if (delta > 0 && p_rf_calibrate_info->txpowertrack_control) {
|
||||
/* "delta" here is used to record the absolute value of differrence. */
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
delta = thermal_value > p_hal_data->eeprom_thermal_meter ? (thermal_value - p_hal_data->eeprom_thermal_meter) : (p_hal_data->eeprom_thermal_meter - thermal_value);
|
||||
#else
|
||||
delta = (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - p_dm_odm->priv->pmib->dot11RFEntry.ther) : (p_dm_odm->priv->pmib->dot11RFEntry.ther - thermal_value);
|
||||
#endif
|
||||
if (delta >= TXPWR_TRACK_TABLE_SIZE)
|
||||
delta = TXPWR_TRACK_TABLE_SIZE - 1;
|
||||
|
||||
/*4 7.1 The Final Power index = BaseIndex + power_index_offset*/
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
if (thermal_value > p_hal_data->eeprom_thermal_meter) {
|
||||
#else
|
||||
if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) {
|
||||
#endif
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
p_rf_calibrate_info->delta_power_index_last[p] = p_rf_calibrate_info->delta_power_index[p]; /*recording poer index offset*/
|
||||
switch (p) {
|
||||
|
@ -556,12 +526,7 @@ odm_txpowertracking_callback_thermal_meter(
|
|||
}
|
||||
}
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
if (thermal_value > p_hal_data->eeprom_thermal_meter)
|
||||
#else
|
||||
if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther)
|
||||
#endif
|
||||
{
|
||||
if (thermal_value > p_hal_data->eeprom_thermal_meter) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature(%d) higher than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter));
|
||||
|
||||
|
@ -616,11 +581,7 @@ odm_txpowertracking_callback_thermal_meter(
|
|||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter Xtal Tracking**********\n"));
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
if (thermal_value > p_hal_data->eeprom_thermal_meter) {
|
||||
#else
|
||||
if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) {
|
||||
#endif
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature(%d) higher than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter));
|
||||
(*c.odm_txxtaltrack_set_xtal)(p_dm_odm);
|
||||
|
@ -632,9 +593,6 @@ odm_txpowertracking_callback_thermal_meter(
|
|||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********End Xtal Tracking**********\n"));
|
||||
}
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
|
||||
if (!IS_HARDWARE_TYPE_8723B(adapter)) {
|
||||
/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
|
||||
if (delta_IQK >= c.threshold_iqk) {
|
||||
|
@ -678,8 +636,6 @@ odm_txpowertracking_callback_thermal_meter(
|
|||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===odm_txpowertracking_callback_thermal_meter\n"));
|
||||
|
||||
p_rf_calibrate_info->tx_powercount = 0;
|
||||
|
@ -698,7 +654,6 @@ odm_reset_iqk_result(
|
|||
{
|
||||
return;
|
||||
}
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
|
||||
{
|
||||
u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
|
||||
|
@ -716,24 +671,13 @@ u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
|
|||
return 0;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
static void
|
||||
odm_iq_calibrate(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
)
|
||||
static void odm_iq_calibrate(struct PHY_DM_STRUCT *p_dm_odm)
|
||||
{
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
if (*p_dm_odm->p_is_fcs_mode_enable)
|
||||
return;
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
|
||||
if (IS_HARDWARE_TYPE_8812AU(adapter))
|
||||
return;
|
||||
#endif
|
||||
|
||||
if (p_dm_odm->is_linked) {
|
||||
if ((*p_dm_odm->p_channel != p_dm_odm->pre_channel) && (!*p_dm_odm->p_is_scan_in_process)) {
|
||||
|
@ -775,25 +719,14 @@ void phydm_rf_init(void *p_dm_void)
|
|||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
odm_txpowertracking_init(p_dm_odm);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
odm_clear_txpowertracking_state(p_dm_odm);
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
phy_iq_calibrate_8814a_init(p_dm_odm);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
void phydm_rf_watchdog(void *p_dm_void)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
|
||||
odm_txpowertracking_check(p_dm_odm);
|
||||
if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)
|
||||
odm_iq_calibrate(p_dm_odm);
|
||||
#endif
|
||||
}
|
||||
|
|
|
@ -90,18 +90,11 @@ odm_clear_txpowertracking_state(
|
|||
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
void *p_dm_void
|
||||
#else
|
||||
struct _ADAPTER *adapter
|
||||
#endif
|
||||
);
|
||||
|
||||
|
||||
|
||||
#define ODM_TARGET_CHNL_NUM_2G_5G 59
|
||||
|
||||
|
||||
void
|
||||
odm_reset_iqk_result(
|
||||
void *p_dm_void
|
||||
|
|
|
@ -1,784 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \
|
||||
do {\
|
||||
for (_offset = 0; _offset < _size; _offset++) { \
|
||||
\
|
||||
if (_delta_thermal < thermal_threshold[_direction][_offset]) { \
|
||||
\
|
||||
if (_offset != 0)\
|
||||
_offset--;\
|
||||
break;\
|
||||
} \
|
||||
} \
|
||||
if (_offset >= _size)\
|
||||
_offset = _size-1;\
|
||||
} while (0)
|
||||
|
||||
void configure_txpower_track(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
struct _TXPWRTRACK_CFG *p_config
|
||||
)
|
||||
{
|
||||
#if RTL8192E_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8192E)
|
||||
configure_txpower_track_8192e(p_config);
|
||||
#endif
|
||||
#if RTL8821A_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8821)
|
||||
configure_txpower_track_8821a(p_config);
|
||||
#endif
|
||||
#if RTL8812A_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8812)
|
||||
configure_txpower_track_8812a(p_config);
|
||||
#endif
|
||||
#if RTL8188E_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8188E)
|
||||
configure_txpower_track_8188e(p_config);
|
||||
#endif
|
||||
|
||||
#if RTL8188F_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8188F)
|
||||
configure_txpower_track_8188f(p_config);
|
||||
#endif
|
||||
|
||||
#if RTL8723B_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8723B)
|
||||
configure_txpower_track_8723b(p_config);
|
||||
#endif
|
||||
|
||||
#if RTL8814A_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8814A)
|
||||
configure_txpower_track_8814a(p_config);
|
||||
#endif
|
||||
|
||||
#if RTL8703B_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8703B)
|
||||
configure_txpower_track_8703b(p_config);
|
||||
#endif
|
||||
|
||||
#if RTL8822B_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8822B)
|
||||
configure_txpower_track_8822b(p_config);
|
||||
#endif
|
||||
|
||||
#if RTL8723D_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8723D)
|
||||
configure_txpower_track_8723d(p_config);
|
||||
#endif
|
||||
|
||||
#if RTL8821C_SUPPORT
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8821C)
|
||||
configure_txpower_track_8821c(p_config);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/* **********************************************************************
|
||||
* <20121113, Kordan> This function should be called when tx_agc changed.
|
||||
* Otherwise the previous compensation is gone, because we record the
|
||||
* delta of temperature between two TxPowerTracking watch dogs.
|
||||
*
|
||||
* NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
|
||||
* need to call this function.
|
||||
* ********************************************************************** */
|
||||
void
|
||||
odm_clear_txpowertracking_state(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
)
|
||||
{
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(p_dm_odm->adapter);
|
||||
u8 p = 0;
|
||||
struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
|
||||
|
||||
p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index;
|
||||
p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->default_cck_index;
|
||||
p_rf_calibrate_info->CCK_index = 0;
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) {
|
||||
p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->default_ofdm_index;
|
||||
p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->default_ofdm_index;
|
||||
p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index;
|
||||
|
||||
p_rf_calibrate_info->power_index_offset[p] = 0;
|
||||
p_rf_calibrate_info->delta_power_index[p] = 0;
|
||||
p_rf_calibrate_info->delta_power_index_last[p] = 0;
|
||||
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = 0; /* Initial Mix mode power tracking*/
|
||||
p_rf_calibrate_info->remnant_ofdm_swing_idx[p] = 0;
|
||||
p_rf_calibrate_info->kfree_offset[p] = 0;
|
||||
}
|
||||
|
||||
p_rf_calibrate_info->modify_tx_agc_flag_path_a = false; /*Initial at Modify Tx Scaling mode*/
|
||||
p_rf_calibrate_info->modify_tx_agc_flag_path_b = false; /*Initial at Modify Tx Scaling mode*/
|
||||
p_rf_calibrate_info->modify_tx_agc_flag_path_c = false; /*Initial at Modify Tx Scaling mode*/
|
||||
p_rf_calibrate_info->modify_tx_agc_flag_path_d = false; /*Initial at Modify Tx Scaling mode*/
|
||||
p_rf_calibrate_info->remnant_cck_swing_idx = 0;
|
||||
p_rf_calibrate_info->thermal_value = p_hal_data->eeprom_thermal_meter;
|
||||
|
||||
p_rf_calibrate_info->modify_tx_agc_value_cck = 0; /* modify by Mingzhi.Guo */
|
||||
p_rf_calibrate_info->modify_tx_agc_value_ofdm = 0; /* modify by Mingzhi.Guo */
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
#else
|
||||
struct _ADAPTER *adapter
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
|
||||
|
||||
u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
|
||||
s8 diff_DPK[4] = {0};
|
||||
u8 thermal_value_avg_count = 0;
|
||||
u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
|
||||
|
||||
u8 OFDM_min_index = 0; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
|
||||
u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(p_hal_data->current_channel) */
|
||||
u8 power_tracking_type = p_hal_data->RfPowerTrackingType;
|
||||
u8 xtal_offset_eanble = 0;
|
||||
|
||||
struct _TXPWRTRACK_CFG c;
|
||||
|
||||
/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
|
||||
u8 *delta_swing_table_idx_tup_a = NULL;
|
||||
u8 *delta_swing_table_idx_tdown_a = NULL;
|
||||
u8 *delta_swing_table_idx_tup_b = NULL;
|
||||
u8 *delta_swing_table_idx_tdown_b = NULL;
|
||||
/*for 8814 add by Yu Chen*/
|
||||
u8 *delta_swing_table_idx_tup_c = NULL;
|
||||
u8 *delta_swing_table_idx_tdown_c = NULL;
|
||||
u8 *delta_swing_table_idx_tup_d = NULL;
|
||||
u8 *delta_swing_table_idx_tdown_d = NULL;
|
||||
/*for Xtal Offset by James.Tung*/
|
||||
s8 *delta_swing_table_xtal_up = NULL;
|
||||
s8 *delta_swing_table_xtal_down = NULL;
|
||||
|
||||
/* 4 2. Initilization ( 7 steps in total ) */
|
||||
|
||||
configure_txpower_track(p_dm_odm, &c);
|
||||
|
||||
(*c.get_delta_swing_table)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
|
||||
(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/
|
||||
(*c.get_delta_swing_table8814only)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
|
||||
(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D)) /*for Xtal Offset*/
|
||||
(*c.get_delta_swing_xtal_table)(p_dm_odm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down);
|
||||
|
||||
|
||||
p_rf_calibrate_info->txpowertracking_callback_cnt++; /*cosa add for debug*/
|
||||
p_rf_calibrate_info->is_txpowertracking_init = true;
|
||||
|
||||
/*p_rf_calibrate_info->txpowertrack_control = p_hal_data->txpowertrack_control;
|
||||
<Kordan> We should keep updating the control variable according to HalData.
|
||||
<Kordan> rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
#if (MP_DRIVER == 1)
|
||||
p_rf_calibrate_info->rega24 = 0x090e1317;
|
||||
#endif
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
if (p_dm_odm->mp_mode == true)
|
||||
p_rf_calibrate_info->rega24 = 0x090e1317;
|
||||
#endif
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("===>odm_txpowertracking_callback_thermal_meter\n p_rf_calibrate_info->bb_swing_idx_cck_base: %d, p_rf_calibrate_info->bb_swing_idx_ofdm_base[A]: %d, p_rf_calibrate_info->default_ofdm_index: %d\n",
|
||||
p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->bb_swing_idx_ofdm_base[ODM_RF_PATH_A], p_rf_calibrate_info->default_ofdm_index));
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("p_rf_calibrate_info->txpowertrack_control=%d, p_hal_data->eeprom_thermal_meter %d\n", p_rf_calibrate_info->txpowertrack_control, p_hal_data->eeprom_thermal_meter));
|
||||
thermal_value = (u8)odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
|
||||
|
||||
/*add log by zhao he, check c80/c94/c14/ca0 value*/
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8723D) {
|
||||
regc80 = odm_get_bb_reg(p_dm_odm, 0xc80, MASKDWORD);
|
||||
regcd0 = odm_get_bb_reg(p_dm_odm, 0xcd0, MASKDWORD);
|
||||
regcd4 = odm_get_bb_reg(p_dm_odm, 0xcd4, MASKDWORD);
|
||||
regab4 = odm_get_bb_reg(p_dm_odm, 0xab4, 0x000007FF);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4));
|
||||
}
|
||||
|
||||
if (!p_rf_calibrate_info->txpowertrack_control)
|
||||
return;
|
||||
|
||||
|
||||
/*4 3. Initialize ThermalValues of rf_calibrate_info*/
|
||||
|
||||
if (p_rf_calibrate_info->is_reloadtxpowerindex)
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("reload ofdm index for band switch\n"));
|
||||
|
||||
/*4 4. Calculate average thermal meter*/
|
||||
|
||||
p_rf_calibrate_info->thermal_value_avg[p_rf_calibrate_info->thermal_value_avg_index] = thermal_value;
|
||||
p_rf_calibrate_info->thermal_value_avg_index++;
|
||||
if (p_rf_calibrate_info->thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/
|
||||
p_rf_calibrate_info->thermal_value_avg_index = 0;
|
||||
|
||||
for (i = 0; i < c.average_thermal_num; i++) {
|
||||
if (p_rf_calibrate_info->thermal_value_avg[i]) {
|
||||
thermal_value_avg += p_rf_calibrate_info->thermal_value_avg[i];
|
||||
thermal_value_avg_count++;
|
||||
}
|
||||
}
|
||||
|
||||
if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */
|
||||
thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
|
||||
p_rf_calibrate_info->thermal_value_delta = thermal_value - p_hal_data->eeprom_thermal_meter;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, p_hal_data->eeprom_thermal_meter));
|
||||
}
|
||||
|
||||
/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
|
||||
|
||||
/* "delta" here is used to determine whether thermal value changes or not. */
|
||||
delta = (thermal_value > p_rf_calibrate_info->thermal_value) ? (thermal_value - p_rf_calibrate_info->thermal_value) : (p_rf_calibrate_info->thermal_value - thermal_value);
|
||||
delta_LCK = (thermal_value > p_rf_calibrate_info->thermal_value_lck) ? (thermal_value - p_rf_calibrate_info->thermal_value_lck) : (p_rf_calibrate_info->thermal_value_lck - thermal_value);
|
||||
delta_IQK = (thermal_value > p_rf_calibrate_info->thermal_value_iqk) ? (thermal_value - p_rf_calibrate_info->thermal_value_iqk) : (p_rf_calibrate_info->thermal_value_iqk - thermal_value);
|
||||
|
||||
if (p_rf_calibrate_info->thermal_value_iqk == 0xff) { /*no PG, use thermal value for IQK*/
|
||||
p_rf_calibrate_info->thermal_value_iqk = thermal_value;
|
||||
delta_IQK = (thermal_value > p_rf_calibrate_info->thermal_value_iqk) ? (thermal_value - p_rf_calibrate_info->thermal_value_iqk) : (p_rf_calibrate_info->thermal_value_iqk - thermal_value);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, use thermal_value for IQK\n"));
|
||||
}
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
diff_DPK[p] = (s8)thermal_value - (s8)p_rf_calibrate_info->dpk_thermal[p];
|
||||
|
||||
/*4 6. If necessary, do LCK.*/
|
||||
|
||||
if (!(p_dm_odm->support_ic_type & ODM_RTL8821)) { /*no PG, do LCK at initial status*/
|
||||
if (p_rf_calibrate_info->thermal_value_lck == 0xff) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, do LCK\n"));
|
||||
p_rf_calibrate_info->thermal_value_lck = thermal_value;
|
||||
|
||||
/*Use RTLCK, so close power tracking driver LCK*/
|
||||
if (!(p_dm_odm->support_ic_type & ODM_RTL8814A)) {
|
||||
if (c.phy_lc_calibrate)
|
||||
(*c.phy_lc_calibrate)(p_dm_odm);
|
||||
}
|
||||
|
||||
delta_LCK = (thermal_value > p_rf_calibrate_info->thermal_value_lck) ? (thermal_value - p_rf_calibrate_info->thermal_value_lck) : (p_rf_calibrate_info->thermal_value_lck - thermal_value);
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK));
|
||||
|
||||
/* Delta temperature is equal to or larger than 20 centigrade.*/
|
||||
if (delta_LCK >= c.threshold_iqk) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk));
|
||||
p_rf_calibrate_info->thermal_value_lck = thermal_value;
|
||||
|
||||
/*Use RTLCK, so close power tracking driver LCK*/
|
||||
if (!(p_dm_odm->support_ic_type & ODM_RTL8814A)) {
|
||||
if (c.phy_lc_calibrate)
|
||||
(*c.phy_lc_calibrate)(p_dm_odm);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
|
||||
|
||||
if (delta > 0 && p_rf_calibrate_info->txpowertrack_control) {
|
||||
/* "delta" here is used to record the absolute value of differrence. */
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
delta = thermal_value > p_hal_data->eeprom_thermal_meter ? (thermal_value - p_hal_data->eeprom_thermal_meter) : (p_hal_data->eeprom_thermal_meter - thermal_value);
|
||||
#else
|
||||
delta = (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - p_dm_odm->priv->pmib->dot11RFEntry.ther) : (p_dm_odm->priv->pmib->dot11RFEntry.ther - thermal_value);
|
||||
#endif
|
||||
if (delta >= TXPWR_TRACK_TABLE_SIZE)
|
||||
delta = TXPWR_TRACK_TABLE_SIZE - 1;
|
||||
|
||||
/*4 7.1 The Final Power index = BaseIndex + power_index_offset*/
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
if (thermal_value > p_hal_data->eeprom_thermal_meter) {
|
||||
#else
|
||||
if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) {
|
||||
#endif
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
p_rf_calibrate_info->delta_power_index_last[p] = p_rf_calibrate_info->delta_power_index[p]; /*recording poer index offset*/
|
||||
switch (p) {
|
||||
case ODM_RF_PATH_B:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]));
|
||||
|
||||
p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
|
||||
case ODM_RF_PATH_C:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]));
|
||||
|
||||
p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
|
||||
case ODM_RF_PATH_D:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]));
|
||||
|
||||
p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
|
||||
default:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]));
|
||||
|
||||
p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D)) {
|
||||
/*Save xtal_offset from Xtal table*/
|
||||
p_rf_calibrate_info->xtal_offset_last = p_rf_calibrate_info->xtal_offset; /*recording last Xtal offset*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]));
|
||||
p_rf_calibrate_info->xtal_offset = delta_swing_table_xtal_up[delta];
|
||||
|
||||
if (p_rf_calibrate_info->xtal_offset_last == p_rf_calibrate_info->xtal_offset)
|
||||
xtal_offset_eanble = 0;
|
||||
else
|
||||
xtal_offset_eanble = 1;
|
||||
}
|
||||
|
||||
} else {
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
p_rf_calibrate_info->delta_power_index_last[p] = p_rf_calibrate_info->delta_power_index[p]; /*recording poer index offset*/
|
||||
|
||||
switch (p) {
|
||||
case ODM_RF_PATH_B:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]));
|
||||
p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
|
||||
case ODM_RF_PATH_C:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]));
|
||||
p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
|
||||
case ODM_RF_PATH_D:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]));
|
||||
p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
|
||||
default:
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]));
|
||||
p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta];
|
||||
p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p]));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D)) {
|
||||
/*Save xtal_offset from Xtal table*/
|
||||
p_rf_calibrate_info->xtal_offset_last = p_rf_calibrate_info->xtal_offset; /*recording last Xtal offset*/
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]));
|
||||
p_rf_calibrate_info->xtal_offset = delta_swing_table_xtal_down[delta];
|
||||
|
||||
if (p_rf_calibrate_info->xtal_offset_last == p_rf_calibrate_info->xtal_offset)
|
||||
xtal_offset_eanble = 0;
|
||||
else
|
||||
xtal_offset_eanble = 1;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p));
|
||||
|
||||
if (p_rf_calibrate_info->delta_power_index[p] == p_rf_calibrate_info->delta_power_index_last[p]) /*If Thermal value changes but lookup table value still the same*/
|
||||
p_rf_calibrate_info->power_index_offset[p] = 0;
|
||||
else
|
||||
p_rf_calibrate_info->power_index_offset[p] = p_rf_calibrate_info->delta_power_index[p] - p_rf_calibrate_info->delta_power_index_last[p]; /*Power index diff between 2 times Power Tracking*/
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, p_rf_calibrate_info->power_index_offset[p], p_rf_calibrate_info->delta_power_index[p], p_rf_calibrate_info->delta_power_index_last[p]));
|
||||
|
||||
p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] + p_rf_calibrate_info->power_index_offset[p];
|
||||
p_rf_calibrate_info->CCK_index = p_rf_calibrate_info->bb_swing_idx_cck_base + p_rf_calibrate_info->power_index_offset[p];
|
||||
|
||||
p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->CCK_index;
|
||||
p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->OFDM_index[p];
|
||||
|
||||
/*************Print BB Swing base and index Offset*************/
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_cck, p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->power_index_offset[p]));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_ofdm[p], p, p_rf_calibrate_info->bb_swing_idx_ofdm_base[p], p_rf_calibrate_info->power_index_offset[p]));
|
||||
|
||||
/*4 7.1 Handle boundary conditions of index.*/
|
||||
|
||||
if (p_rf_calibrate_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)
|
||||
p_rf_calibrate_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;
|
||||
else if (p_rf_calibrate_info->OFDM_index[p] <= OFDM_min_index)
|
||||
p_rf_calibrate_info->OFDM_index[p] = OFDM_min_index;
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("\n\n========================================================================================================\n"));
|
||||
|
||||
if (p_rf_calibrate_info->CCK_index > c.swing_table_size_cck - 1)
|
||||
p_rf_calibrate_info->CCK_index = c.swing_table_size_cck - 1;
|
||||
else if (p_rf_calibrate_info->CCK_index <= 0)
|
||||
p_rf_calibrate_info->CCK_index = 0;
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, p_rf_calibrate_info->thermal_value: %d\n",
|
||||
p_rf_calibrate_info->txpowertrack_control, thermal_value, p_rf_calibrate_info->thermal_value));
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
p_rf_calibrate_info->power_index_offset[p] = 0;
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
|
||||
p_rf_calibrate_info->CCK_index, p_rf_calibrate_info->bb_swing_idx_cck_base)); /*Print Swing base & current*/
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
|
||||
p_rf_calibrate_info->OFDM_index[p], p, p_rf_calibrate_info->bb_swing_idx_ofdm_base[p]));
|
||||
}
|
||||
|
||||
if ((p_dm_odm->support_ic_type & ODM_RTL8814A)) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("power_tracking_type=%d\n", power_tracking_type));
|
||||
|
||||
if (power_tracking_type == 0) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0);
|
||||
} else if (power_tracking_type == 1) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_2G_TSSI_5G_MODE, p, 0);
|
||||
} else if (power_tracking_type == 2) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_5G_TSSI_2G_MODE, p, 0);
|
||||
} else if (power_tracking_type == 3) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking TSSI MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, TSSI_MODE, p, 0);
|
||||
}
|
||||
p_rf_calibrate_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/
|
||||
|
||||
} else if ((p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_A] != 0 ||
|
||||
p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_B] != 0 ||
|
||||
p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_C] != 0 ||
|
||||
p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_D] != 0) &&
|
||||
p_rf_calibrate_info->txpowertrack_control && (p_hal_data->eeprom_thermal_meter != 0xff)) {
|
||||
/* 4 7.2 Configure the Swing Table to adjust Tx Power. */
|
||||
|
||||
p_rf_calibrate_info->is_tx_power_changed = true; /*Always true after Tx Power is adjusted by power tracking.*/
|
||||
/* */
|
||||
/* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */
|
||||
/* to increase TX power. Otherwise, EVM will be bad. */
|
||||
/* */
|
||||
/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
|
||||
if (thermal_value > p_rf_calibrate_info->thermal_value) {
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
|
||||
p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_rf_calibrate_info->thermal_value));
|
||||
}
|
||||
} else if (thermal_value < p_rf_calibrate_info->thermal_value) { /*Low temperature*/
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
|
||||
p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_rf_calibrate_info->thermal_value));
|
||||
}
|
||||
}
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
if (thermal_value > p_hal_data->eeprom_thermal_meter)
|
||||
#else
|
||||
if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther)
|
||||
#endif
|
||||
{
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature(%d) higher than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter));
|
||||
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8821 ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8814A ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8822B ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8821C) {
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0);
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, indexforchannel);
|
||||
}
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature(%d) lower than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter));
|
||||
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8821 ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8814A ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8822B ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8821C) {
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, indexforchannel);
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n"));
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
(*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, indexforchannel);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->bb_swing_idx_cck; /*Record last time Power Tracking result as base.*/
|
||||
for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++)
|
||||
p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->bb_swing_idx_ofdm[p];
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("p_rf_calibrate_info->thermal_value = %d thermal_value= %d\n", p_rf_calibrate_info->thermal_value, thermal_value));
|
||||
|
||||
p_rf_calibrate_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/
|
||||
|
||||
}
|
||||
|
||||
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8723D) {
|
||||
|
||||
if (xtal_offset_eanble != 0 && p_rf_calibrate_info->txpowertrack_control && (p_hal_data->eeprom_thermal_meter != 0xff)) {
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter Xtal Tracking**********\n"));
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
if (thermal_value > p_hal_data->eeprom_thermal_meter) {
|
||||
#else
|
||||
if (thermal_value > p_dm_odm->priv->pmib->dot11RFEntry.ther) {
|
||||
#endif
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature(%d) higher than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter));
|
||||
(*c.odm_txxtaltrack_set_xtal)(p_dm_odm);
|
||||
} else {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("Temperature(%d) lower than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter));
|
||||
(*c.odm_txxtaltrack_set_xtal)(p_dm_odm);
|
||||
}
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********End Xtal Tracking**********\n"));
|
||||
}
|
||||
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
|
||||
if (!IS_HARDWARE_TYPE_8723B(adapter)) {
|
||||
/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
|
||||
if (delta_IQK >= c.threshold_iqk) {
|
||||
p_rf_calibrate_info->thermal_value_iqk = thermal_value;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk));
|
||||
if (!p_rf_calibrate_info->is_iqk_in_progress)
|
||||
(*c.do_iqk)(p_dm_odm, delta_IQK, thermal_value, 8);
|
||||
}
|
||||
}
|
||||
if (p_rf_calibrate_info->dpk_thermal[ODM_RF_PATH_A] != 0) {
|
||||
if (diff_DPK[ODM_RF_PATH_A] >= c.threshold_dpk) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk));
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
|
||||
} else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.threshold_dpk)) {
|
||||
s32 value = 0x20 + (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk);
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
|
||||
} else {
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
|
||||
}
|
||||
}
|
||||
if (p_rf_calibrate_info->dpk_thermal[ODM_RF_PATH_B] != 0) {
|
||||
if (diff_DPK[ODM_RF_PATH_B] >= c.threshold_dpk) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk));
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
|
||||
} else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.threshold_dpk)) {
|
||||
s32 value = 0x20 + (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk);
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
|
||||
} else {
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1);
|
||||
odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===odm_txpowertracking_callback_thermal_meter\n"));
|
||||
|
||||
p_rf_calibrate_info->tx_powercount = 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* 3============================================================
|
||||
* 3 IQ Calibration
|
||||
* 3============================================================ */
|
||||
|
||||
void
|
||||
odm_reset_iqk_result(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
|
||||
{
|
||||
u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
|
||||
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165
|
||||
};
|
||||
u8 place = chnl;
|
||||
|
||||
|
||||
if (chnl > 14) {
|
||||
for (place = 14; place < sizeof(channel_all); place++) {
|
||||
if (channel_all[place] == chnl)
|
||||
return place - 13;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
void
|
||||
odm_iq_calibrate(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
)
|
||||
{
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
|
||||
|
||||
RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("=>%s\n" , __func__));
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
if (*p_dm_odm->p_is_fcs_mode_enable)
|
||||
return;
|
||||
#endif
|
||||
|
||||
if (p_dm_odm->is_linked) {
|
||||
RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("interval=%d ch=%d prech=%d scan=%s\n", p_dm_odm->linked_interval,
|
||||
*p_dm_odm->p_channel, p_dm_odm->pre_channel, *p_dm_odm->p_is_scan_in_process == TRUE ? "TRUE":"FALSE"));
|
||||
|
||||
if (*p_dm_odm->p_channel != p_dm_odm->pre_channel) {
|
||||
p_dm_odm->pre_channel = *p_dm_odm->p_channel;
|
||||
p_dm_odm->linked_interval = 0;
|
||||
}
|
||||
|
||||
if ((p_dm_odm->linked_interval < 3) && (!*p_dm_odm->p_is_scan_in_process))
|
||||
p_dm_odm->linked_interval++;
|
||||
|
||||
if (p_dm_odm->linked_interval == 2)
|
||||
PHY_IQCalibrate(adapter, false);
|
||||
} else
|
||||
p_dm_odm->linked_interval = 0;
|
||||
|
||||
RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("<=%s interval=%d ch=%d prech=%d scan=%s\n", __func__, p_dm_odm->linked_interval,
|
||||
*p_dm_odm->p_channel, p_dm_odm->pre_channel, *p_dm_odm->p_is_scan_in_process == TRUE?"TRUE":"FALSE"));
|
||||
}
|
||||
|
||||
void phydm_rf_init(struct PHY_DM_STRUCT *p_dm_odm)
|
||||
{
|
||||
|
||||
odm_txpowertracking_init(p_dm_odm);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
odm_clear_txpowertracking_state(p_dm_odm);
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
phy_iq_calibrate_8814a_init(p_dm_odm);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
void phydm_rf_watchdog(struct PHY_DM_STRUCT *p_dm_odm)
|
||||
{
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
odm_txpowertracking_check(p_dm_odm);
|
||||
if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)
|
||||
odm_iq_calibrate(p_dm_odm);
|
||||
#endif
|
||||
}
|
|
@ -1,119 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HAL_PHY_RF_H__
|
||||
#define __HAL_PHY_RF_H__
|
||||
|
||||
#include "phydm_kfree.h"
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
#include "rtl8814a/phydm_iqk_8814a.h"
|
||||
#endif
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
#include "rtl8822b/phydm_iqk_8822b.h"
|
||||
#include "../mac/Halmac_type.h"
|
||||
#endif
|
||||
#include "phydm_powertracking_win.h"
|
||||
|
||||
#if (RTL8821C_SUPPORT == 1)
|
||||
#include "rtl8821c/phydm_iqk_8821c.h"
|
||||
#endif
|
||||
|
||||
enum spur_cal_method {
|
||||
PLL_RESET,
|
||||
AFE_PHASE_SEL
|
||||
};
|
||||
|
||||
enum pwrtrack_method {
|
||||
BBSWING,
|
||||
TXAGC,
|
||||
MIX_MODE,
|
||||
TSSI_MODE,
|
||||
MIX_2G_TSSI_5G_MODE,
|
||||
MIX_5G_TSSI_2G_MODE
|
||||
};
|
||||
|
||||
typedef void(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
|
||||
typedef void(*func_iqk)(void *, u8, u8, u8);
|
||||
typedef void(*func_lck)(void *);
|
||||
typedef void(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
|
||||
typedef void(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
|
||||
typedef void (*func_swing_xtal)(void *, s8 **, s8 **);
|
||||
typedef void (*func_set_xtal)(void *);
|
||||
typedef void(*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
|
||||
|
||||
struct _TXPWRTRACK_CFG {
|
||||
u8 swing_table_size_cck;
|
||||
u8 swing_table_size_ofdm;
|
||||
u8 threshold_iqk;
|
||||
u8 threshold_dpk;
|
||||
u8 average_thermal_num;
|
||||
u8 rf_path_count;
|
||||
u32 thermal_reg_addr;
|
||||
func_set_pwr odm_tx_pwr_track_set_pwr;
|
||||
func_iqk do_iqk;
|
||||
func_lck phy_lc_calibrate;
|
||||
func_swing get_delta_swing_table;
|
||||
func_swing8814only get_delta_swing_table8814only;
|
||||
func_swing_xtal get_delta_swing_xtal_table;
|
||||
func_set_xtal odm_txxtaltrack_set_xtal;
|
||||
func_all_swing get_delta_all_swing_table;
|
||||
};
|
||||
|
||||
void
|
||||
configure_txpower_track(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
struct _TXPWRTRACK_CFG *p_config
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
odm_clear_txpowertracking_state(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter(
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
#else
|
||||
struct _ADAPTER *adapter
|
||||
#endif
|
||||
);
|
||||
|
||||
|
||||
|
||||
#define ODM_TARGET_CHNL_NUM_2G_5G 59
|
||||
|
||||
|
||||
void
|
||||
odm_reset_iqk_result(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
u8
|
||||
odm_get_right_chnl_place_for_iqk(
|
||||
u8 chnl
|
||||
);
|
||||
|
||||
void odm_iq_calibrate(struct PHY_DM_STRUCT *p_dm_odm);
|
||||
void phydm_rf_init(struct PHY_DM_STRUCT *p_dm_odm);
|
||||
void phydm_rf_watchdog(struct PHY_DM_STRUCT *p_dm_odm);
|
||||
|
||||
#endif /* #ifndef __HAL_PHY_RF_H__ */
|
|
@ -38,27 +38,6 @@ struct _ACS_ {
|
|||
u8 clean_channel_5g;
|
||||
u16 channel_info_2g[2][ODM_MAX_CHANNEL_2G]; /* Channel_Info[1]: channel score, Channel_Info[2]:Channel_Scan_Times */
|
||||
u16 channel_info_5g[2][ODM_MAX_CHANNEL_5G];
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
u8 acs_step;
|
||||
/* NHM count 0-11 */
|
||||
u8 nhm_cnt[14][11];
|
||||
|
||||
/* AC-Series, for storing previous setting */
|
||||
u32 reg0x990;
|
||||
u32 reg0x994;
|
||||
u32 reg0x998;
|
||||
u32 reg0x99c;
|
||||
u8 reg0x9a0; /* u8 */
|
||||
|
||||
/* N-Series, for storing previous setting */
|
||||
u32 reg0x890;
|
||||
u32 reg0x894;
|
||||
u32 reg0x898;
|
||||
u32 reg0x89c;
|
||||
u8 reg0xe28; /* u8 */
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
@ -84,22 +63,4 @@ odm_get_auto_channel_select_result(
|
|||
u8 band
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
|
||||
void
|
||||
phydm_auto_channel_select_setting_ap(
|
||||
void *p_dm_void,
|
||||
u32 setting, /* 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING */
|
||||
u32 acs_step
|
||||
);
|
||||
|
||||
void
|
||||
phydm_get_nhm_statistics_ap(
|
||||
void *p_dm_void,
|
||||
u32 idx, /* @ 2G, Real channel number = idx+1 */
|
||||
u32 acs_step
|
||||
);
|
||||
|
||||
#endif /* #if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) */
|
||||
|
||||
#endif /* #ifndef __PHYDMACS_H__ */
|
||||
|
|
|
@ -24,13 +24,6 @@
|
|||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
#if WPP_SOFTWARE_TRACE
|
||||
#include "PhyDM_Adaptivity.tmh"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
void
|
||||
phydm_check_adaptivity(
|
||||
void *p_dm_void
|
||||
|
@ -40,13 +33,6 @@ phydm_check_adaptivity(
|
|||
struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY);
|
||||
|
||||
if (p_dm_odm->support_ability & ODM_BB_ADAPTIVITY) {
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
if (p_dm_odm->ap_total_num > adaptivity->ap_num_th) {
|
||||
p_dm_odm->adaptivity_enable = false;
|
||||
p_dm_odm->adaptivity_flag = false;
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("AP total num > %d!!, disable adaptivity\n", adaptivity->ap_num_th));
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
if (adaptivity->dynamic_link_adaptivity || adaptivity->acs_for_adaptivity) {
|
||||
if (p_dm_odm->is_linked && adaptivity->is_check == false) {
|
||||
|
@ -67,72 +53,8 @@ phydm_check_adaptivity(
|
|||
p_dm_odm->adaptivity_enable = false;
|
||||
p_dm_odm->adaptivity_flag = false;
|
||||
}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
bool
|
||||
phydm_check_channel_plan(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ADAPTER *p_adapter = p_dm_odm->adapter;
|
||||
PMGNT_INFO p_mgnt_info = &(p_adapter->MgntInfo);
|
||||
|
||||
if (p_mgnt_info->RegEnableAdaptivity == 2) {
|
||||
if (p_dm_odm->carrier_sense_enable == false) { /*check domain Code for adaptivity or CarrierSense*/
|
||||
if ((*p_dm_odm->p_band_type == ODM_BAND_5G) &&
|
||||
!(p_dm_odm->odm_regulation_5g == REGULATION_ETSI || p_dm_odm->odm_regulation_5g == REGULATION_WW)) {
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity skip 5G domain code : %d\n", p_dm_odm->odm_regulation_5g));
|
||||
p_dm_odm->adaptivity_enable = false;
|
||||
p_dm_odm->adaptivity_flag = false;
|
||||
return true;
|
||||
} else if ((*p_dm_odm->p_band_type == ODM_BAND_2_4G) &&
|
||||
!(p_dm_odm->odm_regulation_2_4g == REGULATION_ETSI || p_dm_odm->odm_regulation_2_4g == REGULATION_WW)) {
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity skip 2.4G domain code : %d\n", p_dm_odm->odm_regulation_2_4g));
|
||||
p_dm_odm->adaptivity_enable = false;
|
||||
p_dm_odm->adaptivity_flag = false;
|
||||
return true;
|
||||
|
||||
} else if ((*p_dm_odm->p_band_type != ODM_BAND_2_4G) && (*p_dm_odm->p_band_type != ODM_BAND_5G)) {
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity neither 2G nor 5G band, return\n"));
|
||||
p_dm_odm->adaptivity_enable = false;
|
||||
p_dm_odm->adaptivity_flag = false;
|
||||
return true;
|
||||
}
|
||||
} else {
|
||||
if ((*p_dm_odm->p_band_type == ODM_BAND_5G) &&
|
||||
!(p_dm_odm->odm_regulation_5g == REGULATION_MKK || p_dm_odm->odm_regulation_5g == REGULATION_WW)) {
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 5G domain code : %d\n", p_dm_odm->odm_regulation_5g));
|
||||
p_dm_odm->adaptivity_enable = false;
|
||||
p_dm_odm->adaptivity_flag = false;
|
||||
return true;
|
||||
}
|
||||
|
||||
else if ((*p_dm_odm->p_band_type == ODM_BAND_2_4G) &&
|
||||
!(p_dm_odm->odm_regulation_2_4g == REGULATION_MKK || p_dm_odm->odm_regulation_2_4g == REGULATION_WW)) {
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 2.4G domain code : %d\n", p_dm_odm->odm_regulation_2_4g));
|
||||
p_dm_odm->adaptivity_enable = false;
|
||||
p_dm_odm->adaptivity_flag = false;
|
||||
return true;
|
||||
|
||||
} else if ((*p_dm_odm->p_band_type != ODM_BAND_2_4G) && (*p_dm_odm->p_band_type != ODM_BAND_5G)) {
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense neither 2G nor 5G band, return\n"));
|
||||
p_dm_odm->adaptivity_enable = false;
|
||||
p_dm_odm->adaptivity_flag = false;
|
||||
return true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
void
|
||||
phydm_nhm_counter_statistics_init(
|
||||
void *p_dm_void
|
||||
|
@ -426,9 +348,6 @@ phydm_check_environment(
|
|||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY);
|
||||
bool is_clean_environment = false;
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct rtl8192cd_priv *priv = p_dm_odm->priv;
|
||||
#endif
|
||||
|
||||
if (adaptivity->is_first_link == true) {
|
||||
if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
|
||||
|
@ -456,9 +375,6 @@ phydm_check_environment(
|
|||
p_dm_odm->adaptivity_flag = false;
|
||||
else
|
||||
p_dm_odm->adaptivity_flag = true;
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
priv->pshare->rf_ft_var.is_clean_environment = true;
|
||||
#endif
|
||||
} else {
|
||||
if (!adaptivity->acs_for_adaptivity) {
|
||||
p_dm_odm->th_l2h_ini = p_dm_odm->th_l2h_ini_mode2; /*mode2*/
|
||||
|
@ -467,9 +383,6 @@ phydm_check_environment(
|
|||
p_dm_odm->adaptivity_flag = false;
|
||||
p_dm_odm->adaptivity_enable = false;
|
||||
}
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
priv->pshare->rf_ft_var.is_clean_environment = false;
|
||||
#endif
|
||||
}
|
||||
adaptivity->nhm_wait = 0;
|
||||
adaptivity->is_first_link = true;
|
||||
|
@ -677,9 +590,6 @@ phydm_adaptivity_init(
|
|||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY);
|
||||
s8 igi_target = 0x32;
|
||||
/*struct _dynamic_initial_gain_threshold_* p_dm_dig_table = &p_dm_odm->dm_dig_table;*/
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
|
||||
|
||||
if (p_dm_odm->carrier_sense_enable == false) {
|
||||
if (p_dm_odm->th_l2h_ini == 0)
|
||||
|
@ -689,40 +599,11 @@ phydm_adaptivity_init(
|
|||
|
||||
if (p_dm_odm->th_edcca_hl_diff == 0)
|
||||
p_dm_odm->th_edcca_hl_diff = 7;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
|
||||
if (p_dm_odm->wifi_test == true || p_dm_odm->mp_mode == true)
|
||||
#else
|
||||
if ((p_dm_odm->wifi_test & RT_WIFI_LOGO) == true)
|
||||
#endif
|
||||
p_dm_odm->edcca_enable = false; /*even no adaptivity, we still enable EDCCA, AP side use mib control*/
|
||||
else
|
||||
p_dm_odm->edcca_enable = true;
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
struct rtl8192cd_priv *priv = p_dm_odm->priv;
|
||||
|
||||
if (p_dm_odm->carrier_sense_enable) {
|
||||
p_dm_odm->th_l2h_ini = 0xa;
|
||||
p_dm_odm->th_edcca_hl_diff = 7;
|
||||
} else {
|
||||
p_dm_odm->th_l2h_ini = p_dm_odm->TH_L2H_default; /*set by mib*/
|
||||
p_dm_odm->th_edcca_hl_diff = p_dm_odm->th_edcca_hl_diff_default;
|
||||
}
|
||||
|
||||
if (priv->pshare->rf_ft_var.adaptivity_enable == 3)
|
||||
adaptivity->acs_for_adaptivity = true;
|
||||
else
|
||||
adaptivity->acs_for_adaptivity = false;
|
||||
|
||||
if (priv->pshare->rf_ft_var.adaptivity_enable == 2)
|
||||
adaptivity->dynamic_link_adaptivity = true;
|
||||
else
|
||||
adaptivity->dynamic_link_adaptivity = false;
|
||||
|
||||
priv->pshare->rf_ft_var.is_clean_environment = false;
|
||||
|
||||
#endif
|
||||
|
||||
p_dm_odm->adaptivity_igi_upper = 0;
|
||||
p_dm_odm->adaptivity_enable = false; /*use this flag to decide enable or disable*/
|
||||
|
||||
|
@ -759,10 +640,6 @@ phydm_adaptivity_init(
|
|||
odm_set_bb_reg(p_dm_odm, ODM_REG_PAGE_B1_97F, BIT(30), 0x1); /*set to page B1*/
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_EDCCA_DCNF_97F, BIT(27) | BIT26, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_PAGE_B1_97F, BIT(30), 0x0);
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
if (priv->pshare->rf_ft_var.adaptivity_enable == 1)
|
||||
odm_set_bb_reg(p_dm_odm, 0xce8, BIT(13), 0x1); /*0: mean, 1:max pwdB*/
|
||||
#endif
|
||||
} else
|
||||
odm_set_bb_reg(p_dm_odm, ODM_REG_EDCCA_DCNF_11N, BIT(21) | BIT20, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
|
||||
}
|
||||
|
@ -801,16 +678,6 @@ phydm_adaptivity(
|
|||
s8 th_l2h_dmc, th_h2l_dmc;
|
||||
s8 diff = 0, igi_target;
|
||||
struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY);
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *p_adapter = p_dm_odm->adapter;
|
||||
bool is_fw_current_in_ps_mode = false;
|
||||
|
||||
p_adapter->HalFunc.GetHwRegHandler(p_adapter, HW_VAR_FW_PSMODE_STATUS, (u8 *)(&is_fw_current_in_ps_mode));
|
||||
|
||||
/*Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.*/
|
||||
if (is_fw_current_in_ps_mode)
|
||||
return;
|
||||
#endif
|
||||
|
||||
if ((p_dm_odm->edcca_enable == false) || (adaptivity->is_stop_edcca == true)) {
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Disable EDCCA!!!\n"));
|
||||
|
@ -822,18 +689,6 @@ phydm_adaptivity(
|
|||
p_dm_odm->th_l2h_ini = p_dm_odm->th_l2h_ini_mode2;
|
||||
p_dm_odm->th_edcca_hl_diff = p_dm_odm->th_edcca_hl_diff_mode2;
|
||||
}
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
else {
|
||||
if (phydm_check_channel_plan(p_dm_odm) || (p_dm_odm->ap_total_num > adaptivity->ap_num_th)) {
|
||||
p_dm_odm->th_l2h_ini = p_dm_odm->th_l2h_ini_mode2;
|
||||
p_dm_odm->th_edcca_hl_diff = p_dm_odm->th_edcca_hl_diff_mode2;
|
||||
} else {
|
||||
p_dm_odm->th_l2h_ini = adaptivity->th_l2h_ini_backup;
|
||||
p_dm_odm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("odm_Adaptivity() =====>\n"));
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("igi_base=0x%x, th_l2h_ini = %d, th_edcca_hl_diff = %d\n",
|
||||
adaptivity->igi_base, p_dm_odm->th_l2h_ini, p_dm_odm->th_edcca_hl_diff));
|
||||
|
@ -901,73 +756,6 @@ phydm_adaptivity(
|
|||
return;
|
||||
}
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
|
||||
void
|
||||
phydm_adaptivity_bsod(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ADAPTER *p_adapter = p_dm_odm->adapter;
|
||||
PMGNT_INFO p_mgnt_info = &(p_adapter->MgntInfo);
|
||||
u8 count = 0;
|
||||
u32 u4_value;
|
||||
|
||||
/*
|
||||
1. turn off RF (TRX Mux in standby mode)
|
||||
2. H2C mac id drop
|
||||
3. ignore EDCCA
|
||||
4. wait for clear FIFO
|
||||
5. don't ignore EDCCA
|
||||
6. turn on RF (TRX Mux in TRx mdoe)
|
||||
7. H2C mac id resume
|
||||
*/
|
||||
|
||||
RT_TRACE(COMP_MLME, DBG_WARNING, ("MAC id drop packet!!!!!\n"));
|
||||
|
||||
p_adapter->dropPktByMacIdCnt++;
|
||||
p_mgnt_info->bDropPktInProgress = true;
|
||||
|
||||
p_adapter->HalFunc.GetHwRegHandler(p_adapter, HW_VAR_MAX_Q_PAGE_NUM, (u8 *)(&u4_value));
|
||||
RT_TRACE(COMP_INIT, DBG_LOUD, ("Queue Reserved Page number = 0x%08x\n", u4_value));
|
||||
p_adapter->HalFunc.GetHwRegHandler(p_adapter, HW_VAR_AVBL_Q_PAGE_NUM, (u8 *)(&u4_value));
|
||||
RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page number = 0x%08x\n", u4_value));
|
||||
|
||||
/*Standby mode*/
|
||||
phydm_set_trx_mux(p_dm_odm, phydm_standby_mode, phydm_standby_mode);
|
||||
odm_write_dig(p_dm_odm, 0x20);
|
||||
|
||||
/*H2C mac id drop*/
|
||||
MacIdIndicateDisconnect(p_adapter);
|
||||
|
||||
/*Ignore EDCCA*/
|
||||
phydm_mac_edcca_state(p_dm_odm, phydm_ignore_edcca);
|
||||
|
||||
delay_ms(50);
|
||||
count = 5;
|
||||
|
||||
/*Resume EDCCA*/
|
||||
phydm_mac_edcca_state(p_dm_odm, phydm_dont_ignore_edcca);
|
||||
|
||||
/*Turn on TRx mode*/
|
||||
phydm_set_trx_mux(p_dm_odm, phydm_tx_mode, phydm_rx_mode);
|
||||
odm_write_dig(p_dm_odm, 0x20);
|
||||
|
||||
/*Resume H2C macid*/
|
||||
MacIdRecoverMediaStatus(p_adapter);
|
||||
|
||||
p_adapter->HalFunc.GetHwRegHandler(p_adapter, HW_VAR_AVBL_Q_PAGE_NUM, (u8 *)(&u4_value));
|
||||
RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page number = 0x%08x\n", u4_value));
|
||||
|
||||
p_mgnt_info->bDropPktInProgress = false;
|
||||
RT_TRACE(COMP_MLME, DBG_WARNING, ("End of MAC id drop packet, spent %dms\n", count * 10));
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*This API is for solving USB can't Tx problem due to USB3.0 interference in 2.4G*/
|
||||
void
|
||||
phydm_pause_edcca(
|
||||
|
@ -983,7 +771,6 @@ phydm_pause_edcca(
|
|||
|
||||
if (is_pasue_edcca) {
|
||||
adaptivity->is_stop_edcca = true;
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
|
||||
if (adaptivity->adajust_igi_level > IGI)
|
||||
diff = adaptivity->adajust_igi_level - IGI;
|
||||
|
@ -1010,45 +797,23 @@ phydm_pause_edcca(
|
|||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("pauseEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", adaptivity->backup_l2h, adaptivity->backup_h2l, IGI));
|
||||
|
||||
/*Disable EDCCA*/
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
if (odm_is_work_item_scheduled(&(adaptivity->phydm_pause_edcca_work_item)) == false)
|
||||
odm_schedule_work_item(&(adaptivity->phydm_pause_edcca_work_item));
|
||||
#else
|
||||
phydm_pause_edcca_work_item_callback(p_dm_odm);
|
||||
#endif
|
||||
|
||||
} else {
|
||||
|
||||
adaptivity->is_stop_edcca = false;
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("resumeEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", adaptivity->backup_l2h, adaptivity->backup_h2l, IGI));
|
||||
/*Resume EDCCA*/
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
if (odm_is_work_item_scheduled(&(adaptivity->phydm_resume_edcca_work_item)) == false)
|
||||
odm_schedule_work_item(&(adaptivity->phydm_resume_edcca_work_item));
|
||||
#else
|
||||
phydm_resume_edcca_work_item_callback(p_dm_odm);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
phydm_pause_edcca_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#else
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#endif
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)
|
||||
odm_set_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)(0x7f | 0x7f << 16));
|
||||
|
@ -1061,19 +826,10 @@ phydm_pause_edcca_work_item_callback(
|
|||
|
||||
void
|
||||
phydm_resume_edcca_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#else
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#endif
|
||||
struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY);
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)
|
||||
|
|
|
@ -27,17 +27,6 @@
|
|||
#define pwdb_upper_bound 7
|
||||
#define dfir_loss 5
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
|
||||
enum phydm_regulation_type {
|
||||
REGULATION_FCC = 0,
|
||||
REGULATION_MKK = 1,
|
||||
REGULATION_ETSI = 2,
|
||||
REGULATION_WW = 3,
|
||||
|
||||
MAX_REGULATION_NUM = 4
|
||||
};
|
||||
#endif
|
||||
|
||||
enum phydm_adapinfo_e {
|
||||
PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0,
|
||||
PHYDM_ADAPINFO_DCBACKOFF,
|
||||
|
@ -45,11 +34,8 @@ enum phydm_adapinfo_e {
|
|||
PHYDM_ADAPINFO_TH_L2H_INI,
|
||||
PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF,
|
||||
PHYDM_ADAPINFO_AP_NUM_TH
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
enum phydm_set_lna {
|
||||
phydm_disable_lna = 0,
|
||||
phydm_enable_lna = 1,
|
||||
|
@ -85,10 +71,6 @@ struct _ADAPTIVITY_STATISTICS {
|
|||
s8 backup_l2h;
|
||||
s8 backup_h2l;
|
||||
bool is_stop_edcca;
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
RT_WORK_ITEM phydm_pause_edcca_work_item;
|
||||
RT_WORK_ITEM phydm_resume_edcca_work_item;
|
||||
#endif
|
||||
};
|
||||
|
||||
void
|
||||
|
@ -180,40 +162,14 @@ phydm_set_edcca_threshold_api(
|
|||
u8 IGI
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void
|
||||
phydm_disable_edcca(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_dynamic_edcca(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
phydm_adaptivity_bsod(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
void
|
||||
phydm_pause_edcca_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
);
|
||||
|
||||
void
|
||||
phydm_resume_edcca_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -1,26 +1,9 @@
|
|||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
#if ((RTL8197F_SUPPORT == 1) || (RTL8822B_SUPPORT == 1))
|
||||
#include "rtl8197f/Hal8197FPhyReg.h"
|
||||
#include "WlanHAL/HalMac88XX/halmac_reg2.h"
|
||||
#else
|
||||
#include "WlanHAL/HalHeader/HalComReg.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (PHYDM_LA_MODE_SUPPORT == 1)
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
|
||||
#if WPP_SOFTWARE_TRACE
|
||||
#include "phydm_adc_sampling.tmh"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
bool
|
||||
phydm_la_buffer_allocate(
|
||||
void *p_dm_void
|
||||
|
@ -36,12 +19,8 @@ phydm_la_buffer_allocate(
|
|||
|
||||
if (adc_smp_buf->length == 0) {
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
if (PlatformAllocateMemoryWithZero(adapter, (void **)&(adc_smp_buf->octet), adc_smp_buf->buffer_size) != RT_STATUS_SUCCESS) {
|
||||
#else
|
||||
odm_allocate_memory(p_dm_odm, (void **)&adc_smp_buf->octet, adc_smp_buf->buffer_size);
|
||||
if (!adc_smp_buf->octet) {
|
||||
#endif
|
||||
ret = false;
|
||||
} else
|
||||
adc_smp_buf->length = adc_smp_buf->buffer_size;
|
||||
|
@ -50,7 +29,6 @@ phydm_la_buffer_allocate(
|
|||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
void
|
||||
phydm_la_get_tx_pkt_buf(
|
||||
|
@ -92,14 +70,6 @@ phydm_la_get_tx_pkt_buf(
|
|||
dbg_print("is_round_up = ((%d)), finish_addr=((0x%x * 8Byte)), Start_Addr = ((0x%x * 8Byte)), smp_number = ((%d))\n", is_round_up, finish_addr, addr_8byte, smp_number);
|
||||
|
||||
}
|
||||
/*
|
||||
dbg_print("is_round_up = %d, finish_addr=0x%x, value32=0x%x\n", is_round_up, finish_addr, value32);
|
||||
dbg_print("end_addr = %x, adc_smp_buf->start_pos = 0x%x, adc_smp_buf->buffer_size = 0x%x\n", end_addr, adc_smp_buf->start_pos, adc_smp_buf->buffer_size);
|
||||
*/
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
watchdog_stop(p_dm_odm->priv);
|
||||
#endif
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8197F) {
|
||||
for (addr = 0x0, i = 0; addr < end_addr; addr += 8, i += 2) { /*64K byte*/
|
||||
if ((addr & 0xfff) == 0)
|
||||
|
@ -121,19 +91,12 @@ phydm_la_get_tx_pkt_buf(
|
|||
data_l = odm_get_bb_reg(p_dm_odm, 0x8000 + (addr & 0xfff), MASKDWORD);
|
||||
data_h = odm_get_bb_reg(p_dm_odm, 0x8000 + (addr & 0xfff) + 4, MASKDWORD);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
adc_smp_buf->octet[i] = data_h;
|
||||
adc_smp_buf->octet[i + 1] = data_l;
|
||||
#endif
|
||||
|
||||
#if DBG
|
||||
dbg_print("%08x%08x\n", data_h, data_l);
|
||||
#else
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("%08x%08x\n", adc_smp_buf->octet[i], adc_smp_buf->octet[i + 1]));
|
||||
#endif
|
||||
#endif
|
||||
|
||||
i = i + 2;
|
||||
|
||||
if ((addr + 8) >= end_addr)
|
||||
|
@ -146,14 +109,7 @@ phydm_la_get_tx_pkt_buf(
|
|||
break;
|
||||
}
|
||||
dbg_print("smp_cnt = ((%d))\n", smp_cnt);
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("smp_cnt = ((%d))\n", smp_cnt));
|
||||
#endif
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
watchdog_resume(p_dm_odm->priv);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
|
@ -198,10 +154,6 @@ phydm_la_mode_set_mac_iq_dump(
|
|||
|
||||
reg_value = odm_get_bb_reg(p_dm_odm, 0x7c0, 0xff);
|
||||
dbg_print("4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value);
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value));
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
|
@ -213,10 +165,6 @@ phydm_la_mode_set_dma_type(
|
|||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
|
||||
dbg_print("2. [LA mode DMA setting] Dma_type = ((%d))\n", la_dma_type);
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("2. [LA mode DMA setting] Dma_type = ((%d))\n", la_dma_type));
|
||||
#endif
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_N_ANTDIV_SUPPORT)
|
||||
odm_set_bb_reg(p_dm_odm, 0x9a0, 0xf00, la_dma_type); /*0x9A0[11:8]*/
|
||||
else
|
||||
|
@ -248,9 +196,6 @@ phydm_adc_smp_start(
|
|||
|
||||
phydm_la_mode_set_mac_iq_dump(p_dm_odm);
|
||||
/* return; */
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
watchdog_stop(p_dm_odm->priv);
|
||||
#endif
|
||||
|
||||
target_polling_bit = (adc_smp->is_bb_trigger) ? BIT(1) : BIT(2);
|
||||
do { /*Polling time always use 100ms, when it exceed 2s, break while loop*/
|
||||
|
@ -273,23 +218,6 @@ phydm_adc_smp_start(
|
|||
}
|
||||
} while (while_cnt < 20);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
watchdog_resume(p_dm_odm->priv);
|
||||
#if (RTL8197F_SUPPORT)
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8197F) {
|
||||
/*Stop DMA*/
|
||||
backup_DMA = odm_get_mac_reg(p_dm_odm, 0x300, MASKLWORD);
|
||||
odm_set_mac_reg(p_dm_odm, 0x300, 0x7fff, backup_DMA | 0x7fff);
|
||||
|
||||
/*move LA mode content from IMEM to TxPktBuffer
|
||||
Src : OCPBASE_IMEM 0x00000000
|
||||
Dest : OCPBASE_TXBUF 0x18780000
|
||||
Len : 64K*/
|
||||
GET_HAL_INTERFACE(p_dm_odm->priv)->init_ddma_handler(p_dm_odm->priv, OCPBASE_IMEM, OCPBASE_TXBUF, 0x10000);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
if (adc_smp->adc_smp_state == ADCSMP_STATE_SET) {
|
||||
|
||||
if (polling_ok)
|
||||
|
@ -298,21 +226,10 @@ phydm_adc_smp_start(
|
|||
dbg_print("[Polling timeout]\n");
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8197F)
|
||||
odm_set_mac_reg(p_dm_odm, 0x300, 0x7fff, backup_DMA); /*Resume DMA*/
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
if (adc_smp->adc_smp_state == ADCSMP_STATE_SET)
|
||||
adc_smp->adc_smp_state = ADCSMP_STATE_QUERY;
|
||||
#endif
|
||||
|
||||
dbg_print("[LA mode] LA_pattern_count = ((%d))\n", adc_smp->la_count);
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("[LA mode] la_count = ((%d))\n", adc_smp->la_count));
|
||||
#endif
|
||||
|
||||
|
||||
adc_smp_stop(p_dm_odm);
|
||||
|
||||
|
@ -327,22 +244,6 @@ phydm_adc_smp_start(
|
|||
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
void
|
||||
adc_smp_work_item_callback(
|
||||
void *p_context
|
||||
)
|
||||
{
|
||||
struct _ADAPTER *adapter = (struct _ADAPTER *)p_context;
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp);
|
||||
|
||||
dbg_print("[WorkItem Call back] LA_State=((%d))\n", adc_smp->adc_smp_state);
|
||||
phydm_adc_smp_start(p_dm_odm);
|
||||
}
|
||||
#endif
|
||||
|
||||
void
|
||||
adc_smp_set(
|
||||
void *p_dm_void,
|
||||
|
@ -362,75 +263,23 @@ adc_smp_set(
|
|||
adc_smp->la_dma_type = dma_data_sig_sel;
|
||||
adc_smp->la_trigger_time = trigger_time;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
if (adc_smp->adc_smp_state != ADCSMP_STATE_IDLE)
|
||||
is_set_success = false;
|
||||
else if (adc_smp->adc_smp_buf.length == 0)
|
||||
is_set_success = phydm_la_buffer_allocate(p_dm_odm);
|
||||
#endif
|
||||
|
||||
if (is_set_success) {
|
||||
adc_smp->adc_smp_state = ADCSMP_STATE_SET;
|
||||
|
||||
dbg_print("[LA Set Success] LA_State=((%d))\n", adc_smp->adc_smp_state);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
|
||||
dbg_print("ADCSmp_work_item_index = ((%d))\n", adc_smp->la_work_item_index);
|
||||
if (adc_smp->la_work_item_index != 0) {
|
||||
odm_schedule_work_item(&(adc_smp->adc_smp_work_item_1));
|
||||
adc_smp->la_work_item_index = 0;
|
||||
} else {
|
||||
odm_schedule_work_item(&(adc_smp->adc_smp_work_item));
|
||||
adc_smp->la_work_item_index = 1;
|
||||
}
|
||||
#else
|
||||
phydm_adc_smp_start(p_dm_odm);
|
||||
#endif
|
||||
} else
|
||||
dbg_print("[LA Set Fail] LA_State=((%d))\n", adc_smp->adc_smp_state);
|
||||
|
||||
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
enum rt_status
|
||||
adc_smp_query(
|
||||
void *p_dm_void,
|
||||
ULONG information_buffer_length,
|
||||
void *information_buffer,
|
||||
PULONG bytes_written
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp);
|
||||
enum rt_status ret_status = RT_STATUS_SUCCESS;
|
||||
struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf);
|
||||
|
||||
dbg_print("[%s] LA_State=((%d))", __func__, adc_smp->adc_smp_state);
|
||||
|
||||
if (information_buffer_length != adc_smp_buf->buffer_size) {
|
||||
*bytes_written = 0;
|
||||
ret_status = RT_STATUS_RESOURCE;
|
||||
} else if (adc_smp_buf->length != adc_smp_buf->buffer_size) {
|
||||
*bytes_written = 0;
|
||||
ret_status = RT_STATUS_RESOURCE;
|
||||
} else if (adc_smp->adc_smp_state != ADCSMP_STATE_QUERY) {
|
||||
*bytes_written = 0;
|
||||
ret_status = RT_STATUS_PENDING;
|
||||
} else {
|
||||
odm_move_memory(p_dm_odm, information_buffer, adc_smp_buf->octet, adc_smp_buf->buffer_size);
|
||||
*bytes_written = adc_smp_buf->buffer_size;
|
||||
|
||||
adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
|
||||
}
|
||||
|
||||
dbg_print("Return status %d\n", ret_status);
|
||||
|
||||
return ret_status;
|
||||
}
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
|
||||
void
|
||||
adc_smp_query(
|
||||
void *p_dm_void,
|
||||
|
@ -498,8 +347,6 @@ adc_smp_query_single_data(
|
|||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
void
|
||||
adc_smp_stop(
|
||||
void *p_dm_void
|
||||
|
@ -539,7 +386,6 @@ adc_smp_init(
|
|||
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
void
|
||||
adc_smp_de_init(
|
||||
void *p_dm_void
|
||||
|
@ -557,9 +403,6 @@ adc_smp_de_init(
|
|||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
void
|
||||
phydm_la_mode_bb_setting(
|
||||
void *p_dm_void
|
||||
|
@ -577,11 +420,6 @@ phydm_la_mode_bb_setting(
|
|||
dbg_print("1. [LA mode bb_setting] trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x))\n",
|
||||
trig_mode, dbg_port, is_trigger_edge, sampling_rate, trig_sig_sel);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("1. [LA mode bb_setting]trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x))\n",
|
||||
trig_mode, dbg_port, is_trigger_edge, sampling_rate, trig_sig_sel));
|
||||
#endif
|
||||
|
||||
if (trig_mode == PHYDM_MAC_TRIG)
|
||||
trig_sig_sel = 0; /*ignore this setting*/
|
||||
|
||||
|
@ -671,16 +509,12 @@ phydm_la_mode_set_trigger_time(
|
|||
trigger_time_unit_num = (u8)(trigger_time_mu_sec >> time_unit);
|
||||
|
||||
dbg_print("3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", trigger_time_unit_num, time_unit);
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", trigger_time_unit_num, time_unit));
|
||||
#endif
|
||||
|
||||
odm_set_mac_reg(p_dm_odm, 0x7cc, BIT(20) | BIT(19) | BIT(18), time_unit);
|
||||
odm_set_mac_reg(p_dm_odm, 0x7c0, 0x7f00, (trigger_time_unit_num & 0x7f));
|
||||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
phydm_lamode_trigger_setting(
|
||||
void *p_dm_void,
|
||||
|
@ -744,10 +578,6 @@ phydm_lamode_trigger_setting(
|
|||
|
||||
|
||||
dbg_print("echo lamode %d %d %d %d %d %d %x %d %d %d\n", var1[0], var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], var1[7], var1[8], var1[9]);
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("echo lamode %d %d %d %d %d %d %x %d %d %d\n", var1[0], var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], var1[7], var1[8], var1[9]));
|
||||
#endif
|
||||
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "a.En= ((1)), b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n", trig_mode, trig_sig_sel, dma_data_sig_sel));
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "e.Trig_Time = ((%dus)), f.mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n", trigger_time_mu_sec, adc_smp->la_mac_ref_mask, adc_smp->la_dbg_port));
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n", adc_smp->la_trigger_edge, (80 >> adc_smp->la_smp_rate), adc_smp->la_count));
|
||||
|
|
|
@ -51,20 +51,8 @@ struct _RT_ADCSMP {
|
|||
u32 la_count;
|
||||
u8 is_bb_trigger;
|
||||
u8 la_work_item_index;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
RT_WORK_ITEM adc_smp_work_item;
|
||||
RT_WORK_ITEM adc_smp_work_item_1;
|
||||
#endif
|
||||
};
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
void
|
||||
adc_smp_work_item_callback(
|
||||
void *p_context
|
||||
);
|
||||
#endif
|
||||
|
||||
void
|
||||
adc_smp_set(
|
||||
void *p_dm_void,
|
||||
|
@ -75,15 +63,6 @@ adc_smp_set(
|
|||
u16 polling_time
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
enum rt_status
|
||||
adc_smp_query(
|
||||
void *p_dm_void,
|
||||
ULONG information_buffer_length,
|
||||
void *information_buffer,
|
||||
PULONG bytes_written
|
||||
);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
void
|
||||
adc_smp_query(
|
||||
void *p_dm_void,
|
||||
|
@ -105,7 +84,6 @@ adc_smp_query_single_data(
|
|||
u32 index
|
||||
);
|
||||
|
||||
#endif
|
||||
void
|
||||
adc_smp_stop(
|
||||
void *p_dm_void
|
||||
|
@ -116,12 +94,10 @@ adc_smp_init(
|
|||
void *p_dm_void
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
void
|
||||
adc_smp_de_init(
|
||||
void *p_dm_void
|
||||
);
|
||||
#endif
|
||||
|
||||
void
|
||||
phydm_la_mode_bb_setting(
|
||||
|
|
|
@ -25,7 +25,6 @@
|
|||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
/* #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */
|
||||
#if (defined(CONFIG_ANT_DETECTION))
|
||||
|
||||
/* IS_ANT_DETECT_SUPPORT_SINGLE_TONE(adapter)
|
||||
|
|
|
@ -24,7 +24,6 @@
|
|||
#define ANTDECT_VERSION "2.1" /*2015.07.29 by YuChen*/
|
||||
|
||||
#if (defined(CONFIG_ANT_DETECTION))
|
||||
/* #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */
|
||||
/* ANT Test */
|
||||
#define ANTTESTALL 0x00 /*ant A or B will be Testing*/
|
||||
#define ANTTESTA 0x01 /*ant A will be Testing*/
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -151,12 +151,6 @@ struct _sw_antenna_switch_ {
|
|||
u32 pkt_cnt_sw_ant_div_by_ctrl_frame;
|
||||
bool is_sw_ant_div_by_ctrl_frame;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#if USE_WORKITEM
|
||||
RT_WORK_ITEM phydm_sw_antenna_switch_workitem;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* AntDect (Before link Antenna Switch check) need to be moved*/
|
||||
u16 single_ant_counter;
|
||||
u16 dual_ant_counter;
|
||||
|
@ -170,42 +164,8 @@ struct _sw_antenna_switch_ {
|
|||
bool rssi_ant_dect_result;
|
||||
u8 ant_5g;
|
||||
u8 ant_2g;
|
||||
|
||||
|
||||
};
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
|
||||
struct _BF_DIV_COEX_ {
|
||||
bool w_bfer_client[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
bool w_bfee_client[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u32 MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
u32 MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM];
|
||||
|
||||
u8 bd_ccoex_type_wbfer;
|
||||
u8 num_txbfee_client;
|
||||
u8 num_txbfer_client;
|
||||
u8 bdc_try_counter;
|
||||
u8 bdc_hold_counter;
|
||||
u8 bdc_mode;
|
||||
u8 bdc_active_mode;
|
||||
u8 BDC_state;
|
||||
u8 bdc_rx_idle_update_counter;
|
||||
u8 num_client;
|
||||
u8 pre_num_client;
|
||||
u8 num_bf_tar;
|
||||
u8 num_div_tar;
|
||||
|
||||
bool is_all_div_sta_idle;
|
||||
bool is_all_bf_sta_idle;
|
||||
bool bdc_try_flag;
|
||||
bool BF_pass;
|
||||
bool DIV_pass;
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
|
||||
struct _SMART_ANTENNA_TRAINNING_ {
|
||||
u32 latch_time;
|
||||
|
@ -237,12 +197,6 @@ struct _SMART_ANTENNA_TRAINNING_ {
|
|||
u32 beacon_counter;
|
||||
u32 pre_beacon_counter;
|
||||
u8 update_beam_idx;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
RT_WORK_ITEM hl_smart_antenna_workitem;
|
||||
RT_WORK_ITEM hl_smart_antenna_decision_workitem;
|
||||
#endif
|
||||
|
||||
};
|
||||
#endif
|
||||
|
||||
|
@ -296,7 +250,6 @@ struct _FAST_ANTENNA_TRAINNING_ {
|
|||
u32 main_crc32_fail_cnt;
|
||||
u32 aux_crc32_fail_cnt;
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
u32 cck_ctrl_frame_cnt_main;
|
||||
u32 cck_ctrl_frame_cnt_aux;
|
||||
u32 ofdm_ctrl_frame_cnt_main;
|
||||
|
@ -305,7 +258,6 @@ struct _FAST_ANTENNA_TRAINNING_ {
|
|||
u32 aux_ant_ctrl_frame_sum;
|
||||
u32 main_ant_ctrl_frame_cnt;
|
||||
u32 aux_ant_ctrl_frame_cnt;
|
||||
#endif
|
||||
u8 b_fix_tx_ant;
|
||||
bool fix_ant_bfee;
|
||||
bool enable_ctrl_frame_antdiv;
|
||||
|
@ -417,20 +369,6 @@ phydm_set_tx_ant_pwr_8723d(
|
|||
|
||||
#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void
|
||||
odm_sw_antdiv_callback(
|
||||
struct timer_list *p_timer
|
||||
);
|
||||
|
||||
void
|
||||
odm_sw_antdiv_workitem_callback(
|
||||
void *p_context
|
||||
);
|
||||
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
|
||||
void
|
||||
odm_sw_antdiv_workitem_callback(
|
||||
void *p_context
|
||||
|
@ -441,8 +379,6 @@ odm_sw_antdiv_callback(
|
|||
void *function_context
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
void
|
||||
odm_s0s1_sw_ant_div_by_ctrl_frame(
|
||||
void *p_dm_void,
|
||||
|
@ -497,19 +433,6 @@ odm_fast_ant_training_work_item_callback(
|
|||
|
||||
#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void
|
||||
phydm_beam_switch_workitem_callback(
|
||||
void *p_context
|
||||
);
|
||||
|
||||
void
|
||||
phydm_beam_decision_workitem_callback(
|
||||
void *p_context
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
void
|
||||
phydm_update_beam_pattern(
|
||||
void *p_dm_void,
|
||||
|
@ -562,7 +485,6 @@ odm_process_rssi_for_ant_div(
|
|||
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
void
|
||||
odm_set_tx_ant_by_tx_info(
|
||||
void *p_dm_void,
|
||||
|
@ -570,28 +492,6 @@ odm_set_tx_ant_by_tx_info(
|
|||
u8 mac_id
|
||||
);
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
|
||||
struct tx_desc; /*declared tx_desc here or compile error happened when enabled 8822B*/
|
||||
|
||||
void
|
||||
odm_set_tx_ant_by_tx_info(
|
||||
struct rtl8192cd_priv *priv,
|
||||
struct tx_desc *pdesc,
|
||||
unsigned short aid
|
||||
);
|
||||
|
||||
#if 1/*def def CONFIG_WLAN_HAL*/
|
||||
void
|
||||
odm_set_tx_ant_by_tx_info_hal(
|
||||
struct rtl8192cd_priv *priv,
|
||||
void *pdesc_data,
|
||||
u16 aid
|
||||
);
|
||||
#endif /*#ifdef CONFIG_WLAN_HAL*/
|
||||
#endif
|
||||
|
||||
|
||||
void
|
||||
odm_ant_div_config(
|
||||
void *p_dm_void
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -26,7 +26,6 @@ odm_set_crystal_cap(
|
|||
u8 crystal_cap
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK);
|
||||
|
||||
|
@ -62,7 +61,6 @@ odm_set_crystal_cap(
|
|||
}
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_set_crystal_cap(): crystal_cap = 0x%x\n", crystal_cap));
|
||||
#endif
|
||||
}
|
||||
|
||||
static u8
|
||||
|
@ -73,17 +71,10 @@ odm_get_default_crytaltal_cap(
|
|||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u8 crystal_cap = 0x20;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
|
||||
crystal_cap = p_hal_data->crystal_cap;
|
||||
#else
|
||||
struct rtl8192cd_priv *priv = p_dm_odm->priv;
|
||||
|
||||
if (priv->pmib->dot11RFEntry.xcap > 0)
|
||||
crystal_cap = priv->pmib->dot11RFEntry.xcap;
|
||||
#endif
|
||||
|
||||
crystal_cap = crystal_cap & 0x3f;
|
||||
|
||||
|
@ -138,10 +129,7 @@ odm_cfo_tracking_reset(
|
|||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD,
|
||||
("odm_cfo_tracking_reset(): approch default value (0x%x)\n", p_cfo_track->crystal_cap));
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
odm_set_atc_status(p_dm_odm, true);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
|
@ -260,25 +248,12 @@ odm_cfo_tracking(
|
|||
p_cfo_track->is_adjust = false;
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
/* 4 1.5 BT case: Disable CFO tracking */
|
||||
if (p_dm_odm->is_bt_enabled) {
|
||||
p_cfo_track->is_adjust = false;
|
||||
odm_set_crystal_cap(p_dm_odm, p_cfo_track->def_x_cap);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Disable CFO tracking for BT!!\n"));
|
||||
}
|
||||
#if 0
|
||||
/* 4 1.6 Big jump */
|
||||
if (p_cfo_track->is_adjust) {
|
||||
if (CFO_ave > CFO_TH_XTAL_LOW)
|
||||
adjust_xtal = adjust_xtal + ((CFO_ave - CFO_TH_XTAL_LOW) >> 2);
|
||||
else if (CFO_ave < (-CFO_TH_XTAL_LOW))
|
||||
adjust_xtal = adjust_xtal + ((CFO_TH_XTAL_LOW - CFO_ave) >> 2);
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Crystal cap offset = %d\n", adjust_xtal));
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* 4 1.7 Adjust Crystal Cap. */
|
||||
if (p_cfo_track->is_adjust) {
|
||||
|
@ -297,7 +272,6 @@ odm_cfo_tracking(
|
|||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Crystal cap = 0x%x, Default Crystal cap = 0x%x\n",
|
||||
p_cfo_track->crystal_cap, p_cfo_track->def_x_cap));
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES)
|
||||
return;
|
||||
|
||||
|
@ -309,7 +283,6 @@ odm_cfo_tracking(
|
|||
odm_set_atc_status(p_dm_odm, true);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Enable ATC!!\n"));
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -329,18 +302,10 @@ odm_parsing_cfo(
|
|||
if (!(p_dm_odm->support_ability & ODM_BB_CFO_TRACKING))
|
||||
return;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
if (p_pktinfo->is_packet_match_bssid)
|
||||
#else
|
||||
if (p_pktinfo->station_id != 0)
|
||||
#endif
|
||||
{
|
||||
if (p_pktinfo->is_packet_match_bssid) {
|
||||
if (num_ss > p_dm_odm->num_rf_path) /*For fool proof*/
|
||||
num_ss = p_dm_odm->num_rf_path;
|
||||
|
||||
/*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("num_ss = ((%d)), p_dm_odm->num_rf_path = ((%d))\n", num_ss, p_dm_odm->num_rf_path));*/
|
||||
|
||||
|
||||
/* 3 Update CFO report for path-A & path-B */
|
||||
/* Only paht-A and path-B have CFO tail and short CFO */
|
||||
for (i = 0; i < num_ss; i++) {
|
||||
|
|
|
@ -876,70 +876,12 @@ phydm_bb_debug_info(
|
|||
}
|
||||
#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
|
||||
#if CONFIG_PHYDM_DEBUG_FUNCTION
|
||||
void phydm_sbd_check(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
)
|
||||
{
|
||||
static u32 pkt_cnt = 0;
|
||||
static bool sbd_state = 0;
|
||||
u32 sym_count, count, value32;
|
||||
|
||||
if (sbd_state == 0) {
|
||||
pkt_cnt++;
|
||||
if (pkt_cnt % 5 == 0) { /*read SBD conter once every 5 packets*/
|
||||
odm_set_timer(p_dm_odm, &p_dm_odm->sbdcnt_timer, 0); /*ms*/
|
||||
sbd_state = 1;
|
||||
}
|
||||
} else { /*read counter*/
|
||||
value32 = odm_get_bb_reg(p_dm_odm, 0xF98, MASKDWORD);
|
||||
sym_count = (value32 & 0x7C000000) >> 26;
|
||||
count = (value32 & 0x3F00000) >> 20;
|
||||
dbg_print("#SBD# sym_count %d count %d\n", sym_count, count);
|
||||
sbd_state = 0;
|
||||
}
|
||||
}
|
||||
#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/
|
||||
|
||||
void phydm_sbd_callback(
|
||||
struct timer_list *p_timer
|
||||
)
|
||||
{
|
||||
#if CONFIG_PHYDM_DEBUG_FUNCTION
|
||||
struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->Adapter;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
|
||||
#if USE_WORKITEM
|
||||
odm_schedule_work_item(&p_dm_odm->sbdcnt_workitem);
|
||||
#else
|
||||
phydm_sbd_check(p_dm_odm);
|
||||
#endif
|
||||
#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/
|
||||
}
|
||||
|
||||
void phydm_sbd_workitem_callback(
|
||||
void *p_context
|
||||
)
|
||||
{
|
||||
#if CONFIG_PHYDM_DEBUG_FUNCTION
|
||||
struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
|
||||
phydm_sbd_check(p_dm_odm);
|
||||
#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/
|
||||
}
|
||||
#endif
|
||||
void
|
||||
phydm_basic_dbg_message
|
||||
(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT);
|
||||
struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK);
|
||||
|
@ -1026,25 +968,8 @@ phydm_basic_dbg_message
|
|||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("is_linked = %d, Num_client = %d, rssi_min = %d, current_igi = 0x%x, bNoisy=%d\n\n",
|
||||
p_dm_odm->is_linked, p_dm_odm->number_linked_client, p_dm_odm->rssi_min, p_dm_dig_table->cur_ig_value, p_dm_odm->noisy_decision));
|
||||
|
||||
/*
|
||||
temp_reg = odm_get_bb_reg(p_dm_odm, 0xDD0, MASKBYTE0);
|
||||
ODM_RT_TRACE(p_dm_odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("0xDD0 = 0x%x\n",temp_reg));
|
||||
|
||||
temp_reg = odm_get_bb_reg(p_dm_odm, 0xDDc, MASKBYTE1);
|
||||
ODM_RT_TRACE(p_dm_odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("0xDDD = 0x%x\n",temp_reg));
|
||||
|
||||
temp_reg = odm_get_bb_reg(p_dm_odm, 0xc50, MASKBYTE0);
|
||||
ODM_RT_TRACE(p_dm_odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("0xC50 = 0x%x\n",temp_reg));
|
||||
|
||||
temp_reg = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0, 0x3fe0);
|
||||
ODM_RT_TRACE(p_dm_odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RF 0x0[13:5] = 0x%x\n\n",temp_reg));
|
||||
*/
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void phydm_basic_profile(
|
||||
void *p_dm_void,
|
||||
u32 *_used,
|
||||
|
@ -1199,23 +1124,11 @@ void phydm_basic_profile(
|
|||
PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "PHY Parameter Commit by", commit_by));
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d\n", "PHY Parameter Release version", release_ver));
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
{
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW version", adapter->MgntInfo.FirmwareVersion, adapter->MgntInfo.FirmwareSubVersion));
|
||||
}
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
{
|
||||
struct rtl8192cd_priv *priv = p_dm_odm->priv;
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW version", priv->pshare->fw_version, priv->pshare->fw_sub_version));
|
||||
}
|
||||
#else
|
||||
{
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW version", p_hal_data->firmware_version, p_hal_data->firmware_sub_version));
|
||||
}
|
||||
#endif
|
||||
/* 1 PHY DM version List */
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "% PHYDM version %"));
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Code base", PHYDM_CODE_BASE));
|
||||
|
@ -1228,9 +1141,6 @@ void phydm_basic_profile(
|
|||
PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Power Tracking", POWRTRACKING_VERSION));
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Dynamic TxPower", DYNAMIC_TXPWR_VERSION));
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "RA Info", RAINFO_VERSION));
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Antenna Detection", ANTDECT_VERSION));
|
||||
#endif
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Auto channel Selection", ACS_VERSION));
|
||||
#if PHYDM_SUPPORT_EDCA
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "EDCA Turbo", EDCATURBO_VERSION));
|
||||
|
@ -1239,15 +1149,6 @@ void phydm_basic_profile(
|
|||
PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "LA mode", DYNAMIC_LA_MODE));
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Dynamic RX path", DYNAMIC_RX_PATH_VERSION));
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8822B)
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "PHY config 8822B", PHY_CONFIG_VERSION_8822B));
|
||||
|
||||
#endif
|
||||
#if (RTL8197F_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8197F)
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "PHY config 8197F", PHY_CONFIG_VERSION_8197F));
|
||||
#endif
|
||||
*_used = used;
|
||||
*_out_len = out_len;
|
||||
#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/
|
||||
|
@ -1308,45 +1209,6 @@ phydm_api_set_txagc(
|
|||
{
|
||||
bool ret = false;
|
||||
|
||||
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1))
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
|
||||
if (is_single_rate) {
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8822B)
|
||||
ret = phydm_write_txagc_1byte_8822b(p_dm_odm, power_index, path, hw_rate);
|
||||
#endif
|
||||
#if (RTL8821C_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8821C)
|
||||
ret = phydm_write_txagc_1byte_8821c(p_dm_odm, power_index, path, hw_rate);
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
set_current_tx_agc(p_dm_odm->priv, path, hw_rate, (u8)power_index);
|
||||
#endif
|
||||
|
||||
} else {
|
||||
u8 i;
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8822B)
|
||||
ret = config_phydm_write_txagc_8822b(p_dm_odm, power_index, path, hw_rate);
|
||||
#endif
|
||||
#if (RTL8821C_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8821C)
|
||||
ret = config_phydm_write_txagc_8821c(p_dm_odm, power_index, path, hw_rate);
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
for (i = 0; i < 4; i++)
|
||||
set_current_tx_agc(p_dm_odm->priv, path, (hw_rate + i), (u8)power_index);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#if (RTL8197F_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8197F)
|
||||
ret = config_phydm_write_txagc_8197f(p_dm_odm, power_index, path, hw_rate);
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
@ -1359,21 +1221,6 @@ phydm_api_get_txagc(
|
|||
{
|
||||
u8 ret = 0;
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8822B)
|
||||
ret = config_phydm_read_txagc_8822b(p_dm_odm, path, hw_rate);
|
||||
#endif
|
||||
|
||||
#if (RTL8197F_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8197F)
|
||||
ret = config_phydm_read_txagc_8197f(p_dm_odm, path, hw_rate);
|
||||
#endif
|
||||
|
||||
#if (RTL8821C_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8821C)
|
||||
ret = config_phydm_read_txagc_8821c(p_dm_odm, path, hw_rate);
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
@ -1388,21 +1235,6 @@ phydm_api_switch_bw_channel(
|
|||
{
|
||||
bool ret = false;
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8822B)
|
||||
ret = config_phydm_switch_channel_bw_8822b(p_dm_odm, central_ch, primary_ch_idx, bandwidth);
|
||||
#endif
|
||||
|
||||
#if (RTL8197F_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8197F)
|
||||
ret = config_phydm_switch_channel_bw_8197f(p_dm_odm, central_ch, primary_ch_idx, bandwidth);
|
||||
#endif
|
||||
|
||||
#if (RTL8821C_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8821C)
|
||||
ret = config_phydm_switch_channel_bw_8821c(p_dm_odm, central_ch, primary_ch_idx, bandwidth);
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
@ -1970,12 +1802,7 @@ phydm_cmd_parser(
|
|||
|
||||
case PHYDM_DEMO: { /*echo demo 10 0x3a z abcde >cmd*/
|
||||
u32 directory = 0;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
|
||||
char char_temp;
|
||||
#else
|
||||
u32 char_temp = ' ';
|
||||
#endif
|
||||
|
||||
PHYDM_SSCANF(input[1], DCMD_DECIMAL, &directory);
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "Decimal value = %d\n", directory));
|
||||
|
@ -2397,7 +2224,6 @@ phydm_cmd_parser(
|
|||
break;
|
||||
|
||||
case PHYDM_DFS:
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
{
|
||||
u32 var[6] = {0};
|
||||
|
||||
|
@ -2411,19 +2237,9 @@ phydm_cmd_parser(
|
|||
if (input_idx >= 1)
|
||||
phydm_dfs_debug(p_dm_odm, var, &used, output, &out_len);
|
||||
}
|
||||
#endif
|
||||
break;
|
||||
|
||||
case PHYDM_IQK:
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
phy_iq_calibrate(p_dm_odm->priv);
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "IQK !!\n"));
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
phy_iq_calibrate(p_dm_odm->adapter, false);
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "IQK !!\n"));
|
||||
#endif
|
||||
break;
|
||||
|
||||
case PHYDM_NHM:
|
||||
{
|
||||
u8 target_rssi;
|
||||
|
@ -2588,7 +2404,6 @@ phydm_cmd_parser(
|
|||
|
||||
case PHYDM_TXBF:
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info;
|
||||
|
||||
|
@ -2605,7 +2420,6 @@ phydm_cmd_parser(
|
|||
PHYDM_SNPRINTF((output + used, out_len - used, "\r\n unknown cmd!!\n"));
|
||||
#else
|
||||
PHYDM_SNPRINTF((output + used, out_len - used, "\r\n no TxBF !!\n"));
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
break;
|
||||
|
@ -2713,7 +2527,6 @@ char *strsep(char **s, const char *ct)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
|
||||
s32
|
||||
phydm_cmd(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
|
@ -2744,8 +2557,6 @@ phydm_cmd(
|
|||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
void
|
||||
phydm_fw_trace_handler(
|
||||
|
@ -3025,22 +2836,11 @@ phydm_fw_trace_handler_8051(
|
|||
extend_c2h_dbg_len = buffer[1];
|
||||
extend_c2h_dbg_content = buffer + 2; /*DbgSeq+DbgContent for show HEX*/
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
RT_DISP(FC2H, C2H_Summary, ("[Extend C2H packet], Extend_c2hSubId=0x%x, extend_c2h_dbg_len=%d\n",
|
||||
extend_c2h_sub_id, extend_c2h_dbg_len));
|
||||
|
||||
RT_DISP_DATA(FC2H, C2H_Summary, "[Extend C2H packet], Content Hex:", extend_c2h_dbg_content, cmd_len - 2);
|
||||
#endif
|
||||
|
||||
go_backfor_aggre_dbg_pkt:
|
||||
i = 0;
|
||||
extend_c2h_dbg_seq = buffer[2];
|
||||
extend_c2h_dbg_content = buffer + 3;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
RT_DISP(FC2H, C2H_Summary, ("[RTKFW, SEQ= %d] :", extend_c2h_dbg_seq));
|
||||
#endif
|
||||
|
||||
for (; ; i++) {
|
||||
fw_debug_trace[i] = extend_c2h_dbg_content[i];
|
||||
if (extend_c2h_dbg_content[i + 1] == '\0') {
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -49,18 +49,14 @@ odm_rf_saving(
|
|||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
|
||||
struct _dynamic_power_saving *p_dm_ps_table = &p_dm_odm->dm_ps_table;
|
||||
u8 rssi_up_bound = 30 ;
|
||||
u8 rssi_low_bound = 25;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
if (p_dm_odm->patch_id == 40) { /* RT_CID_819x_FUNAI_TV */
|
||||
rssi_up_bound = 50 ;
|
||||
rssi_low_bound = 45;
|
||||
}
|
||||
#endif
|
||||
if (p_dm_ps_table->initialize == 0) {
|
||||
|
||||
p_dm_ps_table->reg874 = (odm_get_bb_reg(p_dm_odm, 0x874, MASKDWORD) & 0x1CC000) >> 14;
|
||||
p_dm_ps_table->regc70 = (odm_get_bb_reg(p_dm_odm, 0xc70, MASKDWORD) & BIT(3)) >> 3;
|
||||
p_dm_ps_table->reg85c = (odm_get_bb_reg(p_dm_odm, 0x85c, MASKDWORD) & 0xFF000000) >> 24;
|
||||
|
@ -105,7 +101,6 @@ odm_rf_saving(
|
|||
}
|
||||
p_dm_ps_table->pre_rf_state = p_dm_ps_table->cur_rf_state;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -30,44 +30,10 @@ odm_dynamic_tx_power_init(
|
|||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
PMGNT_INFO p_mgnt_info = &adapter->MgntInfo;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
|
||||
/*if (!IS_HARDWARE_TYPE_8814A(adapter)) {*/
|
||||
/* ODM_RT_TRACE(p_dm_odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, */
|
||||
/* ("odm_dynamic_tx_power_init DynamicTxPowerEnable=%d\n", p_mgnt_info->is_dynamic_tx_power_enable));*/
|
||||
/* return;*/
|
||||
/*} else*/
|
||||
{
|
||||
p_mgnt_info->bDynamicTxPowerEnable = true;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD,
|
||||
("odm_dynamic_tx_power_init DynamicTxPowerEnable=%d\n", p_mgnt_info->bDynamicTxPowerEnable));
|
||||
}
|
||||
|
||||
#if DEV_BUS_TYPE == RT_USB_INTERFACE
|
||||
if (RT_GetInterfaceSelection(adapter) == INTF_SEL1_USB_High_Power) {
|
||||
odm_dynamic_tx_power_save_power_index(p_dm_odm);
|
||||
p_mgnt_info->bDynamicTxPowerEnable = true;
|
||||
} else
|
||||
#else
|
||||
/* so 92c pci do not need dynamic tx power? vivi check it later */
|
||||
p_mgnt_info->bDynamicTxPowerEnable = false;
|
||||
#endif
|
||||
|
||||
|
||||
p_hal_data->LastDTPLvl = tx_high_pwr_level_normal;
|
||||
p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
|
||||
p_dm_odm->last_dtp_lvl = tx_high_pwr_level_normal;
|
||||
p_dm_odm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal;
|
||||
p_dm_odm->tx_agc_ofdm_18_6 = odm_get_bb_reg(p_dm_odm, 0xC24, MASKDWORD); /*TXAGC {18M 12M 9M 6M}*/
|
||||
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
|
@ -76,19 +42,9 @@ odm_dynamic_tx_power_save_power_index(
|
|||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
|
||||
u8 index;
|
||||
u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
for (index = 0; index < 6; index++)
|
||||
p_hal_data->PowerIndex_backup[index] = PlatformEFIORead1Byte(adapter, power_index_reg[index]);
|
||||
|
||||
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
|
@ -97,18 +53,10 @@ odm_dynamic_tx_power_restore_power_index(
|
|||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
|
||||
u8 index;
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
for (index = 0; index < 6; index++)
|
||||
PlatformEFIOWrite1Byte(adapter, power_index_reg[index], p_hal_data->PowerIndex_backup[index]);
|
||||
|
||||
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
|
@ -131,68 +79,8 @@ odm_dynamic_tx_power_nic_ce(
|
|||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
|
||||
#if (RTL8821A_SUPPORT == 1)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u8 val;
|
||||
u8 rssi_tmp = p_dm_odm->rssi_min;
|
||||
|
||||
if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_TXPWR))
|
||||
return;
|
||||
|
||||
if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
|
||||
p_dm_odm->dynamic_tx_high_power_lvl = tx_high_pwr_level_level2;
|
||||
/**/
|
||||
} else if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL1) {
|
||||
p_dm_odm->dynamic_tx_high_power_lvl = tx_high_pwr_level_level1;
|
||||
/**/
|
||||
} else if (rssi_tmp < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
|
||||
p_dm_odm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal;
|
||||
/**/
|
||||
}
|
||||
|
||||
if (p_dm_odm->last_dtp_lvl != p_dm_odm->dynamic_tx_high_power_lvl) {
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("update_DTP_lv: ((%d)) -> ((%d))\n", p_dm_odm->last_dtp_lvl, p_dm_odm->dynamic_tx_high_power_lvl));
|
||||
|
||||
p_dm_odm->last_dtp_lvl = p_dm_odm->dynamic_tx_high_power_lvl;
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8821)) {
|
||||
|
||||
if (p_dm_odm->dynamic_tx_high_power_lvl == tx_high_pwr_level_level2) {
|
||||
|
||||
odm_set_mac_reg(p_dm_odm, 0x6D8, BIT(20) | BIT19 | BIT18, 1); /* Resp TXAGC offset = -3dB*/
|
||||
|
||||
val = p_dm_odm->tx_agc_ofdm_18_6 & 0xff;
|
||||
if (val >= 0x20)
|
||||
val -= 0x16;
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, 0xC24, 0xff, val);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: level 2\n"));
|
||||
} else if (p_dm_odm->dynamic_tx_high_power_lvl == tx_high_pwr_level_level1) {
|
||||
|
||||
odm_set_mac_reg(p_dm_odm, 0x6D8, BIT(20) | BIT19 | BIT18, 1); /* Resp TXAGC offset = -3dB*/
|
||||
|
||||
val = p_dm_odm->tx_agc_ofdm_18_6 & 0xff;
|
||||
if (val >= 0x20)
|
||||
val -= 0x10;
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, 0xC24, 0xff, val);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: level 1\n"));
|
||||
} else if (p_dm_odm->dynamic_tx_high_power_lvl == tx_high_pwr_level_normal) {
|
||||
|
||||
odm_set_mac_reg(p_dm_odm, 0x6D8, BIT(20) | BIT19 | BIT18, 0); /* Resp TXAGC offset = 0dB*/
|
||||
odm_set_bb_reg(p_dm_odm, 0xC24, MASKDWORD, p_dm_odm->tx_agc_ofdm_18_6);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: normal\n"));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_dynamic_tx_power(
|
||||
void *p_dm_void
|
||||
|
@ -239,23 +127,6 @@ odm_dynamic_tx_power_nic(
|
|||
|
||||
if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_TXPWR))
|
||||
return;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8814A)
|
||||
odm_dynamic_tx_power_8814a(p_dm_odm);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8821) {
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
PMGNT_INFO p_mgnt_info = GetDefaultMgntInfo(adapter);
|
||||
|
||||
if (p_mgnt_info->RegRspPwr == 1) {
|
||||
if (p_dm_odm->rssi_min > 60)
|
||||
odm_set_mac_reg(p_dm_odm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT19 | BIT18, 1); /*Resp TXAGC offset = -3dB*/
|
||||
else if (p_dm_odm->rssi_min < 55)
|
||||
odm_set_mac_reg(p_dm_odm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT19 | BIT18, 0); /*Resp TXAGC offset = 0dB*/
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
|
@ -265,70 +136,6 @@ odm_dynamic_tx_power_ap(
|
|||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
|
||||
/* #if ((RTL8192C_SUPPORT==1) || (RTL8192D_SUPPORT==1) || (RTL8188E_SUPPORT==1) || (RTL8812E_SUPPORT==1)) */
|
||||
|
||||
|
||||
struct rtl8192cd_priv *priv = p_dm_odm->priv;
|
||||
s32 i;
|
||||
s16 pwr_thd = 63;
|
||||
|
||||
if (!priv->pshare->rf_ft_var.tx_pwr_ctrl)
|
||||
return;
|
||||
|
||||
#if ((RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1))
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A))
|
||||
pwr_thd = TX_POWER_NEAR_FIELD_THRESH_LVL1;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Check if station is near by to use lower tx power
|
||||
*/
|
||||
|
||||
if ((priv->up_time % 3) == 0) {
|
||||
int disable_pwr_ctrl = ((p_dm_odm->false_alm_cnt.cnt_all > 1000) || ((p_dm_odm->false_alm_cnt.cnt_all > 300) && ((RTL_R8(0xc50) & 0x7f) >= 0x32))) ? 1 : 0;
|
||||
|
||||
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
|
||||
struct sta_info *pstat = p_dm_odm->p_odm_sta_info[i];
|
||||
if (IS_STA_VALID(pstat)) {
|
||||
if (disable_pwr_ctrl)
|
||||
pstat->hp_level = 0;
|
||||
else if ((pstat->hp_level == 0) && (pstat->rssi > pwr_thd))
|
||||
pstat->hp_level = 1;
|
||||
else if ((pstat->hp_level == 1) && (pstat->rssi < (pwr_thd - 8)))
|
||||
pstat->hp_level = 0;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_WLAN_HAL_8192EE)
|
||||
if (GET_CHIP_VER(priv) == VERSION_8192E) {
|
||||
if (!disable_pwr_ctrl && (p_dm_odm->rssi_min != 0xff)) {
|
||||
if (p_dm_odm->rssi_min > pwr_thd)
|
||||
RRSR_power_control_11n(priv, 1);
|
||||
else if (p_dm_odm->rssi_min < (pwr_thd - 8))
|
||||
RRSR_power_control_11n(priv, 0);
|
||||
} else
|
||||
RRSR_power_control_11n(priv, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_WLAN_HAL_8814AE
|
||||
if (GET_CHIP_VER(priv) == VERSION_8814A) {
|
||||
if (!disable_pwr_ctrl && (p_dm_odm->rssi_min != 0xff)) {
|
||||
if (p_dm_odm->rssi_min > pwr_thd)
|
||||
RRSR_power_control_14(priv, 1);
|
||||
else if (p_dm_odm->rssi_min < (pwr_thd - 8))
|
||||
RRSR_power_control_14(priv, 0);
|
||||
} else
|
||||
RRSR_power_control_14(priv, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
}
|
||||
/* #endif */
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
|
@ -338,198 +145,4 @@ odm_dynamic_tx_power_8821(
|
|||
u8 mac_id
|
||||
)
|
||||
{
|
||||
#if (RTL8821A_SUPPORT == 1)
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct sta_info *p_entry;
|
||||
u8 reg0xc56_byte;
|
||||
u8 txpwr_offset = 0;
|
||||
|
||||
p_entry = p_dm_odm->p_odm_sta_info[mac_id];
|
||||
|
||||
reg0xc56_byte = odm_read_1byte(p_dm_odm, 0xc56);
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("reg0xc56_byte=%d\n", reg0xc56_byte));
|
||||
|
||||
if (p_entry[mac_id].rssi_stat.undecorated_smoothed_pwdb > 85) {
|
||||
|
||||
/* Avoid TXAGC error after TX power offset is applied.
|
||||
For example: Reg0xc56=0x6, if txpwr_offset=3( reduce 11dB )
|
||||
Total power = 6-11= -5( overflow!! ), PA may be burned !
|
||||
so txpwr_offset should be adjusted by Reg0xc56*/
|
||||
|
||||
if (reg0xc56_byte < 7)
|
||||
txpwr_offset = 1;
|
||||
else if (reg0xc56_byte < 11)
|
||||
txpwr_offset = 2;
|
||||
else
|
||||
txpwr_offset = 3;
|
||||
|
||||
SET_TX_DESC_TX_POWER_OFFSET_8812(p_desc, txpwr_offset);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_dynamic_tx_power_8821: RSSI=%d, txpwr_offset=%d\n", p_entry[mac_id].rssi_stat.undecorated_smoothed_pwdb, txpwr_offset));
|
||||
|
||||
} else {
|
||||
SET_TX_DESC_TX_POWER_OFFSET_8812(p_desc, txpwr_offset);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_dynamic_tx_power_8821: RSSI=%d, txpwr_offset=%d\n", p_entry[mac_id].rssi_stat.undecorated_smoothed_pwdb, txpwr_offset));
|
||||
|
||||
}
|
||||
#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
|
||||
#endif /*#if (RTL8821A_SUPPORT==1)*/
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void
|
||||
odm_dynamic_tx_power_8814a(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
PMGNT_INFO p_mgnt_info = &adapter->MgntInfo;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
s32 undecorated_smoothed_pwdb;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD,
|
||||
("TxLevel=%d p_mgnt_info->iot_action=%x p_mgnt_info->is_dynamic_tx_power_enable=%d\n",
|
||||
p_hal_data->DynamicTxHighPowerLvl, p_mgnt_info->IOTAction, p_mgnt_info->bDynamicTxPowerEnable));
|
||||
|
||||
/*STA not connected and AP not connected*/
|
||||
if ((!p_mgnt_info->bMediaConnect) && (p_hal_data->EntryMinUndecoratedSmoothedPWDB == 0)) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("Not connected to any reset power lvl\n"));
|
||||
p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
if ((p_mgnt_info->bDynamicTxPowerEnable != true) || p_mgnt_info->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)
|
||||
p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
|
||||
else {
|
||||
if (p_mgnt_info->bMediaConnect) { /*Default port*/
|
||||
if (ACTING_AS_AP(adapter) || ACTING_AS_IBSS(adapter)) {
|
||||
undecorated_smoothed_pwdb = p_hal_data->EntryMinUndecoratedSmoothedPWDB;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Client PWDB = 0x%x\n", undecorated_smoothed_pwdb));
|
||||
} else {
|
||||
undecorated_smoothed_pwdb = p_hal_data->UndecoratedSmoothedPWDB;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x\n", undecorated_smoothed_pwdb));
|
||||
}
|
||||
} else {/*associated entry pwdb*/
|
||||
undecorated_smoothed_pwdb = p_hal_data->EntryMinUndecoratedSmoothedPWDB;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x\n", undecorated_smoothed_pwdb));
|
||||
}
|
||||
|
||||
/*Should we separate as 2.4G/5G band?*/
|
||||
|
||||
if (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
|
||||
p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_level2;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("tx_high_pwr_level_level1 (TxPwr=0x0)\n"));
|
||||
} else if ((undecorated_smoothed_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
|
||||
(undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
|
||||
p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_level1;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("tx_high_pwr_level_level1 (TxPwr=0x10)\n"));
|
||||
} else if (undecorated_smoothed_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
|
||||
p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("tx_high_pwr_level_normal\n"));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if (p_hal_data->DynamicTxHighPowerLvl != p_hal_data->LastDTPLvl) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_dynamic_tx_power_8814a() channel = %d\n", p_hal_data->CurrentChannel));
|
||||
odm_set_tx_power_level8814(adapter, p_hal_data->CurrentChannel, p_hal_data->DynamicTxHighPowerLvl);
|
||||
}
|
||||
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD,
|
||||
("odm_dynamic_tx_power_8814a() channel = %d TXpower lvl=%d/%d\n",
|
||||
p_hal_data->CurrentChannel, p_hal_data->LastDTPLvl, p_hal_data->DynamicTxHighPowerLvl));
|
||||
|
||||
p_hal_data->LastDTPLvl = p_hal_data->DynamicTxHighPowerLvl;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**/
|
||||
/*For normal driver we always use the FW method to configure TX power index to reduce I/O transaction.*/
|
||||
/**/
|
||||
/**/
|
||||
void
|
||||
odm_set_tx_power_level8814(
|
||||
struct _ADAPTER *adapter,
|
||||
u8 channel,
|
||||
u8 pwr_lvl
|
||||
)
|
||||
{
|
||||
#if (DEV_BUS_TYPE == RT_USB_INTERFACE)
|
||||
u32 i, j, k = 0;
|
||||
u32 value[264] = {0};
|
||||
u32 path = 0, power_index, txagc_table_wd = 0x00801000;
|
||||
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
|
||||
u8 jaguar2_rates[][4] = { {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M},
|
||||
{MGN_6M, MGN_9M, MGN_12M, MGN_18M},
|
||||
{MGN_24M, MGN_36M, MGN_48M, MGN_54M},
|
||||
{MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3},
|
||||
{MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7},
|
||||
{MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11},
|
||||
{MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15},
|
||||
{MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19},
|
||||
{MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23},
|
||||
{MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3},
|
||||
{MGN_VHT1SS_MCS4, MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7},
|
||||
{MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9, MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1},
|
||||
{MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4, MGN_VHT2SS_MCS5},
|
||||
{MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9},
|
||||
{MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3},
|
||||
{MGN_VHT3SS_MCS4, MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7},
|
||||
{MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9, 0, 0}
|
||||
};
|
||||
|
||||
for (path = ODM_RF_PATH_A; path <= ODM_RF_PATH_D; ++path) {
|
||||
|
||||
u8 usb_host = UsbModeQueryHubUsbType(adapter);
|
||||
u8 usb_rfset = UsbModeQueryRfSet(adapter);
|
||||
u8 usb_rf_type = RT_GetRFType(adapter);
|
||||
|
||||
for (i = 0; i <= 16; i++) {
|
||||
for (j = 0; j <= 3; j++) {
|
||||
if (jaguar2_rates[i][j] == 0)
|
||||
continue;
|
||||
|
||||
txagc_table_wd = 0x00801000;
|
||||
power_index = (u32) PHY_GetTxPowerIndex(adapter, (u8)path, jaguar2_rates[i][j], p_hal_data->CurrentChannelBW, channel);
|
||||
|
||||
/*for Query bus type to recude tx power.*/
|
||||
if (usb_host != USB_MODE_U3 && usb_rfset == 1 && IS_HARDWARE_TYPE_8814AU(adapter) && usb_rf_type == RF_3T3R) {
|
||||
if (channel <= 14) {
|
||||
if (power_index >= 16)
|
||||
power_index -= 16;
|
||||
else
|
||||
power_index = 0;
|
||||
} else
|
||||
power_index = 0;
|
||||
}
|
||||
|
||||
if (pwr_lvl == tx_high_pwr_level_level1) {
|
||||
if (power_index >= 0x10)
|
||||
power_index -= 0x10;
|
||||
else
|
||||
power_index = 0;
|
||||
} else if (pwr_lvl == tx_high_pwr_level_level2)
|
||||
power_index = 0;
|
||||
|
||||
txagc_table_wd |= (path << 8) | MRateToHwRate(jaguar2_rates[i][j]) | (power_index << 24);
|
||||
|
||||
PHY_SetTxPowerIndexShadow(adapter, (u8)power_index, (u8)path, jaguar2_rates[i][j]);
|
||||
|
||||
value[k++] = txagc_table_wd;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (adapter->MgntInfo.bScanInProgress == false && adapter->MgntInfo.RegFWOffload == 2)
|
||||
HalDownloadTxPowerLevel8814(adapter, value);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -32,35 +32,15 @@ odm_edca_turbo_init(
|
|||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter = NULL;
|
||||
HAL_DATA_TYPE *p_hal_data = NULL;
|
||||
|
||||
if (p_dm_odm->adapter == NULL) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("EdcaTurboInit fail!!!\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
adapter = p_dm_odm->adapter;
|
||||
p_hal_data = GET_HAL_DATA(adapter);
|
||||
|
||||
p_dm_odm->dm_edca_table.is_current_turbo_edca = false;
|
||||
p_dm_odm->dm_edca_table.is_cur_rdl_state = false;
|
||||
p_hal_data->is_any_non_be_pkts = false;
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
p_dm_odm->dm_edca_table.is_current_turbo_edca = false;
|
||||
p_dm_odm->dm_edca_table.is_cur_rdl_state = false;
|
||||
adapter->recvpriv.is_any_non_be_pkts = false;
|
||||
|
||||
#endif
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_VO_PARAM)));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_VI_PARAM)));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_BE_PARAM)));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_BK_PARAM)));
|
||||
|
||||
|
||||
} /* ODM_InitEdcaTurbo */
|
||||
|
||||
void
|
||||
|
@ -86,25 +66,15 @@ odm_edca_turbo_check(
|
|||
|
||||
switch (p_dm_odm->support_platform) {
|
||||
case ODM_WIN:
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
odm_edca_turbo_check_mp(p_dm_odm);
|
||||
#endif
|
||||
break;
|
||||
|
||||
case ODM_CE:
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
odm_edca_turbo_check_ce(p_dm_odm);
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("<========================odm_edca_turbo_check\n"));
|
||||
|
||||
} /* odm_CheckEdcaTurbo */
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
|
||||
|
||||
void
|
||||
odm_edca_turbo_check_ce(
|
||||
void *p_dm_void
|
||||
|
@ -233,466 +203,6 @@ odm_edca_turbo_check_ce(
|
|||
p_dm_odm->dm_edca_table.is_current_turbo_edca = _FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void
|
||||
odm_edca_turbo_check_mp(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
|
||||
struct _ADAPTER *p_default_adapter = get_default_adapter(adapter);
|
||||
struct _ADAPTER *p_ext_adapter = get_first_ext_adapter(adapter); /* NULL; */
|
||||
PMGNT_INFO p_mgnt_info = &adapter->MgntInfo;
|
||||
PSTA_QOS p_sta_qos = adapter->MgntInfo.p_sta_qos;
|
||||
/* [Win7 count Tx/Rx statistic for Extension Port] odm_CheckEdcaTurbo's adapter is always Default. 2009.08.20, by Bohn */
|
||||
u64 ext_cur_tx_ok_cnt = 0;
|
||||
u64 ext_cur_rx_ok_cnt = 0;
|
||||
/* For future Win7 Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn. */
|
||||
u8 two_port_status = (u8)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE;
|
||||
|
||||
/* Keep past Tx/Rx packet count for RT-to-RT EDCA turbo. */
|
||||
u64 cur_tx_ok_cnt = 0;
|
||||
u64 cur_rx_ok_cnt = 0;
|
||||
u32 EDCA_BE_UL = 0x5ea42b;/* Parameter suggested by Scott */ /* edca_setting_UL[p_mgnt_info->iot_peer]; */
|
||||
u32 EDCA_BE_DL = 0x5ea42b;/* Parameter suggested by Scott */ /* edca_setting_DL[p_mgnt_info->iot_peer]; */
|
||||
u32 EDCA_BE = 0x5ea42b;
|
||||
u8 iot_peer = 0;
|
||||
bool *p_is_cur_rdl_state = NULL;
|
||||
bool is_last_is_cur_rdl_state = false;
|
||||
bool is_bias_on_rx = false;
|
||||
bool is_edca_turbo_on = false;
|
||||
u8 tx_rate = 0xFF;
|
||||
u64 value64;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_edca_turbo_check_mp========================>"));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", odm_read_4byte(p_dm_odm, ODM_EDCA_BE_PARAM)));
|
||||
|
||||
/* *******************************
|
||||
* list paramter for different platform
|
||||
* ******************************* */
|
||||
is_last_is_cur_rdl_state = p_dm_odm->dm_edca_table.is_cur_rdl_state;
|
||||
p_is_cur_rdl_state = &(p_dm_odm->dm_edca_table.is_cur_rdl_state);
|
||||
|
||||
/* 2012/09/14 MH Add */
|
||||
if (p_mgnt_info->num_non_be_pkt > p_mgnt_info->reg_edca_thresh && !(adapter->MgntInfo.wifi_confg & RT_WIFI_LOGO))
|
||||
p_hal_data->is_any_non_be_pkts = true;
|
||||
|
||||
p_mgnt_info->num_non_be_pkt = 0;
|
||||
|
||||
/* Caculate TX/RX TP: */
|
||||
cur_tx_ok_cnt = p_dm_odm->cur_tx_ok_cnt;
|
||||
cur_rx_ok_cnt = p_dm_odm->cur_rx_ok_cnt;
|
||||
|
||||
|
||||
if (p_ext_adapter == NULL)
|
||||
p_ext_adapter = p_default_adapter;
|
||||
|
||||
ext_cur_tx_ok_cnt = p_ext_adapter->tx_stats.num_tx_bytes_unicast - p_mgnt_info->ext_last_tx_ok_cnt;
|
||||
ext_cur_rx_ok_cnt = p_ext_adapter->rx_stats.num_rx_bytes_unicast - p_mgnt_info->ext_last_rx_ok_cnt;
|
||||
get_two_port_shared_resource(adapter, TWO_PORT_SHARED_OBJECT__STATUS, NULL, &two_port_status);
|
||||
/* For future Win7 Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn. */
|
||||
if (two_port_status == TWO_PORT_STATUS__EXTENSION_ONLY) {
|
||||
cur_tx_ok_cnt = ext_cur_tx_ok_cnt ;
|
||||
cur_rx_ok_cnt = ext_cur_rx_ok_cnt ;
|
||||
}
|
||||
/* */
|
||||
iot_peer = p_mgnt_info->iot_peer;
|
||||
is_bias_on_rx = (p_mgnt_info->iot_action & HT_IOT_ACT_EDCA_BIAS_ON_RX) ? true : false;
|
||||
is_edca_turbo_on = ((!p_hal_data->is_any_non_be_pkts)) ? true : false;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("is_any_non_be_pkts : 0x%lx\n", p_hal_data->is_any_non_be_pkts));
|
||||
|
||||
|
||||
/* *******************************
|
||||
* check if edca turbo is disabled
|
||||
* ******************************* */
|
||||
if (odm_is_edca_turbo_disable(p_dm_odm)) {
|
||||
p_hal_data->is_any_non_be_pkts = false;
|
||||
p_mgnt_info->last_tx_ok_cnt = adapter->tx_stats.num_tx_bytes_unicast;
|
||||
p_mgnt_info->last_rx_ok_cnt = adapter->rx_stats.num_rx_bytes_unicast;
|
||||
p_mgnt_info->ext_last_tx_ok_cnt = p_ext_adapter->tx_stats.num_tx_bytes_unicast;
|
||||
p_mgnt_info->ext_last_rx_ok_cnt = p_ext_adapter->rx_stats.num_rx_bytes_unicast;
|
||||
|
||||
}
|
||||
|
||||
/* *******************************
|
||||
* remove iot case out
|
||||
* ******************************* */
|
||||
odm_edca_para_sel_by_iot(p_dm_odm, &EDCA_BE_UL, &EDCA_BE_DL);
|
||||
|
||||
|
||||
/* *******************************
|
||||
* Check if the status needs to be changed.
|
||||
* ******************************* */
|
||||
if (is_edca_turbo_on) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("is_edca_turbo_on : 0x%x is_bias_on_rx : 0x%x\n", is_edca_turbo_on, is_bias_on_rx));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("cur_tx_ok_cnt : 0x%lx\n", cur_tx_ok_cnt));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("cur_rx_ok_cnt : 0x%lx\n", cur_rx_ok_cnt));
|
||||
if (is_bias_on_rx)
|
||||
odm_edca_choose_traffic_idx(p_dm_odm, cur_tx_ok_cnt, cur_rx_ok_cnt, true, p_is_cur_rdl_state);
|
||||
else
|
||||
odm_edca_choose_traffic_idx(p_dm_odm, cur_tx_ok_cnt, cur_rx_ok_cnt, false, p_is_cur_rdl_state);
|
||||
|
||||
/* modify by Guo.Mingzhi 2011-12-29 */
|
||||
if (adapter->AP_EDCA_PARAM[0] != EDCA_BE)
|
||||
EDCA_BE = adapter->AP_EDCA_PARAM[0];
|
||||
else
|
||||
EDCA_BE = ((*p_is_cur_rdl_state) == true) ? EDCA_BE_DL : EDCA_BE_UL;
|
||||
|
||||
/*For TPLINK 8188EU test*/
|
||||
if ((IS_HARDWARE_TYPE_8188EU(adapter)) && (p_hal_data->UndecoratedSmoothedPWDB < 28)) { /* Set to origimal EDCA 0x5EA42B now need to update.*/
|
||||
|
||||
} else { /*Use TPLINK preferred EDCA parameters.*/
|
||||
EDCA_BE = p_mgnt_info->EDCABEPara;
|
||||
}
|
||||
|
||||
if (IS_HARDWARE_TYPE_8821U(adapter)) {
|
||||
if (p_mgnt_info->reg_tx_duty_enable) {
|
||||
/* 2013.01.23 LukeLee: debug for 8811AU thermal issue (reduce Tx duty cycle) */
|
||||
if (!p_mgnt_info->forced_data_rate) { /* auto rate */
|
||||
if (p_dm_odm->tx_rate != 0xFF)
|
||||
tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(p_dm_odm->tx_rate);
|
||||
} else /* force rate */
|
||||
tx_rate = (u8) p_mgnt_info->forced_data_rate;
|
||||
|
||||
value64 = (cur_rx_ok_cnt << 2);
|
||||
if (cur_tx_ok_cnt < value64) /* Downlink */
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
|
||||
else { /* Uplink */
|
||||
/*dbg_print("p_rf_calibrate_info->thermal_value = 0x%X\n", p_rf_calibrate_info->thermal_value);*/
|
||||
/*if(p_rf_calibrate_info->thermal_value < p_hal_data->eeprom_thermal_meter)*/
|
||||
if ((p_dm_odm->rf_calibrate_info.thermal_value < 0x2c) || (*p_dm_odm->p_band_type == BAND_ON_2_4G))
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
|
||||
else {
|
||||
switch (tx_rate) {
|
||||
case MGN_VHT1SS_MCS6:
|
||||
case MGN_VHT1SS_MCS5:
|
||||
case MGN_MCS6:
|
||||
case MGN_MCS5:
|
||||
case MGN_48M:
|
||||
case MGN_54M:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0x1ea42b);
|
||||
break;
|
||||
case MGN_VHT1SS_MCS4:
|
||||
case MGN_MCS4:
|
||||
case MGN_36M:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa42b);
|
||||
break;
|
||||
case MGN_VHT1SS_MCS3:
|
||||
case MGN_MCS3:
|
||||
case MGN_24M:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa47f);
|
||||
break;
|
||||
case MGN_VHT1SS_MCS2:
|
||||
case MGN_MCS2:
|
||||
case MGN_18M:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa57f);
|
||||
break;
|
||||
case MGN_VHT1SS_MCS1:
|
||||
case MGN_MCS1:
|
||||
case MGN_9M:
|
||||
case MGN_12M:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa77f);
|
||||
break;
|
||||
case MGN_VHT1SS_MCS0:
|
||||
case MGN_MCS0:
|
||||
case MGN_6M:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa87f);
|
||||
break;
|
||||
default:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
} else
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
|
||||
|
||||
} else if (IS_HARDWARE_TYPE_8812AU(adapter)) {
|
||||
if (p_mgnt_info->reg_tx_duty_enable) {
|
||||
/* 2013.07.26 Wilson: debug for 8812AU thermal issue (reduce Tx duty cycle) */
|
||||
/* it;s the same issue as 8811AU */
|
||||
if (!p_mgnt_info->forced_data_rate) { /* auto rate */
|
||||
if (p_dm_odm->tx_rate != 0xFF)
|
||||
tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(p_dm_odm->tx_rate);
|
||||
} else /* force rate */
|
||||
tx_rate = (u8) p_mgnt_info->forced_data_rate;
|
||||
|
||||
value64 = (cur_rx_ok_cnt << 2);
|
||||
if (cur_tx_ok_cnt < value64) /* Downlink */
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
|
||||
else { /* Uplink */
|
||||
/*dbg_print("p_rf_calibrate_info->thermal_value = 0x%X\n", p_rf_calibrate_info->thermal_value);*/
|
||||
/*if(p_rf_calibrate_info->thermal_value < p_hal_data->eeprom_thermal_meter)*/
|
||||
if ((p_dm_odm->rf_calibrate_info.thermal_value < 0x2c) || (*p_dm_odm->p_band_type == BAND_ON_2_4G))
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
|
||||
else {
|
||||
switch (tx_rate) {
|
||||
case MGN_VHT2SS_MCS9:
|
||||
case MGN_VHT1SS_MCS9:
|
||||
case MGN_VHT1SS_MCS8:
|
||||
case MGN_MCS15:
|
||||
case MGN_MCS7:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0x1ea44f);
|
||||
case MGN_VHT2SS_MCS8:
|
||||
case MGN_VHT1SS_MCS7:
|
||||
case MGN_MCS14:
|
||||
case MGN_MCS6:
|
||||
case MGN_54M:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa44f);
|
||||
case MGN_VHT2SS_MCS7:
|
||||
case MGN_VHT2SS_MCS6:
|
||||
case MGN_VHT1SS_MCS6:
|
||||
case MGN_VHT1SS_MCS5:
|
||||
case MGN_MCS13:
|
||||
case MGN_MCS5:
|
||||
case MGN_48M:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa630);
|
||||
break;
|
||||
case MGN_VHT2SS_MCS5:
|
||||
case MGN_VHT2SS_MCS4:
|
||||
case MGN_VHT1SS_MCS4:
|
||||
case MGN_VHT1SS_MCS3:
|
||||
case MGN_MCS12:
|
||||
case MGN_MCS4:
|
||||
case MGN_MCS3:
|
||||
case MGN_36M:
|
||||
case MGN_24M:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa730);
|
||||
break;
|
||||
case MGN_VHT2SS_MCS3:
|
||||
case MGN_VHT2SS_MCS2:
|
||||
case MGN_VHT2SS_MCS1:
|
||||
case MGN_VHT1SS_MCS2:
|
||||
case MGN_VHT1SS_MCS1:
|
||||
case MGN_MCS11:
|
||||
case MGN_MCS10:
|
||||
case MGN_MCS9:
|
||||
case MGN_MCS2:
|
||||
case MGN_MCS1:
|
||||
case MGN_18M:
|
||||
case MGN_12M:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa830);
|
||||
break;
|
||||
case MGN_VHT2SS_MCS0:
|
||||
case MGN_VHT1SS_MCS0:
|
||||
case MGN_MCS0:
|
||||
case MGN_MCS8:
|
||||
case MGN_9M:
|
||||
case MGN_6M:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, 0xa87f);
|
||||
break;
|
||||
default:
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
} else
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
|
||||
} else
|
||||
odm_write_4byte(p_dm_odm, ODM_EDCA_BE_PARAM, EDCA_BE);
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("EDCA Turbo on: EDCA_BE:0x%lx\n", EDCA_BE));
|
||||
|
||||
p_dm_odm->dm_edca_table.is_current_turbo_edca = true;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("EDCA_BE_DL : 0x%lx EDCA_BE_UL : 0x%lx EDCA_BE : 0x%lx\n", EDCA_BE_DL, EDCA_BE_UL, EDCA_BE));
|
||||
|
||||
} else {
|
||||
/* Turn Off EDCA turbo here. */
|
||||
/* Restore original EDCA according to the declaration of AP. */
|
||||
if (p_dm_odm->dm_edca_table.is_current_turbo_edca) {
|
||||
phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_AC_PARAM, GET_WMM_PARAM_ELE_SINGLE_AC_PARAM(p_sta_qos->wmm_param_ele, AC0_BE));
|
||||
|
||||
p_dm_odm->dm_edca_table.is_current_turbo_edca = false;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Restore EDCA BE: 0x%lx\n", p_dm_odm->WMMEDCA_BE));
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/* check if edca turbo is disabled */
|
||||
bool
|
||||
odm_is_edca_turbo_disable(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
PMGNT_INFO p_mgnt_info = &adapter->MgntInfo;
|
||||
u32 iot_peer = p_mgnt_info->iot_peer;
|
||||
|
||||
if (p_dm_odm->is_bt_disable_edca_turbo) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("EdcaTurboDisable for BT!!\n"));
|
||||
return true;
|
||||
}
|
||||
|
||||
if ((!(p_dm_odm->support_ability & ODM_MAC_EDCA_TURBO)) ||
|
||||
(p_dm_odm->wifi_test & RT_WIFI_LOGO) ||
|
||||
(iot_peer >= HT_IOT_PEER_MAX)) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("EdcaTurboDisable\n"));
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
/* 1. We do not turn on EDCA turbo mode for some AP that has IOT issue */
|
||||
/* 2. User may disable EDCA Turbo mode with OID settings. */
|
||||
if (p_mgnt_info->iot_action & HT_IOT_ACT_DISABLE_EDCA_TURBO) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("iot_action:EdcaTurboDisable\n"));
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
|
||||
|
||||
}
|
||||
|
||||
/* add iot case here: for MP/CE */
|
||||
void
|
||||
odm_edca_para_sel_by_iot(
|
||||
void *p_dm_void,
|
||||
u32 *EDCA_BE_UL,
|
||||
u32 *EDCA_BE_DL
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
u32 iot_peer = 0;
|
||||
u32 ic_type = p_dm_odm->support_ic_type;
|
||||
u8 wireless_mode = 0xFF; /* invalid value */
|
||||
u32 iot_peer_sub_type = 0;
|
||||
|
||||
PMGNT_INFO p_mgnt_info = &adapter->MgntInfo;
|
||||
u8 two_port_status = (u8)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE;
|
||||
|
||||
if (p_dm_odm->p_wireless_mode != NULL)
|
||||
wireless_mode = *(p_dm_odm->p_wireless_mode);
|
||||
|
||||
/* ========================================================= */
|
||||
/* list paramter for different platform */
|
||||
|
||||
iot_peer = p_mgnt_info->iot_peer;
|
||||
iot_peer_sub_type = p_mgnt_info->iot_peer_subtype;
|
||||
get_two_port_shared_resource(adapter, TWO_PORT_SHARED_OBJECT__STATUS, NULL, &two_port_status);
|
||||
|
||||
/* ****************************
|
||||
* / IOT case for MP
|
||||
* **************************** */
|
||||
if (p_dm_odm->support_interface == ODM_ITRF_PCIE) {
|
||||
(*EDCA_BE_UL) = 0x6ea42b;
|
||||
(*EDCA_BE_DL) = 0x6ea42b;
|
||||
}
|
||||
|
||||
if (two_port_status == TWO_PORT_STATUS__EXTENSION_ONLY) {
|
||||
(*EDCA_BE_UL) = 0x5ea42b;/* Parameter suggested by Scott */ /* edca_setting_UL[ExtAdapter->mgnt_info.iot_peer]; */
|
||||
(*EDCA_BE_DL) = 0x5ea42b;/* Parameter suggested by Scott */ /* edca_setting_DL[ExtAdapter->mgnt_info.iot_peer]; */
|
||||
}
|
||||
|
||||
#if (INTEL_PROXIMITY_SUPPORT == 1)
|
||||
if (p_mgnt_info->intel_class_mode_info.is_enable_ca == true)
|
||||
(*EDCA_BE_UL) = (*EDCA_BE_DL) = 0xa44f;
|
||||
else
|
||||
#endif
|
||||
{
|
||||
if ((p_mgnt_info->iot_action & (HT_IOT_ACT_FORCED_ENABLE_BE_TXOP | HT_IOT_ACT_AMSDU_ENABLE))) {
|
||||
/* To check whether we shall force turn on TXOP configuration. */
|
||||
if (!((*EDCA_BE_UL) & 0xffff0000))
|
||||
(*EDCA_BE_UL) |= 0x005e0000; /* Force TxOP limit to 0x005e for UL. */
|
||||
if (!((*EDCA_BE_DL) & 0xffff0000))
|
||||
(*EDCA_BE_DL) |= 0x005e0000; /* Force TxOP limit to 0x005e for DL. */
|
||||
}
|
||||
|
||||
/* 92D txop can't be set to 0x3e for cisco1250 */
|
||||
if ((iot_peer == HT_IOT_PEER_CISCO) && (wireless_mode == ODM_WM_N24G)) {
|
||||
(*EDCA_BE_DL) = edca_setting_DL[iot_peer];
|
||||
(*EDCA_BE_UL) = edca_setting_UL[iot_peer];
|
||||
}
|
||||
/* merge from 92s_92c_merge temp brunch v2445 20120215 */
|
||||
else if ((iot_peer == HT_IOT_PEER_CISCO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == (ODM_WM_B | ODM_WM_G)) || (wireless_mode == ODM_WM_A) || (wireless_mode == ODM_WM_B)))
|
||||
(*EDCA_BE_DL) = edca_setting_dl_g_mode[iot_peer];
|
||||
else if ((iot_peer == HT_IOT_PEER_AIRGO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == ODM_WM_A)))
|
||||
(*EDCA_BE_DL) = 0xa630;
|
||||
|
||||
else if (iot_peer == HT_IOT_PEER_MARVELL) {
|
||||
(*EDCA_BE_DL) = edca_setting_DL[iot_peer];
|
||||
(*EDCA_BE_UL) = edca_setting_UL[iot_peer];
|
||||
} else if (iot_peer == HT_IOT_PEER_ATHEROS && iot_peer_sub_type != HT_IOT_PEER_TPLINK_AC1750) {
|
||||
/* Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue. */
|
||||
if (wireless_mode == ODM_WM_G)
|
||||
(*EDCA_BE_DL) = edca_setting_dl_g_mode[iot_peer];
|
||||
else
|
||||
(*EDCA_BE_DL) = edca_setting_DL[iot_peer];
|
||||
|
||||
if (ic_type == ODM_RTL8821)
|
||||
(*EDCA_BE_DL) = 0x5ea630;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
if ((ic_type == ODM_RTL8812) || (ic_type == ODM_RTL8192E)) { /* add 8812AU/8812AE */
|
||||
(*EDCA_BE_UL) = 0x5ea42b;
|
||||
(*EDCA_BE_DL) = 0x5ea42b;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("8812A: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx\n", (*EDCA_BE_UL), (*EDCA_BE_DL)));
|
||||
}
|
||||
|
||||
if ((ic_type == ODM_RTL8814A) && (iot_peer == HT_IOT_PEER_REALTEK)) { /*8814AU and 8814AR*/
|
||||
(*EDCA_BE_UL) = 0x5ea42b;
|
||||
(*EDCA_BE_DL) = 0xa42b;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("8814A: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx\n", (*EDCA_BE_UL), (*EDCA_BE_DL)));
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Special: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx, iot_peer = %d\n", (*EDCA_BE_UL), (*EDCA_BE_DL), iot_peer));
|
||||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_edca_choose_traffic_idx(
|
||||
void *p_dm_void,
|
||||
u64 cur_tx_bytes,
|
||||
u64 cur_rx_bytes,
|
||||
bool is_bias_on_rx,
|
||||
bool *p_is_cur_rdl_state
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
|
||||
if (is_bias_on_rx) {
|
||||
|
||||
if (cur_tx_bytes > (cur_rx_bytes * 4)) {
|
||||
*p_is_cur_rdl_state = false;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Uplink Traffic\n "));
|
||||
|
||||
} else {
|
||||
*p_is_cur_rdl_state = true;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Balance Traffic\n"));
|
||||
|
||||
}
|
||||
} else {
|
||||
if (cur_rx_bytes > (cur_tx_bytes * 4)) {
|
||||
*p_is_cur_rdl_state = true;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Downlink Traffic\n"));
|
||||
|
||||
} else {
|
||||
*p_is_cur_rdl_state = false;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Balance Traffic\n"));
|
||||
}
|
||||
}
|
||||
|
||||
return ;
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif /*PHYDM_SUPPORT_EDCA*/
|
||||
|
|
|
@ -29,13 +29,10 @@ struct _EDCA_TURBO_ {
|
|||
bool is_current_turbo_edca;
|
||||
bool is_cur_rdl_state;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
u32 prv_traffic_idx; /* edca turbo */
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
|
||||
/* UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU MARVELL 92U_AP SELF_AP(DownLink/Tx) */
|
||||
{ 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322};
|
||||
|
@ -49,10 +46,6 @@ static u32 edca_setting_dl_g_mode[HT_IOT_PEER_MAX] =
|
|||
/* UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP */
|
||||
{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b};
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
void
|
||||
odm_edca_turbo_check(
|
||||
void *p_dm_void
|
||||
|
@ -62,40 +55,10 @@ odm_edca_turbo_init(
|
|||
void *p_dm_void
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void
|
||||
odm_edca_turbo_check_mp(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
/* check if edca turbo is disabled */
|
||||
bool
|
||||
odm_is_edca_turbo_disable(
|
||||
void *p_dm_void
|
||||
);
|
||||
/* choose edca paramter for special IOT case */
|
||||
void
|
||||
odm_edca_para_sel_by_iot(
|
||||
void *p_dm_void,
|
||||
u32 *EDCA_BE_UL,
|
||||
u32 *EDCA_BE_DL
|
||||
);
|
||||
/* check if it is UL or DL */
|
||||
void
|
||||
odm_edca_choose_traffic_idx(
|
||||
void *p_dm_void,
|
||||
u64 cur_tx_bytes,
|
||||
u64 cur_rx_bytes,
|
||||
bool is_bias_on_rx,
|
||||
bool *p_is_cur_rdl_state
|
||||
);
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
void
|
||||
odm_edca_turbo_check_ce(
|
||||
void *p_dm_void
|
||||
);
|
||||
#endif
|
||||
|
||||
#endif /*PHYDM_SUPPORT_EDCA*/
|
||||
|
||||
|
|
|
@ -28,162 +28,31 @@
|
|||
#define PHYDM_LA_MODE_SUPPORT 0
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
/*phydm debyg report & tools*/
|
||||
#define CONFIG_PHYDM_DEBUG_FUNCTION 1
|
||||
|
||||
/*phydm debyg report & tools*/
|
||||
#define CONFIG_PHYDM_DEBUG_FUNCTION 1
|
||||
#define CONFIG_DYNAMIC_RX_PATH 0
|
||||
|
||||
/*Antenna Diversity*/
|
||||
#define PHYDM_SUPPORT_EDCA 1
|
||||
#define SUPPORTABLITY_PHYDMLIZE 1
|
||||
#define RA_MASK_PHYDMLIZE_CE 1
|
||||
|
||||
/*Antenna Diversity*/
|
||||
#ifdef CONFIG_ANTENNA_DIVERSITY
|
||||
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
|
||||
#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
|
||||
|
||||
#if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1)
|
||||
#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY
|
||||
#endif
|
||||
|
||||
#if (RTL8821A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1)
|
||||
/*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
|
||||
#define CONFIG_FAT_PATCH
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
#define CONFIG_DYNAMIC_RX_PATH 0
|
||||
#else
|
||||
#define CONFIG_DYNAMIC_RX_PATH 0
|
||||
#endif
|
||||
|
||||
#if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1)
|
||||
#define CONFIG_RECEIVER_BLOCKING
|
||||
#endif
|
||||
#define PHYDM_SUPPORT_EDCA 0
|
||||
#define SUPPORTABLITY_PHYDMLIZE 1
|
||||
#define RA_MASK_PHYDMLIZE_WIN 1
|
||||
/*#define CONFIG_PATH_DIVERSITY*/
|
||||
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
|
||||
#define CONFIG_ANT_DETECTION
|
||||
/*#define CONFIG_RA_DBG_CMD*/
|
||||
#define CONFIG_RA_FW_DBG_CODE 1
|
||||
/*#define CONFIG_PHYDM_RX_SNIFFER_PARSING*/
|
||||
#define CONFIG_BB_POWER_SAVING
|
||||
#define CONFIG_BB_TXBF_API
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
|
||||
/*phydm debyg report & tools*/
|
||||
#if defined(CONFIG_DISABLE_PHYDM_DEBUG_FUNCTION)
|
||||
#define CONFIG_PHYDM_DEBUG_FUNCTION 0
|
||||
#else
|
||||
#define CONFIG_PHYDM_DEBUG_FUNCTION 1
|
||||
#endif
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
#define CONFIG_DYNAMIC_RX_PATH 0
|
||||
#else
|
||||
#define CONFIG_DYNAMIC_RX_PATH 0
|
||||
#endif
|
||||
|
||||
#define PHYDM_SUPPORT_EDCA 1
|
||||
#define SUPPORTABLITY_PHYDMLIZE 0
|
||||
#define RA_MASK_PHYDMLIZE_AP 1
|
||||
|
||||
/* #define CONFIG_RA_DBG_CMD*/
|
||||
#define CONFIG_RA_FW_DBG_CODE 0
|
||||
|
||||
/*#define CONFIG_PATH_DIVERSITY*/
|
||||
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
|
||||
#define CONFIG_RA_DYNAMIC_RATE_ID
|
||||
/*#define CONFIG_BB_POWER_SAVING*/
|
||||
#define CONFIG_BB_TXBF_API
|
||||
|
||||
/* [ Configure Antenna Diversity ] */
|
||||
#if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH)
|
||||
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
|
||||
#define ODM_EVM_ENHANCE_ANTDIV
|
||||
|
||||
/*----------*/
|
||||
|
||||
#if (!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
|
||||
#define CONFIG_NO_2G_DIVERSITY
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NO_5G_DIVERSITY_8881A
|
||||
#define CONFIG_NO_5G_DIVERSITY
|
||||
#elif defined(CONFIG_5G_CGCS_RX_DIVERSITY_8881A)
|
||||
#define CONFIG_5G_CGCS_RX_DIVERSITY
|
||||
#elif defined(CONFIG_5G_CG_TRX_DIVERSITY_8881A)
|
||||
#define CONFIG_5G_CG_TRX_DIVERSITY
|
||||
#elif defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)
|
||||
#define CONFIG_2G5G_CG_TRX_DIVERSITY
|
||||
#endif
|
||||
#if (!defined(CONFIG_NO_5G_DIVERSITY) && !defined(CONFIG_5G_CGCS_RX_DIVERSITY) && !defined(CONFIG_5G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY) && !defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
|
||||
#define CONFIG_NO_5G_DIVERSITY
|
||||
#endif
|
||||
/*----------*/
|
||||
#if (defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY))
|
||||
#define CONFIG_NOT_SUPPORT_ANTDIV
|
||||
#elif (!defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY))
|
||||
#define CONFIG_2G_SUPPORT_ANTDIV
|
||||
#elif (defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY))
|
||||
#define CONFIG_5G_SUPPORT_ANTDIV
|
||||
#elif ((!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY))
|
||||
#define CONFIG_2G5G_SUPPORT_ANTDIV
|
||||
#endif
|
||||
/*----------*/
|
||||
#endif
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
|
||||
/*phydm debyg report & tools*/
|
||||
#define CONFIG_PHYDM_DEBUG_FUNCTION 1
|
||||
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
#define CONFIG_DYNAMIC_RX_PATH 0
|
||||
#else
|
||||
#define CONFIG_DYNAMIC_RX_PATH 0
|
||||
#endif
|
||||
|
||||
#define PHYDM_SUPPORT_EDCA 1
|
||||
#define SUPPORTABLITY_PHYDMLIZE 1
|
||||
#define RA_MASK_PHYDMLIZE_CE 1
|
||||
|
||||
/*Antenna Diversity*/
|
||||
#ifdef CONFIG_ANTENNA_DIVERSITY
|
||||
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
|
||||
|
||||
#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
|
||||
|
||||
#if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1)
|
||||
#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY
|
||||
#endif
|
||||
|
||||
#if (RTL8821A_SUPPORT == 1)
|
||||
/*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DFS_MASTER
|
||||
#define CONFIG_PHYDM_DFS_MASTER
|
||||
#endif
|
||||
|
||||
#if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1)
|
||||
#define CONFIG_RECEIVER_BLOCKING
|
||||
#endif
|
||||
/*#define CONFIG_RA_DBG_CMD*/
|
||||
#define CONFIG_RA_FW_DBG_CODE 0
|
||||
/*#define CONFIG_ANT_DETECTION*/
|
||||
/*#define CONFIG_PATH_DIVERSITY*/
|
||||
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
|
||||
#define CONFIG_BB_POWER_SAVING
|
||||
#define CONFIG_BB_TXBF_API
|
||||
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
#define BT_SUPPORT 1
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DFS_MASTER
|
||||
#define CONFIG_PHYDM_DFS_MASTER
|
||||
#endif
|
||||
|
||||
#define CONFIG_RECEIVER_BLOCKING
|
||||
#define CONFIG_RA_FW_DBG_CODE 0
|
||||
#define CONFIG_BB_POWER_SAVING
|
||||
#define CONFIG_BB_TXBF_API
|
||||
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
#define BT_SUPPORT 1
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -195,17 +195,6 @@ odm_init_rssi_for_dm(
|
|||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void
|
||||
phydm_normal_driver_rx_sniffer(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 *p_desc,
|
||||
PRT_RFD_STATUS p_rt_rfd_status,
|
||||
u8 *p_drv_info,
|
||||
u8 phy_status
|
||||
);
|
||||
#endif
|
||||
|
||||
void
|
||||
odm_phy_status_query(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
|
|
|
@ -35,60 +35,33 @@ odm_read_1byte(
|
|||
u32 reg_addr
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
struct rtl8192cd_priv *priv = p_dm_odm->priv;
|
||||
return RTL_R8(reg_addr);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
|
||||
return rtw_read8(adapter, reg_addr);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
return PlatformEFIORead1Byte(adapter, reg_addr);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
u16
|
||||
odm_read_2byte(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 reg_addr
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
struct rtl8192cd_priv *priv = p_dm_odm->priv;
|
||||
return RTL_R16(reg_addr);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
|
||||
return rtw_read16(adapter, reg_addr);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
return PlatformEFIORead2Byte(adapter, reg_addr);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
u32
|
||||
odm_read_4byte(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u32 reg_addr
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
struct rtl8192cd_priv *priv = p_dm_odm->priv;
|
||||
return RTL_R32(reg_addr);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
|
||||
return rtw_read32(adapter, reg_addr);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
return PlatformEFIORead4Byte(adapter, reg_addr);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_write_1byte(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
|
@ -96,17 +69,9 @@ odm_write_1byte(
|
|||
u8 data
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
struct rtl8192cd_priv *priv = p_dm_odm->priv;
|
||||
RTL_W8(reg_addr, data);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
rtw_write8(adapter, reg_addr, data);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
PlatformEFIOWrite1Byte(adapter, reg_addr, data);
|
||||
#endif
|
||||
|
||||
rtw_write8(adapter, reg_addr, data);
|
||||
}
|
||||
|
||||
|
||||
|
@ -117,20 +82,11 @@ odm_write_2byte(
|
|||
u16 data
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
struct rtl8192cd_priv *priv = p_dm_odm->priv;
|
||||
RTL_W16(reg_addr, data);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
|
||||
rtw_write16(adapter, reg_addr, data);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
PlatformEFIOWrite2Byte(adapter, reg_addr, data);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_write_4byte(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
|
@ -138,20 +94,11 @@ odm_write_4byte(
|
|||
u32 data
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
struct rtl8192cd_priv *priv = p_dm_odm->priv;
|
||||
RTL_W32(reg_addr, data);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
|
||||
rtw_write32(adapter, reg_addr, data);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
PlatformEFIOWrite4Byte(adapter, reg_addr, data);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_set_mac_reg(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
|
@ -160,17 +107,9 @@ odm_set_mac_reg(
|
|||
u32 data
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
phy_set_bb_reg(p_dm_odm->priv, reg_addr, bit_mask, data);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
PHY_SetBBReg(adapter, reg_addr, bit_mask, data);
|
||||
#else
|
||||
phy_set_bb_reg(p_dm_odm->adapter, reg_addr, bit_mask, data);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
u32
|
||||
odm_get_mac_reg(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
|
@ -178,16 +117,9 @@ odm_get_mac_reg(
|
|||
u32 bit_mask
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
return phy_query_bb_reg(p_dm_odm->priv, reg_addr, bit_mask);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
return PHY_QueryMacReg(p_dm_odm->adapter, reg_addr, bit_mask);
|
||||
#else
|
||||
return phy_query_mac_reg(p_dm_odm->adapter, reg_addr, bit_mask);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_set_bb_reg(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
|
@ -196,17 +128,9 @@ odm_set_bb_reg(
|
|||
u32 data
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
phy_set_bb_reg(p_dm_odm->priv, reg_addr, bit_mask, data);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
PHY_SetBBReg(adapter, reg_addr, bit_mask, data);
|
||||
#else
|
||||
phy_set_bb_reg(p_dm_odm->adapter, reg_addr, bit_mask, data);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
u32
|
||||
odm_get_bb_reg(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
|
@ -214,17 +138,9 @@ odm_get_bb_reg(
|
|||
u32 bit_mask
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
return phy_query_bb_reg(p_dm_odm->priv, reg_addr, bit_mask);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
return PHY_QueryBBReg(adapter, reg_addr, bit_mask);
|
||||
#else
|
||||
return phy_query_bb_reg(p_dm_odm->adapter, reg_addr, bit_mask);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_set_rf_reg(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
|
@ -234,16 +150,7 @@ odm_set_rf_reg(
|
|||
u32 data
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
phy_set_rf_reg(p_dm_odm->priv, e_rf_path, reg_addr, bit_mask, data);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
PHY_SetRFReg(adapter, e_rf_path, reg_addr, bit_mask, data);
|
||||
ODM_delay_us(2);
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
phy_set_rf_reg(p_dm_odm->adapter, e_rf_path, reg_addr, bit_mask, data);
|
||||
#endif
|
||||
}
|
||||
|
||||
u32
|
||||
|
@ -254,19 +161,9 @@ odm_get_rf_reg(
|
|||
u32 bit_mask
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
return phy_query_rf_reg(p_dm_odm->priv, e_rf_path, reg_addr, bit_mask, 1);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
return PHY_QueryRFReg(adapter, e_rf_path, reg_addr, bit_mask);
|
||||
#else
|
||||
return phy_query_rf_reg(p_dm_odm->adapter, e_rf_path, reg_addr, bit_mask);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ODM Memory relative API.
|
||||
* */
|
||||
|
@ -277,14 +174,7 @@ odm_allocate_memory(
|
|||
u32 length
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
*p_ptr = kmalloc(length, GFP_ATOMIC);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
*p_ptr = rtw_zvmalloc(length);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
PlatformAllocateMemory(adapter, p_ptr, length);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* length could be ignored, used to detect memory leakage. */
|
||||
|
@ -295,14 +185,7 @@ odm_free_memory(
|
|||
u32 length
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
kfree(p_ptr);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
rtw_vmfree(p_ptr, length);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
/* struct _ADAPTER* adapter = p_dm_odm->adapter; */
|
||||
PlatformFreeMemory(p_ptr, length);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
|
@ -313,13 +196,7 @@ odm_move_memory(
|
|||
u32 length
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
memcpy(p_dest, p_src, length);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
_rtw_memcpy(p_dest, p_src, length);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PlatformMoveMemory(p_dest, p_src, length);
|
||||
#endif
|
||||
}
|
||||
|
||||
void odm_memory_set(
|
||||
|
@ -329,14 +206,9 @@ void odm_memory_set(
|
|||
u32 length
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
memset(pbuf, value, length);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
_rtw_memset(pbuf, value, length);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PlatformFillMemory(pbuf, length, value);
|
||||
#endif
|
||||
}
|
||||
|
||||
s32 odm_compare_memory(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
void *p_buf1,
|
||||
|
@ -344,17 +216,9 @@ s32 odm_compare_memory(
|
|||
u32 length
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
return memcmp(p_buf1, p_buf2, length);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
return _rtw_memcmp(p_buf1, p_buf2, length);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
return PlatformCompareMemory(p_buf1, p_buf2, length);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ODM MISC relative API.
|
||||
* */
|
||||
|
@ -364,133 +228,21 @@ odm_acquire_spin_lock(
|
|||
enum rt_spinlock_type type
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
|
||||
rtw_odm_acquirespinlock(adapter, type);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
PlatformAcquireSpinLock(adapter, type);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
odm_release_spin_lock(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
enum rt_spinlock_type type
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
rtw_odm_releasespinlock(adapter, type);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
PlatformReleaseSpinLock(adapter, type);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
/*
|
||||
* Work item relative API. FOr MP driver only~!
|
||||
* */
|
||||
void
|
||||
odm_initialize_work_item(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
PRT_WORK_ITEM p_rt_work_item,
|
||||
RT_WORKITEM_CALL_BACK rt_work_item_callback,
|
||||
void *p_context,
|
||||
const char *sz_id
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
PlatformInitializeWorkItem(adapter, p_rt_work_item, rt_work_item_callback, p_context, sz_id);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_start_work_item(
|
||||
PRT_WORK_ITEM p_rt_work_item
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PlatformStartWorkItem(p_rt_work_item);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_stop_work_item(
|
||||
PRT_WORK_ITEM p_rt_work_item
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PlatformStopWorkItem(p_rt_work_item);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_free_work_item(
|
||||
PRT_WORK_ITEM p_rt_work_item
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PlatformFreeWorkItem(p_rt_work_item);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_schedule_work_item(
|
||||
PRT_WORK_ITEM p_rt_work_item
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PlatformScheduleWorkItem(p_rt_work_item);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
bool
|
||||
odm_is_work_item_scheduled(
|
||||
PRT_WORK_ITEM p_rt_work_item
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
return PlatformIsWorkItemScheduled(p_rt_work_item);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* ODM Timer relative API.
|
||||
* */
|
||||
|
@ -499,59 +251,31 @@ odm_stall_execution(
|
|||
u32 us_delay
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
rtw_udelay_os(us_delay);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PlatformStallExecution(us_delay);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
ODM_delay_ms(u32 ms)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
delay_ms(ms);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
rtw_mdelay_os(ms);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
delay_ms(ms);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
ODM_delay_us(u32 us)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
delay_us(us);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
rtw_udelay_os(us);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
PlatformStallExecution(us);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
ODM_sleep_ms(u32 ms)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
rtw_msleep_os(ms);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
ODM_sleep_us(u32 us)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
rtw_usleep_os(us);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
|
@ -561,15 +285,7 @@ odm_set_timer(
|
|||
u32 ms_delay
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
mod_timer(p_timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(ms_delay));
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
_set_timer(p_timer, ms_delay); /* ms */
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
PlatformSetTimer(adapter, p_timer, ms_delay);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0)
|
||||
|
@ -593,43 +309,17 @@ odm_cancel_timer(
|
|||
struct timer_list *p_timer
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
del_timer(p_timer);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
_cancel_timer_ex(p_timer);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
PlatformCancelTimer(adapter, p_timer);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_release_timer(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
struct timer_list *p_timer
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
|
||||
/* <20120301, Kordan> If the initilization fails, InitializeAdapterXxx will return regardless of InitHalDm.
|
||||
* Hence, uninitialized timers cause BSOD when the driver releases resources since the init fail. */
|
||||
if (p_timer == 0) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_SERIOUS, ("=====>odm_release_timer(), The timer is NULL! Please check it!\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
PlatformReleaseTimer(adapter, p_timer);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
static u8
|
||||
phydm_trans_h2c_id(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
|
@ -641,168 +331,33 @@ phydm_trans_h2c_id(
|
|||
switch (phydm_h2c_id) {
|
||||
/* 1 [0] */
|
||||
case ODM_H2C_RSSI_REPORT:
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8188E)
|
||||
platform_h2c_id = H2C_88E_RSSI_REPORT;
|
||||
else if (p_dm_odm->support_ic_type == ODM_RTL8814A)
|
||||
platform_h2c_id = H2C_8814A_RSSI_REPORT;
|
||||
else
|
||||
platform_h2c_id = H2C_RSSI_REPORT;
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
platform_h2c_id = H2C_RSSI_SETTING;
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8881A || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES)
|
||||
platform_h2c_id = H2C_88XX_RSSI_REPORT;
|
||||
else
|
||||
#endif
|
||||
#if (RTL8812A_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8812)
|
||||
platform_h2c_id = H2C_8812_RSSI_REPORT;
|
||||
else
|
||||
#endif
|
||||
{}
|
||||
#endif
|
||||
|
||||
break;
|
||||
|
||||
/* 1 [3] */
|
||||
case ODM_H2C_WIFI_CALIBRATION:
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
platform_h2c_id = H2C_WIFI_CALIBRATION;
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
#if (RTL8723B_SUPPORT == 1)
|
||||
platform_h2c_id = H2C_8723B_BT_WLAN_CALIBRATION;
|
||||
#endif
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
#endif
|
||||
break;
|
||||
|
||||
|
||||
/* 1 [4] */
|
||||
case ODM_H2C_IQ_CALIBRATION:
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
platform_h2c_id = H2C_IQ_CALIBRATION;
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
|
||||
platform_h2c_id = H2C_8812_IQ_CALIBRATION;
|
||||
#endif
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
#endif
|
||||
|
||||
break;
|
||||
/* 1 [5] */
|
||||
case ODM_H2C_RA_PARA_ADJUST:
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B))
|
||||
platform_h2c_id = H2C_8814A_RA_PARA_ADJUST;
|
||||
else
|
||||
platform_h2c_id = H2C_RA_PARA_ADJUST;
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
|
||||
platform_h2c_id = H2C_8812_RA_PARA_ADJUST;
|
||||
#elif ((RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1))
|
||||
platform_h2c_id = H2C_RA_PARA_ADJUST;
|
||||
#elif (RTL8192E_SUPPORT == 1)
|
||||
platform_h2c_id = H2C_8192E_RA_PARA_ADJUST;
|
||||
#elif (RTL8723B_SUPPORT == 1)
|
||||
platform_h2c_id = H2C_8723B_RA_PARA_ADJUST;
|
||||
#endif
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8881A || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES)
|
||||
platform_h2c_id = H2C_88XX_RA_PARA_ADJUST;
|
||||
else
|
||||
#endif
|
||||
#if (RTL8812A_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8812)
|
||||
platform_h2c_id = H2C_8812_RA_PARA_ADJUST;
|
||||
else
|
||||
#endif
|
||||
{}
|
||||
#endif
|
||||
|
||||
break;
|
||||
|
||||
|
||||
/* 1 [6] */
|
||||
case PHYDM_H2C_DYNAMIC_TX_PATH:
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8814A)
|
||||
platform_h2c_id = H2C_8814A_DYNAMIC_TX_PATH;
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8814A)
|
||||
platform_h2c_id = H2C_DYNAMIC_TX_PATH;
|
||||
#endif
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
#if (RTL8814A_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8814A)
|
||||
platform_h2c_id = H2C_88XX_DYNAMIC_TX_PATH;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
break;
|
||||
|
||||
/* [7]*/
|
||||
case PHYDM_H2C_FW_TRACE_EN:
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B))
|
||||
platform_h2c_id = H2C_8814A_FW_TRACE_EN;
|
||||
else
|
||||
platform_h2c_id = H2C_FW_TRACE_EN;
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
|
||||
platform_h2c_id = 0x49;
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8881A || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES)
|
||||
platform_h2c_id = H2C_88XX_FW_TRACE_EN;
|
||||
else
|
||||
#endif
|
||||
#if (RTL8812A_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8812)
|
||||
platform_h2c_id = H2C_8812_FW_TRACE_EN;
|
||||
else
|
||||
#endif
|
||||
{}
|
||||
|
||||
#endif
|
||||
|
||||
break;
|
||||
|
||||
case PHYDM_H2C_TXBF:
|
||||
#if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1))
|
||||
platform_h2c_id = 0x41; /*H2C_TxBF*/
|
||||
#endif
|
||||
break;
|
||||
|
||||
case PHYDM_H2C_MU:
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
platform_h2c_id = 0x4a; /*H2C_MU*/
|
||||
#endif
|
||||
break;
|
||||
|
||||
default:
|
||||
platform_h2c_id = phydm_h2c_id;
|
||||
break;
|
||||
}
|
||||
|
||||
return platform_h2c_id;
|
||||
|
||||
}
|
||||
|
||||
/*ODM FW relative API.*/
|
||||
|
@ -822,35 +377,7 @@ odm_fill_h2c_cmd(
|
|||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] platform_h2c_id = ((0x%x))\n", platform_h2c_id));
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8188E) {
|
||||
if (!p_dm_odm->ra_support88e)
|
||||
FillH2CCmd88E(adapter, platform_h2c_id, cmd_len, p_cmd_buffer);
|
||||
} else if (p_dm_odm->support_ic_type == ODM_RTL8814A)
|
||||
FillH2CCmd8814A(adapter, platform_h2c_id, cmd_len, p_cmd_buffer);
|
||||
else if (p_dm_odm->support_ic_type == ODM_RTL8822B)
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
FillH2CCmd8822B(adapter, platform_h2c_id, cmd_len, p_cmd_buffer);
|
||||
#endif
|
||||
else
|
||||
FillH2CCmd(adapter, platform_h2c_id, cmd_len, p_cmd_buffer);
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
rtw_hal_fill_h2c_cmd(adapter, platform_h2c_id, cmd_len, p_cmd_buffer);
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
|
||||
#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8881A || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES)
|
||||
GET_HAL_INTERFACE(p_dm_odm->priv)->fill_h2c_cmd_handler(p_dm_odm->priv, platform_h2c_id, cmd_len, p_cmd_buffer);
|
||||
else
|
||||
#endif
|
||||
#if (RTL8812A_SUPPORT == 1)
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8812)
|
||||
fill_h2c_cmd8812(p_dm_odm->priv, platform_h2c_id, cmd_len, p_cmd_buffer);
|
||||
else
|
||||
#endif
|
||||
{}
|
||||
#endif
|
||||
}
|
||||
|
||||
u8
|
||||
|
@ -862,9 +389,6 @@ phydm_c2H_content_parsing(
|
|||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
#endif
|
||||
u8 extend_c2h_sub_id = 0;
|
||||
u8 find_c2h_cmd = true;
|
||||
|
||||
|
@ -872,36 +396,18 @@ phydm_c2H_content_parsing(
|
|||
case PHYDM_C2H_DBG:
|
||||
phydm_fw_trace_handler(p_dm_odm, tmp_buf, c2h_cmd_len);
|
||||
break;
|
||||
|
||||
case PHYDM_C2H_RA_RPT:
|
||||
phydm_c2h_ra_report_handler(p_dm_odm, tmp_buf, c2h_cmd_len);
|
||||
break;
|
||||
|
||||
case PHYDM_C2H_RA_PARA_RPT:
|
||||
odm_c2h_ra_para_report_handler(p_dm_odm, tmp_buf, c2h_cmd_len);
|
||||
break;
|
||||
|
||||
case PHYDM_C2H_DYNAMIC_TX_PATH_RPT:
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8814A))
|
||||
phydm_c2h_dtp_handler(p_dm_odm, tmp_buf, c2h_cmd_len);
|
||||
break;
|
||||
|
||||
case PHYDM_C2H_IQK_FINISH:
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) {
|
||||
|
||||
RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK Finish ==\n"));
|
||||
odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK);
|
||||
p_dm_odm->rf_calibrate_info.is_iqk_in_progress = false;
|
||||
odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK);
|
||||
p_dm_odm->rf_calibrate_info.iqk_progressing_time = 0;
|
||||
p_dm_odm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(p_dm_odm, p_dm_odm->rf_calibrate_info.iqk_start_time);
|
||||
}
|
||||
|
||||
#endif
|
||||
break;
|
||||
|
||||
case PHYDM_C2H_DBG_CODE:
|
||||
phydm_fw_trace_handler_code(p_dm_odm, tmp_buf, c2h_cmd_len);
|
||||
break;
|
||||
|
@ -912,14 +418,11 @@ phydm_c2H_content_parsing(
|
|||
phydm_fw_trace_handler_8051(p_dm_odm, tmp_buf, c2h_cmd_len);
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
find_c2h_cmd = false;
|
||||
break;
|
||||
}
|
||||
|
||||
return find_c2h_cmd;
|
||||
|
||||
}
|
||||
|
||||
u64
|
||||
|
@ -927,13 +430,7 @@ odm_get_current_time(
|
|||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
return 0;
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
return (u64)rtw_get_current_time();
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
return PlatformGetCurrentTime();
|
||||
#endif
|
||||
}
|
||||
|
||||
u64
|
||||
|
@ -942,17 +439,9 @@ odm_get_progressing_time(
|
|||
u64 start_time
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
return 0;
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
return rtw_get_passing_time_ms((u32)start_time);
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
return ((PlatformGetCurrentTime() - start_time) >> 10);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
|
||||
void
|
||||
phydm_set_hw_reg_handler_interface (
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
|
@ -960,17 +449,9 @@ phydm_set_hw_reg_handler_interface (
|
|||
u8 *val
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
adapter->HalFunc.SetHwRegHandler(adapter, RegName, val);
|
||||
#else
|
||||
adapter->hal_func.set_hw_reg_handler(adapter, RegName, val);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
|
@ -980,16 +461,7 @@ phydm_get_hal_def_var_handler_interface (
|
|||
void *p_value
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
adapter->HalFunc.GetHalDefVarHandler(adapter, e_variable, p_value);
|
||||
#else
|
||||
adapter->hal_func.get_hal_def_var_handler(adapter, e_variable, p_value);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -39,8 +39,6 @@
|
|||
#define VALID_MAX 10
|
||||
#define VALID_CNT 5
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
|
||||
|
||||
static s16 odm_inband_noise_monitor_n_series(struct PHY_DM_STRUCT *p_dm_odm, u8 is_pause_dig, u8 igi_value, u32 max_time)
|
||||
{
|
||||
u32 tmp4b;
|
||||
|
@ -276,8 +274,6 @@ odm_inband_noise_monitor_ac_series(struct PHY_DM_STRUCT *p_dm_odm, u8 is_pause_d
|
|||
return p_dm_odm->noise_level.noise_all;
|
||||
}
|
||||
|
||||
|
||||
|
||||
s16
|
||||
odm_inband_noise_monitor(void *p_dm_void, u8 is_pause_dig, u8 igi_value, u32 max_time)
|
||||
{
|
||||
|
@ -288,5 +284,3 @@ odm_inband_noise_monitor(void *p_dm_void, u8 is_pause_dig, u8 igi_value, u32 max
|
|||
else
|
||||
return odm_inband_noise_monitor_n_series(p_dm_odm, is_pause_dig, igi_value, max_time);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -25,500 +25,7 @@
|
|||
#include "phydm_precomp.h"
|
||||
|
||||
#if (defined(CONFIG_PATH_DIVERSITY))
|
||||
#if RTL8814A_SUPPORT
|
||||
|
||||
void
|
||||
phydm_dtp_fix_tx_path(
|
||||
void *p_dm_void,
|
||||
u8 path
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &p_dm_odm->dm_path_div;
|
||||
u8 i, num_enable_path = 0;
|
||||
|
||||
if (path == p_dm_path_div->pre_tx_path)
|
||||
return;
|
||||
else
|
||||
p_dm_path_div->pre_tx_path = path;
|
||||
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(18) | BIT(19), 3);
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
if (path & BIT(i))
|
||||
num_enable_path++;
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" number of trun-on path : (( %d ))\n", num_enable_path));
|
||||
|
||||
if (num_enable_path == 1) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, 0xf00000, path);
|
||||
|
||||
if (path == PHYDM_A) { /* 1-1 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A ))\n"));
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0);
|
||||
} else if (path == PHYDM_B) { /* 1-2 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B ))\n"));
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 0);
|
||||
} else if (path == PHYDM_C) { /* 1-3 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( C ))\n"));
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 0);
|
||||
|
||||
} else if (path == PHYDM_D) { /* 1-4 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( D ))\n"));
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 0);
|
||||
}
|
||||
|
||||
} else if (num_enable_path == 2) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, 0xf00000, path);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, 0xf0, path);
|
||||
|
||||
if (path == PHYDM_AB) { /* 2-1 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B ))\n"));
|
||||
/* set for 1ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 1);
|
||||
/* set for 2ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 1);
|
||||
} else if (path == PHYDM_AC) { /* 2-2 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A C ))\n"));
|
||||
/* set for 1ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 1);
|
||||
/* set for 2ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 1);
|
||||
} else if (path == PHYDM_AD) { /* 2-3 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A D ))\n"));
|
||||
/* set for 1ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 1);
|
||||
/* set for 2ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 1);
|
||||
} else if (path == PHYDM_BC) { /* 2-4 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B C ))\n"));
|
||||
/* set for 1ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 1);
|
||||
/* set for 2ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 1);
|
||||
} else if (path == PHYDM_BD) { /* 2-5 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B D ))\n"));
|
||||
/* set for 1ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 1);
|
||||
/* set for 2ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 1);
|
||||
} else if (path == PHYDM_CD) { /* 2-6 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( C D ))\n"));
|
||||
/* set for 1ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 1);
|
||||
/* set for 2ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 1);
|
||||
}
|
||||
|
||||
} else if (num_enable_path == 3) {
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, 0xf00000, path);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, 0xf0, path);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, 0xf0000, path);
|
||||
|
||||
if (path == PHYDM_ABC) { /* 3-1 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B C))\n"));
|
||||
/* set for 1ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 2);
|
||||
/* set for 2ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 2);
|
||||
/* set for 3ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(21) | BIT(20), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(23) | BIT(22), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(25) | BIT(24), 2);
|
||||
} else if (path == PHYDM_ABD) { /* 3-2 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B D ))\n"));
|
||||
/* set for 1ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 2);
|
||||
/* set for 2ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 2);
|
||||
/* set for 3ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(21) | BIT(20), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(23) | BIT(22), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(27) | BIT(26), 2);
|
||||
|
||||
} else if (path == PHYDM_ACD) { /* 3-3 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A C D ))\n"));
|
||||
/* set for 1ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 2);
|
||||
/* set for 2ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 2);
|
||||
/* set for 3ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(21) | BIT(20), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(25) | BIT(24), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(27) | BIT(26), 2);
|
||||
} else if (path == PHYDM_BCD) { /* 3-4 */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B C D))\n"));
|
||||
/* set for 1ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 2);
|
||||
/* set for 2ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 2);
|
||||
/* set for 3ss */
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(23) | BIT(22), 0);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(25) | BIT(24), 1);
|
||||
odm_set_bb_reg(p_dm_odm, 0x940, BIT(27) | BIT(26), 2);
|
||||
}
|
||||
} else if (num_enable_path == 4)
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path ((A B C D))\n"));
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
phydm_find_default_path(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &p_dm_odm->dm_path_div;
|
||||
u32 rssi_avg_a = 0, rssi_avg_b = 0, rssi_avg_c = 0, rssi_avg_d = 0, rssi_avg_bcd = 0;
|
||||
u32 rssi_total_a = 0, rssi_total_b = 0, rssi_total_c = 0, rssi_total_d = 0;
|
||||
|
||||
/* 2 Default path Selection By RSSI */
|
||||
|
||||
rssi_avg_a = (p_dm_path_div->path_a_cnt_all > 0) ? (p_dm_path_div->path_a_sum_all / p_dm_path_div->path_a_cnt_all) : 0 ;
|
||||
rssi_avg_b = (p_dm_path_div->path_b_cnt_all > 0) ? (p_dm_path_div->path_b_sum_all / p_dm_path_div->path_b_cnt_all) : 0 ;
|
||||
rssi_avg_c = (p_dm_path_div->path_c_cnt_all > 0) ? (p_dm_path_div->path_c_sum_all / p_dm_path_div->path_c_cnt_all) : 0 ;
|
||||
rssi_avg_d = (p_dm_path_div->path_d_cnt_all > 0) ? (p_dm_path_div->path_d_sum_all / p_dm_path_div->path_d_cnt_all) : 0 ;
|
||||
|
||||
|
||||
p_dm_path_div->path_a_sum_all = 0;
|
||||
p_dm_path_div->path_a_cnt_all = 0;
|
||||
p_dm_path_div->path_b_sum_all = 0;
|
||||
p_dm_path_div->path_b_cnt_all = 0;
|
||||
p_dm_path_div->path_c_sum_all = 0;
|
||||
p_dm_path_div->path_c_cnt_all = 0;
|
||||
p_dm_path_div->path_d_sum_all = 0;
|
||||
p_dm_path_div->path_d_cnt_all = 0;
|
||||
|
||||
if (p_dm_path_div->use_path_a_as_default_ant == 1) {
|
||||
rssi_avg_bcd = (rssi_avg_b + rssi_avg_c + rssi_avg_d) / 3;
|
||||
|
||||
if ((rssi_avg_a + ANT_DECT_RSSI_TH) > rssi_avg_bcd) {
|
||||
p_dm_path_div->is_path_a_exist = true;
|
||||
p_dm_path_div->default_path = PATH_A;
|
||||
} else
|
||||
p_dm_path_div->is_path_a_exist = false;
|
||||
} else {
|
||||
if ((rssi_avg_a >= rssi_avg_b) && (rssi_avg_a >= rssi_avg_c) && (rssi_avg_a >= rssi_avg_d))
|
||||
p_dm_path_div->default_path = PATH_A;
|
||||
else if ((rssi_avg_b >= rssi_avg_c) && (rssi_avg_b >= rssi_avg_d))
|
||||
p_dm_path_div->default_path = PATH_B;
|
||||
else if (rssi_avg_c >= rssi_avg_d)
|
||||
p_dm_path_div->default_path = PATH_C;
|
||||
else
|
||||
p_dm_path_div->default_path = PATH_D;
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
phydm_candidate_dtp_update(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &p_dm_odm->dm_path_div;
|
||||
|
||||
p_dm_path_div->num_candidate = 3;
|
||||
|
||||
if (p_dm_path_div->use_path_a_as_default_ant == 1) {
|
||||
if (p_dm_path_div->num_tx_path == 3) {
|
||||
if (p_dm_path_div->is_path_a_exist) {
|
||||
p_dm_path_div->ant_candidate_1 = PHYDM_ABC;
|
||||
p_dm_path_div->ant_candidate_2 = PHYDM_ABD;
|
||||
p_dm_path_div->ant_candidate_3 = PHYDM_ACD;
|
||||
} else { /* use path BCD */
|
||||
p_dm_path_div->num_candidate = 1;
|
||||
phydm_dtp_fix_tx_path(p_dm_odm, PHYDM_BCD);
|
||||
return;
|
||||
}
|
||||
} else if (p_dm_path_div->num_tx_path == 2) {
|
||||
if (p_dm_path_div->is_path_a_exist) {
|
||||
p_dm_path_div->ant_candidate_1 = PHYDM_AB;
|
||||
p_dm_path_div->ant_candidate_2 = PHYDM_AC;
|
||||
p_dm_path_div->ant_candidate_3 = PHYDM_AD;
|
||||
} else {
|
||||
p_dm_path_div->ant_candidate_1 = PHYDM_BC;
|
||||
p_dm_path_div->ant_candidate_2 = PHYDM_BD;
|
||||
p_dm_path_div->ant_candidate_3 = PHYDM_CD;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
/* 2 3 TX mode */
|
||||
if (p_dm_path_div->num_tx_path == 3) { /* choose 3 ant form 4 */
|
||||
if (p_dm_path_div->default_path == PATH_A) { /* choose 2 ant form 3 */
|
||||
p_dm_path_div->ant_candidate_1 = PHYDM_ABC;
|
||||
p_dm_path_div->ant_candidate_2 = PHYDM_ABD;
|
||||
p_dm_path_div->ant_candidate_3 = PHYDM_ACD;
|
||||
} else if (p_dm_path_div->default_path == PATH_B) {
|
||||
p_dm_path_div->ant_candidate_1 = PHYDM_ABC;
|
||||
p_dm_path_div->ant_candidate_2 = PHYDM_ABD;
|
||||
p_dm_path_div->ant_candidate_3 = PHYDM_BCD;
|
||||
} else if (p_dm_path_div->default_path == PATH_C) {
|
||||
p_dm_path_div->ant_candidate_1 = PHYDM_ABC;
|
||||
p_dm_path_div->ant_candidate_2 = PHYDM_ACD;
|
||||
p_dm_path_div->ant_candidate_3 = PHYDM_BCD;
|
||||
} else if (p_dm_path_div->default_path == PATH_D) {
|
||||
p_dm_path_div->ant_candidate_1 = PHYDM_ABD;
|
||||
p_dm_path_div->ant_candidate_2 = PHYDM_ACD;
|
||||
p_dm_path_div->ant_candidate_3 = PHYDM_BCD;
|
||||
}
|
||||
}
|
||||
|
||||
/* 2 2 TX mode */
|
||||
else if (p_dm_path_div->num_tx_path == 2) { /* choose 2 ant form 4 */
|
||||
if (p_dm_path_div->default_path == PATH_A) { /* choose 2 ant form 3 */
|
||||
p_dm_path_div->ant_candidate_1 = PHYDM_AB;
|
||||
p_dm_path_div->ant_candidate_2 = PHYDM_AC;
|
||||
p_dm_path_div->ant_candidate_3 = PHYDM_AD;
|
||||
} else if (p_dm_path_div->default_path == PATH_B) {
|
||||
p_dm_path_div->ant_candidate_1 = PHYDM_AB;
|
||||
p_dm_path_div->ant_candidate_2 = PHYDM_BC;
|
||||
p_dm_path_div->ant_candidate_3 = PHYDM_BD;
|
||||
} else if (p_dm_path_div->default_path == PATH_C) {
|
||||
p_dm_path_div->ant_candidate_1 = PHYDM_AC;
|
||||
p_dm_path_div->ant_candidate_2 = PHYDM_BC;
|
||||
p_dm_path_div->ant_candidate_3 = PHYDM_CD;
|
||||
} else if (p_dm_path_div->default_path == PATH_D) {
|
||||
p_dm_path_div->ant_candidate_1 = PHYDM_AD;
|
||||
p_dm_path_div->ant_candidate_2 = PHYDM_BD;
|
||||
p_dm_path_div->ant_candidate_3 = PHYDM_CD;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
phydm_dynamic_tx_path(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &p_dm_odm->dm_path_div;
|
||||
|
||||
struct sta_info *p_entry;
|
||||
u32 i;
|
||||
u8 num_client = 0;
|
||||
u8 h2c_parameter[6] = {0};
|
||||
|
||||
|
||||
if (!p_dm_odm->is_linked) { /* is_linked==False */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("DTP_8814 [No Link!!!]\n"));
|
||||
|
||||
if (p_dm_path_div->is_become_linked == true) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" [Be disconnected]----->\n"));
|
||||
p_dm_path_div->is_become_linked = p_dm_odm->is_linked;
|
||||
}
|
||||
return;
|
||||
} else {
|
||||
if (p_dm_path_div->is_become_linked == false) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" [Be Linked !!!]----->\n"));
|
||||
p_dm_path_div->is_become_linked = p_dm_odm->is_linked;
|
||||
}
|
||||
}
|
||||
|
||||
/* 2 [period CTRL] */
|
||||
if (p_dm_path_div->dtp_period >= 2)
|
||||
p_dm_path_div->dtp_period = 0;
|
||||
else {
|
||||
/* ODM_RT_TRACE(p_dm_odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Phydm_Dynamic_Tx_Path_8814A() Stay = (( %d ))\n",p_dm_path_div->dtp_period)); */
|
||||
p_dm_path_div->dtp_period++;
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/* 2 [Fix path] */
|
||||
if (p_dm_odm->path_select != PHYDM_AUTO_PATH)
|
||||
return;
|
||||
|
||||
/* 2 [Check Bfer] */
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
{
|
||||
enum beamforming_cap beamform_cap = (p_dm_odm->beamforming_info.beamform_cap);
|
||||
|
||||
if (beamform_cap & BEAMFORMER_CAP) { /* BFmer On && Div On->Div Off */
|
||||
if (p_dm_path_div->fix_path_bfer == 0) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("[ PathDiv : OFF ] BFmer ==1\n"));
|
||||
p_dm_path_div->fix_path_bfer = 1 ;
|
||||
}
|
||||
return;
|
||||
} else { /* BFmer Off && Div Off->Div On */
|
||||
if (p_dm_path_div->fix_path_bfer == 1) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("[ PathDiv : ON ] BFmer ==0\n"));
|
||||
p_dm_path_div->fix_path_bfer = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
if (p_dm_path_div->use_path_a_as_default_ant == 1) {
|
||||
phydm_find_default_path(p_dm_odm);
|
||||
phydm_candidate_dtp_update(p_dm_odm);
|
||||
} else {
|
||||
if (p_dm_path_div->phydm_dtp_state == PHYDM_DTP_INIT) {
|
||||
phydm_find_default_path(p_dm_odm);
|
||||
phydm_candidate_dtp_update(p_dm_odm);
|
||||
p_dm_path_div->phydm_dtp_state = PHYDM_DTP_RUNNING_1;
|
||||
}
|
||||
|
||||
else if (p_dm_path_div->phydm_dtp_state == PHYDM_DTP_RUNNING_1) {
|
||||
p_dm_path_div->dtp_check_patha_counter++;
|
||||
|
||||
if (p_dm_path_div->dtp_check_patha_counter >= NUM_RESET_DTP_PERIOD) {
|
||||
p_dm_path_div->dtp_check_patha_counter = 0;
|
||||
p_dm_path_div->phydm_dtp_state = PHYDM_DTP_INIT;
|
||||
}
|
||||
/* 2 Search space update */
|
||||
else {
|
||||
/* 1. find the worst candidate */
|
||||
|
||||
|
||||
/* 2. repalce the worst candidate */
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* 2 Dynamic path Selection H2C */
|
||||
|
||||
if (p_dm_path_div->num_candidate == 1)
|
||||
return;
|
||||
else {
|
||||
h2c_parameter[0] = p_dm_path_div->num_candidate;
|
||||
h2c_parameter[1] = p_dm_path_div->num_tx_path;
|
||||
h2c_parameter[2] = p_dm_path_div->ant_candidate_1;
|
||||
h2c_parameter[3] = p_dm_path_div->ant_candidate_2;
|
||||
h2c_parameter[4] = p_dm_path_div->ant_candidate_3;
|
||||
|
||||
odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_DYNAMIC_TX_PATH, 6, h2c_parameter);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
void
|
||||
phydm_dynamic_tx_path_init(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &(p_dm_odm->dm_path_div);
|
||||
struct _ADAPTER *p_adapter = p_dm_odm->adapter;
|
||||
#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) && USB_SWITCH_SUPPORT)
|
||||
USB_MODE_MECH *p_usb_mode_mech = &p_adapter->usb_mode_mechanism;
|
||||
#endif
|
||||
u8 search_space_2[NUM_CHOOSE2_FROM4] = {PHYDM_AB, PHYDM_AC, PHYDM_AD, PHYDM_BC, PHYDM_BD, PHYDM_CD };
|
||||
u8 search_space_3[NUM_CHOOSE3_FROM4] = {PHYDM_BCD, PHYDM_ACD, PHYDM_ABD, PHYDM_ABC};
|
||||
|
||||
#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) && USB_SWITCH_SUPPORT)
|
||||
p_dm_path_div->is_u3_mode = (p_usb_mode_mech->cur_usb_mode == USB_MODE_U3) ? 1 : 0 ;
|
||||
#else
|
||||
p_dm_path_div->is_u3_mode = 1;
|
||||
#endif
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Dynamic TX path Init 8814\n"));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("is_u3_mode = (( %d ))\n", p_dm_path_div->is_u3_mode));
|
||||
|
||||
memcpy(&(p_dm_path_div->search_space_2[0]), &(search_space_2[0]), NUM_CHOOSE2_FROM4);
|
||||
memcpy(&(p_dm_path_div->search_space_3[0]), &(search_space_3[0]), NUM_CHOOSE3_FROM4);
|
||||
|
||||
p_dm_path_div->use_path_a_as_default_ant = 1;
|
||||
p_dm_path_div->phydm_dtp_state = PHYDM_DTP_INIT;
|
||||
p_dm_odm->path_select = PHYDM_AUTO_PATH;
|
||||
p_dm_path_div->phydm_path_div_type = PHYDM_4R_PATH_DIV;
|
||||
|
||||
|
||||
if (p_dm_path_div->is_u3_mode) {
|
||||
p_dm_path_div->num_tx_path = 3;
|
||||
phydm_dtp_fix_tx_path(p_dm_odm, PHYDM_BCD);/* 3TX Set Init TX path*/
|
||||
|
||||
} else {
|
||||
p_dm_path_div->num_tx_path = 2;
|
||||
phydm_dtp_fix_tx_path(p_dm_odm, PHYDM_BC);/* 2TX // Set Init TX path*/
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
phydm_process_rssi_for_path_div(
|
||||
void *p_dm_void,
|
||||
void *p_phy_info_void,
|
||||
void *p_pkt_info_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)p_phy_info_void;
|
||||
struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pkt_info_void;
|
||||
struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &(p_dm_odm->dm_path_div);
|
||||
|
||||
if (p_pktinfo->is_packet_to_self || p_pktinfo->is_packet_match_bssid) {
|
||||
if (p_pktinfo->data_rate > ODM_RATE11M) {
|
||||
if (p_dm_path_div->phydm_path_div_type == PHYDM_4R_PATH_DIV) {
|
||||
#if RTL8814A_SUPPORT
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8814A) {
|
||||
p_dm_path_div->path_a_sum_all += p_phy_info->rx_mimo_signal_strength[0];
|
||||
p_dm_path_div->path_a_cnt_all++;
|
||||
|
||||
p_dm_path_div->path_b_sum_all += p_phy_info->rx_mimo_signal_strength[1];
|
||||
p_dm_path_div->path_b_cnt_all++;
|
||||
|
||||
p_dm_path_div->path_c_sum_all += p_phy_info->rx_mimo_signal_strength[2];
|
||||
p_dm_path_div->path_c_cnt_all++;
|
||||
|
||||
p_dm_path_div->path_d_sum_all += p_phy_info->rx_mimo_signal_strength[3];
|
||||
p_dm_path_div->path_d_cnt_all++;
|
||||
}
|
||||
#endif
|
||||
} else {
|
||||
p_dm_path_div->path_a_sum[p_pktinfo->station_id] += p_phy_info->rx_mimo_signal_strength[0];
|
||||
p_dm_path_div->path_a_cnt[p_pktinfo->station_id]++;
|
||||
|
||||
p_dm_path_div->path_b_sum[p_pktinfo->station_id] += p_phy_info->rx_mimo_signal_strength[1];
|
||||
p_dm_path_div->path_b_cnt[p_pktinfo->station_id]++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
#endif /* #if RTL8814A_SUPPORT */
|
||||
|
||||
void
|
||||
odm_pathdiv_debug(
|
||||
void *p_dm_void,
|
||||
void odm_pathdiv_debug(void *p_dm_void,
|
||||
u32 *const dm_value,
|
||||
u32 *_used,
|
||||
char *output,
|
||||
|
@ -566,20 +73,6 @@ phydm_c2h_dtp_handler(
|
|||
u8 nsc_3 = cmd_buf[4];
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Target_candidate = (( %d ))\n", target));
|
||||
/*
|
||||
if( (nsc_1 >= nsc_2) && (nsc_1 >= nsc_3))
|
||||
{
|
||||
phydm_dtp_fix_tx_path(p_dm_odm, p_dm_path_div->ant_candidate_1);
|
||||
}
|
||||
else if( nsc_2 >= nsc_3)
|
||||
{
|
||||
phydm_dtp_fix_tx_path(p_dm_odm, p_dm_path_div->ant_candidate_2);
|
||||
}
|
||||
else
|
||||
{
|
||||
phydm_dtp_fix_tx_path(p_dm_odm, p_dm_path_div->ant_candidate_3);
|
||||
}
|
||||
*/
|
||||
#endif
|
||||
}
|
||||
|
||||
|
@ -594,20 +87,6 @@ odm_path_diversity(
|
|||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Return: Not Support PathDiv\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
#if RTL8812A_SUPPORT
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8812)
|
||||
odm_path_diversity_8812a(p_dm_odm);
|
||||
else
|
||||
#endif
|
||||
|
||||
#if RTL8814A_SUPPORT
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
phydm_dynamic_tx_path(p_dm_odm);
|
||||
else
|
||||
#endif
|
||||
{}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
@ -628,69 +107,5 @@ odm_path_diversity_init(
|
|||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Return: Not Support PathDiv\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
#if RTL8812A_SUPPORT
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8812)
|
||||
odm_path_diversity_init_8812a(p_dm_odm);
|
||||
else
|
||||
#endif
|
||||
|
||||
#if RTL8814A_SUPPORT
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
phydm_dynamic_tx_path_init(p_dm_odm);
|
||||
else
|
||||
#endif
|
||||
{}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
/*
|
||||
* 2011/12/02 MH Copy from MP oursrc for temporarily test.
|
||||
* */
|
||||
|
||||
void
|
||||
odm_path_div_chk_ant_switch_callback(
|
||||
struct timer_list *p_timer
|
||||
)
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
odm_path_div_chk_ant_switch_workitem_callback(
|
||||
void *p_context
|
||||
)
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
odm_cck_tx_path_diversity_callback(
|
||||
struct timer_list *p_timer
|
||||
)
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
odm_cck_tx_path_diversity_work_item_callback(
|
||||
void *p_context
|
||||
)
|
||||
{
|
||||
}
|
||||
u8
|
||||
odm_sw_ant_div_select_scan_chnl(
|
||||
struct _ADAPTER *adapter
|
||||
)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
void
|
||||
odm_sw_ant_div_construct_scan_chnl(
|
||||
struct _ADAPTER *adapter,
|
||||
u8 scan_chnl
|
||||
)
|
||||
{
|
||||
}
|
||||
|
||||
#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) */
|
||||
|
|
|
@ -149,171 +149,4 @@ odm_pathdiv_debug(
|
|||
u32 *_out_len
|
||||
);
|
||||
|
||||
|
||||
|
||||
/* 1 [OLD IC]-------------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
|
||||
|
||||
/* #define PATHDIV_ENABLE 1 */
|
||||
#define dm_path_div_rssi_check odm_path_div_chk_per_pkt_rssi
|
||||
#define path_div_check_before_link8192c odm_path_diversity_before_link92c
|
||||
|
||||
|
||||
|
||||
|
||||
struct _path_div_parameter_define_ {
|
||||
u32 org_5g_rege30;
|
||||
u32 org_5g_regc14;
|
||||
u32 org_5g_regca0;
|
||||
u32 swt_5g_rege30;
|
||||
u32 swt_5g_regc14;
|
||||
u32 swt_5g_regca0;
|
||||
/* for 2G IQK information */
|
||||
u32 org_2g_regc80;
|
||||
u32 org_2g_regc4c;
|
||||
u32 org_2g_regc94;
|
||||
u32 org_2g_regc14;
|
||||
u32 org_2g_regca0;
|
||||
|
||||
u32 swt_2g_regc80;
|
||||
u32 swt_2g_regc4c;
|
||||
u32 swt_2g_regc94;
|
||||
u32 swt_2g_regc14;
|
||||
u32 swt_2g_regca0;
|
||||
};
|
||||
|
||||
void
|
||||
odm_path_diversity_init_92c(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_2t_path_diversity_init_92c(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_1t_path_diversity_init_92c(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
bool
|
||||
odm_is_connected_92c(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
bool
|
||||
odm_path_diversity_before_link92c(
|
||||
/* struct _ADAPTER* adapter */
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
void
|
||||
odm_path_diversity_after_link_92c(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_set_resp_path_92c(
|
||||
struct _ADAPTER *adapter,
|
||||
u8 default_resp_path
|
||||
);
|
||||
|
||||
void
|
||||
odm_ofdm_tx_path_diversity_92c(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_cck_tx_path_diversity_92c(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_reset_path_diversity_92c(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_cck_tx_path_diversity_callback(
|
||||
struct timer_list *p_timer
|
||||
);
|
||||
|
||||
void
|
||||
odm_cck_tx_path_diversity_work_item_callback(
|
||||
void *p_context
|
||||
);
|
||||
|
||||
void
|
||||
odm_path_div_chk_ant_switch_callback(
|
||||
struct timer_list *p_timer
|
||||
);
|
||||
|
||||
void
|
||||
odm_path_div_chk_ant_switch_workitem_callback(
|
||||
void *p_context
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
odm_path_div_chk_ant_switch(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
void
|
||||
odm_cck_path_diversity_chk_per_pkt_rssi(
|
||||
struct _ADAPTER *adapter,
|
||||
bool is_def_port,
|
||||
bool is_match_bssid,
|
||||
struct _WLAN_STA *p_entry,
|
||||
PRT_RFD p_rfd,
|
||||
u8 *p_desc
|
||||
);
|
||||
|
||||
void
|
||||
odm_path_div_chk_per_pkt_rssi(
|
||||
struct _ADAPTER *adapter,
|
||||
bool is_def_port,
|
||||
bool is_match_bssid,
|
||||
struct _WLAN_STA *p_entry,
|
||||
PRT_RFD p_rfd
|
||||
);
|
||||
|
||||
void
|
||||
odm_path_div_rest_after_link(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
void
|
||||
odm_fill_tx_path_in_txdesc(
|
||||
struct _ADAPTER *adapter,
|
||||
PRT_TCB p_tcb,
|
||||
u8 *p_desc
|
||||
);
|
||||
|
||||
void
|
||||
odm_path_div_init_92d(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
u8
|
||||
odm_sw_ant_div_select_scan_chnl(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_sw_ant_div_construct_scan_chnl(
|
||||
struct _ADAPTER *adapter,
|
||||
u8 scan_chnl
|
||||
);
|
||||
|
||||
#endif /* #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) */
|
||||
|
||||
|
||||
#endif /* #ifndef __ODMPATHDIV_H__ */
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -169,11 +169,7 @@ struct odm_rf_calibration_structure {
|
|||
|
||||
u8 bb_swing_idx_ofdm[MAX_RF_PATH];
|
||||
u8 bb_swing_idx_ofdm_current;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
|
||||
#else
|
||||
u8 bb_swing_idx_ofdm_base;
|
||||
#endif
|
||||
bool default_bb_swing_index_flag;
|
||||
bool bb_swing_flag_ofdm;
|
||||
u8 bb_swing_idx_cck;
|
||||
|
@ -302,33 +298,4 @@ odm_txpowertracking_check_ce(
|
|||
void *p_dm_void
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
|
||||
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter92c(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_callback_rx_gain_thermal_meter92d(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_callback_thermal_meter92d(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_direct_call92c(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
void
|
||||
odm_txpowertracking_thermal_meter_check(
|
||||
struct _ADAPTER *adapter
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
@ -1,749 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* ************************************************************
|
||||
* include files
|
||||
* ************************************************************ */
|
||||
#include "mp_precomp.h"
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
/* ************************************************************
|
||||
* Global var
|
||||
* ************************************************************ */
|
||||
|
||||
u32 ofdm_swing_table[OFDM_TABLE_SIZE] = {
|
||||
0x7f8001fe, /* 0, +6.0dB */
|
||||
0x788001e2, /* 1, +5.5dB */
|
||||
0x71c001c7, /* 2, +5.0dB */
|
||||
0x6b8001ae, /* 3, +4.5dB */
|
||||
0x65400195, /* 4, +4.0dB */
|
||||
0x5fc0017f, /* 5, +3.5dB */
|
||||
0x5a400169, /* 6, +3.0dB */
|
||||
0x55400155, /* 7, +2.5dB */
|
||||
0x50800142, /* 8, +2.0dB */
|
||||
0x4c000130, /* 9, +1.5dB */
|
||||
0x47c0011f, /* 10, +1.0dB */
|
||||
0x43c0010f, /* 11, +0.5dB */
|
||||
0x40000100, /* 12, +0dB */
|
||||
0x3c8000f2, /* 13, -0.5dB */
|
||||
0x390000e4, /* 14, -1.0dB */
|
||||
0x35c000d7, /* 15, -1.5dB */
|
||||
0x32c000cb, /* 16, -2.0dB */
|
||||
0x300000c0, /* 17, -2.5dB */
|
||||
0x2d4000b5, /* 18, -3.0dB */
|
||||
0x2ac000ab, /* 19, -3.5dB */
|
||||
0x288000a2, /* 20, -4.0dB */
|
||||
0x26000098, /* 21, -4.5dB */
|
||||
0x24000090, /* 22, -5.0dB */
|
||||
0x22000088, /* 23, -5.5dB */
|
||||
0x20000080, /* 24, -6.0dB */
|
||||
0x1e400079, /* 25, -6.5dB */
|
||||
0x1c800072, /* 26, -7.0dB */
|
||||
0x1b00006c, /* 27. -7.5dB */
|
||||
0x19800066, /* 28, -8.0dB */
|
||||
0x18000060, /* 29, -8.5dB */
|
||||
0x16c0005b, /* 30, -9.0dB */
|
||||
0x15800056, /* 31, -9.5dB */
|
||||
0x14400051, /* 32, -10.0dB */
|
||||
0x1300004c, /* 33, -10.5dB */
|
||||
0x12000048, /* 34, -11.0dB */
|
||||
0x11000044, /* 35, -11.5dB */
|
||||
0x10000040, /* 36, -12.0dB */
|
||||
};
|
||||
|
||||
u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
|
||||
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
|
||||
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
|
||||
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
|
||||
{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
|
||||
{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
|
||||
{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
|
||||
{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
|
||||
{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
|
||||
{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
|
||||
{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
|
||||
{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
|
||||
{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
|
||||
{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB <== default */
|
||||
{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
|
||||
{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
|
||||
{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
|
||||
{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
|
||||
{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
|
||||
{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
|
||||
{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
|
||||
{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */
|
||||
{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */
|
||||
{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */
|
||||
{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */
|
||||
{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */
|
||||
{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */
|
||||
{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */
|
||||
{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */
|
||||
{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */
|
||||
{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */
|
||||
{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */
|
||||
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */
|
||||
{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */
|
||||
};
|
||||
|
||||
|
||||
u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
|
||||
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
|
||||
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
|
||||
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
|
||||
{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
|
||||
{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
|
||||
{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
|
||||
{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
|
||||
{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
|
||||
{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
|
||||
{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
|
||||
{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
|
||||
{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
|
||||
{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB <== default */
|
||||
{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
|
||||
{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
|
||||
{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
|
||||
{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
|
||||
{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
|
||||
{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
|
||||
{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
|
||||
{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */
|
||||
{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */
|
||||
{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */
|
||||
{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */
|
||||
{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */
|
||||
{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */
|
||||
{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */
|
||||
{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */
|
||||
{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */
|
||||
{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */
|
||||
{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */
|
||||
{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */
|
||||
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */
|
||||
};
|
||||
|
||||
|
||||
u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
|
||||
0x0b40002d, /* 0, -15.0dB */
|
||||
0x0c000030, /* 1, -14.5dB */
|
||||
0x0cc00033, /* 2, -14.0dB */
|
||||
0x0d800036, /* 3, -13.5dB */
|
||||
0x0e400039, /* 4, -13.0dB */
|
||||
0x0f00003c, /* 5, -12.5dB */
|
||||
0x10000040, /* 6, -12.0dB */
|
||||
0x11000044, /* 7, -11.5dB */
|
||||
0x12000048, /* 8, -11.0dB */
|
||||
0x1300004c, /* 9, -10.5dB */
|
||||
0x14400051, /* 10, -10.0dB */
|
||||
0x15800056, /* 11, -9.5dB */
|
||||
0x16c0005b, /* 12, -9.0dB */
|
||||
0x18000060, /* 13, -8.5dB */
|
||||
0x19800066, /* 14, -8.0dB */
|
||||
0x1b00006c, /* 15, -7.5dB */
|
||||
0x1c800072, /* 16, -7.0dB */
|
||||
0x1e400079, /* 17, -6.5dB */
|
||||
0x20000080, /* 18, -6.0dB */
|
||||
0x22000088, /* 19, -5.5dB */
|
||||
0x24000090, /* 20, -5.0dB */
|
||||
0x26000098, /* 21, -4.5dB */
|
||||
0x288000a2, /* 22, -4.0dB */
|
||||
0x2ac000ab, /* 23, -3.5dB */
|
||||
0x2d4000b5, /* 24, -3.0dB */
|
||||
0x300000c0, /* 25, -2.5dB */
|
||||
0x32c000cb, /* 26, -2.0dB */
|
||||
0x35c000d7, /* 27, -1.5dB */
|
||||
0x390000e4, /* 28, -1.0dB */
|
||||
0x3c8000f2, /* 29, -0.5dB */
|
||||
0x40000100, /* 30, +0dB */
|
||||
0x43c0010f, /* 31, +0.5dB */
|
||||
0x47c0011f, /* 32, +1.0dB */
|
||||
0x4c000130, /* 33, +1.5dB */
|
||||
0x50800142, /* 34, +2.0dB */
|
||||
0x55400155, /* 35, +2.5dB */
|
||||
0x5a400169, /* 36, +3.0dB */
|
||||
0x5fc0017f, /* 37, +3.5dB */
|
||||
0x65400195, /* 38, +4.0dB */
|
||||
0x6b8001ae, /* 39, +4.5dB */
|
||||
0x71c001c7, /* 40, +5.0dB */
|
||||
0x788001e2, /* 41, +5.5dB */
|
||||
0x7f8001fe /* 42, +6.0dB */
|
||||
};
|
||||
|
||||
|
||||
u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
|
||||
{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
|
||||
{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
|
||||
{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
|
||||
{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
|
||||
{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
|
||||
{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
|
||||
{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
|
||||
{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
|
||||
{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
|
||||
{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
|
||||
{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
|
||||
{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
|
||||
{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
|
||||
{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
|
||||
{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
|
||||
{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
|
||||
{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
|
||||
{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
|
||||
{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
|
||||
{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
|
||||
{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
|
||||
};
|
||||
|
||||
|
||||
u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
|
||||
{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
|
||||
{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
|
||||
{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
|
||||
{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
|
||||
{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
|
||||
{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
|
||||
{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
|
||||
{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
|
||||
{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
|
||||
{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
|
||||
{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
|
||||
{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
|
||||
{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
|
||||
{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
|
||||
{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
|
||||
{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
|
||||
{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
|
||||
{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
|
||||
{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
|
||||
{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
|
||||
{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
|
||||
};
|
||||
|
||||
|
||||
u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
|
||||
{0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
|
||||
{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
|
||||
{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
|
||||
{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
|
||||
{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
|
||||
{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
|
||||
{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
|
||||
{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
|
||||
{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
|
||||
{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
|
||||
{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
|
||||
{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
|
||||
{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
|
||||
{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
|
||||
{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
|
||||
{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
|
||||
{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
|
||||
{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
|
||||
{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
|
||||
{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
|
||||
{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
|
||||
{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB */
|
||||
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB */
|
||||
{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB */
|
||||
{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB */
|
||||
{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB */
|
||||
{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB */
|
||||
{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB */
|
||||
{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB */
|
||||
{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB */
|
||||
{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB */
|
||||
{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB */
|
||||
{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB */
|
||||
{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB */
|
||||
{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB */
|
||||
{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */
|
||||
{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB */
|
||||
{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
|
||||
{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB */
|
||||
{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */
|
||||
{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB */
|
||||
{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 20, -6.0dB */
|
||||
{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB */
|
||||
{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */
|
||||
{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB */
|
||||
{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */
|
||||
{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB */
|
||||
{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB */
|
||||
{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB */
|
||||
{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */
|
||||
{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB */
|
||||
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB */
|
||||
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB */
|
||||
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB */
|
||||
};
|
||||
|
||||
|
||||
u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
|
||||
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB */
|
||||
{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB */
|
||||
{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB */
|
||||
{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB */
|
||||
{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB */
|
||||
{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 5, -13.5dB */
|
||||
{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB */
|
||||
{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB */
|
||||
{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB */
|
||||
{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB */
|
||||
{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB */
|
||||
{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 11, -10.5dB */
|
||||
{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB */
|
||||
{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB */
|
||||
{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 14, -9.0dB */
|
||||
{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB */
|
||||
{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
|
||||
{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB */
|
||||
{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */
|
||||
{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */
|
||||
{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */
|
||||
{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB */
|
||||
{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */
|
||||
{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 23, -4.5dB */
|
||||
{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */
|
||||
{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */
|
||||
{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */
|
||||
{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 27, -2.5dB */
|
||||
{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */
|
||||
{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 29, -1.5dB */
|
||||
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */
|
||||
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */
|
||||
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */
|
||||
};
|
||||
u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
|
||||
0x0CD,
|
||||
0x0D9,
|
||||
0x0E6,
|
||||
0x0F3,
|
||||
0x102,
|
||||
0x111,
|
||||
0x121,
|
||||
0x132,
|
||||
0x144,
|
||||
0x158,
|
||||
0x16C,
|
||||
0x182,
|
||||
0x198,
|
||||
0x1B1,
|
||||
0x1CA,
|
||||
0x1E5,
|
||||
0x202,
|
||||
0x221,
|
||||
0x241,
|
||||
0x263,
|
||||
0x287,
|
||||
0x2AE,
|
||||
0x2D6,
|
||||
0x301,
|
||||
0x32F,
|
||||
0x35F,
|
||||
0x392,
|
||||
0x3C9,
|
||||
0x402,
|
||||
0x43F,
|
||||
0x47F,
|
||||
0x4C3,
|
||||
0x50C,
|
||||
0x558,
|
||||
0x5A9,
|
||||
0x5FF,
|
||||
0x65A,
|
||||
0x6BA,
|
||||
0x720,
|
||||
0x78C,
|
||||
0x7FF,
|
||||
};
|
||||
|
||||
|
||||
u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
|
||||
0x081, /* 0, -12.0dB */
|
||||
0x088, /* 1, -11.5dB */
|
||||
0x090, /* 2, -11.0dB */
|
||||
0x099, /* 3, -10.5dB */
|
||||
0x0A2, /* 4, -10.0dB */
|
||||
0x0AC, /* 5, -9.5dB */
|
||||
0x0B6, /* 6, -9.0dB */
|
||||
0x0C0, /* 7, -8.5dB */
|
||||
0x0CC, /* 8, -8.0dB */
|
||||
0x0D8, /* 9, -7.5dB */
|
||||
0x0E5, /* 10, -7.0dB */
|
||||
0x0F2, /* 11, -6.5dB */
|
||||
0x101, /* 12, -6.0dB */
|
||||
0x110, /* 13, -5.5dB */
|
||||
0x120, /* 14, -5.0dB */
|
||||
0x131, /* 15, -4.5dB */
|
||||
0x143, /* 16, -4.0dB */
|
||||
0x156, /* 17, -3.5dB */
|
||||
0x16A, /* 18, -3.0dB */
|
||||
0x180, /* 19, -2.5dB */
|
||||
0x197, /* 20, -2.0dB */
|
||||
0x1AF, /* 21, -1.5dB */
|
||||
0x1C8, /* 22, -1.0dB */
|
||||
0x1E3, /* 23, -0.5dB */
|
||||
0x200, /* 24, +0 dB */
|
||||
0x21E, /* 25, +0.5dB */
|
||||
0x23E, /* 26, +1.0dB */
|
||||
0x261, /* 27, +1.5dB */
|
||||
0x285, /* 28, +2.0dB */
|
||||
0x2AB, /* 29, +2.5dB */
|
||||
0x2D3, /* 30, +3.0dB */
|
||||
0x2FE, /* 31, +3.5dB */
|
||||
0x32B, /* 32, +4.0dB */
|
||||
0x35C, /* 33, +4.5dB */
|
||||
0x38E, /* 34, +5.0dB */
|
||||
0x3C4, /* 35, +5.5dB */
|
||||
0x3FE /* 36, +6.0dB */
|
||||
};
|
||||
|
||||
|
||||
#ifdef AP_BUILD_WORKAROUND
|
||||
|
||||
unsigned int tx_pwr_trk_ofdm_swing_tbl[tx_pwr_trk_ofdm_swing_tbl_len] = {
|
||||
/* +6.0dB */ 0x7f8001fe,
|
||||
/* +5.5dB */ 0x788001e2,
|
||||
/* +5.0dB */ 0x71c001c7,
|
||||
/* +4.5dB */ 0x6b8001ae,
|
||||
/* +4.0dB */ 0x65400195,
|
||||
/* +3.5dB */ 0x5fc0017f,
|
||||
/* +3.0dB */ 0x5a400169,
|
||||
/* +2.5dB */ 0x55400155,
|
||||
/* +2.0dB */ 0x50800142,
|
||||
/* +1.5dB */ 0x4c000130,
|
||||
/* +1.0dB */ 0x47c0011f,
|
||||
/* +0.5dB */ 0x43c0010f,
|
||||
/* 0.0dB */ 0x40000100,
|
||||
/* -0.5dB */ 0x3c8000f2,
|
||||
/* -1.0dB */ 0x390000e4,
|
||||
/* -1.5dB */ 0x35c000d7,
|
||||
/* -2.0dB */ 0x32c000cb,
|
||||
/* -2.5dB */ 0x300000c0,
|
||||
/* -3.0dB */ 0x2d4000b5,
|
||||
/* -3.5dB */ 0x2ac000ab,
|
||||
/* -4.0dB */ 0x288000a2,
|
||||
/* -4.5dB */ 0x26000098,
|
||||
/* -5.0dB */ 0x24000090,
|
||||
/* -5.5dB */ 0x22000088,
|
||||
/* -6.0dB */ 0x20000080,
|
||||
/* -6.5dB */ 0x1a00006c,
|
||||
/* -7.0dB */ 0x1c800072,
|
||||
/* -7.5dB */ 0x18000060,
|
||||
/* -8.0dB */ 0x19800066,
|
||||
/* -8.5dB */ 0x15800056,
|
||||
/* -9.0dB */ 0x26c0005b,
|
||||
/* -9.5dB */ 0x14400051,
|
||||
/* -10.0dB */ 0x24400051,
|
||||
/* -10.5dB */ 0x1300004c,
|
||||
/* -11.0dB */ 0x12000048,
|
||||
/* -11.5dB */ 0x11000044,
|
||||
/* -12.0dB */ 0x10000040
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
void
|
||||
odm_txpowertracking_init(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
if (!(p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_IC_11N_SERIES | ODM_RTL8822B)))
|
||||
return;
|
||||
#endif
|
||||
|
||||
odm_txpowertracking_thermal_meter_init(p_dm_odm);
|
||||
}
|
||||
|
||||
u8
|
||||
get_swing_index(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
u8 i = 0;
|
||||
u32 bb_swing;
|
||||
u32 swing_table_size;
|
||||
u32 *p_swing_table;
|
||||
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8703B) {
|
||||
bb_swing = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000);
|
||||
|
||||
p_swing_table = ofdm_swing_table_new;
|
||||
swing_table_size = OFDM_TABLE_SIZE;
|
||||
} else {
|
||||
bb_swing = PHY_GetTxBBSwing_8812A(adapter, p_hal_data->CurrentBandType, ODM_RF_PATH_A);
|
||||
p_swing_table = tx_scaling_table_jaguar;
|
||||
swing_table_size = TXSCALE_TABLE_SIZE;
|
||||
}
|
||||
|
||||
for (i = 0; i < swing_table_size; ++i) {
|
||||
u32 table_value = p_swing_table[i];
|
||||
|
||||
if (table_value >= 0x100000)
|
||||
table_value >>= 22;
|
||||
if (bb_swing == table_value)
|
||||
break;
|
||||
}
|
||||
return i;
|
||||
}
|
||||
|
||||
void
|
||||
odm_txpowertracking_thermal_meter_init(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u8 default_swing_index = get_swing_index(p_dm_odm);
|
||||
struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
u8 p = 0;
|
||||
|
||||
if (p_dm_odm->mp_mode == false)
|
||||
p_rf_calibrate_info->txpowertrack_control = true;
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
{
|
||||
p_rf_calibrate_info->is_txpowertracking = _TRUE;
|
||||
p_rf_calibrate_info->tx_powercount = 0;
|
||||
p_rf_calibrate_info->is_txpowertracking_init = _FALSE;
|
||||
|
||||
if (p_dm_odm->mp_mode == false)
|
||||
p_rf_calibrate_info->txpowertrack_control = _TRUE;
|
||||
|
||||
MSG_8192C("p_dm_odm txpowertrack_control = %d\n", p_rf_calibrate_info->txpowertrack_control);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#if (MP_DRIVER == 1)
|
||||
p_rf_calibrate_info->txpowertrack_control = false;
|
||||
#else
|
||||
p_rf_calibrate_info->txpowertrack_control = true;
|
||||
#endif
|
||||
#else
|
||||
p_rf_calibrate_info->txpowertrack_control = true;
|
||||
#endif
|
||||
|
||||
p_rf_calibrate_info->thermal_value = p_hal_data->eeprom_thermal_meter;
|
||||
p_rf_calibrate_info->thermal_value_iqk = p_hal_data->eeprom_thermal_meter;
|
||||
p_rf_calibrate_info->thermal_value_lck = p_hal_data->eeprom_thermal_meter;
|
||||
|
||||
if (p_rf_calibrate_info->default_bb_swing_index_flag != true) {
|
||||
/*The index of "0 dB" in SwingTable.*/
|
||||
if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B ||
|
||||
p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8703B) {
|
||||
p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index;
|
||||
p_rf_calibrate_info->default_cck_index = 20;
|
||||
} else if (p_dm_odm->support_ic_type == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/
|
||||
p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/
|
||||
p_rf_calibrate_info->default_cck_index = 20; /*CCK:-6dB*/
|
||||
} else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/
|
||||
p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/
|
||||
p_rf_calibrate_info->default_cck_index = 28; /*CCK: -6dB*/
|
||||
} else {
|
||||
p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index;
|
||||
p_rf_calibrate_info->default_cck_index = 24;
|
||||
}
|
||||
p_rf_calibrate_info->default_bb_swing_index_flag = true;
|
||||
}
|
||||
|
||||
p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index;
|
||||
p_rf_calibrate_info->CCK_index = p_rf_calibrate_info->default_cck_index;
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) {
|
||||
p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->default_ofdm_index;
|
||||
p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index;
|
||||
p_rf_calibrate_info->delta_power_index[p] = 0;
|
||||
p_rf_calibrate_info->delta_power_index_last[p] = 0;
|
||||
p_rf_calibrate_info->power_index_offset[p] = 0;
|
||||
p_rf_calibrate_info->kfree_offset[p] = 0;
|
||||
}
|
||||
p_rf_calibrate_info->modify_tx_agc_value_ofdm = 0;
|
||||
p_rf_calibrate_info->modify_tx_agc_value_cck = 0;
|
||||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_txpowertracking_check(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
|
||||
#if 0
|
||||
/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
|
||||
/* at the same time. In the stage2/3, we need to prive universal interface and merge all */
|
||||
/* HW dynamic mechanism. */
|
||||
#endif
|
||||
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
switch (p_dm_odm->support_platform) {
|
||||
case ODM_WIN:
|
||||
odm_txpowertracking_check_mp(p_dm_odm);
|
||||
break;
|
||||
|
||||
case ODM_CE:
|
||||
odm_txpowertracking_check_ce(p_dm_odm);
|
||||
break;
|
||||
|
||||
case ODM_AP:
|
||||
odm_txpowertracking_check_ap(p_dm_odm);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
odm_txpowertracking_check_ce(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
#if ((RTL8188F_SUPPORT == 1))
|
||||
rtl8192c_odm_check_txpowertracking(adapter);
|
||||
#endif
|
||||
|
||||
#if (RTL8188E_SUPPORT == 1)
|
||||
|
||||
if (!(p_dm_odm->support_ability & ODM_RF_TX_PWR_TRACK))
|
||||
return;
|
||||
|
||||
if (!p_rf_calibrate_info->tm_trigger) {
|
||||
odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
|
||||
/*DBG_8192C("Trigger 92C Thermal Meter!!\n");*/
|
||||
|
||||
p_rf_calibrate_info->tm_trigger = 1;
|
||||
return;
|
||||
|
||||
} else {
|
||||
/*DBG_8192C("Schedule TxPowerTracking direct call!!\n");*/
|
||||
odm_txpowertracking_callback_thermal_meter_8188e(adapter);
|
||||
p_rf_calibrate_info->tm_trigger = 0;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
odm_txpowertracking_check_mp(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter;
|
||||
|
||||
if (*p_dm_odm->p_is_fcs_mode_enable)
|
||||
return;
|
||||
|
||||
if (odm_check_power_status(adapter) == false) {
|
||||
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===>odm_check_power_status() return false\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
if (IS_HARDWARE_TYPE_8821B(adapter)) /* TODO: Don't Do PowerTracking*/
|
||||
return;
|
||||
|
||||
odm_txpowertracking_thermal_meter_check(adapter);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
odm_txpowertracking_check_ap(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
return;
|
||||
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
|
||||
void
|
||||
odm_txpowertracking_direct_call(
|
||||
struct _ADAPTER *adapter
|
||||
)
|
||||
{
|
||||
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
|
||||
odm_txpowertracking_callback_thermal_meter(adapter);
|
||||
}
|
||||
|
||||
void
|
||||
odm_txpowertracking_thermal_meter_check(
|
||||
struct _ADAPTER *adapter
|
||||
)
|
||||
{
|
||||
#ifndef AP_BUILD_WORKAROUND
|
||||
static u8 tm_trigger = 0;
|
||||
|
||||
if (!(GET_HAL_DATA(adapter)->DM_OutSrc.support_ability & ODM_RF_TX_PWR_TRACK)) {
|
||||
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
|
||||
("===>odm_txpowertracking_thermal_meter_check(),p_mgnt_info->is_txpowertracking is false, return!!\n"));
|
||||
return;
|
||||
}
|
||||
|
||||
if (!tm_trigger) {
|
||||
if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8192E(adapter) ||
|
||||
IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8814A(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8703B(adapter)
|
||||
|| IS_HARDWARE_TYPE_8822B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8821C(adapter))
|
||||
PHY_SetRFReg(adapter, ODM_RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);
|
||||
else
|
||||
PHY_SetRFReg(adapter, ODM_RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
|
||||
|
||||
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Trigger Thermal Meter!!\n"));
|
||||
|
||||
tm_trigger = 1;
|
||||
return;
|
||||
} else {
|
||||
RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Schedule TxPowerTracking direct call!!\n"));
|
||||
odm_txpowertracking_direct_call(adapter);
|
||||
tm_trigger = 0;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
|
@ -66,15 +66,8 @@
|
|||
#define PHYDM_ABCD (BIT(0) | BIT(1) | BIT(2) | BIT(3))
|
||||
|
||||
/* number of entry */
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
|
||||
#define ASSOCIATE_ENTRY_NUM MACID_NUM_SW_LIMIT /* Max size of asoc_entry[].*/
|
||||
#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
|
||||
#elif(DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
#define ASSOCIATE_ENTRY_NUM NUM_STAT
|
||||
#define ODM_ASSOCIATE_ENTRY_NUM (ASSOCIATE_ENTRY_NUM+1)
|
||||
#else
|
||||
#define ODM_ASSOCIATE_ENTRY_NUM ((ASSOCIATE_ENTRY_NUM*3)+1)
|
||||
#endif
|
||||
#define ASSOCIATE_ENTRY_NUM MACID_NUM_SW_LIMIT /* Max size of asoc_entry[].*/
|
||||
#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
|
||||
|
||||
/* -----MGN rate--------------------------------- */
|
||||
|
||||
|
@ -278,27 +271,7 @@ enum ODM_MGN_RATE {
|
|||
#define ODM_RATEVHTSS4MCS8 0x52
|
||||
#define ODM_RATEVHTSS4MCS9 0x53
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1)
|
||||
#else
|
||||
#if (RTL8192E_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)
|
||||
#define ODM_NUM_RATE_IDX (ODM_RATEMCS15+1)
|
||||
#elif (RTL8723B_SUPPORT == 1) || (RTL8188E_SUPPORT == 1) || (RTL8188F_SUPPORT == 1)
|
||||
#define ODM_NUM_RATE_IDX (ODM_RATEMCS7+1)
|
||||
#elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1)
|
||||
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS1MCS9+1)
|
||||
#elif (RTL8812A_SUPPORT == 1)
|
||||
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS2MCS9+1)
|
||||
#elif (RTL8814A_SUPPORT == 1)
|
||||
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS3MCS9+1)
|
||||
#else
|
||||
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define CONFIG_SFW_SUPPORTED
|
||||
#endif
|
||||
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1)
|
||||
|
||||
/* 1 ============================================================
|
||||
* 1 enumeration
|
||||
|
@ -354,34 +327,8 @@ enum odm_ic_type_e {
|
|||
|
||||
#define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
|
||||
#ifdef RTK_AC_SUPPORT
|
||||
#define ODM_IC_11AC_SERIES_SUPPORT 1
|
||||
#else
|
||||
#define ODM_IC_11AC_SERIES_SUPPORT 0
|
||||
#endif
|
||||
|
||||
#define ODM_IC_11N_SERIES_SUPPORT 1
|
||||
#define ODM_CONFIG_BT_COEXIST 0
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
|
||||
#define ODM_IC_11AC_SERIES_SUPPORT 1
|
||||
#define ODM_IC_11N_SERIES_SUPPORT 1
|
||||
#define ODM_CONFIG_BT_COEXIST 1
|
||||
|
||||
#else
|
||||
|
||||
#if ((RTL8188E_SUPPORT == 1) || \
|
||||
(RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8195A_SUPPORT == 1) || (RTL8703B_SUPPORT == 1) || \
|
||||
(RTL8188F_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
|
||||
#define ODM_IC_11N_SERIES_SUPPORT 1
|
||||
#define ODM_IC_11N_SERIES_SUPPORT 1
|
||||
#define ODM_IC_11AC_SERIES_SUPPORT 0
|
||||
#else
|
||||
#define ODM_IC_11N_SERIES_SUPPORT 0
|
||||
#define ODM_IC_11AC_SERIES_SUPPORT 1
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
#define ODM_CONFIG_BT_COEXIST 1
|
||||
|
@ -389,9 +336,6 @@ enum odm_ic_type_e {
|
|||
#define ODM_CONFIG_BT_COEXIST 0
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if ((RTL8197F_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1))
|
||||
#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 1
|
||||
#else
|
||||
|
@ -479,7 +423,6 @@ enum odm_operation_mode_e {
|
|||
};
|
||||
|
||||
/* ODM_CMNINFO_WM_MODE */
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
|
||||
enum odm_wireless_mode_e {
|
||||
ODM_WM_UNKNOW = 0x0,
|
||||
ODM_WM_B = BIT(0),
|
||||
|
@ -490,37 +433,15 @@ enum odm_wireless_mode_e {
|
|||
ODM_WM_AUTO = BIT(5),
|
||||
ODM_WM_AC = BIT(6),
|
||||
};
|
||||
#else
|
||||
enum odm_wireless_mode_e {
|
||||
ODM_WM_UNKNOWN = 0x00,/*0x0*/
|
||||
ODM_WM_A = BIT(0), /* 0x1*/
|
||||
ODM_WM_B = BIT(1), /* 0x2*/
|
||||
ODM_WM_G = BIT(2),/* 0x4*/
|
||||
ODM_WM_AUTO = BIT(3),/* 0x8*/
|
||||
ODM_WM_N24G = BIT(4),/* 0x10*/
|
||||
ODM_WM_N5G = BIT(5),/* 0x20*/
|
||||
ODM_WM_AC_5G = BIT(6),/* 0x40*/
|
||||
ODM_WM_AC_24G = BIT(7),/* 0x80*/
|
||||
ODM_WM_AC_ONLY = BIT(8),/* 0x100*/
|
||||
ODM_WM_MAX = BIT(11)/* 0x800*/
|
||||
|
||||
};
|
||||
#endif
|
||||
|
||||
/* ODM_CMNINFO_BAND */
|
||||
enum odm_band_type_e {
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
ODM_BAND_2_4G = BIT(0),
|
||||
ODM_BAND_5G = BIT(1),
|
||||
#else
|
||||
ODM_BAND_2_4G = 0,
|
||||
ODM_BAND_5G,
|
||||
ODM_BAND_ON_BOTH,
|
||||
ODM_BANDMAX
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* ODM_CMNINFO_SEC_CHNL_OFFSET */
|
||||
enum phydm_sec_chnl_offset_e {
|
||||
|
||||
|
|
|
@ -63,15 +63,7 @@
|
|||
#define RA_MASK_VHT1SS 0x3ff000
|
||||
#define RA_MASK_VHT2SS 0xffc00000
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#define RA_FIRST_MACID 1
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define RA_FIRST_MACID 0
|
||||
#define WIN_DEFAULT_PORT_MACID 0
|
||||
#define WIN_BT_PORT_MACID 2
|
||||
#else /*if (DM_ODM_SUPPORT_TYPE == ODM_CE)*/
|
||||
#define RA_FIRST_MACID 0
|
||||
#endif
|
||||
|
||||
#define ap_init_rate_adaptive_state odm_rate_adaptive_state_ap_init
|
||||
|
||||
|
@ -205,25 +197,12 @@ struct _odm_ra_info_ {
|
|||
u8 ra_stage; /* StageRA, decide how many times RA will be done between PT */
|
||||
u8 pt_smooth_factor;
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
|
||||
u8 rate_down_counter;
|
||||
u8 rate_up_counter;
|
||||
u8 rate_direction;
|
||||
u8 bounding_type;
|
||||
u8 bounding_counter;
|
||||
u8 bounding_learning_time;
|
||||
u8 rate_down_start_time;
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
struct _rate_adaptive_table_ {
|
||||
u8 firstconnect;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
bool PT_collision_pre;
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_RA_DBG_CMD))
|
||||
bool is_ra_dbg_init;
|
||||
|
||||
|
@ -272,20 +251,10 @@ struct _ODM_RATE_ADAPTIVE {
|
|||
u8 low_rssi_thresh; /* if RSSI <= low_rssi_thresh => ratr_state is DM_RATR_STA_LOW */
|
||||
u8 ratr_state; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
u8 ldpc_thres; /* if RSSI > ldpc_thres => switch from LPDC to BCC */
|
||||
bool is_lower_rts_rate;
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
|
||||
u8 rts_thres;
|
||||
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
|
||||
bool is_use_ldpc;
|
||||
#else
|
||||
u8 ultra_low_rssi_thresh;
|
||||
u32 last_ratr; /* RATR Register Content */
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
void
|
||||
|
@ -480,8 +449,6 @@ odm_ra_post_action_on_assoc(
|
|||
void *p_dm_odm
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
|
||||
u8
|
||||
odm_find_rts_rate(
|
||||
void *p_dm_void,
|
||||
|
@ -501,49 +468,12 @@ phydm_update_pwr_track(
|
|||
u8 rate
|
||||
);
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
|
||||
s32
|
||||
phydm_find_minimum_rssi(
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
struct _ADAPTER *p_adapter,
|
||||
OUT bool *p_is_link_temp
|
||||
);
|
||||
|
||||
void
|
||||
odm_update_init_rate_work_item_callback(
|
||||
void *p_context
|
||||
);
|
||||
|
||||
void
|
||||
odm_rssi_dump_to_register(
|
||||
void *p_dm_void
|
||||
);
|
||||
|
||||
void
|
||||
odm_refresh_ldpc_rts_mp(
|
||||
struct _ADAPTER *p_adapter,
|
||||
struct PHY_DM_STRUCT *p_dm_odm,
|
||||
u8 m_mac_id,
|
||||
u8 iot_peer,
|
||||
s32 undecorated_smoothed_pwdb
|
||||
);
|
||||
|
||||
#if 0
|
||||
void
|
||||
odm_dynamic_arfb_select(
|
||||
void *p_dm_void,
|
||||
u8 rate,
|
||||
bool collision_state
|
||||
);
|
||||
#endif
|
||||
|
||||
void
|
||||
odm_rate_adaptive_state_ap_init(
|
||||
void *PADAPTER_VOID,
|
||||
struct sta_info *p_entry
|
||||
);
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
|
||||
static void
|
||||
find_minimum_rssi(
|
||||
|
@ -568,18 +498,5 @@ odm_get_rate_bitmap(
|
|||
);
|
||||
|
||||
void phydm_ra_rssi_rpt_wk(void *p_context);
|
||||
#endif/*#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)*/
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
/*
|
||||
void
|
||||
phydm_gen_ramask_h2c_AP(
|
||||
void *p_dm_void,
|
||||
struct rtl8192cd_priv *priv,
|
||||
struct sta_info *p_entry,
|
||||
u8 rssi_level
|
||||
);
|
||||
*/
|
||||
#endif/*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/
|
||||
|
||||
#endif /*#ifndef __ODMRAINFO_H__*/
|
||||
|
|
|
@ -126,89 +126,7 @@
|
|||
/*
|
||||
* Bitmap Definition
|
||||
* */
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||||
/* TX AGC */
|
||||
#define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR 0xc20
|
||||
#define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR 0xc24
|
||||
#define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR 0xc28
|
||||
#define REG_TX_AGC_A_MCS3_MCS0_JAGUAR 0xc2c
|
||||
#define REG_TX_AGC_A_MCS7_MCS4_JAGUAR 0xc30
|
||||
#define REG_TX_AGC_A_MCS11_MCS8_JAGUAR 0xc34
|
||||
#define REG_TX_AGC_A_MCS15_MCS12_JAGUAR 0xc38
|
||||
#define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0xc3c
|
||||
#define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0xc40
|
||||
#define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0xc44
|
||||
#define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0xc48
|
||||
#define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0xc4c
|
||||
#if defined(CONFIG_WLAN_HAL_8814AE)
|
||||
#define REG_TX_AGC_A_MCS19_MCS16_JAGUAR 0xcd8
|
||||
#define REG_TX_AGC_A_MCS23_MCS20_JAGUAR 0xcdc
|
||||
#define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0xce0
|
||||
#define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0xce4
|
||||
#define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0xce8
|
||||
#endif
|
||||
#define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR 0xe20
|
||||
#define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR 0xe24
|
||||
#define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR 0xe28
|
||||
#define REG_TX_AGC_B_MCS3_MCS0_JAGUAR 0xe2c
|
||||
#define REG_TX_AGC_B_MCS7_MCS4_JAGUAR 0xe30
|
||||
#define REG_TX_AGC_B_MCS11_MCS8_JAGUAR 0xe34
|
||||
#define REG_TX_AGC_B_MCS15_MCS12_JAGUAR 0xe38
|
||||
#define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0xe3c
|
||||
#define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0xe40
|
||||
#define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0xe44
|
||||
#define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0xe48
|
||||
#define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0xe4c
|
||||
#if defined(CONFIG_WLAN_HAL_8814AE)
|
||||
#define REG_TX_AGC_B_MCS19_MCS16_JAGUAR 0xed8
|
||||
#define REG_TX_AGC_B_MCS23_MCS20_JAGUAR 0xedc
|
||||
#define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0xee0
|
||||
#define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0xee4
|
||||
#define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0xee8
|
||||
#define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR 0x1820
|
||||
#define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR 0x1824
|
||||
#define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR 0x1828
|
||||
#define REG_TX_AGC_C_MCS3_MCS0_JAGUAR 0x182c
|
||||
#define REG_TX_AGC_C_MCS7_MCS4_JAGUAR 0x1830
|
||||
#define REG_TX_AGC_C_MCS11_MCS8_JAGUAR 0x1834
|
||||
#define REG_TX_AGC_C_MCS15_MCS12_JAGUAR 0x1838
|
||||
#define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0x183c
|
||||
#define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0x1840
|
||||
#define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0x1844
|
||||
#define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0x1848
|
||||
#define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0x184c
|
||||
#define REG_TX_AGC_C_MCS19_MCS16_JAGUAR 0x18d8
|
||||
#define REG_TX_AGC_C_MCS23_MCS20_JAGUAR 0x18dc
|
||||
#define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0x18e0
|
||||
#define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0x18e4
|
||||
#define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0x18e8
|
||||
#define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR 0x1a20
|
||||
#define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR 0x1a24
|
||||
#define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR 0x1a28
|
||||
#define REG_TX_AGC_D_MCS3_MCS0_JAGUAR 0x1a2c
|
||||
#define REG_TX_AGC_D_MCS7_MCS4_JAGUAR 0x1a30
|
||||
#define REG_TX_AGC_D_MCS11_MCS8_JAGUAR 0x1a34
|
||||
#define REG_TX_AGC_D_MCS15_MCS12_JAGUAR 0x1a38
|
||||
#define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0x1a3c
|
||||
#define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0x1a40
|
||||
#define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0x1a44
|
||||
#define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0x1a48
|
||||
#define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0x1a4c
|
||||
#define REG_TX_AGC_D_MCS19_MCS16_JAGUAR 0x1ad8
|
||||
#define REG_TX_AGC_D_MCS23_MCS20_JAGUAR 0x1adc
|
||||
#define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0x1ae0
|
||||
#define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0x1ae4
|
||||
#define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0x1ae8
|
||||
#endif
|
||||
|
||||
#define is_tx_agc_byte0_jaguar 0xff
|
||||
#define is_tx_agc_byte1_jaguar 0xff00
|
||||
#define is_tx_agc_byte2_jaguar 0xff0000
|
||||
#define is_tx_agc_byte3_jaguar 0xff000000
|
||||
#endif
|
||||
|
||||
#define BIT_FA_RESET BIT(0)
|
||||
|
||||
|
||||
#define BIT_FA_RESET BIT(0)
|
||||
|
||||
#endif
|
||||
|
|
|
@ -18,55 +18,41 @@
|
|||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* ************************************************************
|
||||
* include files
|
||||
* ************************************************************ */
|
||||
|
||||
#include "mp_precomp.h"
|
||||
|
||||
#include "phydm_precomp.h"
|
||||
|
||||
#if (RTL8188E_SUPPORT == 1)
|
||||
|
||||
void
|
||||
odm_dig_lower_bound_88e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
)
|
||||
void odm_dig_lower_bound_88e(struct PHY_DM_STRUCT *p_dm_odm)
|
||||
{
|
||||
struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table;
|
||||
struct _dynamic_initial_gain_threshold_ *p_dm_dig_table =
|
||||
&p_dm_odm->dm_dig_table;
|
||||
|
||||
if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) {
|
||||
p_dm_dig_table->rx_gain_range_min = (u8) p_dm_dig_table->ant_div_rssi_max;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_dig_lower_bound_88e(): p_dm_dig_table->ant_div_rssi_max=%d\n", p_dm_dig_table->ant_div_rssi_max));
|
||||
p_dm_dig_table->rx_gain_range_min =
|
||||
(u8)p_dm_dig_table->ant_div_rssi_max;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
|
||||
("odm_dig_lower_bound_88e(): p_dm_dig_table->ant_div_rssi_max=%d\n",
|
||||
p_dm_dig_table->ant_div_rssi_max));
|
||||
}
|
||||
/* If only one Entry connected */
|
||||
}
|
||||
|
||||
/*=============================================================
|
||||
* AntDiv Before Link
|
||||
===============================================================*/
|
||||
void
|
||||
odm_sw_ant_div_reset_before_link(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
)
|
||||
void odm_sw_ant_div_reset_before_link(struct PHY_DM_STRUCT *p_dm_odm)
|
||||
{
|
||||
|
||||
struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table;
|
||||
struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table;
|
||||
|
||||
p_dm_swat_table->swas_no_link_state = 0;
|
||||
|
||||
}
|
||||
|
||||
|
||||
/* 3============================================================
|
||||
* 3 Dynamic Primary CCA
|
||||
* 3============================================================ */
|
||||
|
||||
void
|
||||
odm_primary_cca_init(
|
||||
struct PHY_DM_STRUCT *p_dm_odm)
|
||||
void odm_primary_cca_init(struct PHY_DM_STRUCT *p_dm_odm)
|
||||
{
|
||||
struct _dynamic_primary_cca *primary_cca = &(p_dm_odm->dm_pri_cca);
|
||||
struct _dynamic_primary_cca *primary_cca = &(p_dm_odm->dm_pri_cca);
|
||||
primary_cca->dup_rts_flag = 0;
|
||||
primary_cca->intf_flag = 0;
|
||||
primary_cca->intf_type = 0;
|
||||
|
@ -74,315 +60,13 @@ odm_primary_cca_init(
|
|||
primary_cca->pri_cca_flag = 0;
|
||||
}
|
||||
|
||||
bool
|
||||
odm_dynamic_primary_cca_dup_rts(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
)
|
||||
bool odm_dynamic_primary_cca_dup_rts(struct PHY_DM_STRUCT *p_dm_odm)
|
||||
{
|
||||
struct _dynamic_primary_cca *primary_cca = &(p_dm_odm->dm_pri_cca);
|
||||
struct _dynamic_primary_cca *primary_cca = &(p_dm_odm->dm_pri_cca);
|
||||
|
||||
return primary_cca->dup_rts_flag;
|
||||
}
|
||||
|
||||
void
|
||||
odm_dynamic_primary_cca(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
)
|
||||
void odm_dynamic_primary_cca(struct PHY_DM_STRUCT *p_dm_odm)
|
||||
{
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_CE)
|
||||
|
||||
struct _ADAPTER *adapter = p_dm_odm->adapter; /* for NIC */
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
|
||||
struct sta_info *p_entry;
|
||||
#endif
|
||||
|
||||
struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT);
|
||||
struct _dynamic_primary_cca *primary_cca = &(p_dm_odm->dm_pri_cca);
|
||||
|
||||
bool is_40mhz;
|
||||
bool client_40mhz = false, client_tmp = false; /* connected client BW */
|
||||
bool is_connected = false; /* connected or not */
|
||||
static u8 client_40mhz_pre = 0;
|
||||
static u64 last_tx_ok_cnt = 0;
|
||||
static u64 last_rx_ok_cnt = 0;
|
||||
static u32 counter = 0;
|
||||
static u8 delay = 1;
|
||||
u64 cur_tx_ok_cnt;
|
||||
u64 cur_rx_ok_cnt;
|
||||
u8 sec_ch_offset;
|
||||
u8 i;
|
||||
|
||||
if (!(p_dm_odm->support_ability & ODM_BB_PRIMARY_CCA))
|
||||
return;
|
||||
|
||||
if (p_dm_odm->support_ic_type != ODM_RTL8188E)
|
||||
return;
|
||||
|
||||
is_40mhz = *(p_dm_odm->p_band_width);
|
||||
sec_ch_offset = *(p_dm_odm->p_sec_ch_offset);
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Second CH Offset = %d\n", sec_ch_offset));
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
if (is_40mhz == 1)
|
||||
sec_ch_offset = sec_ch_offset % 2 + 1; /* NIC's definition is reverse to AP 1:secondary below, 2: secondary above */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Second CH Offset = %d\n", sec_ch_offset));
|
||||
/* 3 Check Current WLAN Traffic */
|
||||
cur_tx_ok_cnt = adapter->TxStats.NumTxBytesUnicast - last_tx_ok_cnt;
|
||||
cur_rx_ok_cnt = adapter->RxStats.NumRxBytesUnicast - last_rx_ok_cnt;
|
||||
last_tx_ok_cnt = adapter->TxStats.NumTxBytesUnicast;
|
||||
last_rx_ok_cnt = adapter->RxStats.NumRxBytesUnicast;
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
/* 3 Check Current WLAN Traffic */
|
||||
cur_tx_ok_cnt = *(p_dm_odm->p_num_tx_bytes_unicast) - last_tx_ok_cnt;
|
||||
cur_rx_ok_cnt = *(p_dm_odm->p_num_rx_bytes_unicast) - last_rx_ok_cnt;
|
||||
last_tx_ok_cnt = *(p_dm_odm->p_num_tx_bytes_unicast);
|
||||
last_rx_ok_cnt = *(p_dm_odm->p_num_rx_bytes_unicast);
|
||||
#endif
|
||||
|
||||
/* ==================Debug Message==================== */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("TP = %llu\n", cur_tx_ok_cnt + cur_rx_ok_cnt));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("is_40mhz = %d\n", is_40mhz));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("BW_LSC = %d\n", false_alm_cnt->cnt_bw_lsc));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("BW_USC = %d\n", false_alm_cnt->cnt_bw_usc));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCA OFDM = %d\n", false_alm_cnt->cnt_ofdm_cca));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCA CCK = %d\n", false_alm_cnt->cnt_cck_cca));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("OFDM FA = %d\n", false_alm_cnt->cnt_ofdm_fail));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCK FA = %d\n", false_alm_cnt->cnt_cck_fail));
|
||||
/* ================================================ */
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
if (ACTING_AS_AP(adapter)) /* primary cca process only do at AP mode */
|
||||
#endif
|
||||
{
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("ACTING as AP mode=%d\n", ACTING_AS_AP(adapter)));
|
||||
/* 3 To get entry's connection and BW infomation status. */
|
||||
for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) {
|
||||
if (IsAPModeExist(adapter) && GetFirstExtAdapter(adapter) != NULL)
|
||||
p_entry = AsocEntry_EnumStation(GetFirstExtAdapter(adapter), i);
|
||||
else
|
||||
p_entry = AsocEntry_EnumStation(GetDefaultAdapter(adapter), i);
|
||||
if (p_entry != NULL) {
|
||||
client_tmp = p_entry->BandWidth; /* client BW */
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Client_BW=%d\n", client_tmp));
|
||||
if (client_tmp > client_40mhz)
|
||||
client_40mhz = client_tmp; /* 40M/20M coexist => 40M priority is High */
|
||||
|
||||
if (p_entry->bAssociated) {
|
||||
is_connected = true; /* client is connected or not */
|
||||
break;
|
||||
}
|
||||
} else
|
||||
break;
|
||||
}
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
/* 3 To get entry's connection and BW infomation status. */
|
||||
|
||||
struct sta_info *pstat;
|
||||
|
||||
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
|
||||
pstat = p_dm_odm->p_odm_sta_info[i];
|
||||
if (IS_STA_VALID(pstat)) {
|
||||
client_tmp = pstat->tx_bw;
|
||||
if (client_tmp > client_40mhz)
|
||||
client_40mhz = client_tmp; /* 40M/20M coexist => 40M priority is High */
|
||||
|
||||
is_connected = true;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("is_connected=%d\n", is_connected));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Is Client 40MHz=%d\n", client_40mhz));
|
||||
/* 1 Monitor whether the interference exists or not */
|
||||
if (primary_cca->monitor_flag == 1) {
|
||||
if (sec_ch_offset == 1) { /* secondary channel is below the primary channel */
|
||||
if ((false_alm_cnt->cnt_ofdm_cca > 500) && (false_alm_cnt->cnt_bw_lsc > false_alm_cnt->cnt_bw_usc + 500)) {
|
||||
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1) {
|
||||
primary_cca->intf_type = 1;
|
||||
primary_cca->pri_cca_flag = 1;
|
||||
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT7, 2); /* USC MF */
|
||||
if (primary_cca->dup_rts_flag == 1)
|
||||
primary_cca->dup_rts_flag = 0;
|
||||
} else {
|
||||
primary_cca->intf_type = 2;
|
||||
if (primary_cca->dup_rts_flag == 0)
|
||||
primary_cca->dup_rts_flag = 1;
|
||||
}
|
||||
|
||||
} else { /* interferecne disappear */
|
||||
primary_cca->dup_rts_flag = 0;
|
||||
primary_cca->intf_flag = 0;
|
||||
primary_cca->intf_type = 0;
|
||||
}
|
||||
} else if (sec_ch_offset == 2) { /* secondary channel is above the primary channel */
|
||||
if ((false_alm_cnt->cnt_ofdm_cca > 500) && (false_alm_cnt->cnt_bw_usc > false_alm_cnt->cnt_bw_lsc + 500)) {
|
||||
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1) {
|
||||
primary_cca->intf_type = 1;
|
||||
primary_cca->pri_cca_flag = 1;
|
||||
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT7, 1); /* LSC MF */
|
||||
if (primary_cca->dup_rts_flag == 1)
|
||||
primary_cca->dup_rts_flag = 0;
|
||||
} else {
|
||||
primary_cca->intf_type = 2;
|
||||
if (primary_cca->dup_rts_flag == 0)
|
||||
primary_cca->dup_rts_flag = 1;
|
||||
}
|
||||
|
||||
} else { /* interferecne disappear */
|
||||
primary_cca->dup_rts_flag = 0;
|
||||
primary_cca->intf_flag = 0;
|
||||
primary_cca->intf_type = 0;
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
primary_cca->monitor_flag = 0;
|
||||
}
|
||||
|
||||
/* 1 Dynamic Primary CCA Main Function */
|
||||
if (primary_cca->monitor_flag == 0) {
|
||||
if (is_40mhz) { /* if RFBW==40M mode which require to process primary cca */
|
||||
/* 2 STA is NOT Connected */
|
||||
if (!is_connected) {
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("STA NOT Connected!!!!\n"));
|
||||
|
||||
if (primary_cca->pri_cca_flag == 1) { /* reset primary cca when STA is disconnected */
|
||||
primary_cca->pri_cca_flag = 0;
|
||||
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT(7), 0);
|
||||
}
|
||||
if (primary_cca->dup_rts_flag == 1) /* reset Duplicate RTS when STA is disconnected */
|
||||
primary_cca->dup_rts_flag = 0;
|
||||
|
||||
if (sec_ch_offset == 1) { /* secondary channel is below the primary channel */
|
||||
if ((false_alm_cnt->cnt_ofdm_cca > 800) && (false_alm_cnt->cnt_bw_lsc * 5 > false_alm_cnt->cnt_bw_usc * 9)) {
|
||||
primary_cca->intf_flag = 1; /* secondary channel interference is detected!!! */
|
||||
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
|
||||
primary_cca->intf_type = 1; /* interference is shift */
|
||||
else
|
||||
primary_cca->intf_type = 2; /* interference is in-band */
|
||||
} else {
|
||||
primary_cca->intf_flag = 0;
|
||||
primary_cca->intf_type = 0;
|
||||
}
|
||||
} else if (sec_ch_offset == 2) { /* secondary channel is above the primary channel */
|
||||
if ((false_alm_cnt->cnt_ofdm_cca > 800) && (false_alm_cnt->cnt_bw_usc * 5 > false_alm_cnt->cnt_bw_lsc * 9)) {
|
||||
primary_cca->intf_flag = 1; /* secondary channel interference is detected!!! */
|
||||
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
|
||||
primary_cca->intf_type = 1; /* interference is shift */
|
||||
else
|
||||
primary_cca->intf_type = 2; /* interference is in-band */
|
||||
} else {
|
||||
primary_cca->intf_flag = 0;
|
||||
primary_cca->intf_type = 0;
|
||||
}
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("primary_cca=%d\n", primary_cca->pri_cca_flag));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Intf_Type=%d\n", primary_cca->intf_type));
|
||||
}
|
||||
/* 2 STA is Connected */
|
||||
else {
|
||||
if (client_40mhz == 0) /* 3 */ { /* client BW = 20MHz */
|
||||
if (primary_cca->pri_cca_flag == 0) {
|
||||
primary_cca->pri_cca_flag = 1;
|
||||
if (sec_ch_offset == 1)
|
||||
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT(7), 2);
|
||||
else if (sec_ch_offset == 2)
|
||||
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT(7), 1);
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("STA Connected 20M!!! primary_cca=%d\n", primary_cca->pri_cca_flag));
|
||||
} else /* 3 */ { /* client BW = 40MHz */
|
||||
if (primary_cca->intf_flag == 1) { /* interference is detected!! */
|
||||
if (primary_cca->intf_type == 1) {
|
||||
if (primary_cca->pri_cca_flag != 1) {
|
||||
primary_cca->pri_cca_flag = 1;
|
||||
if (sec_ch_offset == 1)
|
||||
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT(7), 2);
|
||||
else if (sec_ch_offset == 2)
|
||||
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT(7), 1);
|
||||
}
|
||||
} else if (primary_cca->intf_type == 2) {
|
||||
if (primary_cca->dup_rts_flag != 1)
|
||||
primary_cca->dup_rts_flag = 1;
|
||||
}
|
||||
} else { /* if intf_flag==0 */
|
||||
if ((cur_tx_ok_cnt + cur_rx_ok_cnt) < 10000) { /* idle mode or TP traffic is very low */
|
||||
if (sec_ch_offset == 1) {
|
||||
if ((false_alm_cnt->cnt_ofdm_cca > 800) && (false_alm_cnt->cnt_bw_lsc * 5 > false_alm_cnt->cnt_bw_usc * 9)) {
|
||||
primary_cca->intf_flag = 1;
|
||||
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
|
||||
primary_cca->intf_type = 1; /* interference is shift */
|
||||
else
|
||||
primary_cca->intf_type = 2; /* interference is in-band */
|
||||
}
|
||||
} else if (sec_ch_offset == 2) {
|
||||
if ((false_alm_cnt->cnt_ofdm_cca > 800) && (false_alm_cnt->cnt_bw_usc * 5 > false_alm_cnt->cnt_bw_lsc * 9)) {
|
||||
primary_cca->intf_flag = 1;
|
||||
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
|
||||
primary_cca->intf_type = 1; /* interference is shift */
|
||||
else
|
||||
primary_cca->intf_type = 2; /* interference is in-band */
|
||||
}
|
||||
|
||||
}
|
||||
} else { /* TP Traffic is High */
|
||||
if (sec_ch_offset == 1) {
|
||||
if (false_alm_cnt->cnt_bw_lsc > (false_alm_cnt->cnt_bw_usc + 500)) {
|
||||
if (delay == 0) { /* add delay to avoid interference occurring abruptly, jump one time */
|
||||
primary_cca->intf_flag = 1;
|
||||
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
|
||||
primary_cca->intf_type = 1; /* interference is shift */
|
||||
else
|
||||
primary_cca->intf_type = 2; /* interference is in-band */
|
||||
delay = 1;
|
||||
} else
|
||||
delay = 0;
|
||||
}
|
||||
} else if (sec_ch_offset == 2) {
|
||||
if (false_alm_cnt->cnt_bw_usc > (false_alm_cnt->cnt_bw_lsc + 500)) {
|
||||
if (delay == 0) { /* add delay to avoid interference occurring abruptly */
|
||||
primary_cca->intf_flag = 1;
|
||||
if (false_alm_cnt->cnt_ofdm_fail > false_alm_cnt->cnt_ofdm_cca >> 1)
|
||||
primary_cca->intf_type = 1; /* interference is shift */
|
||||
else
|
||||
primary_cca->intf_type = 2; /* interference is in-band */
|
||||
delay = 1;
|
||||
} else
|
||||
delay = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Primary CCA=%d\n", primary_cca->pri_cca_flag));
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Duplicate RTS=%d\n", primary_cca->dup_rts_flag));
|
||||
}
|
||||
|
||||
} /* end of connected */
|
||||
}
|
||||
}
|
||||
/* 1 Dynamic Primary CCA Monitor counter */
|
||||
if ((primary_cca->pri_cca_flag == 1) || (primary_cca->dup_rts_flag == 1)) {
|
||||
if (client_40mhz == 0) { /* client=20M no need to monitor primary cca flag */
|
||||
client_40mhz_pre = client_40mhz;
|
||||
return;
|
||||
}
|
||||
counter++;
|
||||
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("counter=%d\n", counter));
|
||||
if ((counter == 30) || ((client_40mhz - client_40mhz_pre) == 1)) { /* Every 60 sec to monitor one time */
|
||||
primary_cca->monitor_flag = 1; /* monitor flag is triggered!!!!! */
|
||||
if (primary_cca->pri_cca_flag == 1) {
|
||||
primary_cca->pri_cca_flag = 0;
|
||||
odm_set_bb_reg(p_dm_odm, 0xc6c, BIT(8) | BIT(7), 0);
|
||||
}
|
||||
counter = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
client_40mhz_pre = client_40mhz;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* #if (RTL8188E_SUPPORT == 1) */
|
||||
|
|
|
@ -34,11 +34,6 @@ odm_dig_lower_bound_88e(
|
|||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
|
||||
|
||||
#define sw_ant_div_reset_before_link odm_sw_ant_div_reset_before_link
|
||||
|
||||
void odm_sw_ant_div_reset_before_link(struct PHY_DM_STRUCT *p_dm_odm);
|
||||
|
@ -49,12 +44,6 @@ odm_set_tx_ant_by_tx_info_88e(
|
|||
u8 *p_desc,
|
||||
u8 mac_id
|
||||
);
|
||||
#else/* (DM_ODM_SUPPORT_TYPE == ODM_AP) */
|
||||
void
|
||||
odm_set_tx_ant_by_tx_info_88e(
|
||||
struct PHY_DM_STRUCT *p_dm_odm
|
||||
);
|
||||
#endif
|
||||
|
||||
void
|
||||
odm_primary_cca_init(
|
||||
|
|
|
@ -32,17 +32,11 @@
|
|||
#define ODM_ENDIAN_BIG 0
|
||||
#define ODM_ENDIAN_LITTLE 1
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define GET_PDM_ODM(__padapter) ((struct PHY_DM_STRUCT*)(&((GET_HAL_DATA(__padapter))->DM_OutSrc)))
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#define GET_PDM_ODM(__padapter) ((struct PHY_DM_STRUCT*)(&((GET_HAL_DATA(__padapter))->odmpriv)))
|
||||
#endif
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
|
||||
#define RT_PCI_INTERFACE 1
|
||||
#define RT_USB_INTERFACE 2
|
||||
#define RT_SDIO_INTERFACE 3
|
||||
#endif
|
||||
|
||||
enum hal_status {
|
||||
HAL_STATUS_SUCCESS,
|
||||
|
@ -55,10 +49,6 @@ enum hal_status {
|
|||
RT_STATUS_OS_API_FAILED,*/
|
||||
};
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
#define MP_DRIVER 0
|
||||
#endif
|
||||
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
|
||||
|
||||
#define VISTA_USB_RX_REVISE 0
|
||||
|
||||
|
@ -112,73 +102,6 @@ enum rt_spinlock_type {
|
|||
RT_LAST_SPINLOCK,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define sta_info _RT_WLAN_STA
|
||||
#define __func__ __func__
|
||||
#define PHYDM_TESTCHIP_SUPPORT TESTCHIP_SUPPORT
|
||||
#define MASKH3BYTES 0xffffff00
|
||||
#define SUCCESS 0
|
||||
#define FAIL (-1)
|
||||
|
||||
#define u8 u1Byte
|
||||
#define s8 s1Byte
|
||||
|
||||
#define u16 u2Byte
|
||||
#define s16 s2Byte
|
||||
|
||||
#define u32 u4Byte
|
||||
#define s32 s4Byte
|
||||
|
||||
#define u64 u8Byte
|
||||
#define s64 s8Byte
|
||||
|
||||
#define bool BOOLEAN
|
||||
|
||||
#define timer_list _RT_TIMER
|
||||
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
|
||||
|
||||
/* To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07. */
|
||||
#define ADSL_AP_BUILD_WORKAROUND
|
||||
#define AP_BUILD_WORKAROUND
|
||||
|
||||
#ifdef AP_BUILD_WORKAROUND
|
||||
#include "../typedef.h"
|
||||
#else
|
||||
typedef void void, *void *;
|
||||
typedef unsigned char bool, *bool *;
|
||||
typedef unsigned char u8, *u8 *;
|
||||
typedef unsigned short u16, *u16 *;
|
||||
typedef unsigned int u32, *u32 *;
|
||||
typedef unsigned long long u64, *u64 *;
|
||||
#if 1
|
||||
/* In ARM platform, system would use the type -- "char" as "unsigned char"
|
||||
* And we only use s8/s8* as INT8 now, so changes the type of s8.*/
|
||||
typedef signed char s8, *s8 *;
|
||||
#else
|
||||
typedef char s8, *s8 *;
|
||||
#endif
|
||||
typedef short s16, *s16 *;
|
||||
typedef long s32, *s32 *;
|
||||
typedef long long s64, *s64 *;
|
||||
#endif
|
||||
|
||||
#define _TRUE 1
|
||||
#define _FALSE 0
|
||||
|
||||
#if (defined(TESTCHIP_SUPPORT))
|
||||
#define PHYDM_TESTCHIP_SUPPORT 1
|
||||
#else
|
||||
#define PHYDM_TESTCHIP_SUPPORT 0
|
||||
#endif
|
||||
|
||||
#define sta_info stat_info
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#include <drv_types.h>
|
||||
#define DEV_BUS_TYPE RT_USB_INTERFACE
|
||||
|
||||
|
@ -207,7 +130,6 @@ enum rt_spinlock_type {
|
|||
#else
|
||||
#define PHYDM_TESTCHIP_SUPPORT 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define READ_NEXT_PAIR(v1, v2, i) do { if (i+2 >= array_len) break; i += 2; v1 = array[i]; v2 = array[i+1]; } while (0)
|
||||
#define COND_ELSE 2
|
||||
|
|
|
@ -1,538 +0,0 @@
|
|||
/* ************************************************************
|
||||
* Description:
|
||||
*
|
||||
* This file is for TXBF mechanism
|
||||
*
|
||||
* ************************************************************ */
|
||||
#include "mp_precomp.h"
|
||||
#include "../phydm_precomp.h"
|
||||
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
/*Beamforming halcomtxbf API create by YuChen 2015/05*/
|
||||
|
||||
void
|
||||
hal_com_txbf_beamform_init(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
bool is_iqgen_setting_ok = false;
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8814A) {
|
||||
is_iqgen_setting_ok = phydm_beamforming_set_iqgen_8814A(p_dm_odm);
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] is_iqgen_setting_ok = %d\n", __func__, is_iqgen_setting_ok));
|
||||
}
|
||||
}
|
||||
|
||||
/*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/
|
||||
void
|
||||
hal_com_txbf_config_gtab(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8822B)
|
||||
hal_txbf_8822b_config_gtab(p_dm_odm);
|
||||
}
|
||||
|
||||
void
|
||||
phydm_beamform_set_sounding_enter(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_enter_work_item)) == false)
|
||||
odm_schedule_work_item(&(p_txbf_info->txbf_enter_work_item));
|
||||
#else
|
||||
hal_com_txbf_enter_work_item_callback(p_dm_odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
phydm_beamform_set_sounding_leave(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_leave_work_item)) == false)
|
||||
odm_schedule_work_item(&(p_txbf_info->txbf_leave_work_item));
|
||||
#else
|
||||
hal_com_txbf_leave_work_item_callback(p_dm_odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
phydm_beamform_set_sounding_rate(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_rate_work_item)) == false)
|
||||
odm_schedule_work_item(&(p_txbf_info->txbf_rate_work_item));
|
||||
#else
|
||||
hal_com_txbf_rate_work_item_callback(p_dm_odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
phydm_beamform_set_sounding_status(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_status_work_item)) == false)
|
||||
odm_schedule_work_item(&(p_txbf_info->txbf_status_work_item));
|
||||
#else
|
||||
hal_com_txbf_status_work_item_callback(p_dm_odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
phydm_beamform_set_sounding_fw_ndpa(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
if (*p_dm_odm->p_is_fw_dw_rsvd_page_in_progress)
|
||||
odm_set_timer(p_dm_odm, &(p_txbf_info->txbf_fw_ndpa_timer), 5);
|
||||
else
|
||||
odm_schedule_work_item(&(p_txbf_info->txbf_fw_ndpa_work_item));
|
||||
#else
|
||||
hal_com_txbf_fw_ndpa_work_item_callback(p_dm_odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
phydm_beamform_set_sounding_clk(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_clk_work_item)) == false)
|
||||
odm_schedule_work_item(&(p_txbf_info->txbf_clk_work_item));
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
struct _ADAPTER *padapter = p_dm_odm->adapter;
|
||||
|
||||
rtw_run_in_thread_cmd(padapter, hal_com_txbf_clk_work_item_callback, padapter);
|
||||
#else
|
||||
hal_com_txbf_clk_work_item_callback(p_dm_odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
phydm_beamform_set_reset_tx_path(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_reset_tx_path_work_item)) == false)
|
||||
odm_schedule_work_item(&(p_txbf_info->txbf_reset_tx_path_work_item));
|
||||
#else
|
||||
hal_com_txbf_reset_tx_path_work_item_callback(p_dm_odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
phydm_beamform_set_get_tx_rate(
|
||||
void *p_dm_void
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_get_tx_rate_work_item)) == false)
|
||||
odm_schedule_work_item(&(p_txbf_info->txbf_get_tx_rate_work_item));
|
||||
#else
|
||||
hal_com_txbf_get_tx_rate_work_item_callback(p_dm_odm);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
hal_com_txbf_enter_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#else
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#endif
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
u8 idx = p_txbf_info->txbf_idx;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))
|
||||
hal_txbf_jaguar_enter(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8192E)
|
||||
hal_txbf_8192e_enter(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
hal_txbf_8814a_enter(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8822B)
|
||||
hal_txbf_8822b_enter(p_dm_odm, idx);
|
||||
}
|
||||
|
||||
void
|
||||
hal_com_txbf_leave_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#else
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#endif
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
u8 idx = p_txbf_info->txbf_idx;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))
|
||||
hal_txbf_jaguar_leave(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8192E)
|
||||
hal_txbf_8192e_leave(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
hal_txbf_8814a_leave(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8822B)
|
||||
hal_txbf_8822b_leave(p_dm_odm, idx);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
hal_com_txbf_fw_ndpa_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#else
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#endif
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
u8 idx = p_txbf_info->ndpa_idx;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))
|
||||
hal_txbf_jaguar_fw_txbf(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8192E)
|
||||
hal_txbf_8192e_fw_tx_bf(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
hal_txbf_8814a_fw_txbf(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8822B)
|
||||
hal_txbf_8822b_fw_txbf(p_dm_odm, idx);
|
||||
}
|
||||
|
||||
void
|
||||
hal_com_txbf_clk_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#else
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#endif
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8812)
|
||||
hal_txbf_jaguar_clk_8812a(p_dm_odm);
|
||||
}
|
||||
|
||||
|
||||
|
||||
void
|
||||
hal_com_txbf_rate_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#else
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#endif
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
u8 BW = p_txbf_info->BW;
|
||||
u8 rate = p_txbf_info->rate;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8812)
|
||||
hal_txbf_8812a_set_ndpa_rate(p_dm_odm, BW, rate);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8192E)
|
||||
hal_txbf_8192e_set_ndpa_rate(p_dm_odm, BW, rate);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
hal_txbf_8814a_set_ndpa_rate(p_dm_odm, BW, rate);
|
||||
|
||||
}
|
||||
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
void
|
||||
hal_com_txbf_fw_ndpa_timer_callback(
|
||||
struct timer_list *p_timer
|
||||
)
|
||||
{
|
||||
|
||||
struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->Adapter;
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (*p_dm_odm->p_is_fw_dw_rsvd_page_in_progress)
|
||||
odm_set_timer(p_dm_odm, &(p_txbf_info->txbf_fw_ndpa_timer), 5);
|
||||
else
|
||||
odm_schedule_work_item(&(p_txbf_info->txbf_fw_ndpa_work_item));
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
void
|
||||
hal_com_txbf_status_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#else
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#endif
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
u8 idx = p_txbf_info->txbf_idx;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))
|
||||
hal_txbf_jaguar_status(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8192E)
|
||||
hal_txbf_8192e_status(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
hal_txbf_8814a_status(p_dm_odm, idx);
|
||||
else if (p_dm_odm->support_ic_type & ODM_RTL8822B)
|
||||
hal_txbf_8822b_status(p_dm_odm, idx);
|
||||
}
|
||||
|
||||
void
|
||||
hal_com_txbf_reset_tx_path_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#else
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#endif
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
u8 idx = p_txbf_info->txbf_idx;
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
hal_txbf_8814a_reset_tx_path(p_dm_odm, idx);
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
hal_com_txbf_get_tx_rate_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
)
|
||||
{
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
#else
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
#endif
|
||||
|
||||
if (p_dm_odm->support_ic_type & ODM_RTL8814A)
|
||||
hal_txbf_8814a_get_tx_rate(p_dm_odm);
|
||||
}
|
||||
|
||||
|
||||
bool
|
||||
hal_com_txbf_set(
|
||||
void *p_dm_void,
|
||||
u8 set_type,
|
||||
void *p_in_buf
|
||||
)
|
||||
{
|
||||
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
|
||||
u8 *p_u1_tmp = (u8 *)p_in_buf;
|
||||
struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] set_type = 0x%X\n", __func__, set_type));
|
||||
|
||||
switch (set_type) {
|
||||
case TXBF_SET_SOUNDING_ENTER:
|
||||
p_txbf_info->txbf_idx = *p_u1_tmp;
|
||||
phydm_beamform_set_sounding_enter(p_dm_odm);
|
||||
break;
|
||||
|
||||
case TXBF_SET_SOUNDING_LEAVE:
|
||||
p_txbf_info->txbf_idx = *p_u1_tmp;
|
||||
phydm_beamform_set_sounding_leave(p_dm_odm);
|
||||
break;
|
||||
|
||||
case TXBF_SET_SOUNDING_RATE:
|
||||
p_txbf_info->BW = p_u1_tmp[0];
|
||||
p_txbf_info->rate = p_u1_tmp[1];
|
||||
phydm_beamform_set_sounding_rate(p_dm_odm);
|
||||
break;
|
||||
|
||||
case TXBF_SET_SOUNDING_STATUS:
|
||||
p_txbf_info->txbf_idx = *p_u1_tmp;
|
||||
phydm_beamform_set_sounding_status(p_dm_odm);
|
||||
break;
|
||||
|
||||
case TXBF_SET_SOUNDING_FW_NDPA:
|
||||
p_txbf_info->ndpa_idx = *p_u1_tmp;
|
||||
phydm_beamform_set_sounding_fw_ndpa(p_dm_odm);
|
||||
break;
|
||||
|
||||
case TXBF_SET_SOUNDING_CLK:
|
||||
phydm_beamform_set_sounding_clk(p_dm_odm);
|
||||
break;
|
||||
|
||||
case TXBF_SET_TX_PATH_RESET:
|
||||
p_txbf_info->txbf_idx = *p_u1_tmp;
|
||||
phydm_beamform_set_reset_tx_path(p_dm_odm);
|
||||
break;
|
||||
|
||||
case TXBF_SET_GET_TX_RATE:
|
||||
phydm_beamform_set_get_tx_rate(p_dm_odm);
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
bool
|
||||
hal_com_txbf_get(
|
||||
struct _ADAPTER *adapter,
|
||||
u8 get_type,
|
||||
void *p_out_buf
|
||||
)
|
||||
{
|
||||
PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter);
|
||||
struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc;
|
||||
bool *p_boolean = (bool *)p_out_buf;
|
||||
|
||||
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
|
||||
|
||||
if (get_type == TXBF_GET_EXPLICIT_BEAMFORMEE) {
|
||||
if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(adapter))
|
||||
*p_boolean = false;
|
||||
else if (/*IS_HARDWARE_TYPE_8822B(adapter) ||*/
|
||||
IS_HARDWARE_TYPE_8821B(adapter) ||
|
||||
IS_HARDWARE_TYPE_8192E(adapter) ||
|
||||
IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
|
||||
*p_boolean = true;
|
||||
else
|
||||
*p_boolean = false;
|
||||
} else if (get_type == TXBF_GET_EXPLICIT_BEAMFORMER) {
|
||||
if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(adapter))
|
||||
*p_boolean = false;
|
||||
else if (/*IS_HARDWARE_TYPE_8822B(adapter) ||*/
|
||||
IS_HARDWARE_TYPE_8821B(adapter) ||
|
||||
IS_HARDWARE_TYPE_8192E(adapter) ||
|
||||
IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) {
|
||||
if (p_hal_data->RF_Type == RF_2T2R || p_hal_data->RF_Type == RF_3T3R)
|
||||
*p_boolean = true;
|
||||
else
|
||||
*p_boolean = false;
|
||||
} else
|
||||
*p_boolean = false;
|
||||
} else if (get_type == TXBF_GET_MU_MIMO_STA) {
|
||||
#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1))
|
||||
if (IS_HARDWARE_TYPE_8822B(adapter) || IS_HARDWARE_TYPE_8821C(adapter))
|
||||
*p_boolean = true;
|
||||
else
|
||||
#endif
|
||||
*p_boolean = false;
|
||||
|
||||
|
||||
} else if (get_type == TXBF_GET_MU_MIMO_AP) {
|
||||
#if (RTL8822B_SUPPORT == 1)
|
||||
if (IS_HARDWARE_TYPE_8822B(adapter))
|
||||
*p_boolean = true;
|
||||
else
|
||||
#endif
|
||||
*p_boolean = false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
|
@ -44,19 +44,7 @@ struct _HAL_TXBF_INFO {
|
|||
u8 ndpa_idx;
|
||||
u8 BW;
|
||||
u8 rate;
|
||||
|
||||
struct timer_list txbf_fw_ndpa_timer;
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
RT_WORK_ITEM txbf_enter_work_item;
|
||||
RT_WORK_ITEM txbf_leave_work_item;
|
||||
RT_WORK_ITEM txbf_fw_ndpa_work_item;
|
||||
RT_WORK_ITEM txbf_clk_work_item;
|
||||
RT_WORK_ITEM txbf_status_work_item;
|
||||
RT_WORK_ITEM txbf_rate_work_item;
|
||||
RT_WORK_ITEM txbf_reset_tx_path_work_item;
|
||||
RT_WORK_ITEM txbf_get_tx_rate_work_item;
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
|
@ -73,65 +61,37 @@ hal_com_txbf_config_gtab(
|
|||
|
||||
void
|
||||
hal_com_txbf_enter_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
);
|
||||
|
||||
void
|
||||
hal_com_txbf_leave_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
);
|
||||
|
||||
void
|
||||
hal_com_txbf_fw_ndpa_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
);
|
||||
|
||||
void
|
||||
hal_com_txbf_clk_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
);
|
||||
|
||||
void
|
||||
hal_com_txbf_reset_tx_path_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
);
|
||||
|
||||
void
|
||||
hal_com_txbf_get_tx_rate_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
);
|
||||
|
||||
void
|
||||
hal_com_txbf_rate_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
);
|
||||
|
||||
void
|
||||
|
@ -141,11 +101,7 @@ hal_com_txbf_fw_ndpa_timer_callback(
|
|||
|
||||
void
|
||||
hal_com_txbf_status_work_item_callback(
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
struct _ADAPTER *adapter
|
||||
#else
|
||||
void *p_dm_void
|
||||
#endif
|
||||
);
|
||||
|
||||
bool
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -1,158 +1,8 @@
|
|||
#ifndef __HAL_TXBF_INTERFACE_H__
|
||||
#define __HAL_TXBF_INTERFACE_H__
|
||||
|
||||
#if (BEAMFORMING_SUPPORT == 1)
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
|
||||
#define a_SifsTime ((IS_WIRELESS_MODE_5G(adapter)|| IS_WIRELESS_MODE_N_24G(adapter))? 16 : 10)
|
||||
|
||||
void
|
||||
beamforming_gid_paid(
|
||||
struct _ADAPTER *adapter,
|
||||
PRT_TCB p_tcb
|
||||
);
|
||||
|
||||
enum rt_status
|
||||
beamforming_get_report_frame(
|
||||
struct _ADAPTER *adapter,
|
||||
PRT_RFD p_rfd,
|
||||
POCTET_STRING p_pdu_os
|
||||
);
|
||||
|
||||
void
|
||||
beamforming_get_ndpa_frame(
|
||||
void *p_dm_void,
|
||||
OCTET_STRING pdu_os
|
||||
);
|
||||
|
||||
bool
|
||||
send_fw_ht_ndpa_packet(
|
||||
void *p_dm_void,
|
||||
u8 *RA,
|
||||
CHANNEL_WIDTH BW
|
||||
);
|
||||
|
||||
bool
|
||||
send_fw_vht_ndpa_packet(
|
||||
void *p_dm_void,
|
||||
u8 *RA,
|
||||
u16 AID,
|
||||
CHANNEL_WIDTH BW
|
||||
);
|
||||
|
||||
bool
|
||||
send_sw_vht_ndpa_packet(
|
||||
void *p_dm_void,
|
||||
u8 *RA,
|
||||
u16 AID,
|
||||
CHANNEL_WIDTH BW
|
||||
);
|
||||
|
||||
bool
|
||||
send_sw_ht_ndpa_packet(
|
||||
void *p_dm_void,
|
||||
u8 *RA,
|
||||
CHANNEL_WIDTH BW
|
||||
);
|
||||
|
||||
#if (SUPPORT_MU_BF == 1)
|
||||
enum rt_status
|
||||
beamforming_get_vht_gid_mgnt_frame(
|
||||
struct _ADAPTER *adapter,
|
||||
PRT_RFD p_rfd,
|
||||
POCTET_STRING p_pdu_os
|
||||
);
|
||||
|
||||
bool
|
||||
send_sw_vht_gid_mgnt_frame(
|
||||
void *p_dm_void,
|
||||
u8 *RA,
|
||||
u8 idx
|
||||
);
|
||||
|
||||
bool
|
||||
send_sw_vht_bf_report_poll(
|
||||
void *p_dm_void,
|
||||
u8 *RA,
|
||||
bool is_final_poll
|
||||
);
|
||||
|
||||
bool
|
||||
send_sw_vht_mu_ndpa_packet(
|
||||
void *p_dm_void,
|
||||
CHANNEL_WIDTH BW
|
||||
);
|
||||
#else
|
||||
#define beamforming_get_vht_gid_mgnt_frame(adapter, p_rfd, p_pdu_os) RT_STATUS_FAILURE
|
||||
#define send_sw_vht_gid_mgnt_frame(p_dm_void, RA)
|
||||
#define send_sw_vht_bf_report_poll(p_dm_void, RA, is_final_poll)
|
||||
#define send_sw_vht_mu_ndpa_packet(p_dm_void, BW)
|
||||
#endif
|
||||
|
||||
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
|
||||
u32
|
||||
beamforming_get_report_frame(
|
||||
void *p_dm_void,
|
||||
union recv_frame *precv_frame
|
||||
);
|
||||
|
||||
bool
|
||||
send_fw_ht_ndpa_packet(
|
||||
void *p_dm_void,
|
||||
u8 *RA,
|
||||
CHANNEL_WIDTH BW
|
||||
);
|
||||
|
||||
bool
|
||||
send_sw_ht_ndpa_packet(
|
||||
void *p_dm_void,
|
||||
u8 *RA,
|
||||
CHANNEL_WIDTH BW
|
||||
);
|
||||
|
||||
bool
|
||||
send_fw_vht_ndpa_packet(
|
||||
void *p_dm_void,
|
||||
u8 *RA,
|
||||
u16 AID,
|
||||
CHANNEL_WIDTH BW
|
||||
);
|
||||
|
||||
bool
|
||||
send_sw_vht_ndpa_packet(
|
||||
void *p_dm_void,
|
||||
u8 *RA,
|
||||
u16 AID,
|
||||
CHANNEL_WIDTH BW
|
||||
);
|
||||
#endif
|
||||
|
||||
void
|
||||
beamforming_get_ndpa_frame(
|
||||
void *p_dm_void,
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
OCTET_STRING pdu_os
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
union recv_frame *precv_frame
|
||||
#endif
|
||||
);
|
||||
|
||||
bool
|
||||
dbg_send_sw_vht_mundpa_packet(
|
||||
void *p_dm_void,
|
||||
CHANNEL_WIDTH BW
|
||||
);
|
||||
|
||||
#else
|
||||
#define beamforming_get_ndpa_frame(p_dm_odm, _pdu_os)
|
||||
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
|
||||
#define beamforming_get_report_frame(adapter, precv_frame) RT_STATUS_FAILURE
|
||||
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||||
#define beamforming_get_report_frame(adapter, p_rfd, p_pdu_os) RT_STATUS_FAILURE
|
||||
#define beamforming_get_vht_gid_mgnt_frame(adapter, p_rfd, p_pdu_os) RT_STATUS_FAILURE
|
||||
#endif
|
||||
#define beamforming_get_report_frame(adapter, precv_frame) RT_STATUS_FAILURE
|
||||
#define send_fw_ht_ndpa_packet(p_dm_void, RA, BW)
|
||||
#define send_sw_ht_ndpa_packet(p_dm_void, RA, BW)
|
||||
#define send_fw_vht_ndpa_packet(p_dm_void, RA, AID, BW)
|
||||
|
@ -160,6 +10,5 @@ dbg_send_sw_vht_mundpa_packet(
|
|||
#define send_sw_vht_gid_mgnt_frame(p_dm_void, RA, idx)
|
||||
#define send_sw_vht_bf_report_poll(p_dm_void, RA, is_final_poll)
|
||||
#define send_sw_vht_mu_ndpa_packet(p_dm_void, BW)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
Loading…
Reference in a new issue