mirror of
https://github.com/lwfinger/rtl8188eu.git
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rtl8188eu: Fix checkpatch errors in hal/rtl8188e_mp.c, hal/rtl8188e_phycfg.c, and hal/rtl8188e_rf6052.c
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
parent
9c3c9ddc8c
commit
f527ca59c9
3 changed files with 709 additions and 1013 deletions
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
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@ -50,15 +50,15 @@
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/* Define local structure for debug!!!!! */
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struct rf_shadow {
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/* Shadow register value */
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u32 Value;
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u32 Value;
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/* Compare or not flag */
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u8 Compare;
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u8 Compare;
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/* Record If it had ever modified unpredicted */
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u8 ErrorOrNot;
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u8 ErrorOrNot;
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/* Recorver Flag */
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u8 Recorver;
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u8 Recorver;
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/* */
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u8 Driver_Write;
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u8 Driver_Write;
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};
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/*---------------------------Define Local Constant---------------------------*/
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@ -91,8 +91,7 @@ static struct rf_shadow RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
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* Firmwaer support the utility later.
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*
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*---------------------------------------------------------------------------*/
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void rtl8188e_RF_ChangeTxPath( struct adapter * Adapter,
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u16 DataRate)
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void rtl8188e_RF_ChangeTxPath(struct adapter *Adapter, u16 DataRate)
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{
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/* We do not support gain table change inACUT now !!!! Delete later !!! */
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} /* RF_ChangeTxPath */
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@ -103,7 +102,7 @@ void rtl8188e_RF_ChangeTxPath( struct adapter * Adapter,
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*
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* Overview: This function is called by SetBWModeCallback8190Pci() only
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*
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* Input: struct adapter * Adapter
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* Input: struct adapter *Adapter
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* WIRELESS_BANDWIDTH_E Bandwidth 20M or 40M
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*
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* Output: NONE
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@ -112,33 +111,25 @@ void rtl8188e_RF_ChangeTxPath( struct adapter * Adapter,
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*
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* Note: For RF type 0222D
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*---------------------------------------------------------------------------*/
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void
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rtl8188e_PHY_RF6052SetBandwidth(
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struct adapter * Adapter,
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enum ht_channel_width Bandwidth) /* 20M or 40M */
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void rtl8188e_PHY_RF6052SetBandwidth(struct adapter *Adapter,
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enum ht_channel_width Bandwidth)
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{
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struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
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struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
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switch (Bandwidth)
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{
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case HT_CHANNEL_WIDTH_20:
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pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10) | BIT(11));
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PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
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break;
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case HT_CHANNEL_WIDTH_40:
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pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff)| BIT(10));
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PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
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break;
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default:
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/* RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth )); */
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break;
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switch (Bandwidth) {
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case HT_CHANNEL_WIDTH_20:
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pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10) | BIT(11));
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PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
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break;
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case HT_CHANNEL_WIDTH_40:
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pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10));
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PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
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break;
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default:
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break;
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}
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}
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/*-----------------------------------------------------------------------------
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* Function: PHY_RF6052SetCckTxPower
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*
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@ -158,34 +149,30 @@ rtl8188e_PHY_RF6052SetBandwidth(
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void
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rtl8188e_PHY_RF6052SetCckTxPower(
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struct adapter * Adapter,
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u8* pPowerlevel)
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struct adapter *Adapter,
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u8 *pPowerlevel)
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{
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struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
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struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
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struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
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struct dm_priv *pdmpriv = &pHalData->dmpriv;
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struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
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/* PMGNT_INFO pMgntInfo=&Adapter->MgntInfo; */
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u32 TxAGC[2]={0, 0}, tmpval=0,pwrtrac_value;
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bool TurboScanOff = false;
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u8 idx1, idx2;
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u8* ptr;
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u8 direction;
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u32 TxAGC[2] = {0, 0}, tmpval = 0, pwrtrac_value;
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bool TurboScanOff = false;
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u8 idx1, idx2;
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u8 *ptr;
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u8 direction;
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/* FOR CE ,must disable turbo scan */
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TurboScanOff = true;
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if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS)
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{
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if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) {
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TxAGC[RF_PATH_A] = 0x3f3f3f3f;
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TxAGC[RF_PATH_B] = 0x3f3f3f3f;
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TurboScanOff = true;/* disable turbo scan */
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if (TurboScanOff)
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{
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for (idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
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{
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if (TurboScanOff) {
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for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
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TxAGC[idx1] =
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pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
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(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
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@ -194,33 +181,27 @@ rtl8188e_PHY_RF6052SetCckTxPower(
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TxAGC[idx1] = 0x20;
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}
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}
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}
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else
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{
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/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
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/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
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/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */
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if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
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{
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} else {
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/* Driver dynamic Tx power shall not affect Tx power.
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* It shall be determined by power training mechanism.
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i * Currently, we cannot fully disable driver dynamic
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* tx power mechanism because it is referenced by BT
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* coexist mechanism.
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* In the future, two mechanism shall be separated from
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* each other and maintained independantly. */
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if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) {
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TxAGC[RF_PATH_A] = 0x10101010;
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TxAGC[RF_PATH_B] = 0x10101010;
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}
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else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
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{
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} else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) {
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TxAGC[RF_PATH_A] = 0x00000000;
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TxAGC[RF_PATH_B] = 0x00000000;
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}
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else
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{
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for (idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
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{
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} else {
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for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
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TxAGC[idx1] =
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pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
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(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
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}
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if (pHalData->EEPROMRegulatory==0)
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{
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if (pHalData->EEPROMRegulatory == 0) {
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tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) +
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(pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8);
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TxAGC[RF_PATH_A] += tmpval;
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@ -231,12 +212,9 @@ rtl8188e_PHY_RF6052SetCckTxPower(
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}
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}
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}
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for (idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
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{
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ptr = (u8*)(&(TxAGC[idx1]));
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for (idx2=0; idx2<4; idx2++)
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{
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for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
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ptr = (u8 *)(&(TxAGC[idx1]));
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for (idx2 = 0; idx2 < 4; idx2++) {
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if (*ptr > RF6052_MAX_TX_PWR)
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*ptr = RF6052_MAX_TX_PWR;
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ptr++;
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@ -244,18 +222,16 @@ rtl8188e_PHY_RF6052SetCckTxPower(
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}
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ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 1, &direction, &pwrtrac_value);
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if (direction == 1) /* Increase TX pwoer */
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{
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if (direction == 1) {
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/* Increase TX pwoer */
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TxAGC[0] += pwrtrac_value;
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TxAGC[1] += pwrtrac_value;
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}
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else if (direction == 2) /* Decrease TX pwoer */
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{
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} else if (direction == 2) {
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/* Decrease TX pwoer */
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TxAGC[0] -= pwrtrac_value;
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TxAGC[1] -= pwrtrac_value;
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}
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/* rf-A cck tx power */
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tmpval = TxAGC[RF_PATH_A]&0xff;
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PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
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@ -273,142 +249,113 @@ rtl8188e_PHY_RF6052SetCckTxPower(
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/* powerbase0 for OFDM rates */
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/* powerbase1 for HT MCS rates */
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/* */
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static void getPowerBase88E(
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struct adapter * Adapter,
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u8* pPowerLevelOFDM,
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u8* pPowerLevelBW20,
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u8* pPowerLevelBW40,
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u8 Channel,
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u32* OfdmBase,
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u32* MCSBase
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)
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static void getpowerbase88e(struct adapter *Adapter, u8 *pPowerLevelOFDM,
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u8 *pPowerLevelBW20, u8 *pPowerLevelBW40, u8 Channel, u32 *OfdmBase, u32 *MCSBase)
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{
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struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
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u32 powerBase0, powerBase1;
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u8 Legacy_pwrdiff=0;
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s8 HT20_pwrdiff=0;
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u8 i, powerlevel[2];
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struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
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u32 powerBase0, powerBase1;
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u8 Legacy_pwrdiff = 0;
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s8 HT20_pwrdiff = 0;
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u8 i, powerlevel[2];
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for (i=0; i<2; i++)
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{
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for (i = 0; i < 2; i++) {
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powerBase0 = pPowerLevelOFDM[i];
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powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
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powerBase0 = (powerBase0<<24) | (powerBase0<<16) | (powerBase0<<8) | powerBase0;
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*(OfdmBase+i) = powerBase0;
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}
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for (i=0; i<pHalData->NumTotalRFPath; i++)
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{
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for (i = 0; i < pHalData->NumTotalRFPath; i++) {
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/* Check HT20 to HT40 diff */
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if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
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{
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powerlevel[i] = pPowerLevelBW20[i];
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}
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else
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{
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powerlevel[i] = pPowerLevelBW40[i];
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}
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powerBase1 = powerlevel[i];
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powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
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powerBase1 = (powerBase1<<24) | (powerBase1<<16) | (powerBase1<<8) | powerBase1;
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*(MCSBase+i) = powerBase1;
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}
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}
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static void getTxPowerWriteValByRegulatory88E(
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struct adapter * Adapter,
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u8 Channel,
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u8 index,
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u32* powerBase0,
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u32* powerBase1,
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u32* pOutWriteVal
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)
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static void get_rx_power_val_by_reg(struct adapter *Adapter, u8 Channel,
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u8 index, u32 *powerBase0, u32 *powerBase1,
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u32 *pOutWriteVal)
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{
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struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
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struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
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struct dm_priv *pdmpriv = &pHalData->dmpriv;
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u1Byte i, chnlGroup=0, pwr_diff_limit[4], customer_pwr_limit;
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s1Byte pwr_diff=0;
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u4Byte writeVal, customer_limit, rf;
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u1Byte Regulatory = pHalData->EEPROMRegulatory;
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u1Byte i, chnlGroup = 0, pwr_diff_limit[4], customer_pwr_limit;
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s1Byte pwr_diff = 0;
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u4Byte writeVal, customer_limit, rf;
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u1Byte Regulatory = pHalData->EEPROMRegulatory;
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/* */
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/* Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */
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/* */
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for (rf=0; rf<2; rf++) {
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switch (Regulatory)
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{
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case 0: /* Realtek better performance */
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/* increase power diff defined by Realtek for large power */
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chnlGroup = 0;
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writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
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((index<2)?powerBase0[rf]:powerBase1[rf]);
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break;
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case 1: /* Realtek regulatory */
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/* increase power diff defined by Realtek for regulatory */
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{
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if (pHalData->pwrGroupCnt == 1)
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chnlGroup = 0;
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if (pHalData->pwrGroupCnt >= pHalData->PGMaxGroup)
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{
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if (Channel < 3) /* Chanel 1-2 */
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chnlGroup = 0;
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else if (Channel < 6) /* Channel 3-5 */
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chnlGroup = 1;
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else if (Channel <9) /* Channel 6-8 */
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chnlGroup = 2;
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else if (Channel <12) /* Channel 9-11 */
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chnlGroup = 3;
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else if (Channel <14) /* Channel 12-13 */
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chnlGroup = 4;
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else if (Channel ==14) /* Channel 14 */
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chnlGroup = 5;
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}
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writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
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((index<2)?powerBase0[rf]:powerBase1[rf]);
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}
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break;
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case 2: /* Better regulatory */
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/* don't increase any power diff */
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writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]);
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break;
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case 3: /* Customer defined power diff. */
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/* increase power diff defined by customer. */
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for (rf = 0; rf < 2; rf++) {
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switch (Regulatory) {
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case 0: /* Realtek better performance */
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/* increase power diff defined by Realtek for large power */
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chnlGroup = 0;
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writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] +
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((index < 2) ? powerBase0[rf] : powerBase1[rf]);
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break;
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case 1: /* Realtek regulatory */
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/* increase power diff defined by Realtek for regulatory */
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if (pHalData->pwrGroupCnt == 1)
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chnlGroup = 0;
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if (pHalData->pwrGroupCnt >= pHalData->PGMaxGroup) {
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if (Channel < 3) /* Chanel 1-2 */
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chnlGroup = 0;
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else if (Channel < 6) /* Channel 3-5 */
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chnlGroup = 1;
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else if (Channel < 9) /* Channel 6-8 */
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chnlGroup = 2;
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else if (Channel < 12) /* Channel 9-11 */
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chnlGroup = 3;
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else if (Channel < 14) /* Channel 12-13 */
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chnlGroup = 4;
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else if (Channel == 14) /* Channel 14 */
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chnlGroup = 5;
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}
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writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] +
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((index < 2) ? powerBase0[rf] : powerBase1[rf]);
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break;
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case 2: /* Better regulatory */
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/* don't increase any power diff */
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writeVal = ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
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break;
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case 3: /* Customer defined power diff. */
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/* increase power diff defined by customer. */
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chnlGroup = 0;
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if (index < 2)
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pwr_diff = pHalData->TxPwrLegacyHtDiff[rf][Channel-1];
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else if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
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pwr_diff = pHalData->TxPwrHt20Diff[rf][Channel-1];
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if (index < 2)
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pwr_diff = pHalData->TxPwrLegacyHtDiff[rf][Channel-1];
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else if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
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pwr_diff = pHalData->TxPwrHt20Diff[rf][Channel-1];
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if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
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customer_pwr_limit = pHalData->PwrGroupHT40[rf][Channel-1];
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else
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customer_pwr_limit = pHalData->PwrGroupHT20[rf][Channel-1];
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if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
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customer_pwr_limit = pHalData->PwrGroupHT40[rf][Channel-1];
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else
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customer_pwr_limit = pHalData->PwrGroupHT20[rf][Channel-1];
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if (pwr_diff >= customer_pwr_limit)
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pwr_diff = 0;
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else
|
||||
pwr_diff = customer_pwr_limit - pwr_diff;
|
||||
if (pwr_diff >= customer_pwr_limit)
|
||||
pwr_diff = 0;
|
||||
else
|
||||
pwr_diff = customer_pwr_limit - pwr_diff;
|
||||
|
||||
for (i=0; i<4; i++)
|
||||
{
|
||||
pwr_diff_limit[i] = (u1Byte)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]&(0x7f<<(i*8)))>>(i*8));
|
||||
for (i = 0; i < 4; i++) {
|
||||
pwr_diff_limit[i] = (u1Byte)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)]&(0x7f<<(i*8)))>>(i*8));
|
||||
|
||||
if (pwr_diff_limit[i] > pwr_diff)
|
||||
pwr_diff_limit[i] = pwr_diff;
|
||||
}
|
||||
customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
|
||||
(pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
|
||||
writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]);
|
||||
break;
|
||||
default:
|
||||
chnlGroup = 0;
|
||||
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
|
||||
((index<2)?powerBase0[rf]:powerBase1[rf]);
|
||||
break;
|
||||
if (pwr_diff_limit[i] > pwr_diff)
|
||||
pwr_diff_limit[i] = pwr_diff;
|
||||
}
|
||||
customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
|
||||
(pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
|
||||
writeVal = customer_limit + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
|
||||
break;
|
||||
default:
|
||||
chnlGroup = 0;
|
||||
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] +
|
||||
((index < 2) ? powerBase0[rf] : powerBase1[rf]);
|
||||
break;
|
||||
}
|
||||
|
||||
/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
|
||||
/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
|
||||
/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */
|
||||
|
|
@ -421,76 +368,64 @@ static void getTxPowerWriteValByRegulatory88E(
|
|||
/* 20100628 Joseph: High power mode for BT-Coexist mechanism. */
|
||||
/* This mechanism is only applied when Driver-Highpower-Mechanism is OFF. */
|
||||
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
|
||||
{
|
||||
writeVal = writeVal - 0x06060606;
|
||||
}
|
||||
else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
|
||||
{
|
||||
writeVal = writeVal ;
|
||||
}
|
||||
writeVal = writeVal;
|
||||
*(pOutWriteVal+rf) = writeVal;
|
||||
}
|
||||
}
|
||||
|
||||
static void writeOFDMPowerReg88E(
|
||||
struct adapter * Adapter,
|
||||
u8 index,
|
||||
u32* pValue
|
||||
)
|
||||
static void writeOFDMPowerReg88E(struct adapter *Adapter, u8 index, u32 *pValue)
|
||||
{
|
||||
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
|
||||
u16 RegOffset_A[6] = { rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24,
|
||||
rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04,
|
||||
rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12};
|
||||
u16 RegOffset_B[6] = { rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24,
|
||||
rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04,
|
||||
rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12};
|
||||
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
|
||||
u16 regoffset_a[6] = {
|
||||
rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24,
|
||||
rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04,
|
||||
rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12};
|
||||
u16 regoffset_b[6] = {
|
||||
rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24,
|
||||
rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04,
|
||||
rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12};
|
||||
u8 i, rf, pwr_val[4];
|
||||
u32 writeVal;
|
||||
u16 RegOffset;
|
||||
u16 regoffset;
|
||||
|
||||
for (rf=0; rf<2; rf++)
|
||||
{
|
||||
for (rf = 0; rf < 2; rf++) {
|
||||
writeVal = pValue[rf];
|
||||
for (i=0; i<4; i++)
|
||||
{
|
||||
for (i = 0; i < 4; i++) {
|
||||
pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));
|
||||
if (pwr_val[i] > RF6052_MAX_TX_PWR)
|
||||
pwr_val[i] = RF6052_MAX_TX_PWR;
|
||||
}
|
||||
writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) |(pwr_val[1]<<8) |pwr_val[0];
|
||||
writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) | (pwr_val[1]<<8) | pwr_val[0];
|
||||
|
||||
if (rf == 0)
|
||||
RegOffset = RegOffset_A[index];
|
||||
regoffset = regoffset_a[index];
|
||||
else
|
||||
RegOffset = RegOffset_B[index];
|
||||
regoffset = regoffset_b[index];
|
||||
|
||||
PHY_SetBBReg(Adapter, RegOffset, bMaskDWord, writeVal);
|
||||
PHY_SetBBReg(Adapter, regoffset, bMaskDWord, writeVal);
|
||||
|
||||
/* 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */
|
||||
if (((pHalData->rf_type == RF_2T2R) &&
|
||||
(RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs15_Mcs12))||
|
||||
((pHalData->rf_type != RF_2T2R) &&
|
||||
(RegOffset == rTxAGC_A_Mcs07_Mcs04 || RegOffset == rTxAGC_B_Mcs07_Mcs04)) )
|
||||
{
|
||||
(regoffset == rTxAGC_A_Mcs15_Mcs12 || regoffset == rTxAGC_B_Mcs15_Mcs12)) ||
|
||||
((pHalData->rf_type != RF_2T2R) &&
|
||||
(regoffset == rTxAGC_A_Mcs07_Mcs04 || regoffset == rTxAGC_B_Mcs07_Mcs04))) {
|
||||
writeVal = pwr_val[3];
|
||||
if (RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_A_Mcs07_Mcs04)
|
||||
RegOffset = 0xc90;
|
||||
if (RegOffset == rTxAGC_B_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs07_Mcs04)
|
||||
RegOffset = 0xc98;
|
||||
for (i=0; i<3; i++)
|
||||
{
|
||||
if (i!=2)
|
||||
writeVal = (writeVal>8)?(writeVal-8):0;
|
||||
if (regoffset == rTxAGC_A_Mcs15_Mcs12 || regoffset == rTxAGC_A_Mcs07_Mcs04)
|
||||
regoffset = 0xc90;
|
||||
if (regoffset == rTxAGC_B_Mcs15_Mcs12 || regoffset == rTxAGC_B_Mcs07_Mcs04)
|
||||
regoffset = 0xc98;
|
||||
for (i = 0; i < 3; i++) {
|
||||
if (i != 2)
|
||||
writeVal = (writeVal > 8) ? (writeVal-8) : 0;
|
||||
else
|
||||
writeVal = (writeVal>6)?(writeVal-6):0;
|
||||
rtw_write8(Adapter, (u32)(RegOffset+i), (u8)writeVal);
|
||||
writeVal = (writeVal > 6) ? (writeVal-6) : 0;
|
||||
rtw_write8(Adapter, (u32)(regoffset+i), (u8)writeVal);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Function: PHY_RF6052SetOFDMTxPower
|
||||
*
|
||||
|
|
@ -516,71 +451,53 @@ static void writeOFDMPowerReg88E(
|
|||
|
||||
void
|
||||
rtl8188e_PHY_RF6052SetOFDMTxPower(
|
||||
struct adapter * Adapter,
|
||||
u8* pPowerLevelOFDM,
|
||||
u8* pPowerLevelBW20,
|
||||
u8* pPowerLevelBW40,
|
||||
u8 Channel)
|
||||
struct adapter *Adapter,
|
||||
u8 *pPowerLevelOFDM,
|
||||
u8 *pPowerLevelBW20,
|
||||
u8 *pPowerLevelBW40,
|
||||
u8 Channel)
|
||||
{
|
||||
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
|
||||
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
|
||||
u32 writeVal[2], powerBase0[2], powerBase1[2], pwrtrac_value;
|
||||
u8 direction;
|
||||
u8 index = 0;
|
||||
|
||||
getPowerBase88E(Adapter, pPowerLevelOFDM,pPowerLevelBW20,pPowerLevelBW40, Channel, &powerBase0[0], &powerBase1[0]);
|
||||
getpowerbase88e(Adapter, pPowerLevelOFDM, pPowerLevelBW20, pPowerLevelBW40, Channel, &powerBase0[0], &powerBase1[0]);
|
||||
|
||||
/* */
|
||||
/* 2012/04/23 MH According to power tracking value, we need to revise OFDM tx power. */
|
||||
/* This is ued to fix unstable power tracking mode. */
|
||||
/* */
|
||||
ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 0, &direction, &pwrtrac_value);
|
||||
|
||||
for (index=0; index<6; index++)
|
||||
{
|
||||
getTxPowerWriteValByRegulatory88E(Adapter, Channel, index,
|
||||
&powerBase0[0], &powerBase1[0], &writeVal[0]);
|
||||
for (index = 0; index < 6; index++) {
|
||||
get_rx_power_val_by_reg(Adapter, Channel, index,
|
||||
&powerBase0[0], &powerBase1[0],
|
||||
&writeVal[0]);
|
||||
|
||||
if (direction == 1)
|
||||
{
|
||||
if (direction == 1) {
|
||||
writeVal[0] += pwrtrac_value;
|
||||
writeVal[1] += pwrtrac_value;
|
||||
}
|
||||
else if (direction == 2)
|
||||
{
|
||||
} else if (direction == 2) {
|
||||
writeVal[0] -= pwrtrac_value;
|
||||
writeVal[1] -= pwrtrac_value;
|
||||
}
|
||||
|
||||
writeOFDMPowerReg88E(Adapter, index, &writeVal[0]);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
phy_RF6052_Config_HardCode(
|
||||
struct adapter * Adapter
|
||||
)
|
||||
static int phy_RF6052_Config_ParaFile(struct adapter *Adapter)
|
||||
{
|
||||
}
|
||||
|
||||
static int
|
||||
phy_RF6052_Config_ParaFile(
|
||||
struct adapter * Adapter
|
||||
)
|
||||
{
|
||||
u32 u4RegValue;
|
||||
u8 eRFPath;
|
||||
u32 u4RegValue;
|
||||
u8 eRFPath;
|
||||
struct bb_reg_def *pPhyReg;
|
||||
int rtStatus = _SUCCESS;
|
||||
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
|
||||
static char sz88eRadioAFile[] = RTL8188E_PHY_RADIO_A;
|
||||
static char sz88eRadioBFile[] = RTL8188E_PHY_RADIO_B;
|
||||
int rtStatus = _SUCCESS;
|
||||
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
|
||||
static char sz88eRadioAFile[] = RTL8188E_PHY_RADIO_A;
|
||||
static char sz88eRadioBFile[] = RTL8188E_PHY_RADIO_B;
|
||||
|
||||
/* 3----------------------------------------------------------------- */
|
||||
/* 3 <2> Initialize RF */
|
||||
/* 3----------------------------------------------------------------- */
|
||||
for (eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
|
||||
{
|
||||
|
||||
for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
|
||||
pPhyReg = &pHalData->PHYRegDef[eRFPath];
|
||||
|
||||
/*----Store original RFENV control type----*/
|
||||
|
|
@ -589,12 +506,11 @@ phy_RF6052_Config_ParaFile(
|
|||
case RF_PATH_C:
|
||||
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
|
||||
break;
|
||||
case RF_PATH_B :
|
||||
case RF_PATH_B:
|
||||
case RF_PATH_D:
|
||||
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
|
||||
break;
|
||||
}
|
||||
|
||||
/*----Set RF_ENV enable----*/
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
|
||||
rtw_udelay_os(1);/* PlatformStallExecution(1); */
|
||||
|
|
@ -613,50 +529,42 @@ phy_RF6052_Config_ParaFile(
|
|||
/*----Initialize RF fom connfiguration file----*/
|
||||
switch (eRFPath) {
|
||||
case RF_PATH_A:
|
||||
if (HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(enum ODM_RF_RADIO_PATH)eRFPath, (enum ODM_RF_RADIO_PATH)eRFPath))
|
||||
rtStatus= _FAIL;
|
||||
if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, (enum ODM_RF_RADIO_PATH)eRFPath, (enum ODM_RF_RADIO_PATH)eRFPath))
|
||||
rtStatus = _FAIL;
|
||||
break;
|
||||
case RF_PATH_B:
|
||||
if (HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(enum ODM_RF_RADIO_PATH)eRFPath, (enum ODM_RF_RADIO_PATH)eRFPath))
|
||||
rtStatus= _FAIL;
|
||||
if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, (enum ODM_RF_RADIO_PATH)eRFPath, (enum ODM_RF_RADIO_PATH)eRFPath))
|
||||
rtStatus = _FAIL;
|
||||
break;
|
||||
case RF_PATH_C:
|
||||
break;
|
||||
case RF_PATH_D:
|
||||
break;
|
||||
}
|
||||
|
||||
/*----Restore RFENV control type----*/;
|
||||
switch (eRFPath)
|
||||
{
|
||||
switch (eRFPath) {
|
||||
case RF_PATH_A:
|
||||
case RF_PATH_C:
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
|
||||
break;
|
||||
case RF_PATH_B :
|
||||
case RF_PATH_B:
|
||||
case RF_PATH_D:
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
|
||||
break;
|
||||
}
|
||||
|
||||
if (rtStatus != _SUCCESS)
|
||||
goto phy_RF6052_Config_ParaFile_Fail;
|
||||
|
||||
}
|
||||
|
||||
return rtStatus;
|
||||
|
||||
phy_RF6052_Config_ParaFile_Fail:
|
||||
return rtStatus;
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
PHY_RF6052_Config8188E(
|
||||
struct adapter * Adapter)
|
||||
int PHY_RF6052_Config8188E(struct adapter *Adapter)
|
||||
{
|
||||
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
|
||||
int rtStatus = _SUCCESS;
|
||||
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
|
||||
int rtStatus = _SUCCESS;
|
||||
|
||||
/* */
|
||||
/* Initialize general global value */
|
||||
|
|
@ -673,5 +581,3 @@ PHY_RF6052_Config8188E(
|
|||
rtStatus = phy_RF6052_Config_ParaFile(Adapter);
|
||||
return rtStatus;
|
||||
}
|
||||
|
||||
/* End of HalRf6052.c */
|
||||
|
|
|
|||
Loading…
Reference in a new issue