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rtl8188eu: Fix checkpatch errors in hal/rtl8188e_mp.c, hal/rtl8188e_phycfg.c, and hal/rtl8188e_rf6052.c

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2013-08-08 09:31:29 -05:00
parent 9c3c9ddc8c
commit f527ca59c9
3 changed files with 709 additions and 1013 deletions
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192
hal/rtl8188e_mp.c
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@ -21,11 +21,9 @@
#include <drv_types.h> #include <drv_types.h>
#include <rtw_mp.h> #include <rtw_mp.h>
#include <rtl8188e_hal.h> #include <rtl8188e_hal.h>
#include <rtl8188e_dm.h> #include <rtl8188e_dm.h>
s32 Hal_SetPowerTracking(struct adapter *padapter, u8 enable) s32 Hal_SetPowerTracking(struct adapter *padapter, u8 enable)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
@ -35,19 +33,19 @@ s32 Hal_SetPowerTracking(struct adapter * padapter, u8 enable)
if (!netif_running(padapter->pnetdev)) { if (!netif_running(padapter->pnetdev)) {
RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: interface not opened!\n")); RT_TRACE(_module_mp_, _drv_warning_,
("SetPowerTracking! Fail: interface not opened!\n"));
return _FAIL; return _FAIL;
} }
if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == false) { if (!check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE)) {
RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: not in MP mode!\n")); RT_TRACE(_module_mp_, _drv_warning_,
("SetPowerTracking! Fail: not in MP mode!\n"));
return _FAIL; return _FAIL;
} }
if (enable) if (enable)
{
pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true; pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true;
}
else else
pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = false; pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = false;
@ -135,19 +133,15 @@ void Hal_MPT_CCKTxPowerAdjust(struct adapter * Adapter, bool bInCH14)
u8 i; u8 i;
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
/* get current cck swing value and check 0xa22 & 0xa23 later to match the table. */ /* get current cck swing value and check 0xa22 & 0xa23 later to match the table. */
CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord); CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
if (!bInCH14) if (!bInCH14) {
{
/* Readback the current bb cck swing value and compare with the table to */ /* Readback the current bb cck swing value and compare with the table to */
/* get the current swing index */ /* get the current swing index */
for (i = 0; i < CCK_TABLE_SIZE; i++) for (i = 0; i < CCK_TABLE_SIZE; i++) {
{
if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) && if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&
(((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1])) (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1])) {
{
CCKSwingIndex = i; CCKSwingIndex = i;
break; break;
} }
@ -169,14 +163,10 @@ void Hal_MPT_CCKTxPowerAdjust(struct adapter * Adapter, bool bInCH14)
TempVal3 = 0; TempVal3 = 0;
TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] + TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +
(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8); (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8);
} } else {
else for (i = 0; i < CCK_TABLE_SIZE; i++) {
{
for (i = 0; i < CCK_TABLE_SIZE; i++)
{
if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch14[i][0]) && if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch14[i][0]) &&
(((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1])) (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1])) {
{
CCKSwingIndex = i; CCKSwingIndex = i;
break; break;
} }
@ -220,35 +210,27 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(struct adapter * pAdapter, bool beven)
if (!IS_92C_SERIAL(pHalData->VersionID)) if (!IS_92C_SERIAL(pHalData->VersionID))
return; return;
if (beven && !pMptCtx->bMptIndexEven) /* odd->even */ if (beven && !pMptCtx->bMptIndexEven) {
{ /* odd->even */
Action = 2; Action = 2;
pMptCtx->bMptIndexEven = true; pMptCtx->bMptIndexEven = true;
} } else if (!beven && pMptCtx->bMptIndexEven) {
else if (!beven && pMptCtx->bMptIndexEven) /* even->odd */ /* even->odd */
{
Action = 1; Action = 1;
pMptCtx->bMptIndexEven = false; pMptCtx->bMptIndexEven = false;
} }
if (Action != 0) if (Action != 0) {
{
/* Query CCK default setting From 0xa24 */ /* Query CCK default setting From 0xa24 */
TempCCk = read_bbreg(pAdapter, rCCK0_TxFilter2, bMaskDWord) & bMaskCCK; TempCCk = read_bbreg(pAdapter, rCCK0_TxFilter2, bMaskDWord) & bMaskCCK;
for (i = 0; i < CCK_TABLE_SIZE; i++) for (i = 0; i < CCK_TABLE_SIZE; i++) {
{ if (pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
if (pDM_Odm->RFCalibrateInfo.bCCKinCH14) if (_rtw_memcmp((void *)&TempCCk, (void *)&CCKSwingTable_Ch14[i][2], 4)) {
{
if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4) == true)
{
CCK_index_old = (u8)i; CCK_index_old = (u8)i;
break; break;
} }
} } else {
else if (_rtw_memcmp((void *)&TempCCk, (void *)&CCKSwingTable_Ch1_Ch13[i][2], 4)) {
{
if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4) == true)
{
CCK_index_old = (u8)i; CCK_index_old = (u8)i;
break; break;
} }
@ -305,8 +287,7 @@ void Hal_SetChannel(struct adapter * pAdapter)
/* set RF channel register */ /* set RF channel register */
for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
{
if (IS_HARDWARE_TYPE_8192D(pAdapter)) if (IS_HARDWARE_TYPE_8192D(pAdapter))
_write_rfreg(pAdapter, (enum rf_radio_path)eRFPath, ODM_CHANNEL, 0xFF, channel); _write_rfreg(pAdapter, (enum rf_radio_path)eRFPath, ODM_CHANNEL, 0xFF, channel);
else else
@ -319,8 +300,7 @@ void Hal_SetChannel(struct adapter * pAdapter)
if (pHalData->CurrentChannel == 14 && !pDM_Odm->RFCalibrateInfo.bCCKinCH14) { if (pHalData->CurrentChannel == 14 && !pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
pDM_Odm->RFCalibrateInfo.bCCKinCH14 = true; pDM_Odm->RFCalibrateInfo.bCCKinCH14 = true;
Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14); Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14);
} } else if (pHalData->CurrentChannel != 14 && pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
else if (pHalData->CurrentChannel != 14 && pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
pDM_Odm->RFCalibrateInfo.bCCKinCH14 = false; pDM_Odm->RFCalibrateInfo.bCCKinCH14 = false;
Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14); Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14);
} }
@ -388,7 +368,6 @@ void Hal_SetOFDMTxPower(struct adapter * pAdapter, u8 *TxPower)
write_bbreg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC); write_bbreg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
write_bbreg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC); write_bbreg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
write_bbreg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC); write_bbreg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
} }
void Hal_SetAntennaPathPower(struct adapter *pAdapter) void Hal_SetAntennaPathPower(struct adapter *pAdapter)
@ -400,8 +379,7 @@ void Hal_SetAntennaPathPower(struct adapter * pAdapter)
TxPowerLevel[RF_PATH_A] = pAdapter->mppriv.txpoweridx; TxPowerLevel[RF_PATH_A] = pAdapter->mppriv.txpoweridx;
TxPowerLevel[RF_PATH_B] = pAdapter->mppriv.txpoweridx_b; TxPowerLevel[RF_PATH_B] = pAdapter->mppriv.txpoweridx_b;
switch (pAdapter->mppriv.antenna_tx) switch (pAdapter->mppriv.antenna_tx) {
{
case ANTENNA_A: case ANTENNA_A:
default: default:
rfPath = RF_PATH_A; rfPath = RF_PATH_A;
@ -414,8 +392,7 @@ void Hal_SetAntennaPathPower(struct adapter * pAdapter)
break; break;
} }
switch (pHalData->rf_chip) switch (pHalData->rf_chip) {
{
case RF_8225: case RF_8225:
case RF_8256: case RF_8256:
case RF_6052: case RF_6052:
@ -424,7 +401,6 @@ void Hal_SetAntennaPathPower(struct adapter * pAdapter)
Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0); Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);
Hal_SetOFDMTxPower(pAdapter, TxPowerLevel); Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
break; break;
default: default:
break; break;
} }
@ -437,12 +413,10 @@ void Hal_SetTxPower(struct adapter * pAdapter)
u8 TxPowerLevel[MAX_RF_PATH_NUMS]; u8 TxPowerLevel[MAX_RF_PATH_NUMS];
u8 rf, rfPath; u8 rf, rfPath;
for (rf = 0; rf < MAX_RF_PATH_NUMS; rf++) { for (rf = 0; rf < MAX_RF_PATH_NUMS; rf++)
TxPowerLevel[rf] = TxPower; TxPowerLevel[rf] = TxPower;
}
switch (pAdapter->mppriv.antenna_tx) switch (pAdapter->mppriv.antenna_tx) {
{
case ANTENNA_A: case ANTENNA_A:
default: default:
rfPath = RF_PATH_A; rfPath = RF_PATH_A;
@ -455,8 +429,7 @@ void Hal_SetTxPower(struct adapter * pAdapter)
break; break;
} }
switch (pHalData->rf_chip) switch (pHalData->rf_chip) {
{
/* 2008/09/12 MH Test only !! We enable the TX power tracking for MP!!!!! */ /* 2008/09/12 MH Test only !! We enable the TX power tracking for MP!!!!! */
/* We should call normal driver API later!! */ /* We should call normal driver API later!! */
case RF_8225: case RF_8225:
@ -467,7 +440,6 @@ void Hal_SetTxPower(struct adapter * pAdapter)
Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0); Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);
Hal_SetOFDMTxPower(pAdapter, TxPowerLevel); Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
break; break;
default: default:
break; break;
} }
@ -484,7 +456,6 @@ void Hal_SetAntenna(struct adapter * pAdapter)
struct ant_sel_ofdm *p_ofdm_tx; /* OFDM Tx register */ struct ant_sel_ofdm *p_ofdm_tx; /* OFDM Tx register */
struct ant_sel_cck *p_cck_txrx; struct ant_sel_cck *p_cck_txrx;
u8 r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0; u8 r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
u8 chgTx = 0, chgRx = 0; u8 chgTx = 0, chgRx = 0;
u32 r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0; u32 r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
@ -497,8 +468,7 @@ void Hal_SetAntenna(struct adapter * pAdapter)
p_ofdm_tx->r_ant_ht2 = 0x2; /* Second TX RF path is A */ p_ofdm_tx->r_ant_ht2 = 0x2; /* Second TX RF path is A */
p_ofdm_tx->r_ant_non_ht = 0x3; /* 0x1+0x2=0x3 */ p_ofdm_tx->r_ant_non_ht = 0x3; /* 0x1+0x2=0x3 */
switch (pAdapter->mppriv.antenna_tx) switch (pAdapter->mppriv.antenna_tx) {
{
case ANTENNA_A: case ANTENNA_A:
p_ofdm_tx->r_tx_antenna = 0x1; p_ofdm_tx->r_tx_antenna = 0x1;
r_ofdm_tx_en_val = 0x1; r_ofdm_tx_en_val = 0x1;
@ -514,11 +484,9 @@ void Hal_SetAntenna(struct adapter * pAdapter)
r_ofdm_tx_en_val = 0x3; r_ofdm_tx_en_val = 0x3;
/* Power save */ /* Power save */
/* cosa r_ant_select_ofdm_val = 0x11111111; */
/* We need to close RFB by SW control */ /* We need to close RFB by SW control */
if (pHalData->rf_type == RF_2T2R) if (pHalData->rf_type == RF_2T2R) {
{
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0); PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1); PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0); PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
@ -526,7 +494,6 @@ void Hal_SetAntenna(struct adapter * pAdapter)
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0); PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
} }
break; break;
case ANTENNA_B: case ANTENNA_B:
p_ofdm_tx->r_tx_antenna = 0x2; p_ofdm_tx->r_tx_antenna = 0x2;
r_ofdm_tx_en_val = 0x2; r_ofdm_tx_en_val = 0x2;
@ -535,7 +502,6 @@ void Hal_SetAntenna(struct adapter * pAdapter)
p_ofdm_tx->r_ant_non_ht_s1 = 0x2; p_ofdm_tx->r_ant_non_ht_s1 = 0x2;
p_cck_txrx->r_ccktx_enable = 0x4; p_cck_txrx->r_ccktx_enable = 0x4;
chgTx = 1; chgTx = 1;
/* From SD3 Willis suggestion !!! Set RF A as standby */ /* From SD3 Willis suggestion !!! Set RF A as standby */
PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1); PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2); PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
@ -545,8 +511,7 @@ void Hal_SetAntenna(struct adapter * pAdapter)
/* 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table. */ /* 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table. */
/* 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control */ /* 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control */
if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
{
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1); PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0); PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0); PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
@ -554,7 +519,6 @@ void Hal_SetAntenna(struct adapter * pAdapter)
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1); PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
} }
break; break;
case ANTENNA_AB: /* For 8192S */ case ANTENNA_AB: /* For 8192S */
p_ofdm_tx->r_tx_antenna = 0x3; p_ofdm_tx->r_tx_antenna = 0x3;
r_ofdm_tx_en_val = 0x3; r_ofdm_tx_en_val = 0x3;
@ -571,8 +535,7 @@ void Hal_SetAntenna(struct adapter * pAdapter)
/* Disable Power save */ /* Disable Power save */
/* cosa r_ant_select_ofdm_val = 0x3321333; */ /* cosa r_ant_select_ofdm_val = 0x3321333; */
/* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control */ /* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control */
if (pHalData->rf_type == RF_2T2R) if (pHalData->rf_type == RF_2T2R) {
{
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0); PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0); PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1); PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
@ -583,42 +546,34 @@ void Hal_SetAntenna(struct adapter * pAdapter)
break; break;
} }
/* */
/* r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */ /* r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
/* r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */ /* r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
/* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D */ /* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D */
/* */ switch (pAdapter->mppriv.antenna_rx) {
switch (pAdapter->mppriv.antenna_rx)
{
case ANTENNA_A: case ANTENNA_A:
r_rx_antenna_ofdm = 0x1; /* A */ r_rx_antenna_ofdm = 0x1; /* A */
p_cck_txrx->r_cckrx_enable = 0x0; /* default: A */ p_cck_txrx->r_cckrx_enable = 0x0; /* default: A */
p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A */ p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A */
chgRx = 1; chgRx = 1;
break; break;
case ANTENNA_B: case ANTENNA_B:
r_rx_antenna_ofdm = 0x2; /* B */ r_rx_antenna_ofdm = 0x2; /* B */
p_cck_txrx->r_cckrx_enable = 0x1; /* default: B */ p_cck_txrx->r_cckrx_enable = 0x1; /* default: B */
p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option: B */ p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option: B */
chgRx = 1; chgRx = 1;
break; break;
case ANTENNA_AB: case ANTENNA_AB:
r_rx_antenna_ofdm = 0x3; /* AB */ r_rx_antenna_ofdm = 0x3; /* AB */
p_cck_txrx->r_cckrx_enable = 0x0; /* default:A */ p_cck_txrx->r_cckrx_enable = 0x0; /* default:A */
p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option:B */ p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option:B */
chgRx = 1; chgRx = 1;
break; break;
default: default:
break; break;
} }
if (chgTx && chgRx) if (chgTx && chgRx) {
{ switch (pHalData->rf_chip) {
switch (pHalData->rf_chip)
{
case RF_8225: case RF_8225:
case RF_8256: case RF_8256:
case RF_6052: case RF_6052:
@ -630,7 +585,6 @@ void Hal_SetAntenna(struct adapter * pAdapter)
PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val); /* CCK TxRx */ PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val); /* CCK TxRx */
break; break;
default: default:
break; break;
} }
@ -667,7 +621,6 @@ s32 Hal_SetThermalMeter(struct adapter * pAdapter, u8 target_ther)
void Hal_TriggerRFThermalMeter(struct adapter *pAdapter) void Hal_TriggerRFThermalMeter(struct adapter *pAdapter)
{ {
_write_rfreg(pAdapter, RF_PATH_A , RF_T_METER_88E , BIT17 | BIT16 , 0x03); _write_rfreg(pAdapter, RF_PATH_A , RF_T_METER_88E , BIT17 | BIT16 , 0x03);
} }
@ -689,20 +642,19 @@ void Hal_GetThermalMeter(struct adapter * pAdapter, u8 *value)
void Hal_SetSingleCarrierTx(struct adapter *pAdapter, u8 bStart) void Hal_SetSingleCarrierTx(struct adapter *pAdapter, u8 bStart)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
pAdapter->mppriv.MptCtx.bSingleCarrier = bStart; pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;
if (bStart)/* Start Single Carrier. */ if (bStart) {
{ /* Start Single Carrier. */
RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleCarrierTx: test start\n")); RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleCarrierTx: test start\n"));
/* 1. if OFDM block on? */ /* 1. if OFDM block on? */
if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);/* set OFDM block on */ write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);/* set OFDM block on */
{
/* 2. set CCK test mode off, set to CCK normal mode */ /* 2. set CCK test mode off, set to CCK normal mode */
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable); write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
/* 3. turn on scramble setting */ /* 3. turn on scramble setting */
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
}
/* 4. Turn On Single Carrier Tx and turn off the other test modes. */ /* 4. Turn On Single Carrier Tx and turn off the other test modes. */
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable); write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);
@ -710,10 +662,8 @@ void Hal_SetSingleCarrierTx(struct adapter * pAdapter, u8 bStart)
/* for dynamic set Power index. */ /* for dynamic set Power index. */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
} else {
} /* Stop Single Carrier. */
else/* Stop Single Carrier. */
{
RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleCarrierTx: test stop\n")); RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleCarrierTx: test stop\n"));
/* Turn off all test modes. */ /* Turn off all test modes. */
@ -729,7 +679,6 @@ void Hal_SetSingleCarrierTx(struct adapter * pAdapter, u8 bStart)
/* Stop for dynamic set Power index. */ /* Stop for dynamic set Power index. */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
} }
} }
@ -741,8 +690,7 @@ void Hal_SetSingleToneTx(struct adapter * pAdapter, u8 bStart)
u8 rfPath; u8 rfPath;
u32 reg58 = 0x0; u32 reg58 = 0x0;
switch (pAdapter->mppriv.antenna_tx) switch (pAdapter->mppriv.antenna_tx) {
{
case ANTENNA_A: case ANTENNA_A:
default: default:
rfPath = RF_PATH_A; rfPath = RF_PATH_A;
@ -756,12 +704,11 @@ void Hal_SetSingleToneTx(struct adapter * pAdapter, u8 bStart)
} }
pAdapter->mppriv.MptCtx.bSingleTone = bStart; pAdapter->mppriv.MptCtx.bSingleTone = bStart;
if (bStart)/* Start Single Tone. */ if (bStart) {
{ /* Start Single Tone. */
RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleToneTx: test start\n")); RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleToneTx: test start\n"));
{ /* <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu) */ /* <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu) */
if (IS_HARDWARE_TYPE_8188E(pAdapter)) if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
{
reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask); reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask);
reg58 &= 0xFFFFFFF0; reg58 &= 0xFFFFFFF0;
reg58 += 2; reg58 += 2;
@ -769,10 +716,8 @@ void Hal_SetSingleToneTx(struct adapter * pAdapter, u8 bStart)
} }
PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0); PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0); PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
}
if (is92C) if (is92C) {
{
_write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x01); _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x01);
rtw_usleep_os(100); rtw_usleep_os(100);
if (rfPath == RF_PATH_A) if (rfPath == RF_PATH_A)
@ -781,9 +726,7 @@ void Hal_SetSingleToneTx(struct adapter * pAdapter, u8 bStart)
write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x10000); /* PAD all on. */ write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x10000); /* PAD all on. */
write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); /* PAD all on. */ write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); /* PAD all on. */
rtw_usleep_os(100); rtw_usleep_os(100);
} } else {
else
{
write_rfreg(pAdapter, rfPath, 0x21, 0xd4000); write_rfreg(pAdapter, rfPath, 0x21, 0xd4000);
rtw_usleep_os(100); rtw_usleep_os(100);
write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); /* PAD all on. */ write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); /* PAD all on. */
@ -794,23 +737,19 @@ void Hal_SetSingleToneTx(struct adapter * pAdapter, u8 bStart)
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
} } else {
else/* Stop Single Tone. */ /* Stop Single Tone. */
{
RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleToneTx: test stop\n")); RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleToneTx: test stop\n"));
{ /* <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu) */ /* <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu) */
/* <20120326, Kordan> Only in single tone mode. (asked by Edlu) */ /* <20120326, Kordan> Only in single tone mode. (asked by Edlu) */
if (IS_HARDWARE_TYPE_8188E(pAdapter)) if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
{
reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask); reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask);
reg58 &= 0xFFFFFFF0; reg58 &= 0xFFFFFFF0;
PHY_SetRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, reg58); PHY_SetRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, reg58);
} }
write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1); write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1); write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
}
if (is92C) { if (is92C) {
_write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x00); _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x00);
rtw_usleep_os(100); rtw_usleep_os(100);
@ -827,9 +766,7 @@ void Hal_SetSingleToneTx(struct adapter * pAdapter, u8 bStart)
/* Stop for dynamic set Power index. */ /* Stop for dynamic set Power index. */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
} }
} }
@ -837,11 +774,10 @@ void Hal_SetSingleToneTx(struct adapter * pAdapter, u8 bStart)
void Hal_SetCarrierSuppressionTx(struct adapter *pAdapter, u8 bStart) void Hal_SetCarrierSuppressionTx(struct adapter *pAdapter, u8 bStart)
{ {
pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart; pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;
if (bStart) /* Start Carrier Suppression. */ if (bStart) {
{ /* Start Carrier Suppression. */
RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test start\n")); RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test start\n"));
if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) {
{
/* 1. if CCK block on? */ /* 1. if CCK block on? */
if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn)) if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/* set CCK block on */ write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/* set CCK block on */
@ -861,10 +797,8 @@ void Hal_SetCarrierSuppressionTx(struct adapter * pAdapter, u8 bStart)
/* for dynamic set Power index. */ /* for dynamic set Power index. */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
} else {
} /* Stop Carrier Suppression. */
else/* Stop Carrier Suppression. */
{
RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test stop\n")); RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test stop\n"));
if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) { if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) {
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /* normal mode */ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /* normal mode */
@ -878,7 +812,6 @@ void Hal_SetCarrierSuppressionTx(struct adapter * pAdapter, u8 bStart)
/* Stop for dynamic set Power index. */ /* Stop for dynamic set Power index. */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
} }
} }
@ -886,8 +819,7 @@ void Hal_SetCCKContinuousTx(struct adapter * pAdapter, u8 bStart)
{ {
u32 cckrate; u32 cckrate;
if (bStart) if (bStart) {
{
RT_TRACE(_module_mp_, _drv_alert_, RT_TRACE(_module_mp_, _drv_alert_,
("SetCCKContinuousTx: test start\n")); ("SetCCKContinuousTx: test start\n"));
@ -908,9 +840,7 @@ void Hal_SetCCKContinuousTx(struct adapter * pAdapter, u8 bStart)
/* for dynamic set Power index. */ /* for dynamic set Power index. */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
} else {
}
else {
RT_TRACE(_module_mp_, _drv_info_, RT_TRACE(_module_mp_, _drv_info_,
("SetCCKContinuousTx: test stop\n")); ("SetCCKContinuousTx: test stop\n"));
@ -939,14 +869,12 @@ void Hal_SetOFDMContinuousTx(struct adapter * pAdapter, u8 bStart)
/* 1. if OFDM block on? */ /* 1. if OFDM block on? */
if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);/* set OFDM block on */ write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);/* set OFDM block on */
{
/* 2. set CCK test mode off, set to CCK normal mode */ /* 2. set CCK test mode off, set to CCK normal mode */
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable); write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
/* 3. turn on scramble setting */ /* 3. turn on scramble setting */
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
}
/* 4. Turn On Continue Tx and turn off the other test modes. */ /* 4. Turn On Continue Tx and turn off the other test modes. */
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable); write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
@ -983,12 +911,8 @@ void Hal_SetContinuousTx(struct adapter * pAdapter, u8 bStart)
pAdapter->mppriv.MptCtx.bStartContTx = bStart; pAdapter->mppriv.MptCtx.bStartContTx = bStart;
if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)
{
Hal_SetCCKContinuousTx(pAdapter, bStart); Hal_SetCCKContinuousTx(pAdapter, bStart);
}
else if ((pAdapter->mppriv.rateidx >= MPT_RATE_6M) && else if ((pAdapter->mppriv.rateidx >= MPT_RATE_6M) &&
(pAdapter->mppriv.rateidx <= MPT_RATE_MCS15)) (pAdapter->mppriv.rateidx <= MPT_RATE_MCS15))
{
Hal_SetOFDMContinuousTx(pAdapter, bStart); Hal_SetOFDMContinuousTx(pAdapter, bStart);
} }
}

222
hal/rtl8188e_phycfg.c
View file

@ -60,20 +60,15 @@
* Output: none * Output: none
* Return: u4Byte Return the shift bit bit position of the mask * Return: u4Byte Return the shift bit bit position of the mask
*/ */
static u32 static u32 phy_CalculateBitShift(u32 BitMask)
phy_CalculateBitShift(
u32 BitMask
)
{ {
u32 i; u32 i;
for (i=0; i<=31; i++) for (i = 0; i <= 31; i++) {
{
if (((BitMask>>i) & 0x1) == 1) if (((BitMask>>i) & 0x1) == 1)
break; break;
} }
return i;
return (i);
} }
/** /**
@ -103,7 +98,7 @@ rtl8188e_PHY_QueryBBReg(
OriginalValue = rtw_read32(Adapter, RegAddr); OriginalValue = rtw_read32(Adapter, RegAddr);
BitShift = phy_CalculateBitShift(BitMask); BitShift = phy_CalculateBitShift(BitMask);
ReturnValue = (OriginalValue & BitMask) >> BitShift; ReturnValue = (OriginalValue & BitMask) >> BitShift;
return (ReturnValue); return ReturnValue;
} }
@ -125,13 +120,7 @@ rtl8188e_PHY_QueryBBReg(
* Note: This function is equal to "PutRegSetting" in PHY programming guide * Note: This function is equal to "PutRegSetting" in PHY programming guide
*/ */
void void rtl8188e_PHY_SetBBReg(struct adapter *Adapter, u32 RegAddr, u32 BitMask, u32 Data)
rtl8188e_PHY_SetBBReg(
struct adapter * Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data
)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
u32 OriginalValue, BitShift; u32 OriginalValue, BitShift;
@ -215,15 +204,11 @@ phy_RFSerialRead(
else if (eRFPath == RF_PATH_B) else if (eRFPath == RF_PATH_B)
RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1, BIT8); RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1, BIT8);
if (RfPiEnable) if (RfPiEnable) { /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
{ /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData); retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);
} } else { /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
else
{ /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
} }
return retValue; return retValue;
} }
@ -329,7 +314,7 @@ u32 rtl8188e_PHY_QueryRFReg(struct adapter * Adapter, enum rf_radio_path eRFPath
BitShift = phy_CalculateBitShift(BitMask); BitShift = phy_CalculateBitShift(BitMask);
Readback_Value = (Original_Value & BitMask) >> BitShift; Readback_Value = (Original_Value & BitMask) >> BitShift;
return (Readback_Value); return Readback_Value;
} }
/** /**
@ -362,8 +347,7 @@ rtl8188e_PHY_SetRFReg(
u32 Original_Value, BitShift; u32 Original_Value, BitShift;
/* RF data is 12 bits only */ /* RF data is 12 bits only */
if (BitMask != bRFRegOffsetMask) if (BitMask != bRFRegOffsetMask) {
{
Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr); Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);
BitShift = phy_CalculateBitShift(BitMask); BitShift = phy_CalculateBitShift(BitMask);
Data = ((Original_Value & (~BitMask)) | (Data << BitShift)); Data = ((Original_Value & (~BitMask)) | (Data << BitShift));
@ -392,11 +376,7 @@ rtl8188e_PHY_SetRFReg(
* Note: The format of MACPHY_REG.txt is different from PHY and RF. * Note: The format of MACPHY_REG.txt is different from PHY and RF.
* [Register][Mask][Value] * [Register][Mask][Value]
*---------------------------------------------------------------------------*/ *---------------------------------------------------------------------------*/
static int static int phy_ConfigMACWithParaFile(struct adapter *Adapter, u8 *pFileName)
phy_ConfigMACWithParaFile(
struct adapter * Adapter,
u8* pFileName
)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
@ -571,44 +551,17 @@ phy_InitBBRFRegisterDefinition(
* parameter file compare!!!!!!?? * parameter file compare!!!!!!??
* *
*---------------------------------------------------------------------------*/ *---------------------------------------------------------------------------*/
static int static int phy_ConfigBBWithParaFile(struct adapter *Adapter, u8 *pFileName)
phy_ConfigBBWithParaFile(
struct adapter * Adapter,
u8* pFileName
)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); return _SUCCESS;
int rtStatus = _SUCCESS;
return rtStatus;
} }
/* */
/* The following is for High Power PA */ /* The following is for High Power PA */
/* */
static void phy_ConfigBBExternalPA(struct adapter *Adapter) static void phy_ConfigBBExternalPA(struct adapter *Adapter)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
u16 i=0;
u32 temp=0;
if (!pHalData->ExternalPA)
return;
/* 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the */
/* same code as SU. It is already updated in PHY_REG_1T_HP.txt. */
} }
void void storePwrIndexDiffRateOffset(struct adapter *Adapter, u32 RegAddr, u32 BitMask, u32 Data)
storePwrIndexDiffRateOffset(
struct adapter * Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data
)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
@ -667,24 +620,12 @@ storePwrIndexDiffRateOffset(
* 11/06/2008 MHC Create Version 0. * 11/06/2008 MHC Create Version 0.
* 2009/07/29 tynli (porting from 92SE branch)2009/03/11 Add copy parameter file to buffer for silent reset * 2009/07/29 tynli (porting from 92SE branch)2009/03/11 Add copy parameter file to buffer for silent reset
*---------------------------------------------------------------------------*/ *---------------------------------------------------------------------------*/
static int static int phy_ConfigBBWithPgParaFile(struct adapter *Adapter, u8 *pFileName)
phy_ConfigBBWithPgParaFile(
struct adapter * Adapter,
u8* pFileName)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); return _SUCCESS;
}
int rtStatus = _SUCCESS; static void phy_BB8192C_Config_1T(struct adapter *Adapter)
return rtStatus;
} /* phy_ConfigBBWithPgParaFile */
static void
phy_BB8192C_Config_1T(
struct adapter * Adapter
)
{ {
/* for path - B */ /* for path - B */
PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x2); PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x2);
@ -738,11 +679,8 @@ phy_BB8188E_Config_ParaFile(
if (rtStatus != _SUCCESS) if (rtStatus != _SUCCESS)
goto phy_BB8190_Config_ParaFile_Fail; goto phy_BB8190_Config_ParaFile_Fail;
/* */
/* 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */ /* 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */
/* */ if (!pEEPROM->bautoload_fail_flag) {
if (pEEPROM->bautoload_fail_flag == false)
{
pHalData->pwrGroupCnt = 0; pHalData->pwrGroupCnt = 0;
if (HAL_STATUS_FAILURE == ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_PG)) if (HAL_STATUS_FAILURE == ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_PG))
@ -752,9 +690,7 @@ phy_BB8188E_Config_ParaFile(
if (rtStatus != _SUCCESS) if (rtStatus != _SUCCESS)
goto phy_BB8190_Config_ParaFile_Fail; goto phy_BB8190_Config_ParaFile_Fail;
/* */
/* 3. BB AGC table Initialization */ /* 3. BB AGC table Initialization */
/* */
if (HAL_STATUS_FAILURE == ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB)) if (HAL_STATUS_FAILURE == ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
rtStatus = _FAIL; rtStatus = _FAIL;
@ -790,9 +726,7 @@ PHY_BBConfig8188E(
rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB); rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
/* */
/* Config BB and AGC */ /* Config BB and AGC */
/* */
rtStatus = phy_BB8188E_Config_ParaFile(Adapter); rtStatus = phy_BB8188E_Config_ParaFile(Adapter);
/* write 0x24[16:11] = 0x24[22:17] = CrystalCap */ /* write 0x24[16:11] = 0x24[22:17] = CrystalCap */
@ -802,17 +736,12 @@ PHY_BBConfig8188E(
return rtStatus; return rtStatus;
} }
int int PHY_RFConfig8188E(struct adapter *Adapter)
PHY_RFConfig8188E(
struct adapter * Adapter
)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
int rtStatus = _SUCCESS; int rtStatus = _SUCCESS;
/* */
/* RF config */ /* RF config */
/* */
rtStatus = PHY_RF6052_Config8188E(Adapter); rtStatus = PHY_RF6052_Config8188E(Adapter);
return rtStatus; return rtStatus;
} }
@ -833,28 +762,14 @@ PHY_RFConfig8188E(
* *
* Note: Delay may be required for RF configuration * Note: Delay may be required for RF configuration
*---------------------------------------------------------------------------*/ *---------------------------------------------------------------------------*/
int int rtl8188e_PHY_ConfigRFWithParaFile(struct adapter *Adapter, u8 *pFileName, enum rf_radio_path eRFPath)
rtl8188e_PHY_ConfigRFWithParaFile(
struct adapter * Adapter,
u8* pFileName,
enum rf_radio_path eRFPath
)
{ {
return _SUCCESS; return _SUCCESS;
} }
static int PHY_ConfigRFExternalPA(struct adapter *Adapter, enum rf_radio_path eRFPath) static int PHY_ConfigRFExternalPA(struct adapter *Adapter, enum rf_radio_path eRFPath)
{ {
int rtStatus = _SUCCESS; return _SUCCESS;
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
u16 i=0;
if (!pHalData->ExternalPA)
return rtStatus;
/* 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the */
/* same code as SU. It is already updated in radio_a_1T_HP.txt. */
return rtStatus;
} }
void void
@ -882,12 +797,7 @@ rtl8192c_PHY_GetHWRegOriginalValue(
/* current wireless mode. */ /* current wireless mode. */
/* By Bruce, 2008-01-29. */ /* By Bruce, 2008-01-29. */
/* */ /* */
static u8 static u8 phy_DbmToTxPwrIdx(struct adapter *Adapter, enum wireless_mode WirelessMode, int PowerInDbm)
phy_DbmToTxPwrIdx(
struct adapter * Adapter,
enum wireless_mode WirelessMode,
int PowerInDbm
)
{ {
u8 TxPwrIdx = 0; u8 TxPwrIdx = 0;
int Offset = 0; int Offset = 0;
@ -900,16 +810,13 @@ phy_DbmToTxPwrIdx(
/* The mapping may be different by different NICs. Do not use this formula for what needs accurate result. */ /* The mapping may be different by different NICs. Do not use this formula for what needs accurate result. */
/* By Bruce, 2008-01-29. */ /* By Bruce, 2008-01-29. */
/* */ /* */
switch (WirelessMode) switch (WirelessMode) {
{
case WIRELESS_MODE_B: case WIRELESS_MODE_B:
Offset = -7; Offset = -7;
break; break;
case WIRELESS_MODE_G: case WIRELESS_MODE_G:
case WIRELESS_MODE_N_24G: case WIRELESS_MODE_N_24G:
Offset = -8;
break;
default: default:
Offset = -8; Offset = -8;
break; break;
@ -945,15 +852,12 @@ static int phy_TxPwrIdxToDbm(struct adapter * Adapter, enum wireless_mode Wirele
/* The mapping may be different by different NICs. Do not use this formula for what needs accurate result. */ /* The mapping may be different by different NICs. Do not use this formula for what needs accurate result. */
/* By Bruce, 2008-01-29. */ /* By Bruce, 2008-01-29. */
/* */ /* */
switch (WirelessMode) switch (WirelessMode) {
{
case WIRELESS_MODE_B: case WIRELESS_MODE_B:
Offset = -7; Offset = -7;
break; break;
case WIRELESS_MODE_G: case WIRELESS_MODE_G:
case WIRELESS_MODE_N_24G: case WIRELESS_MODE_N_24G:
Offset = -8;
default: default:
Offset = -8; Offset = -8;
break; break;
@ -978,11 +882,7 @@ static int phy_TxPwrIdxToDbm(struct adapter * Adapter, enum wireless_mode Wirele
* Return: NONE * Return: NONE
* *
*---------------------------------------------------------------------------*/ *---------------------------------------------------------------------------*/
void void PHY_GetTxPowerLevel8188E(struct adapter *Adapter, u32 *powerlevel)
PHY_GetTxPowerLevel8188E(
struct adapter * Adapter,
u32* powerlevel
)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
u8 TxPwrLevel = 0; u8 TxPwrLevel = 0;
@ -1165,10 +1065,8 @@ PHY_UpdateTxPowerDbm8188E(
else else
OfdmTxPwrIdx = 0; OfdmTxPwrIdx = 0;
for (idx = 0; idx < 14; idx++) for (idx = 0; idx < 14; idx++) {
{ for (rf_path = 0; rf_path < 2; rf_path++) {
for (rf_path = 0; rf_path < 2; rf_path++)
{
pHalData->TxPwrLevelCck[rf_path][idx] = CckTxPwrIdx; pHalData->TxPwrLevelCck[rf_path][idx] = CckTxPwrIdx;
pHalData->TxPwrLevelHT40_1S[rf_path][idx] = pHalData->TxPwrLevelHT40_1S[rf_path][idx] =
pHalData->TxPwrLevelHT40_2S[rf_path][idx] = OfdmTxPwrIdx; pHalData->TxPwrLevelHT40_2S[rf_path][idx] = OfdmTxPwrIdx;
@ -1226,23 +1124,19 @@ _PHY_SetBWMode92C(
regBwOpMode = rtw_read8(Adapter, REG_BWOPMODE); regBwOpMode = rtw_read8(Adapter, REG_BWOPMODE);
regRRSR_RSC = rtw_read8(Adapter, REG_RRSR+2); regRRSR_RSC = rtw_read8(Adapter, REG_RRSR+2);
switch (pHalData->CurrentChannelBW) switch (pHalData->CurrentChannelBW) {
{
case HT_CHANNEL_WIDTH_20: case HT_CHANNEL_WIDTH_20:
regBwOpMode |= BW_OPMODE_20MHZ; regBwOpMode |= BW_OPMODE_20MHZ;
/* 2007/02/07 Mark by Emily becasue we have not verify whether this register works */ /* 2007/02/07 Mark by Emily becasue we have not verify whether this register works */
rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode); rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
break; break;
case HT_CHANNEL_WIDTH_40: case HT_CHANNEL_WIDTH_40:
regBwOpMode &= ~BW_OPMODE_20MHZ; regBwOpMode &= ~BW_OPMODE_20MHZ;
/* 2007/02/07 Mark by Emily becasue we have not verify whether this register works */ /* 2007/02/07 Mark by Emily becasue we have not verify whether this register works */
rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode); rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
regRRSR_RSC = (regRRSR_RSC&0x90) | (pHalData->nCur40MhzPrimeSC<<5); regRRSR_RSC = (regRRSR_RSC&0x90) | (pHalData->nCur40MhzPrimeSC<<5);
rtw_write8(Adapter, REG_RRSR+2, regRRSR_RSC); rtw_write8(Adapter, REG_RRSR+2, regRRSR_RSC);
break; break;
default: default:
break; break;
} }
@ -1250,38 +1144,29 @@ _PHY_SetBWMode92C(
/* 3 */ /* 3 */
/* 3 <2>Set PHY related register */ /* 3 <2>Set PHY related register */
/* 3 */ /* 3 */
switch (pHalData->CurrentChannelBW) switch (pHalData->CurrentChannelBW) {
{
/* 20 MHz channel*/ /* 20 MHz channel*/
case HT_CHANNEL_WIDTH_20: case HT_CHANNEL_WIDTH_20:
PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0); PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);
PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0); PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
/* PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1); */
break; break;
/* 40 MHz channel*/ /* 40 MHz channel*/
case HT_CHANNEL_WIDTH_40: case HT_CHANNEL_WIDTH_40:
PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1); PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);
PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1); PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
/* Set Control channel to upper or lower. These settings are required only for 40MHz */ /* Set Control channel to upper or lower. These settings are required only for 40MHz */
PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1)); PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1));
PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC); PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
PHY_SetBBReg(Adapter, 0x818, (BIT26 | BIT27),
PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC==HAL_PRIME_CHNL_OFFSET_LOWER)?2:1); (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
break; break;
default: default:
break; break;
} }
/* Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 */ /* Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 */
/* 3<3>Set RF related register */ /* 3<3>Set RF related register */
switch (pHalData->rf_chip) switch (pHalData->rf_chip) {
{
case RF_8225: case RF_8225:
break; break;
case RF_8256: case RF_8256:
@ -1314,12 +1199,8 @@ _PHY_SetBWMode92C(
* *
* Note: We do not take j mode into consideration now * Note: We do not take j mode into consideration now
*---------------------------------------------------------------------------*/ *---------------------------------------------------------------------------*/
void void PHY_SetBWMode8188E(struct adapter *Adapter, enum ht_channel_width Bandwidth, /* 20M or 40M */
PHY_SetBWMode8188E( unsigned char Offset) /* Upper, Lower, or Don't care */
struct adapter * Adapter,
enum ht_channel_width Bandwidth, /* 20M or 40M */
unsigned char Offset /* Upper, Lower, or Don't care */
)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
enum ht_channel_width tmpBW = pHalData->CurrentChannelBW; enum ht_channel_width tmpBW = pHalData->CurrentChannelBW;
@ -1341,9 +1222,7 @@ static void _PHY_SwChnl8192C(struct adapter * Adapter, u8 channel)
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
if (Adapter->bNotifyChannelChange) if (Adapter->bNotifyChannelChange)
{
DBG_88E("[%s] ch = %d\n", __func__, channel); DBG_88E("[%s] ch = %d\n", __func__, channel);
}
/* s1. pre common command - CmdID_SetTxPowerLevel */ /* s1. pre common command - CmdID_SetTxPowerLevel */
PHY_SetTxPowerLevel8188E(Adapter, channel); PHY_SetTxPowerLevel8188E(Adapter, channel);
@ -1357,12 +1236,9 @@ static void _PHY_SwChnl8192C(struct adapter * Adapter, u8 channel)
} }
} }
void void PHY_SwChnl8188E(struct adapter *Adapter, u8 channel)
PHY_SwChnl8188E( /* Call after initialization */
struct adapter * Adapter,
u8 channel
)
{ {
/* Call after initialization */
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
u8 tmpchannel = pHalData->CurrentChannel; u8 tmpchannel = pHalData->CurrentChannel;
bool bResult = true; bool bResult = true;
@ -1393,15 +1269,12 @@ PHY_SwChnl8188E( /* Call after initialization */
if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) { if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) {
_PHY_SwChnl8192C(Adapter, channel); _PHY_SwChnl8192C(Adapter, channel);
if (bResult) { if (bResult)
; ;
} else {
pHalData->CurrentChannel = tmpchannel;
}
}
else else
{ pHalData->CurrentChannel = tmpchannel;
} else {
pHalData->CurrentChannel = tmpchannel; pHalData->CurrentChannel = tmpchannel;
} }
} }
@ -1446,12 +1319,9 @@ phy_SetSwChnlCmdArray(
return true; return true;
} }
static void static void phy_FinishSwChnlNow(struct adapter *Adapter, u8 channel)
phy_FinishSwChnlNow( /* We should not call this function directly */
struct adapter * Adapter,
u8 channel
)
{ {
/* We should not call this function directly */
} }
/* */ /* */
@ -1462,12 +1332,8 @@ phy_FinishSwChnlNow( /* We should not call this function directly */
/* The following procedure is operted according to SwChanlCallback8190Pci(). */ /* The following procedure is operted according to SwChanlCallback8190Pci(). */
/* However, this procedure is performed synchronously which should be running under */ /* However, this procedure is performed synchronously which should be running under */
/* passive level. */ /* passive level. */
/* */ /* Only called during initialize */
void void PHY_SwChnlPhy8192C(struct adapter *Adapter, u8 channel)
PHY_SwChnlPhy8192C( /* Only called during initialize */
struct adapter * Adapter,
u8 channel
)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);

226
hal/rtl8188e_rf6052.c
View file

@ -91,8 +91,7 @@ static struct rf_shadow RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
* Firmwaer support the utility later. * Firmwaer support the utility later.
* *
*---------------------------------------------------------------------------*/ *---------------------------------------------------------------------------*/
void rtl8188e_RF_ChangeTxPath( struct adapter * Adapter, void rtl8188e_RF_ChangeTxPath(struct adapter *Adapter, u16 DataRate)
u16 DataRate)
{ {
/* We do not support gain table change inACUT now !!!! Delete later !!! */ /* We do not support gain table change inACUT now !!!! Delete later !!! */
} /* RF_ChangeTxPath */ } /* RF_ChangeTxPath */
@ -112,33 +111,25 @@ void rtl8188e_RF_ChangeTxPath( struct adapter * Adapter,
* *
* Note: For RF type 0222D * Note: For RF type 0222D
*---------------------------------------------------------------------------*/ *---------------------------------------------------------------------------*/
void void rtl8188e_PHY_RF6052SetBandwidth(struct adapter *Adapter,
rtl8188e_PHY_RF6052SetBandwidth( enum ht_channel_width Bandwidth)
struct adapter * Adapter,
enum ht_channel_width Bandwidth) /* 20M or 40M */
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
switch (Bandwidth) switch (Bandwidth) {
{
case HT_CHANNEL_WIDTH_20: case HT_CHANNEL_WIDTH_20:
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10) | BIT(11)); pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10) | BIT(11));
PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
break; break;
case HT_CHANNEL_WIDTH_40: case HT_CHANNEL_WIDTH_40:
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10)); pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10));
PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
break; break;
default: default:
/* RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth )); */
break; break;
} }
} }
/*----------------------------------------------------------------------------- /*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetCckTxPower * Function: PHY_RF6052SetCckTxPower
* *
@ -165,7 +156,6 @@ rtl8188e_PHY_RF6052SetCckTxPower(
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
struct dm_priv *pdmpriv = &pHalData->dmpriv; struct dm_priv *pdmpriv = &pHalData->dmpriv;
struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
/* PMGNT_INFO pMgntInfo=&Adapter->MgntInfo; */
u32 TxAGC[2] = {0, 0}, tmpval = 0, pwrtrac_value; u32 TxAGC[2] = {0, 0}, tmpval = 0, pwrtrac_value;
bool TurboScanOff = false; bool TurboScanOff = false;
u8 idx1, idx2; u8 idx1, idx2;
@ -175,17 +165,14 @@ rtl8188e_PHY_RF6052SetCckTxPower(
TurboScanOff = true; TurboScanOff = true;
if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) {
{
TxAGC[RF_PATH_A] = 0x3f3f3f3f; TxAGC[RF_PATH_A] = 0x3f3f3f3f;
TxAGC[RF_PATH_B] = 0x3f3f3f3f; TxAGC[RF_PATH_B] = 0x3f3f3f3f;
TurboScanOff = true;/* disable turbo scan */ TurboScanOff = true;/* disable turbo scan */
if (TurboScanOff) if (TurboScanOff) {
{ for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
for (idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
{
TxAGC[idx1] = TxAGC[idx1] =
pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
@ -194,33 +181,27 @@ rtl8188e_PHY_RF6052SetCckTxPower(
TxAGC[idx1] = 0x20; TxAGC[idx1] = 0x20;
} }
} }
} } else {
else /* Driver dynamic Tx power shall not affect Tx power.
{ * It shall be determined by power training mechanism.
/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */ i * Currently, we cannot fully disable driver dynamic
/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */ * tx power mechanism because it is referenced by BT
/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */ * coexist mechanism.
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) * In the future, two mechanism shall be separated from
{ * each other and maintained independantly. */
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) {
TxAGC[RF_PATH_A] = 0x10101010; TxAGC[RF_PATH_A] = 0x10101010;
TxAGC[RF_PATH_B] = 0x10101010; TxAGC[RF_PATH_B] = 0x10101010;
} } else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) {
else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
{
TxAGC[RF_PATH_A] = 0x00000000; TxAGC[RF_PATH_A] = 0x00000000;
TxAGC[RF_PATH_B] = 0x00000000; TxAGC[RF_PATH_B] = 0x00000000;
} } else {
else for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
{
for (idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
{
TxAGC[idx1] = TxAGC[idx1] =
pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
} }
if (pHalData->EEPROMRegulatory == 0) {
if (pHalData->EEPROMRegulatory==0)
{
tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) + tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) +
(pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8); (pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8);
TxAGC[RF_PATH_A] += tmpval; TxAGC[RF_PATH_A] += tmpval;
@ -231,12 +212,9 @@ rtl8188e_PHY_RF6052SetCckTxPower(
} }
} }
} }
for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
for (idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
{
ptr = (u8 *)(&(TxAGC[idx1])); ptr = (u8 *)(&(TxAGC[idx1]));
for (idx2=0; idx2<4; idx2++) for (idx2 = 0; idx2 < 4; idx2++) {
{
if (*ptr > RF6052_MAX_TX_PWR) if (*ptr > RF6052_MAX_TX_PWR)
*ptr = RF6052_MAX_TX_PWR; *ptr = RF6052_MAX_TX_PWR;
ptr++; ptr++;
@ -244,18 +222,16 @@ rtl8188e_PHY_RF6052SetCckTxPower(
} }
ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 1, &direction, &pwrtrac_value); ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 1, &direction, &pwrtrac_value);
if (direction == 1) /* Increase TX pwoer */ if (direction == 1) {
{ /* Increase TX pwoer */
TxAGC[0] += pwrtrac_value; TxAGC[0] += pwrtrac_value;
TxAGC[1] += pwrtrac_value; TxAGC[1] += pwrtrac_value;
} } else if (direction == 2) {
else if (direction == 2) /* Decrease TX pwoer */ /* Decrease TX pwoer */
{
TxAGC[0] -= pwrtrac_value; TxAGC[0] -= pwrtrac_value;
TxAGC[1] -= pwrtrac_value; TxAGC[1] -= pwrtrac_value;
} }
/* rf-A cck tx power */ /* rf-A cck tx power */
tmpval = TxAGC[RF_PATH_A]&0xff; tmpval = TxAGC[RF_PATH_A]&0xff;
PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
@ -273,15 +249,8 @@ rtl8188e_PHY_RF6052SetCckTxPower(
/* powerbase0 for OFDM rates */ /* powerbase0 for OFDM rates */
/* powerbase1 for HT MCS rates */ /* powerbase1 for HT MCS rates */
/* */ /* */
static void getPowerBase88E( static void getpowerbase88e(struct adapter *Adapter, u8 *pPowerLevelOFDM,
struct adapter * Adapter, u8 *pPowerLevelBW20, u8 *pPowerLevelBW40, u8 Channel, u32 *OfdmBase, u32 *MCSBase)
u8* pPowerLevelOFDM,
u8* pPowerLevelBW20,
u8* pPowerLevelBW40,
u8 Channel,
u32* OfdmBase,
u32* MCSBase
)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
u32 powerBase0, powerBase1; u32 powerBase0, powerBase1;
@ -289,41 +258,27 @@ static void getPowerBase88E(
s8 HT20_pwrdiff = 0; s8 HT20_pwrdiff = 0;
u8 i, powerlevel[2]; u8 i, powerlevel[2];
for (i=0; i<2; i++) for (i = 0; i < 2; i++) {
{
powerBase0 = pPowerLevelOFDM[i]; powerBase0 = pPowerLevelOFDM[i];
powerBase0 = (powerBase0<<24) | (powerBase0<<16) | (powerBase0<<8) | powerBase0; powerBase0 = (powerBase0<<24) | (powerBase0<<16) | (powerBase0<<8) | powerBase0;
*(OfdmBase+i) = powerBase0; *(OfdmBase+i) = powerBase0;
} }
for (i = 0; i < pHalData->NumTotalRFPath; i++) {
for (i=0; i<pHalData->NumTotalRFPath; i++)
{
/* Check HT20 to HT40 diff */ /* Check HT20 to HT40 diff */
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
{
powerlevel[i] = pPowerLevelBW20[i]; powerlevel[i] = pPowerLevelBW20[i];
}
else else
{
powerlevel[i] = pPowerLevelBW40[i]; powerlevel[i] = pPowerLevelBW40[i];
}
powerBase1 = powerlevel[i]; powerBase1 = powerlevel[i];
powerBase1 = (powerBase1<<24) | (powerBase1<<16) | (powerBase1<<8) | powerBase1; powerBase1 = (powerBase1<<24) | (powerBase1<<16) | (powerBase1<<8) | powerBase1;
*(MCSBase+i) = powerBase1; *(MCSBase+i) = powerBase1;
} }
} }
static void get_rx_power_val_by_reg(struct adapter *Adapter, u8 Channel,
static void getTxPowerWriteValByRegulatory88E( u8 index, u32 *powerBase0, u32 *powerBase1,
struct adapter * Adapter, u32 *pOutWriteVal)
u8 Channel,
u8 index,
u32* powerBase0,
u32* powerBase1,
u32* pOutWriteVal
)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv; struct dm_priv *pdmpriv = &pHalData->dmpriv;
u1Byte i, chnlGroup = 0, pwr_diff_limit[4], customer_pwr_limit; u1Byte i, chnlGroup = 0, pwr_diff_limit[4], customer_pwr_limit;
@ -331,13 +286,10 @@ static void getTxPowerWriteValByRegulatory88E(
u4Byte writeVal, customer_limit, rf; u4Byte writeVal, customer_limit, rf;
u1Byte Regulatory = pHalData->EEPROMRegulatory; u1Byte Regulatory = pHalData->EEPROMRegulatory;
/* */
/* Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */ /* Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */
/* */
for (rf = 0; rf < 2; rf++) { for (rf = 0; rf < 2; rf++) {
switch (Regulatory) switch (Regulatory) {
{
case 0: /* Realtek better performance */ case 0: /* Realtek better performance */
/* increase power diff defined by Realtek for large power */ /* increase power diff defined by Realtek for large power */
chnlGroup = 0; chnlGroup = 0;
@ -346,11 +298,9 @@ static void getTxPowerWriteValByRegulatory88E(
break; break;
case 1: /* Realtek regulatory */ case 1: /* Realtek regulatory */
/* increase power diff defined by Realtek for regulatory */ /* increase power diff defined by Realtek for regulatory */
{
if (pHalData->pwrGroupCnt == 1) if (pHalData->pwrGroupCnt == 1)
chnlGroup = 0; chnlGroup = 0;
if (pHalData->pwrGroupCnt >= pHalData->PGMaxGroup) if (pHalData->pwrGroupCnt >= pHalData->PGMaxGroup) {
{
if (Channel < 3) /* Chanel 1-2 */ if (Channel < 3) /* Chanel 1-2 */
chnlGroup = 0; chnlGroup = 0;
else if (Channel < 6) /* Channel 3-5 */ else if (Channel < 6) /* Channel 3-5 */
@ -366,7 +316,6 @@ static void getTxPowerWriteValByRegulatory88E(
} }
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] + writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] +
((index < 2) ? powerBase0[rf] : powerBase1[rf]); ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
}
break; break;
case 2: /* Better regulatory */ case 2: /* Better regulatory */
/* don't increase any power diff */ /* don't increase any power diff */
@ -391,8 +340,7 @@ static void getTxPowerWriteValByRegulatory88E(
else else
pwr_diff = customer_pwr_limit - pwr_diff; pwr_diff = customer_pwr_limit - pwr_diff;
for (i=0; i<4; i++) for (i = 0; i < 4; i++) {
{
pwr_diff_limit[i] = (u1Byte)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)]&(0x7f<<(i*8)))>>(i*8)); pwr_diff_limit[i] = (u1Byte)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)]&(0x7f<<(i*8)))>>(i*8));
if (pwr_diff_limit[i] > pwr_diff) if (pwr_diff_limit[i] > pwr_diff)
@ -408,7 +356,6 @@ static void getTxPowerWriteValByRegulatory88E(
((index < 2) ? powerBase0[rf] : powerBase1[rf]); ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
break; break;
} }
/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */ /* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */ /* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */ /* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */
@ -421,39 +368,30 @@ static void getTxPowerWriteValByRegulatory88E(
/* 20100628 Joseph: High power mode for BT-Coexist mechanism. */ /* 20100628 Joseph: High power mode for BT-Coexist mechanism. */
/* This mechanism is only applied when Driver-Highpower-Mechanism is OFF. */ /* This mechanism is only applied when Driver-Highpower-Mechanism is OFF. */
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1) if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
{
writeVal = writeVal - 0x06060606; writeVal = writeVal - 0x06060606;
}
else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2) else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
{
writeVal = writeVal; writeVal = writeVal;
}
*(pOutWriteVal+rf) = writeVal; *(pOutWriteVal+rf) = writeVal;
} }
} }
static void writeOFDMPowerReg88E(struct adapter *Adapter, u8 index, u32 *pValue)
static void writeOFDMPowerReg88E(
struct adapter * Adapter,
u8 index,
u32* pValue
)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
u16 RegOffset_A[6] = { rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24, u16 regoffset_a[6] = {
rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24,
rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04, rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04,
rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12}; rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12};
u16 RegOffset_B[6] = { rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24, u16 regoffset_b[6] = {
rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24,
rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04, rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04,
rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12}; rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12};
u8 i, rf, pwr_val[4]; u8 i, rf, pwr_val[4];
u32 writeVal; u32 writeVal;
u16 RegOffset; u16 regoffset;
for (rf=0; rf<2; rf++) for (rf = 0; rf < 2; rf++) {
{
writeVal = pValue[rf]; writeVal = pValue[rf];
for (i=0; i<4; i++) for (i = 0; i < 4; i++) {
{
pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8)); pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));
if (pwr_val[i] > RF6052_MAX_TX_PWR) if (pwr_val[i] > RF6052_MAX_TX_PWR)
pwr_val[i] = RF6052_MAX_TX_PWR; pwr_val[i] = RF6052_MAX_TX_PWR;
@ -461,36 +399,33 @@ static void writeOFDMPowerReg88E(
writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) | (pwr_val[1]<<8) | pwr_val[0]; writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) | (pwr_val[1]<<8) | pwr_val[0];
if (rf == 0) if (rf == 0)
RegOffset = RegOffset_A[index]; regoffset = regoffset_a[index];
else else
RegOffset = RegOffset_B[index]; regoffset = regoffset_b[index];
PHY_SetBBReg(Adapter, RegOffset, bMaskDWord, writeVal); PHY_SetBBReg(Adapter, regoffset, bMaskDWord, writeVal);
/* 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */ /* 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */
if (((pHalData->rf_type == RF_2T2R) && if (((pHalData->rf_type == RF_2T2R) &&
(RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs15_Mcs12))|| (regoffset == rTxAGC_A_Mcs15_Mcs12 || regoffset == rTxAGC_B_Mcs15_Mcs12)) ||
((pHalData->rf_type != RF_2T2R) && ((pHalData->rf_type != RF_2T2R) &&
(RegOffset == rTxAGC_A_Mcs07_Mcs04 || RegOffset == rTxAGC_B_Mcs07_Mcs04)) ) (regoffset == rTxAGC_A_Mcs07_Mcs04 || regoffset == rTxAGC_B_Mcs07_Mcs04))) {
{
writeVal = pwr_val[3]; writeVal = pwr_val[3];
if (RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_A_Mcs07_Mcs04) if (regoffset == rTxAGC_A_Mcs15_Mcs12 || regoffset == rTxAGC_A_Mcs07_Mcs04)
RegOffset = 0xc90; regoffset = 0xc90;
if (RegOffset == rTxAGC_B_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs07_Mcs04) if (regoffset == rTxAGC_B_Mcs15_Mcs12 || regoffset == rTxAGC_B_Mcs07_Mcs04)
RegOffset = 0xc98; regoffset = 0xc98;
for (i=0; i<3; i++) for (i = 0; i < 3; i++) {
{
if (i != 2) if (i != 2)
writeVal = (writeVal > 8) ? (writeVal-8) : 0; writeVal = (writeVal > 8) ? (writeVal-8) : 0;
else else
writeVal = (writeVal > 6) ? (writeVal-6) : 0; writeVal = (writeVal > 6) ? (writeVal-6) : 0;
rtw_write8(Adapter, (u32)(RegOffset+i), (u8)writeVal); rtw_write8(Adapter, (u32)(regoffset+i), (u8)writeVal);
} }
} }
} }
} }
/*----------------------------------------------------------------------------- /*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetOFDMTxPower * Function: PHY_RF6052SetOFDMTxPower
* *
@ -527,45 +462,29 @@ rtl8188e_PHY_RF6052SetOFDMTxPower(
u8 direction; u8 direction;
u8 index = 0; u8 index = 0;
getPowerBase88E(Adapter, pPowerLevelOFDM,pPowerLevelBW20,pPowerLevelBW40, Channel, &powerBase0[0], &powerBase1[0]); getpowerbase88e(Adapter, pPowerLevelOFDM, pPowerLevelBW20, pPowerLevelBW40, Channel, &powerBase0[0], &powerBase1[0]);
/* */
/* 2012/04/23 MH According to power tracking value, we need to revise OFDM tx power. */ /* 2012/04/23 MH According to power tracking value, we need to revise OFDM tx power. */
/* This is ued to fix unstable power tracking mode. */ /* This is ued to fix unstable power tracking mode. */
/* */
ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 0, &direction, &pwrtrac_value); ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 0, &direction, &pwrtrac_value);
for (index=0; index<6; index++) for (index = 0; index < 6; index++) {
{ get_rx_power_val_by_reg(Adapter, Channel, index,
getTxPowerWriteValByRegulatory88E(Adapter, Channel, index, &powerBase0[0], &powerBase1[0],
&powerBase0[0], &powerBase1[0], &writeVal[0]); &writeVal[0]);
if (direction == 1) if (direction == 1) {
{
writeVal[0] += pwrtrac_value; writeVal[0] += pwrtrac_value;
writeVal[1] += pwrtrac_value; writeVal[1] += pwrtrac_value;
} } else if (direction == 2) {
else if (direction == 2)
{
writeVal[0] -= pwrtrac_value; writeVal[0] -= pwrtrac_value;
writeVal[1] -= pwrtrac_value; writeVal[1] -= pwrtrac_value;
} }
writeOFDMPowerReg88E(Adapter, index, &writeVal[0]); writeOFDMPowerReg88E(Adapter, index, &writeVal[0]);
} }
} }
static void static int phy_RF6052_Config_ParaFile(struct adapter *Adapter)
phy_RF6052_Config_HardCode(
struct adapter * Adapter
)
{
}
static int
phy_RF6052_Config_ParaFile(
struct adapter * Adapter
)
{ {
u32 u4RegValue; u32 u4RegValue;
u8 eRFPath; u8 eRFPath;
@ -578,9 +497,7 @@ phy_RF6052_Config_ParaFile(
/* 3----------------------------------------------------------------- */ /* 3----------------------------------------------------------------- */
/* 3 <2> Initialize RF */ /* 3 <2> Initialize RF */
/* 3----------------------------------------------------------------- */ /* 3----------------------------------------------------------------- */
for (eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
{
pPhyReg = &pHalData->PHYRegDef[eRFPath]; pPhyReg = &pHalData->PHYRegDef[eRFPath];
/*----Store original RFENV control type----*/ /*----Store original RFENV control type----*/
@ -594,7 +511,6 @@ phy_RF6052_Config_ParaFile(
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16); u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
break; break;
} }
/*----Set RF_ENV enable----*/ /*----Set RF_ENV enable----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
rtw_udelay_os(1);/* PlatformStallExecution(1); */ rtw_udelay_os(1);/* PlatformStallExecution(1); */
@ -625,10 +541,8 @@ phy_RF6052_Config_ParaFile(
case RF_PATH_D: case RF_PATH_D:
break; break;
} }
/*----Restore RFENV control type----*/; /*----Restore RFENV control type----*/;
switch (eRFPath) switch (eRFPath) {
{
case RF_PATH_A: case RF_PATH_A:
case RF_PATH_C: case RF_PATH_C:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
@ -638,22 +552,16 @@ phy_RF6052_Config_ParaFile(
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
break; break;
} }
if (rtStatus != _SUCCESS) if (rtStatus != _SUCCESS)
goto phy_RF6052_Config_ParaFile_Fail; goto phy_RF6052_Config_ParaFile_Fail;
} }
return rtStatus; return rtStatus;
phy_RF6052_Config_ParaFile_Fail: phy_RF6052_Config_ParaFile_Fail:
return rtStatus; return rtStatus;
} }
int PHY_RF6052_Config8188E(struct adapter *Adapter)
int
PHY_RF6052_Config8188E(
struct adapter * Adapter)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
int rtStatus = _SUCCESS; int rtStatus = _SUCCESS;
@ -673,5 +581,3 @@ PHY_RF6052_Config8188E(
rtStatus = phy_RF6052_Config_ParaFile(Adapter); rtStatus = phy_RF6052_Config_ParaFile(Adapter);
return rtStatus; return rtStatus;
} }
/* End of HalRf6052.c */