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rtl8188eu: Fix checkpatch errors in hal/rtl8188e_mp.c, hal/rtl8188e_phycfg.c, and hal/rtl8188e_rf6052.c

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2013-08-08 09:31:29 -05:00
parent 9c3c9ddc8c
commit f527ca59c9
3 changed files with 709 additions and 1013 deletions
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622
hal/rtl8188e_mp.c
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File diff suppressed because it is too large Load diff

620
hal/rtl8188e_phycfg.c
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File diff suppressed because it is too large Load diff

480
hal/rtl8188e_rf6052.c
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@ -50,15 +50,15 @@
/* Define local structure for debug!!!!! */ /* Define local structure for debug!!!!! */
struct rf_shadow { struct rf_shadow {
/* Shadow register value */ /* Shadow register value */
u32 Value; u32 Value;
/* Compare or not flag */ /* Compare or not flag */
u8 Compare; u8 Compare;
/* Record If it had ever modified unpredicted */ /* Record If it had ever modified unpredicted */
u8 ErrorOrNot; u8 ErrorOrNot;
/* Recorver Flag */ /* Recorver Flag */
u8 Recorver; u8 Recorver;
/* */ /* */
u8 Driver_Write; u8 Driver_Write;
}; };
/*---------------------------Define Local Constant---------------------------*/ /*---------------------------Define Local Constant---------------------------*/
@ -91,8 +91,7 @@ static struct rf_shadow RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
* Firmwaer support the utility later. * Firmwaer support the utility later.
* *
*---------------------------------------------------------------------------*/ *---------------------------------------------------------------------------*/
void rtl8188e_RF_ChangeTxPath( struct adapter * Adapter, void rtl8188e_RF_ChangeTxPath(struct adapter *Adapter, u16 DataRate)
u16 DataRate)
{ {
/* We do not support gain table change inACUT now !!!! Delete later !!! */ /* We do not support gain table change inACUT now !!!! Delete later !!! */
} /* RF_ChangeTxPath */ } /* RF_ChangeTxPath */
@ -103,7 +102,7 @@ void rtl8188e_RF_ChangeTxPath( struct adapter * Adapter,
* *
* Overview: This function is called by SetBWModeCallback8190Pci() only * Overview: This function is called by SetBWModeCallback8190Pci() only
* *
* Input: struct adapter * Adapter * Input: struct adapter *Adapter
* WIRELESS_BANDWIDTH_E Bandwidth 20M or 40M * WIRELESS_BANDWIDTH_E Bandwidth 20M or 40M
* *
* Output: NONE * Output: NONE
@ -112,33 +111,25 @@ void rtl8188e_RF_ChangeTxPath( struct adapter * Adapter,
* *
* Note: For RF type 0222D * Note: For RF type 0222D
*---------------------------------------------------------------------------*/ *---------------------------------------------------------------------------*/
void void rtl8188e_PHY_RF6052SetBandwidth(struct adapter *Adapter,
rtl8188e_PHY_RF6052SetBandwidth( enum ht_channel_width Bandwidth)
struct adapter * Adapter,
enum ht_channel_width Bandwidth) /* 20M or 40M */
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
switch (Bandwidth) switch (Bandwidth) {
{ case HT_CHANNEL_WIDTH_20:
case HT_CHANNEL_WIDTH_20: pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10) | BIT(11));
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10) | BIT(11)); PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); break;
break; case HT_CHANNEL_WIDTH_40:
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10));
case HT_CHANNEL_WIDTH_40: PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff)| BIT(10)); break;
PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); default:
break; break;
default:
/* RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth )); */
break;
} }
} }
/*----------------------------------------------------------------------------- /*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetCckTxPower * Function: PHY_RF6052SetCckTxPower
* *
@ -158,34 +149,30 @@ rtl8188e_PHY_RF6052SetBandwidth(
void void
rtl8188e_PHY_RF6052SetCckTxPower( rtl8188e_PHY_RF6052SetCckTxPower(
struct adapter * Adapter, struct adapter *Adapter,
u8* pPowerlevel) u8 *pPowerlevel)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
struct dm_priv *pdmpriv = &pHalData->dmpriv; struct dm_priv *pdmpriv = &pHalData->dmpriv;
struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
/* PMGNT_INFO pMgntInfo=&Adapter->MgntInfo; */ u32 TxAGC[2] = {0, 0}, tmpval = 0, pwrtrac_value;
u32 TxAGC[2]={0, 0}, tmpval=0,pwrtrac_value; bool TurboScanOff = false;
bool TurboScanOff = false; u8 idx1, idx2;
u8 idx1, idx2; u8 *ptr;
u8* ptr; u8 direction;
u8 direction;
/* FOR CE ,must disable turbo scan */ /* FOR CE ,must disable turbo scan */
TurboScanOff = true; TurboScanOff = true;
if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) {
{
TxAGC[RF_PATH_A] = 0x3f3f3f3f; TxAGC[RF_PATH_A] = 0x3f3f3f3f;
TxAGC[RF_PATH_B] = 0x3f3f3f3f; TxAGC[RF_PATH_B] = 0x3f3f3f3f;
TurboScanOff = true;/* disable turbo scan */ TurboScanOff = true;/* disable turbo scan */
if (TurboScanOff) if (TurboScanOff) {
{ for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
for (idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
{
TxAGC[idx1] = TxAGC[idx1] =
pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
@ -194,33 +181,27 @@ rtl8188e_PHY_RF6052SetCckTxPower(
TxAGC[idx1] = 0x20; TxAGC[idx1] = 0x20;
} }
} }
} } else {
else /* Driver dynamic Tx power shall not affect Tx power.
{ * It shall be determined by power training mechanism.
/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */ i * Currently, we cannot fully disable driver dynamic
/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */ * tx power mechanism because it is referenced by BT
/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */ * coexist mechanism.
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) * In the future, two mechanism shall be separated from
{ * each other and maintained independantly. */
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) {
TxAGC[RF_PATH_A] = 0x10101010; TxAGC[RF_PATH_A] = 0x10101010;
TxAGC[RF_PATH_B] = 0x10101010; TxAGC[RF_PATH_B] = 0x10101010;
} } else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) {
else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
{
TxAGC[RF_PATH_A] = 0x00000000; TxAGC[RF_PATH_A] = 0x00000000;
TxAGC[RF_PATH_B] = 0x00000000; TxAGC[RF_PATH_B] = 0x00000000;
} } else {
else for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
{
for (idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
{
TxAGC[idx1] = TxAGC[idx1] =
pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
} }
if (pHalData->EEPROMRegulatory == 0) {
if (pHalData->EEPROMRegulatory==0)
{
tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) + tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) +
(pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8); (pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8);
TxAGC[RF_PATH_A] += tmpval; TxAGC[RF_PATH_A] += tmpval;
@ -231,12 +212,9 @@ rtl8188e_PHY_RF6052SetCckTxPower(
} }
} }
} }
for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
for (idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++) ptr = (u8 *)(&(TxAGC[idx1]));
{ for (idx2 = 0; idx2 < 4; idx2++) {
ptr = (u8*)(&(TxAGC[idx1]));
for (idx2=0; idx2<4; idx2++)
{
if (*ptr > RF6052_MAX_TX_PWR) if (*ptr > RF6052_MAX_TX_PWR)
*ptr = RF6052_MAX_TX_PWR; *ptr = RF6052_MAX_TX_PWR;
ptr++; ptr++;
@ -244,18 +222,16 @@ rtl8188e_PHY_RF6052SetCckTxPower(
} }
ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 1, &direction, &pwrtrac_value); ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 1, &direction, &pwrtrac_value);
if (direction == 1) /* Increase TX pwoer */ if (direction == 1) {
{ /* Increase TX pwoer */
TxAGC[0] += pwrtrac_value; TxAGC[0] += pwrtrac_value;
TxAGC[1] += pwrtrac_value; TxAGC[1] += pwrtrac_value;
} } else if (direction == 2) {
else if (direction == 2) /* Decrease TX pwoer */ /* Decrease TX pwoer */
{
TxAGC[0] -= pwrtrac_value; TxAGC[0] -= pwrtrac_value;
TxAGC[1] -= pwrtrac_value; TxAGC[1] -= pwrtrac_value;
} }
/* rf-A cck tx power */ /* rf-A cck tx power */
tmpval = TxAGC[RF_PATH_A]&0xff; tmpval = TxAGC[RF_PATH_A]&0xff;
PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
@ -273,142 +249,113 @@ rtl8188e_PHY_RF6052SetCckTxPower(
/* powerbase0 for OFDM rates */ /* powerbase0 for OFDM rates */
/* powerbase1 for HT MCS rates */ /* powerbase1 for HT MCS rates */
/* */ /* */
static void getPowerBase88E( static void getpowerbase88e(struct adapter *Adapter, u8 *pPowerLevelOFDM,
struct adapter * Adapter, u8 *pPowerLevelBW20, u8 *pPowerLevelBW40, u8 Channel, u32 *OfdmBase, u32 *MCSBase)
u8* pPowerLevelOFDM,
u8* pPowerLevelBW20,
u8* pPowerLevelBW40,
u8 Channel,
u32* OfdmBase,
u32* MCSBase
)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
u32 powerBase0, powerBase1; u32 powerBase0, powerBase1;
u8 Legacy_pwrdiff=0; u8 Legacy_pwrdiff = 0;
s8 HT20_pwrdiff=0; s8 HT20_pwrdiff = 0;
u8 i, powerlevel[2]; u8 i, powerlevel[2];
for (i=0; i<2; i++) for (i = 0; i < 2; i++) {
{
powerBase0 = pPowerLevelOFDM[i]; powerBase0 = pPowerLevelOFDM[i];
powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; powerBase0 = (powerBase0<<24) | (powerBase0<<16) | (powerBase0<<8) | powerBase0;
*(OfdmBase+i) = powerBase0; *(OfdmBase+i) = powerBase0;
} }
for (i = 0; i < pHalData->NumTotalRFPath; i++) {
for (i=0; i<pHalData->NumTotalRFPath; i++)
{
/* Check HT20 to HT40 diff */ /* Check HT20 to HT40 diff */
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
{
powerlevel[i] = pPowerLevelBW20[i]; powerlevel[i] = pPowerLevelBW20[i];
}
else else
{
powerlevel[i] = pPowerLevelBW40[i]; powerlevel[i] = pPowerLevelBW40[i];
}
powerBase1 = powerlevel[i]; powerBase1 = powerlevel[i];
powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; powerBase1 = (powerBase1<<24) | (powerBase1<<16) | (powerBase1<<8) | powerBase1;
*(MCSBase+i) = powerBase1; *(MCSBase+i) = powerBase1;
} }
} }
static void get_rx_power_val_by_reg(struct adapter *Adapter, u8 Channel,
static void getTxPowerWriteValByRegulatory88E( u8 index, u32 *powerBase0, u32 *powerBase1,
struct adapter * Adapter, u32 *pOutWriteVal)
u8 Channel,
u8 index,
u32* powerBase0,
u32* powerBase1,
u32* pOutWriteVal
)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv; struct dm_priv *pdmpriv = &pHalData->dmpriv;
u1Byte i, chnlGroup=0, pwr_diff_limit[4], customer_pwr_limit; u1Byte i, chnlGroup = 0, pwr_diff_limit[4], customer_pwr_limit;
s1Byte pwr_diff=0; s1Byte pwr_diff = 0;
u4Byte writeVal, customer_limit, rf; u4Byte writeVal, customer_limit, rf;
u1Byte Regulatory = pHalData->EEPROMRegulatory; u1Byte Regulatory = pHalData->EEPROMRegulatory;
/* */
/* Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */ /* Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */
/* */
for (rf=0; rf<2; rf++) { for (rf = 0; rf < 2; rf++) {
switch (Regulatory) switch (Regulatory) {
{ case 0: /* Realtek better performance */
case 0: /* Realtek better performance */ /* increase power diff defined by Realtek for large power */
/* increase power diff defined by Realtek for large power */ chnlGroup = 0;
chnlGroup = 0; writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] +
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
((index<2)?powerBase0[rf]:powerBase1[rf]); break;
break; case 1: /* Realtek regulatory */
case 1: /* Realtek regulatory */ /* increase power diff defined by Realtek for regulatory */
/* increase power diff defined by Realtek for regulatory */ if (pHalData->pwrGroupCnt == 1)
{
if (pHalData->pwrGroupCnt == 1)
chnlGroup = 0;
if (pHalData->pwrGroupCnt >= pHalData->PGMaxGroup)
{
if (Channel < 3) /* Chanel 1-2 */
chnlGroup = 0;
else if (Channel < 6) /* Channel 3-5 */
chnlGroup = 1;
else if (Channel <9) /* Channel 6-8 */
chnlGroup = 2;
else if (Channel <12) /* Channel 9-11 */
chnlGroup = 3;
else if (Channel <14) /* Channel 12-13 */
chnlGroup = 4;
else if (Channel ==14) /* Channel 14 */
chnlGroup = 5;
}
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
}
break;
case 2: /* Better regulatory */
/* don't increase any power diff */
writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]);
break;
case 3: /* Customer defined power diff. */
/* increase power diff defined by customer. */
chnlGroup = 0; chnlGroup = 0;
if (pHalData->pwrGroupCnt >= pHalData->PGMaxGroup) {
if (Channel < 3) /* Chanel 1-2 */
chnlGroup = 0;
else if (Channel < 6) /* Channel 3-5 */
chnlGroup = 1;
else if (Channel < 9) /* Channel 6-8 */
chnlGroup = 2;
else if (Channel < 12) /* Channel 9-11 */
chnlGroup = 3;
else if (Channel < 14) /* Channel 12-13 */
chnlGroup = 4;
else if (Channel == 14) /* Channel 14 */
chnlGroup = 5;
}
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] +
((index < 2) ? powerBase0[rf] : powerBase1[rf]);
break;
case 2: /* Better regulatory */
/* don't increase any power diff */
writeVal = ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
break;
case 3: /* Customer defined power diff. */
/* increase power diff defined by customer. */
chnlGroup = 0;
if (index < 2) if (index < 2)
pwr_diff = pHalData->TxPwrLegacyHtDiff[rf][Channel-1]; pwr_diff = pHalData->TxPwrLegacyHtDiff[rf][Channel-1];
else if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) else if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
pwr_diff = pHalData->TxPwrHt20Diff[rf][Channel-1]; pwr_diff = pHalData->TxPwrHt20Diff[rf][Channel-1];
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40) if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
customer_pwr_limit = pHalData->PwrGroupHT40[rf][Channel-1]; customer_pwr_limit = pHalData->PwrGroupHT40[rf][Channel-1];
else else
customer_pwr_limit = pHalData->PwrGroupHT20[rf][Channel-1]; customer_pwr_limit = pHalData->PwrGroupHT20[rf][Channel-1];
if (pwr_diff >= customer_pwr_limit) if (pwr_diff >= customer_pwr_limit)
pwr_diff = 0; pwr_diff = 0;
else else
pwr_diff = customer_pwr_limit - pwr_diff; pwr_diff = customer_pwr_limit - pwr_diff;
for (i=0; i<4; i++) for (i = 0; i < 4; i++) {
{ pwr_diff_limit[i] = (u1Byte)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)]&(0x7f<<(i*8)))>>(i*8));
pwr_diff_limit[i] = (u1Byte)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]&(0x7f<<(i*8)))>>(i*8));
if (pwr_diff_limit[i] > pwr_diff) if (pwr_diff_limit[i] > pwr_diff)
pwr_diff_limit[i] = pwr_diff; pwr_diff_limit[i] = pwr_diff;
} }
customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) | customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
(pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]); (pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]); writeVal = customer_limit + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
break; break;
default: default:
chnlGroup = 0; chnlGroup = 0;
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]); ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
break; break;
} }
/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */ /* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */ /* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */ /* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */
@ -421,76 +368,64 @@ static void getTxPowerWriteValByRegulatory88E(
/* 20100628 Joseph: High power mode for BT-Coexist mechanism. */ /* 20100628 Joseph: High power mode for BT-Coexist mechanism. */
/* This mechanism is only applied when Driver-Highpower-Mechanism is OFF. */ /* This mechanism is only applied when Driver-Highpower-Mechanism is OFF. */
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1) if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
{
writeVal = writeVal - 0x06060606; writeVal = writeVal - 0x06060606;
}
else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2) else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
{ writeVal = writeVal;
writeVal = writeVal ;
}
*(pOutWriteVal+rf) = writeVal; *(pOutWriteVal+rf) = writeVal;
} }
} }
static void writeOFDMPowerReg88E(struct adapter *Adapter, u8 index, u32 *pValue)
static void writeOFDMPowerReg88E(
struct adapter * Adapter,
u8 index,
u32* pValue
)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
u16 RegOffset_A[6] = { rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24, u16 regoffset_a[6] = {
rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04, rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24,
rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12}; rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04,
u16 RegOffset_B[6] = { rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24, rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12};
rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04, u16 regoffset_b[6] = {
rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12}; rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24,
rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04,
rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12};
u8 i, rf, pwr_val[4]; u8 i, rf, pwr_val[4];
u32 writeVal; u32 writeVal;
u16 RegOffset; u16 regoffset;
for (rf=0; rf<2; rf++) for (rf = 0; rf < 2; rf++) {
{
writeVal = pValue[rf]; writeVal = pValue[rf];
for (i=0; i<4; i++) for (i = 0; i < 4; i++) {
{
pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8)); pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));
if (pwr_val[i] > RF6052_MAX_TX_PWR) if (pwr_val[i] > RF6052_MAX_TX_PWR)
pwr_val[i] = RF6052_MAX_TX_PWR; pwr_val[i] = RF6052_MAX_TX_PWR;
} }
writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) |(pwr_val[1]<<8) |pwr_val[0]; writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) | (pwr_val[1]<<8) | pwr_val[0];
if (rf == 0) if (rf == 0)
RegOffset = RegOffset_A[index]; regoffset = regoffset_a[index];
else else
RegOffset = RegOffset_B[index]; regoffset = regoffset_b[index];
PHY_SetBBReg(Adapter, RegOffset, bMaskDWord, writeVal); PHY_SetBBReg(Adapter, regoffset, bMaskDWord, writeVal);
/* 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */ /* 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */
if (((pHalData->rf_type == RF_2T2R) && if (((pHalData->rf_type == RF_2T2R) &&
(RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs15_Mcs12))|| (regoffset == rTxAGC_A_Mcs15_Mcs12 || regoffset == rTxAGC_B_Mcs15_Mcs12)) ||
((pHalData->rf_type != RF_2T2R) && ((pHalData->rf_type != RF_2T2R) &&
(RegOffset == rTxAGC_A_Mcs07_Mcs04 || RegOffset == rTxAGC_B_Mcs07_Mcs04)) ) (regoffset == rTxAGC_A_Mcs07_Mcs04 || regoffset == rTxAGC_B_Mcs07_Mcs04))) {
{
writeVal = pwr_val[3]; writeVal = pwr_val[3];
if (RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_A_Mcs07_Mcs04) if (regoffset == rTxAGC_A_Mcs15_Mcs12 || regoffset == rTxAGC_A_Mcs07_Mcs04)
RegOffset = 0xc90; regoffset = 0xc90;
if (RegOffset == rTxAGC_B_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs07_Mcs04) if (regoffset == rTxAGC_B_Mcs15_Mcs12 || regoffset == rTxAGC_B_Mcs07_Mcs04)
RegOffset = 0xc98; regoffset = 0xc98;
for (i=0; i<3; i++) for (i = 0; i < 3; i++) {
{ if (i != 2)
if (i!=2) writeVal = (writeVal > 8) ? (writeVal-8) : 0;
writeVal = (writeVal>8)?(writeVal-8):0;
else else
writeVal = (writeVal>6)?(writeVal-6):0; writeVal = (writeVal > 6) ? (writeVal-6) : 0;
rtw_write8(Adapter, (u32)(RegOffset+i), (u8)writeVal); rtw_write8(Adapter, (u32)(regoffset+i), (u8)writeVal);
} }
} }
} }
} }
/*----------------------------------------------------------------------------- /*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetOFDMTxPower * Function: PHY_RF6052SetOFDMTxPower
* *
@ -516,71 +451,53 @@ static void writeOFDMPowerReg88E(
void void
rtl8188e_PHY_RF6052SetOFDMTxPower( rtl8188e_PHY_RF6052SetOFDMTxPower(
struct adapter * Adapter, struct adapter *Adapter,
u8* pPowerLevelOFDM, u8 *pPowerLevelOFDM,
u8* pPowerLevelBW20, u8 *pPowerLevelBW20,
u8* pPowerLevelBW40, u8 *pPowerLevelBW40,
u8 Channel) u8 Channel)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
u32 writeVal[2], powerBase0[2], powerBase1[2], pwrtrac_value; u32 writeVal[2], powerBase0[2], powerBase1[2], pwrtrac_value;
u8 direction; u8 direction;
u8 index = 0; u8 index = 0;
getPowerBase88E(Adapter, pPowerLevelOFDM,pPowerLevelBW20,pPowerLevelBW40, Channel, &powerBase0[0], &powerBase1[0]); getpowerbase88e(Adapter, pPowerLevelOFDM, pPowerLevelBW20, pPowerLevelBW40, Channel, &powerBase0[0], &powerBase1[0]);
/* */
/* 2012/04/23 MH According to power tracking value, we need to revise OFDM tx power. */ /* 2012/04/23 MH According to power tracking value, we need to revise OFDM tx power. */
/* This is ued to fix unstable power tracking mode. */ /* This is ued to fix unstable power tracking mode. */
/* */
ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 0, &direction, &pwrtrac_value); ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 0, &direction, &pwrtrac_value);
for (index=0; index<6; index++) for (index = 0; index < 6; index++) {
{ get_rx_power_val_by_reg(Adapter, Channel, index,
getTxPowerWriteValByRegulatory88E(Adapter, Channel, index, &powerBase0[0], &powerBase1[0],
&powerBase0[0], &powerBase1[0], &writeVal[0]); &writeVal[0]);
if (direction == 1) if (direction == 1) {
{
writeVal[0] += pwrtrac_value; writeVal[0] += pwrtrac_value;
writeVal[1] += pwrtrac_value; writeVal[1] += pwrtrac_value;
} } else if (direction == 2) {
else if (direction == 2)
{
writeVal[0] -= pwrtrac_value; writeVal[0] -= pwrtrac_value;
writeVal[1] -= pwrtrac_value; writeVal[1] -= pwrtrac_value;
} }
writeOFDMPowerReg88E(Adapter, index, &writeVal[0]); writeOFDMPowerReg88E(Adapter, index, &writeVal[0]);
} }
} }
static void static int phy_RF6052_Config_ParaFile(struct adapter *Adapter)
phy_RF6052_Config_HardCode(
struct adapter * Adapter
)
{ {
} u32 u4RegValue;
u8 eRFPath;
static int
phy_RF6052_Config_ParaFile(
struct adapter * Adapter
)
{
u32 u4RegValue;
u8 eRFPath;
struct bb_reg_def *pPhyReg; struct bb_reg_def *pPhyReg;
int rtStatus = _SUCCESS; int rtStatus = _SUCCESS;
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
static char sz88eRadioAFile[] = RTL8188E_PHY_RADIO_A; static char sz88eRadioAFile[] = RTL8188E_PHY_RADIO_A;
static char sz88eRadioBFile[] = RTL8188E_PHY_RADIO_B; static char sz88eRadioBFile[] = RTL8188E_PHY_RADIO_B;
/* 3----------------------------------------------------------------- */ /* 3----------------------------------------------------------------- */
/* 3 <2> Initialize RF */ /* 3 <2> Initialize RF */
/* 3----------------------------------------------------------------- */ /* 3----------------------------------------------------------------- */
for (eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
{
pPhyReg = &pHalData->PHYRegDef[eRFPath]; pPhyReg = &pHalData->PHYRegDef[eRFPath];
/*----Store original RFENV control type----*/ /*----Store original RFENV control type----*/
@ -589,12 +506,11 @@ phy_RF6052_Config_ParaFile(
case RF_PATH_C: case RF_PATH_C:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV); u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
break; break;
case RF_PATH_B : case RF_PATH_B:
case RF_PATH_D: case RF_PATH_D:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16); u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
break; break;
} }
/*----Set RF_ENV enable----*/ /*----Set RF_ENV enable----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
rtw_udelay_os(1);/* PlatformStallExecution(1); */ rtw_udelay_os(1);/* PlatformStallExecution(1); */
@ -613,50 +529,42 @@ phy_RF6052_Config_ParaFile(
/*----Initialize RF fom connfiguration file----*/ /*----Initialize RF fom connfiguration file----*/
switch (eRFPath) { switch (eRFPath) {
case RF_PATH_A: case RF_PATH_A:
if (HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(enum ODM_RF_RADIO_PATH)eRFPath, (enum ODM_RF_RADIO_PATH)eRFPath)) if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, (enum ODM_RF_RADIO_PATH)eRFPath, (enum ODM_RF_RADIO_PATH)eRFPath))
rtStatus= _FAIL; rtStatus = _FAIL;
break; break;
case RF_PATH_B: case RF_PATH_B:
if (HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(enum ODM_RF_RADIO_PATH)eRFPath, (enum ODM_RF_RADIO_PATH)eRFPath)) if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, (enum ODM_RF_RADIO_PATH)eRFPath, (enum ODM_RF_RADIO_PATH)eRFPath))
rtStatus= _FAIL; rtStatus = _FAIL;
break; break;
case RF_PATH_C: case RF_PATH_C:
break; break;
case RF_PATH_D: case RF_PATH_D:
break; break;
} }
/*----Restore RFENV control type----*/; /*----Restore RFENV control type----*/;
switch (eRFPath) switch (eRFPath) {
{
case RF_PATH_A: case RF_PATH_A:
case RF_PATH_C: case RF_PATH_C:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
break; break;
case RF_PATH_B : case RF_PATH_B:
case RF_PATH_D: case RF_PATH_D:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
break; break;
} }
if (rtStatus != _SUCCESS) if (rtStatus != _SUCCESS)
goto phy_RF6052_Config_ParaFile_Fail; goto phy_RF6052_Config_ParaFile_Fail;
} }
return rtStatus; return rtStatus;
phy_RF6052_Config_ParaFile_Fail: phy_RF6052_Config_ParaFile_Fail:
return rtStatus; return rtStatus;
} }
int PHY_RF6052_Config8188E(struct adapter *Adapter)
int
PHY_RF6052_Config8188E(
struct adapter * Adapter)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
int rtStatus = _SUCCESS; int rtStatus = _SUCCESS;
/* */ /* */
/* Initialize general global value */ /* Initialize general global value */
@ -673,5 +581,3 @@ PHY_RF6052_Config8188E(
rtStatus = phy_RF6052_Config_ParaFile(Adapter); rtStatus = phy_RF6052_Config_ParaFile(Adapter);
return rtStatus; return rtStatus;
} }
/* End of HalRf6052.c */