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rtl8188eu: Fix checkpatch errors in hal/rtl8188e_mp.c, hal/rtl8188e_phycfg.c, and hal/rtl8188e_rf6052.c

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2013-08-08 09:31:29 -05:00
parent 9c3c9ddc8c
commit f527ca59c9
3 changed files with 709 additions and 1013 deletions
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294
hal/rtl8188e_mp.c
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@ -21,57 +21,55 @@
#include <drv_types.h>
#include <rtw_mp.h>
#include <rtl8188e_hal.h>
#include <rtl8188e_dm.h>
s32 Hal_SetPowerTracking(struct adapter * padapter, u8 enable)
s32 Hal_SetPowerTracking(struct adapter *padapter, u8 enable)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
struct odm_dm_struct * pDM_Odm = &(pHalData->odmpriv);
struct odm_dm_struct *pDM_Odm = &(pHalData->odmpriv);
if (!netif_running(padapter->pnetdev)) {
RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: interface not opened!\n"));
RT_TRACE(_module_mp_, _drv_warning_,
("SetPowerTracking! Fail: interface not opened!\n"));
return _FAIL;
}
if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == false) {
RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: not in MP mode!\n"));
if (!check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE)) {
RT_TRACE(_module_mp_, _drv_warning_,
("SetPowerTracking! Fail: not in MP mode!\n"));
return _FAIL;
}
if (enable)
{
pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true;
}
else
pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit= false;
pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = false;
return _SUCCESS;
}
void Hal_GetPowerTracking(struct adapter * padapter, u8 *enable)
void Hal_GetPowerTracking(struct adapter *padapter, u8 *enable)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
struct odm_dm_struct * pDM_Odm = &(pHalData->odmpriv);
struct odm_dm_struct *pDM_Odm = &(pHalData->odmpriv);
*enable = pDM_Odm->RFCalibrateInfo.TxPowerTrackControl;
}
static void Hal_disable_dm(struct adapter * padapter)
static void Hal_disable_dm(struct adapter *padapter)
{
u8 v8;
struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
struct odm_dm_struct * pDM_Odm = &(pHalData->odmpriv);
struct odm_dm_struct *pDM_Odm = &(pHalData->odmpriv);
/* 3 1. disable firmware dynamic mechanism */
@ -108,7 +106,7 @@ static void Hal_disable_dm(struct adapter * padapter)
* 01/09/2009 MHC Add CCK modification for 40MHZ. Suggestion from SD3.
*
*---------------------------------------------------------------------------*/
void Hal_mpt_SwitchRfSetting(struct adapter * pAdapter)
void Hal_mpt_SwitchRfSetting(struct adapter *pAdapter)
{
/* struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter); */
struct mp_priv *pmp = &pAdapter->mppriv;
@ -123,31 +121,27 @@ void Hal_mpt_SwitchRfSetting(struct adapter * pAdapter)
PHY_SetRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD);
PHY_SetRFReg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD);
return ;
return;
}
/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
void Hal_MPT_CCKTxPowerAdjust(struct adapter * Adapter, bool bInCH14)
void Hal_MPT_CCKTxPowerAdjust(struct adapter *Adapter, bool bInCH14)
{
u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0;
u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12;
u8 i;
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
/* get current cck swing value and check 0xa22 & 0xa23 later to match the table. */
CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
if (!bInCH14)
{
if (!bInCH14) {
/* Readback the current bb cck swing value and compare with the table to */
/* get the current swing index */
for (i = 0; i < CCK_TABLE_SIZE; i++)
{
for (i = 0; i < CCK_TABLE_SIZE; i++) {
if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&
(((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1]))
{
(((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1])) {
CCKSwingIndex = i;
break;
}
@ -155,28 +149,24 @@ void Hal_MPT_CCKTxPowerAdjust(struct adapter * Adapter, bool bInCH14)
/* Write 0xa22 0xa23 */
TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] +
(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8) ;
(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8);
/* Write 0xa24 ~ 0xa27 */
TempVal2 = 0;
TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] +
(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3]<<8) +
(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16 )+
(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16)+
(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5]<<24);
/* Write 0xa28 0xa29 */
TempVal3 = 0;
TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +
(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8) ;
}
else
{
for (i = 0; i < CCK_TABLE_SIZE; i++)
{
(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8);
} else {
for (i = 0; i < CCK_TABLE_SIZE; i++) {
if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch14[i][0]) &&
(((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1]))
{
(((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1])) {
CCKSwingIndex = i;
break;
}
@ -184,19 +174,19 @@ void Hal_MPT_CCKTxPowerAdjust(struct adapter * Adapter, bool bInCH14)
/* Write 0xa22 0xa23 */
TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] +
(CCKSwingTable_Ch14[CCKSwingIndex][1]<<8) ;
(CCKSwingTable_Ch14[CCKSwingIndex][1]<<8);
/* Write 0xa24 ~ 0xa27 */
TempVal2 = 0;
TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] +
(CCKSwingTable_Ch14[CCKSwingIndex][3]<<8) +
(CCKSwingTable_Ch14[CCKSwingIndex][4]<<16 )+
(CCKSwingTable_Ch14[CCKSwingIndex][4]<<16)+
(CCKSwingTable_Ch14[CCKSwingIndex][5]<<24);
/* Write 0xa28 0xa29 */
TempVal3 = 0;
TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] +
(CCKSwingTable_Ch14[CCKSwingIndex][7]<<8) ;
(CCKSwingTable_Ch14[CCKSwingIndex][7]<<8);
}
write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
@ -204,7 +194,7 @@ void Hal_MPT_CCKTxPowerAdjust(struct adapter * Adapter, bool bInCH14)
write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
}
void Hal_MPT_CCKTxPowerAdjustbyIndex(struct adapter * pAdapter, bool beven)
void Hal_MPT_CCKTxPowerAdjustbyIndex(struct adapter *pAdapter, bool beven)
{
s32 TempCCk;
u8 CCK_index, CCK_index_old;
@ -212,44 +202,36 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(struct adapter * pAdapter, bool beven)
u8 TimeOut = 100;
s32 i = 0;
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
struct mpt_context * pMptCtx = &pAdapter->mppriv.MptCtx;
struct mpt_context *pMptCtx = &pAdapter->mppriv.MptCtx;
struct dm_priv *pdmpriv = &pHalData->dmpriv;
struct odm_dm_struct * pDM_Odm = &(pHalData->odmpriv);
struct odm_dm_struct *pDM_Odm = &(pHalData->odmpriv);
if (!IS_92C_SERIAL(pHalData->VersionID))
return;
if (beven && !pMptCtx->bMptIndexEven) /* odd->even */
{
if (beven && !pMptCtx->bMptIndexEven) {
/* odd->even */
Action = 2;
pMptCtx->bMptIndexEven = true;
}
else if (!beven && pMptCtx->bMptIndexEven) /* even->odd */
{
} else if (!beven && pMptCtx->bMptIndexEven) {
/* even->odd */
Action = 1;
pMptCtx->bMptIndexEven = false;
}
if (Action != 0)
{
if (Action != 0) {
/* Query CCK default setting From 0xa24 */
TempCCk = read_bbreg(pAdapter, rCCK0_TxFilter2, bMaskDWord) & bMaskCCK;
for (i = 0; i < CCK_TABLE_SIZE; i++)
{
if (pDM_Odm->RFCalibrateInfo.bCCKinCH14)
{
if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4) == true)
{
CCK_index_old = (u8) i;
for (i = 0; i < CCK_TABLE_SIZE; i++) {
if (pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
if (_rtw_memcmp((void *)&TempCCk, (void *)&CCKSwingTable_Ch14[i][2], 4)) {
CCK_index_old = (u8)i;
break;
}
}
else
{
if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4) == true)
{
CCK_index_old = (u8) i;
} else {
if (_rtw_memcmp((void *)&TempCCk, (void *)&CCKSwingTable_Ch1_Ch13[i][2], 4)) {
CCK_index_old = (u8)i;
break;
}
}
@ -290,14 +272,14 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(struct adapter * pAdapter, bool beven)
* Use H2C command to change channel,
* not only modify rf register, but also other setting need to be done.
*/
void Hal_SetChannel(struct adapter * pAdapter)
void Hal_SetChannel(struct adapter *pAdapter)
{
u8 eRFPath;
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
struct mp_priv *pmp = &pAdapter->mppriv;
struct dm_priv *pdmpriv = &pHalData->dmpriv;
struct odm_dm_struct * pDM_Odm = &(pHalData->odmpriv);
struct odm_dm_struct *pDM_Odm = &(pHalData->odmpriv);
u8 channel = pmp->channel;
u8 bandwidth = pmp->bandwidth;
@ -305,8 +287,7 @@ void Hal_SetChannel(struct adapter * pAdapter)
/* set RF channel register */
for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)
{
for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
if (IS_HARDWARE_TYPE_8192D(pAdapter))
_write_rfreg(pAdapter, (enum rf_radio_path)eRFPath, ODM_CHANNEL, 0xFF, channel);
else
@ -319,8 +300,7 @@ void Hal_SetChannel(struct adapter * pAdapter)
if (pHalData->CurrentChannel == 14 && !pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
pDM_Odm->RFCalibrateInfo.bCCKinCH14 = true;
Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14);
}
else if (pHalData->CurrentChannel != 14 && pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
} else if (pHalData->CurrentChannel != 14 && pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
pDM_Odm->RFCalibrateInfo.bCCKinCH14 = false;
Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14);
}
@ -330,7 +310,7 @@ void Hal_SetChannel(struct adapter * pAdapter)
* Notice
* Switch bandwitdth may change center frequency(channel)
*/
void Hal_SetBandwidth(struct adapter * pAdapter)
void Hal_SetBandwidth(struct adapter *pAdapter)
{
struct mp_priv *pmp = &pAdapter->mppriv;
@ -339,7 +319,7 @@ void Hal_SetBandwidth(struct adapter * pAdapter)
Hal_mpt_SwitchRfSetting(pAdapter);
}
void Hal_SetCCKTxPower(struct adapter * pAdapter, u8 *TxPower)
void Hal_SetCCKTxPower(struct adapter *pAdapter, u8 *TxPower)
{
u32 tmpval = 0;
@ -359,7 +339,7 @@ void Hal_SetCCKTxPower(struct adapter * pAdapter, u8 *TxPower)
TxPower[RF_PATH_A], TxPower[RF_PATH_B]));
}
void Hal_SetOFDMTxPower(struct adapter * pAdapter, u8 *TxPower)
void Hal_SetOFDMTxPower(struct adapter *pAdapter, u8 *TxPower)
{
u32 TxAGC = 0;
u8 tmpval = 0;
@ -388,10 +368,9 @@ void Hal_SetOFDMTxPower(struct adapter * pAdapter, u8 *TxPower)
write_bbreg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
write_bbreg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
write_bbreg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
}
void Hal_SetAntennaPathPower(struct adapter * pAdapter)
void Hal_SetAntennaPathPower(struct adapter *pAdapter)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
u8 TxPowerLevel[MAX_RF_PATH_NUMS];
@ -400,8 +379,7 @@ void Hal_SetAntennaPathPower(struct adapter * pAdapter)
TxPowerLevel[RF_PATH_A] = pAdapter->mppriv.txpoweridx;
TxPowerLevel[RF_PATH_B] = pAdapter->mppriv.txpoweridx_b;
switch (pAdapter->mppriv.antenna_tx)
{
switch (pAdapter->mppriv.antenna_tx) {
case ANTENNA_A:
default:
rfPath = RF_PATH_A;
@ -414,8 +392,7 @@ void Hal_SetAntennaPathPower(struct adapter * pAdapter)
break;
}
switch (pHalData->rf_chip)
{
switch (pHalData->rf_chip) {
case RF_8225:
case RF_8256:
case RF_6052:
@ -424,25 +401,22 @@ void Hal_SetAntennaPathPower(struct adapter * pAdapter)
Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);
Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
break;
default:
break;
}
}
void Hal_SetTxPower(struct adapter * pAdapter)
void Hal_SetTxPower(struct adapter *pAdapter)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
u8 TxPower = pAdapter->mppriv.txpoweridx;
u8 TxPowerLevel[MAX_RF_PATH_NUMS];
u8 rf, rfPath;
for (rf = 0; rf < MAX_RF_PATH_NUMS; rf++) {
for (rf = 0; rf < MAX_RF_PATH_NUMS; rf++)
TxPowerLevel[rf] = TxPower;
}
switch (pAdapter->mppriv.antenna_tx)
{
switch (pAdapter->mppriv.antenna_tx) {
case ANTENNA_A:
default:
rfPath = RF_PATH_A;
@ -455,8 +429,7 @@ void Hal_SetTxPower(struct adapter * pAdapter)
break;
}
switch (pHalData->rf_chip)
{
switch (pHalData->rf_chip) {
/* 2008/09/12 MH Test only !! We enable the TX power tracking for MP!!!!! */
/* We should call normal driver API later!! */
case RF_8225:
@ -467,24 +440,22 @@ void Hal_SetTxPower(struct adapter * pAdapter)
Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);
Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
break;
default:
break;
}
}
void Hal_SetDataRate(struct adapter * pAdapter)
void Hal_SetDataRate(struct adapter *pAdapter)
{
Hal_mpt_SwitchRfSetting(pAdapter);
}
void Hal_SetAntenna(struct adapter * pAdapter)
void Hal_SetAntenna(struct adapter *pAdapter)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
struct ant_sel_ofdm *p_ofdm_tx; /* OFDM Tx register */
struct ant_sel_cck *p_cck_txrx;
u8 r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
u8 chgTx = 0, chgRx = 0;
u32 r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
@ -497,8 +468,7 @@ void Hal_SetAntenna(struct adapter * pAdapter)
p_ofdm_tx->r_ant_ht2 = 0x2; /* Second TX RF path is A */
p_ofdm_tx->r_ant_non_ht = 0x3; /* 0x1+0x2=0x3 */
switch (pAdapter->mppriv.antenna_tx)
{
switch (pAdapter->mppriv.antenna_tx) {
case ANTENNA_A:
p_ofdm_tx->r_tx_antenna = 0x1;
r_ofdm_tx_en_val = 0x1;
@ -514,11 +484,9 @@ void Hal_SetAntenna(struct adapter * pAdapter)
r_ofdm_tx_en_val = 0x3;
/* Power save */
/* cosa r_ant_select_ofdm_val = 0x11111111; */
/* We need to close RFB by SW control */
if (pHalData->rf_type == RF_2T2R)
{
if (pHalData->rf_type == RF_2T2R) {
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
@ -526,7 +494,6 @@ void Hal_SetAntenna(struct adapter * pAdapter)
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
}
break;
case ANTENNA_B:
p_ofdm_tx->r_tx_antenna = 0x2;
r_ofdm_tx_en_val = 0x2;
@ -535,7 +502,6 @@ void Hal_SetAntenna(struct adapter * pAdapter)
p_ofdm_tx->r_ant_non_ht_s1 = 0x2;
p_cck_txrx->r_ccktx_enable = 0x4;
chgTx = 1;
/* From SD3 Willis suggestion !!! Set RF A as standby */
PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
@ -545,8 +511,7 @@ void Hal_SetAntenna(struct adapter * pAdapter)
/* 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table. */
/* 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control */
if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R)
{
if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
@ -554,7 +519,6 @@ void Hal_SetAntenna(struct adapter * pAdapter)
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
}
break;
case ANTENNA_AB: /* For 8192S */
p_ofdm_tx->r_tx_antenna = 0x3;
r_ofdm_tx_en_val = 0x3;
@ -571,8 +535,7 @@ void Hal_SetAntenna(struct adapter * pAdapter)
/* Disable Power save */
/* cosa r_ant_select_ofdm_val = 0x3321333; */
/* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control */
if (pHalData->rf_type == RF_2T2R)
{
if (pHalData->rf_type == RF_2T2R) {
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
@ -583,42 +546,34 @@ void Hal_SetAntenna(struct adapter * pAdapter)
break;
}
/* */
/* r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
/* r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
/* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D */
/* */
switch (pAdapter->mppriv.antenna_rx)
{
switch (pAdapter->mppriv.antenna_rx) {
case ANTENNA_A:
r_rx_antenna_ofdm = 0x1; /* A */
p_cck_txrx->r_cckrx_enable = 0x0; /* default: A */
p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A */
chgRx = 1;
break;
case ANTENNA_B:
r_rx_antenna_ofdm = 0x2; /* B */
p_cck_txrx->r_cckrx_enable = 0x1; /* default: B */
p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option: B */
chgRx = 1;
break;
case ANTENNA_AB:
r_rx_antenna_ofdm = 0x3; /* AB */
p_cck_txrx->r_cckrx_enable = 0x0; /* default:A */
p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option:B */
chgRx = 1;
break;
default:
break;
}
if (chgTx && chgRx)
{
switch (pHalData->rf_chip)
{
if (chgTx && chgRx) {
switch (pHalData->rf_chip) {
case RF_8225:
case RF_8256:
case RF_6052:
@ -630,7 +585,6 @@ void Hal_SetAntenna(struct adapter * pAdapter)
PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val); /* CCK TxRx */
break;
default:
break;
}
@ -639,7 +593,7 @@ void Hal_SetAntenna(struct adapter * pAdapter)
RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
}
s32 Hal_SetThermalMeter(struct adapter * pAdapter, u8 target_ther)
s32 Hal_SetThermalMeter(struct adapter *pAdapter, u8 target_ther)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
@ -665,13 +619,12 @@ s32 Hal_SetThermalMeter(struct adapter * pAdapter, u8 target_ther)
return _SUCCESS;
}
void Hal_TriggerRFThermalMeter(struct adapter * pAdapter)
void Hal_TriggerRFThermalMeter(struct adapter *pAdapter)
{
_write_rfreg( pAdapter, RF_PATH_A , RF_T_METER_88E , BIT17 |BIT16 , 0x03 );
_write_rfreg(pAdapter, RF_PATH_A , RF_T_METER_88E , BIT17 | BIT16 , 0x03);
}
u8 Hal_ReadRFThermalMeter(struct adapter * pAdapter)
u8 Hal_ReadRFThermalMeter(struct adapter *pAdapter)
{
u32 ThermalValue = 0;
@ -679,30 +632,29 @@ u8 Hal_ReadRFThermalMeter(struct adapter * pAdapter)
return (u8)ThermalValue;
}
void Hal_GetThermalMeter(struct adapter * pAdapter, u8 *value)
void Hal_GetThermalMeter(struct adapter *pAdapter, u8 *value)
{
Hal_TriggerRFThermalMeter(pAdapter);
rtw_msleep_os(1000);
*value = Hal_ReadRFThermalMeter(pAdapter);
}
void Hal_SetSingleCarrierTx(struct adapter * pAdapter, u8 bStart)
void Hal_SetSingleCarrierTx(struct adapter *pAdapter, u8 bStart)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;
if (bStart)/* Start Single Carrier. */
{
RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test start\n"));
if (bStart) {
/* Start Single Carrier. */
RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleCarrierTx: test start\n"));
/* 1. if OFDM block on? */
if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);/* set OFDM block on */
{
/* 2. set CCK test mode off, set to CCK normal mode */
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
/* 3. turn on scramble setting */
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
}
/* 4. Turn On Single Carrier Tx and turn off the other test modes. */
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);
@ -710,11 +662,9 @@ void Hal_SetSingleCarrierTx(struct adapter * pAdapter, u8 bStart)
/* for dynamic set Power index. */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
}
else/* Stop Single Carrier. */
{
RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test stop\n"));
} else {
/* Stop Single Carrier. */
RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleCarrierTx: test stop\n"));
/* Turn off all test modes. */
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
@ -729,20 +679,18 @@ void Hal_SetSingleCarrierTx(struct adapter * pAdapter, u8 bStart)
/* Stop for dynamic set Power index. */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
}
}
void Hal_SetSingleToneTx(struct adapter * pAdapter, u8 bStart)
void Hal_SetSingleToneTx(struct adapter *pAdapter, u8 bStart)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
bool is92C = IS_92C_SERIAL(pHalData->VersionID);
u8 rfPath;
u32 reg58 = 0x0;
switch (pAdapter->mppriv.antenna_tx)
{
switch (pAdapter->mppriv.antenna_tx) {
case ANTENNA_A:
default:
rfPath = RF_PATH_A;
@ -756,12 +704,11 @@ void Hal_SetSingleToneTx(struct adapter * pAdapter, u8 bStart)
}
pAdapter->mppriv.MptCtx.bSingleTone = bStart;
if (bStart)/* Start Single Tone. */
{
RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test start\n"));
{ /* <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu) */
if (IS_HARDWARE_TYPE_8188E(pAdapter))
{
if (bStart) {
/* Start Single Tone. */
RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleToneTx: test start\n"));
/* <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu) */
if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask);
reg58 &= 0xFFFFFFF0;
reg58 += 2;
@ -769,10 +716,8 @@ void Hal_SetSingleToneTx(struct adapter * pAdapter, u8 bStart)
}
PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
}
if (is92C)
{
if (is92C) {
_write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x01);
rtw_usleep_os(100);
if (rfPath == RF_PATH_A)
@ -781,9 +726,7 @@ void Hal_SetSingleToneTx(struct adapter * pAdapter, u8 bStart)
write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x10000); /* PAD all on. */
write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); /* PAD all on. */
rtw_usleep_os(100);
}
else
{
} else {
write_rfreg(pAdapter, rfPath, 0x21, 0xd4000);
rtw_usleep_os(100);
write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); /* PAD all on. */
@ -794,23 +737,19 @@ void Hal_SetSingleToneTx(struct adapter * pAdapter, u8 bStart)
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
}
else/* Stop Single Tone. */
{
RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test stop\n"));
} else {
/* Stop Single Tone. */
RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleToneTx: test stop\n"));
{ /* <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu) */
/* <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu) */
/* <20120326, Kordan> Only in single tone mode. (asked by Edlu) */
if (IS_HARDWARE_TYPE_8188E(pAdapter))
{
if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask);
reg58 &= 0xFFFFFFF0;
PHY_SetRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, reg58);
}
write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
}
if (is92C) {
_write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x00);
rtw_usleep_os(100);
@ -827,21 +766,18 @@ void Hal_SetSingleToneTx(struct adapter * pAdapter, u8 bStart)
/* Stop for dynamic set Power index. */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
}
}
void Hal_SetCarrierSuppressionTx(struct adapter * pAdapter, u8 bStart)
void Hal_SetCarrierSuppressionTx(struct adapter *pAdapter, u8 bStart)
{
pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;
if (bStart) /* Start Carrier Suppression. */
{
RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test start\n"));
if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)
{
if (bStart) {
/* Start Carrier Suppression. */
RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test start\n"));
if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) {
/* 1. if CCK block on? */
if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/* set CCK block on */
@ -861,12 +797,10 @@ void Hal_SetCarrierSuppressionTx(struct adapter * pAdapter, u8 bStart)
/* for dynamic set Power index. */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
}
else/* Stop Carrier Suppression. */
{
RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test stop\n"));
if (pAdapter->mppriv.rateidx <= MPT_RATE_11M ) {
} else {
/* Stop Carrier Suppression. */
RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test stop\n"));
if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) {
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /* normal mode */
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /* turn on scramble setting */
@ -878,16 +812,14 @@ void Hal_SetCarrierSuppressionTx(struct adapter * pAdapter, u8 bStart)
/* Stop for dynamic set Power index. */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
}
}
void Hal_SetCCKContinuousTx(struct adapter * pAdapter, u8 bStart)
void Hal_SetCCKContinuousTx(struct adapter *pAdapter, u8 bStart)
{
u32 cckrate;
if (bStart)
{
if (bStart) {
RT_TRACE(_module_mp_, _drv_alert_,
("SetCCKContinuousTx: test start\n"));
@ -908,9 +840,7 @@ void Hal_SetCCKContinuousTx(struct adapter * pAdapter, u8 bStart)
/* for dynamic set Power index. */
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
}
else {
} else {
RT_TRACE(_module_mp_, _drv_info_,
("SetCCKContinuousTx: test stop\n"));
@ -928,9 +858,9 @@ void Hal_SetCCKContinuousTx(struct adapter * pAdapter, u8 bStart)
pAdapter->mppriv.MptCtx.bCckContTx = bStart;
pAdapter->mppriv.MptCtx.bOfdmContTx = false;
}/* mpt_StartCckContTx */
} /* mpt_StartCckContTx */
void Hal_SetOFDMContinuousTx(struct adapter * pAdapter, u8 bStart)
void Hal_SetOFDMContinuousTx(struct adapter *pAdapter, u8 bStart)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
@ -939,14 +869,12 @@ void Hal_SetOFDMContinuousTx(struct adapter * pAdapter, u8 bStart)
/* 1. if OFDM block on? */
if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);/* set OFDM block on */
{
/* 2. set CCK test mode off, set to CCK normal mode */
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
/* 3. turn on scramble setting */
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
}
/* 4. Turn On Continue Tx and turn off the other test modes. */
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
@ -957,7 +885,7 @@ void Hal_SetOFDMContinuousTx(struct adapter * pAdapter, u8 bStart)
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
} else {
RT_TRACE(_module_mp_,_drv_info_, ("SetOFDMContinuousTx: test stop\n"));
RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test stop\n"));
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
@ -974,21 +902,17 @@ void Hal_SetOFDMContinuousTx(struct adapter * pAdapter, u8 bStart)
pAdapter->mppriv.MptCtx.bCckContTx = false;
pAdapter->mppriv.MptCtx.bOfdmContTx = bStart;
}/* mpt_StartOfdmContTx */
} /* mpt_StartOfdmContTx */
void Hal_SetContinuousTx(struct adapter * pAdapter, u8 bStart)
void Hal_SetContinuousTx(struct adapter *pAdapter, u8 bStart)
{
RT_TRACE(_module_mp_, _drv_info_,
("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx));
pAdapter->mppriv.MptCtx.bStartContTx = bStart;
if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)
{
Hal_SetCCKContinuousTx(pAdapter, bStart);
}
else if ((pAdapter->mppriv.rateidx >= MPT_RATE_6M) &&
(pAdapter->mppriv.rateidx <= MPT_RATE_MCS15))
{
Hal_SetOFDMContinuousTx(pAdapter, bStart);
}
}

368
hal/rtl8188e_phycfg.c
View file

@ -60,20 +60,15 @@
* Output: none
* Return: u4Byte Return the shift bit bit position of the mask
*/
static u32
phy_CalculateBitShift(
u32 BitMask
)
static u32 phy_CalculateBitShift(u32 BitMask)
{
u32 i;
for (i=0; i<=31; i++)
{
if ( ((BitMask>>i) & 0x1 ) == 1)
for (i = 0; i <= 31; i++) {
if (((BitMask>>i) & 0x1) == 1)
break;
}
return (i);
return i;
}
/**
@ -82,7 +77,7 @@ phy_CalculateBitShift(
* OverView: Read "sepcific bits" from BB register
*
* Input:
* struct adapter * Adapter,
* struct adapter *Adapter,
* u4Byte RegAddr, The target address to be readback
* u4Byte BitMask The target bit position in the target address
* to be readback
@ -92,7 +87,7 @@ phy_CalculateBitShift(
*/
u32
rtl8188e_PHY_QueryBBReg(
struct adapter * Adapter,
struct adapter *Adapter,
u32 RegAddr,
u32 BitMask
)
@ -103,7 +98,7 @@ rtl8188e_PHY_QueryBBReg(
OriginalValue = rtw_read32(Adapter, RegAddr);
BitShift = phy_CalculateBitShift(BitMask);
ReturnValue = (OriginalValue & BitMask) >> BitShift;
return (ReturnValue);
return ReturnValue;
}
@ -113,7 +108,7 @@ rtl8188e_PHY_QueryBBReg(
* OverView: Write "Specific bits" to BB register (page 8~)
*
* Input:
* struct adapter * Adapter,
* struct adapter *Adapter,
* u4Byte RegAddr, The target address to be modified
* u4Byte BitMask The target bit position in the target address
* to be modified
@ -125,18 +120,12 @@ rtl8188e_PHY_QueryBBReg(
* Note: This function is equal to "PutRegSetting" in PHY programming guide
*/
void
rtl8188e_PHY_SetBBReg(
struct adapter * Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data
)
void rtl8188e_PHY_SetBBReg(struct adapter *Adapter, u32 RegAddr, u32 BitMask, u32 Data)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
u32 OriginalValue, BitShift;
if (BitMask!= bMaskDWord){/* if not "double word" write */
if (BitMask != bMaskDWord) { /* if not "double word" write */
OriginalValue = rtw_read32(Adapter, RegAddr);
BitShift = phy_CalculateBitShift(BitMask);
Data = ((OriginalValue & (~BitMask)) | (Data << BitShift));
@ -155,7 +144,7 @@ rtl8188e_PHY_SetBBReg(
* OverView: Read regster from RF chips
*
* Input:
* struct adapter * Adapter,
* struct adapter *Adapter,
* enum rf_radio_path eRFPath, Radio path of A/B/C/D
* u4Byte Offset, The target address to be read
*
@ -170,7 +159,7 @@ rtl8188e_PHY_SetBBReg(
*/
static u32
phy_RFSerialRead(
struct adapter * Adapter,
struct adapter *Adapter,
enum rf_radio_path eRFPath,
u32 Offset
)
@ -179,8 +168,8 @@ phy_RFSerialRead(
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
struct bb_reg_def *pPhyReg = &pHalData->PHYRegDef[eRFPath];
u32 NewOffset;
u32 tmplong,tmplong2;
u8 RfPiEnable=0;
u32 tmplong, tmplong2;
u8 RfPiEnable = 0;
/* */
/* Make sure RF register offset is correct */
/* */
@ -215,15 +204,11 @@ phy_RFSerialRead(
else if (eRFPath == RF_PATH_B)
RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1, BIT8);
if (RfPiEnable)
{ /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
if (RfPiEnable) { /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);
}
else
{ /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
} else { /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
}
return retValue;
}
@ -233,7 +218,7 @@ phy_RFSerialRead(
* OverView: Write data to RF register (page 8~)
*
* Input:
* struct adapter * Adapter,
* struct adapter *Adapter,
* enum rf_radio_path eRFPath, Radio path of A/B/C/D
* u4Byte Offset, The target address to be read
* u4Byte Data The new register Data in the target bit position
@ -272,7 +257,7 @@ phy_RFSerialRead(
*/
static void
phy_RFSerialWrite(
struct adapter * Adapter,
struct adapter *Adapter,
enum rf_radio_path eRFPath,
u32 Offset,
u32 Data
@ -310,7 +295,7 @@ phy_RFSerialWrite(
* OverView: Query "Specific bits" to RF register (page 8~)
*
* Input:
* struct adapter * Adapter,
* struct adapter *Adapter,
* enum rf_radio_path eRFPath, Radio path of A/B/C/D
* u4Byte RegAddr, The target address to be read
* u4Byte BitMask The target bit position in the target address
@ -320,7 +305,7 @@ phy_RFSerialWrite(
* Return: u4Byte Readback value
* Note: This function is equal to "GetRFRegSetting" in PHY programming guide
*/
u32 rtl8188e_PHY_QueryRFReg(struct adapter * Adapter, enum rf_radio_path eRFPath,
u32 rtl8188e_PHY_QueryRFReg(struct adapter *Adapter, enum rf_radio_path eRFPath,
u32 RegAddr, u32 BitMask)
{
u32 Original_Value, Readback_Value, BitShift;
@ -329,7 +314,7 @@ u32 rtl8188e_PHY_QueryRFReg(struct adapter * Adapter, enum rf_radio_path eRFPath
BitShift = phy_CalculateBitShift(BitMask);
Readback_Value = (Original_Value & BitMask) >> BitShift;
return (Readback_Value);
return Readback_Value;
}
/**
@ -338,7 +323,7 @@ u32 rtl8188e_PHY_QueryRFReg(struct adapter * Adapter, enum rf_radio_path eRFPath
* OverView: Write "Specific bits" to RF register (page 8~)
*
* Input:
* struct adapter * Adapter,
* struct adapter *Adapter,
* enum rf_radio_path eRFPath, Radio path of A/B/C/D
* u4Byte RegAddr, The target address to be modified
* u4Byte BitMask The target bit position in the target address
@ -352,7 +337,7 @@ u32 rtl8188e_PHY_QueryRFReg(struct adapter * Adapter, enum rf_radio_path eRFPath
*/
void
rtl8188e_PHY_SetRFReg(
struct adapter * Adapter,
struct adapter *Adapter,
enum rf_radio_path eRFPath,
u32 RegAddr,
u32 BitMask,
@ -362,11 +347,10 @@ rtl8188e_PHY_SetRFReg(
u32 Original_Value, BitShift;
/* RF data is 12 bits only */
if (BitMask != bRFRegOffsetMask)
{
if (BitMask != bRFRegOffsetMask) {
Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);
BitShift = phy_CalculateBitShift(BitMask);
Data = ((Original_Value & (~BitMask)) | (Data<< BitShift));
Data = ((Original_Value & (~BitMask)) | (Data << BitShift));
}
phy_RFSerialWrite(Adapter, eRFPath, RegAddr, Data);
@ -382,7 +366,7 @@ rtl8188e_PHY_SetRFReg(
* Overview: This function read BB parameters from general file format, and do register
* Read/Write
*
* Input: struct adapter * Adapter
* Input: struct adapter *Adapter
* ps1Byte pFileName
*
* Output: NONE
@ -392,11 +376,7 @@ rtl8188e_PHY_SetRFReg(
* Note: The format of MACPHY_REG.txt is different from PHY and RF.
* [Register][Mask][Value]
*---------------------------------------------------------------------------*/
static int
phy_ConfigMACWithParaFile(
struct adapter * Adapter,
u8* pFileName
)
static int phy_ConfigMACWithParaFile(struct adapter *Adapter, u8 *pFileName)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
@ -421,7 +401,7 @@ phy_ConfigMACWithParaFile(
* 08/12/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
s32 PHY_MACConfig8188E(struct adapter * Adapter)
s32 PHY_MACConfig8188E(struct adapter *Adapter)
{
int rtStatus = _SUCCESS;
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
@ -445,7 +425,7 @@ s32 PHY_MACConfig8188E(struct adapter * Adapter)
* OverView: Initialize Register definition offset for Radio Path A/B/C/D
*
* Input:
* struct adapter * Adapter,
* struct adapter *Adapter,
*
* Output: None
* Return: None
@ -453,7 +433,7 @@ s32 PHY_MACConfig8188E(struct adapter * Adapter)
*/
static void
phy_InitBBRFRegisterDefinition(
struct adapter * Adapter
struct adapter *Adapter
)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
@ -561,7 +541,7 @@ phy_InitBBRFRegisterDefinition(
* Overview: This function read BB parameters from general file format, and do register
* Read/Write
*
* Input: struct adapter * Adapter
* Input: struct adapter *Adapter
* ps1Byte pFileName
*
* Output: NONE
@ -571,44 +551,17 @@ phy_InitBBRFRegisterDefinition(
* parameter file compare!!!!!!??
*
*---------------------------------------------------------------------------*/
static int
phy_ConfigBBWithParaFile(
struct adapter * Adapter,
u8* pFileName
)
static int phy_ConfigBBWithParaFile(struct adapter *Adapter, u8 *pFileName)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
int rtStatus = _SUCCESS;
return rtStatus;
return _SUCCESS;
}
/* */
/* The following is for High Power PA */
/* */
static void phy_ConfigBBExternalPA(struct adapter * Adapter)
static void phy_ConfigBBExternalPA(struct adapter *Adapter)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
u16 i=0;
u32 temp=0;
if (!pHalData->ExternalPA)
return;
/* 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the */
/* same code as SU. It is already updated in PHY_REG_1T_HP.txt. */
}
void
storePwrIndexDiffRateOffset(
struct adapter * Adapter,
u32 RegAddr,
u32 BitMask,
u32 Data
)
void storePwrIndexDiffRateOffset(struct adapter *Adapter, u32 RegAddr, u32 BitMask, u32 Data)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
@ -628,7 +581,7 @@ storePwrIndexDiffRateOffset(
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4] = Data;
if (RegAddr == rTxAGC_A_Mcs15_Mcs12) {
pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5] = Data;
if (pHalData->rf_type== RF_1T1R)
if (pHalData->rf_type == RF_1T1R)
pHalData->pwrGroupCnt++;
}
if (RegAddr == rTxAGC_B_Rate18_06)
@ -667,24 +620,12 @@ storePwrIndexDiffRateOffset(
* 11/06/2008 MHC Create Version 0.
* 2009/07/29 tynli (porting from 92SE branch)2009/03/11 Add copy parameter file to buffer for silent reset
*---------------------------------------------------------------------------*/
static int
phy_ConfigBBWithPgParaFile(
struct adapter * Adapter,
u8* pFileName)
static int phy_ConfigBBWithPgParaFile(struct adapter *Adapter, u8 *pFileName)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
return _SUCCESS;
}
int rtStatus = _SUCCESS;
return rtStatus;
} /* phy_ConfigBBWithPgParaFile */
static void
phy_BB8192C_Config_1T(
struct adapter * Adapter
)
static void phy_BB8192C_Config_1T(struct adapter *Adapter)
{
/* for path - B */
PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x2);
@ -709,7 +650,7 @@ phy_BB8192C_Config_1T(
/* Now it is just for 8256. */
static int
phy_BB8190_Config_HardCode(
struct adapter * Adapter
struct adapter *Adapter
)
{
return _SUCCESS;
@ -717,7 +658,7 @@ phy_BB8190_Config_HardCode(
static int
phy_BB8188E_Config_ParaFile(
struct adapter * Adapter
struct adapter *Adapter
)
{
struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
@ -733,29 +674,24 @@ phy_BB8188E_Config_ParaFile(
/* 1. Read PHY_REG.TXT BB INIT!! */
/* We will seperate as 88C / 92C according to chip version */
/* */
if (HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
if (HAL_STATUS_FAILURE == ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
rtStatus = _FAIL;
if (rtStatus != _SUCCESS)
goto phy_BB8190_Config_ParaFile_Fail;
/* */
/* 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */
/* */
if (pEEPROM->bautoload_fail_flag == false)
{
if (!pEEPROM->bautoload_fail_flag) {
pHalData->pwrGroupCnt = 0;
if (HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_PG))
if (HAL_STATUS_FAILURE == ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_PG))
rtStatus = _FAIL;
}
if (rtStatus != _SUCCESS)
goto phy_BB8190_Config_ParaFile_Fail;
/* */
/* 3. BB AGC table Initialization */
/* */
if (HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
if (HAL_STATUS_FAILURE == ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
rtStatus = _FAIL;
if (rtStatus != _SUCCESS)
@ -768,14 +704,14 @@ phy_BB8190_Config_ParaFile_Fail:
int
PHY_BBConfig8188E(
struct adapter * Adapter
struct adapter *Adapter
)
{
int rtStatus = _SUCCESS;
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
u32 RegVal;
u8 TmpU1B=0;
u8 value8,CrystalCap;
u8 TmpU1B = 0;
u8 value8, CrystalCap;
phy_InitBBRFRegisterDefinition(Adapter);
@ -790,9 +726,7 @@ PHY_BBConfig8188E(
rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
/* */
/* Config BB and AGC */
/* */
rtStatus = phy_BB8188E_Config_ParaFile(Adapter);
/* write 0x24[16:11] = 0x24[22:17] = CrystalCap */
@ -802,17 +736,12 @@ PHY_BBConfig8188E(
return rtStatus;
}
int
PHY_RFConfig8188E(
struct adapter * Adapter
)
int PHY_RFConfig8188E(struct adapter *Adapter)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
int rtStatus = _SUCCESS;
/* */
/* RF config */
/* */
rtStatus = PHY_RF6052_Config8188E(Adapter);
return rtStatus;
}
@ -823,7 +752,7 @@ PHY_RFConfig8188E(
*
* Overview: This function read RF parameters from general file format, and do RF 3-wire
*
* Input: struct adapter * Adapter
* Input: struct adapter *Adapter
* ps1Byte pFileName
* enum rf_radio_path eRFPath
*
@ -833,33 +762,19 @@ PHY_RFConfig8188E(
*
* Note: Delay may be required for RF configuration
*---------------------------------------------------------------------------*/
int
rtl8188e_PHY_ConfigRFWithParaFile(
struct adapter * Adapter,
u8* pFileName,
enum rf_radio_path eRFPath
)
int rtl8188e_PHY_ConfigRFWithParaFile(struct adapter *Adapter, u8 *pFileName, enum rf_radio_path eRFPath)
{
return _SUCCESS;
}
static int PHY_ConfigRFExternalPA(struct adapter * Adapter, enum rf_radio_path eRFPath)
static int PHY_ConfigRFExternalPA(struct adapter *Adapter, enum rf_radio_path eRFPath)
{
int rtStatus = _SUCCESS;
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
u16 i=0;
if (!pHalData->ExternalPA)
return rtStatus;
/* 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the */
/* same code as SU. It is already updated in radio_a_1T_HP.txt. */
return rtStatus;
return _SUCCESS;
}
void
rtl8192c_PHY_GetHWRegOriginalValue(
struct adapter * Adapter
struct adapter *Adapter
)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
@ -882,12 +797,7 @@ rtl8192c_PHY_GetHWRegOriginalValue(
/* current wireless mode. */
/* By Bruce, 2008-01-29. */
/* */
static u8
phy_DbmToTxPwrIdx(
struct adapter * Adapter,
enum wireless_mode WirelessMode,
int PowerInDbm
)
static u8 phy_DbmToTxPwrIdx(struct adapter *Adapter, enum wireless_mode WirelessMode, int PowerInDbm)
{
u8 TxPwrIdx = 0;
int Offset = 0;
@ -900,16 +810,13 @@ phy_DbmToTxPwrIdx(
/* The mapping may be different by different NICs. Do not use this formula for what needs accurate result. */
/* By Bruce, 2008-01-29. */
/* */
switch (WirelessMode)
{
switch (WirelessMode) {
case WIRELESS_MODE_B:
Offset = -7;
break;
case WIRELESS_MODE_G:
case WIRELESS_MODE_N_24G:
Offset = -8;
break;
default:
Offset = -8;
break;
@ -934,7 +841,7 @@ phy_DbmToTxPwrIdx(
/* current wireless mode. */
/* By Bruce, 2008-01-29. */
/* */
static int phy_TxPwrIdxToDbm(struct adapter * Adapter, enum wireless_mode WirelessMode, u8 TxPwrIdx)
static int phy_TxPwrIdxToDbm(struct adapter *Adapter, enum wireless_mode WirelessMode, u8 TxPwrIdx)
{
int Offset = 0;
int PwrOutDbm = 0;
@ -945,15 +852,12 @@ static int phy_TxPwrIdxToDbm(struct adapter * Adapter, enum wireless_mode Wirele
/* The mapping may be different by different NICs. Do not use this formula for what needs accurate result. */
/* By Bruce, 2008-01-29. */
/* */
switch (WirelessMode)
{
switch (WirelessMode) {
case WIRELESS_MODE_B:
Offset = -7;
break;
case WIRELESS_MODE_G:
case WIRELESS_MODE_N_24G:
Offset = -8;
default:
Offset = -8;
break;
@ -970,7 +874,7 @@ static int phy_TxPwrIdxToDbm(struct adapter * Adapter, enum wireless_mode Wirele
*
* Overview: This function is export to "common" moudule
*
* Input: struct adapter * Adapter
* Input: struct adapter *Adapter
* psByte Power Level
*
* Output: NONE
@ -978,11 +882,7 @@ static int phy_TxPwrIdxToDbm(struct adapter * Adapter, enum wireless_mode Wirele
* Return: NONE
*
*---------------------------------------------------------------------------*/
void
PHY_GetTxPowerLevel8188E(
struct adapter * Adapter,
u32* powerlevel
)
void PHY_GetTxPowerLevel8188E(struct adapter *Adapter, u32 *powerlevel)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
u8 TxPwrLevel = 0;
@ -1014,21 +914,21 @@ PHY_GetTxPowerLevel8188E(
*powerlevel = TxPwrDbm;
}
static void getTxPowerIndex88E(struct adapter * Adapter, u8 channel, u8 *cckPowerLevel,
static void getTxPowerIndex88E(struct adapter *Adapter, u8 channel, u8 *cckPowerLevel,
u8 *ofdmPowerLevel, u8 *BW20PowerLevel,
u8 *BW40PowerLevel)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
u8 index = (channel -1);
u8 TxCount=0,path_nums;
u8 index = (channel - 1);
u8 TxCount = 0, path_nums;
if ((RF_1T2R == pHalData->rf_type) || (RF_1T1R ==pHalData->rf_type))
if ((RF_1T2R == pHalData->rf_type) || (RF_1T1R == pHalData->rf_type))
path_nums = 1;
else
path_nums = 2;
for (TxCount=0; TxCount < path_nums; TxCount++) {
if (TxCount==RF_PATH_A) {
for (TxCount = 0; TxCount < path_nums; TxCount++) {
if (TxCount == RF_PATH_A) {
/* 1. CCK */
cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index];
/* 2. OFDM */
@ -1039,7 +939,7 @@ static void getTxPowerIndex88E(struct adapter * Adapter, u8 channel, u8 *cckPowe
pHalData->BW20_24G_Diff[TxCount][RF_PATH_A];
/* 2. BW40 */
BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
} else if (TxCount==RF_PATH_B) {
} else if (TxCount == RF_PATH_B) {
/* 1. CCK */
cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index];
/* 2. OFDM */
@ -1052,7 +952,7 @@ static void getTxPowerIndex88E(struct adapter * Adapter, u8 channel, u8 *cckPowe
pHalData->BW20_24G_Diff[TxCount][index];
/* 2. BW40 */
BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
} else if (TxCount==RF_PATH_C) {
} else if (TxCount == RF_PATH_C) {
/* 1. CCK */
cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index];
/* 2. OFDM */
@ -1067,7 +967,7 @@ static void getTxPowerIndex88E(struct adapter * Adapter, u8 channel, u8 *cckPowe
pHalData->BW20_24G_Diff[TxCount][index];
/* 2. BW40 */
BW40PowerLevel[TxCount] = pHalData->Index24G_BW40_Base[TxCount][index];
} else if (TxCount==RF_PATH_D) {
} else if (TxCount == RF_PATH_D) {
/* 1. CCK */
cckPowerLevel[TxCount] = pHalData->Index24G_CCK_Base[TxCount][index];
/* 2. OFDM */
@ -1090,7 +990,7 @@ static void getTxPowerIndex88E(struct adapter * Adapter, u8 channel, u8 *cckPowe
}
}
static void phy_PowerIndexCheck88E(struct adapter * Adapter, u8 channel, u8 *cckPowerLevel,
static void phy_PowerIndexCheck88E(struct adapter *Adapter, u8 channel, u8 *cckPowerLevel,
u8 *ofdmPowerLevel, u8 *BW20PowerLevel, u8 *BW40PowerLevel)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
@ -1107,7 +1007,7 @@ static void phy_PowerIndexCheck88E(struct adapter * Adapter, u8 channel, u8 *cck
* Overview: This function is export to "HalCommon" moudule
* We must consider RF path later!!!!!!!
*
* Input: struct adapter * Adapter
* Input: struct adapter *Adapter
* u1Byte channel
*
* Output: NONE
@ -1120,7 +1020,7 @@ static void phy_PowerIndexCheck88E(struct adapter * Adapter, u8 channel, u8 *cck
*---------------------------------------------------------------------------*/
void
PHY_SetTxPowerLevel8188E(
struct adapter * Adapter,
struct adapter *Adapter,
u8 channel
)
{
@ -1128,14 +1028,14 @@ PHY_SetTxPowerLevel8188E(
u8 cckPowerLevel[MAX_TX_COUNT], ofdmPowerLevel[MAX_TX_COUNT];/* [0]:RF-A, [1]:RF-B */
u8 BW20PowerLevel[MAX_TX_COUNT], BW40PowerLevel[MAX_TX_COUNT];
u8 i=0;
u8 i = 0;
getTxPowerIndex88E(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0],&BW20PowerLevel[0],&BW40PowerLevel[0]);
getTxPowerIndex88E(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0], &BW20PowerLevel[0], &BW40PowerLevel[0]);
phy_PowerIndexCheck88E(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0],&BW20PowerLevel[0],&BW40PowerLevel[0]);
phy_PowerIndexCheck88E(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0], &BW20PowerLevel[0], &BW40PowerLevel[0]);
rtl8188e_PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);
rtl8188e_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0],&BW20PowerLevel[0],&BW40PowerLevel[0], channel);
rtl8188e_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], &BW20PowerLevel[0], &BW40PowerLevel[0], channel);
}
/* */
@ -1148,7 +1048,7 @@ PHY_SetTxPowerLevel8188E(
/* */
bool
PHY_UpdateTxPowerDbm8188E(
struct adapter * Adapter,
struct adapter *Adapter,
int powerInDbm
)
{
@ -1165,10 +1065,8 @@ PHY_UpdateTxPowerDbm8188E(
else
OfdmTxPwrIdx = 0;
for (idx = 0; idx < 14; idx++)
{
for (rf_path = 0; rf_path < 2; rf_path++)
{
for (idx = 0; idx < 14; idx++) {
for (rf_path = 0; rf_path < 2; rf_path++) {
pHalData->TxPwrLevelCck[rf_path][idx] = CckTxPwrIdx;
pHalData->TxPwrLevelHT40_1S[rf_path][idx] =
pHalData->TxPwrLevelHT40_2S[rf_path][idx] = OfdmTxPwrIdx;
@ -1179,7 +1077,7 @@ PHY_UpdateTxPowerDbm8188E(
void
PHY_ScanOperationBackup8188E(
struct adapter * Adapter,
struct adapter *Adapter,
u8 Operation
)
{
@ -1202,7 +1100,7 @@ PHY_ScanOperationBackup8188E(
*---------------------------------------------------------------------------*/
static void
_PHY_SetBWMode92C(
struct adapter * Adapter
struct adapter *Adapter
)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
@ -1213,7 +1111,7 @@ _PHY_SetBWMode92C(
return;
/* There is no 40MHz mode in RF_8225. */
if (pHalData->rf_chip==RF_8225)
if (pHalData->rf_chip == RF_8225)
return;
if (Adapter->bDriverStopped)
@ -1226,23 +1124,19 @@ _PHY_SetBWMode92C(
regBwOpMode = rtw_read8(Adapter, REG_BWOPMODE);
regRRSR_RSC = rtw_read8(Adapter, REG_RRSR+2);
switch (pHalData->CurrentChannelBW)
{
switch (pHalData->CurrentChannelBW) {
case HT_CHANNEL_WIDTH_20:
regBwOpMode |= BW_OPMODE_20MHZ;
/* 2007/02/07 Mark by Emily becasue we have not verify whether this register works */
rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
break;
case HT_CHANNEL_WIDTH_40:
regBwOpMode &= ~BW_OPMODE_20MHZ;
/* 2007/02/07 Mark by Emily becasue we have not verify whether this register works */
rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
regRRSR_RSC = (regRRSR_RSC&0x90) |(pHalData->nCur40MhzPrimeSC<<5);
regRRSR_RSC = (regRRSR_RSC&0x90) | (pHalData->nCur40MhzPrimeSC<<5);
rtw_write8(Adapter, REG_RRSR+2, regRRSR_RSC);
break;
default:
break;
}
@ -1250,38 +1144,29 @@ _PHY_SetBWMode92C(
/* 3 */
/* 3 <2>Set PHY related register */
/* 3 */
switch (pHalData->CurrentChannelBW)
{
switch (pHalData->CurrentChannelBW) {
/* 20 MHz channel*/
case HT_CHANNEL_WIDTH_20:
PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);
PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
/* PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1); */
break;
/* 40 MHz channel*/
case HT_CHANNEL_WIDTH_40:
PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);
PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
/* Set Control channel to upper or lower. These settings are required only for 40MHz */
PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1));
PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC==HAL_PRIME_CHNL_OFFSET_LOWER)?2:1);
PHY_SetBBReg(Adapter, 0x818, (BIT26 | BIT27),
(pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
break;
default:
break;
}
/* Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 */
/* 3<3>Set RF related register */
switch (pHalData->rf_chip)
{
switch (pHalData->rf_chip) {
case RF_8225:
break;
case RF_8256:
@ -1305,7 +1190,7 @@ _PHY_SetBWMode92C(
*
* Overview: This function is export to "HalCommon" moudule
*
* Input: struct adapter * Adapter
* Input: struct adapter *Adapter
* enum ht_channel_width Bandwidth 20M or 40M
*
* Output: NONE
@ -1314,15 +1199,11 @@ _PHY_SetBWMode92C(
*
* Note: We do not take j mode into consideration now
*---------------------------------------------------------------------------*/
void
PHY_SetBWMode8188E(
struct adapter * Adapter,
enum ht_channel_width Bandwidth, /* 20M or 40M */
unsigned char Offset /* Upper, Lower, or Don't care */
)
void PHY_SetBWMode8188E(struct adapter *Adapter, enum ht_channel_width Bandwidth, /* 20M or 40M */
unsigned char Offset) /* Upper, Lower, or Don't care */
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
enum ht_channel_width tmpBW= pHalData->CurrentChannelBW;
enum ht_channel_width tmpBW = pHalData->CurrentChannelBW;
pHalData->CurrentChannelBW = Bandwidth;
@ -1334,16 +1215,14 @@ PHY_SetBWMode8188E(
pHalData->CurrentChannelBW = tmpBW;
}
static void _PHY_SwChnl8192C(struct adapter * Adapter, u8 channel)
static void _PHY_SwChnl8192C(struct adapter *Adapter, u8 channel)
{
u8 eRFPath;
u32 param1, param2;
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
if ( Adapter->bNotifyChannelChange )
{
DBG_88E( "[%s] ch = %d\n", __func__, channel );
}
if (Adapter->bNotifyChannelChange)
DBG_88E("[%s] ch = %d\n", __func__, channel);
/* s1. pre common command - CmdID_SetTxPowerLevel */
PHY_SetTxPowerLevel8188E(Adapter, channel);
@ -1351,18 +1230,15 @@ static void _PHY_SwChnl8192C(struct adapter * Adapter, u8 channel)
/* s2. RF dependent command - CmdID_RF_WriteReg, param1=RF_CHNLBW, param2=channel */
param1 = RF_CHNLBW;
param2 = channel;
for (eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) {
for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2);
PHY_SetRFReg(Adapter, (enum rf_radio_path)eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
}
}
void
PHY_SwChnl8188E( /* Call after initialization */
struct adapter * Adapter,
u8 channel
)
void PHY_SwChnl8188E(struct adapter *Adapter, u8 channel)
{
/* Call after initialization */
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
u8 tmpchannel = pHalData->CurrentChannel;
bool bResult = true;
@ -1388,27 +1264,24 @@ PHY_SwChnl8188E( /* Call after initialization */
if (channel == 0)
channel = 1;
pHalData->CurrentChannel=channel;
pHalData->CurrentChannel = channel;
if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) {
_PHY_SwChnl8192C(Adapter, channel);
if (bResult) {
if (bResult)
;
} else {
pHalData->CurrentChannel = tmpchannel;
}
}
else
{
pHalData->CurrentChannel = tmpchannel;
} else {
pHalData->CurrentChannel = tmpchannel;
}
}
static bool
phy_SwChnlStepByStep(
struct adapter * Adapter,
struct adapter *Adapter,
u8 channel,
u8 *stage,
u8 *step,
@ -1446,12 +1319,9 @@ phy_SetSwChnlCmdArray(
return true;
}
static void
phy_FinishSwChnlNow( /* We should not call this function directly */
struct adapter * Adapter,
u8 channel
)
static void phy_FinishSwChnlNow(struct adapter *Adapter, u8 channel)
{
/* We should not call this function directly */
}
/* */
@ -1462,12 +1332,8 @@ phy_FinishSwChnlNow( /* We should not call this function directly */
/* The following procedure is operted according to SwChanlCallback8190Pci(). */
/* However, this procedure is performed synchronously which should be running under */
/* passive level. */
/* */
void
PHY_SwChnlPhy8192C( /* Only called during initialize */
struct adapter * Adapter,
u8 channel
)
/* Only called during initialize */
void PHY_SwChnlPhy8192C(struct adapter *Adapter, u8 channel)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
@ -1475,12 +1341,12 @@ PHY_SwChnlPhy8192C( /* Only called during initialize */
if (pHalData->rf_chip == RF_PSEUDO_11N)
return;
if ( channel == 0)
if (channel == 0)
channel = 1;
pHalData->CurrentChannel=channel;
pHalData->CurrentChannel = channel;
phy_FinishSwChnlNow(Adapter,channel);
phy_FinishSwChnlNow(Adapter, channel);
}
/* */
@ -1491,7 +1357,7 @@ PHY_SwChnlPhy8192C( /* Only called during initialize */
/* */
void
PHY_SetMonitorMode8192C(
struct adapter * pAdapter,
struct adapter *pAdapter,
bool bEnableMonitorMode
)
{
@ -1515,12 +1381,12 @@ PHY_SetMonitorMode8192C(
* 11/15/2007 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
bool PHY_CheckIsLegalRfPath8192C(struct adapter * pAdapter, u32 eRFPath)
bool PHY_CheckIsLegalRfPath8192C(struct adapter *pAdapter, u32 eRFPath)
{
return true;
} /* PHY_CheckIsLegalRfPath8192C */
static void _PHY_SetRFPathSwitch(struct adapter * pAdapter, bool bMain, bool is2T)
static void _PHY_SetRFPathSwitch(struct adapter *pAdapter, bool bMain, bool is2T)
{
u8 u1bTmp;
@ -1542,7 +1408,7 @@ static void _PHY_SetRFPathSwitch(struct adapter * pAdapter, bool bMain, bool is2
}
}
static bool _PHY_QueryRFPathSwitch(struct adapter * pAdapter, bool is2T)
static bool _PHY_QueryRFPathSwitch(struct adapter *pAdapter, bool is2T)
{
if (!pAdapter->hw_init_completed) {
PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01);
@ -1562,6 +1428,6 @@ static bool _PHY_QueryRFPathSwitch(struct adapter * pAdapter, bool is2T)
}
}
static void _PHY_DumpRFReg(struct adapter * pAdapter)
static void _PHY_DumpRFReg(struct adapter *pAdapter)
{
}

310
hal/rtl8188e_rf6052.c
View file

@ -91,8 +91,7 @@ static struct rf_shadow RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
* Firmwaer support the utility later.
*
*---------------------------------------------------------------------------*/
void rtl8188e_RF_ChangeTxPath( struct adapter * Adapter,
u16 DataRate)
void rtl8188e_RF_ChangeTxPath(struct adapter *Adapter, u16 DataRate)
{
/* We do not support gain table change inACUT now !!!! Delete later !!! */
} /* RF_ChangeTxPath */
@ -103,7 +102,7 @@ void rtl8188e_RF_ChangeTxPath( struct adapter * Adapter,
*
* Overview: This function is called by SetBWModeCallback8190Pci() only
*
* Input: struct adapter * Adapter
* Input: struct adapter *Adapter
* WIRELESS_BANDWIDTH_E Bandwidth 20M or 40M
*
* Output: NONE
@ -112,33 +111,25 @@ void rtl8188e_RF_ChangeTxPath( struct adapter * Adapter,
*
* Note: For RF type 0222D
*---------------------------------------------------------------------------*/
void
rtl8188e_PHY_RF6052SetBandwidth(
struct adapter * Adapter,
enum ht_channel_width Bandwidth) /* 20M or 40M */
void rtl8188e_PHY_RF6052SetBandwidth(struct adapter *Adapter,
enum ht_channel_width Bandwidth)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
switch (Bandwidth)
{
switch (Bandwidth) {
case HT_CHANNEL_WIDTH_20:
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10) | BIT(11));
PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
break;
case HT_CHANNEL_WIDTH_40:
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff)| BIT(10));
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10));
PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
break;
default:
/* RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth )); */
break;
}
}
/*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetCckTxPower
*
@ -158,34 +149,30 @@ rtl8188e_PHY_RF6052SetBandwidth(
void
rtl8188e_PHY_RF6052SetCckTxPower(
struct adapter * Adapter,
u8* pPowerlevel)
struct adapter *Adapter,
u8 *pPowerlevel)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
struct dm_priv *pdmpriv = &pHalData->dmpriv;
struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
/* PMGNT_INFO pMgntInfo=&Adapter->MgntInfo; */
u32 TxAGC[2]={0, 0}, tmpval=0,pwrtrac_value;
u32 TxAGC[2] = {0, 0}, tmpval = 0, pwrtrac_value;
bool TurboScanOff = false;
u8 idx1, idx2;
u8* ptr;
u8 *ptr;
u8 direction;
/* FOR CE ,must disable turbo scan */
TurboScanOff = true;
if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS)
{
if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) {
TxAGC[RF_PATH_A] = 0x3f3f3f3f;
TxAGC[RF_PATH_B] = 0x3f3f3f3f;
TurboScanOff = true;/* disable turbo scan */
if (TurboScanOff)
{
for (idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
{
if (TurboScanOff) {
for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
TxAGC[idx1] =
pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
@ -194,33 +181,27 @@ rtl8188e_PHY_RF6052SetCckTxPower(
TxAGC[idx1] = 0x20;
}
}
}
else
{
/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
{
} else {
/* Driver dynamic Tx power shall not affect Tx power.
* It shall be determined by power training mechanism.
i * Currently, we cannot fully disable driver dynamic
* tx power mechanism because it is referenced by BT
* coexist mechanism.
* In the future, two mechanism shall be separated from
* each other and maintained independantly. */
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) {
TxAGC[RF_PATH_A] = 0x10101010;
TxAGC[RF_PATH_B] = 0x10101010;
}
else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
{
} else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) {
TxAGC[RF_PATH_A] = 0x00000000;
TxAGC[RF_PATH_B] = 0x00000000;
}
else
{
for (idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
{
} else {
for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
TxAGC[idx1] =
pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
}
if (pHalData->EEPROMRegulatory==0)
{
if (pHalData->EEPROMRegulatory == 0) {
tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) +
(pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8);
TxAGC[RF_PATH_A] += tmpval;
@ -231,12 +212,9 @@ rtl8188e_PHY_RF6052SetCckTxPower(
}
}
}
for (idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
{
ptr = (u8*)(&(TxAGC[idx1]));
for (idx2=0; idx2<4; idx2++)
{
for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
ptr = (u8 *)(&(TxAGC[idx1]));
for (idx2 = 0; idx2 < 4; idx2++) {
if (*ptr > RF6052_MAX_TX_PWR)
*ptr = RF6052_MAX_TX_PWR;
ptr++;
@ -244,18 +222,16 @@ rtl8188e_PHY_RF6052SetCckTxPower(
}
ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 1, &direction, &pwrtrac_value);
if (direction == 1) /* Increase TX pwoer */
{
if (direction == 1) {
/* Increase TX pwoer */
TxAGC[0] += pwrtrac_value;
TxAGC[1] += pwrtrac_value;
}
else if (direction == 2) /* Decrease TX pwoer */
{
} else if (direction == 2) {
/* Decrease TX pwoer */
TxAGC[0] -= pwrtrac_value;
TxAGC[1] -= pwrtrac_value;
}
/* rf-A cck tx power */
tmpval = TxAGC[RF_PATH_A]&0xff;
PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
@ -273,104 +249,77 @@ rtl8188e_PHY_RF6052SetCckTxPower(
/* powerbase0 for OFDM rates */
/* powerbase1 for HT MCS rates */
/* */
static void getPowerBase88E(
struct adapter * Adapter,
u8* pPowerLevelOFDM,
u8* pPowerLevelBW20,
u8* pPowerLevelBW40,
u8 Channel,
u32* OfdmBase,
u32* MCSBase
)
static void getpowerbase88e(struct adapter *Adapter, u8 *pPowerLevelOFDM,
u8 *pPowerLevelBW20, u8 *pPowerLevelBW40, u8 Channel, u32 *OfdmBase, u32 *MCSBase)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
u32 powerBase0, powerBase1;
u8 Legacy_pwrdiff=0;
s8 HT20_pwrdiff=0;
u8 Legacy_pwrdiff = 0;
s8 HT20_pwrdiff = 0;
u8 i, powerlevel[2];
for (i=0; i<2; i++)
{
for (i = 0; i < 2; i++) {
powerBase0 = pPowerLevelOFDM[i];
powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
powerBase0 = (powerBase0<<24) | (powerBase0<<16) | (powerBase0<<8) | powerBase0;
*(OfdmBase+i) = powerBase0;
}
for (i=0; i<pHalData->NumTotalRFPath; i++)
{
for (i = 0; i < pHalData->NumTotalRFPath; i++) {
/* Check HT20 to HT40 diff */
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
{
powerlevel[i] = pPowerLevelBW20[i];
}
else
{
powerlevel[i] = pPowerLevelBW40[i];
}
powerBase1 = powerlevel[i];
powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
powerBase1 = (powerBase1<<24) | (powerBase1<<16) | (powerBase1<<8) | powerBase1;
*(MCSBase+i) = powerBase1;
}
}
static void getTxPowerWriteValByRegulatory88E(
struct adapter * Adapter,
u8 Channel,
u8 index,
u32* powerBase0,
u32* powerBase1,
u32* pOutWriteVal
)
static void get_rx_power_val_by_reg(struct adapter *Adapter, u8 Channel,
u8 index, u32 *powerBase0, u32 *powerBase1,
u32 *pOutWriteVal)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
u1Byte i, chnlGroup=0, pwr_diff_limit[4], customer_pwr_limit;
s1Byte pwr_diff=0;
u1Byte i, chnlGroup = 0, pwr_diff_limit[4], customer_pwr_limit;
s1Byte pwr_diff = 0;
u4Byte writeVal, customer_limit, rf;
u1Byte Regulatory = pHalData->EEPROMRegulatory;
/* */
/* Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */
/* */
for (rf=0; rf<2; rf++) {
switch (Regulatory)
{
for (rf = 0; rf < 2; rf++) {
switch (Regulatory) {
case 0: /* Realtek better performance */
/* increase power diff defined by Realtek for large power */
chnlGroup = 0;
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] +
((index < 2) ? powerBase0[rf] : powerBase1[rf]);
break;
case 1: /* Realtek regulatory */
/* increase power diff defined by Realtek for regulatory */
{
if (pHalData->pwrGroupCnt == 1)
chnlGroup = 0;
if (pHalData->pwrGroupCnt >= pHalData->PGMaxGroup)
{
if (pHalData->pwrGroupCnt >= pHalData->PGMaxGroup) {
if (Channel < 3) /* Chanel 1-2 */
chnlGroup = 0;
else if (Channel < 6) /* Channel 3-5 */
chnlGroup = 1;
else if (Channel <9) /* Channel 6-8 */
else if (Channel < 9) /* Channel 6-8 */
chnlGroup = 2;
else if (Channel <12) /* Channel 9-11 */
else if (Channel < 12) /* Channel 9-11 */
chnlGroup = 3;
else if (Channel <14) /* Channel 12-13 */
else if (Channel < 14) /* Channel 12-13 */
chnlGroup = 4;
else if (Channel ==14) /* Channel 14 */
else if (Channel == 14) /* Channel 14 */
chnlGroup = 5;
}
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
}
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] +
((index < 2) ? powerBase0[rf] : powerBase1[rf]);
break;
case 2: /* Better regulatory */
/* don't increase any power diff */
writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]);
writeVal = ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
break;
case 3: /* Customer defined power diff. */
/* increase power diff defined by customer. */
@ -391,24 +340,22 @@ static void getTxPowerWriteValByRegulatory88E(
else
pwr_diff = customer_pwr_limit - pwr_diff;
for (i=0; i<4; i++)
{
pwr_diff_limit[i] = (u1Byte)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]&(0x7f<<(i*8)))>>(i*8));
for (i = 0; i < 4; i++) {
pwr_diff_limit[i] = (u1Byte)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)]&(0x7f<<(i*8)))>>(i*8));
if (pwr_diff_limit[i] > pwr_diff)
pwr_diff_limit[i] = pwr_diff;
}
customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
(pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]);
writeVal = customer_limit + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
break;
default:
chnlGroup = 0;
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] +
((index < 2) ? powerBase0[rf] : powerBase1[rf]);
break;
}
/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */
@ -421,76 +368,64 @@ static void getTxPowerWriteValByRegulatory88E(
/* 20100628 Joseph: High power mode for BT-Coexist mechanism. */
/* This mechanism is only applied when Driver-Highpower-Mechanism is OFF. */
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
{
writeVal = writeVal - 0x06060606;
}
else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
{
writeVal = writeVal ;
}
writeVal = writeVal;
*(pOutWriteVal+rf) = writeVal;
}
}
static void writeOFDMPowerReg88E(
struct adapter * Adapter,
u8 index,
u32* pValue
)
static void writeOFDMPowerReg88E(struct adapter *Adapter, u8 index, u32 *pValue)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
u16 RegOffset_A[6] = { rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24,
u16 regoffset_a[6] = {
rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24,
rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04,
rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12};
u16 RegOffset_B[6] = { rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24,
u16 regoffset_b[6] = {
rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24,
rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04,
rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12};
u8 i, rf, pwr_val[4];
u32 writeVal;
u16 RegOffset;
u16 regoffset;
for (rf=0; rf<2; rf++)
{
for (rf = 0; rf < 2; rf++) {
writeVal = pValue[rf];
for (i=0; i<4; i++)
{
for (i = 0; i < 4; i++) {
pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));
if (pwr_val[i] > RF6052_MAX_TX_PWR)
pwr_val[i] = RF6052_MAX_TX_PWR;
}
writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) |(pwr_val[1]<<8) |pwr_val[0];
writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) | (pwr_val[1]<<8) | pwr_val[0];
if (rf == 0)
RegOffset = RegOffset_A[index];
regoffset = regoffset_a[index];
else
RegOffset = RegOffset_B[index];
regoffset = regoffset_b[index];
PHY_SetBBReg(Adapter, RegOffset, bMaskDWord, writeVal);
PHY_SetBBReg(Adapter, regoffset, bMaskDWord, writeVal);
/* 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */
if (((pHalData->rf_type == RF_2T2R) &&
(RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs15_Mcs12))||
(regoffset == rTxAGC_A_Mcs15_Mcs12 || regoffset == rTxAGC_B_Mcs15_Mcs12)) ||
((pHalData->rf_type != RF_2T2R) &&
(RegOffset == rTxAGC_A_Mcs07_Mcs04 || RegOffset == rTxAGC_B_Mcs07_Mcs04)) )
{
(regoffset == rTxAGC_A_Mcs07_Mcs04 || regoffset == rTxAGC_B_Mcs07_Mcs04))) {
writeVal = pwr_val[3];
if (RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_A_Mcs07_Mcs04)
RegOffset = 0xc90;
if (RegOffset == rTxAGC_B_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs07_Mcs04)
RegOffset = 0xc98;
for (i=0; i<3; i++)
{
if (i!=2)
writeVal = (writeVal>8)?(writeVal-8):0;
if (regoffset == rTxAGC_A_Mcs15_Mcs12 || regoffset == rTxAGC_A_Mcs07_Mcs04)
regoffset = 0xc90;
if (regoffset == rTxAGC_B_Mcs15_Mcs12 || regoffset == rTxAGC_B_Mcs07_Mcs04)
regoffset = 0xc98;
for (i = 0; i < 3; i++) {
if (i != 2)
writeVal = (writeVal > 8) ? (writeVal-8) : 0;
else
writeVal = (writeVal>6)?(writeVal-6):0;
rtw_write8(Adapter, (u32)(RegOffset+i), (u8)writeVal);
writeVal = (writeVal > 6) ? (writeVal-6) : 0;
rtw_write8(Adapter, (u32)(regoffset+i), (u8)writeVal);
}
}
}
}
/*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetOFDMTxPower
*
@ -516,10 +451,10 @@ static void writeOFDMPowerReg88E(
void
rtl8188e_PHY_RF6052SetOFDMTxPower(
struct adapter * Adapter,
u8* pPowerLevelOFDM,
u8* pPowerLevelBW20,
u8* pPowerLevelBW40,
struct adapter *Adapter,
u8 *pPowerLevelOFDM,
u8 *pPowerLevelBW20,
u8 *pPowerLevelBW40,
u8 Channel)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
@ -527,45 +462,29 @@ rtl8188e_PHY_RF6052SetOFDMTxPower(
u8 direction;
u8 index = 0;
getPowerBase88E(Adapter, pPowerLevelOFDM,pPowerLevelBW20,pPowerLevelBW40, Channel, &powerBase0[0], &powerBase1[0]);
getpowerbase88e(Adapter, pPowerLevelOFDM, pPowerLevelBW20, pPowerLevelBW40, Channel, &powerBase0[0], &powerBase1[0]);
/* */
/* 2012/04/23 MH According to power tracking value, we need to revise OFDM tx power. */
/* This is ued to fix unstable power tracking mode. */
/* */
ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 0, &direction, &pwrtrac_value);
for (index=0; index<6; index++)
{
getTxPowerWriteValByRegulatory88E(Adapter, Channel, index,
&powerBase0[0], &powerBase1[0], &writeVal[0]);
for (index = 0; index < 6; index++) {
get_rx_power_val_by_reg(Adapter, Channel, index,
&powerBase0[0], &powerBase1[0],
&writeVal[0]);
if (direction == 1)
{
if (direction == 1) {
writeVal[0] += pwrtrac_value;
writeVal[1] += pwrtrac_value;
}
else if (direction == 2)
{
} else if (direction == 2) {
writeVal[0] -= pwrtrac_value;
writeVal[1] -= pwrtrac_value;
}
writeOFDMPowerReg88E(Adapter, index, &writeVal[0]);
}
}
static void
phy_RF6052_Config_HardCode(
struct adapter * Adapter
)
{
}
static int
phy_RF6052_Config_ParaFile(
struct adapter * Adapter
)
static int phy_RF6052_Config_ParaFile(struct adapter *Adapter)
{
u32 u4RegValue;
u8 eRFPath;
@ -578,9 +497,7 @@ phy_RF6052_Config_ParaFile(
/* 3----------------------------------------------------------------- */
/* 3 <2> Initialize RF */
/* 3----------------------------------------------------------------- */
for (eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
{
for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
pPhyReg = &pHalData->PHYRegDef[eRFPath];
/*----Store original RFENV control type----*/
@ -589,12 +506,11 @@ phy_RF6052_Config_ParaFile(
case RF_PATH_C:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
break;
case RF_PATH_B :
case RF_PATH_B:
case RF_PATH_D:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
break;
}
/*----Set RF_ENV enable----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
rtw_udelay_os(1);/* PlatformStallExecution(1); */
@ -613,47 +529,39 @@ phy_RF6052_Config_ParaFile(
/*----Initialize RF fom connfiguration file----*/
switch (eRFPath) {
case RF_PATH_A:
if (HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(enum ODM_RF_RADIO_PATH)eRFPath, (enum ODM_RF_RADIO_PATH)eRFPath))
rtStatus= _FAIL;
if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, (enum ODM_RF_RADIO_PATH)eRFPath, (enum ODM_RF_RADIO_PATH)eRFPath))
rtStatus = _FAIL;
break;
case RF_PATH_B:
if (HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(enum ODM_RF_RADIO_PATH)eRFPath, (enum ODM_RF_RADIO_PATH)eRFPath))
rtStatus= _FAIL;
if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, (enum ODM_RF_RADIO_PATH)eRFPath, (enum ODM_RF_RADIO_PATH)eRFPath))
rtStatus = _FAIL;
break;
case RF_PATH_C:
break;
case RF_PATH_D:
break;
}
/*----Restore RFENV control type----*/;
switch (eRFPath)
{
switch (eRFPath) {
case RF_PATH_A:
case RF_PATH_C:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
break;
case RF_PATH_B :
case RF_PATH_B:
case RF_PATH_D:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
break;
}
if (rtStatus != _SUCCESS)
goto phy_RF6052_Config_ParaFile_Fail;
}
return rtStatus;
phy_RF6052_Config_ParaFile_Fail:
return rtStatus;
}
int
PHY_RF6052_Config8188E(
struct adapter * Adapter)
int PHY_RF6052_Config8188E(struct adapter *Adapter)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
int rtStatus = _SUCCESS;
@ -673,5 +581,3 @@ PHY_RF6052_Config8188E(
rtStatus = phy_RF6052_Config_ParaFile(Adapter);
return rtStatus;
}
/* End of HalRf6052.c */