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rtl8188eu: Remove most of the remaining parameters from autoconf.h

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2013-07-26 22:47:25 -05:00
parent 1e96c9a1d4
commit f55990fd29
13 changed files with 31 additions and 192 deletions
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3
hal/HalHWImg8188E_BB.c
View file

@ -22,7 +22,6 @@
#include <rtw_iol.h> #include <rtw_iol.h>
#if (RTL8188E_SUPPORT == 1)
static bool static bool
CheckCondition( CheckCondition(
const u4Byte Condition, const u4Byte Condition,
@ -792,5 +791,3 @@ ODM_ReadAndConfig_PHY_REG_PG_8188E(
} }
} }
#endif /* end of HWIMG_SUPPORT */

10
hal/HalHWImg8188E_MAC.c
View file

@ -20,12 +20,8 @@
#include "odm_precomp.h" #include "odm_precomp.h"
#include <rtw_iol.h> #include <rtw_iol.h>
#if (RTL8188E_SUPPORT == 1)
static bool static bool CheckCondition(const u4Byte Condition, const u4Byte Hex)
CheckCondition(
const u4Byte Condition,
const u4Byte Hex
)
{ {
u4Byte _board = (Hex & 0x000000FF); u4Byte _board = (Hex & 0x000000FF);
u4Byte _interface = (Hex & 0x0000FF00) >> 8; u4Byte _interface = (Hex & 0x0000FF00) >> 8;
@ -256,5 +252,3 @@ ODM_ReadAndConfig_MAC_REG_8188E(
} }
return rst; return rst;
} }
#endif /* end of HWIMG_SUPPORT */

9
hal/HalHWImg8188E_RF.c
View file

@ -22,12 +22,7 @@
#include <rtw_iol.h> #include <rtw_iol.h>
#if (RTL8188E_SUPPORT == 1) static bool CheckCondition(const u4Byte Condition, const u4Byte Hex)
static bool
CheckCondition(
const u4Byte Condition,
const u4Byte Hex
)
{ {
u4Byte _board = (Hex & 0x000000FF); u4Byte _board = (Hex & 0x000000FF);
u4Byte _interface = (Hex & 0x0000FF00) >> 8; u4Byte _interface = (Hex & 0x0000FF00) >> 8;
@ -303,5 +298,3 @@ enum HAL_STATUS ODM_ReadAndConfig_RadioA_1T_8188E(struct odm_dm_struct * pDM_Odm
} }
return rst; return rst;
} }
#endif /* end of HWIMG_SUPPORT */

32
hal/odm_HWConfig.c
View file

@ -24,18 +24,7 @@
#include "odm_precomp.h" #include "odm_precomp.h"
#if (RTL8188E_FOR_TEST_CHIP > 1) #define READ_AND_CONFIG READ_AND_CONFIG_MP
#define READ_AND_CONFIG(ic, txt) do {\
if (pDM_Odm->bIsMPChip)\
READ_AND_CONFIG_MP(ic,txt);\
else\
READ_AND_CONFIG_TC(ic,txt);\
} while (0)
#elif (RTL8188E_FOR_TEST_CHIP == 1)
#define READ_AND_CONFIG READ_AND_CONFIG_TC
#else
#define READ_AND_CONFIG READ_AND_CONFIG_MP
#endif
#define READ_AND_CONFIG_MP(ic, txt) (ODM_ReadAndConfig##txt##ic(pDM_Odm)) #define READ_AND_CONFIG_MP(ic, txt) (ODM_ReadAndConfig##txt##ic(pDM_Odm))
#define READ_AND_CONFIG_TC(ic, txt) (ODM_ReadAndConfig_TC##txt##ic(pDM_Odm)) #define READ_AND_CONFIG_TC(ic, txt) (ODM_ReadAndConfig_TC##txt##ic(pDM_Odm))
@ -851,28 +840,19 @@ ODM_ConfigRFWithHeaderFile(
enum ODM_RF_RADIO_PATH eRFPath enum ODM_RF_RADIO_PATH eRFPath
) )
{ {
/* RT_STATUS rtStatus = RT_STATUS_SUCCESS; */ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===>ODM_ConfigRFWithHeaderFile\n"));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===>ODM_ConfigRFWithHeaderFile\n"));
#if (RTL8188E_SUPPORT == 1)
if (pDM_Odm->SupportICType == ODM_RTL8188E) if (pDM_Odm->SupportICType == ODM_RTL8188E)
{ {
if (eRFPath == ODM_RF_PATH_A) if (eRFPath == ODM_RF_PATH_A)
READ_AND_CONFIG(8188E,_RadioA_1T_); READ_AND_CONFIG(8188E,_RadioA_1T_);
/* else if (eRFPath == ODM_RF_PATH_B) */
/* READ_AND_CONFIG(8188E,_RadioB_1T_); */
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> ODM_ConfigRFWithHeaderFile() Radio_A:Rtl8188ERadioA_1TArray\n")); ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> ODM_ConfigRFWithHeaderFile() Radio_A:Rtl8188ERadioA_1TArray\n"));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> ODM_ConfigRFWithHeaderFile() Radio_B:Rtl8188ERadioB_1TArray\n")); ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> ODM_ConfigRFWithHeaderFile() Radio_B:Rtl8188ERadioB_1TArray\n"));
} }
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("ODM_ConfigRFWithHeaderFile: Radio No %x\n", eRFPath)); ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("ODM_ConfigRFWithHeaderFile: Radio No %x\n", eRFPath));
/* rtStatus = RT_STATUS_SUCCESS; */
#endif
return HAL_STATUS_SUCCESS; return HAL_STATUS_SUCCESS;
} }
enum HAL_STATUS enum HAL_STATUS
ODM_ConfigBBWithHeaderFile( ODM_ConfigBBWithHeaderFile(
struct odm_dm_struct * pDM_Odm, struct odm_dm_struct * pDM_Odm,
@ -880,7 +860,6 @@ ODM_ConfigBBWithHeaderFile(
) )
{ {
#if (RTL8188E_SUPPORT == 1)
if (pDM_Odm->SupportICType == ODM_RTL8188E) if (pDM_Odm->SupportICType == ODM_RTL8188E)
{ {
@ -898,8 +877,6 @@ ODM_ConfigBBWithHeaderFile(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8188EPHY_REG_PGArray\n")); ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8188EPHY_REG_PGArray\n"));
} }
} }
#endif
return HAL_STATUS_SUCCESS; return HAL_STATUS_SUCCESS;
} }
@ -909,12 +886,7 @@ ODM_ConfigMACWithHeaderFile(
) )
{ {
u1Byte result = HAL_STATUS_SUCCESS; u1Byte result = HAL_STATUS_SUCCESS;
#if (RTL8188E_SUPPORT == 1)
if (pDM_Odm->SupportICType == ODM_RTL8188E) if (pDM_Odm->SupportICType == ODM_RTL8188E)
{
result = READ_AND_CONFIG(8188E,_MAC_REG_); result = READ_AND_CONFIG(8188E,_MAC_REG_);
}
#endif
return result; return result;
} }

129
hal/odm_RTL8188E.c
View file

@ -24,30 +24,20 @@
#include "odm_precomp.h" #include "odm_precomp.h"
#if (RTL8188E_SUPPORT == 1) void ODM_DIG_LowerBound_88E(struct odm_dm_struct * pDM_Odm)
void
ODM_DIG_LowerBound_88E(
struct odm_dm_struct * pDM_Odm
)
{ {
struct rtw_dig * pDM_DigTable = &pDM_Odm->DM_DigTable; struct rtw_dig * pDM_DigTable = &pDM_Odm->DM_DigTable;
if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
{ {
pDM_DigTable->rx_gain_range_min = (u1Byte) pDM_DigTable->AntDiv_RSSI_max; pDM_DigTable->rx_gain_range_min = (u1Byte) pDM_DigTable->AntDiv_RSSI_max;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_DIG_LowerBound_88E(): pDM_DigTable->AntDiv_RSSI_max=%d\n",pDM_DigTable->AntDiv_RSSI_max)); ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
("ODM_DIG_LowerBound_88E(): pDM_DigTable->AntDiv_RSSI_max=%d\n",pDM_DigTable->AntDiv_RSSI_max));
} }
/* If only one Entry connected */ /* If only one Entry connected */
} }
static void static void odm_RX_HWAntDivInit(struct odm_dm_struct * pDM_Odm)
odm_RX_HWAntDivInit(
struct odm_dm_struct * pDM_Odm
)
{ {
u4Byte value32; u4Byte value32;
struct adapter *Adapter = pDM_Odm->Adapter; struct adapter *Adapter = pDM_Odm->Adapter;
@ -78,16 +68,12 @@ odm_RX_HWAntDivInit(
ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0201); /* antenna mapping table */ ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0201); /* antenna mapping table */
} }
static void static void odm_TRX_HWAntDivInit(struct odm_dm_struct * pDM_Odm)
odm_TRX_HWAntDivInit(
struct odm_dm_struct * pDM_Odm
)
{ {
u4Byte value32; u4Byte value32;
struct adapter * Adapter = pDM_Odm->Adapter; struct adapter * Adapter = pDM_Odm->Adapter;
if (*(pDM_Odm->mp_mode) == 1) if (*(pDM_Odm->mp_mode) == 1) {
{
pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV; pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); /* disable HW AntDiv */ ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); /* disable HW AntDiv */
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); /* Default RX (0/1) */ ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); /* Default RX (0/1) */
@ -122,10 +108,7 @@ odm_TRX_HWAntDivInit(
ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); /* Reg914=3'b010, Reg915=3'b001 */ ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); /* Reg914=3'b010, Reg915=3'b001 */
} }
static void static void odm_FastAntTrainingInit(struct odm_dm_struct *pDM_Odm)
odm_FastAntTrainingInit(
struct odm_dm_struct * pDM_Odm
)
{ {
u4Byte value32, i; u4Byte value32, i;
struct fast_ant_train *pDM_FatTable = &pDM_Odm->DM_FatTable; struct fast_ant_train *pDM_FatTable = &pDM_Odm->DM_FatTable;
@ -133,8 +116,7 @@ odm_FastAntTrainingInit(
struct adapter * Adapter = pDM_Odm->Adapter; struct adapter * Adapter = pDM_Odm->Adapter;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_FastAntTrainingInit()\n")); ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_FastAntTrainingInit()\n"));
if (*(pDM_Odm->mp_mode) == 1) if (*(pDM_Odm->mp_mode) == 1) {
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("pDM_Odm->AntDivType: %d\n", pDM_Odm->AntDivType)); ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("pDM_Odm->AntDivType: %d\n", pDM_Odm->AntDivType));
return; return;
} }
@ -177,9 +159,7 @@ odm_FastAntTrainingInit(
ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 1); ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 1);
ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2); ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2);
} }
} } else if (AntCombination == 7) {
else if (AntCombination == 7)
{
if (!pDM_Odm->bIsMPChip) /* testchip */ if (!pDM_Odm->bIsMPChip) /* testchip */
{ {
ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); /* Reg858[10:8]=3'b000 */ ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); /* Reg858[10:8]=3'b000 */
@ -216,10 +196,7 @@ odm_FastAntTrainingInit(
ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); /* RegC50[7]=1'b1 enable HW AntDiv */ ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); /* RegC50[7]=1'b1 enable HW AntDiv */
} }
void void ODM_AntennaDiversityInit_88E(struct odm_dm_struct *pDM_Odm)
ODM_AntennaDiversityInit_88E(
struct odm_dm_struct * pDM_Odm
)
{ {
if (pDM_Odm->SupportICType != ODM_RTL8188E) if (pDM_Odm->SupportICType != ODM_RTL8188E)
return; return;
@ -235,9 +212,7 @@ ODM_AntennaDiversityInit_88E(
odm_FastAntTrainingInit(pDM_Odm); odm_FastAntTrainingInit(pDM_Odm);
} }
void ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *pDM_Odm, u1Byte Ant)
void
ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *pDM_Odm, u1Byte Ant)
{ {
struct fast_ant_train *pDM_FatTable = &pDM_Odm->DM_FatTable; struct fast_ant_train *pDM_FatTable = &pDM_Odm->DM_FatTable;
u4Byte DefaultAnt, OptionalAnt; u4Byte DefaultAnt, OptionalAnt;
@ -276,8 +251,7 @@ ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *pDM_Odm, u1Byte Ant)
} }
static void static void odm_UpdateTxAnt_88E(struct odm_dm_struct *pDM_Odm, u1Byte Ant, u4Byte MacId)
odm_UpdateTxAnt_88E(struct odm_dm_struct *pDM_Odm, u1Byte Ant, u4Byte MacId)
{ {
struct fast_ant_train *pDM_FatTable = &pDM_Odm->DM_FatTable; struct fast_ant_train *pDM_FatTable = &pDM_Odm->DM_FatTable;
u1Byte TargetAnt; u1Byte TargetAnt;
@ -297,69 +271,43 @@ odm_UpdateTxAnt_88E(struct odm_dm_struct *pDM_Odm, u1Byte Ant, u4Byte MacId)
pDM_FatTable->antsel_c[MacId] , pDM_FatTable->antsel_b[MacId] , pDM_FatTable->antsel_a[MacId] )); pDM_FatTable->antsel_c[MacId] , pDM_FatTable->antsel_b[MacId] , pDM_FatTable->antsel_a[MacId] ));
} }
void void ODM_SetTxAntByTxInfo_88E(struct odm_dm_struct *pDM_Odm, pu1Byte pDesc, u1Byte macId)
ODM_SetTxAntByTxInfo_88E(
struct odm_dm_struct * pDM_Odm,
pu1Byte pDesc,
u1Byte macId
)
{ {
struct fast_ant_train *pDM_FatTable = &pDM_Odm->DM_FatTable; struct fast_ant_train *pDM_FatTable = &pDM_Odm->DM_FatTable;
if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) {
{
SET_TX_DESC_ANTSEL_A_88E(pDesc, pDM_FatTable->antsel_a[macId]); SET_TX_DESC_ANTSEL_A_88E(pDesc, pDM_FatTable->antsel_a[macId]);
SET_TX_DESC_ANTSEL_B_88E(pDesc, pDM_FatTable->antsel_b[macId]); SET_TX_DESC_ANTSEL_B_88E(pDesc, pDM_FatTable->antsel_b[macId]);
SET_TX_DESC_ANTSEL_C_88E(pDesc, pDM_FatTable->antsel_c[macId]); SET_TX_DESC_ANTSEL_C_88E(pDesc, pDM_FatTable->antsel_c[macId]);
} }
} }
void void ODM_AntselStatistics_88E(struct odm_dm_struct *pDM_Odm, u1Byte antsel_tr_mux, u4Byte MacId, u1Byte RxPWDBAll)
ODM_AntselStatistics_88E(
struct odm_dm_struct * pDM_Odm,
u1Byte antsel_tr_mux,
u4Byte MacId,
u1Byte RxPWDBAll
)
{ {
struct fast_ant_train *pDM_FatTable = &pDM_Odm->DM_FatTable; struct fast_ant_train *pDM_FatTable = &pDM_Odm->DM_FatTable;
if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) {
{ if (antsel_tr_mux == MAIN_ANT_CG_TRX) {
if (antsel_tr_mux == MAIN_ANT_CG_TRX)
{
pDM_FatTable->MainAnt_Sum[MacId]+=RxPWDBAll; pDM_FatTable->MainAnt_Sum[MacId]+=RxPWDBAll;
pDM_FatTable->MainAnt_Cnt[MacId]++; pDM_FatTable->MainAnt_Cnt[MacId]++;
} } else {
else
{
pDM_FatTable->AuxAnt_Sum[MacId]+=RxPWDBAll; pDM_FatTable->AuxAnt_Sum[MacId]+=RxPWDBAll;
pDM_FatTable->AuxAnt_Cnt[MacId]++; pDM_FatTable->AuxAnt_Cnt[MacId]++;
} }
} } else if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) {
else if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) if (antsel_tr_mux == MAIN_ANT_CGCS_RX) {
{
if (antsel_tr_mux == MAIN_ANT_CGCS_RX)
{
pDM_FatTable->MainAnt_Sum[MacId]+=RxPWDBAll; pDM_FatTable->MainAnt_Sum[MacId]+=RxPWDBAll;
pDM_FatTable->MainAnt_Cnt[MacId]++; pDM_FatTable->MainAnt_Cnt[MacId]++;
} } else {
else
{
pDM_FatTable->AuxAnt_Sum[MacId]+=RxPWDBAll; pDM_FatTable->AuxAnt_Sum[MacId]+=RxPWDBAll;
pDM_FatTable->AuxAnt_Cnt[MacId]++; pDM_FatTable->AuxAnt_Cnt[MacId]++;
} }
} }
} }
#define TX_BY_REG 0 #define TX_BY_REG 0
static void static void odm_HWAntDiv(struct odm_dm_struct *pDM_Odm)
odm_HWAntDiv(
struct odm_dm_struct * pDM_Odm
)
{ {
u4Byte i, MinRSSI=0xFF, AntDivMaxRSSI=0, MaxRSSI=0, LocalMinRSSI, LocalMaxRSSI; u4Byte i, MinRSSI=0xFF, AntDivMaxRSSI=0, MaxRSSI=0, LocalMinRSSI, LocalMaxRSSI;
u4Byte Main_RSSI, Aux_RSSI; u4Byte Main_RSSI, Aux_RSSI;
@ -370,11 +318,9 @@ odm_HWAntDiv(
bool bPktFilterMacth = false; bool bPktFilterMacth = false;
struct sta_info * pEntry; struct sta_info * pEntry;
for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++) for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++) {
{
pEntry = pDM_Odm->pODM_StaInfo[i]; pEntry = pDM_Odm->pODM_StaInfo[i];
if (IS_STA_VALID(pEntry)) if (IS_STA_VALID(pEntry)) {
{
/* 2 Caculate RSSI per Antenna */ /* 2 Caculate RSSI per Antenna */
Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0; Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0;
Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0; Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0;
@ -397,8 +343,7 @@ odm_HWAntDiv(
Aux_RSSI = Main_RSSI; Aux_RSSI = Main_RSSI;
LocalMinRSSI = (Main_RSSI>Aux_RSSI)?Aux_RSSI:Main_RSSI; LocalMinRSSI = (Main_RSSI>Aux_RSSI)?Aux_RSSI:Main_RSSI;
if (LocalMinRSSI < MinRSSI) if (LocalMinRSSI < MinRSSI) {
{
MinRSSI = LocalMinRSSI; MinRSSI = LocalMinRSSI;
RxIdleAnt = TargetAnt; RxIdleAnt = TargetAnt;
} }
@ -792,27 +737,3 @@ odm_DynamicPrimaryCCA(
Client_40MHz_pre = Client_40MHz; Client_40MHz_pre = Client_40MHz;
} }
#else /* if (RTL8188E_SUPPORT == 1) */
void
ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *pDM_Odm, u1Byte Ant)
{
}
void
odm_PrimaryCCA_Init(
struct odm_dm_struct * pDM_Odm)
{
}
void
odm_DynamicPrimaryCCA(
struct odm_dm_struct * pDM_Odm
)
{
}
bool
ODM_DynamicPrimaryCCA_DupRTS(
struct odm_dm_struct * pDM_Odm
)
{
return false;
}
#endif /* if (RTL8188E_SUPPORT == 1) */

3
hal/odm_RegConfig8188E.c
View file

@ -20,8 +20,6 @@
#include "odm_precomp.h" #include "odm_precomp.h"
#if (RTL8188E_SUPPORT == 1)
void void
odm_ConfigRFReg_8188E( odm_ConfigRFReg_8188E(
struct odm_dm_struct * pDM_Odm, struct odm_dm_struct * pDM_Odm,
@ -189,4 +187,3 @@ odm_ConfigBB_PHY_8188E(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
} }
} }
#endif

6
include/Hal8188EPhyCfg.h
View file

@ -318,14 +318,8 @@ storePwrIndexDiffRateOffset(
#define SIC_CMD_WRITE 1 #define SIC_CMD_WRITE 1
#define SIC_CMD_READ 2 #define SIC_CMD_READ 2
#if (RTL8188E_SUPPORT == 1)
#define SIC_CMD_REG 0x1EB // 1byte #define SIC_CMD_REG 0x1EB // 1byte
#define SIC_ADDR_REG 0x1E8 // 1b9~1ba, 2 bytes #define SIC_ADDR_REG 0x1E8 // 1b9~1ba, 2 bytes
#define SIC_DATA_REG 0x1EC // 1bc~1bf #define SIC_DATA_REG 0x1EC // 1bc~1bf
#else
#define SIC_CMD_REG 0x1b8 // 1byte
#define SIC_ADDR_REG 0x1b9 // 1b9~1ba, 2 bytes
#define SIC_DATA_REG 0x1bc // 1bc~1bf
#endif
#endif // __INC_HAL8192CPHYCFG_H #endif // __INC_HAL8192CPHYCFG_H

2
include/HalHWImg8188E_BB.h
View file

@ -18,7 +18,6 @@
* *
******************************************************************************/ ******************************************************************************/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_BB_8188E_HW_IMG_H #ifndef __INC_BB_8188E_HW_IMG_H
#define __INC_BB_8188E_HW_IMG_H #define __INC_BB_8188E_HW_IMG_H
@ -52,4 +51,3 @@ ODM_ReadAndConfig_PHY_REG_PG_8188E(
); );
#endif #endif
#endif // end of HWIMG_SUPPORT

4
include/HalHWImg8188E_FW.h
View file

@ -18,7 +18,6 @@
* *
******************************************************************************/ ******************************************************************************/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_FW_8188E_HW_IMG_H #ifndef __INC_FW_8188E_HW_IMG_H
#define __INC_FW_8188E_HW_IMG_H #define __INC_FW_8188E_HW_IMG_H
@ -31,6 +30,5 @@
******************************************************************************/ ******************************************************************************/
#define ArrayLength_8188E_FW_WoWLAN 15764 #define ArrayLength_8188E_FW_WoWLAN 15764
extern const u8 Array_8188E_FW_WoWLAN[ArrayLength_8188E_FW_WoWLAN]; extern const u8 Array_8188E_FW_WoWLAN[ArrayLength_8188E_FW_WoWLAN];
#endif
#endif // end of HWIMG_SUPPORT #endif

10
include/autoconf.h
View file

@ -39,16 +39,6 @@
#define CONFIG_BR_EXT_BRNAME "br0" #define CONFIG_BR_EXT_BRNAME "br0"
/*
* Outsource Related Config
*/
#define RTL8188EE_SUPPORT 0
#define RTL8188EU_SUPPORT 1
#define RTL8188ES_SUPPORT 0
#define RTL8188E_SUPPORT (RTL8188EE_SUPPORT|RTL8188EU_SUPPORT|RTL8188ES_SUPPORT)
#define RTL8188E_FOR_TEST_CHIP 0
/* /*
* Debug Related Config * Debug Related Config
*/ */

3
include/odm_RegConfig8188E.h
View file

@ -20,8 +20,6 @@
#ifndef __INC_ODM_REGCONFIG_H_8188E #ifndef __INC_ODM_REGCONFIG_H_8188E
#define __INC_ODM_REGCONFIG_H_8188E #define __INC_ODM_REGCONFIG_H_8188E
#if (RTL8188E_SUPPORT == 1)
void odm_ConfigRFReg_8188E(struct odm_dm_struct *pDM_Odm, u4Byte Addr, u4Byte Data, void odm_ConfigRFReg_8188E(struct odm_dm_struct *pDM_Odm, u4Byte Addr, u4Byte Data,
enum ODM_RF_RADIO_PATH RF_PATH, u4Byte RegAddr); enum ODM_RF_RADIO_PATH RF_PATH, u4Byte RegAddr);
@ -70,4 +68,3 @@ odm_ConfigBB_PHY_8188E(
u4Byte Data u4Byte Data
); );
#endif #endif
#endif // end of SUPPORT

8
include/odm_precomp.h
View file

@ -57,16 +57,8 @@
#include "HalHWImg8188E_BB.h" #include "HalHWImg8188E_BB.h"
#include "Hal8188EReg.h" #include "Hal8188EReg.h"
#if (RTL8188E_FOR_TEST_CHIP >= 1)
#include "HalHWImg8188E_TestChip_MAC.h"
#include "HalHWImg8188E_TestChip_RF.h"
#include "HalHWImg8188E_TestChip_BB.h"
#endif
#ifdef CONFIG_WOWLAN #ifdef CONFIG_WOWLAN
#if (RTL8188E_SUPPORT==1)
#include "HalHWImg8188E_FW.h" #include "HalHWImg8188E_FW.h"
#endif
#endif //CONFIG_WOWLAN #endif //CONFIG_WOWLAN
#include "odm_RegConfig8188E.h" #include "odm_RegConfig8188E.h"

4
include/rtl8188e_spec.h
View file

@ -1556,11 +1556,7 @@ Current IOREG MAP
#define EEPROM_Default_AntTxPowerDiff 0x0 #define EEPROM_Default_AntTxPowerDiff 0x0
#define EEPROM_Default_TxPwDiff_CrystalCap 0x5 #define EEPROM_Default_TxPwDiff_CrystalCap 0x5
#if (RTL8188ES_SUPPORT==1) //for SDIO
#define EEPROM_Default_TxPowerLevel 0x25
#else //for USB/PCIE
#define EEPROM_Default_TxPowerLevel 0x2A #define EEPROM_Default_TxPowerLevel 0x2A
#endif
#define EEPROM_Default_HT40_2SDiff 0x0 #define EEPROM_Default_HT40_2SDiff 0x0
#define EEPROM_Default_HT20_Diff 2 // HT20<->40 default Tx Power Index Difference #define EEPROM_Default_HT20_Diff 2 // HT20<->40 default Tx Power Index Difference