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rtl8188eu: Fix all W=1 warnings

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Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger 2013-06-21 13:41:29 -05:00
parent 5c8ff88003
commit fb786d0283
29 changed files with 217 additions and 507 deletions
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2
hal/Hal8188ERateAdaptive.c
View file

@ -582,14 +582,12 @@ odm_PTDecision_8188E(
PODM_RA_INFO_T pRaInfo
)
{
u1Byte stage_BUF;
u1Byte j;
u1Byte temp_stage;
u4Byte numsc;
u4Byte num_total;
u1Byte stage_id;
stage_BUF=pRaInfo->PTStage;
numsc = 0;
num_total= pRaInfo->TOTAL* PT_PENALTY[5];
for (j=0;j<=4;j++)

10
hal/HalPhyRf_8188e.c
View file

@ -172,7 +172,7 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
u4Byte ThermalValue_AVG = 0;
s4Byte ele_A=0, ele_D, TempCCk, X, value32;
s4Byte Y, ele_C=0;
s1Byte OFDM_index[2], CCK_index=0, OFDM_index_old[2]={0,0}, CCK_index_old=0, index;
s1Byte OFDM_index[2], CCK_index=0, OFDM_index_old[2]={0,0}, CCK_index_old=0;
u4Byte i = 0, j = 0;
bool is2T = false;
bool bInteralPA = false;
@ -417,8 +417,6 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E(
if (offset >= index_mapping_NUM_88E)
offset = index_mapping_NUM_88E-1;
index = OFDM_index_mapping[j][offset];
for (i = 0; i < rf; i++)
OFDM_index[i] = pDM_Odm->RFCalibrateInfo.OFDM_index[i] + OFDM_index_mapping[j][offset];
CCK_index = pDM_Odm->RFCalibrateInfo.CCK_index + OFDM_index_mapping[j][offset];
@ -2338,7 +2336,7 @@ PHY_IQCalibrate_8188E(
bool bPathAOK, bPathBOK;
s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0;
bool is12simular, is13simular, is23simular;
bool bStartContTx = false, bSingleTone = false, bCarrierSuppression = false;
bool bSingleTone = false, bCarrierSuppression = false;
u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance,
rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable,
@ -2378,7 +2376,6 @@ PHY_IQCalibrate_8188E(
#if MP_DRIVER == 1
if (*(pDM_Odm->mp_mode) == 1)
{
bStartContTx = pMptCtx->bStartContTx;
bSingleTone = pMptCtx->bSingleTone;
bCarrierSuppression = pMptCtx->bCarrierSuppression;
}
@ -2579,7 +2576,7 @@ PHY_LCCalibrate_8188E(
#endif
)
{
bool bStartContTx = false, bSingleTone = false, bCarrierSuppression = false;
bool bSingleTone = false, bCarrierSuppression = false;
u4Byte timeout = 2000, timecount = 0;
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
@ -2606,7 +2603,6 @@ PHY_LCCalibrate_8188E(
#if MP_DRIVER == 1
if (*(pDM_Odm->mp_mode) == 1)
{
bStartContTx = pMptCtx->bStartContTx;
bSingleTone = pMptCtx->bSingleTone;
bCarrierSuppression = pMptCtx->bCarrierSuppression;
}

87
hal/odm_HWConfig.c
View file

@ -367,14 +367,13 @@ odm_RxPhyStatus92CSeries_Parsing(
PPHY_STATUS_RPT_8192CD_T pPhyStaRpt = (PPHY_STATUS_RPT_8192CD_T)pPhyStatus;
isCCKrate = ((pPktinfo->Rate >= DESC92C_RATE1M) && (pPktinfo->Rate <= DESC92C_RATE11M))?true :false;
isCCKrate = ((pPktinfo->Rate >= DESC92C_RATE1M) && (pPktinfo->Rate <= DESC92C_RATE11M)) ? true : false;
pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = -1;
pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1;
if (isCCKrate)
{
if (isCCKrate) {
u1Byte report;
u1Byte cck_agc_rpt;
@ -384,56 +383,49 @@ odm_RxPhyStatus92CSeries_Parsing(
// (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive)
//
//if (pHalData->eRFPowerState == eRfOn)
cck_highpwr = pDM_Odm->bCckHighPower;
//else
// cck_highpwr = false;
cck_highpwr = pDM_Odm->bCckHighPower;
cck_agc_rpt = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a ;
//2011.11.28 LukeLee: 88E use different LNA & VGA gain table
//The RSSI formula should be modified according to the gain table
//In 88E, cck_highpwr is always set to 1
if (pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8812))
{
if (pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8812)) {
LNA_idx = ((cck_agc_rpt & 0xE0) >>5);
VGA_idx = (cck_agc_rpt & 0x1F);
switch (LNA_idx)
{
case 7:
if (VGA_idx <= 27)
rx_pwr_all = -100 + 2*(27-VGA_idx); //VGA_idx = 27~2
else
rx_pwr_all = -100;
break;
case 6:
rx_pwr_all = -48 + 2*(2-VGA_idx); //VGA_idx = 2~0
break;
case 5:
rx_pwr_all = -42 + 2*(7-VGA_idx); //VGA_idx = 7~5
break;
case 4:
rx_pwr_all = -36 + 2*(7-VGA_idx); //VGA_idx = 7~4
break;
case 3:
//rx_pwr_all = -28 + 2*(7-VGA_idx); //VGA_idx = 7~0
rx_pwr_all = -24 + 2*(7-VGA_idx); //VGA_idx = 7~0
break;
case 2:
if (cck_highpwr)
rx_pwr_all = -12 + 2*(5-VGA_idx); //VGA_idx = 5~0
else
rx_pwr_all = -6+ 2*(5-VGA_idx);
break;
case 1:
rx_pwr_all = 8-2*VGA_idx;
break;
case 0:
rx_pwr_all = 14-2*VGA_idx;
break;
default:
//DbgPrint("CCK Exception default\n");
break;
switch (LNA_idx) {
case 7:
if (VGA_idx <= 27)
rx_pwr_all = -100 + 2*(27-VGA_idx); //VGA_idx = 27~2
else
rx_pwr_all = -100;
break;
case 6:
rx_pwr_all = -48 + 2*(2-VGA_idx); //VGA_idx = 2~0
break;
case 5:
rx_pwr_all = -42 + 2*(7-VGA_idx); //VGA_idx = 7~5
break;
case 4:
rx_pwr_all = -36 + 2*(7-VGA_idx); //VGA_idx = 7~4
break;
case 3:
rx_pwr_all = -24 + 2*(7-VGA_idx); //VGA_idx = 7~0
break;
case 2:
if (cck_highpwr)
rx_pwr_all = -12 + 2*(5-VGA_idx); //VGA_idx = 5~0
else
rx_pwr_all = -6+ 2*(5-VGA_idx);
break;
case 1:
rx_pwr_all = 8-2*VGA_idx;
break;
case 0:
rx_pwr_all = 14-2*VGA_idx;
break;
default:
break;
}
rx_pwr_all += 6;
PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all);
@ -716,8 +708,7 @@ odm_Init_RSSIForDM(
}
static void
odm_Process_RSSIForDM(
static void odm_Process_RSSIForDM(
PDM_ODM_T pDM_Odm,
PODM_PHY_INFO_T pPhyInfo,
PODM_PACKET_INFO_T pPktinfo
@ -750,7 +741,7 @@ odm_Process_RSSIForDM(
return;
}
isCCKrate = ((pPktinfo->Rate >= DESC92C_RATE1M) && (pPktinfo->Rate <= DESC92C_RATE11M))?true :false;
isCCKrate = ((pPktinfo->Rate >= DESC92C_RATE1M) && (pPktinfo->Rate <= DESC92C_RATE11M)) ? true : false;
#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
#if ((RTL8192C_SUPPORT == 1) ||(RTL8192D_SUPPORT == 1))

20
hal/rtl8188e_hal_init.c
View file

@ -57,13 +57,12 @@ static s32 iol_execute(PADAPTER padapter, u8 control)
s32 status = _FAIL;
u8 reg_0x88 = 0,reg_1c7=0;
u32 start = 0, passing_time = 0;
u32 t1,t2;
control = control&0x0f;
reg_0x88 = rtw_read8(padapter, REG_HMEBOX_E0);
rtw_write8(padapter, REG_HMEBOX_E0, reg_0x88|control);
t1 = start = rtw_get_current_time();
start = rtw_get_current_time();
while ((reg_0x88=rtw_read8(padapter, REG_HMEBOX_E0)) & control &&
(passing_time=rtw_get_passing_time_ms(start))<1000) {
}
@ -72,7 +71,6 @@ static s32 iol_execute(PADAPTER padapter, u8 control)
status = (reg_0x88 & control)?_FAIL:_SUCCESS;
if (reg_0x88 & control<<4)
status = _FAIL;
t2= rtw_get_current_time();
return status;
}
@ -99,7 +97,6 @@ efuse_phymap_to_logical(u8 * phymap, u16 _offset, u16 _size_byte, u8 *pbuf)
u16 i, j;
u16 **eFuseWord = NULL;
u16 efuse_utilized = 0;
u8 efuse_usage = 0;
u8 u1temp = 0;
efuseTbl = (u8*)rtw_zmalloc(EFUSE_MAP_LEN_88E);
@ -207,7 +204,6 @@ efuse_phymap_to_logical(u8 * phymap, u16 _offset, u16 _size_byte, u8 *pbuf)
//
// 5. Calculate Efuse utilization.
//
efuse_usage = (u1Byte)((efuse_utilized*100)/EFUSE_REAL_CONTENT_LEN_88E);
exit:
if (efuseTbl)
@ -359,7 +355,6 @@ static int rtl8188e_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit
u32 passing_time_ms;
u8 polling_ret,i;
int ret = _FAIL;
u32 t1,t2;
if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS)
goto exit;
@ -374,7 +369,6 @@ static int rtl8188e_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit
dump_mgntframe_and_wait(adapter, xmit_frame, max_wating_ms);
t1= rtw_get_current_time();
iol_mode_enable(adapter, 1);
for (i=0;i<bndy_cnt;i++){
u8 page_no = 0;
@ -383,7 +377,6 @@ static int rtl8188e_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit
break;
}
iol_mode_enable(adapter, 0);
t2 = rtw_get_current_time();
exit:
//restore BCN_HEAD
rtw_write8(adapter, REG_TDECTRL+1, 0);
@ -1036,7 +1029,6 @@ Hal_EfuseReadEFuse88E(
//u16 eFuseWord[EFUSE_MAX_SECTION_88E][EFUSE_MAX_WORD_UNIT];
u16 **eFuseWord = NULL;
u16 efuse_utilized = 0;
u8 efuse_usage = 0;
u8 u1temp = 0;
//
@ -1201,7 +1193,6 @@ Hal_EfuseReadEFuse88E(
//
// 5. Calculate Efuse utilization.
//
efuse_usage = (u1Byte)((eFuse_Addr*100)/EFUSE_REAL_CONTENT_LEN_88E);
rtw_hal_set_hwreg(Adapter, HW_VAR_EFUSE_BYTES, (u8 *)&eFuse_Addr);
exit:
@ -2884,15 +2875,12 @@ Hal_EEValueCheck(
{
case EETYPE_TX_PWR:
{
u8 *pIn, *pOut;
s8 *pIn, *pOut;
pIn = (u8*)pInValue;
pOut = (u8*)pOutValue;
if (*pIn >= 0 && *pIn <= 63)
{
if (*pIn >= 0 && *pIn <= 63) {
*pOut = *pIn;
}
else
{
} else {
RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("EETYPE_TX_PWR, value=%d is invalid, set to default=0x%x\n",
*pIn, EEPROM_Default_TxPowerLevel));
*pOut = EEPROM_Default_TxPowerLevel;

22
hal/rtl8188e_phycfg.c
View file

@ -883,11 +883,14 @@ s32 PHY_MACConfig8188E(PADAPTER Adapter)
{
int rtStatus = _SUCCESS;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
#ifndef CONFIG_EMBEDDED_FWIMG
s8 *pszMACRegFile;
#endif
s8 sz8188EMACRegFile[] = RTL8188E_PHY_MACREG;
#ifndef CONFIG_EMBEDDED_FWIMG
pszMACRegFile = sz8188EMACRegFile;
#endif
//
// Config MAC
//
@ -1469,15 +1472,20 @@ phy_BB8188E_Config_ParaFile(
u8 sz8188EBBRegPgFile[] = RTL8188E_PHY_REG_PG;
u8 sz8188EBBRegMpFile[] = RTL8188E_PHY_REG_MP;
u8 *pszBBRegFile = NULL, *pszAGCTableFile = NULL, *pszBBRegPgFile = NULL, *pszBBRegMpFile=NULL;
#ifndef CONFIG_EMBEDDED_FWIMG
u8 *pszBBRegFile = NULL;
u8 *pszBBRegPgFile = NULL;
u8 *pszAGCTableFile = NULL;
#endif
//RT_TRACE(COMP_INIT, DBG_TRACE, ("==>phy_BB8192S_Config_ParaFile\n"));
pszBBRegFile = sz8188EBBRegFile ;
pszAGCTableFile = sz8188EAGCTableFile;
#ifndef CONFIG_EMBEDDED_FWIMG
pszBBRegFile = sz8188EBBRegFile;
pszBBRegPgFile = sz8188EBBRegPgFile;
pszBBRegMpFile = sz8188EBBRegMpFile;
pszAGCTableFile = sz8188EAGCTableFile;
#endif
//
// 1. Read PHY_REG.TXT BB INIT!!
@ -2707,8 +2715,4 @@ static bool _PHY_QueryRFPathSwitch(PADAPTER pAdapter, bool is2T)
static void _PHY_DumpRFReg(PADAPTER pAdapter)
{
u32 rfRegValue,rfRegOffset;
for (rfRegOffset = 0x00;rfRegOffset<=0x30;rfRegOffset++)
rfRegValue = PHY_QueryRFReg(pAdapter,RF_PATH_A, rfRegOffset, bMaskDWord);
}

5
hal/rtl8188e_rf6052.c
View file

@ -650,13 +650,12 @@ phy_RF6052_Config_ParaFile(
static char sz88eRadioAFile[] = RTL8188E_PHY_RADIO_A;
static char sz88eRadioBFile[] = RTL8188E_PHY_RADIO_B;
#ifndef CONFIG_EMBEDDED_FWIMG
char *pszRadioAFile, *pszRadioBFile;
pszRadioAFile = sz88eRadioAFile;
pszRadioBFile = sz88eRadioBFile;
#endif
//3//-----------------------------------------------------------------
//3// <2> Initialize RF

6
hal/rtl8188e_rxdesc.c
View file

@ -185,10 +185,6 @@ void update_recvframe_attrib_88e(
{
struct rx_pkt_attrib *pattrib;
struct recv_stat report;
PRXREPORT prxreport;
//struct recv_frame_hdr *phdr;
//phdr = &precvframe->u.hdr;
report.rxdw0 = le32_to_cpu(prxstat->rxdw0);
report.rxdw1 = le32_to_cpu(prxstat->rxdw1);
@ -197,8 +193,6 @@ void update_recvframe_attrib_88e(
report.rxdw4 = le32_to_cpu(prxstat->rxdw4);
report.rxdw5 = le32_to_cpu(prxstat->rxdw5);
prxreport = (PRXREPORT)&report;
pattrib = &precvframe->u.hdr.attrib;
_rtw_memset(pattrib, 0, sizeof(struct rx_pkt_attrib));

5
hal/usb_halinit.c
View file

@ -4355,12 +4355,10 @@ static void rtl8188eu_init_default_value(_adapter * padapter)
{
PHAL_DATA_TYPE pHalData;
struct pwrctrl_priv *pwrctrlpriv;
struct dm_priv *pdmpriv;
u8 i;
pHalData = GET_HAL_DATA(padapter);
pwrctrlpriv = &padapter->pwrctrlpriv;
pdmpriv = &pHalData->dmpriv;
//init default value
@ -4371,9 +4369,6 @@ static void rtl8188eu_init_default_value(_adapter * padapter)
//init dm default value
pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = false;
pHalData->odmpriv.RFCalibrateInfo.TM_Trigger = 0;//for IQK
//pdmpriv->binitialized = false;
// pdmpriv->prv_traffic_idx = 3;
// pdmpriv->initialize = 0;
pHalData->pwrGroupCnt = 0;
pHalData->PGMaxGroup= 13;
pHalData->odmpriv.RFCalibrateInfo.ThermalValue_HP_index = 0;