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https://github.com/lwfinger/rtl8188eu.git
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rtl8188eu: Convert C90 comments to kernel form for hal/*.c
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
parent
e5113c831c
commit
fe06a8b006
30 changed files with 4334 additions and 6166 deletions
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@ -75,19 +75,19 @@ static void Hal_disable_dm(PADAPTER padapter)
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PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
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//3 1. disable firmware dynamic mechanism
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// disable Power Training, Rate Adaptive
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/* 3 1. disable firmware dynamic mechanism */
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/* disable Power Training, Rate Adaptive */
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v8 = rtw_read8(padapter, REG_BCN_CTRL);
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v8 &= ~EN_BCN_FUNCTION;
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rtw_write8(padapter, REG_BCN_CTRL, v8);
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//3 2. disable driver dynamic mechanism
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// disable Dynamic Initial Gain
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// disable High Power
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// disable Power Tracking
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/* 3 2. disable driver dynamic mechanism */
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/* disable Dynamic Initial Gain */
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/* disable High Power */
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/* disable Power Tracking */
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Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, false);
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// enable APK, LCK and IQK but disable power tracking
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/* enable APK, LCK and IQK but disable power tracking */
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pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = false;
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Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, true);
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}
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@ -111,14 +111,14 @@ static void Hal_disable_dm(PADAPTER padapter)
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*---------------------------------------------------------------------------*/
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void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter)
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{
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//HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
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/* HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); */
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struct mp_priv *pmp = &pAdapter->mppriv;
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u1Byte ChannelToSw = pmp->channel;
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ULONG ulRateIdx = pmp->rateidx;
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ULONG ulbandwidth = pmp->bandwidth;
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
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// <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.
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/* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis. */
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pmp->MptCtx.backup0x52_RF_A = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
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pmp->MptCtx.backup0x52_RF_B = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
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PHY_SetRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD);
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@ -137,38 +137,36 @@ void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, bool bInCH14)
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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// get current cck swing value and check 0xa22 & 0xa23 later to match the table.
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/* get current cck swing value and check 0xa22 & 0xa23 later to match the table. */
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CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
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if (!bInCH14)
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{
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// Readback the current bb cck swing value and compare with the table to
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// get the current swing index
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/* Readback the current bb cck swing value and compare with the table to */
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/* get the current swing index */
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for (i = 0; i < CCK_TABLE_SIZE; i++)
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{
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if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&
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(((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1]))
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{
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CCKSwingIndex = i;
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// RT_TRACE(COMP_INIT, DBG_LOUD,("Ch1~13, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",
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// (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));
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break;
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}
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}
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//Write 0xa22 0xa23
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/* Write 0xa22 0xa23 */
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TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] +
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(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8) ;
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//Write 0xa24 ~ 0xa27
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/* Write 0xa24 ~ 0xa27 */
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TempVal2 = 0;
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TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] +
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(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3]<<8) +
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(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16 )+
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(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5]<<24);
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//Write 0xa28 0xa29
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/* Write 0xa28 0xa29 */
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TempVal3 = 0;
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TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +
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(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8) ;
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@ -181,24 +179,22 @@ void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, bool bInCH14)
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(((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1]))
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{
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CCKSwingIndex = i;
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// RT_TRACE(COMP_INIT, DBG_LOUD,("Ch14, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",
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// (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));
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break;
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}
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}
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//Write 0xa22 0xa23
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/* Write 0xa22 0xa23 */
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TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] +
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(CCKSwingTable_Ch14[CCKSwingIndex][1]<<8) ;
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//Write 0xa24 ~ 0xa27
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/* Write 0xa24 ~ 0xa27 */
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TempVal2 = 0;
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TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] +
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(CCKSwingTable_Ch14[CCKSwingIndex][3]<<8) +
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(CCKSwingTable_Ch14[CCKSwingIndex][4]<<16 )+
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(CCKSwingTable_Ch14[CCKSwingIndex][5]<<24);
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//Write 0xa28 0xa29
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/* Write 0xa28 0xa29 */
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TempVal3 = 0;
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TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] +
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(CCKSwingTable_Ch14[CCKSwingIndex][7]<<8) ;
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@ -213,7 +209,7 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, bool beven)
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{
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s32 TempCCk;
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u8 CCK_index, CCK_index_old;
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u8 Action = 0; //0: no action, 1: even->odd, 2:odd->even
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u8 Action = 0; /* 0: no action, 1: even->odd, 2:odd->even */
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u8 TimeOut = 100;
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s32 i = 0;
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
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@ -225,12 +221,12 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, bool beven)
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if (!IS_92C_SERIAL(pHalData->VersionID))
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return;
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if (beven && !pMptCtx->bMptIndexEven) //odd->even
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if (beven && !pMptCtx->bMptIndexEven) /* odd->even */
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{
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Action = 2;
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pMptCtx->bMptIndexEven = true;
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}
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else if (!beven && pMptCtx->bMptIndexEven) //even->odd
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else if (!beven && pMptCtx->bMptIndexEven) /* even->odd */
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{
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Action = 1;
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pMptCtx->bMptIndexEven = false;
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@ -238,7 +234,7 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, bool beven)
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if (Action != 0)
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{
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//Query CCK default setting From 0xa24
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/* Query CCK default setting From 0xa24 */
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TempCCk = read_bbreg(pAdapter, rCCK0_TxFilter2, bMaskDWord) & bMaskCCK;
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for (i = 0; i < CCK_TABLE_SIZE; i++)
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{
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@ -247,8 +243,6 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, bool beven)
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if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4) == true)
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{
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CCK_index_old = (u8) i;
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// RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch 14 %d\n",
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// rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14));
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break;
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}
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}
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@ -257,8 +251,6 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, bool beven)
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if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4) == true)
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{
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CCK_index_old = (u8) i;
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// RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch14 %d\n",
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// rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14));
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break;
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}
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}
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@ -269,10 +261,7 @@ void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, bool beven)
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else
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CCK_index = CCK_index_old + 1;
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// RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: new CCK_index=0x%x\n",
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// CCK_index));
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//Adjust CCK according to gain index
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/* Adjust CCK according to gain index */
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if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
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rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch1_Ch13[CCK_index][0]);
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rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch1_Ch13[CCK_index][1]);
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@ -316,7 +305,7 @@ void Hal_SetChannel(PADAPTER pAdapter)
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u8 rate = pmp->rateidx;
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// set RF channel register
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/* set RF channel register */
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for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)
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{
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if (IS_HARDWARE_TYPE_8192D(pAdapter))
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@ -356,12 +345,12 @@ void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 *TxPower)
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u32 tmpval = 0;
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// rf-A cck tx power
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/* rf-A cck tx power */
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write_bbreg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, TxPower[RF_PATH_A]);
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tmpval = (TxPower[RF_PATH_A]<<16) | (TxPower[RF_PATH_A]<<8) | TxPower[RF_PATH_A];
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write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
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// rf-B cck tx power
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/* rf-B cck tx power */
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write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, TxPower[RF_PATH_B]);
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tmpval = (TxPower[RF_PATH_B]<<16) | (TxPower[RF_PATH_B]<<8) | TxPower[RF_PATH_B];
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write_bbreg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
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@ -379,7 +368,7 @@ void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 *TxPower)
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
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// HT Tx-rf(A)
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/* HT Tx-rf(A) */
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tmpval = TxPower[RF_PATH_A];
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TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;
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@ -390,7 +379,7 @@ void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 *TxPower)
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write_bbreg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
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write_bbreg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
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// HT Tx-rf(B)
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/* HT Tx-rf(B) */
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tmpval = TxPower[RF_PATH_B];
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TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;
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@ -432,7 +421,7 @@ void Hal_SetAntennaPathPower(PADAPTER pAdapter)
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case RF_8256:
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case RF_6052:
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Hal_SetCCKTxPower(pAdapter, TxPowerLevel);
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if (pAdapter->mppriv.rateidx < MPT_RATE_6M) // CCK rate
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if (pAdapter->mppriv.rateidx < MPT_RATE_6M) /* CCK rate */
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Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);
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Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
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break;
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@ -469,13 +458,13 @@ void Hal_SetTxPower(PADAPTER pAdapter)
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switch (pHalData->rf_chip)
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{
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// 2008/09/12 MH Test only !! We enable the TX power tracking for MP!!!!!
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// We should call normal driver API later!!
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/* 2008/09/12 MH Test only !! We enable the TX power tracking for MP!!!!! */
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/* We should call normal driver API later!! */
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case RF_8225:
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case RF_8256:
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case RF_6052:
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Hal_SetCCKTxPower(pAdapter, TxPowerLevel);
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if (pAdapter->mppriv.rateidx < MPT_RATE_6M) // CCK rate
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if (pAdapter->mppriv.rateidx < MPT_RATE_6M) /* CCK rate */
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Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);
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Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
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break;
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@ -483,9 +472,6 @@ void Hal_SetTxPower(PADAPTER pAdapter)
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default:
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break;
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}
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// SetCCKTxPower(pAdapter, TxPower);
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// SetOFDMTxPower(pAdapter, TxPower);
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}
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void Hal_SetDataRate(PADAPTER pAdapter)
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@ -509,8 +495,8 @@ void Hal_SetAntenna(PADAPTER pAdapter)
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p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
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p_ofdm_tx->r_ant_ht1 = 0x1;
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p_ofdm_tx->r_ant_ht2 = 0x2; // Second TX RF path is A
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p_ofdm_tx->r_ant_non_ht = 0x3; // 0x1+0x2=0x3
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p_ofdm_tx->r_ant_ht2 = 0x2; /* Second TX RF path is A */
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p_ofdm_tx->r_ant_non_ht = 0x3; /* 0x1+0x2=0x3 */
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switch (pAdapter->mppriv.antenna_tx)
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{
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@ -523,17 +509,15 @@ void Hal_SetAntenna(PADAPTER pAdapter)
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p_cck_txrx->r_ccktx_enable = 0x8;
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chgTx = 1;
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// From SD3 Willis suggestion !!! Set RF A=TX and B as standby
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// if (IS_HARDWARE_TYPE_8192S(pAdapter))
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{
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/* From SD3 Willis suggestion !!! Set RF A=TX and B as standby */
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write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
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write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
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r_ofdm_tx_en_val = 0x3;
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// Power save
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//cosa r_ant_select_ofdm_val = 0x11111111;
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/* Power save */
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/* cosa r_ant_select_ofdm_val = 0x11111111; */
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// We need to close RFB by SW control
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/* We need to close RFB by SW control */
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if (pHalData->rf_type == RF_2T2R)
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{
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PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
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@ -542,7 +526,6 @@ void Hal_SetAntenna(PADAPTER pAdapter)
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PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
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PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
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}
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}
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break;
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case ANTENNA_B:
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@ -554,31 +537,26 @@ void Hal_SetAntenna(PADAPTER pAdapter)
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p_cck_txrx->r_ccktx_enable = 0x4;
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chgTx = 1;
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// From SD3 Willis suggestion !!! Set RF A as standby
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//if (IS_HARDWARE_TYPE_8192S(pAdapter))
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{
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/* From SD3 Willis suggestion !!! Set RF A as standby */
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PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
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PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
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// r_ofdm_tx_en_val = 0x3;
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// Power save
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//cosa r_ant_select_ofdm_val = 0x22222222;
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/* Power save */
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/* cosa r_ant_select_ofdm_val = 0x22222222; */
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// 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.
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// 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control
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/* 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table. */
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/* 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control */
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if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R)
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{
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PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
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PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
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PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
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// PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
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PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
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PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
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}
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}
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break;
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case ANTENNA_AB: // For 8192S
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case ANTENNA_AB: /* For 8192S */
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p_ofdm_tx->r_tx_antenna = 0x3;
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r_ofdm_tx_en_val = 0x3;
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p_ofdm_tx->r_ant_l = 0x3;
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@ -587,15 +565,13 @@ void Hal_SetAntenna(PADAPTER pAdapter)
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p_cck_txrx->r_ccktx_enable = 0xC;
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chgTx = 1;
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// From SD3 Willis suggestion !!! Set RF B as standby
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//if (IS_HARDWARE_TYPE_8192S(pAdapter))
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{
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/* From SD3 Willis suggestion !!! Set RF B as standby */
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||||
PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
|
||||
|
||||
// Disable Power save
|
||||
//cosa r_ant_select_ofdm_val = 0x3321333;
|
||||
// 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control
|
||||
/* Disable Power save */
|
||||
/* cosa r_ant_select_ofdm_val = 0x3321333; */
|
||||
/* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control */
|
||||
if (pHalData->rf_type == RF_2T2R)
|
||||
{
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
|
||||
|
|
@ -603,38 +579,36 @@ void Hal_SetAntenna(PADAPTER pAdapter)
|
|||
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
//
|
||||
// r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D
|
||||
// r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D
|
||||
// r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D
|
||||
//
|
||||
/* */
|
||||
/* r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
|
||||
/* r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
|
||||
/* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D */
|
||||
/* */
|
||||
switch (pAdapter->mppriv.antenna_rx)
|
||||
{
|
||||
case ANTENNA_A:
|
||||
r_rx_antenna_ofdm = 0x1; // A
|
||||
p_cck_txrx->r_cckrx_enable = 0x0; // default: A
|
||||
p_cck_txrx->r_cckrx_enable_2 = 0x0; // option: A
|
||||
r_rx_antenna_ofdm = 0x1; /* A */
|
||||
p_cck_txrx->r_cckrx_enable = 0x0; /* default: A */
|
||||
p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A */
|
||||
chgRx = 1;
|
||||
break;
|
||||
|
||||
case ANTENNA_B:
|
||||
r_rx_antenna_ofdm = 0x2; // B
|
||||
p_cck_txrx->r_cckrx_enable = 0x1; // default: B
|
||||
p_cck_txrx->r_cckrx_enable_2 = 0x1; // option: B
|
||||
r_rx_antenna_ofdm = 0x2; /* B */
|
||||
p_cck_txrx->r_cckrx_enable = 0x1; /* default: B */
|
||||
p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option: B */
|
||||
chgRx = 1;
|
||||
break;
|
||||
|
||||
case ANTENNA_AB:
|
||||
r_rx_antenna_ofdm = 0x3; // AB
|
||||
p_cck_txrx->r_cckrx_enable = 0x0; // default:A
|
||||
p_cck_txrx->r_cckrx_enable_2 = 0x1; // option:B
|
||||
r_rx_antenna_ofdm = 0x3; /* AB */
|
||||
p_cck_txrx->r_cckrx_enable = 0x0; /* default:A */
|
||||
p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option:B */
|
||||
chgRx = 1;
|
||||
break;
|
||||
|
||||
|
|
@ -649,12 +623,12 @@ void Hal_SetAntenna(PADAPTER pAdapter)
|
|||
case RF_8225:
|
||||
case RF_8256:
|
||||
case RF_6052:
|
||||
//r_ant_sel_cck_val = r_ant_select_cck_val;
|
||||
PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); //OFDM Tx
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); //OFDM Tx
|
||||
PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); //OFDM Rx
|
||||
PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); //OFDM Rx
|
||||
PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);//r_ant_sel_cck_val); //CCK TxRx
|
||||
/* r_ant_sel_cck_val = r_ant_select_cck_val; */
|
||||
PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); /* OFDM Tx */
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /* OFDM Tx */
|
||||
PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /* OFDM Rx */
|
||||
PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /* OFDM Rx */
|
||||
PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val); /* CCK TxRx */
|
||||
|
||||
break;
|
||||
|
||||
|
|
@ -696,19 +670,13 @@ void Hal_TriggerRFThermalMeter(PADAPTER pAdapter)
|
|||
{
|
||||
|
||||
_write_rfreg( pAdapter, RF_PATH_A , RF_T_METER_88E , BIT17 |BIT16 , 0x03 );
|
||||
|
||||
// RT_TRACE(_module_mp_,_drv_alert_, ("TriggerRFThermalMeter() finished.\n" ));
|
||||
}
|
||||
|
||||
u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter)
|
||||
{
|
||||
u32 ThermalValue = 0;
|
||||
|
||||
//ThermalValue = _read_rfreg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F); // 0x24: RF Reg[4:0]
|
||||
|
||||
ThermalValue = _read_rfreg(pAdapter, RF_PATH_A, RF_T_METER_88E, 0xfc00);
|
||||
|
||||
// RT_TRACE(_module_mp_, _drv_alert_, ("ThermalValue = 0x%x\n", ThermalValue));
|
||||
return (u8)ThermalValue;
|
||||
}
|
||||
|
||||
|
|
@ -723,52 +691,51 @@ void Hal_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
|
|||
{
|
||||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
|
||||
pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;
|
||||
if (bStart)// Start Single Carrier.
|
||||
if (bStart)/* Start Single Carrier. */
|
||||
{
|
||||
RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test start\n"));
|
||||
// 1. if OFDM block on?
|
||||
/* 1. if OFDM block on? */
|
||||
if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
|
||||
write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on
|
||||
write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);/* set OFDM block on */
|
||||
|
||||
{
|
||||
// 2. set CCK test mode off, set to CCK normal mode
|
||||
/* 2. set CCK test mode off, set to CCK normal mode */
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
|
||||
// 3. turn on scramble setting
|
||||
/* 3. turn on scramble setting */
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
|
||||
}
|
||||
// 4. Turn On Single Carrier Tx and turn off the other test modes.
|
||||
/* 4. Turn On Single Carrier Tx and turn off the other test modes. */
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
|
||||
#ifdef CONFIG_RTL8192C
|
||||
// 5. Disable TX power saving at STF & LLTF
|
||||
/* 5. Disable TX power saving at STF & LLTF */
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, BIT22, 1);
|
||||
#endif
|
||||
//for dynamic set Power index.
|
||||
/* for dynamic set Power index. */
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
|
||||
}
|
||||
else// Stop Single Carrier.
|
||||
else/* Stop Single Carrier. */
|
||||
{
|
||||
RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test stop\n"));
|
||||
|
||||
// Turn off all test modes.
|
||||
/* Turn off all test modes. */
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
|
||||
#ifdef CONFIG_RTL8192C
|
||||
// Cancel disable TX power saving at STF&LLTF
|
||||
/* Cancel disable TX power saving at STF&LLTF */
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, BIT22, 0);
|
||||
#endif
|
||||
//Delay 10 ms //delay_ms(10);
|
||||
rtw_msleep_os(10);
|
||||
|
||||
//BB Reset
|
||||
/* BB Reset */
|
||||
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
|
||||
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
|
||||
|
||||
//Stop for dynamic set Power index.
|
||||
/* Stop for dynamic set Power index. */
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
|
||||
|
||||
|
|
@ -798,10 +765,10 @@ void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
|
|||
}
|
||||
|
||||
pAdapter->mppriv.MptCtx.bSingleTone = bStart;
|
||||
if (bStart)// Start Single Tone.
|
||||
if (bStart)/* Start Single Tone. */
|
||||
{
|
||||
RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test start\n"));
|
||||
{ // <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)
|
||||
{ /* <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu) */
|
||||
if (IS_HARDWARE_TYPE_8188E(pAdapter))
|
||||
{
|
||||
reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask);
|
||||
|
|
@ -818,31 +785,31 @@ void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
|
|||
_write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x01);
|
||||
rtw_usleep_os(100);
|
||||
if (rfPath == RF_PATH_A)
|
||||
write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x10000); // PAD all on.
|
||||
write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x10000); /* PAD all on. */
|
||||
else if (rfPath == RF_PATH_B)
|
||||
write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x10000); // PAD all on.
|
||||
write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); // PAD all on.
|
||||
write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x10000); /* PAD all on. */
|
||||
write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); /* PAD all on. */
|
||||
rtw_usleep_os(100);
|
||||
}
|
||||
else
|
||||
{
|
||||
write_rfreg(pAdapter, rfPath, 0x21, 0xd4000);
|
||||
rtw_usleep_os(100);
|
||||
write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); // PAD all on.
|
||||
write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); /* PAD all on. */
|
||||
rtw_usleep_os(100);
|
||||
}
|
||||
|
||||
//for dynamic set Power index.
|
||||
/* for dynamic set Power index. */
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
|
||||
}
|
||||
else// Stop Single Tone.
|
||||
else/* Stop Single Tone. */
|
||||
{
|
||||
RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test stop\n"));
|
||||
|
||||
{ // <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)
|
||||
// <20120326, Kordan> Only in single tone mode. (asked by Edlu)
|
||||
{ /* <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu) */
|
||||
/* <20120326, Kordan> Only in single tone mode. (asked by Edlu) */
|
||||
if (IS_HARDWARE_TYPE_8188E(pAdapter))
|
||||
{
|
||||
reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask);
|
||||
|
|
@ -856,17 +823,17 @@ void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
|
|||
if (is92C) {
|
||||
_write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x00);
|
||||
rtw_usleep_os(100);
|
||||
write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x32d75); // PAD all on.
|
||||
write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x32d75); // PAD all on.
|
||||
write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x32d75); /* PAD all on. */
|
||||
write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x32d75); /* PAD all on. */
|
||||
rtw_usleep_os(100);
|
||||
} else {
|
||||
write_rfreg(pAdapter, rfPath, 0x21, 0x54000);
|
||||
rtw_usleep_os(100);
|
||||
write_rfreg(pAdapter, rfPath, 0x00, 0x30000); // PAD all on.
|
||||
write_rfreg(pAdapter, rfPath, 0x00, 0x30000); /* PAD all on. */
|
||||
rtw_usleep_os(100);
|
||||
}
|
||||
|
||||
//Stop for dynamic set Power index.
|
||||
/* Stop for dynamic set Power index. */
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
|
||||
|
||||
|
|
@ -879,53 +846,49 @@ void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
|
|||
void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
|
||||
{
|
||||
pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;
|
||||
if (bStart) // Start Carrier Suppression.
|
||||
if (bStart) /* Start Carrier Suppression. */
|
||||
{
|
||||
RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test start\n"));
|
||||
//if (pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B)
|
||||
if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)
|
||||
{
|
||||
// 1. if CCK block on?
|
||||
/* 1. if CCK block on? */
|
||||
if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
|
||||
write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on
|
||||
write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/* set CCK block on */
|
||||
|
||||
//Turn Off All Test Mode
|
||||
/* Turn Off All Test Mode */
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
|
||||
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); //transmit mode
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); //turn off scramble setting
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /* transmit mode */
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); /* turn off scramble setting */
|
||||
|
||||
//Set CCK Tx Test Rate
|
||||
//PHY_SetBBReg(pAdapter, rCCK0_System, bCCKTxRate, pMgntInfo->ForcedDataRate);
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); //Set FTxRate to 1Mbps
|
||||
/* Set CCK Tx Test Rate */
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); /* Set FTxRate to 1Mbps */
|
||||
}
|
||||
|
||||
//for dynamic set Power index.
|
||||
/* for dynamic set Power index. */
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
|
||||
}
|
||||
else// Stop Carrier Suppression.
|
||||
else/* Stop Carrier Suppression. */
|
||||
{
|
||||
RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test stop\n"));
|
||||
//if (pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B)
|
||||
if (pAdapter->mppriv.rateidx <= MPT_RATE_11M ) {
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); //normal mode
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); //turn on scramble setting
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /* normal mode */
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /* turn on scramble setting */
|
||||
|
||||
//BB Reset
|
||||
/* BB Reset */
|
||||
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
|
||||
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
|
||||
}
|
||||
|
||||
//Stop for dynamic set Power index.
|
||||
/* Stop for dynamic set Power index. */
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
|
||||
|
||||
}
|
||||
//DbgPrint("\n MPT_ProSetCarrierSupp() is finished.\n");
|
||||
}
|
||||
|
||||
void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)
|
||||
|
|
@ -937,28 +900,28 @@ void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)
|
|||
RT_TRACE(_module_mp_, _drv_alert_,
|
||||
("SetCCKContinuousTx: test start\n"));
|
||||
|
||||
// 1. if CCK block on?
|
||||
/* 1. if CCK block on? */
|
||||
if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
|
||||
write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on
|
||||
write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/* set CCK block on */
|
||||
|
||||
//Turn Off All Test Mode
|
||||
/* Turn Off All Test Mode */
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
|
||||
//Set CCK Tx Test Rate
|
||||
/* Set CCK Tx Test Rate */
|
||||
cckrate = pAdapter->mppriv.rateidx;
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); //transmit mode
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); //turn on scramble setting
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /* transmit mode */
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); /* turn on scramble setting */
|
||||
|
||||
#ifdef CONFIG_RTL8192C
|
||||
// Patch for CCK 11M waveform
|
||||
/* Patch for CCK 11M waveform */
|
||||
if (cckrate == MPT_RATE_1M)
|
||||
write_bbreg(pAdapter, 0xA71, BIT(6), bDisable);
|
||||
else
|
||||
write_bbreg(pAdapter, 0xA71, BIT(6), bEnable);
|
||||
#endif
|
||||
//for dynamic set Power index.
|
||||
/* for dynamic set Power index. */
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
|
||||
|
|
@ -967,14 +930,14 @@ void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)
|
|||
RT_TRACE(_module_mp_, _drv_info_,
|
||||
("SetCCKContinuousTx: test stop\n"));
|
||||
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); //normal mode
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); //turn on scramble setting
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /* normal mode */
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); /* turn on scramble setting */
|
||||
|
||||
//BB Reset
|
||||
/* BB Reset */
|
||||
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
|
||||
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
|
||||
|
||||
//Stop for dynamic set Power index.
|
||||
/* Stop for dynamic set Power index. */
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
|
||||
}
|
||||
|
|
@ -989,23 +952,23 @@ void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)
|
|||
|
||||
if (bStart) {
|
||||
RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n"));
|
||||
// 1. if OFDM block on?
|
||||
/* 1. if OFDM block on? */
|
||||
if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
|
||||
write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on
|
||||
write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);/* set OFDM block on */
|
||||
{
|
||||
|
||||
// 2. set CCK test mode off, set to CCK normal mode
|
||||
/* 2. set CCK test mode off, set to CCK normal mode */
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
|
||||
|
||||
// 3. turn on scramble setting
|
||||
/* 3. turn on scramble setting */
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
|
||||
}
|
||||
// 4. Turn On Continue Tx and turn off the other test modes.
|
||||
/* 4. Turn On Continue Tx and turn off the other test modes. */
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
|
||||
|
||||
//for dynamic set Power index.
|
||||
/* for dynamic set Power index. */
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
|
||||
|
|
@ -1014,13 +977,13 @@ void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)
|
|||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
|
||||
//Delay 10 ms
|
||||
/* Delay 10 ms */
|
||||
rtw_msleep_os(10);
|
||||
//BB Reset
|
||||
/* BB Reset */
|
||||
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
|
||||
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
|
||||
|
||||
//Stop for dynamic set Power index.
|
||||
/* Stop for dynamic set Power index. */
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
|
||||
}
|
||||
|
|
@ -1046,4 +1009,4 @@ void Hal_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
|
|||
}
|
||||
}
|
||||
|
||||
#endif // CONFIG_MP_INCLUDE
|
||||
#endif /* CONFIG_MP_INCLUDE */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue