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rtl8188eu: Convert C90 comments to kernel form for hal/*.c
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
parent
e5113c831c
commit
fe06a8b006
30 changed files with 4334 additions and 6166 deletions
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@ -48,17 +48,17 @@
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#include <rtl8188e_hal.h>
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/*---------------------------Define Local Constant---------------------------*/
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// Define local structure for debug!!!!!
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/* Define local structure for debug!!!!! */
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typedef struct RF_Shadow_Compare_Map {
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// Shadow register value
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/* Shadow register value */
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u32 Value;
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// Compare or not flag
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/* Compare or not flag */
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u8 Compare;
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// Record If it had ever modified unpredicted
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/* Record If it had ever modified unpredicted */
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u8 ErrorOrNot;
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// Recorver Flag
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/* Recorver Flag */
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u8 Recorver;
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//
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/* */
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u8 Driver_Write;
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}RF_SHADOW_T;
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/*---------------------------Define Local Constant---------------------------*/
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@ -69,8 +69,8 @@ typedef struct RF_Shadow_Compare_Map {
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/*------------------------Define local variable------------------------------*/
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// 2008/11/20 MH For Debug only, RF
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//static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG] = {0};
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/* 2008/11/20 MH For Debug only, RF */
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/* static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG] = {0}; */
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static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
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/*------------------------Define local variable------------------------------*/
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@ -80,7 +80,7 @@ static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
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*
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* Overview: For RL6052, we must change some RF settign for 1T or 2T.
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*
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* Input: u2Byte DataRate // 0x80-8f, 0x90-9f
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* Input: u2Byte DataRate 0x80-8f, 0x90-9f
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*
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* Output: NONE
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*
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@ -95,7 +95,7 @@ static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
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void rtl8188e_RF_ChangeTxPath( PADAPTER Adapter,
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u16 DataRate)
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{
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// We do not support gain table change inACUT now !!!! Delete later !!!
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/* We do not support gain table change inACUT now !!!! Delete later !!! */
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} /* RF_ChangeTxPath */
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@ -105,7 +105,7 @@ void rtl8188e_RF_ChangeTxPath( PADAPTER Adapter,
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* Overview: This function is called by SetBWModeCallback8190Pci() only
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*
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* Input: PADAPTER Adapter
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* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
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* WIRELESS_BANDWIDTH_E Bandwidth 20M or 40M
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*
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* Output: NONE
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*
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@ -116,7 +116,7 @@ void rtl8188e_RF_ChangeTxPath( PADAPTER Adapter,
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void
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rtl8188e_PHY_RF6052SetBandwidth(
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PADAPTER Adapter,
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HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
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HT_CHANNEL_WIDTH Bandwidth) /* 20M or 40M */
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{
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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@ -133,7 +133,7 @@ rtl8188e_PHY_RF6052SetBandwidth(
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break;
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default:
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//RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ));
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/* RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth )); */
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break;
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}
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@ -166,13 +166,13 @@ rtl8188e_PHY_RF6052SetCckTxPower(
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struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
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struct dm_priv *pdmpriv = &pHalData->dmpriv;
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struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
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//PMGNT_INFO pMgntInfo=&Adapter->MgntInfo;
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/* PMGNT_INFO pMgntInfo=&Adapter->MgntInfo; */
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u32 TxAGC[2]={0, 0}, tmpval=0,pwrtrac_value;
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bool TurboScanOff = false;
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u8 idx1, idx2;
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u8* ptr;
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u8 direction;
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//FOR CE ,must disable turbo scan
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/* FOR CE ,must disable turbo scan */
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TurboScanOff = true;
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@ -181,7 +181,7 @@ rtl8188e_PHY_RF6052SetCckTxPower(
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TxAGC[RF_PATH_A] = 0x3f3f3f3f;
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TxAGC[RF_PATH_B] = 0x3f3f3f3f;
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TurboScanOff = true;//disable turbo scan
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TurboScanOff = true;/* disable turbo scan */
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if (TurboScanOff)
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{
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@ -191,7 +191,7 @@ rtl8188e_PHY_RF6052SetCckTxPower(
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pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
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(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
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#ifdef CONFIG_USB_HCI
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// 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20.
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/* 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20. */
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if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA)
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TxAGC[idx1] = 0x20;
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#endif
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@ -200,9 +200,9 @@ rtl8188e_PHY_RF6052SetCckTxPower(
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}
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else
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{
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// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.
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// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.
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// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.
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/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
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/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
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/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */
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if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
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{
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TxAGC[RF_PATH_A] = 0x10101010;
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@ -247,41 +247,35 @@ rtl8188e_PHY_RF6052SetCckTxPower(
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}
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ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 1, &direction, &pwrtrac_value);
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if (direction == 1) // Increase TX pwoer
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if (direction == 1) /* Increase TX pwoer */
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{
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TxAGC[0] += pwrtrac_value;
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TxAGC[1] += pwrtrac_value;
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}
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else if (direction == 2) // Decrease TX pwoer
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else if (direction == 2) /* Decrease TX pwoer */
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{
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TxAGC[0] -= pwrtrac_value;
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TxAGC[1] -= pwrtrac_value;
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}
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// rf-A cck tx power
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/* rf-A cck tx power */
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tmpval = TxAGC[RF_PATH_A]&0xff;
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PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
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//RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_A_CCK1_Mcs32));
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tmpval = TxAGC[RF_PATH_A]>>8;
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PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
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//RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11));
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// rf-B cck tx power
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/* rf-B cck tx power */
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tmpval = TxAGC[RF_PATH_B]>>24;
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PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval);
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//RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11));
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tmpval = TxAGC[RF_PATH_B]&0x00ffffff;
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PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
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//RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n",
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// tmpval, rTxAGC_B_CCK1_55_Mcs32));
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} /* PHY_RF6052SetCckTxPower */
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//
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// powerbase0 for OFDM rates
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// powerbase1 for HT MCS rates
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//
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/* */
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/* powerbase0 for OFDM rates */
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/* powerbase1 for HT MCS rates */
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/* */
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static void getPowerBase88E(
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PADAPTER Adapter,
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u8* pPowerLevelOFDM,
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@ -304,12 +298,11 @@ static void getPowerBase88E(
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powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
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*(OfdmBase+i) = powerBase0;
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//DBG_88E(" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i));
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}
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for (i=0; i<pHalData->NumTotalRFPath; i++)
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{
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//Check HT20 to HT40 diff
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/* Check HT20 to HT40 diff */
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if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
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{
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powerlevel[i] = pPowerLevelBW20[i];
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@ -321,7 +314,6 @@ static void getPowerBase88E(
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powerBase1 = powerlevel[i];
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powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
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*(MCSBase+i) = powerBase1;
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//DBG_88E(" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i));
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}
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}
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@ -342,101 +334,61 @@ static void getTxPowerWriteValByRegulatory88E(
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u4Byte writeVal, customer_limit, rf;
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u1Byte Regulatory = pHalData->EEPROMRegulatory;
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//
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// Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
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//
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/* */
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/* Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */
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/* */
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for (rf=0; rf<2; rf++) {
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switch (Regulatory)
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{
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case 0: // Realtek better performance
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// increase power diff defined by Realtek for large power
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case 0: /* Realtek better performance */
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/* increase power diff defined by Realtek for large power */
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chnlGroup = 0;
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//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
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// chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
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writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
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((index<2)?powerBase0[rf]:powerBase1[rf]);
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//RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
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break;
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case 1: // Realtek regulatory
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// increase power diff defined by Realtek for regulatory
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case 1: /* Realtek regulatory */
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/* increase power diff defined by Realtek for regulatory */
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{
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if (pHalData->pwrGroupCnt == 1)
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chnlGroup = 0;
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if (pHalData->pwrGroupCnt >= pHalData->PGMaxGroup)
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{
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if (Channel < 3) // Chanel 1-2
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if (Channel < 3) /* Chanel 1-2 */
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chnlGroup = 0;
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else if (Channel < 6) // Channel 3-5
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else if (Channel < 6) /* Channel 3-5 */
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chnlGroup = 1;
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else if (Channel <9) // Channel 6-8
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else if (Channel <9) /* Channel 6-8 */
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chnlGroup = 2;
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else if (Channel <12) // Channel 9-11
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else if (Channel <12) /* Channel 9-11 */
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chnlGroup = 3;
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else if (Channel <14) // Channel 12-13
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else if (Channel <14) /* Channel 12-13 */
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chnlGroup = 4;
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else if (Channel ==14) // Channel 14
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else if (Channel ==14) /* Channel 14 */
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chnlGroup = 5;
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/*
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if (Channel <= 3)
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chnlGroup = 0;
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else if (Channel >= 4 && Channel <= 9)
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chnlGroup = 1;
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else if (Channel > 9)
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chnlGroup = 2;
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if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
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chnlGroup++;
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else
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chnlGroup+=4;
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*/
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}
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//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
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//chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
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writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
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((index<2)?powerBase0[rf]:powerBase1[rf]);
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//RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
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}
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break;
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case 2: // Better regulatory
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// don't increase any power diff
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case 2: /* Better regulatory */
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/* don't increase any power diff */
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writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]);
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//RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
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break;
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case 3: // Customer defined power diff.
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// increase power diff defined by customer.
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case 3: /* Customer defined power diff. */
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/* increase power diff defined by customer. */
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chnlGroup = 0;
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//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
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// chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
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/*
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if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
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{
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RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 40MHz rf(%c) = 0x%x\n",
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((rf==0)?'A':'B'), pHalData->PwrGroupHT40[rf][Channel-1]));
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}
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else
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{
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RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 20MHz rf(%c) = 0x%x\n",
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((rf==0)?'A':'B'), pHalData->PwrGroupHT20[rf][Channel-1]));
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}*/
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if (index < 2)
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pwr_diff = pHalData->TxPwrLegacyHtDiff[rf][Channel-1];
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else if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
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pwr_diff = pHalData->TxPwrHt20Diff[rf][Channel-1];
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//RTPRINT(FPHY, PHY_TXPWR, ("power diff rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), pwr_diff));
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if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
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customer_pwr_limit = pHalData->PwrGroupHT40[rf][Channel-1];
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else
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customer_pwr_limit = pHalData->PwrGroupHT20[rf][Channel-1];
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//RTPRINT(FPHY, PHY_TXPWR, ("customer pwr limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_pwr_limit));
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if (pwr_diff >= customer_pwr_limit)
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pwr_diff = 0;
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else
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@ -451,46 +403,34 @@ static void getTxPowerWriteValByRegulatory88E(
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}
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customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
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(pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
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//RTPRINT(FPHY, PHY_TXPWR, ("Customer's limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_limit));
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writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]);
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//RTPRINT(FPHY, PHY_TXPWR, ("Customer, writeVal rf(%c)= 0x%x\n", ((rf==0)?'A':'B'), writeVal));
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break;
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default:
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chnlGroup = 0;
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writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
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((index<2)?powerBase0[rf]:powerBase1[rf]);
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//RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
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break;
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}
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// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.
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// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.
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// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.
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//92d do not need this
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/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
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/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
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/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */
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/* 92d do not need this */
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if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
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writeVal = 0x14141414;
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else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
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writeVal = 0x00000000;
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// 20100628 Joseph: High power mode for BT-Coexist mechanism.
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// This mechanism is only applied when Driver-Highpower-Mechanism is OFF.
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/* 20100628 Joseph: High power mode for BT-Coexist mechanism. */
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/* This mechanism is only applied when Driver-Highpower-Mechanism is OFF. */
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if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
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{
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//RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n"));
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writeVal = writeVal - 0x06060606;
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}
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else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
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{
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//RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n"));
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writeVal = writeVal ;
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}
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/*
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if (pMgntInfo->bDisableTXPowerByRate)
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{
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// add for OID_RT_11N_TX_POWER_BY_RATE ,disable tx powre change by rate
|
||||
writeVal = 0x2c2c2c2c;
|
||||
}
|
||||
*/
|
||||
*(pOutWriteVal+rf) = writeVal;
|
||||
}
|
||||
}
|
||||
|
|
@ -529,9 +469,8 @@ static void writeOFDMPowerReg88E(
|
|||
RegOffset = RegOffset_B[index];
|
||||
|
||||
PHY_SetBBReg(Adapter, RegOffset, bMaskDWord, writeVal);
|
||||
//RTPRINT(FPHY, PHY_TXPWR, ("Set 0x%x = %08x\n", RegOffset, writeVal));
|
||||
|
||||
// 201005115 Joseph: Set Tx Power diff for Tx power training mechanism.
|
||||
/* 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */
|
||||
if (((pHalData->rf_type == RF_2T2R) &&
|
||||
(RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs15_Mcs12))||
|
||||
((pHalData->rf_type != RF_2T2R) &&
|
||||
|
|
@ -591,15 +530,12 @@ rtl8188e_PHY_RF6052SetOFDMTxPower(
|
|||
u8 direction;
|
||||
u8 index = 0;
|
||||
|
||||
|
||||
//DBG_88E("PHY_RF6052SetOFDMTxPower, channel(%d)\n", Channel);
|
||||
|
||||
getPowerBase88E(Adapter, pPowerLevelOFDM,pPowerLevelBW20,pPowerLevelBW40, Channel, &powerBase0[0], &powerBase1[0]);
|
||||
|
||||
//
|
||||
// 2012/04/23 MH According to power tracking value, we need to revise OFDM tx power.
|
||||
// This is ued to fix unstable power tracking mode.
|
||||
//
|
||||
/* */
|
||||
/* 2012/04/23 MH According to power tracking value, we need to revise OFDM tx power. */
|
||||
/* This is ued to fix unstable power tracking mode. */
|
||||
/* */
|
||||
ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 0, &direction, &pwrtrac_value);
|
||||
|
||||
for (index=0; index<6; index++)
|
||||
|
|
@ -622,18 +558,11 @@ rtl8188e_PHY_RF6052SetOFDMTxPower(
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
phy_RF6052_Config_HardCode(
|
||||
PADAPTER Adapter
|
||||
)
|
||||
{
|
||||
|
||||
// Set Default Bandwidth to 20M
|
||||
//Adapter->HalFunc .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20);
|
||||
|
||||
// TODO: Set Default Channel to channel one for RTL8225
|
||||
|
||||
}
|
||||
|
||||
static int
|
||||
|
|
@ -657,18 +586,16 @@ phy_RF6052_Config_ParaFile(
|
|||
pszRadioBFile = sz88eRadioBFile;
|
||||
#endif
|
||||
|
||||
//3//-----------------------------------------------------------------
|
||||
//3// <2> Initialize RF
|
||||
//3//-----------------------------------------------------------------
|
||||
//for (eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
|
||||
/* 3----------------------------------------------------------------- */
|
||||
/* 3 <2> Initialize RF */
|
||||
/* 3----------------------------------------------------------------- */
|
||||
for (eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
|
||||
{
|
||||
|
||||
pPhyReg = &pHalData->PHYRegDef[eRFPath];
|
||||
|
||||
/*----Store original RFENV control type----*/
|
||||
switch (eRFPath)
|
||||
{
|
||||
switch (eRFPath) {
|
||||
case RF_PATH_A:
|
||||
case RF_PATH_C:
|
||||
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
|
||||
|
|
@ -681,22 +608,21 @@ phy_RF6052_Config_ParaFile(
|
|||
|
||||
/*----Set RF_ENV enable----*/
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
|
||||
rtw_udelay_os(1);//PlatformStallExecution(1);
|
||||
rtw_udelay_os(1);/* PlatformStallExecution(1); */
|
||||
|
||||
/*----Set RF_ENV output high----*/
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
|
||||
rtw_udelay_os(1);//PlatformStallExecution(1);
|
||||
rtw_udelay_os(1);/* PlatformStallExecution(1); */
|
||||
|
||||
/* Set bit number of Address and Data for RF register */
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255
|
||||
rtw_udelay_os(1);//PlatformStallExecution(1);
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */
|
||||
rtw_udelay_os(1);/* PlatformStallExecution(1); */
|
||||
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255
|
||||
rtw_udelay_os(1);//PlatformStallExecution(1);
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */
|
||||
rtw_udelay_os(1);/* PlatformStallExecution(1); */
|
||||
|
||||
/*----Initialize RF fom connfiguration file----*/
|
||||
switch (eRFPath)
|
||||
{
|
||||
switch (eRFPath) {
|
||||
case RF_PATH_A:
|
||||
#ifdef CONFIG_EMBEDDED_FWIMG
|
||||
#ifdef CONFIG_PHY_SETTING_WITH_ODM
|
||||
|
|
@ -704,10 +630,10 @@ phy_RF6052_Config_ParaFile(
|
|||
rtStatus= _FAIL;
|
||||
#else
|
||||
rtStatus= rtl8188e_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath);
|
||||
#endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM
|
||||
#endif/* ifdef CONFIG_PHY_SETTING_WITH_ODM */
|
||||
#else
|
||||
rtStatus = rtl8188e_PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF_RADIO_PATH_E)eRFPath);
|
||||
#endif//#ifdef CONFIG_EMBEDDED_FWIMG
|
||||
#endif/* ifdef CONFIG_EMBEDDED_FWIMG */
|
||||
break;
|
||||
case RF_PATH_B:
|
||||
#ifdef CONFIG_EMBEDDED_FWIMG
|
||||
|
|
@ -716,7 +642,7 @@ phy_RF6052_Config_ParaFile(
|
|||
rtStatus= _FAIL;
|
||||
#else
|
||||
rtStatus = rtl8188e_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath);
|
||||
#endif //#ifdef CONFIG_PHY_SETTING_WITH_ODM
|
||||
#endif /* ifdef CONFIG_PHY_SETTING_WITH_ODM */
|
||||
#else
|
||||
rtStatus =rtl8188e_PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF_RADIO_PATH_E)eRFPath);
|
||||
#endif
|
||||
|
|
@ -740,14 +666,11 @@ phy_RF6052_Config_ParaFile(
|
|||
break;
|
||||
}
|
||||
|
||||
if (rtStatus != _SUCCESS){
|
||||
//RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath));
|
||||
if (rtStatus != _SUCCESS)
|
||||
goto phy_RF6052_Config_ParaFile_Fail;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
//RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n"));
|
||||
return rtStatus;
|
||||
|
||||
phy_RF6052_Config_ParaFile_Fail:
|
||||
|
|
@ -762,18 +685,18 @@ PHY_RF6052_Config8188E(
|
|||
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
||||
int rtStatus = _SUCCESS;
|
||||
|
||||
//
|
||||
// Initialize general global value
|
||||
//
|
||||
// TODO: Extend RF_PATH_C and RF_PATH_D in the future
|
||||
/* */
|
||||
/* Initialize general global value */
|
||||
/* */
|
||||
/* TODO: Extend RF_PATH_C and RF_PATH_D in the future */
|
||||
if (pHalData->rf_type == RF_1T1R)
|
||||
pHalData->NumTotalRFPath = 1;
|
||||
else
|
||||
pHalData->NumTotalRFPath = 2;
|
||||
|
||||
//
|
||||
// Config BB and RF
|
||||
//
|
||||
/* */
|
||||
/* Config BB and RF */
|
||||
/* */
|
||||
rtStatus = phy_RF6052_Config_ParaFile(Adapter);
|
||||
return rtStatus;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue